1 //
2 // Copyright (c) 1998, 2012, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Must be visible to the DFA in dfa_sparc.cpp
461 extern bool can_branch_register( Node *bol, Node *cmp );
462
463 extern bool use_block_zeroing(Node* count);
464
465 // Macros to extract hi & lo halves from a long pair.
466 // G0 is not part of any long pair, so assert on that.
467 // Prevents accidentally using G1 instead of G0.
468 #define LONG_HI_REG(x) (x)
469 #define LONG_LO_REG(x) (x)
470
471 %}
472
473 source %{
474 #define __ _masm.
475
476 // tertiary op of a LoadP or StoreP encoding
477 #define REGP_OP true
478
479 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
480 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
481 static Register reg_to_register_object(int register_encoding);
482
483 // Used by the DFA in dfa_sparc.cpp.
484 // Check for being able to use a V9 branch-on-register. Requires a
485 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
486 // extended. Doesn't work following an integer ADD, for example, because of
487 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
488 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
489 // replace them with zero, which could become sign-extension in a different OS
490 // release. There's no obvious reason why an interrupt will ever fill these
491 // bits with non-zero junk (the registers are reloaded with standard LD
492 // instructions which either zero-fill or sign-fill).
493 bool can_branch_register( Node *bol, Node *cmp ) {
494 if( !BranchOnRegister ) return false;
495 #ifdef _LP64
496 if( cmp->Opcode() == Op_CmpP )
497 return true; // No problems with pointer compares
498 #endif
499 if( cmp->Opcode() == Op_CmpL )
500 return true; // No problems with long compares
501
502 if( !SparcV9RegsHiBitsZero ) return false;
503 if( bol->as_Bool()->_test._test != BoolTest::ne &&
504 bol->as_Bool()->_test._test != BoolTest::eq )
505 return false;
506
507 // Check for comparing against a 'safe' value. Any operation which
508 // clears out the high word is safe. Thus, loads and certain shifts
509 // are safe, as are non-negative constants. Any operation which
510 // preserves zero bits in the high word is safe as long as each of its
511 // inputs are safe. Thus, phis and bitwise booleans are safe if their
512 // inputs are safe. At present, the only important case to recognize
513 // seems to be loads. Constants should fold away, and shifts &
514 // logicals can use the 'cc' forms.
515 Node *x = cmp->in(1);
516 if( x->is_Load() ) return true;
517 if( x->is_Phi() ) {
518 for( uint i = 1; i < x->req(); i++ )
519 if( !x->in(i)->is_Load() )
520 return false;
521 return true;
522 }
523 return false;
524 }
525
526 bool use_block_zeroing(Node* count) {
527 // Use BIS for zeroing if count is not constant
528 // or it is >= BlockZeroingLowLimit.
529 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
530 }
531
532 // ****************************************************************************
533
534 // REQUIRED FUNCTIONALITY
535
536 // !!!!! Special hack to get all type of calls to specify the byte offset
537 // from the start of the call to the point where the return address
538 // will point.
539 // The "return address" is the address of the call instruction, plus 8.
540
541 int MachCallStaticJavaNode::ret_addr_offset() {
542 int offset = NativeCall::instruction_size; // call; delay slot
543 if (_method_handle_invoke)
544 offset += 4; // restore SP
545 return offset;
546 }
547
548 int MachCallDynamicJavaNode::ret_addr_offset() {
549 int vtable_index = this->_vtable_index;
550 if (vtable_index < 0) {
551 // must be invalid_vtable_index, not nonvirtual_vtable_index
552 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
553 return (NativeMovConstReg::instruction_size +
554 NativeCall::instruction_size); // sethi; setlo; call; delay slot
555 } else {
556 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
557 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
558 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
559 int klass_load_size;
560 if (UseCompressedKlassPointers) {
561 assert(Universe::heap() != NULL, "java heap should be initialized");
562 if (Universe::narrow_klass_base() == NULL)
563 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
564 else
565 klass_load_size = 3*BytesPerInstWord;
566 } else {
567 klass_load_size = 1*BytesPerInstWord;
568 }
569 if (Assembler::is_simm13(v_off)) {
570 return klass_load_size +
571 (2*BytesPerInstWord + // ld_ptr, ld_ptr
572 NativeCall::instruction_size); // call; delay slot
573 } else {
574 return klass_load_size +
575 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
576 NativeCall::instruction_size); // call; delay slot
577 }
578 }
579 }
580
581 int MachCallRuntimeNode::ret_addr_offset() {
582 #ifdef _LP64
583 if (MacroAssembler::is_far_target(entry_point())) {
584 return NativeFarCall::instruction_size;
585 } else {
586 return NativeCall::instruction_size;
587 }
588 #else
589 return NativeCall::instruction_size; // call; delay slot
590 #endif
591 }
592
593 // Indicate if the safepoint node needs the polling page as an input.
594 // Since Sparc does not have absolute addressing, it does.
595 bool SafePointNode::needs_polling_address_input() {
596 return true;
597 }
598
599 // emit an interrupt that is caught by the debugger (for debugging compiler)
600 void emit_break(CodeBuffer &cbuf) {
601 MacroAssembler _masm(&cbuf);
602 __ breakpoint_trap();
603 }
604
605 #ifndef PRODUCT
606 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
607 st->print("TA");
608 }
609 #endif
610
611 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
612 emit_break(cbuf);
613 }
614
615 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
616 return MachNode::size(ra_);
617 }
618
619 // Traceable jump
620 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
621 MacroAssembler _masm(&cbuf);
622 Register rdest = reg_to_register_object(jump_target);
623 __ JMP(rdest, 0);
624 __ delayed()->nop();
625 }
626
627 // Traceable jump and set exception pc
628 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
629 MacroAssembler _masm(&cbuf);
630 Register rdest = reg_to_register_object(jump_target);
631 __ JMP(rdest, 0);
632 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
633 }
634
635 void emit_nop(CodeBuffer &cbuf) {
636 MacroAssembler _masm(&cbuf);
637 __ nop();
638 }
639
640 void emit_illtrap(CodeBuffer &cbuf) {
641 MacroAssembler _masm(&cbuf);
642 __ illtrap(0);
643 }
644
645
646 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
647 assert(n->rule() != loadUB_rule, "");
648
649 intptr_t offset = 0;
650 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
651 const Node* addr = n->get_base_and_disp(offset, adr_type);
652 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
653 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
654 assert(addr->bottom_type()->isa_oopptr() == atype, "");
655 atype = atype->add_offset(offset);
656 assert(disp32 == offset, "wrong disp32");
657 return atype->_offset;
658 }
659
660
661 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
662 assert(n->rule() != loadUB_rule, "");
663
664 intptr_t offset = 0;
665 Node* addr = n->in(2);
666 assert(addr->bottom_type()->isa_oopptr() == atype, "");
667 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
668 Node* a = addr->in(2/*AddPNode::Address*/);
669 Node* o = addr->in(3/*AddPNode::Offset*/);
670 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
671 atype = a->bottom_type()->is_ptr()->add_offset(offset);
672 assert(atype->isa_oop_ptr(), "still an oop");
673 }
674 offset = atype->is_ptr()->_offset;
675 if (offset != Type::OffsetBot) offset += disp32;
676 return offset;
677 }
678
679 static inline jdouble replicate_immI(int con, int count, int width) {
680 // Load a constant replicated "count" times with width "width"
681 assert(count*width == 8 && width <= 4, "sanity");
682 int bit_width = width * 8;
683 jlong val = con;
684 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
685 for (int i = 0; i < count - 1; i++) {
686 val |= (val << bit_width);
687 }
688 jdouble dval = *((jdouble*) &val); // coerce to double type
689 return dval;
690 }
691
692 static inline jdouble replicate_immF(float con) {
693 // Replicate float con 2 times and pack into vector.
694 int val = *((int*)&con);
695 jlong lval = val;
696 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
697 jdouble dval = *((jdouble*) &lval); // coerce to double type
698 return dval;
699 }
700
701 // Standard Sparc opcode form2 field breakdown
702 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
703 f0 &= (1<<19)-1; // Mask displacement to 19 bits
704 int op = (f30 << 30) |
705 (f29 << 29) |
706 (f25 << 25) |
707 (f22 << 22) |
708 (f20 << 20) |
709 (f19 << 19) |
710 (f0 << 0);
711 cbuf.insts()->emit_int32(op);
712 }
713
714 // Standard Sparc opcode form2 field breakdown
715 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
716 f0 >>= 10; // Drop 10 bits
717 f0 &= (1<<22)-1; // Mask displacement to 22 bits
718 int op = (f30 << 30) |
719 (f25 << 25) |
720 (f22 << 22) |
721 (f0 << 0);
722 cbuf.insts()->emit_int32(op);
723 }
724
725 // Standard Sparc opcode form3 field breakdown
726 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
727 int op = (f30 << 30) |
728 (f25 << 25) |
729 (f19 << 19) |
730 (f14 << 14) |
731 (f5 << 5) |
732 (f0 << 0);
733 cbuf.insts()->emit_int32(op);
734 }
735
736 // Standard Sparc opcode form3 field breakdown
737 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
738 simm13 &= (1<<13)-1; // Mask to 13 bits
739 int op = (f30 << 30) |
740 (f25 << 25) |
741 (f19 << 19) |
742 (f14 << 14) |
743 (1 << 13) | // bit to indicate immediate-mode
744 (simm13<<0);
745 cbuf.insts()->emit_int32(op);
746 }
747
748 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
749 simm10 &= (1<<10)-1; // Mask to 10 bits
750 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
751 }
752
753 #ifdef ASSERT
754 // Helper function for VerifyOops in emit_form3_mem_reg
755 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
756 warning("VerifyOops encountered unexpected instruction:");
757 n->dump(2);
758 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
759 }
760 #endif
761
762
763 void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
764 int src1_enc, int disp32, int src2_enc, int dst_enc) {
765
766 #ifdef ASSERT
767 // The following code implements the +VerifyOops feature.
768 // It verifies oop values which are loaded into or stored out of
769 // the current method activation. +VerifyOops complements techniques
770 // like ScavengeALot, because it eagerly inspects oops in transit,
771 // as they enter or leave the stack, as opposed to ScavengeALot,
772 // which inspects oops "at rest", in the stack or heap, at safepoints.
773 // For this reason, +VerifyOops can sometimes detect bugs very close
774 // to their point of creation. It can also serve as a cross-check
775 // on the validity of oop maps, when used toegether with ScavengeALot.
776
777 // It would be good to verify oops at other points, especially
778 // when an oop is used as a base pointer for a load or store.
779 // This is presently difficult, because it is hard to know when
780 // a base address is biased or not. (If we had such information,
781 // it would be easy and useful to make a two-argument version of
782 // verify_oop which unbiases the base, and performs verification.)
783
784 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
785 bool is_verified_oop_base = false;
786 bool is_verified_oop_load = false;
787 bool is_verified_oop_store = false;
788 int tmp_enc = -1;
789 if (VerifyOops && src1_enc != R_SP_enc) {
790 // classify the op, mainly for an assert check
791 int st_op = 0, ld_op = 0;
792 switch (primary) {
793 case Assembler::stb_op3: st_op = Op_StoreB; break;
794 case Assembler::sth_op3: st_op = Op_StoreC; break;
795 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
796 case Assembler::stw_op3: st_op = Op_StoreI; break;
797 case Assembler::std_op3: st_op = Op_StoreL; break;
798 case Assembler::stf_op3: st_op = Op_StoreF; break;
799 case Assembler::stdf_op3: st_op = Op_StoreD; break;
800
801 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
802 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
803 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
804 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
805 case Assembler::ldx_op3: // may become LoadP or stay LoadI
806 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
807 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
808 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
809 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
810 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
811 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
812
813 default: ShouldNotReachHere();
814 }
815 if (tertiary == REGP_OP) {
816 if (st_op == Op_StoreI) st_op = Op_StoreP;
817 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
818 else ShouldNotReachHere();
819 if (st_op) {
820 // a store
821 // inputs are (0:control, 1:memory, 2:address, 3:value)
822 Node* n2 = n->in(3);
823 if (n2 != NULL) {
824 const Type* t = n2->bottom_type();
825 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
826 }
827 } else {
828 // a load
829 const Type* t = n->bottom_type();
830 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
831 }
832 }
833
834 if (ld_op) {
835 // a Load
836 // inputs are (0:control, 1:memory, 2:address)
837 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
838 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
839 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
840 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
841 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
842 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
843 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
844 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
845 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
846 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
847 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
848 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) &&
849 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
850 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
851 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
852 !(n->rule() == loadUB_rule)) {
853 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
854 }
855 } else if (st_op) {
856 // a Store
857 // inputs are (0:control, 1:memory, 2:address, 3:value)
858 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
859 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
860 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
861 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
862 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
863 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
864 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
865 verify_oops_warning(n, n->ideal_Opcode(), st_op);
866 }
867 }
868
869 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
870 Node* addr = n->in(2);
871 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
872 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
873 if (atype != NULL) {
874 intptr_t offset = get_offset_from_base(n, atype, disp32);
875 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
876 if (offset != offset_2) {
877 get_offset_from_base(n, atype, disp32);
878 get_offset_from_base_2(n, atype, disp32);
879 }
880 assert(offset == offset_2, "different offsets");
881 if (offset == disp32) {
882 // we now know that src1 is a true oop pointer
883 is_verified_oop_base = true;
884 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
885 if( primary == Assembler::ldd_op3 ) {
886 is_verified_oop_base = false; // Cannot 'ldd' into O7
887 } else {
888 tmp_enc = dst_enc;
889 dst_enc = R_O7_enc; // Load into O7; preserve source oop
890 assert(src1_enc != dst_enc, "");
891 }
892 }
893 }
894 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
895 || offset == oopDesc::mark_offset_in_bytes())) {
896 // loading the mark should not be allowed either, but
897 // we don't check this since it conflicts with InlineObjectHash
898 // usage of LoadINode to get the mark. We could keep the
899 // check if we create a new LoadMarkNode
900 // but do not verify the object before its header is initialized
901 ShouldNotReachHere();
902 }
903 }
904 }
905 }
906 }
907 #endif
908
909 uint instr;
910 instr = (Assembler::ldst_op << 30)
911 | (dst_enc << 25)
912 | (primary << 19)
913 | (src1_enc << 14);
914
915 uint index = src2_enc;
916 int disp = disp32;
917
918 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
919 disp += STACK_BIAS;
920
921 // We should have a compiler bailout here rather than a guarantee.
922 // Better yet would be some mechanism to handle variable-size matches correctly.
923 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
924
925 if( disp == 0 ) {
926 // use reg-reg form
927 // bit 13 is already zero
928 instr |= index;
929 } else {
930 // use reg-imm form
931 instr |= 0x00002000; // set bit 13 to one
932 instr |= disp & 0x1FFF;
933 }
934
935 cbuf.insts()->emit_int32(instr);
936
937 #ifdef ASSERT
938 {
939 MacroAssembler _masm(&cbuf);
940 if (is_verified_oop_base) {
941 __ verify_oop(reg_to_register_object(src1_enc));
942 }
943 if (is_verified_oop_store) {
944 __ verify_oop(reg_to_register_object(dst_enc));
945 }
946 if (tmp_enc != -1) {
947 __ mov(O7, reg_to_register_object(tmp_enc));
948 }
949 if (is_verified_oop_load) {
950 __ verify_oop(reg_to_register_object(dst_enc));
951 }
952 }
953 #endif
954 }
955
956 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
957 // The method which records debug information at every safepoint
958 // expects the call to be the first instruction in the snippet as
959 // it creates a PcDesc structure which tracks the offset of a call
960 // from the start of the codeBlob. This offset is computed as
961 // code_end() - code_begin() of the code which has been emitted
962 // so far.
963 // In this particular case we have skirted around the problem by
964 // putting the "mov" instruction in the delay slot but the problem
965 // may bite us again at some other point and a cleaner/generic
966 // solution using relocations would be needed.
967 MacroAssembler _masm(&cbuf);
968 __ set_inst_mark();
969
970 // We flush the current window just so that there is a valid stack copy
971 // the fact that the current window becomes active again instantly is
972 // not a problem there is nothing live in it.
973
974 #ifdef ASSERT
975 int startpos = __ offset();
976 #endif /* ASSERT */
977
978 __ call((address)entry_point, rtype);
979
980 if (preserve_g2) __ delayed()->mov(G2, L7);
981 else __ delayed()->nop();
982
983 if (preserve_g2) __ mov(L7, G2);
984
985 #ifdef ASSERT
986 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
987 #ifdef _LP64
988 // Trash argument dump slots.
989 __ set(0xb0b8ac0db0b8ac0d, G1);
990 __ mov(G1, G5);
991 __ stx(G1, SP, STACK_BIAS + 0x80);
992 __ stx(G1, SP, STACK_BIAS + 0x88);
993 __ stx(G1, SP, STACK_BIAS + 0x90);
994 __ stx(G1, SP, STACK_BIAS + 0x98);
995 __ stx(G1, SP, STACK_BIAS + 0xA0);
996 __ stx(G1, SP, STACK_BIAS + 0xA8);
997 #else // _LP64
998 // this is also a native call, so smash the first 7 stack locations,
999 // and the various registers
1000
1001 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1002 // while [SP+0x44..0x58] are the argument dump slots.
1003 __ set((intptr_t)0xbaadf00d, G1);
1004 __ mov(G1, G5);
1005 __ sllx(G1, 32, G1);
1006 __ or3(G1, G5, G1);
1007 __ mov(G1, G5);
1008 __ stx(G1, SP, 0x40);
1009 __ stx(G1, SP, 0x48);
1010 __ stx(G1, SP, 0x50);
1011 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1012 #endif // _LP64
1013 }
1014 #endif /*ASSERT*/
1015 }
1016
1017 //=============================================================================
1018 // REQUIRED FUNCTIONALITY for encoding
1019 void emit_lo(CodeBuffer &cbuf, int val) { }
1020 void emit_hi(CodeBuffer &cbuf, int val) { }
1021
1022
1023 //=============================================================================
1024 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1025
1026 int Compile::ConstantTable::calculate_table_base_offset() const {
1027 if (UseRDPCForConstantTableBase) {
1028 // The table base offset might be less but then it fits into
1029 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1030 return Assembler::min_simm13();
1031 } else {
1032 int offset = -(size() / 2);
1033 if (!Assembler::is_simm13(offset)) {
1034 offset = Assembler::min_simm13();
1035 }
1036 return offset;
1037 }
1038 }
1039
1040 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1041 Compile* C = ra_->C;
1042 Compile::ConstantTable& constant_table = C->constant_table();
1043 MacroAssembler _masm(&cbuf);
1044
1045 Register r = as_Register(ra_->get_encode(this));
1046 CodeSection* consts_section = __ code()->consts();
1047 int consts_size = consts_section->align_at_start(consts_section->size());
1048 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1049
1050 if (UseRDPCForConstantTableBase) {
1051 // For the following RDPC logic to work correctly the consts
1052 // section must be allocated right before the insts section. This
1053 // assert checks for that. The layout and the SECT_* constants
1054 // are defined in src/share/vm/asm/codeBuffer.hpp.
1055 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1056 int insts_offset = __ offset();
1057
1058 // Layout:
1059 //
1060 // |----------- consts section ------------|----------- insts section -----------...
1061 // |------ constant table -----|- padding -|------------------x----
1062 // \ current PC (RDPC instruction)
1063 // |<------------- consts_size ----------->|<- insts_offset ->|
1064 // \ table base
1065 // The table base offset is later added to the load displacement
1066 // so it has to be negative.
1067 int table_base_offset = -(consts_size + insts_offset);
1068 int disp;
1069
1070 // If the displacement from the current PC to the constant table
1071 // base fits into simm13 we set the constant table base to the
1072 // current PC.
1073 if (Assembler::is_simm13(table_base_offset)) {
1074 constant_table.set_table_base_offset(table_base_offset);
1075 disp = 0;
1076 } else {
1077 // Otherwise we set the constant table base offset to the
1078 // maximum negative displacement of load instructions to keep
1079 // the disp as small as possible:
1080 //
1081 // |<------------- consts_size ----------->|<- insts_offset ->|
1082 // |<--------- min_simm13 --------->|<-------- disp --------->|
1083 // \ table base
1084 table_base_offset = Assembler::min_simm13();
1085 constant_table.set_table_base_offset(table_base_offset);
1086 disp = (consts_size + insts_offset) + table_base_offset;
1087 }
1088
1089 __ rdpc(r);
1090
1091 if (disp != 0) {
1092 assert(r != O7, "need temporary");
1093 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1094 }
1095 }
1096 else {
1097 // Materialize the constant table base.
1098 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1099 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1100 AddressLiteral base(baseaddr, rspec);
1101 __ set(base, r);
1102 }
1103 }
1104
1105 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1106 if (UseRDPCForConstantTableBase) {
1107 // This is really the worst case but generally it's only 1 instruction.
1108 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1109 } else {
1110 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1111 }
1112 }
1113
1114 #ifndef PRODUCT
1115 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1116 char reg[128];
1117 ra_->dump_register(this, reg);
1118 if (UseRDPCForConstantTableBase) {
1119 st->print("RDPC %s\t! constant table base", reg);
1120 } else {
1121 st->print("SET &constanttable,%s\t! constant table base", reg);
1122 }
1123 }
1124 #endif
1125
1126
1127 //=============================================================================
1128
1129 #ifndef PRODUCT
1130 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1131 Compile* C = ra_->C;
1132
1133 for (int i = 0; i < OptoPrologueNops; i++) {
1134 st->print_cr("NOP"); st->print("\t");
1135 }
1136
1137 if( VerifyThread ) {
1138 st->print_cr("Verify_Thread"); st->print("\t");
1139 }
1140
1141 size_t framesize = C->frame_slots() << LogBytesPerInt;
1142
1143 // Calls to C2R adapters often do not accept exceptional returns.
1144 // We require that their callers must bang for them. But be careful, because
1145 // some VM calls (such as call site linkage) can use several kilobytes of
1146 // stack. But the stack safety zone should account for that.
1147 // See bugs 4446381, 4468289, 4497237.
1148 if (C->need_stack_bang(framesize)) {
1149 st->print_cr("! stack bang"); st->print("\t");
1150 }
1151
1152 if (Assembler::is_simm13(-framesize)) {
1153 st->print ("SAVE R_SP,-%d,R_SP",framesize);
1154 } else {
1155 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
1156 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
1157 st->print ("SAVE R_SP,R_G3,R_SP");
1158 }
1159
1160 }
1161 #endif
1162
1163 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1164 Compile* C = ra_->C;
1165 MacroAssembler _masm(&cbuf);
1166
1167 for (int i = 0; i < OptoPrologueNops; i++) {
1168 __ nop();
1169 }
1170
1171 __ verify_thread();
1172
1173 size_t framesize = C->frame_slots() << LogBytesPerInt;
1174 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1175 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1176
1177 // Calls to C2R adapters often do not accept exceptional returns.
1178 // We require that their callers must bang for them. But be careful, because
1179 // some VM calls (such as call site linkage) can use several kilobytes of
1180 // stack. But the stack safety zone should account for that.
1181 // See bugs 4446381, 4468289, 4497237.
1182 if (C->need_stack_bang(framesize)) {
1183 __ generate_stack_overflow_check(framesize);
1184 }
1185
1186 if (Assembler::is_simm13(-framesize)) {
1187 __ save(SP, -framesize, SP);
1188 } else {
1189 __ sethi(-framesize & ~0x3ff, G3);
1190 __ add(G3, -framesize & 0x3ff, G3);
1191 __ save(SP, G3, SP);
1192 }
1193 C->set_frame_complete( __ offset() );
1194
1195 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1196 // NOTE: We set the table base offset here because users might be
1197 // emitted before MachConstantBaseNode.
1198 Compile::ConstantTable& constant_table = C->constant_table();
1199 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1200 }
1201 }
1202
1203 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1204 return MachNode::size(ra_);
1205 }
1206
1207 int MachPrologNode::reloc() const {
1208 return 10; // a large enough number
1209 }
1210
1211 //=============================================================================
1212 #ifndef PRODUCT
1213 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1214 Compile* C = ra_->C;
1215
1216 if( do_polling() && ra_->C->is_method_compilation() ) {
1217 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1218 #ifdef _LP64
1219 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1220 #else
1221 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1222 #endif
1223 }
1224
1225 if( do_polling() )
1226 st->print("RET\n\t");
1227
1228 st->print("RESTORE");
1229 }
1230 #endif
1231
1232 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1233 MacroAssembler _masm(&cbuf);
1234 Compile* C = ra_->C;
1235
1236 __ verify_thread();
1237
1238 // If this does safepoint polling, then do it here
1239 if( do_polling() && ra_->C->is_method_compilation() ) {
1240 AddressLiteral polling_page(os::get_polling_page());
1241 __ sethi(polling_page, L0);
1242 __ relocate(relocInfo::poll_return_type);
1243 __ ld_ptr( L0, 0, G0 );
1244 }
1245
1246 // If this is a return, then stuff the restore in the delay slot
1247 if( do_polling() ) {
1248 __ ret();
1249 __ delayed()->restore();
1250 } else {
1251 __ restore();
1252 }
1253 }
1254
1255 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1256 return MachNode::size(ra_);
1257 }
1258
1259 int MachEpilogNode::reloc() const {
1260 return 16; // a large enough number
1261 }
1262
1263 const Pipeline * MachEpilogNode::pipeline() const {
1264 return MachNode::pipeline_class();
1265 }
1266
1267 int MachEpilogNode::safepoint_offset() const {
1268 assert( do_polling(), "no return for this epilog node");
1269 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1270 }
1271
1272 //=============================================================================
1273
1274 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1275 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1276 static enum RC rc_class( OptoReg::Name reg ) {
1277 if( !OptoReg::is_valid(reg) ) return rc_bad;
1278 if (OptoReg::is_stack(reg)) return rc_stack;
1279 VMReg r = OptoReg::as_VMReg(reg);
1280 if (r->is_Register()) return rc_int;
1281 assert(r->is_FloatRegister(), "must be");
1282 return rc_float;
1283 }
1284
1285 static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1286 if( cbuf ) {
1287 // Better yet would be some mechanism to handle variable-size matches correctly
1288 if (!Assembler::is_simm13(offset + STACK_BIAS)) {
1289 ra_->C->record_method_not_compilable("unable to handle large constant offsets");
1290 } else {
1291 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1292 }
1293 }
1294 #ifndef PRODUCT
1295 else if( !do_size ) {
1296 if( size != 0 ) st->print("\n\t");
1297 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1298 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1299 }
1300 #endif
1301 return size+4;
1302 }
1303
1304 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1305 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1306 #ifndef PRODUCT
1307 else if( !do_size ) {
1308 if( size != 0 ) st->print("\n\t");
1309 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1310 }
1311 #endif
1312 return size+4;
1313 }
1314
1315 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1316 PhaseRegAlloc *ra_,
1317 bool do_size,
1318 outputStream* st ) const {
1319 // Get registers to move
1320 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1321 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1322 OptoReg::Name dst_second = ra_->get_reg_second(this );
1323 OptoReg::Name dst_first = ra_->get_reg_first(this );
1324
1325 enum RC src_second_rc = rc_class(src_second);
1326 enum RC src_first_rc = rc_class(src_first);
1327 enum RC dst_second_rc = rc_class(dst_second);
1328 enum RC dst_first_rc = rc_class(dst_first);
1329
1330 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1331
1332 // Generate spill code!
1333 int size = 0;
1334
1335 if( src_first == dst_first && src_second == dst_second )
1336 return size; // Self copy, no move
1337
1338 // --------------------------------------
1339 // Check for mem-mem move. Load into unused float registers and fall into
1340 // the float-store case.
1341 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1342 int offset = ra_->reg2offset(src_first);
1343 // Further check for aligned-adjacent pair, so we can use a double load
1344 if( (src_first&1)==0 && src_first+1 == src_second ) {
1345 src_second = OptoReg::Name(R_F31_num);
1346 src_second_rc = rc_float;
1347 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1348 } else {
1349 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1350 }
1351 src_first = OptoReg::Name(R_F30_num);
1352 src_first_rc = rc_float;
1353 }
1354
1355 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1356 int offset = ra_->reg2offset(src_second);
1357 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1358 src_second = OptoReg::Name(R_F31_num);
1359 src_second_rc = rc_float;
1360 }
1361
1362 // --------------------------------------
1363 // Check for float->int copy; requires a trip through memory
1364 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1365 int offset = frame::register_save_words*wordSize;
1366 if (cbuf) {
1367 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1368 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1369 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1370 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1371 }
1372 #ifndef PRODUCT
1373 else if (!do_size) {
1374 if (size != 0) st->print("\n\t");
1375 st->print( "SUB R_SP,16,R_SP\n");
1376 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1377 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1378 st->print("\tADD R_SP,16,R_SP\n");
1379 }
1380 #endif
1381 size += 16;
1382 }
1383
1384 // Check for float->int copy on T4
1385 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1386 // Further check for aligned-adjacent pair, so we can use a double move
1387 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1388 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1389 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1390 }
1391 // Check for int->float copy on T4
1392 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1393 // Further check for aligned-adjacent pair, so we can use a double move
1394 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1395 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1396 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1397 }
1398
1399 // --------------------------------------
1400 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1401 // In such cases, I have to do the big-endian swap. For aligned targets, the
1402 // hardware does the flop for me. Doubles are always aligned, so no problem
1403 // there. Misaligned sources only come from native-long-returns (handled
1404 // special below).
1405 #ifndef _LP64
1406 if( src_first_rc == rc_int && // source is already big-endian
1407 src_second_rc != rc_bad && // 64-bit move
1408 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1409 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1410 // Do the big-endian flop.
1411 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1412 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1413 }
1414 #endif
1415
1416 // --------------------------------------
1417 // Check for integer reg-reg copy
1418 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1419 #ifndef _LP64
1420 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1421 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1422 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1423 // operand contains the least significant word of the 64-bit value and vice versa.
1424 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1425 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1426 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1427 if( cbuf ) {
1428 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1429 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1430 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1431 #ifndef PRODUCT
1432 } else if( !do_size ) {
1433 if( size != 0 ) st->print("\n\t");
1434 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1435 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1436 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1437 #endif
1438 }
1439 return size+12;
1440 }
1441 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1442 // returning a long value in I0/I1
1443 // a SpillCopy must be able to target a return instruction's reg_class
1444 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1445 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1446 // operand contains the least significant word of the 64-bit value and vice versa.
1447 OptoReg::Name tdest = dst_first;
1448
1449 if (src_first == dst_first) {
1450 tdest = OptoReg::Name(R_O7_num);
1451 size += 4;
1452 }
1453
1454 if( cbuf ) {
1455 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1456 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1457 // ShrL_reg_imm6
1458 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1459 // ShrR_reg_imm6 src, 0, dst
1460 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1461 if (tdest != dst_first) {
1462 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1463 }
1464 }
1465 #ifndef PRODUCT
1466 else if( !do_size ) {
1467 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1468 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1469 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1470 if (tdest != dst_first) {
1471 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1472 }
1473 }
1474 #endif // PRODUCT
1475 return size+8;
1476 }
1477 #endif // !_LP64
1478 // Else normal reg-reg copy
1479 assert( src_second != dst_first, "smashed second before evacuating it" );
1480 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1481 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1482 // This moves an aligned adjacent pair.
1483 // See if we are done.
1484 if( src_first+1 == src_second && dst_first+1 == dst_second )
1485 return size;
1486 }
1487
1488 // Check for integer store
1489 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1490 int offset = ra_->reg2offset(dst_first);
1491 // Further check for aligned-adjacent pair, so we can use a double store
1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1493 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1494 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1495 }
1496
1497 // Check for integer load
1498 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1499 int offset = ra_->reg2offset(src_first);
1500 // Further check for aligned-adjacent pair, so we can use a double load
1501 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1502 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1503 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1504 }
1505
1506 // Check for float reg-reg copy
1507 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1508 // Further check for aligned-adjacent pair, so we can use a double move
1509 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1510 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1511 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1512 }
1513
1514 // Check for float store
1515 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1516 int offset = ra_->reg2offset(dst_first);
1517 // Further check for aligned-adjacent pair, so we can use a double store
1518 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1519 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1520 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1521 }
1522
1523 // Check for float load
1524 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1525 int offset = ra_->reg2offset(src_first);
1526 // Further check for aligned-adjacent pair, so we can use a double load
1527 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1528 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1529 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1530 }
1531
1532 // --------------------------------------------------------------------
1533 // Check for hi bits still needing moving. Only happens for misaligned
1534 // arguments to native calls.
1535 if( src_second == dst_second )
1536 return size; // Self copy; no move
1537 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1538
1539 #ifndef _LP64
1540 // In the LP64 build, all registers can be moved as aligned/adjacent
1541 // pairs, so there's never any need to move the high bits separately.
1542 // The 32-bit builds have to deal with the 32-bit ABI which can force
1543 // all sorts of silly alignment problems.
1544
1545 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1546 // 32-bits of a 64-bit register, but are needed in low bits of another
1547 // register (else it's a hi-bits-to-hi-bits copy which should have
1548 // happened already as part of a 64-bit move)
1549 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1550 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1551 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1552 // Shift src_second down to dst_second's low bits.
1553 if( cbuf ) {
1554 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1555 #ifndef PRODUCT
1556 } else if( !do_size ) {
1557 if( size != 0 ) st->print("\n\t");
1558 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1559 #endif
1560 }
1561 return size+4;
1562 }
1563
1564 // Check for high word integer store. Must down-shift the hi bits
1565 // into a temp register, then fall into the case of storing int bits.
1566 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1567 // Shift src_second down to dst_second's low bits.
1568 if( cbuf ) {
1569 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1570 #ifndef PRODUCT
1571 } else if( !do_size ) {
1572 if( size != 0 ) st->print("\n\t");
1573 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1574 #endif
1575 }
1576 size+=4;
1577 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1578 }
1579
1580 // Check for high word integer load
1581 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1582 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1583
1584 // Check for high word integer store
1585 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1586 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1587
1588 // Check for high word float store
1589 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1590 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1591
1592 #endif // !_LP64
1593
1594 Unimplemented();
1595 }
1596
1597 #ifndef PRODUCT
1598 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1599 implementation( NULL, ra_, false, st );
1600 }
1601 #endif
1602
1603 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1604 implementation( &cbuf, ra_, false, NULL );
1605 }
1606
1607 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1608 return implementation( NULL, ra_, true, NULL );
1609 }
1610
1611 //=============================================================================
1612 #ifndef PRODUCT
1613 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1614 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1615 }
1616 #endif
1617
1618 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1619 MacroAssembler _masm(&cbuf);
1620 for(int i = 0; i < _count; i += 1) {
1621 __ nop();
1622 }
1623 }
1624
1625 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1626 return 4 * _count;
1627 }
1628
1629
1630 //=============================================================================
1631 #ifndef PRODUCT
1632 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1633 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1634 int reg = ra_->get_reg_first(this);
1635 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1636 }
1637 #endif
1638
1639 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1640 MacroAssembler _masm(&cbuf);
1641 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1642 int reg = ra_->get_encode(this);
1643
1644 if (Assembler::is_simm13(offset)) {
1645 __ add(SP, offset, reg_to_register_object(reg));
1646 } else {
1647 __ set(offset, O7);
1648 __ add(SP, O7, reg_to_register_object(reg));
1649 }
1650 }
1651
1652 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1653 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1654 assert(ra_ == ra_->C->regalloc(), "sanity");
1655 return ra_->C->scratch_emit_size(this);
1656 }
1657
1658 //=============================================================================
1659
1660 // emit call stub, compiled java to interpretor
1661 void emit_java_to_interp(CodeBuffer &cbuf ) {
1662
1663 // Stub is fixed up when the corresponding call is converted from calling
1664 // compiled code to calling interpreted code.
1665 // set (empty), G5
1666 // jmp -1
1667
1668 address mark = cbuf.insts_mark(); // get mark within main instrs section
1669
1670 MacroAssembler _masm(&cbuf);
1671
1672 address base =
1673 __ start_a_stub(Compile::MAX_stubs_size);
1674 if (base == NULL) return; // CodeBuffer::expand failed
1675
1676 // static stub relocation stores the instruction address of the call
1677 __ relocate(static_stub_Relocation::spec(mark));
1678
1679 __ set_metadata(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));
1680
1681 __ set_inst_mark();
1682 AddressLiteral addrlit(-1);
1683 __ JUMP(addrlit, G3, 0);
1684
1685 __ delayed()->nop();
1686
1687 // Update current stubs pointer and restore code_end.
1688 __ end_a_stub();
1689 }
1690
1691 // size of call stub, compiled java to interpretor
1692 uint size_java_to_interp() {
1693 // This doesn't need to be accurate but it must be larger or equal to
1694 // the real size of the stub.
1695 return (NativeMovConstReg::instruction_size + // sethi/setlo;
1696 NativeJump::instruction_size + // sethi; jmp; nop
1697 (TraceJumps ? 20 * BytesPerInstWord : 0) );
1698 }
1699 // relocation entries for call stub, compiled java to interpretor
1700 uint reloc_java_to_interp() {
1701 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call
1702 }
1703
1704
1705 //=============================================================================
1706 #ifndef PRODUCT
1707 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1708 st->print_cr("\nUEP:");
1709 #ifdef _LP64
1710 if (UseCompressedKlassPointers) {
1711 assert(Universe::heap() != NULL, "java heap should be initialized");
1712 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1713 st->print_cr("\tSLL R_G5,3,R_G5");
1714 if (Universe::narrow_klass_base() != NULL)
1715 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1716 } else {
1717 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1718 }
1719 st->print_cr("\tCMP R_G5,R_G3" );
1720 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1721 #else // _LP64
1722 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1723 st->print_cr("\tCMP R_G5,R_G3" );
1724 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1725 #endif // _LP64
1726 }
1727 #endif
1728
1729 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1730 MacroAssembler _masm(&cbuf);
1731 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1732 Register temp_reg = G3;
1733 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1734
1735 // Load klass from receiver
1736 __ load_klass(O0, temp_reg);
1737 // Compare against expected klass
1738 __ cmp(temp_reg, G5_ic_reg);
1739 // Branch to miss code, checks xcc or icc depending
1740 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1741 }
1742
1743 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1744 return MachNode::size(ra_);
1745 }
1746
1747
1748 //=============================================================================
1749
1750 uint size_exception_handler() {
1751 if (TraceJumps) {
1752 return (400); // just a guess
1753 }
1754 return ( NativeJump::instruction_size ); // sethi;jmp;nop
1755 }
1756
1757 uint size_deopt_handler() {
1758 if (TraceJumps) {
1759 return (400); // just a guess
1760 }
1761 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
1762 }
1763
1764 // Emit exception handler code.
1765 int emit_exception_handler(CodeBuffer& cbuf) {
1766 Register temp_reg = G3;
1767 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1768 MacroAssembler _masm(&cbuf);
1769
1770 address base =
1771 __ start_a_stub(size_exception_handler());
1772 if (base == NULL) return 0; // CodeBuffer::expand failed
1773
1774 int offset = __ offset();
1775
1776 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1777 __ delayed()->nop();
1778
1779 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1780
1781 __ end_a_stub();
1782
1783 return offset;
1784 }
1785
1786 int emit_deopt_handler(CodeBuffer& cbuf) {
1787 // Can't use any of the current frame's registers as we may have deopted
1788 // at a poll and everything (including G3) can be live.
1789 Register temp_reg = L0;
1790 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1791 MacroAssembler _masm(&cbuf);
1792
1793 address base =
1794 __ start_a_stub(size_deopt_handler());
1795 if (base == NULL) return 0; // CodeBuffer::expand failed
1796
1797 int offset = __ offset();
1798 __ save_frame(0);
1799 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1800 __ delayed()->restore();
1801
1802 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1803
1804 __ end_a_stub();
1805 return offset;
1806
1807 }
1808
1809 // Given a register encoding, produce a Integer Register object
1810 static Register reg_to_register_object(int register_encoding) {
1811 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1812 return as_Register(register_encoding);
1813 }
1814
1815 // Given a register encoding, produce a single-precision Float Register object
1816 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1817 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1818 return as_SingleFloatRegister(register_encoding);
1819 }
1820
1821 // Given a register encoding, produce a double-precision Float Register object
1822 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1823 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1824 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1825 return as_DoubleFloatRegister(register_encoding);
1826 }
1827
1828 const bool Matcher::match_rule_supported(int opcode) {
1829 if (!has_match_rule(opcode))
1830 return false;
1831
1832 switch (opcode) {
1833 case Op_CountLeadingZerosI:
1834 case Op_CountLeadingZerosL:
1835 case Op_CountTrailingZerosI:
1836 case Op_CountTrailingZerosL:
1837 case Op_PopCountI:
1838 case Op_PopCountL:
1839 if (!UsePopCountInstruction)
1840 return false;
1841 case Op_CompareAndSwapL:
1842 #ifdef _LP64
1843 case Op_CompareAndSwapP:
1844 #endif
1845 if (!VM_Version::supports_cx8())
1846 return false;
1847 break;
1848 }
1849
1850 return true; // Per default match rules are supported.
1851 }
1852
1853 int Matcher::regnum_to_fpu_offset(int regnum) {
1854 return regnum - 32; // The FP registers are in the second chunk
1855 }
1856
1857 #ifdef ASSERT
1858 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1859 #endif
1860
1861 // Vector width in bytes
1862 const int Matcher::vector_width_in_bytes(BasicType bt) {
1863 assert(MaxVectorSize == 8, "");
1864 return 8;
1865 }
1866
1867 // Vector ideal reg
1868 const int Matcher::vector_ideal_reg(int size) {
1869 assert(MaxVectorSize == 8, "");
1870 return Op_RegD;
1871 }
1872
1873 const int Matcher::vector_shift_count_ideal_reg(int size) {
1874 fatal("vector shift is not supported");
1875 return Node::NotAMachineReg;
1876 }
1877
1878 // Limits on vector size (number of elements) loaded into vector.
1879 const int Matcher::max_vector_size(const BasicType bt) {
1880 assert(is_java_primitive(bt), "only primitive type vectors");
1881 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1882 }
1883
1884 const int Matcher::min_vector_size(const BasicType bt) {
1885 return max_vector_size(bt); // Same as max.
1886 }
1887
1888 // SPARC doesn't support misaligned vectors store/load.
1889 const bool Matcher::misaligned_vectors_ok() {
1890 return false;
1891 }
1892
1893 // USII supports fxtof through the whole range of number, USIII doesn't
1894 const bool Matcher::convL2FSupported(void) {
1895 return VM_Version::has_fast_fxtof();
1896 }
1897
1898 // Is this branch offset short enough that a short branch can be used?
1899 //
1900 // NOTE: If the platform does not provide any short branch variants, then
1901 // this method should return false for offset 0.
1902 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1903 // The passed offset is relative to address of the branch.
1904 // Don't need to adjust the offset.
1905 return UseCBCond && Assembler::is_simm12(offset);
1906 }
1907
1908 const bool Matcher::isSimpleConstant64(jlong value) {
1909 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1910 // Depends on optimizations in MacroAssembler::setx.
1911 int hi = (int)(value >> 32);
1912 int lo = (int)(value & ~0);
1913 return (hi == 0) || (hi == -1) || (lo == 0);
1914 }
1915
1916 // No scaling for the parameter the ClearArray node.
1917 const bool Matcher::init_array_count_is_in_bytes = true;
1918
1919 // Threshold size for cleararray.
1920 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1921
1922 // No additional cost for CMOVL.
1923 const int Matcher::long_cmove_cost() { return 0; }
1924
1925 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1926 const int Matcher::float_cmove_cost() {
1927 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1928 }
1929
1930 // Should the Matcher clone shifts on addressing modes, expecting them to
1931 // be subsumed into complex addressing expressions or compute them into
1932 // registers? True for Intel but false for most RISCs
1933 const bool Matcher::clone_shift_expressions = false;
1934
1935 // Do we need to mask the count passed to shift instructions or does
1936 // the cpu only look at the lower 5/6 bits anyway?
1937 const bool Matcher::need_masked_shift_count = false;
1938
1939 bool Matcher::narrow_oop_use_complex_address() {
1940 NOT_LP64(ShouldNotCallThis());
1941 assert(UseCompressedOops, "only for compressed oops code");
1942 return false;
1943 }
1944
1945 bool Matcher::narrow_klass_use_complex_address() {
1946 NOT_LP64(ShouldNotCallThis());
1947 assert(UseCompressedKlassPointers, "only for compressed klass code");
1948 return false;
1949 }
1950
1951 // Is it better to copy float constants, or load them directly from memory?
1952 // Intel can load a float constant from a direct address, requiring no
1953 // extra registers. Most RISCs will have to materialize an address into a
1954 // register first, so they would do better to copy the constant from stack.
1955 const bool Matcher::rematerialize_float_constants = false;
1956
1957 // If CPU can load and store mis-aligned doubles directly then no fixup is
1958 // needed. Else we split the double into 2 integer pieces and move it
1959 // piece-by-piece. Only happens when passing doubles into C code as the
1960 // Java calling convention forces doubles to be aligned.
1961 #ifdef _LP64
1962 const bool Matcher::misaligned_doubles_ok = true;
1963 #else
1964 const bool Matcher::misaligned_doubles_ok = false;
1965 #endif
1966
1967 // No-op on SPARC.
1968 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1969 }
1970
1971 // Advertise here if the CPU requires explicit rounding operations
1972 // to implement the UseStrictFP mode.
1973 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1974
1975 // Are floats conerted to double when stored to stack during deoptimization?
1976 // Sparc does not handle callee-save floats.
1977 bool Matcher::float_in_double() { return false; }
1978
1979 // Do ints take an entire long register or just half?
1980 // Note that we if-def off of _LP64.
1981 // The relevant question is how the int is callee-saved. In _LP64
1982 // the whole long is written but de-opt'ing will have to extract
1983 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1984 #ifdef _LP64
1985 const bool Matcher::int_in_long = true;
1986 #else
1987 const bool Matcher::int_in_long = false;
1988 #endif
1989
1990 // Return whether or not this register is ever used as an argument. This
1991 // function is used on startup to build the trampoline stubs in generateOptoStub.
1992 // Registers not mentioned will be killed by the VM call in the trampoline, and
1993 // arguments in those registers not be available to the callee.
1994 bool Matcher::can_be_java_arg( int reg ) {
1995 // Standard sparc 6 args in registers
1996 if( reg == R_I0_num ||
1997 reg == R_I1_num ||
1998 reg == R_I2_num ||
1999 reg == R_I3_num ||
2000 reg == R_I4_num ||
2001 reg == R_I5_num ) return true;
2002 #ifdef _LP64
2003 // 64-bit builds can pass 64-bit pointers and longs in
2004 // the high I registers
2005 if( reg == R_I0H_num ||
2006 reg == R_I1H_num ||
2007 reg == R_I2H_num ||
2008 reg == R_I3H_num ||
2009 reg == R_I4H_num ||
2010 reg == R_I5H_num ) return true;
2011
2012 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2013 return true;
2014 }
2015
2016 #else
2017 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2018 // Longs cannot be passed in O regs, because O regs become I regs
2019 // after a 'save' and I regs get their high bits chopped off on
2020 // interrupt.
2021 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2022 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2023 #endif
2024 // A few float args in registers
2025 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2026
2027 return false;
2028 }
2029
2030 bool Matcher::is_spillable_arg( int reg ) {
2031 return can_be_java_arg(reg);
2032 }
2033
2034 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2035 // Use hardware SDIVX instruction when it is
2036 // faster than a code which use multiply.
2037 return VM_Version::has_fast_idiv();
2038 }
2039
2040 // Register for DIVI projection of divmodI
2041 RegMask Matcher::divI_proj_mask() {
2042 ShouldNotReachHere();
2043 return RegMask();
2044 }
2045
2046 // Register for MODI projection of divmodI
2047 RegMask Matcher::modI_proj_mask() {
2048 ShouldNotReachHere();
2049 return RegMask();
2050 }
2051
2052 // Register for DIVL projection of divmodL
2053 RegMask Matcher::divL_proj_mask() {
2054 ShouldNotReachHere();
2055 return RegMask();
2056 }
2057
2058 // Register for MODL projection of divmodL
2059 RegMask Matcher::modL_proj_mask() {
2060 ShouldNotReachHere();
2061 return RegMask();
2062 }
2063
2064 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2065 return L7_REGP_mask();
2066 }
2067
2068 %}
2069
2070
2071 // The intptr_t operand types, defined by textual substitution.
2072 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2073 #ifdef _LP64
2074 #define immX immL
2075 #define immX13 immL13
2076 #define immX13m7 immL13m7
2077 #define iRegX iRegL
2078 #define g1RegX g1RegL
2079 #else
2080 #define immX immI
2081 #define immX13 immI13
2082 #define immX13m7 immI13m7
2083 #define iRegX iRegI
2084 #define g1RegX g1RegI
2085 #endif
2086
2087 //----------ENCODING BLOCK-----------------------------------------------------
2088 // This block specifies the encoding classes used by the compiler to output
2089 // byte streams. Encoding classes are parameterized macros used by
2090 // Machine Instruction Nodes in order to generate the bit encoding of the
2091 // instruction. Operands specify their base encoding interface with the
2092 // interface keyword. There are currently supported four interfaces,
2093 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2094 // operand to generate a function which returns its register number when
2095 // queried. CONST_INTER causes an operand to generate a function which
2096 // returns the value of the constant when queried. MEMORY_INTER causes an
2097 // operand to generate four functions which return the Base Register, the
2098 // Index Register, the Scale Value, and the Offset Value of the operand when
2099 // queried. COND_INTER causes an operand to generate six functions which
2100 // return the encoding code (ie - encoding bits for the instruction)
2101 // associated with each basic boolean condition for a conditional instruction.
2102 //
2103 // Instructions specify two basic values for encoding. Again, a function
2104 // is available to check if the constant displacement is an oop. They use the
2105 // ins_encode keyword to specify their encoding classes (which must be
2106 // a sequence of enc_class names, and their parameters, specified in
2107 // the encoding block), and they use the
2108 // opcode keyword to specify, in order, their primary, secondary, and
2109 // tertiary opcode. Only the opcode sections which a particular instruction
2110 // needs for encoding need to be specified.
2111 encode %{
2112 enc_class enc_untested %{
2113 #ifdef ASSERT
2114 MacroAssembler _masm(&cbuf);
2115 __ untested("encoding");
2116 #endif
2117 %}
2118
2119 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2120 emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
2121 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2122 %}
2123
2124 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2125 emit_form3_mem_reg(cbuf, this, $primary, -1,
2126 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2127 %}
2128
2129 enc_class form3_mem_prefetch_read( memory mem ) %{
2130 emit_form3_mem_reg(cbuf, this, $primary, -1,
2131 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2132 %}
2133
2134 enc_class form3_mem_prefetch_write( memory mem ) %{
2135 emit_form3_mem_reg(cbuf, this, $primary, -1,
2136 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2137 %}
2138
2139 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2140 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2141 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2142 guarantee($mem$$index == R_G0_enc, "double index?");
2143 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2144 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2145 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2146 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2147 %}
2148
2149 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2150 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2151 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2152 guarantee($mem$$index == R_G0_enc, "double index?");
2153 // Load long with 2 instructions
2154 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2155 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2156 %}
2157
2158 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2159 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2160 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2161 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2162 %}
2163
2164 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2165 // Encode a reg-reg copy. If it is useless, then empty encoding.
2166 if( $rs2$$reg != $rd$$reg )
2167 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2168 %}
2169
2170 // Target lo half of long
2171 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2172 // Encode a reg-reg copy. If it is useless, then empty encoding.
2173 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2174 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2175 %}
2176
2177 // Source lo half of long
2178 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2179 // Encode a reg-reg copy. If it is useless, then empty encoding.
2180 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2181 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2182 %}
2183
2184 // Target hi half of long
2185 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2186 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2187 %}
2188
2189 // Source lo half of long, and leave it sign extended.
2190 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2191 // Sign extend low half
2192 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2193 %}
2194
2195 // Source hi half of long, and leave it sign extended.
2196 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2197 // Shift high half to low half
2198 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2199 %}
2200
2201 // Source hi half of long
2202 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2203 // Encode a reg-reg copy. If it is useless, then empty encoding.
2204 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2205 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2206 %}
2207
2208 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2209 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2210 %}
2211
2212 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2213 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2214 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2215 %}
2216
2217 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2218 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2219 // clear if nothing else is happening
2220 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2221 // blt,a,pn done
2222 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2223 // mov dst,-1 in delay slot
2224 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2225 %}
2226
2227 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2228 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2229 %}
2230
2231 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2232 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2233 %}
2234
2235 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2236 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2237 %}
2238
2239 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2240 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2241 %}
2242
2243 enc_class move_return_pc_to_o1() %{
2244 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2245 %}
2246
2247 #ifdef _LP64
2248 /* %%% merge with enc_to_bool */
2249 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2250 MacroAssembler _masm(&cbuf);
2251
2252 Register src_reg = reg_to_register_object($src$$reg);
2253 Register dst_reg = reg_to_register_object($dst$$reg);
2254 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2255 %}
2256 #endif
2257
2258 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2259 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2260 MacroAssembler _masm(&cbuf);
2261
2262 Register p_reg = reg_to_register_object($p$$reg);
2263 Register q_reg = reg_to_register_object($q$$reg);
2264 Register y_reg = reg_to_register_object($y$$reg);
2265 Register tmp_reg = reg_to_register_object($tmp$$reg);
2266
2267 __ subcc( p_reg, q_reg, p_reg );
2268 __ add ( p_reg, y_reg, tmp_reg );
2269 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2270 %}
2271
2272 enc_class form_d2i_helper(regD src, regF dst) %{
2273 // fcmp %fcc0,$src,$src
2274 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2275 // branch %fcc0 not-nan, predict taken
2276 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2277 // fdtoi $src,$dst
2278 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2279 // fitos $dst,$dst (if nan)
2280 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2281 // clear $dst (if nan)
2282 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2283 // carry on here...
2284 %}
2285
2286 enc_class form_d2l_helper(regD src, regD dst) %{
2287 // fcmp %fcc0,$src,$src check for NAN
2288 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2289 // branch %fcc0 not-nan, predict taken
2290 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2291 // fdtox $src,$dst convert in delay slot
2292 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2293 // fxtod $dst,$dst (if nan)
2294 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2295 // clear $dst (if nan)
2296 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2297 // carry on here...
2298 %}
2299
2300 enc_class form_f2i_helper(regF src, regF dst) %{
2301 // fcmps %fcc0,$src,$src
2302 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2303 // branch %fcc0 not-nan, predict taken
2304 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2305 // fstoi $src,$dst
2306 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2307 // fitos $dst,$dst (if nan)
2308 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2309 // clear $dst (if nan)
2310 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2311 // carry on here...
2312 %}
2313
2314 enc_class form_f2l_helper(regF src, regD dst) %{
2315 // fcmps %fcc0,$src,$src
2316 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2317 // branch %fcc0 not-nan, predict taken
2318 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2319 // fstox $src,$dst
2320 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2321 // fxtod $dst,$dst (if nan)
2322 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2323 // clear $dst (if nan)
2324 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2325 // carry on here...
2326 %}
2327
2328 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2329 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2330 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2331 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2332
2333 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2334
2335 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2336 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2337
2338 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2339 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2340 %}
2341
2342 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2343 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2344 %}
2345
2346 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2347 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2348 %}
2349
2350 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2351 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2352 %}
2353
2354 enc_class form3_convI2F(regF rs2, regF rd) %{
2355 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2356 %}
2357
2358 // Encloding class for traceable jumps
2359 enc_class form_jmpl(g3RegP dest) %{
2360 emit_jmpl(cbuf, $dest$$reg);
2361 %}
2362
2363 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2364 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2365 %}
2366
2367 enc_class form2_nop() %{
2368 emit_nop(cbuf);
2369 %}
2370
2371 enc_class form2_illtrap() %{
2372 emit_illtrap(cbuf);
2373 %}
2374
2375
2376 // Compare longs and convert into -1, 0, 1.
2377 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2378 // CMP $src1,$src2
2379 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2380 // blt,a,pn done
2381 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2382 // mov dst,-1 in delay slot
2383 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2384 // bgt,a,pn done
2385 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2386 // mov dst,1 in delay slot
2387 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2388 // CLR $dst
2389 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2390 %}
2391
2392 enc_class enc_PartialSubtypeCheck() %{
2393 MacroAssembler _masm(&cbuf);
2394 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2395 __ delayed()->nop();
2396 %}
2397
2398 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2399 MacroAssembler _masm(&cbuf);
2400 Label* L = $labl$$label;
2401 Assembler::Predict predict_taken =
2402 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2403
2404 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2405 __ delayed()->nop();
2406 %}
2407
2408 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2409 MacroAssembler _masm(&cbuf);
2410 Label* L = $labl$$label;
2411 Assembler::Predict predict_taken =
2412 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2413
2414 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2415 __ delayed()->nop();
2416 %}
2417
2418 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2419 int op = (Assembler::arith_op << 30) |
2420 ($dst$$reg << 25) |
2421 (Assembler::movcc_op3 << 19) |
2422 (1 << 18) | // cc2 bit for 'icc'
2423 ($cmp$$cmpcode << 14) |
2424 (0 << 13) | // select register move
2425 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2426 ($src$$reg << 0);
2427 cbuf.insts()->emit_int32(op);
2428 %}
2429
2430 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2431 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2432 int op = (Assembler::arith_op << 30) |
2433 ($dst$$reg << 25) |
2434 (Assembler::movcc_op3 << 19) |
2435 (1 << 18) | // cc2 bit for 'icc'
2436 ($cmp$$cmpcode << 14) |
2437 (1 << 13) | // select immediate move
2438 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2439 (simm11 << 0);
2440 cbuf.insts()->emit_int32(op);
2441 %}
2442
2443 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2444 int op = (Assembler::arith_op << 30) |
2445 ($dst$$reg << 25) |
2446 (Assembler::movcc_op3 << 19) |
2447 (0 << 18) | // cc2 bit for 'fccX'
2448 ($cmp$$cmpcode << 14) |
2449 (0 << 13) | // select register move
2450 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2451 ($src$$reg << 0);
2452 cbuf.insts()->emit_int32(op);
2453 %}
2454
2455 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2456 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2457 int op = (Assembler::arith_op << 30) |
2458 ($dst$$reg << 25) |
2459 (Assembler::movcc_op3 << 19) |
2460 (0 << 18) | // cc2 bit for 'fccX'
2461 ($cmp$$cmpcode << 14) |
2462 (1 << 13) | // select immediate move
2463 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2464 (simm11 << 0);
2465 cbuf.insts()->emit_int32(op);
2466 %}
2467
2468 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2469 int op = (Assembler::arith_op << 30) |
2470 ($dst$$reg << 25) |
2471 (Assembler::fpop2_op3 << 19) |
2472 (0 << 18) |
2473 ($cmp$$cmpcode << 14) |
2474 (1 << 13) | // select register move
2475 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2476 ($primary << 5) | // select single, double or quad
2477 ($src$$reg << 0);
2478 cbuf.insts()->emit_int32(op);
2479 %}
2480
2481 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2482 int op = (Assembler::arith_op << 30) |
2483 ($dst$$reg << 25) |
2484 (Assembler::fpop2_op3 << 19) |
2485 (0 << 18) |
2486 ($cmp$$cmpcode << 14) |
2487 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2488 ($primary << 5) | // select single, double or quad
2489 ($src$$reg << 0);
2490 cbuf.insts()->emit_int32(op);
2491 %}
2492
2493 // Used by the MIN/MAX encodings. Same as a CMOV, but
2494 // the condition comes from opcode-field instead of an argument.
2495 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2496 int op = (Assembler::arith_op << 30) |
2497 ($dst$$reg << 25) |
2498 (Assembler::movcc_op3 << 19) |
2499 (1 << 18) | // cc2 bit for 'icc'
2500 ($primary << 14) |
2501 (0 << 13) | // select register move
2502 (0 << 11) | // cc1, cc0 bits for 'icc'
2503 ($src$$reg << 0);
2504 cbuf.insts()->emit_int32(op);
2505 %}
2506
2507 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2508 int op = (Assembler::arith_op << 30) |
2509 ($dst$$reg << 25) |
2510 (Assembler::movcc_op3 << 19) |
2511 (6 << 16) | // cc2 bit for 'xcc'
2512 ($primary << 14) |
2513 (0 << 13) | // select register move
2514 (0 << 11) | // cc1, cc0 bits for 'icc'
2515 ($src$$reg << 0);
2516 cbuf.insts()->emit_int32(op);
2517 %}
2518
2519 enc_class Set13( immI13 src, iRegI rd ) %{
2520 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2521 %}
2522
2523 enc_class SetHi22( immI src, iRegI rd ) %{
2524 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2525 %}
2526
2527 enc_class Set32( immI src, iRegI rd ) %{
2528 MacroAssembler _masm(&cbuf);
2529 __ set($src$$constant, reg_to_register_object($rd$$reg));
2530 %}
2531
2532 enc_class call_epilog %{
2533 if( VerifyStackAtCalls ) {
2534 MacroAssembler _masm(&cbuf);
2535 int framesize = ra_->C->frame_slots() << LogBytesPerInt;
2536 Register temp_reg = G3;
2537 __ add(SP, framesize, temp_reg);
2538 __ cmp(temp_reg, FP);
2539 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2540 }
2541 %}
2542
2543 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2544 // to G1 so the register allocator will not have to deal with the misaligned register
2545 // pair.
2546 enc_class adjust_long_from_native_call %{
2547 #ifndef _LP64
2548 if (returns_long()) {
2549 // sllx O0,32,O0
2550 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2551 // srl O1,0,O1
2552 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2553 // or O0,O1,G1
2554 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2555 }
2556 #endif
2557 %}
2558
2559 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2560 // CALL directly to the runtime
2561 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2562 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2563 /*preserve_g2=*/true);
2564 %}
2565
2566 enc_class preserve_SP %{
2567 MacroAssembler _masm(&cbuf);
2568 __ mov(SP, L7_mh_SP_save);
2569 %}
2570
2571 enc_class restore_SP %{
2572 MacroAssembler _masm(&cbuf);
2573 __ mov(L7_mh_SP_save, SP);
2574 %}
2575
2576 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2577 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2578 // who we intended to call.
2579 if ( !_method ) {
2580 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2581 } else if (_optimized_virtual) {
2582 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2583 } else {
2584 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2585 }
2586 if( _method ) { // Emit stub for static call
2587 emit_java_to_interp(cbuf);
2588 }
2589 %}
2590
2591 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2592 MacroAssembler _masm(&cbuf);
2593 __ set_inst_mark();
2594 int vtable_index = this->_vtable_index;
2595 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2596 if (vtable_index < 0) {
2597 // must be invalid_vtable_index, not nonvirtual_vtable_index
2598 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2599 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2600 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2601 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2602 __ ic_call((address)$meth$$method);
2603 } else {
2604 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2605 // Just go thru the vtable
2606 // get receiver klass (receiver already checked for non-null)
2607 // If we end up going thru a c2i adapter interpreter expects method in G5
2608 int off = __ offset();
2609 __ load_klass(O0, G3_scratch);
2610 int klass_load_size;
2611 if (UseCompressedKlassPointers) {
2612 assert(Universe::heap() != NULL, "java heap should be initialized");
2613 if (Universe::narrow_klass_base() == NULL)
2614 klass_load_size = 2*BytesPerInstWord;
2615 else
2616 klass_load_size = 3*BytesPerInstWord;
2617 } else {
2618 klass_load_size = 1*BytesPerInstWord;
2619 }
2620 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2621 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2622 if (Assembler::is_simm13(v_off)) {
2623 __ ld_ptr(G3, v_off, G5_method);
2624 } else {
2625 // Generate 2 instructions
2626 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2627 __ or3(G5_method, v_off & 0x3ff, G5_method);
2628 // ld_ptr, set_hi, set
2629 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2630 "Unexpected instruction size(s)");
2631 __ ld_ptr(G3, G5_method, G5_method);
2632 }
2633 // NOTE: for vtable dispatches, the vtable entry will never be null.
2634 // However it may very well end up in handle_wrong_method if the
2635 // method is abstract for the particular class.
2636 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2637 // jump to target (either compiled code or c2iadapter)
2638 __ jmpl(G3_scratch, G0, O7);
2639 __ delayed()->nop();
2640 }
2641 %}
2642
2643 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2644 MacroAssembler _masm(&cbuf);
2645
2646 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2647 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2648 // we might be calling a C2I adapter which needs it.
2649
2650 assert(temp_reg != G5_ic_reg, "conflicting registers");
2651 // Load nmethod
2652 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2653
2654 // CALL to compiled java, indirect the contents of G3
2655 __ set_inst_mark();
2656 __ callr(temp_reg, G0);
2657 __ delayed()->nop();
2658 %}
2659
2660 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2661 MacroAssembler _masm(&cbuf);
2662 Register Rdividend = reg_to_register_object($src1$$reg);
2663 Register Rdivisor = reg_to_register_object($src2$$reg);
2664 Register Rresult = reg_to_register_object($dst$$reg);
2665
2666 __ sra(Rdivisor, 0, Rdivisor);
2667 __ sra(Rdividend, 0, Rdividend);
2668 __ sdivx(Rdividend, Rdivisor, Rresult);
2669 %}
2670
2671 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2672 MacroAssembler _masm(&cbuf);
2673
2674 Register Rdividend = reg_to_register_object($src1$$reg);
2675 int divisor = $imm$$constant;
2676 Register Rresult = reg_to_register_object($dst$$reg);
2677
2678 __ sra(Rdividend, 0, Rdividend);
2679 __ sdivx(Rdividend, divisor, Rresult);
2680 %}
2681
2682 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2683 MacroAssembler _masm(&cbuf);
2684 Register Rsrc1 = reg_to_register_object($src1$$reg);
2685 Register Rsrc2 = reg_to_register_object($src2$$reg);
2686 Register Rdst = reg_to_register_object($dst$$reg);
2687
2688 __ sra( Rsrc1, 0, Rsrc1 );
2689 __ sra( Rsrc2, 0, Rsrc2 );
2690 __ mulx( Rsrc1, Rsrc2, Rdst );
2691 __ srlx( Rdst, 32, Rdst );
2692 %}
2693
2694 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2695 MacroAssembler _masm(&cbuf);
2696 Register Rdividend = reg_to_register_object($src1$$reg);
2697 Register Rdivisor = reg_to_register_object($src2$$reg);
2698 Register Rresult = reg_to_register_object($dst$$reg);
2699 Register Rscratch = reg_to_register_object($scratch$$reg);
2700
2701 assert(Rdividend != Rscratch, "");
2702 assert(Rdivisor != Rscratch, "");
2703
2704 __ sra(Rdividend, 0, Rdividend);
2705 __ sra(Rdivisor, 0, Rdivisor);
2706 __ sdivx(Rdividend, Rdivisor, Rscratch);
2707 __ mulx(Rscratch, Rdivisor, Rscratch);
2708 __ sub(Rdividend, Rscratch, Rresult);
2709 %}
2710
2711 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2712 MacroAssembler _masm(&cbuf);
2713
2714 Register Rdividend = reg_to_register_object($src1$$reg);
2715 int divisor = $imm$$constant;
2716 Register Rresult = reg_to_register_object($dst$$reg);
2717 Register Rscratch = reg_to_register_object($scratch$$reg);
2718
2719 assert(Rdividend != Rscratch, "");
2720
2721 __ sra(Rdividend, 0, Rdividend);
2722 __ sdivx(Rdividend, divisor, Rscratch);
2723 __ mulx(Rscratch, divisor, Rscratch);
2724 __ sub(Rdividend, Rscratch, Rresult);
2725 %}
2726
2727 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2728 MacroAssembler _masm(&cbuf);
2729
2730 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2731 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2732
2733 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2734 %}
2735
2736 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2737 MacroAssembler _masm(&cbuf);
2738
2739 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2740 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2741
2742 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2743 %}
2744
2745 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2746 MacroAssembler _masm(&cbuf);
2747
2748 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2749 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2750
2751 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2752 %}
2753
2754 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2755 MacroAssembler _masm(&cbuf);
2756
2757 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2758 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2759
2760 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2761 %}
2762
2763 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2764 MacroAssembler _masm(&cbuf);
2765
2766 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2767 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2768
2769 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2770 %}
2771
2772 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2773 MacroAssembler _masm(&cbuf);
2774
2775 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2776 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2777
2778 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2779 %}
2780
2781 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2782 MacroAssembler _masm(&cbuf);
2783
2784 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2785 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2786
2787 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2788 %}
2789
2790 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2791 MacroAssembler _masm(&cbuf);
2792
2793 Register Roop = reg_to_register_object($oop$$reg);
2794 Register Rbox = reg_to_register_object($box$$reg);
2795 Register Rscratch = reg_to_register_object($scratch$$reg);
2796 Register Rmark = reg_to_register_object($scratch2$$reg);
2797
2798 assert(Roop != Rscratch, "");
2799 assert(Roop != Rmark, "");
2800 assert(Rbox != Rscratch, "");
2801 assert(Rbox != Rmark, "");
2802
2803 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2804 %}
2805
2806 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2807 MacroAssembler _masm(&cbuf);
2808
2809 Register Roop = reg_to_register_object($oop$$reg);
2810 Register Rbox = reg_to_register_object($box$$reg);
2811 Register Rscratch = reg_to_register_object($scratch$$reg);
2812 Register Rmark = reg_to_register_object($scratch2$$reg);
2813
2814 assert(Roop != Rscratch, "");
2815 assert(Roop != Rmark, "");
2816 assert(Rbox != Rscratch, "");
2817 assert(Rbox != Rmark, "");
2818
2819 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2820 %}
2821
2822 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2823 MacroAssembler _masm(&cbuf);
2824 Register Rmem = reg_to_register_object($mem$$reg);
2825 Register Rold = reg_to_register_object($old$$reg);
2826 Register Rnew = reg_to_register_object($new$$reg);
2827
2828 // casx_under_lock picks 1 of 3 encodings:
2829 // For 32-bit pointers you get a 32-bit CAS
2830 // For 64-bit pointers you get a 64-bit CASX
2831 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2832 __ cmp( Rold, Rnew );
2833 %}
2834
2835 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2836 Register Rmem = reg_to_register_object($mem$$reg);
2837 Register Rold = reg_to_register_object($old$$reg);
2838 Register Rnew = reg_to_register_object($new$$reg);
2839
2840 MacroAssembler _masm(&cbuf);
2841 __ mov(Rnew, O7);
2842 __ casx(Rmem, Rold, O7);
2843 __ cmp( Rold, O7 );
2844 %}
2845
2846 // raw int cas, used for compareAndSwap
2847 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2848 Register Rmem = reg_to_register_object($mem$$reg);
2849 Register Rold = reg_to_register_object($old$$reg);
2850 Register Rnew = reg_to_register_object($new$$reg);
2851
2852 MacroAssembler _masm(&cbuf);
2853 __ mov(Rnew, O7);
2854 __ cas(Rmem, Rold, O7);
2855 __ cmp( Rold, O7 );
2856 %}
2857
2858 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2859 Register Rres = reg_to_register_object($res$$reg);
2860
2861 MacroAssembler _masm(&cbuf);
2862 __ mov(1, Rres);
2863 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2864 %}
2865
2866 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2867 Register Rres = reg_to_register_object($res$$reg);
2868
2869 MacroAssembler _masm(&cbuf);
2870 __ mov(1, Rres);
2871 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2872 %}
2873
2874 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2875 MacroAssembler _masm(&cbuf);
2876 Register Rdst = reg_to_register_object($dst$$reg);
2877 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2878 : reg_to_DoubleFloatRegister_object($src1$$reg);
2879 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2880 : reg_to_DoubleFloatRegister_object($src2$$reg);
2881
2882 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2883 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2884 %}
2885
2886
2887 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2888 Label Ldone, Lloop;
2889 MacroAssembler _masm(&cbuf);
2890
2891 Register str1_reg = reg_to_register_object($str1$$reg);
2892 Register str2_reg = reg_to_register_object($str2$$reg);
2893 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2894 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2895 Register result_reg = reg_to_register_object($result$$reg);
2896
2897 assert(result_reg != str1_reg &&
2898 result_reg != str2_reg &&
2899 result_reg != cnt1_reg &&
2900 result_reg != cnt2_reg ,
2901 "need different registers");
2902
2903 // Compute the minimum of the string lengths(str1_reg) and the
2904 // difference of the string lengths (stack)
2905
2906 // See if the lengths are different, and calculate min in str1_reg.
2907 // Stash diff in O7 in case we need it for a tie-breaker.
2908 Label Lskip;
2909 __ subcc(cnt1_reg, cnt2_reg, O7);
2910 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2911 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2912 // cnt2 is shorter, so use its count:
2913 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2914 __ bind(Lskip);
2915
2916 // reallocate cnt1_reg, cnt2_reg, result_reg
2917 // Note: limit_reg holds the string length pre-scaled by 2
2918 Register limit_reg = cnt1_reg;
2919 Register chr2_reg = cnt2_reg;
2920 Register chr1_reg = result_reg;
2921 // str{12} are the base pointers
2922
2923 // Is the minimum length zero?
2924 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2925 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2926 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2927
2928 // Load first characters
2929 __ lduh(str1_reg, 0, chr1_reg);
2930 __ lduh(str2_reg, 0, chr2_reg);
2931
2932 // Compare first characters
2933 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2934 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2935 assert(chr1_reg == result_reg, "result must be pre-placed");
2936 __ delayed()->nop();
2937
2938 {
2939 // Check after comparing first character to see if strings are equivalent
2940 Label LSkip2;
2941 // Check if the strings start at same location
2942 __ cmp(str1_reg, str2_reg);
2943 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2944 __ delayed()->nop();
2945
2946 // Check if the length difference is zero (in O7)
2947 __ cmp(G0, O7);
2948 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2949 __ delayed()->mov(G0, result_reg); // result is zero
2950
2951 // Strings might not be equal
2952 __ bind(LSkip2);
2953 }
2954
2955 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2956 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2957 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2958
2959 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2960 __ add(str1_reg, limit_reg, str1_reg);
2961 __ add(str2_reg, limit_reg, str2_reg);
2962 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2963
2964 // Compare the rest of the characters
2965 __ lduh(str1_reg, limit_reg, chr1_reg);
2966 __ bind(Lloop);
2967 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2968 __ lduh(str2_reg, limit_reg, chr2_reg);
2969 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2970 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2971 assert(chr1_reg == result_reg, "result must be pre-placed");
2972 __ delayed()->inccc(limit_reg, sizeof(jchar));
2973 // annul LDUH if branch is not taken to prevent access past end of string
2974 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2975 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2976
2977 // If strings are equal up to min length, return the length difference.
2978 __ mov(O7, result_reg);
2979
2980 // Otherwise, return the difference between the first mismatched chars.
2981 __ bind(Ldone);
2982 %}
2983
2984 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2985 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
2986 MacroAssembler _masm(&cbuf);
2987
2988 Register str1_reg = reg_to_register_object($str1$$reg);
2989 Register str2_reg = reg_to_register_object($str2$$reg);
2990 Register cnt_reg = reg_to_register_object($cnt$$reg);
2991 Register tmp1_reg = O7;
2992 Register result_reg = reg_to_register_object($result$$reg);
2993
2994 assert(result_reg != str1_reg &&
2995 result_reg != str2_reg &&
2996 result_reg != cnt_reg &&
2997 result_reg != tmp1_reg ,
2998 "need different registers");
2999
3000 __ cmp(str1_reg, str2_reg); //same char[] ?
3001 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3002 __ delayed()->add(G0, 1, result_reg);
3003
3004 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3005 __ delayed()->add(G0, 1, result_reg); // count == 0
3006
3007 //rename registers
3008 Register limit_reg = cnt_reg;
3009 Register chr1_reg = result_reg;
3010 Register chr2_reg = tmp1_reg;
3011
3012 //check for alignment and position the pointers to the ends
3013 __ or3(str1_reg, str2_reg, chr1_reg);
3014 __ andcc(chr1_reg, 0x3, chr1_reg);
3015 // notZero means at least one not 4-byte aligned.
3016 // We could optimize the case when both arrays are not aligned
3017 // but it is not frequent case and it requires additional checks.
3018 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3019 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3020
3021 // Compare char[] arrays aligned to 4 bytes.
3022 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3023 chr1_reg, chr2_reg, Ldone);
3024 __ ba(Ldone);
3025 __ delayed()->add(G0, 1, result_reg);
3026
3027 // char by char compare
3028 __ bind(Lchar);
3029 __ add(str1_reg, limit_reg, str1_reg);
3030 __ add(str2_reg, limit_reg, str2_reg);
3031 __ neg(limit_reg); //negate count
3032
3033 __ lduh(str1_reg, limit_reg, chr1_reg);
3034 // Lchar_loop
3035 __ bind(Lchar_loop);
3036 __ lduh(str2_reg, limit_reg, chr2_reg);
3037 __ cmp(chr1_reg, chr2_reg);
3038 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3039 __ delayed()->mov(G0, result_reg); //not equal
3040 __ inccc(limit_reg, sizeof(jchar));
3041 // annul LDUH if branch is not taken to prevent access past end of string
3042 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3043 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3044
3045 __ add(G0, 1, result_reg); //equal
3046
3047 __ bind(Ldone);
3048 %}
3049
3050 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3051 Label Lvector, Ldone, Lloop;
3052 MacroAssembler _masm(&cbuf);
3053
3054 Register ary1_reg = reg_to_register_object($ary1$$reg);
3055 Register ary2_reg = reg_to_register_object($ary2$$reg);
3056 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3057 Register tmp2_reg = O7;
3058 Register result_reg = reg_to_register_object($result$$reg);
3059
3060 int length_offset = arrayOopDesc::length_offset_in_bytes();
3061 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3062
3063 // return true if the same array
3064 __ cmp(ary1_reg, ary2_reg);
3065 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3066 __ delayed()->add(G0, 1, result_reg); // equal
3067
3068 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3069 __ delayed()->mov(G0, result_reg); // not equal
3070
3071 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3072 __ delayed()->mov(G0, result_reg); // not equal
3073
3074 //load the lengths of arrays
3075 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3076 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3077
3078 // return false if the two arrays are not equal length
3079 __ cmp(tmp1_reg, tmp2_reg);
3080 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3081 __ delayed()->mov(G0, result_reg); // not equal
3082
3083 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3084 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3085
3086 // load array addresses
3087 __ add(ary1_reg, base_offset, ary1_reg);
3088 __ add(ary2_reg, base_offset, ary2_reg);
3089
3090 // renaming registers
3091 Register chr1_reg = result_reg; // for characters in ary1
3092 Register chr2_reg = tmp2_reg; // for characters in ary2
3093 Register limit_reg = tmp1_reg; // length
3094
3095 // set byte count
3096 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3097
3098 // Compare char[] arrays aligned to 4 bytes.
3099 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3100 chr1_reg, chr2_reg, Ldone);
3101 __ add(G0, 1, result_reg); // equals
3102
3103 __ bind(Ldone);
3104 %}
3105
3106 enc_class enc_rethrow() %{
3107 cbuf.set_insts_mark();
3108 Register temp_reg = G3;
3109 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3110 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3111 MacroAssembler _masm(&cbuf);
3112 #ifdef ASSERT
3113 __ save_frame(0);
3114 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3115 __ sethi(last_rethrow_addrlit, L1);
3116 Address addr(L1, last_rethrow_addrlit.low10());
3117 __ get_pc(L2);
3118 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3119 __ st_ptr(L2, addr);
3120 __ restore();
3121 #endif
3122 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3123 __ delayed()->nop();
3124 %}
3125
3126 enc_class emit_mem_nop() %{
3127 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3128 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3129 %}
3130
3131 enc_class emit_fadd_nop() %{
3132 // Generates the instruction FMOVS f31,f31
3133 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3134 %}
3135
3136 enc_class emit_br_nop() %{
3137 // Generates the instruction BPN,PN .
3138 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3139 %}
3140
3141 enc_class enc_membar_acquire %{
3142 MacroAssembler _masm(&cbuf);
3143 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3144 %}
3145
3146 enc_class enc_membar_release %{
3147 MacroAssembler _masm(&cbuf);
3148 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3149 %}
3150
3151 enc_class enc_membar_volatile %{
3152 MacroAssembler _masm(&cbuf);
3153 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3154 %}
3155
3156 %}
3157
3158 //----------FRAME--------------------------------------------------------------
3159 // Definition of frame structure and management information.
3160 //
3161 // S T A C K L A Y O U T Allocators stack-slot number
3162 // | (to get allocators register number
3163 // G Owned by | | v add VMRegImpl::stack0)
3164 // r CALLER | |
3165 // o | +--------+ pad to even-align allocators stack-slot
3166 // w V | pad0 | numbers; owned by CALLER
3167 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3168 // h ^ | in | 5
3169 // | | args | 4 Holes in incoming args owned by SELF
3170 // | | | | 3
3171 // | | +--------+
3172 // V | | old out| Empty on Intel, window on Sparc
3173 // | old |preserve| Must be even aligned.
3174 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3175 // | | in | 3 area for Intel ret address
3176 // Owned by |preserve| Empty on Sparc.
3177 // SELF +--------+
3178 // | | pad2 | 2 pad to align old SP
3179 // | +--------+ 1
3180 // | | locks | 0
3181 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3182 // | | pad1 | 11 pad to align new SP
3183 // | +--------+
3184 // | | | 10
3185 // | | spills | 9 spills
3186 // V | | 8 (pad0 slot for callee)
3187 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3188 // ^ | out | 7
3189 // | | args | 6 Holes in outgoing args owned by CALLEE
3190 // Owned by +--------+
3191 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3192 // | new |preserve| Must be even-aligned.
3193 // | SP-+--------+----> Matcher::_new_SP, even aligned
3194 // | | |
3195 //
3196 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3197 // known from SELF's arguments and the Java calling convention.
3198 // Region 6-7 is determined per call site.
3199 // Note 2: If the calling convention leaves holes in the incoming argument
3200 // area, those holes are owned by SELF. Holes in the outgoing area
3201 // are owned by the CALLEE. Holes should not be nessecary in the
3202 // incoming area, as the Java calling convention is completely under
3203 // the control of the AD file. Doubles can be sorted and packed to
3204 // avoid holes. Holes in the outgoing arguments may be nessecary for
3205 // varargs C calling conventions.
3206 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3207 // even aligned with pad0 as needed.
3208 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3209 // region 6-11 is even aligned; it may be padded out more so that
3210 // the region from SP to FP meets the minimum stack alignment.
3211
3212 frame %{
3213 // What direction does stack grow in (assumed to be same for native & Java)
3214 stack_direction(TOWARDS_LOW);
3215
3216 // These two registers define part of the calling convention
3217 // between compiled code and the interpreter.
3218 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3219 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3220
3221 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3222 cisc_spilling_operand_name(indOffset);
3223
3224 // Number of stack slots consumed by a Monitor enter
3225 #ifdef _LP64
3226 sync_stack_slots(2);
3227 #else
3228 sync_stack_slots(1);
3229 #endif
3230
3231 // Compiled code's Frame Pointer
3232 frame_pointer(R_SP);
3233
3234 // Stack alignment requirement
3235 stack_alignment(StackAlignmentInBytes);
3236 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3237 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3238
3239 // Number of stack slots between incoming argument block and the start of
3240 // a new frame. The PROLOG must add this many slots to the stack. The
3241 // EPILOG must remove this many slots.
3242 in_preserve_stack_slots(0);
3243
3244 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3245 // for calls to C. Supports the var-args backing area for register parms.
3246 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3247 #ifdef _LP64
3248 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3249 varargs_C_out_slots_killed(12);
3250 #else
3251 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3252 varargs_C_out_slots_killed( 7);
3253 #endif
3254
3255 // The after-PROLOG location of the return address. Location of
3256 // return address specifies a type (REG or STACK) and a number
3257 // representing the register number (i.e. - use a register name) or
3258 // stack slot.
3259 return_addr(REG R_I7); // Ret Addr is in register I7
3260
3261 // Body of function which returns an OptoRegs array locating
3262 // arguments either in registers or in stack slots for calling
3263 // java
3264 calling_convention %{
3265 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3266
3267 %}
3268
3269 // Body of function which returns an OptoRegs array locating
3270 // arguments either in registers or in stack slots for callin
3271 // C.
3272 c_calling_convention %{
3273 // This is obviously always outgoing
3274 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
3275 %}
3276
3277 // Location of native (C/C++) and interpreter return values. This is specified to
3278 // be the same as Java. In the 32-bit VM, long values are actually returned from
3279 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3280 // to and from the register pairs is done by the appropriate call and epilog
3281 // opcodes. This simplifies the register allocator.
3282 c_return_value %{
3283 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3284 #ifdef _LP64
3285 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3286 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3287 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3288 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3289 #else // !_LP64
3290 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3291 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3292 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3293 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3294 #endif
3295 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3296 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3297 %}
3298
3299 // Location of compiled Java return values. Same as C
3300 return_value %{
3301 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3302 #ifdef _LP64
3303 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3304 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3305 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3306 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3307 #else // !_LP64
3308 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3309 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3310 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3311 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3312 #endif
3313 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3314 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3315 %}
3316
3317 %}
3318
3319
3320 //----------ATTRIBUTES---------------------------------------------------------
3321 //----------Operand Attributes-------------------------------------------------
3322 op_attrib op_cost(1); // Required cost attribute
3323
3324 //----------Instruction Attributes---------------------------------------------
3325 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3326 ins_attrib ins_size(32); // Required size attribute (in bits)
3327 ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back
3328 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3329 // non-matching short branch variant of some
3330 // long branch?
3331
3332 //----------OPERANDS-----------------------------------------------------------
3333 // Operand definitions must precede instruction definitions for correct parsing
3334 // in the ADLC because operands constitute user defined types which are used in
3335 // instruction definitions.
3336
3337 //----------Simple Operands----------------------------------------------------
3338 // Immediate Operands
3339 // Integer Immediate: 32-bit
3340 operand immI() %{
3341 match(ConI);
3342
3343 op_cost(0);
3344 // formats are generated automatically for constants and base registers
3345 format %{ %}
3346 interface(CONST_INTER);
3347 %}
3348
3349 // Integer Immediate: 8-bit
3350 operand immI8() %{
3351 predicate(Assembler::is_simm8(n->get_int()));
3352 match(ConI);
3353 op_cost(0);
3354 format %{ %}
3355 interface(CONST_INTER);
3356 %}
3357
3358 // Integer Immediate: 13-bit
3359 operand immI13() %{
3360 predicate(Assembler::is_simm13(n->get_int()));
3361 match(ConI);
3362 op_cost(0);
3363
3364 format %{ %}
3365 interface(CONST_INTER);
3366 %}
3367
3368 // Integer Immediate: 13-bit minus 7
3369 operand immI13m7() %{
3370 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3371 match(ConI);
3372 op_cost(0);
3373
3374 format %{ %}
3375 interface(CONST_INTER);
3376 %}
3377
3378 // Integer Immediate: 16-bit
3379 operand immI16() %{
3380 predicate(Assembler::is_simm16(n->get_int()));
3381 match(ConI);
3382 op_cost(0);
3383 format %{ %}
3384 interface(CONST_INTER);
3385 %}
3386
3387 // Unsigned (positive) Integer Immediate: 13-bit
3388 operand immU13() %{
3389 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3390 match(ConI);
3391 op_cost(0);
3392
3393 format %{ %}
3394 interface(CONST_INTER);
3395 %}
3396
3397 // Integer Immediate: 6-bit
3398 operand immU6() %{
3399 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3400 match(ConI);
3401 op_cost(0);
3402 format %{ %}
3403 interface(CONST_INTER);
3404 %}
3405
3406 // Integer Immediate: 11-bit
3407 operand immI11() %{
3408 predicate(Assembler::is_simm11(n->get_int()));
3409 match(ConI);
3410 op_cost(0);
3411 format %{ %}
3412 interface(CONST_INTER);
3413 %}
3414
3415 // Integer Immediate: 5-bit
3416 operand immI5() %{
3417 predicate(Assembler::is_simm5(n->get_int()));
3418 match(ConI);
3419 op_cost(0);
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 // Integer Immediate: 0-bit
3425 operand immI0() %{
3426 predicate(n->get_int() == 0);
3427 match(ConI);
3428 op_cost(0);
3429
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3433
3434 // Integer Immediate: the value 10
3435 operand immI10() %{
3436 predicate(n->get_int() == 10);
3437 match(ConI);
3438 op_cost(0);
3439
3440 format %{ %}
3441 interface(CONST_INTER);
3442 %}
3443
3444 // Integer Immediate: the values 0-31
3445 operand immU5() %{
3446 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3447 match(ConI);
3448 op_cost(0);
3449
3450 format %{ %}
3451 interface(CONST_INTER);
3452 %}
3453
3454 // Integer Immediate: the values 1-31
3455 operand immI_1_31() %{
3456 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3457 match(ConI);
3458 op_cost(0);
3459
3460 format %{ %}
3461 interface(CONST_INTER);
3462 %}
3463
3464 // Integer Immediate: the values 32-63
3465 operand immI_32_63() %{
3466 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3467 match(ConI);
3468 op_cost(0);
3469
3470 format %{ %}
3471 interface(CONST_INTER);
3472 %}
3473
3474 // Immediates for special shifts (sign extend)
3475
3476 // Integer Immediate: the value 16
3477 operand immI_16() %{
3478 predicate(n->get_int() == 16);
3479 match(ConI);
3480 op_cost(0);
3481
3482 format %{ %}
3483 interface(CONST_INTER);
3484 %}
3485
3486 // Integer Immediate: the value 24
3487 operand immI_24() %{
3488 predicate(n->get_int() == 24);
3489 match(ConI);
3490 op_cost(0);
3491
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 // Integer Immediate: the value 255
3497 operand immI_255() %{
3498 predicate( n->get_int() == 255 );
3499 match(ConI);
3500 op_cost(0);
3501
3502 format %{ %}
3503 interface(CONST_INTER);
3504 %}
3505
3506 // Integer Immediate: the value 65535
3507 operand immI_65535() %{
3508 predicate(n->get_int() == 65535);
3509 match(ConI);
3510 op_cost(0);
3511
3512 format %{ %}
3513 interface(CONST_INTER);
3514 %}
3515
3516 // Long Immediate: the value FF
3517 operand immL_FF() %{
3518 predicate( n->get_long() == 0xFFL );
3519 match(ConL);
3520 op_cost(0);
3521
3522 format %{ %}
3523 interface(CONST_INTER);
3524 %}
3525
3526 // Long Immediate: the value FFFF
3527 operand immL_FFFF() %{
3528 predicate( n->get_long() == 0xFFFFL );
3529 match(ConL);
3530 op_cost(0);
3531
3532 format %{ %}
3533 interface(CONST_INTER);
3534 %}
3535
3536 // Pointer Immediate: 32 or 64-bit
3537 operand immP() %{
3538 match(ConP);
3539
3540 op_cost(5);
3541 // formats are generated automatically for constants and base registers
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3545
3546 #ifdef _LP64
3547 // Pointer Immediate: 64-bit
3548 operand immP_set() %{
3549 predicate(!VM_Version::is_niagara_plus());
3550 match(ConP);
3551
3552 op_cost(5);
3553 // formats are generated automatically for constants and base registers
3554 format %{ %}
3555 interface(CONST_INTER);
3556 %}
3557
3558 // Pointer Immediate: 64-bit
3559 // From Niagara2 processors on a load should be better than materializing.
3560 operand immP_load() %{
3561 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3562 match(ConP);
3563
3564 op_cost(5);
3565 // formats are generated automatically for constants and base registers
3566 format %{ %}
3567 interface(CONST_INTER);
3568 %}
3569
3570 // Pointer Immediate: 64-bit
3571 operand immP_no_oop_cheap() %{
3572 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3573 match(ConP);
3574
3575 op_cost(5);
3576 // formats are generated automatically for constants and base registers
3577 format %{ %}
3578 interface(CONST_INTER);
3579 %}
3580 #endif
3581
3582 operand immP13() %{
3583 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3584 match(ConP);
3585 op_cost(0);
3586
3587 format %{ %}
3588 interface(CONST_INTER);
3589 %}
3590
3591 operand immP0() %{
3592 predicate(n->get_ptr() == 0);
3593 match(ConP);
3594 op_cost(0);
3595
3596 format %{ %}
3597 interface(CONST_INTER);
3598 %}
3599
3600 operand immP_poll() %{
3601 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3602 match(ConP);
3603
3604 // formats are generated automatically for constants and base registers
3605 format %{ %}
3606 interface(CONST_INTER);
3607 %}
3608
3609 // Pointer Immediate
3610 operand immN()
3611 %{
3612 match(ConN);
3613
3614 op_cost(10);
3615 format %{ %}
3616 interface(CONST_INTER);
3617 %}
3618
3619 operand immNKlass()
3620 %{
3621 match(ConNKlass);
3622
3623 op_cost(10);
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 // NULL Pointer Immediate
3629 operand immN0()
3630 %{
3631 predicate(n->get_narrowcon() == 0);
3632 match(ConN);
3633
3634 op_cost(0);
3635 format %{ %}
3636 interface(CONST_INTER);
3637 %}
3638
3639 operand immL() %{
3640 match(ConL);
3641 op_cost(40);
3642 // formats are generated automatically for constants and base registers
3643 format %{ %}
3644 interface(CONST_INTER);
3645 %}
3646
3647 operand immL0() %{
3648 predicate(n->get_long() == 0L);
3649 match(ConL);
3650 op_cost(0);
3651 // formats are generated automatically for constants and base registers
3652 format %{ %}
3653 interface(CONST_INTER);
3654 %}
3655
3656 // Integer Immediate: 5-bit
3657 operand immL5() %{
3658 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3659 match(ConL);
3660 op_cost(0);
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3664
3665 // Long Immediate: 13-bit
3666 operand immL13() %{
3667 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3668 match(ConL);
3669 op_cost(0);
3670
3671 format %{ %}
3672 interface(CONST_INTER);
3673 %}
3674
3675 // Long Immediate: 13-bit minus 7
3676 operand immL13m7() %{
3677 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3678 match(ConL);
3679 op_cost(0);
3680
3681 format %{ %}
3682 interface(CONST_INTER);
3683 %}
3684
3685 // Long Immediate: low 32-bit mask
3686 operand immL_32bits() %{
3687 predicate(n->get_long() == 0xFFFFFFFFL);
3688 match(ConL);
3689 op_cost(0);
3690
3691 format %{ %}
3692 interface(CONST_INTER);
3693 %}
3694
3695 // Long Immediate: cheap (materialize in <= 3 instructions)
3696 operand immL_cheap() %{
3697 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3698 match(ConL);
3699 op_cost(0);
3700
3701 format %{ %}
3702 interface(CONST_INTER);
3703 %}
3704
3705 // Long Immediate: expensive (materialize in > 3 instructions)
3706 operand immL_expensive() %{
3707 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3708 match(ConL);
3709 op_cost(0);
3710
3711 format %{ %}
3712 interface(CONST_INTER);
3713 %}
3714
3715 // Double Immediate
3716 operand immD() %{
3717 match(ConD);
3718
3719 op_cost(40);
3720 format %{ %}
3721 interface(CONST_INTER);
3722 %}
3723
3724 operand immD0() %{
3725 #ifdef _LP64
3726 // on 64-bit architectures this comparision is faster
3727 predicate(jlong_cast(n->getd()) == 0);
3728 #else
3729 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3730 #endif
3731 match(ConD);
3732
3733 op_cost(0);
3734 format %{ %}
3735 interface(CONST_INTER);
3736 %}
3737
3738 // Float Immediate
3739 operand immF() %{
3740 match(ConF);
3741
3742 op_cost(20);
3743 format %{ %}
3744 interface(CONST_INTER);
3745 %}
3746
3747 // Float Immediate: 0
3748 operand immF0() %{
3749 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3750 match(ConF);
3751
3752 op_cost(0);
3753 format %{ %}
3754 interface(CONST_INTER);
3755 %}
3756
3757 // Integer Register Operands
3758 // Integer Register
3759 operand iRegI() %{
3760 constraint(ALLOC_IN_RC(int_reg));
3761 match(RegI);
3762
3763 match(notemp_iRegI);
3764 match(g1RegI);
3765 match(o0RegI);
3766 match(iRegIsafe);
3767
3768 format %{ %}
3769 interface(REG_INTER);
3770 %}
3771
3772 operand notemp_iRegI() %{
3773 constraint(ALLOC_IN_RC(notemp_int_reg));
3774 match(RegI);
3775
3776 match(o0RegI);
3777
3778 format %{ %}
3779 interface(REG_INTER);
3780 %}
3781
3782 operand o0RegI() %{
3783 constraint(ALLOC_IN_RC(o0_regI));
3784 match(iRegI);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 // Pointer Register
3791 operand iRegP() %{
3792 constraint(ALLOC_IN_RC(ptr_reg));
3793 match(RegP);
3794
3795 match(lock_ptr_RegP);
3796 match(g1RegP);
3797 match(g2RegP);
3798 match(g3RegP);
3799 match(g4RegP);
3800 match(i0RegP);
3801 match(o0RegP);
3802 match(o1RegP);
3803 match(l7RegP);
3804
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3808
3809 operand sp_ptr_RegP() %{
3810 constraint(ALLOC_IN_RC(sp_ptr_reg));
3811 match(RegP);
3812 match(iRegP);
3813
3814 format %{ %}
3815 interface(REG_INTER);
3816 %}
3817
3818 operand lock_ptr_RegP() %{
3819 constraint(ALLOC_IN_RC(lock_ptr_reg));
3820 match(RegP);
3821 match(i0RegP);
3822 match(o0RegP);
3823 match(o1RegP);
3824 match(l7RegP);
3825
3826 format %{ %}
3827 interface(REG_INTER);
3828 %}
3829
3830 operand g1RegP() %{
3831 constraint(ALLOC_IN_RC(g1_regP));
3832 match(iRegP);
3833
3834 format %{ %}
3835 interface(REG_INTER);
3836 %}
3837
3838 operand g2RegP() %{
3839 constraint(ALLOC_IN_RC(g2_regP));
3840 match(iRegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand g3RegP() %{
3847 constraint(ALLOC_IN_RC(g3_regP));
3848 match(iRegP);
3849
3850 format %{ %}
3851 interface(REG_INTER);
3852 %}
3853
3854 operand g1RegI() %{
3855 constraint(ALLOC_IN_RC(g1_regI));
3856 match(iRegI);
3857
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 operand g3RegI() %{
3863 constraint(ALLOC_IN_RC(g3_regI));
3864 match(iRegI);
3865
3866 format %{ %}
3867 interface(REG_INTER);
3868 %}
3869
3870 operand g4RegI() %{
3871 constraint(ALLOC_IN_RC(g4_regI));
3872 match(iRegI);
3873
3874 format %{ %}
3875 interface(REG_INTER);
3876 %}
3877
3878 operand g4RegP() %{
3879 constraint(ALLOC_IN_RC(g4_regP));
3880 match(iRegP);
3881
3882 format %{ %}
3883 interface(REG_INTER);
3884 %}
3885
3886 operand i0RegP() %{
3887 constraint(ALLOC_IN_RC(i0_regP));
3888 match(iRegP);
3889
3890 format %{ %}
3891 interface(REG_INTER);
3892 %}
3893
3894 operand o0RegP() %{
3895 constraint(ALLOC_IN_RC(o0_regP));
3896 match(iRegP);
3897
3898 format %{ %}
3899 interface(REG_INTER);
3900 %}
3901
3902 operand o1RegP() %{
3903 constraint(ALLOC_IN_RC(o1_regP));
3904 match(iRegP);
3905
3906 format %{ %}
3907 interface(REG_INTER);
3908 %}
3909
3910 operand o2RegP() %{
3911 constraint(ALLOC_IN_RC(o2_regP));
3912 match(iRegP);
3913
3914 format %{ %}
3915 interface(REG_INTER);
3916 %}
3917
3918 operand o7RegP() %{
3919 constraint(ALLOC_IN_RC(o7_regP));
3920 match(iRegP);
3921
3922 format %{ %}
3923 interface(REG_INTER);
3924 %}
3925
3926 operand l7RegP() %{
3927 constraint(ALLOC_IN_RC(l7_regP));
3928 match(iRegP);
3929
3930 format %{ %}
3931 interface(REG_INTER);
3932 %}
3933
3934 operand o7RegI() %{
3935 constraint(ALLOC_IN_RC(o7_regI));
3936 match(iRegI);
3937
3938 format %{ %}
3939 interface(REG_INTER);
3940 %}
3941
3942 operand iRegN() %{
3943 constraint(ALLOC_IN_RC(int_reg));
3944 match(RegN);
3945
3946 format %{ %}
3947 interface(REG_INTER);
3948 %}
3949
3950 // Long Register
3951 operand iRegL() %{
3952 constraint(ALLOC_IN_RC(long_reg));
3953 match(RegL);
3954
3955 format %{ %}
3956 interface(REG_INTER);
3957 %}
3958
3959 operand o2RegL() %{
3960 constraint(ALLOC_IN_RC(o2_regL));
3961 match(iRegL);
3962
3963 format %{ %}
3964 interface(REG_INTER);
3965 %}
3966
3967 operand o7RegL() %{
3968 constraint(ALLOC_IN_RC(o7_regL));
3969 match(iRegL);
3970
3971 format %{ %}
3972 interface(REG_INTER);
3973 %}
3974
3975 operand g1RegL() %{
3976 constraint(ALLOC_IN_RC(g1_regL));
3977 match(iRegL);
3978
3979 format %{ %}
3980 interface(REG_INTER);
3981 %}
3982
3983 operand g3RegL() %{
3984 constraint(ALLOC_IN_RC(g3_regL));
3985 match(iRegL);
3986
3987 format %{ %}
3988 interface(REG_INTER);
3989 %}
3990
3991 // Int Register safe
3992 // This is 64bit safe
3993 operand iRegIsafe() %{
3994 constraint(ALLOC_IN_RC(long_reg));
3995
3996 match(iRegI);
3997
3998 format %{ %}
3999 interface(REG_INTER);
4000 %}
4001
4002 // Condition Code Flag Register
4003 operand flagsReg() %{
4004 constraint(ALLOC_IN_RC(int_flags));
4005 match(RegFlags);
4006
4007 format %{ "ccr" %} // both ICC and XCC
4008 interface(REG_INTER);
4009 %}
4010
4011 // Condition Code Register, unsigned comparisons.
4012 operand flagsRegU() %{
4013 constraint(ALLOC_IN_RC(int_flags));
4014 match(RegFlags);
4015
4016 format %{ "icc_U" %}
4017 interface(REG_INTER);
4018 %}
4019
4020 // Condition Code Register, pointer comparisons.
4021 operand flagsRegP() %{
4022 constraint(ALLOC_IN_RC(int_flags));
4023 match(RegFlags);
4024
4025 #ifdef _LP64
4026 format %{ "xcc_P" %}
4027 #else
4028 format %{ "icc_P" %}
4029 #endif
4030 interface(REG_INTER);
4031 %}
4032
4033 // Condition Code Register, long comparisons.
4034 operand flagsRegL() %{
4035 constraint(ALLOC_IN_RC(int_flags));
4036 match(RegFlags);
4037
4038 format %{ "xcc_L" %}
4039 interface(REG_INTER);
4040 %}
4041
4042 // Condition Code Register, floating comparisons, unordered same as "less".
4043 operand flagsRegF() %{
4044 constraint(ALLOC_IN_RC(float_flags));
4045 match(RegFlags);
4046 match(flagsRegF0);
4047
4048 format %{ %}
4049 interface(REG_INTER);
4050 %}
4051
4052 operand flagsRegF0() %{
4053 constraint(ALLOC_IN_RC(float_flag0));
4054 match(RegFlags);
4055
4056 format %{ %}
4057 interface(REG_INTER);
4058 %}
4059
4060
4061 // Condition Code Flag Register used by long compare
4062 operand flagsReg_long_LTGE() %{
4063 constraint(ALLOC_IN_RC(int_flags));
4064 match(RegFlags);
4065 format %{ "icc_LTGE" %}
4066 interface(REG_INTER);
4067 %}
4068 operand flagsReg_long_EQNE() %{
4069 constraint(ALLOC_IN_RC(int_flags));
4070 match(RegFlags);
4071 format %{ "icc_EQNE" %}
4072 interface(REG_INTER);
4073 %}
4074 operand flagsReg_long_LEGT() %{
4075 constraint(ALLOC_IN_RC(int_flags));
4076 match(RegFlags);
4077 format %{ "icc_LEGT" %}
4078 interface(REG_INTER);
4079 %}
4080
4081
4082 operand regD() %{
4083 constraint(ALLOC_IN_RC(dflt_reg));
4084 match(RegD);
4085
4086 match(regD_low);
4087
4088 format %{ %}
4089 interface(REG_INTER);
4090 %}
4091
4092 operand regF() %{
4093 constraint(ALLOC_IN_RC(sflt_reg));
4094 match(RegF);
4095
4096 format %{ %}
4097 interface(REG_INTER);
4098 %}
4099
4100 operand regD_low() %{
4101 constraint(ALLOC_IN_RC(dflt_low_reg));
4102 match(regD);
4103
4104 format %{ %}
4105 interface(REG_INTER);
4106 %}
4107
4108 // Special Registers
4109
4110 // Method Register
4111 operand inline_cache_regP(iRegP reg) %{
4112 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4113 match(reg);
4114 format %{ %}
4115 interface(REG_INTER);
4116 %}
4117
4118 operand interpreter_method_oop_regP(iRegP reg) %{
4119 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4120 match(reg);
4121 format %{ %}
4122 interface(REG_INTER);
4123 %}
4124
4125
4126 //----------Complex Operands---------------------------------------------------
4127 // Indirect Memory Reference
4128 operand indirect(sp_ptr_RegP reg) %{
4129 constraint(ALLOC_IN_RC(sp_ptr_reg));
4130 match(reg);
4131
4132 op_cost(100);
4133 format %{ "[$reg]" %}
4134 interface(MEMORY_INTER) %{
4135 base($reg);
4136 index(0x0);
4137 scale(0x0);
4138 disp(0x0);
4139 %}
4140 %}
4141
4142 // Indirect with simm13 Offset
4143 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4144 constraint(ALLOC_IN_RC(sp_ptr_reg));
4145 match(AddP reg offset);
4146
4147 op_cost(100);
4148 format %{ "[$reg + $offset]" %}
4149 interface(MEMORY_INTER) %{
4150 base($reg);
4151 index(0x0);
4152 scale(0x0);
4153 disp($offset);
4154 %}
4155 %}
4156
4157 // Indirect with simm13 Offset minus 7
4158 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4159 constraint(ALLOC_IN_RC(sp_ptr_reg));
4160 match(AddP reg offset);
4161
4162 op_cost(100);
4163 format %{ "[$reg + $offset]" %}
4164 interface(MEMORY_INTER) %{
4165 base($reg);
4166 index(0x0);
4167 scale(0x0);
4168 disp($offset);
4169 %}
4170 %}
4171
4172 // Note: Intel has a swapped version also, like this:
4173 //operand indOffsetX(iRegI reg, immP offset) %{
4174 // constraint(ALLOC_IN_RC(int_reg));
4175 // match(AddP offset reg);
4176 //
4177 // op_cost(100);
4178 // format %{ "[$reg + $offset]" %}
4179 // interface(MEMORY_INTER) %{
4180 // base($reg);
4181 // index(0x0);
4182 // scale(0x0);
4183 // disp($offset);
4184 // %}
4185 //%}
4186 //// However, it doesn't make sense for SPARC, since
4187 // we have no particularly good way to embed oops in
4188 // single instructions.
4189
4190 // Indirect with Register Index
4191 operand indIndex(iRegP addr, iRegX index) %{
4192 constraint(ALLOC_IN_RC(ptr_reg));
4193 match(AddP addr index);
4194
4195 op_cost(100);
4196 format %{ "[$addr + $index]" %}
4197 interface(MEMORY_INTER) %{
4198 base($addr);
4199 index($index);
4200 scale(0x0);
4201 disp(0x0);
4202 %}
4203 %}
4204
4205 //----------Special Memory Operands--------------------------------------------
4206 // Stack Slot Operand - This operand is used for loading and storing temporary
4207 // values on the stack where a match requires a value to
4208 // flow through memory.
4209 operand stackSlotI(sRegI reg) %{
4210 constraint(ALLOC_IN_RC(stack_slots));
4211 op_cost(100);
4212 //match(RegI);
4213 format %{ "[$reg]" %}
4214 interface(MEMORY_INTER) %{
4215 base(0xE); // R_SP
4216 index(0x0);
4217 scale(0x0);
4218 disp($reg); // Stack Offset
4219 %}
4220 %}
4221
4222 operand stackSlotP(sRegP reg) %{
4223 constraint(ALLOC_IN_RC(stack_slots));
4224 op_cost(100);
4225 //match(RegP);
4226 format %{ "[$reg]" %}
4227 interface(MEMORY_INTER) %{
4228 base(0xE); // R_SP
4229 index(0x0);
4230 scale(0x0);
4231 disp($reg); // Stack Offset
4232 %}
4233 %}
4234
4235 operand stackSlotF(sRegF reg) %{
4236 constraint(ALLOC_IN_RC(stack_slots));
4237 op_cost(100);
4238 //match(RegF);
4239 format %{ "[$reg]" %}
4240 interface(MEMORY_INTER) %{
4241 base(0xE); // R_SP
4242 index(0x0);
4243 scale(0x0);
4244 disp($reg); // Stack Offset
4245 %}
4246 %}
4247 operand stackSlotD(sRegD reg) %{
4248 constraint(ALLOC_IN_RC(stack_slots));
4249 op_cost(100);
4250 //match(RegD);
4251 format %{ "[$reg]" %}
4252 interface(MEMORY_INTER) %{
4253 base(0xE); // R_SP
4254 index(0x0);
4255 scale(0x0);
4256 disp($reg); // Stack Offset
4257 %}
4258 %}
4259 operand stackSlotL(sRegL reg) %{
4260 constraint(ALLOC_IN_RC(stack_slots));
4261 op_cost(100);
4262 //match(RegL);
4263 format %{ "[$reg]" %}
4264 interface(MEMORY_INTER) %{
4265 base(0xE); // R_SP
4266 index(0x0);
4267 scale(0x0);
4268 disp($reg); // Stack Offset
4269 %}
4270 %}
4271
4272 // Operands for expressing Control Flow
4273 // NOTE: Label is a predefined operand which should not be redefined in
4274 // the AD file. It is generically handled within the ADLC.
4275
4276 //----------Conditional Branch Operands----------------------------------------
4277 // Comparison Op - This is the operation of the comparison, and is limited to
4278 // the following set of codes:
4279 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4280 //
4281 // Other attributes of the comparison, such as unsignedness, are specified
4282 // by the comparison instruction that sets a condition code flags register.
4283 // That result is represented by a flags operand whose subtype is appropriate
4284 // to the unsignedness (etc.) of the comparison.
4285 //
4286 // Later, the instruction which matches both the Comparison Op (a Bool) and
4287 // the flags (produced by the Cmp) specifies the coding of the comparison op
4288 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4289
4290 operand cmpOp() %{
4291 match(Bool);
4292
4293 format %{ "" %}
4294 interface(COND_INTER) %{
4295 equal(0x1);
4296 not_equal(0x9);
4297 less(0x3);
4298 greater_equal(0xB);
4299 less_equal(0x2);
4300 greater(0xA);
4301 %}
4302 %}
4303
4304 // Comparison Op, unsigned
4305 operand cmpOpU() %{
4306 match(Bool);
4307
4308 format %{ "u" %}
4309 interface(COND_INTER) %{
4310 equal(0x1);
4311 not_equal(0x9);
4312 less(0x5);
4313 greater_equal(0xD);
4314 less_equal(0x4);
4315 greater(0xC);
4316 %}
4317 %}
4318
4319 // Comparison Op, pointer (same as unsigned)
4320 operand cmpOpP() %{
4321 match(Bool);
4322
4323 format %{ "p" %}
4324 interface(COND_INTER) %{
4325 equal(0x1);
4326 not_equal(0x9);
4327 less(0x5);
4328 greater_equal(0xD);
4329 less_equal(0x4);
4330 greater(0xC);
4331 %}
4332 %}
4333
4334 // Comparison Op, branch-register encoding
4335 operand cmpOp_reg() %{
4336 match(Bool);
4337
4338 format %{ "" %}
4339 interface(COND_INTER) %{
4340 equal (0x1);
4341 not_equal (0x5);
4342 less (0x3);
4343 greater_equal(0x7);
4344 less_equal (0x2);
4345 greater (0x6);
4346 %}
4347 %}
4348
4349 // Comparison Code, floating, unordered same as less
4350 operand cmpOpF() %{
4351 match(Bool);
4352
4353 format %{ "fl" %}
4354 interface(COND_INTER) %{
4355 equal(0x9);
4356 not_equal(0x1);
4357 less(0x3);
4358 greater_equal(0xB);
4359 less_equal(0xE);
4360 greater(0x6);
4361 %}
4362 %}
4363
4364 // Used by long compare
4365 operand cmpOp_commute() %{
4366 match(Bool);
4367
4368 format %{ "" %}
4369 interface(COND_INTER) %{
4370 equal(0x1);
4371 not_equal(0x9);
4372 less(0xA);
4373 greater_equal(0x2);
4374 less_equal(0xB);
4375 greater(0x3);
4376 %}
4377 %}
4378
4379 //----------OPERAND CLASSES----------------------------------------------------
4380 // Operand Classes are groups of operands that are used to simplify
4381 // instruction definitions by not requiring the AD writer to specify separate
4382 // instructions for every form of operand when the instruction accepts
4383 // multiple operand types with the same basic encoding and format. The classic
4384 // case of this is memory operands.
4385 opclass memory( indirect, indOffset13, indIndex );
4386 opclass indIndexMemory( indIndex );
4387
4388 //----------PIPELINE-----------------------------------------------------------
4389 pipeline %{
4390
4391 //----------ATTRIBUTES---------------------------------------------------------
4392 attributes %{
4393 fixed_size_instructions; // Fixed size instructions
4394 branch_has_delay_slot; // Branch has delay slot following
4395 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4396 instruction_unit_size = 4; // An instruction is 4 bytes long
4397 instruction_fetch_unit_size = 16; // The processor fetches one line
4398 instruction_fetch_units = 1; // of 16 bytes
4399
4400 // List of nop instructions
4401 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4402 %}
4403
4404 //----------RESOURCES----------------------------------------------------------
4405 // Resources are the functional units available to the machine
4406 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4407
4408 //----------PIPELINE DESCRIPTION-----------------------------------------------
4409 // Pipeline Description specifies the stages in the machine's pipeline
4410
4411 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4412
4413 //----------PIPELINE CLASSES---------------------------------------------------
4414 // Pipeline Classes describe the stages in which input and output are
4415 // referenced by the hardware pipeline.
4416
4417 // Integer ALU reg-reg operation
4418 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4419 single_instruction;
4420 dst : E(write);
4421 src1 : R(read);
4422 src2 : R(read);
4423 IALU : R;
4424 %}
4425
4426 // Integer ALU reg-reg long operation
4427 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4428 instruction_count(2);
4429 dst : E(write);
4430 src1 : R(read);
4431 src2 : R(read);
4432 IALU : R;
4433 IALU : R;
4434 %}
4435
4436 // Integer ALU reg-reg long dependent operation
4437 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4438 instruction_count(1); multiple_bundles;
4439 dst : E(write);
4440 src1 : R(read);
4441 src2 : R(read);
4442 cr : E(write);
4443 IALU : R(2);
4444 %}
4445
4446 // Integer ALU reg-imm operaion
4447 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4448 single_instruction;
4449 dst : E(write);
4450 src1 : R(read);
4451 IALU : R;
4452 %}
4453
4454 // Integer ALU reg-reg operation with condition code
4455 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4456 single_instruction;
4457 dst : E(write);
4458 cr : E(write);
4459 src1 : R(read);
4460 src2 : R(read);
4461 IALU : R;
4462 %}
4463
4464 // Integer ALU reg-imm operation with condition code
4465 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4466 single_instruction;
4467 dst : E(write);
4468 cr : E(write);
4469 src1 : R(read);
4470 IALU : R;
4471 %}
4472
4473 // Integer ALU zero-reg operation
4474 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4475 single_instruction;
4476 dst : E(write);
4477 src2 : R(read);
4478 IALU : R;
4479 %}
4480
4481 // Integer ALU zero-reg operation with condition code only
4482 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4483 single_instruction;
4484 cr : E(write);
4485 src : R(read);
4486 IALU : R;
4487 %}
4488
4489 // Integer ALU reg-reg operation with condition code only
4490 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4491 single_instruction;
4492 cr : E(write);
4493 src1 : R(read);
4494 src2 : R(read);
4495 IALU : R;
4496 %}
4497
4498 // Integer ALU reg-imm operation with condition code only
4499 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4500 single_instruction;
4501 cr : E(write);
4502 src1 : R(read);
4503 IALU : R;
4504 %}
4505
4506 // Integer ALU reg-reg-zero operation with condition code only
4507 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4508 single_instruction;
4509 cr : E(write);
4510 src1 : R(read);
4511 src2 : R(read);
4512 IALU : R;
4513 %}
4514
4515 // Integer ALU reg-imm-zero operation with condition code only
4516 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4517 single_instruction;
4518 cr : E(write);
4519 src1 : R(read);
4520 IALU : R;
4521 %}
4522
4523 // Integer ALU reg-reg operation with condition code, src1 modified
4524 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4525 single_instruction;
4526 cr : E(write);
4527 src1 : E(write);
4528 src1 : R(read);
4529 src2 : R(read);
4530 IALU : R;
4531 %}
4532
4533 // Integer ALU reg-imm operation with condition code, src1 modified
4534 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4535 single_instruction;
4536 cr : E(write);
4537 src1 : E(write);
4538 src1 : R(read);
4539 IALU : R;
4540 %}
4541
4542 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4543 multiple_bundles;
4544 dst : E(write)+4;
4545 cr : E(write);
4546 src1 : R(read);
4547 src2 : R(read);
4548 IALU : R(3);
4549 BR : R(2);
4550 %}
4551
4552 // Integer ALU operation
4553 pipe_class ialu_none(iRegI dst) %{
4554 single_instruction;
4555 dst : E(write);
4556 IALU : R;
4557 %}
4558
4559 // Integer ALU reg operation
4560 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4561 single_instruction; may_have_no_code;
4562 dst : E(write);
4563 src : R(read);
4564 IALU : R;
4565 %}
4566
4567 // Integer ALU reg conditional operation
4568 // This instruction has a 1 cycle stall, and cannot execute
4569 // in the same cycle as the instruction setting the condition
4570 // code. We kludge this by pretending to read the condition code
4571 // 1 cycle earlier, and by marking the functional units as busy
4572 // for 2 cycles with the result available 1 cycle later than
4573 // is really the case.
4574 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4575 single_instruction;
4576 op2_out : C(write);
4577 op1 : R(read);
4578 cr : R(read); // This is really E, with a 1 cycle stall
4579 BR : R(2);
4580 MS : R(2);
4581 %}
4582
4583 #ifdef _LP64
4584 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4585 instruction_count(1); multiple_bundles;
4586 dst : C(write)+1;
4587 src : R(read)+1;
4588 IALU : R(1);
4589 BR : E(2);
4590 MS : E(2);
4591 %}
4592 #endif
4593
4594 // Integer ALU reg operation
4595 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4596 single_instruction; may_have_no_code;
4597 dst : E(write);
4598 src : R(read);
4599 IALU : R;
4600 %}
4601 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4602 single_instruction; may_have_no_code;
4603 dst : E(write);
4604 src : R(read);
4605 IALU : R;
4606 %}
4607
4608 // Two integer ALU reg operations
4609 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4610 instruction_count(2);
4611 dst : E(write);
4612 src : R(read);
4613 A0 : R;
4614 A1 : R;
4615 %}
4616
4617 // Two integer ALU reg operations
4618 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4619 instruction_count(2); may_have_no_code;
4620 dst : E(write);
4621 src : R(read);
4622 A0 : R;
4623 A1 : R;
4624 %}
4625
4626 // Integer ALU imm operation
4627 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4628 single_instruction;
4629 dst : E(write);
4630 IALU : R;
4631 %}
4632
4633 // Integer ALU reg-reg with carry operation
4634 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4635 single_instruction;
4636 dst : E(write);
4637 src1 : R(read);
4638 src2 : R(read);
4639 IALU : R;
4640 %}
4641
4642 // Integer ALU cc operation
4643 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4644 single_instruction;
4645 dst : E(write);
4646 cc : R(read);
4647 IALU : R;
4648 %}
4649
4650 // Integer ALU cc / second IALU operation
4651 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4652 instruction_count(1); multiple_bundles;
4653 dst : E(write)+1;
4654 src : R(read);
4655 IALU : R;
4656 %}
4657
4658 // Integer ALU cc / second IALU operation
4659 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4660 instruction_count(1); multiple_bundles;
4661 dst : E(write)+1;
4662 p : R(read);
4663 q : R(read);
4664 IALU : R;
4665 %}
4666
4667 // Integer ALU hi-lo-reg operation
4668 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4669 instruction_count(1); multiple_bundles;
4670 dst : E(write)+1;
4671 IALU : R(2);
4672 %}
4673
4674 // Float ALU hi-lo-reg operation (with temp)
4675 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4676 instruction_count(1); multiple_bundles;
4677 dst : E(write)+1;
4678 IALU : R(2);
4679 %}
4680
4681 // Long Constant
4682 pipe_class loadConL( iRegL dst, immL src ) %{
4683 instruction_count(2); multiple_bundles;
4684 dst : E(write)+1;
4685 IALU : R(2);
4686 IALU : R(2);
4687 %}
4688
4689 // Pointer Constant
4690 pipe_class loadConP( iRegP dst, immP src ) %{
4691 instruction_count(0); multiple_bundles;
4692 fixed_latency(6);
4693 %}
4694
4695 // Polling Address
4696 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4697 #ifdef _LP64
4698 instruction_count(0); multiple_bundles;
4699 fixed_latency(6);
4700 #else
4701 dst : E(write);
4702 IALU : R;
4703 #endif
4704 %}
4705
4706 // Long Constant small
4707 pipe_class loadConLlo( iRegL dst, immL src ) %{
4708 instruction_count(2);
4709 dst : E(write);
4710 IALU : R;
4711 IALU : R;
4712 %}
4713
4714 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4715 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4716 instruction_count(1); multiple_bundles;
4717 src : R(read);
4718 dst : M(write)+1;
4719 IALU : R;
4720 MS : E;
4721 %}
4722
4723 // Integer ALU nop operation
4724 pipe_class ialu_nop() %{
4725 single_instruction;
4726 IALU : R;
4727 %}
4728
4729 // Integer ALU nop operation
4730 pipe_class ialu_nop_A0() %{
4731 single_instruction;
4732 A0 : R;
4733 %}
4734
4735 // Integer ALU nop operation
4736 pipe_class ialu_nop_A1() %{
4737 single_instruction;
4738 A1 : R;
4739 %}
4740
4741 // Integer Multiply reg-reg operation
4742 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4743 single_instruction;
4744 dst : E(write);
4745 src1 : R(read);
4746 src2 : R(read);
4747 MS : R(5);
4748 %}
4749
4750 // Integer Multiply reg-imm operation
4751 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4752 single_instruction;
4753 dst : E(write);
4754 src1 : R(read);
4755 MS : R(5);
4756 %}
4757
4758 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4759 single_instruction;
4760 dst : E(write)+4;
4761 src1 : R(read);
4762 src2 : R(read);
4763 MS : R(6);
4764 %}
4765
4766 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4767 single_instruction;
4768 dst : E(write)+4;
4769 src1 : R(read);
4770 MS : R(6);
4771 %}
4772
4773 // Integer Divide reg-reg
4774 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4775 instruction_count(1); multiple_bundles;
4776 dst : E(write);
4777 temp : E(write);
4778 src1 : R(read);
4779 src2 : R(read);
4780 temp : R(read);
4781 MS : R(38);
4782 %}
4783
4784 // Integer Divide reg-imm
4785 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4786 instruction_count(1); multiple_bundles;
4787 dst : E(write);
4788 temp : E(write);
4789 src1 : R(read);
4790 temp : R(read);
4791 MS : R(38);
4792 %}
4793
4794 // Long Divide
4795 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4796 dst : E(write)+71;
4797 src1 : R(read);
4798 src2 : R(read)+1;
4799 MS : R(70);
4800 %}
4801
4802 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4803 dst : E(write)+71;
4804 src1 : R(read);
4805 MS : R(70);
4806 %}
4807
4808 // Floating Point Add Float
4809 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4810 single_instruction;
4811 dst : X(write);
4812 src1 : E(read);
4813 src2 : E(read);
4814 FA : R;
4815 %}
4816
4817 // Floating Point Add Double
4818 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4819 single_instruction;
4820 dst : X(write);
4821 src1 : E(read);
4822 src2 : E(read);
4823 FA : R;
4824 %}
4825
4826 // Floating Point Conditional Move based on integer flags
4827 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4828 single_instruction;
4829 dst : X(write);
4830 src : E(read);
4831 cr : R(read);
4832 FA : R(2);
4833 BR : R(2);
4834 %}
4835
4836 // Floating Point Conditional Move based on integer flags
4837 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4838 single_instruction;
4839 dst : X(write);
4840 src : E(read);
4841 cr : R(read);
4842 FA : R(2);
4843 BR : R(2);
4844 %}
4845
4846 // Floating Point Multiply Float
4847 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4848 single_instruction;
4849 dst : X(write);
4850 src1 : E(read);
4851 src2 : E(read);
4852 FM : R;
4853 %}
4854
4855 // Floating Point Multiply Double
4856 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4857 single_instruction;
4858 dst : X(write);
4859 src1 : E(read);
4860 src2 : E(read);
4861 FM : R;
4862 %}
4863
4864 // Floating Point Divide Float
4865 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4866 single_instruction;
4867 dst : X(write);
4868 src1 : E(read);
4869 src2 : E(read);
4870 FM : R;
4871 FDIV : C(14);
4872 %}
4873
4874 // Floating Point Divide Double
4875 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4876 single_instruction;
4877 dst : X(write);
4878 src1 : E(read);
4879 src2 : E(read);
4880 FM : R;
4881 FDIV : C(17);
4882 %}
4883
4884 // Floating Point Move/Negate/Abs Float
4885 pipe_class faddF_reg(regF dst, regF src) %{
4886 single_instruction;
4887 dst : W(write);
4888 src : E(read);
4889 FA : R(1);
4890 %}
4891
4892 // Floating Point Move/Negate/Abs Double
4893 pipe_class faddD_reg(regD dst, regD src) %{
4894 single_instruction;
4895 dst : W(write);
4896 src : E(read);
4897 FA : R;
4898 %}
4899
4900 // Floating Point Convert F->D
4901 pipe_class fcvtF2D(regD dst, regF src) %{
4902 single_instruction;
4903 dst : X(write);
4904 src : E(read);
4905 FA : R;
4906 %}
4907
4908 // Floating Point Convert I->D
4909 pipe_class fcvtI2D(regD dst, regF src) %{
4910 single_instruction;
4911 dst : X(write);
4912 src : E(read);
4913 FA : R;
4914 %}
4915
4916 // Floating Point Convert LHi->D
4917 pipe_class fcvtLHi2D(regD dst, regD src) %{
4918 single_instruction;
4919 dst : X(write);
4920 src : E(read);
4921 FA : R;
4922 %}
4923
4924 // Floating Point Convert L->D
4925 pipe_class fcvtL2D(regD dst, regF src) %{
4926 single_instruction;
4927 dst : X(write);
4928 src : E(read);
4929 FA : R;
4930 %}
4931
4932 // Floating Point Convert L->F
4933 pipe_class fcvtL2F(regD dst, regF src) %{
4934 single_instruction;
4935 dst : X(write);
4936 src : E(read);
4937 FA : R;
4938 %}
4939
4940 // Floating Point Convert D->F
4941 pipe_class fcvtD2F(regD dst, regF src) %{
4942 single_instruction;
4943 dst : X(write);
4944 src : E(read);
4945 FA : R;
4946 %}
4947
4948 // Floating Point Convert I->L
4949 pipe_class fcvtI2L(regD dst, regF src) %{
4950 single_instruction;
4951 dst : X(write);
4952 src : E(read);
4953 FA : R;
4954 %}
4955
4956 // Floating Point Convert D->F
4957 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4958 instruction_count(1); multiple_bundles;
4959 dst : X(write)+6;
4960 src : E(read);
4961 FA : R;
4962 %}
4963
4964 // Floating Point Convert D->L
4965 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4966 instruction_count(1); multiple_bundles;
4967 dst : X(write)+6;
4968 src : E(read);
4969 FA : R;
4970 %}
4971
4972 // Floating Point Convert F->I
4973 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4974 instruction_count(1); multiple_bundles;
4975 dst : X(write)+6;
4976 src : E(read);
4977 FA : R;
4978 %}
4979
4980 // Floating Point Convert F->L
4981 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4982 instruction_count(1); multiple_bundles;
4983 dst : X(write)+6;
4984 src : E(read);
4985 FA : R;
4986 %}
4987
4988 // Floating Point Convert I->F
4989 pipe_class fcvtI2F(regF dst, regF src) %{
4990 single_instruction;
4991 dst : X(write);
4992 src : E(read);
4993 FA : R;
4994 %}
4995
4996 // Floating Point Compare
4997 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4998 single_instruction;
4999 cr : X(write);
5000 src1 : E(read);
5001 src2 : E(read);
5002 FA : R;
5003 %}
5004
5005 // Floating Point Compare
5006 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5007 single_instruction;
5008 cr : X(write);
5009 src1 : E(read);
5010 src2 : E(read);
5011 FA : R;
5012 %}
5013
5014 // Floating Add Nop
5015 pipe_class fadd_nop() %{
5016 single_instruction;
5017 FA : R;
5018 %}
5019
5020 // Integer Store to Memory
5021 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5022 single_instruction;
5023 mem : R(read);
5024 src : C(read);
5025 MS : R;
5026 %}
5027
5028 // Integer Store to Memory
5029 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5030 single_instruction;
5031 mem : R(read);
5032 src : C(read);
5033 MS : R;
5034 %}
5035
5036 // Integer Store Zero to Memory
5037 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5038 single_instruction;
5039 mem : R(read);
5040 MS : R;
5041 %}
5042
5043 // Special Stack Slot Store
5044 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5045 single_instruction;
5046 stkSlot : R(read);
5047 src : C(read);
5048 MS : R;
5049 %}
5050
5051 // Special Stack Slot Store
5052 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5053 instruction_count(2); multiple_bundles;
5054 stkSlot : R(read);
5055 src : C(read);
5056 MS : R(2);
5057 %}
5058
5059 // Float Store
5060 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5061 single_instruction;
5062 mem : R(read);
5063 src : C(read);
5064 MS : R;
5065 %}
5066
5067 // Float Store
5068 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5069 single_instruction;
5070 mem : R(read);
5071 MS : R;
5072 %}
5073
5074 // Double Store
5075 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5076 instruction_count(1);
5077 mem : R(read);
5078 src : C(read);
5079 MS : R;
5080 %}
5081
5082 // Double Store
5083 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5084 single_instruction;
5085 mem : R(read);
5086 MS : R;
5087 %}
5088
5089 // Special Stack Slot Float Store
5090 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5091 single_instruction;
5092 stkSlot : R(read);
5093 src : C(read);
5094 MS : R;
5095 %}
5096
5097 // Special Stack Slot Double Store
5098 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5099 single_instruction;
5100 stkSlot : R(read);
5101 src : C(read);
5102 MS : R;
5103 %}
5104
5105 // Integer Load (when sign bit propagation not needed)
5106 pipe_class iload_mem(iRegI dst, memory mem) %{
5107 single_instruction;
5108 mem : R(read);
5109 dst : C(write);
5110 MS : R;
5111 %}
5112
5113 // Integer Load from stack operand
5114 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5115 single_instruction;
5116 mem : R(read);
5117 dst : C(write);
5118 MS : R;
5119 %}
5120
5121 // Integer Load (when sign bit propagation or masking is needed)
5122 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5123 single_instruction;
5124 mem : R(read);
5125 dst : M(write);
5126 MS : R;
5127 %}
5128
5129 // Float Load
5130 pipe_class floadF_mem(regF dst, memory mem) %{
5131 single_instruction;
5132 mem : R(read);
5133 dst : M(write);
5134 MS : R;
5135 %}
5136
5137 // Float Load
5138 pipe_class floadD_mem(regD dst, memory mem) %{
5139 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5140 mem : R(read);
5141 dst : M(write);
5142 MS : R;
5143 %}
5144
5145 // Float Load
5146 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5147 single_instruction;
5148 stkSlot : R(read);
5149 dst : M(write);
5150 MS : R;
5151 %}
5152
5153 // Float Load
5154 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5155 single_instruction;
5156 stkSlot : R(read);
5157 dst : M(write);
5158 MS : R;
5159 %}
5160
5161 // Memory Nop
5162 pipe_class mem_nop() %{
5163 single_instruction;
5164 MS : R;
5165 %}
5166
5167 pipe_class sethi(iRegP dst, immI src) %{
5168 single_instruction;
5169 dst : E(write);
5170 IALU : R;
5171 %}
5172
5173 pipe_class loadPollP(iRegP poll) %{
5174 single_instruction;
5175 poll : R(read);
5176 MS : R;
5177 %}
5178
5179 pipe_class br(Universe br, label labl) %{
5180 single_instruction_with_delay_slot;
5181 BR : R;
5182 %}
5183
5184 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5185 single_instruction_with_delay_slot;
5186 cr : E(read);
5187 BR : R;
5188 %}
5189
5190 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5191 single_instruction_with_delay_slot;
5192 op1 : E(read);
5193 BR : R;
5194 MS : R;
5195 %}
5196
5197 // Compare and branch
5198 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5199 instruction_count(2); has_delay_slot;
5200 cr : E(write);
5201 src1 : R(read);
5202 src2 : R(read);
5203 IALU : R;
5204 BR : R;
5205 %}
5206
5207 // Compare and branch
5208 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5209 instruction_count(2); has_delay_slot;
5210 cr : E(write);
5211 src1 : R(read);
5212 IALU : R;
5213 BR : R;
5214 %}
5215
5216 // Compare and branch using cbcond
5217 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5218 single_instruction;
5219 src1 : E(read);
5220 src2 : E(read);
5221 IALU : R;
5222 BR : R;
5223 %}
5224
5225 // Compare and branch using cbcond
5226 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5227 single_instruction;
5228 src1 : E(read);
5229 IALU : R;
5230 BR : R;
5231 %}
5232
5233 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5234 single_instruction_with_delay_slot;
5235 cr : E(read);
5236 BR : R;
5237 %}
5238
5239 pipe_class br_nop() %{
5240 single_instruction;
5241 BR : R;
5242 %}
5243
5244 pipe_class simple_call(method meth) %{
5245 instruction_count(2); multiple_bundles; force_serialization;
5246 fixed_latency(100);
5247 BR : R(1);
5248 MS : R(1);
5249 A0 : R(1);
5250 %}
5251
5252 pipe_class compiled_call(method meth) %{
5253 instruction_count(1); multiple_bundles; force_serialization;
5254 fixed_latency(100);
5255 MS : R(1);
5256 %}
5257
5258 pipe_class call(method meth) %{
5259 instruction_count(0); multiple_bundles; force_serialization;
5260 fixed_latency(100);
5261 %}
5262
5263 pipe_class tail_call(Universe ignore, label labl) %{
5264 single_instruction; has_delay_slot;
5265 fixed_latency(100);
5266 BR : R(1);
5267 MS : R(1);
5268 %}
5269
5270 pipe_class ret(Universe ignore) %{
5271 single_instruction; has_delay_slot;
5272 BR : R(1);
5273 MS : R(1);
5274 %}
5275
5276 pipe_class ret_poll(g3RegP poll) %{
5277 instruction_count(3); has_delay_slot;
5278 poll : E(read);
5279 MS : R;
5280 %}
5281
5282 // The real do-nothing guy
5283 pipe_class empty( ) %{
5284 instruction_count(0);
5285 %}
5286
5287 pipe_class long_memory_op() %{
5288 instruction_count(0); multiple_bundles; force_serialization;
5289 fixed_latency(25);
5290 MS : R(1);
5291 %}
5292
5293 // Check-cast
5294 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5295 array : R(read);
5296 match : R(read);
5297 IALU : R(2);
5298 BR : R(2);
5299 MS : R;
5300 %}
5301
5302 // Convert FPU flags into +1,0,-1
5303 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5304 src1 : E(read);
5305 src2 : E(read);
5306 dst : E(write);
5307 FA : R;
5308 MS : R(2);
5309 BR : R(2);
5310 %}
5311
5312 // Compare for p < q, and conditionally add y
5313 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5314 p : E(read);
5315 q : E(read);
5316 y : E(read);
5317 IALU : R(3)
5318 %}
5319
5320 // Perform a compare, then move conditionally in a branch delay slot.
5321 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5322 src2 : E(read);
5323 srcdst : E(read);
5324 IALU : R;
5325 BR : R;
5326 %}
5327
5328 // Define the class for the Nop node
5329 define %{
5330 MachNop = ialu_nop;
5331 %}
5332
5333 %}
5334
5335 //----------INSTRUCTIONS-------------------------------------------------------
5336
5337 //------------Special Stack Slot instructions - no match rules-----------------
5338 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5339 // No match rule to avoid chain rule match.
5340 effect(DEF dst, USE src);
5341 ins_cost(MEMORY_REF_COST);
5342 size(4);
5343 format %{ "LDF $src,$dst\t! stkI to regF" %}
5344 opcode(Assembler::ldf_op3);
5345 ins_encode(simple_form3_mem_reg(src, dst));
5346 ins_pipe(floadF_stk);
5347 %}
5348
5349 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5350 // No match rule to avoid chain rule match.
5351 effect(DEF dst, USE src);
5352 ins_cost(MEMORY_REF_COST);
5353 size(4);
5354 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5355 opcode(Assembler::lddf_op3);
5356 ins_encode(simple_form3_mem_reg(src, dst));
5357 ins_pipe(floadD_stk);
5358 %}
5359
5360 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5361 // No match rule to avoid chain rule match.
5362 effect(DEF dst, USE src);
5363 ins_cost(MEMORY_REF_COST);
5364 size(4);
5365 format %{ "STF $src,$dst\t! regF to stkI" %}
5366 opcode(Assembler::stf_op3);
5367 ins_encode(simple_form3_mem_reg(dst, src));
5368 ins_pipe(fstoreF_stk_reg);
5369 %}
5370
5371 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5372 // No match rule to avoid chain rule match.
5373 effect(DEF dst, USE src);
5374 ins_cost(MEMORY_REF_COST);
5375 size(4);
5376 format %{ "STDF $src,$dst\t! regD to stkL" %}
5377 opcode(Assembler::stdf_op3);
5378 ins_encode(simple_form3_mem_reg(dst, src));
5379 ins_pipe(fstoreD_stk_reg);
5380 %}
5381
5382 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5383 effect(DEF dst, USE src);
5384 ins_cost(MEMORY_REF_COST*2);
5385 size(8);
5386 format %{ "STW $src,$dst.hi\t! long\n\t"
5387 "STW R_G0,$dst.lo" %}
5388 opcode(Assembler::stw_op3);
5389 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5390 ins_pipe(lstoreI_stk_reg);
5391 %}
5392
5393 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5394 // No match rule to avoid chain rule match.
5395 effect(DEF dst, USE src);
5396 ins_cost(MEMORY_REF_COST);
5397 size(4);
5398 format %{ "STX $src,$dst\t! regL to stkD" %}
5399 opcode(Assembler::stx_op3);
5400 ins_encode(simple_form3_mem_reg( dst, src ) );
5401 ins_pipe(istore_stk_reg);
5402 %}
5403
5404 //---------- Chain stack slots between similar types --------
5405
5406 // Load integer from stack slot
5407 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5408 match(Set dst src);
5409 ins_cost(MEMORY_REF_COST);
5410
5411 size(4);
5412 format %{ "LDUW $src,$dst\t!stk" %}
5413 opcode(Assembler::lduw_op3);
5414 ins_encode(simple_form3_mem_reg( src, dst ) );
5415 ins_pipe(iload_mem);
5416 %}
5417
5418 // Store integer to stack slot
5419 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5420 match(Set dst src);
5421 ins_cost(MEMORY_REF_COST);
5422
5423 size(4);
5424 format %{ "STW $src,$dst\t!stk" %}
5425 opcode(Assembler::stw_op3);
5426 ins_encode(simple_form3_mem_reg( dst, src ) );
5427 ins_pipe(istore_mem_reg);
5428 %}
5429
5430 // Load long from stack slot
5431 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5432 match(Set dst src);
5433
5434 ins_cost(MEMORY_REF_COST);
5435 size(4);
5436 format %{ "LDX $src,$dst\t! long" %}
5437 opcode(Assembler::ldx_op3);
5438 ins_encode(simple_form3_mem_reg( src, dst ) );
5439 ins_pipe(iload_mem);
5440 %}
5441
5442 // Store long to stack slot
5443 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5444 match(Set dst src);
5445
5446 ins_cost(MEMORY_REF_COST);
5447 size(4);
5448 format %{ "STX $src,$dst\t! long" %}
5449 opcode(Assembler::stx_op3);
5450 ins_encode(simple_form3_mem_reg( dst, src ) );
5451 ins_pipe(istore_mem_reg);
5452 %}
5453
5454 #ifdef _LP64
5455 // Load pointer from stack slot, 64-bit encoding
5456 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5457 match(Set dst src);
5458 ins_cost(MEMORY_REF_COST);
5459 size(4);
5460 format %{ "LDX $src,$dst\t!ptr" %}
5461 opcode(Assembler::ldx_op3);
5462 ins_encode(simple_form3_mem_reg( src, dst ) );
5463 ins_pipe(iload_mem);
5464 %}
5465
5466 // Store pointer to stack slot
5467 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5468 match(Set dst src);
5469 ins_cost(MEMORY_REF_COST);
5470 size(4);
5471 format %{ "STX $src,$dst\t!ptr" %}
5472 opcode(Assembler::stx_op3);
5473 ins_encode(simple_form3_mem_reg( dst, src ) );
5474 ins_pipe(istore_mem_reg);
5475 %}
5476 #else // _LP64
5477 // Load pointer from stack slot, 32-bit encoding
5478 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5479 match(Set dst src);
5480 ins_cost(MEMORY_REF_COST);
5481 format %{ "LDUW $src,$dst\t!ptr" %}
5482 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5483 ins_encode(simple_form3_mem_reg( src, dst ) );
5484 ins_pipe(iload_mem);
5485 %}
5486
5487 // Store pointer to stack slot
5488 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5489 match(Set dst src);
5490 ins_cost(MEMORY_REF_COST);
5491 format %{ "STW $src,$dst\t!ptr" %}
5492 opcode(Assembler::stw_op3, Assembler::ldst_op);
5493 ins_encode(simple_form3_mem_reg( dst, src ) );
5494 ins_pipe(istore_mem_reg);
5495 %}
5496 #endif // _LP64
5497
5498 //------------Special Nop instructions for bundling - no match rules-----------
5499 // Nop using the A0 functional unit
5500 instruct Nop_A0() %{
5501 ins_cost(0);
5502
5503 format %{ "NOP ! Alu Pipeline" %}
5504 opcode(Assembler::or_op3, Assembler::arith_op);
5505 ins_encode( form2_nop() );
5506 ins_pipe(ialu_nop_A0);
5507 %}
5508
5509 // Nop using the A1 functional unit
5510 instruct Nop_A1( ) %{
5511 ins_cost(0);
5512
5513 format %{ "NOP ! Alu Pipeline" %}
5514 opcode(Assembler::or_op3, Assembler::arith_op);
5515 ins_encode( form2_nop() );
5516 ins_pipe(ialu_nop_A1);
5517 %}
5518
5519 // Nop using the memory functional unit
5520 instruct Nop_MS( ) %{
5521 ins_cost(0);
5522
5523 format %{ "NOP ! Memory Pipeline" %}
5524 ins_encode( emit_mem_nop );
5525 ins_pipe(mem_nop);
5526 %}
5527
5528 // Nop using the floating add functional unit
5529 instruct Nop_FA( ) %{
5530 ins_cost(0);
5531
5532 format %{ "NOP ! Floating Add Pipeline" %}
5533 ins_encode( emit_fadd_nop );
5534 ins_pipe(fadd_nop);
5535 %}
5536
5537 // Nop using the branch functional unit
5538 instruct Nop_BR( ) %{
5539 ins_cost(0);
5540
5541 format %{ "NOP ! Branch Pipeline" %}
5542 ins_encode( emit_br_nop );
5543 ins_pipe(br_nop);
5544 %}
5545
5546 //----------Load/Store/Move Instructions---------------------------------------
5547 //----------Load Instructions--------------------------------------------------
5548 // Load Byte (8bit signed)
5549 instruct loadB(iRegI dst, memory mem) %{
5550 match(Set dst (LoadB mem));
5551 ins_cost(MEMORY_REF_COST);
5552
5553 size(4);
5554 format %{ "LDSB $mem,$dst\t! byte" %}
5555 ins_encode %{
5556 __ ldsb($mem$$Address, $dst$$Register);
5557 %}
5558 ins_pipe(iload_mask_mem);
5559 %}
5560
5561 // Load Byte (8bit signed) into a Long Register
5562 instruct loadB2L(iRegL dst, memory mem) %{
5563 match(Set dst (ConvI2L (LoadB mem)));
5564 ins_cost(MEMORY_REF_COST);
5565
5566 size(4);
5567 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5568 ins_encode %{
5569 __ ldsb($mem$$Address, $dst$$Register);
5570 %}
5571 ins_pipe(iload_mask_mem);
5572 %}
5573
5574 // Load Byte (8 bit signed) with 8-bit mask into Long Register
5575 instruct loadB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5576 match(Set dst (ConvI2L (AndI (LoadB mem) mask)));
5577 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5578
5579 size(2*4);
5580 format %{ "LDUB $mem,$dst\t# byte & 8-bit mask -> long\n\t"
5581 "AND $dst,$mask,$dst" %}
5582 ins_encode %{
5583 __ ldub($mem$$Address, $dst$$Register);
5584 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5585 %}
5586 ins_pipe(iload_mem);
5587 %}
5588
5589 // Load Unsigned Byte (8bit UNsigned) into an int reg
5590 instruct loadUB(iRegI dst, memory mem) %{
5591 match(Set dst (LoadUB mem));
5592 ins_cost(MEMORY_REF_COST);
5593
5594 size(4);
5595 format %{ "LDUB $mem,$dst\t! ubyte" %}
5596 ins_encode %{
5597 __ ldub($mem$$Address, $dst$$Register);
5598 %}
5599 ins_pipe(iload_mem);
5600 %}
5601
5602 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5603 instruct loadUB2L(iRegL dst, memory mem) %{
5604 match(Set dst (ConvI2L (LoadUB mem)));
5605 ins_cost(MEMORY_REF_COST);
5606
5607 size(4);
5608 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5609 ins_encode %{
5610 __ ldub($mem$$Address, $dst$$Register);
5611 %}
5612 ins_pipe(iload_mem);
5613 %}
5614
5615 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5616 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5617 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5618 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5619
5620 size(2*4);
5621 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5622 "AND $dst,$mask,$dst" %}
5623 ins_encode %{
5624 __ ldub($mem$$Address, $dst$$Register);
5625 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5626 %}
5627 ins_pipe(iload_mem);
5628 %}
5629
5630 // Load Short (16bit signed)
5631 instruct loadS(iRegI dst, memory mem) %{
5632 match(Set dst (LoadS mem));
5633 ins_cost(MEMORY_REF_COST);
5634
5635 size(4);
5636 format %{ "LDSH $mem,$dst\t! short" %}
5637 ins_encode %{
5638 __ ldsh($mem$$Address, $dst$$Register);
5639 %}
5640 ins_pipe(iload_mask_mem);
5641 %}
5642
5643 // Load Short (16 bit signed) to Byte (8 bit signed)
5644 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5645 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5646 ins_cost(MEMORY_REF_COST);
5647
5648 size(4);
5649
5650 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5651 ins_encode %{
5652 __ ldsb($mem$$Address, $dst$$Register, 1);
5653 %}
5654 ins_pipe(iload_mask_mem);
5655 %}
5656
5657 // Load Short (16bit signed) into a Long Register
5658 instruct loadS2L(iRegL dst, memory mem) %{
5659 match(Set dst (ConvI2L (LoadS mem)));
5660 ins_cost(MEMORY_REF_COST);
5661
5662 size(4);
5663 format %{ "LDSH $mem,$dst\t! short -> long" %}
5664 ins_encode %{
5665 __ ldsh($mem$$Address, $dst$$Register);
5666 %}
5667 ins_pipe(iload_mask_mem);
5668 %}
5669
5670 // Load Short (16bit signed) with mask 0xFF into a Long Register
5671 instruct loadS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5672 match(Set dst (ConvI2L (AndI (LoadS mem) mask)));
5673 ins_cost(MEMORY_REF_COST);
5674
5675 size(4);
5676 format %{ "LDUB $mem+1,$dst\t! short & 0xFF -> long" %}
5677 ins_encode %{
5678 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5679 %}
5680 ins_pipe(iload_mem);
5681 %}
5682
5683 // Load Short (16bit signed) with a 13-bit mask into a Long Register
5684 instruct loadS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5685 match(Set dst (ConvI2L (AndI (LoadS mem) mask)));
5686 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5687
5688 size(2*4);
5689 format %{ "LDUH $mem,$dst\t! short & 13-bit mask -> long\n\t"
5690 "AND $dst,$mask,$dst" %}
5691 ins_encode %{
5692 Register Rdst = $dst$$Register;
5693 __ lduh($mem$$Address, Rdst);
5694 __ and3(Rdst, $mask$$constant, Rdst);
5695 %}
5696 ins_pipe(iload_mem);
5697 %}
5698
5699 // Load Unsigned Short/Char (16bit UNsigned)
5700 instruct loadUS(iRegI dst, memory mem) %{
5701 match(Set dst (LoadUS mem));
5702 ins_cost(MEMORY_REF_COST);
5703
5704 size(4);
5705 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5706 ins_encode %{
5707 __ lduh($mem$$Address, $dst$$Register);
5708 %}
5709 ins_pipe(iload_mem);
5710 %}
5711
5712 // Load Unsigned Short/Char (16 bit UNsigned) shifting left & right by 16-bit
5713 instruct loadUS_shiftLR_16(iRegI dst, memory mem, immI_16 sixteen)
5714 %{
5715 match(Set dst (RShiftI (LShiftI (LoadUS mem) sixteen) sixteen));
5716 ins_cost(MEMORY_REF_COST);
5717
5718 size(4);
5719 format %{ "LDSH $mem,$dst\t! (ushort/char << 16) >> 16" %}
5720 ins_encode %{
5721 __ ldsh($mem$$Address, $dst$$Register);
5722 %}
5723 ins_pipe(iload_mask_mem);
5724 %}
5725
5726 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5727 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5728 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5729 ins_cost(MEMORY_REF_COST);
5730
5731 size(4);
5732 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5733 ins_encode %{
5734 __ ldsb($mem$$Address, $dst$$Register, 1);
5735 %}
5736 ins_pipe(iload_mask_mem);
5737 %}
5738
5739 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5740 instruct loadUS2L(iRegL dst, memory mem) %{
5741 match(Set dst (ConvI2L (LoadUS mem)));
5742 ins_cost(MEMORY_REF_COST);
5743
5744 size(4);
5745 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5746 ins_encode %{
5747 __ lduh($mem$$Address, $dst$$Register);
5748 %}
5749 ins_pipe(iload_mem);
5750 %}
5751
5752 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5753 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5754 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5755 ins_cost(MEMORY_REF_COST);
5756
5757 size(4);
5758 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5759 ins_encode %{
5760 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5761 %}
5762 ins_pipe(iload_mem);
5763 %}
5764
5765 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5766 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5767 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5768 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5769
5770 size(2*4);
5771 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5772 "AND $dst,$mask,$dst" %}
5773 ins_encode %{
5774 Register Rdst = $dst$$Register;
5775 __ lduh($mem$$Address, Rdst);
5776 __ and3(Rdst, $mask$$constant, Rdst);
5777 %}
5778 ins_pipe(iload_mem);
5779 %}
5780
5781 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5782 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5783 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5784 effect(TEMP dst, TEMP tmp);
5785 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5786
5787 size((3+1)*4); // set may use two instructions.
5788 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5789 "SET $mask,$tmp\n\t"
5790 "AND $dst,$tmp,$dst" %}
5791 ins_encode %{
5792 Register Rdst = $dst$$Register;
5793 Register Rtmp = $tmp$$Register;
5794 __ lduh($mem$$Address, Rdst);
5795 __ set($mask$$constant, Rtmp);
5796 __ and3(Rdst, Rtmp, Rdst);
5797 %}
5798 ins_pipe(iload_mem);
5799 %}
5800
5801 // Load Integer
5802 instruct loadI(iRegI dst, memory mem) %{
5803 match(Set dst (LoadI mem));
5804 ins_cost(MEMORY_REF_COST);
5805
5806 size(4);
5807 format %{ "LDUW $mem,$dst\t! int" %}
5808 ins_encode %{
5809 __ lduw($mem$$Address, $dst$$Register);
5810 %}
5811 ins_pipe(iload_mem);
5812 %}
5813
5814 // Load Integer to Byte (8 bit signed)
5815 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5816 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5817 ins_cost(MEMORY_REF_COST);
5818
5819 size(4);
5820
5821 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5822 ins_encode %{
5823 __ ldsb($mem$$Address, $dst$$Register, 3);
5824 %}
5825 ins_pipe(iload_mask_mem);
5826 %}
5827
5828 // Load Integer to Unsigned Byte (8 bit UNsigned)
5829 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5830 match(Set dst (AndI (LoadI mem) mask));
5831 ins_cost(MEMORY_REF_COST);
5832
5833 size(4);
5834
5835 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5836 ins_encode %{
5837 __ ldub($mem$$Address, $dst$$Register, 3);
5838 %}
5839 ins_pipe(iload_mask_mem);
5840 %}
5841
5842 // Load Integer to Short (16 bit signed)
5843 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5844 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5845 ins_cost(MEMORY_REF_COST);
5846
5847 size(4);
5848
5849 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5850 ins_encode %{
5851 __ ldsh($mem$$Address, $dst$$Register, 2);
5852 %}
5853 ins_pipe(iload_mask_mem);
5854 %}
5855
5856 // Load Integer to Unsigned Short (16 bit UNsigned)
5857 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5858 match(Set dst (AndI (LoadI mem) mask));
5859 ins_cost(MEMORY_REF_COST);
5860
5861 size(4);
5862
5863 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5864 ins_encode %{
5865 __ lduh($mem$$Address, $dst$$Register, 2);
5866 %}
5867 ins_pipe(iload_mask_mem);
5868 %}
5869
5870 // Load Integer into a Long Register
5871 instruct loadI2L(iRegL dst, memory mem) %{
5872 match(Set dst (ConvI2L (LoadI mem)));
5873 ins_cost(MEMORY_REF_COST);
5874
5875 size(4);
5876 format %{ "LDSW $mem,$dst\t! int -> long" %}
5877 ins_encode %{
5878 __ ldsw($mem$$Address, $dst$$Register);
5879 %}
5880 ins_pipe(iload_mask_mem);
5881 %}
5882
5883 // Load Integer with mask 0xFF into a Long Register
5884 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5885 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5886 ins_cost(MEMORY_REF_COST);
5887
5888 size(4);
5889 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5890 ins_encode %{
5891 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5892 %}
5893 ins_pipe(iload_mem);
5894 %}
5895
5896 // Load Integer with mask 0xFFFF into a Long Register
5897 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5898 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5899 ins_cost(MEMORY_REF_COST);
5900
5901 size(4);
5902 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5903 ins_encode %{
5904 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5905 %}
5906 ins_pipe(iload_mem);
5907 %}
5908
5909 // Load Integer with a 13-bit mask into a Long Register
5910 instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5911 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5912 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5913
5914 size(2*4);
5915 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t"
5916 "AND $dst,$mask,$dst" %}
5917 ins_encode %{
5918 Register Rdst = $dst$$Register;
5919 __ lduw($mem$$Address, Rdst);
5920 __ and3(Rdst, $mask$$constant, Rdst);
5921 %}
5922 ins_pipe(iload_mem);
5923 %}
5924
5925 // Load Integer with a 32-bit mask into a Long Register
5926 instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5927 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5928 effect(TEMP dst, TEMP tmp);
5929 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5930
5931 size((3+1)*4); // set may use two instructions.
5932 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t"
5933 "SET $mask,$tmp\n\t"
5934 "AND $dst,$tmp,$dst" %}
5935 ins_encode %{
5936 Register Rdst = $dst$$Register;
5937 Register Rtmp = $tmp$$Register;
5938 __ lduw($mem$$Address, Rdst);
5939 __ set($mask$$constant, Rtmp);
5940 __ and3(Rdst, Rtmp, Rdst);
5941 %}
5942 ins_pipe(iload_mem);
5943 %}
5944
5945 // Load Unsigned Integer into a Long Register
5946 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5947 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5948 ins_cost(MEMORY_REF_COST);
5949
5950 size(4);
5951 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5952 ins_encode %{
5953 __ lduw($mem$$Address, $dst$$Register);
5954 %}
5955 ins_pipe(iload_mem);
5956 %}
5957
5958 // Load Long - aligned
5959 instruct loadL(iRegL dst, memory mem ) %{
5960 match(Set dst (LoadL mem));
5961 ins_cost(MEMORY_REF_COST);
5962
5963 size(4);
5964 format %{ "LDX $mem,$dst\t! long" %}
5965 ins_encode %{
5966 __ ldx($mem$$Address, $dst$$Register);
5967 %}
5968 ins_pipe(iload_mem);
5969 %}
5970
5971 // Load Long - UNaligned
5972 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5973 match(Set dst (LoadL_unaligned mem));
5974 effect(KILL tmp);
5975 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5976 size(16);
5977 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5978 "\tLDUW $mem ,$dst\n"
5979 "\tSLLX #32, $dst, $dst\n"
5980 "\tOR $dst, R_O7, $dst" %}
5981 opcode(Assembler::lduw_op3);
5982 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5983 ins_pipe(iload_mem);
5984 %}
5985
5986 // Load Range
5987 instruct loadRange(iRegI dst, memory mem) %{
5988 match(Set dst (LoadRange mem));
5989 ins_cost(MEMORY_REF_COST);
5990
5991 size(4);
5992 format %{ "LDUW $mem,$dst\t! range" %}
5993 opcode(Assembler::lduw_op3);
5994 ins_encode(simple_form3_mem_reg( mem, dst ) );
5995 ins_pipe(iload_mem);
5996 %}
5997
5998 // Load Integer into %f register (for fitos/fitod)
5999 instruct loadI_freg(regF dst, memory mem) %{
6000 match(Set dst (LoadI mem));
6001 ins_cost(MEMORY_REF_COST);
6002 size(4);
6003
6004 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
6005 opcode(Assembler::ldf_op3);
6006 ins_encode(simple_form3_mem_reg( mem, dst ) );
6007 ins_pipe(floadF_mem);
6008 %}
6009
6010 // Load Pointer
6011 instruct loadP(iRegP dst, memory mem) %{
6012 match(Set dst (LoadP mem));
6013 ins_cost(MEMORY_REF_COST);
6014 size(4);
6015
6016 #ifndef _LP64
6017 format %{ "LDUW $mem,$dst\t! ptr" %}
6018 ins_encode %{
6019 __ lduw($mem$$Address, $dst$$Register);
6020 %}
6021 #else
6022 format %{ "LDX $mem,$dst\t! ptr" %}
6023 ins_encode %{
6024 __ ldx($mem$$Address, $dst$$Register);
6025 %}
6026 #endif
6027 ins_pipe(iload_mem);
6028 %}
6029
6030 // Load Compressed Pointer
6031 instruct loadN(iRegN dst, memory mem) %{
6032 match(Set dst (LoadN mem));
6033 ins_cost(MEMORY_REF_COST);
6034 size(4);
6035
6036 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6037 ins_encode %{
6038 __ lduw($mem$$Address, $dst$$Register);
6039 %}
6040 ins_pipe(iload_mem);
6041 %}
6042
6043 // Load Klass Pointer
6044 instruct loadKlass(iRegP dst, memory mem) %{
6045 match(Set dst (LoadKlass mem));
6046 ins_cost(MEMORY_REF_COST);
6047 size(4);
6048
6049 #ifndef _LP64
6050 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6051 ins_encode %{
6052 __ lduw($mem$$Address, $dst$$Register);
6053 %}
6054 #else
6055 format %{ "LDX $mem,$dst\t! klass ptr" %}
6056 ins_encode %{
6057 __ ldx($mem$$Address, $dst$$Register);
6058 %}
6059 #endif
6060 ins_pipe(iload_mem);
6061 %}
6062
6063 // Load narrow Klass Pointer
6064 instruct loadNKlass(iRegN dst, memory mem) %{
6065 match(Set dst (LoadNKlass mem));
6066 ins_cost(MEMORY_REF_COST);
6067 size(4);
6068
6069 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6070 ins_encode %{
6071 __ lduw($mem$$Address, $dst$$Register);
6072 %}
6073 ins_pipe(iload_mem);
6074 %}
6075
6076 // Load Double
6077 instruct loadD(regD dst, memory mem) %{
6078 match(Set dst (LoadD mem));
6079 ins_cost(MEMORY_REF_COST);
6080
6081 size(4);
6082 format %{ "LDDF $mem,$dst" %}
6083 opcode(Assembler::lddf_op3);
6084 ins_encode(simple_form3_mem_reg( mem, dst ) );
6085 ins_pipe(floadD_mem);
6086 %}
6087
6088 // Load Double - UNaligned
6089 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6090 match(Set dst (LoadD_unaligned mem));
6091 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6092 size(8);
6093 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6094 "\tLDF $mem+4,$dst.lo\t!" %}
6095 opcode(Assembler::ldf_op3);
6096 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6097 ins_pipe(iload_mem);
6098 %}
6099
6100 // Load Float
6101 instruct loadF(regF dst, memory mem) %{
6102 match(Set dst (LoadF mem));
6103 ins_cost(MEMORY_REF_COST);
6104
6105 size(4);
6106 format %{ "LDF $mem,$dst" %}
6107 opcode(Assembler::ldf_op3);
6108 ins_encode(simple_form3_mem_reg( mem, dst ) );
6109 ins_pipe(floadF_mem);
6110 %}
6111
6112 // Load Constant
6113 instruct loadConI( iRegI dst, immI src ) %{
6114 match(Set dst src);
6115 ins_cost(DEFAULT_COST * 3/2);
6116 format %{ "SET $src,$dst" %}
6117 ins_encode( Set32(src, dst) );
6118 ins_pipe(ialu_hi_lo_reg);
6119 %}
6120
6121 instruct loadConI13( iRegI dst, immI13 src ) %{
6122 match(Set dst src);
6123
6124 size(4);
6125 format %{ "MOV $src,$dst" %}
6126 ins_encode( Set13( src, dst ) );
6127 ins_pipe(ialu_imm);
6128 %}
6129
6130 #ifndef _LP64
6131 instruct loadConP(iRegP dst, immP con) %{
6132 match(Set dst con);
6133 ins_cost(DEFAULT_COST * 3/2);
6134 format %{ "SET $con,$dst\t!ptr" %}
6135 ins_encode %{
6136 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6137 intptr_t val = $con$$constant;
6138 if (constant_reloc == relocInfo::oop_type) {
6139 __ set_oop_constant((jobject) val, $dst$$Register);
6140 } else if (constant_reloc == relocInfo::metadata_type) {
6141 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6142 } else { // non-oop pointers, e.g. card mark base, heap top
6143 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6144 __ set(val, $dst$$Register);
6145 }
6146 %}
6147 ins_pipe(loadConP);
6148 %}
6149 #else
6150 instruct loadConP_set(iRegP dst, immP_set con) %{
6151 match(Set dst con);
6152 ins_cost(DEFAULT_COST * 3/2);
6153 format %{ "SET $con,$dst\t! ptr" %}
6154 ins_encode %{
6155 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6156 intptr_t val = $con$$constant;
6157 if (constant_reloc == relocInfo::oop_type) {
6158 __ set_oop_constant((jobject) val, $dst$$Register);
6159 } else if (constant_reloc == relocInfo::metadata_type) {
6160 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6161 } else { // non-oop pointers, e.g. card mark base, heap top
6162 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6163 __ set(val, $dst$$Register);
6164 }
6165 %}
6166 ins_pipe(loadConP);
6167 %}
6168
6169 instruct loadConP_load(iRegP dst, immP_load con) %{
6170 match(Set dst con);
6171 ins_cost(MEMORY_REF_COST);
6172 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6173 ins_encode %{
6174 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6175 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6176 %}
6177 ins_pipe(loadConP);
6178 %}
6179
6180 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6181 match(Set dst con);
6182 ins_cost(DEFAULT_COST * 3/2);
6183 format %{ "SET $con,$dst\t! non-oop ptr" %}
6184 ins_encode %{
6185 __ set($con$$constant, $dst$$Register);
6186 %}
6187 ins_pipe(loadConP);
6188 %}
6189 #endif // _LP64
6190
6191 instruct loadConP0(iRegP dst, immP0 src) %{
6192 match(Set dst src);
6193
6194 size(4);
6195 format %{ "CLR $dst\t!ptr" %}
6196 ins_encode %{
6197 __ clr($dst$$Register);
6198 %}
6199 ins_pipe(ialu_imm);
6200 %}
6201
6202 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6203 match(Set dst src);
6204 ins_cost(DEFAULT_COST);
6205 format %{ "SET $src,$dst\t!ptr" %}
6206 ins_encode %{
6207 AddressLiteral polling_page(os::get_polling_page());
6208 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6209 %}
6210 ins_pipe(loadConP_poll);
6211 %}
6212
6213 instruct loadConN0(iRegN dst, immN0 src) %{
6214 match(Set dst src);
6215
6216 size(4);
6217 format %{ "CLR $dst\t! compressed NULL ptr" %}
6218 ins_encode %{
6219 __ clr($dst$$Register);
6220 %}
6221 ins_pipe(ialu_imm);
6222 %}
6223
6224 instruct loadConN(iRegN dst, immN src) %{
6225 match(Set dst src);
6226 ins_cost(DEFAULT_COST * 3/2);
6227 format %{ "SET $src,$dst\t! compressed ptr" %}
6228 ins_encode %{
6229 Register dst = $dst$$Register;
6230 __ set_narrow_oop((jobject)$src$$constant, dst);
6231 %}
6232 ins_pipe(ialu_hi_lo_reg);
6233 %}
6234
6235 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6236 match(Set dst src);
6237 ins_cost(DEFAULT_COST * 3/2);
6238 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6239 ins_encode %{
6240 Register dst = $dst$$Register;
6241 __ set_narrow_klass((Klass*)$src$$constant, dst);
6242 %}
6243 ins_pipe(ialu_hi_lo_reg);
6244 %}
6245
6246 // Materialize long value (predicated by immL_cheap).
6247 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6248 match(Set dst con);
6249 effect(KILL tmp);
6250 ins_cost(DEFAULT_COST * 3);
6251 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6252 ins_encode %{
6253 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6254 %}
6255 ins_pipe(loadConL);
6256 %}
6257
6258 // Load long value from constant table (predicated by immL_expensive).
6259 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6260 match(Set dst con);
6261 ins_cost(MEMORY_REF_COST);
6262 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6263 ins_encode %{
6264 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6265 __ ldx($constanttablebase, con_offset, $dst$$Register);
6266 %}
6267 ins_pipe(loadConL);
6268 %}
6269
6270 instruct loadConL0( iRegL dst, immL0 src ) %{
6271 match(Set dst src);
6272 ins_cost(DEFAULT_COST);
6273 size(4);
6274 format %{ "CLR $dst\t! long" %}
6275 ins_encode( Set13( src, dst ) );
6276 ins_pipe(ialu_imm);
6277 %}
6278
6279 instruct loadConL13( iRegL dst, immL13 src ) %{
6280 match(Set dst src);
6281 ins_cost(DEFAULT_COST * 2);
6282
6283 size(4);
6284 format %{ "MOV $src,$dst\t! long" %}
6285 ins_encode( Set13( src, dst ) );
6286 ins_pipe(ialu_imm);
6287 %}
6288
6289 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6290 match(Set dst con);
6291 effect(KILL tmp);
6292 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6293 ins_encode %{
6294 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6295 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6296 %}
6297 ins_pipe(loadConFD);
6298 %}
6299
6300 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6301 match(Set dst con);
6302 effect(KILL tmp);
6303 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6304 ins_encode %{
6305 // XXX This is a quick fix for 6833573.
6306 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6307 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6308 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6309 %}
6310 ins_pipe(loadConFD);
6311 %}
6312
6313 // Prefetch instructions.
6314 // Must be safe to execute with invalid address (cannot fault).
6315
6316 instruct prefetchr( memory mem ) %{
6317 match( PrefetchRead mem );
6318 ins_cost(MEMORY_REF_COST);
6319 size(4);
6320
6321 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
6322 opcode(Assembler::prefetch_op3);
6323 ins_encode( form3_mem_prefetch_read( mem ) );
6324 ins_pipe(iload_mem);
6325 %}
6326
6327 instruct prefetchw( memory mem ) %{
6328 match( PrefetchWrite mem );
6329 ins_cost(MEMORY_REF_COST);
6330 size(4);
6331
6332 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
6333 opcode(Assembler::prefetch_op3);
6334 ins_encode( form3_mem_prefetch_write( mem ) );
6335 ins_pipe(iload_mem);
6336 %}
6337
6338 // Prefetch instructions for allocation.
6339
6340 instruct prefetchAlloc( memory mem ) %{
6341 predicate(AllocatePrefetchInstr == 0);
6342 match( PrefetchAllocation mem );
6343 ins_cost(MEMORY_REF_COST);
6344 size(4);
6345
6346 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6347 opcode(Assembler::prefetch_op3);
6348 ins_encode( form3_mem_prefetch_write( mem ) );
6349 ins_pipe(iload_mem);
6350 %}
6351
6352 // Use BIS instruction to prefetch for allocation.
6353 // Could fault, need space at the end of TLAB.
6354 instruct prefetchAlloc_bis( iRegP dst ) %{
6355 predicate(AllocatePrefetchInstr == 1);
6356 match( PrefetchAllocation dst );
6357 ins_cost(MEMORY_REF_COST);
6358 size(4);
6359
6360 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6361 ins_encode %{
6362 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6363 %}
6364 ins_pipe(istore_mem_reg);
6365 %}
6366
6367 // Next code is used for finding next cache line address to prefetch.
6368 #ifndef _LP64
6369 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6370 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6371 ins_cost(DEFAULT_COST);
6372 size(4);
6373
6374 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6375 ins_encode %{
6376 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6377 %}
6378 ins_pipe(ialu_reg_imm);
6379 %}
6380 #else
6381 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6382 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6383 ins_cost(DEFAULT_COST);
6384 size(4);
6385
6386 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6387 ins_encode %{
6388 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6389 %}
6390 ins_pipe(ialu_reg_imm);
6391 %}
6392 #endif
6393
6394 //----------Store Instructions-------------------------------------------------
6395 // Store Byte
6396 instruct storeB(memory mem, iRegI src) %{
6397 match(Set mem (StoreB mem src));
6398 ins_cost(MEMORY_REF_COST);
6399
6400 size(4);
6401 format %{ "STB $src,$mem\t! byte" %}
6402 opcode(Assembler::stb_op3);
6403 ins_encode(simple_form3_mem_reg( mem, src ) );
6404 ins_pipe(istore_mem_reg);
6405 %}
6406
6407 instruct storeB0(memory mem, immI0 src) %{
6408 match(Set mem (StoreB mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 size(4);
6412 format %{ "STB $src,$mem\t! byte" %}
6413 opcode(Assembler::stb_op3);
6414 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6415 ins_pipe(istore_mem_zero);
6416 %}
6417
6418 instruct storeCM0(memory mem, immI0 src) %{
6419 match(Set mem (StoreCM mem src));
6420 ins_cost(MEMORY_REF_COST);
6421
6422 size(4);
6423 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6424 opcode(Assembler::stb_op3);
6425 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6426 ins_pipe(istore_mem_zero);
6427 %}
6428
6429 // Store Char/Short
6430 instruct storeC(memory mem, iRegI src) %{
6431 match(Set mem (StoreC mem src));
6432 ins_cost(MEMORY_REF_COST);
6433
6434 size(4);
6435 format %{ "STH $src,$mem\t! short" %}
6436 opcode(Assembler::sth_op3);
6437 ins_encode(simple_form3_mem_reg( mem, src ) );
6438 ins_pipe(istore_mem_reg);
6439 %}
6440
6441 instruct storeC0(memory mem, immI0 src) %{
6442 match(Set mem (StoreC mem src));
6443 ins_cost(MEMORY_REF_COST);
6444
6445 size(4);
6446 format %{ "STH $src,$mem\t! short" %}
6447 opcode(Assembler::sth_op3);
6448 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6449 ins_pipe(istore_mem_zero);
6450 %}
6451
6452 // Store Integer
6453 instruct storeI(memory mem, iRegI src) %{
6454 match(Set mem (StoreI mem src));
6455 ins_cost(MEMORY_REF_COST);
6456
6457 size(4);
6458 format %{ "STW $src,$mem" %}
6459 opcode(Assembler::stw_op3);
6460 ins_encode(simple_form3_mem_reg( mem, src ) );
6461 ins_pipe(istore_mem_reg);
6462 %}
6463
6464 // Store Long
6465 instruct storeL(memory mem, iRegL src) %{
6466 match(Set mem (StoreL mem src));
6467 ins_cost(MEMORY_REF_COST);
6468 size(4);
6469 format %{ "STX $src,$mem\t! long" %}
6470 opcode(Assembler::stx_op3);
6471 ins_encode(simple_form3_mem_reg( mem, src ) );
6472 ins_pipe(istore_mem_reg);
6473 %}
6474
6475 instruct storeI0(memory mem, immI0 src) %{
6476 match(Set mem (StoreI mem src));
6477 ins_cost(MEMORY_REF_COST);
6478
6479 size(4);
6480 format %{ "STW $src,$mem" %}
6481 opcode(Assembler::stw_op3);
6482 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6483 ins_pipe(istore_mem_zero);
6484 %}
6485
6486 instruct storeL0(memory mem, immL0 src) %{
6487 match(Set mem (StoreL mem src));
6488 ins_cost(MEMORY_REF_COST);
6489
6490 size(4);
6491 format %{ "STX $src,$mem" %}
6492 opcode(Assembler::stx_op3);
6493 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6494 ins_pipe(istore_mem_zero);
6495 %}
6496
6497 // Store Integer from float register (used after fstoi)
6498 instruct storeI_Freg(memory mem, regF src) %{
6499 match(Set mem (StoreI mem src));
6500 ins_cost(MEMORY_REF_COST);
6501
6502 size(4);
6503 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6504 opcode(Assembler::stf_op3);
6505 ins_encode(simple_form3_mem_reg( mem, src ) );
6506 ins_pipe(fstoreF_mem_reg);
6507 %}
6508
6509 // Store Pointer
6510 instruct storeP(memory dst, sp_ptr_RegP src) %{
6511 match(Set dst (StoreP dst src));
6512 ins_cost(MEMORY_REF_COST);
6513 size(4);
6514
6515 #ifndef _LP64
6516 format %{ "STW $src,$dst\t! ptr" %}
6517 opcode(Assembler::stw_op3, 0, REGP_OP);
6518 #else
6519 format %{ "STX $src,$dst\t! ptr" %}
6520 opcode(Assembler::stx_op3, 0, REGP_OP);
6521 #endif
6522 ins_encode( form3_mem_reg( dst, src ) );
6523 ins_pipe(istore_mem_spORreg);
6524 %}
6525
6526 instruct storeP0(memory dst, immP0 src) %{
6527 match(Set dst (StoreP dst src));
6528 ins_cost(MEMORY_REF_COST);
6529 size(4);
6530
6531 #ifndef _LP64
6532 format %{ "STW $src,$dst\t! ptr" %}
6533 opcode(Assembler::stw_op3, 0, REGP_OP);
6534 #else
6535 format %{ "STX $src,$dst\t! ptr" %}
6536 opcode(Assembler::stx_op3, 0, REGP_OP);
6537 #endif
6538 ins_encode( form3_mem_reg( dst, R_G0 ) );
6539 ins_pipe(istore_mem_zero);
6540 %}
6541
6542 // Store Compressed Pointer
6543 instruct storeN(memory dst, iRegN src) %{
6544 match(Set dst (StoreN dst src));
6545 ins_cost(MEMORY_REF_COST);
6546 size(4);
6547
6548 format %{ "STW $src,$dst\t! compressed ptr" %}
6549 ins_encode %{
6550 Register base = as_Register($dst$$base);
6551 Register index = as_Register($dst$$index);
6552 Register src = $src$$Register;
6553 if (index != G0) {
6554 __ stw(src, base, index);
6555 } else {
6556 __ stw(src, base, $dst$$disp);
6557 }
6558 %}
6559 ins_pipe(istore_mem_spORreg);
6560 %}
6561
6562 instruct storeNKlass(memory dst, iRegN src) %{
6563 match(Set dst (StoreNKlass dst src));
6564 ins_cost(MEMORY_REF_COST);
6565 size(4);
6566
6567 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6568 ins_encode %{
6569 Register base = as_Register($dst$$base);
6570 Register index = as_Register($dst$$index);
6571 Register src = $src$$Register;
6572 if (index != G0) {
6573 __ stw(src, base, index);
6574 } else {
6575 __ stw(src, base, $dst$$disp);
6576 }
6577 %}
6578 ins_pipe(istore_mem_spORreg);
6579 %}
6580
6581 instruct storeN0(memory dst, immN0 src) %{
6582 match(Set dst (StoreN dst src));
6583 ins_cost(MEMORY_REF_COST);
6584 size(4);
6585
6586 format %{ "STW $src,$dst\t! compressed ptr" %}
6587 ins_encode %{
6588 Register base = as_Register($dst$$base);
6589 Register index = as_Register($dst$$index);
6590 if (index != G0) {
6591 __ stw(0, base, index);
6592 } else {
6593 __ stw(0, base, $dst$$disp);
6594 }
6595 %}
6596 ins_pipe(istore_mem_zero);
6597 %}
6598
6599 // Store Double
6600 instruct storeD( memory mem, regD src) %{
6601 match(Set mem (StoreD mem src));
6602 ins_cost(MEMORY_REF_COST);
6603
6604 size(4);
6605 format %{ "STDF $src,$mem" %}
6606 opcode(Assembler::stdf_op3);
6607 ins_encode(simple_form3_mem_reg( mem, src ) );
6608 ins_pipe(fstoreD_mem_reg);
6609 %}
6610
6611 instruct storeD0( memory mem, immD0 src) %{
6612 match(Set mem (StoreD mem src));
6613 ins_cost(MEMORY_REF_COST);
6614
6615 size(4);
6616 format %{ "STX $src,$mem" %}
6617 opcode(Assembler::stx_op3);
6618 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6619 ins_pipe(fstoreD_mem_zero);
6620 %}
6621
6622 // Store Float
6623 instruct storeF( memory mem, regF src) %{
6624 match(Set mem (StoreF mem src));
6625 ins_cost(MEMORY_REF_COST);
6626
6627 size(4);
6628 format %{ "STF $src,$mem" %}
6629 opcode(Assembler::stf_op3);
6630 ins_encode(simple_form3_mem_reg( mem, src ) );
6631 ins_pipe(fstoreF_mem_reg);
6632 %}
6633
6634 instruct storeF0( memory mem, immF0 src) %{
6635 match(Set mem (StoreF mem src));
6636 ins_cost(MEMORY_REF_COST);
6637
6638 size(4);
6639 format %{ "STW $src,$mem\t! storeF0" %}
6640 opcode(Assembler::stw_op3);
6641 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6642 ins_pipe(fstoreF_mem_zero);
6643 %}
6644
6645 // Convert oop pointer into compressed form
6646 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6647 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6648 match(Set dst (EncodeP src));
6649 format %{ "encode_heap_oop $src, $dst" %}
6650 ins_encode %{
6651 __ encode_heap_oop($src$$Register, $dst$$Register);
6652 %}
6653 ins_pipe(ialu_reg);
6654 %}
6655
6656 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6657 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6658 match(Set dst (EncodeP src));
6659 format %{ "encode_heap_oop_not_null $src, $dst" %}
6660 ins_encode %{
6661 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6662 %}
6663 ins_pipe(ialu_reg);
6664 %}
6665
6666 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6667 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6668 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6669 match(Set dst (DecodeN src));
6670 format %{ "decode_heap_oop $src, $dst" %}
6671 ins_encode %{
6672 __ decode_heap_oop($src$$Register, $dst$$Register);
6673 %}
6674 ins_pipe(ialu_reg);
6675 %}
6676
6677 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6678 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6679 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6680 match(Set dst (DecodeN src));
6681 format %{ "decode_heap_oop_not_null $src, $dst" %}
6682 ins_encode %{
6683 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6684 %}
6685 ins_pipe(ialu_reg);
6686 %}
6687
6688 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6689 match(Set dst (EncodePKlass src));
6690 format %{ "encode_klass_not_null $src, $dst" %}
6691 ins_encode %{
6692 __ encode_klass_not_null($src$$Register, $dst$$Register);
6693 %}
6694 ins_pipe(ialu_reg);
6695 %}
6696
6697 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6698 match(Set dst (DecodeNKlass src));
6699 format %{ "decode_klass_not_null $src, $dst" %}
6700 ins_encode %{
6701 __ decode_klass_not_null($src$$Register, $dst$$Register);
6702 %}
6703 ins_pipe(ialu_reg);
6704 %}
6705
6706 //----------MemBar Instructions-----------------------------------------------
6707 // Memory barrier flavors
6708
6709 instruct membar_acquire() %{
6710 match(MemBarAcquire);
6711 ins_cost(4*MEMORY_REF_COST);
6712
6713 size(0);
6714 format %{ "MEMBAR-acquire" %}
6715 ins_encode( enc_membar_acquire );
6716 ins_pipe(long_memory_op);
6717 %}
6718
6719 instruct membar_acquire_lock() %{
6720 match(MemBarAcquireLock);
6721 ins_cost(0);
6722
6723 size(0);
6724 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6725 ins_encode( );
6726 ins_pipe(empty);
6727 %}
6728
6729 instruct membar_release() %{
6730 match(MemBarRelease);
6731 ins_cost(4*MEMORY_REF_COST);
6732
6733 size(0);
6734 format %{ "MEMBAR-release" %}
6735 ins_encode( enc_membar_release );
6736 ins_pipe(long_memory_op);
6737 %}
6738
6739 instruct membar_release_lock() %{
6740 match(MemBarReleaseLock);
6741 ins_cost(0);
6742
6743 size(0);
6744 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6745 ins_encode( );
6746 ins_pipe(empty);
6747 %}
6748
6749 instruct membar_volatile() %{
6750 match(MemBarVolatile);
6751 ins_cost(4*MEMORY_REF_COST);
6752
6753 size(4);
6754 format %{ "MEMBAR-volatile" %}
6755 ins_encode( enc_membar_volatile );
6756 ins_pipe(long_memory_op);
6757 %}
6758
6759 instruct unnecessary_membar_volatile() %{
6760 match(MemBarVolatile);
6761 predicate(Matcher::post_store_load_barrier(n));
6762 ins_cost(0);
6763
6764 size(0);
6765 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6766 ins_encode( );
6767 ins_pipe(empty);
6768 %}
6769
6770 instruct membar_storestore() %{
6771 match(MemBarStoreStore);
6772 ins_cost(0);
6773
6774 size(0);
6775 format %{ "!MEMBAR-storestore (empty encoding)" %}
6776 ins_encode( );
6777 ins_pipe(empty);
6778 %}
6779
6780 //----------Register Move Instructions-----------------------------------------
6781 instruct roundDouble_nop(regD dst) %{
6782 match(Set dst (RoundDouble dst));
6783 ins_cost(0);
6784 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6785 ins_encode( );
6786 ins_pipe(empty);
6787 %}
6788
6789
6790 instruct roundFloat_nop(regF dst) %{
6791 match(Set dst (RoundFloat dst));
6792 ins_cost(0);
6793 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6794 ins_encode( );
6795 ins_pipe(empty);
6796 %}
6797
6798
6799 // Cast Index to Pointer for unsafe natives
6800 instruct castX2P(iRegX src, iRegP dst) %{
6801 match(Set dst (CastX2P src));
6802
6803 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6804 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6805 ins_pipe(ialu_reg);
6806 %}
6807
6808 // Cast Pointer to Index for unsafe natives
6809 instruct castP2X(iRegP src, iRegX dst) %{
6810 match(Set dst (CastP2X src));
6811
6812 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6813 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6814 ins_pipe(ialu_reg);
6815 %}
6816
6817 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6818 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6819 match(Set stkSlot src); // chain rule
6820 ins_cost(MEMORY_REF_COST);
6821 format %{ "STDF $src,$stkSlot\t!stk" %}
6822 opcode(Assembler::stdf_op3);
6823 ins_encode(simple_form3_mem_reg(stkSlot, src));
6824 ins_pipe(fstoreD_stk_reg);
6825 %}
6826
6827 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6828 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6829 match(Set dst stkSlot); // chain rule
6830 ins_cost(MEMORY_REF_COST);
6831 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6832 opcode(Assembler::lddf_op3);
6833 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6834 ins_pipe(floadD_stk);
6835 %}
6836
6837 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6838 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6839 match(Set stkSlot src); // chain rule
6840 ins_cost(MEMORY_REF_COST);
6841 format %{ "STF $src,$stkSlot\t!stk" %}
6842 opcode(Assembler::stf_op3);
6843 ins_encode(simple_form3_mem_reg(stkSlot, src));
6844 ins_pipe(fstoreF_stk_reg);
6845 %}
6846
6847 //----------Conditional Move---------------------------------------------------
6848 // Conditional move
6849 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6850 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6851 ins_cost(150);
6852 format %{ "MOV$cmp $pcc,$src,$dst" %}
6853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6854 ins_pipe(ialu_reg);
6855 %}
6856
6857 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6858 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6859 ins_cost(140);
6860 format %{ "MOV$cmp $pcc,$src,$dst" %}
6861 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6862 ins_pipe(ialu_imm);
6863 %}
6864
6865 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6866 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6867 ins_cost(150);
6868 size(4);
6869 format %{ "MOV$cmp $icc,$src,$dst" %}
6870 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6871 ins_pipe(ialu_reg);
6872 %}
6873
6874 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6875 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6876 ins_cost(140);
6877 size(4);
6878 format %{ "MOV$cmp $icc,$src,$dst" %}
6879 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6880 ins_pipe(ialu_imm);
6881 %}
6882
6883 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6884 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6885 ins_cost(150);
6886 size(4);
6887 format %{ "MOV$cmp $icc,$src,$dst" %}
6888 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6889 ins_pipe(ialu_reg);
6890 %}
6891
6892 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6893 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6894 ins_cost(140);
6895 size(4);
6896 format %{ "MOV$cmp $icc,$src,$dst" %}
6897 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6898 ins_pipe(ialu_imm);
6899 %}
6900
6901 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6902 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6903 ins_cost(150);
6904 size(4);
6905 format %{ "MOV$cmp $fcc,$src,$dst" %}
6906 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6907 ins_pipe(ialu_reg);
6908 %}
6909
6910 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6911 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6912 ins_cost(140);
6913 size(4);
6914 format %{ "MOV$cmp $fcc,$src,$dst" %}
6915 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6916 ins_pipe(ialu_imm);
6917 %}
6918
6919 // Conditional move for RegN. Only cmov(reg,reg).
6920 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6921 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6922 ins_cost(150);
6923 format %{ "MOV$cmp $pcc,$src,$dst" %}
6924 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6925 ins_pipe(ialu_reg);
6926 %}
6927
6928 // This instruction also works with CmpN so we don't need cmovNN_reg.
6929 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6930 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6931 ins_cost(150);
6932 size(4);
6933 format %{ "MOV$cmp $icc,$src,$dst" %}
6934 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6935 ins_pipe(ialu_reg);
6936 %}
6937
6938 // This instruction also works with CmpN so we don't need cmovNN_reg.
6939 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6940 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6941 ins_cost(150);
6942 size(4);
6943 format %{ "MOV$cmp $icc,$src,$dst" %}
6944 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6945 ins_pipe(ialu_reg);
6946 %}
6947
6948 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6949 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6950 ins_cost(150);
6951 size(4);
6952 format %{ "MOV$cmp $fcc,$src,$dst" %}
6953 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6954 ins_pipe(ialu_reg);
6955 %}
6956
6957 // Conditional move
6958 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6959 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6960 ins_cost(150);
6961 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6962 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6963 ins_pipe(ialu_reg);
6964 %}
6965
6966 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6967 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6968 ins_cost(140);
6969 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6970 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6971 ins_pipe(ialu_imm);
6972 %}
6973
6974 // This instruction also works with CmpN so we don't need cmovPN_reg.
6975 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6976 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6977 ins_cost(150);
6978
6979 size(4);
6980 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6981 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6982 ins_pipe(ialu_reg);
6983 %}
6984
6985 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6986 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6987 ins_cost(150);
6988
6989 size(4);
6990 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6991 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6992 ins_pipe(ialu_reg);
6993 %}
6994
6995 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6996 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6997 ins_cost(140);
6998
6999 size(4);
7000 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
7001 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7002 ins_pipe(ialu_imm);
7003 %}
7004
7005 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
7006 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
7007 ins_cost(140);
7008
7009 size(4);
7010 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
7011 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
7012 ins_pipe(ialu_imm);
7013 %}
7014
7015 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
7016 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7017 ins_cost(150);
7018 size(4);
7019 format %{ "MOV$cmp $fcc,$src,$dst" %}
7020 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7021 ins_pipe(ialu_imm);
7022 %}
7023
7024 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
7025 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7026 ins_cost(140);
7027 size(4);
7028 format %{ "MOV$cmp $fcc,$src,$dst" %}
7029 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
7030 ins_pipe(ialu_imm);
7031 %}
7032
7033 // Conditional move
7034 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7035 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7036 ins_cost(150);
7037 opcode(0x101);
7038 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7039 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7040 ins_pipe(int_conditional_float_move);
7041 %}
7042
7043 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7044 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7045 ins_cost(150);
7046
7047 size(4);
7048 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7049 opcode(0x101);
7050 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7051 ins_pipe(int_conditional_float_move);
7052 %}
7053
7054 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7055 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7056 ins_cost(150);
7057
7058 size(4);
7059 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7060 opcode(0x101);
7061 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7062 ins_pipe(int_conditional_float_move);
7063 %}
7064
7065 // Conditional move,
7066 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7067 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7068 ins_cost(150);
7069 size(4);
7070 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7071 opcode(0x1);
7072 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7073 ins_pipe(int_conditional_double_move);
7074 %}
7075
7076 // Conditional move
7077 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7078 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7079 ins_cost(150);
7080 size(4);
7081 opcode(0x102);
7082 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7083 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7084 ins_pipe(int_conditional_double_move);
7085 %}
7086
7087 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7088 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7089 ins_cost(150);
7090
7091 size(4);
7092 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7093 opcode(0x102);
7094 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7095 ins_pipe(int_conditional_double_move);
7096 %}
7097
7098 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7099 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7100 ins_cost(150);
7101
7102 size(4);
7103 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7104 opcode(0x102);
7105 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7106 ins_pipe(int_conditional_double_move);
7107 %}
7108
7109 // Conditional move,
7110 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7111 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7112 ins_cost(150);
7113 size(4);
7114 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7115 opcode(0x2);
7116 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7117 ins_pipe(int_conditional_double_move);
7118 %}
7119
7120 // Conditional move
7121 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7122 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7123 ins_cost(150);
7124 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7125 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7126 ins_pipe(ialu_reg);
7127 %}
7128
7129 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7130 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7131 ins_cost(140);
7132 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7133 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7134 ins_pipe(ialu_imm);
7135 %}
7136
7137 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7138 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7139 ins_cost(150);
7140
7141 size(4);
7142 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7143 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7144 ins_pipe(ialu_reg);
7145 %}
7146
7147
7148 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7149 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7150 ins_cost(150);
7151
7152 size(4);
7153 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7154 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7155 ins_pipe(ialu_reg);
7156 %}
7157
7158
7159 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7160 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7161 ins_cost(150);
7162
7163 size(4);
7164 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7165 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7166 ins_pipe(ialu_reg);
7167 %}
7168
7169
7170
7171 //----------OS and Locking Instructions----------------------------------------
7172
7173 // This name is KNOWN by the ADLC and cannot be changed.
7174 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7175 // for this guy.
7176 instruct tlsLoadP(g2RegP dst) %{
7177 match(Set dst (ThreadLocal));
7178
7179 size(0);
7180 ins_cost(0);
7181 format %{ "# TLS is in G2" %}
7182 ins_encode( /*empty encoding*/ );
7183 ins_pipe(ialu_none);
7184 %}
7185
7186 instruct checkCastPP( iRegP dst ) %{
7187 match(Set dst (CheckCastPP dst));
7188
7189 size(0);
7190 format %{ "# checkcastPP of $dst" %}
7191 ins_encode( /*empty encoding*/ );
7192 ins_pipe(empty);
7193 %}
7194
7195
7196 instruct castPP( iRegP dst ) %{
7197 match(Set dst (CastPP dst));
7198 format %{ "# castPP of $dst" %}
7199 ins_encode( /*empty encoding*/ );
7200 ins_pipe(empty);
7201 %}
7202
7203 instruct castII( iRegI dst ) %{
7204 match(Set dst (CastII dst));
7205 format %{ "# castII of $dst" %}
7206 ins_encode( /*empty encoding*/ );
7207 ins_cost(0);
7208 ins_pipe(empty);
7209 %}
7210
7211 //----------Arithmetic Instructions--------------------------------------------
7212 // Addition Instructions
7213 // Register Addition
7214 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7215 match(Set dst (AddI src1 src2));
7216
7217 size(4);
7218 format %{ "ADD $src1,$src2,$dst" %}
7219 ins_encode %{
7220 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7221 %}
7222 ins_pipe(ialu_reg_reg);
7223 %}
7224
7225 // Immediate Addition
7226 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7227 match(Set dst (AddI src1 src2));
7228
7229 size(4);
7230 format %{ "ADD $src1,$src2,$dst" %}
7231 opcode(Assembler::add_op3, Assembler::arith_op);
7232 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7233 ins_pipe(ialu_reg_imm);
7234 %}
7235
7236 // Pointer Register Addition
7237 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7238 match(Set dst (AddP src1 src2));
7239
7240 size(4);
7241 format %{ "ADD $src1,$src2,$dst" %}
7242 opcode(Assembler::add_op3, Assembler::arith_op);
7243 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7244 ins_pipe(ialu_reg_reg);
7245 %}
7246
7247 // Pointer Immediate Addition
7248 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7249 match(Set dst (AddP src1 src2));
7250
7251 size(4);
7252 format %{ "ADD $src1,$src2,$dst" %}
7253 opcode(Assembler::add_op3, Assembler::arith_op);
7254 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7255 ins_pipe(ialu_reg_imm);
7256 %}
7257
7258 // Long Addition
7259 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7260 match(Set dst (AddL src1 src2));
7261
7262 size(4);
7263 format %{ "ADD $src1,$src2,$dst\t! long" %}
7264 opcode(Assembler::add_op3, Assembler::arith_op);
7265 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7266 ins_pipe(ialu_reg_reg);
7267 %}
7268
7269 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7270 match(Set dst (AddL src1 con));
7271
7272 size(4);
7273 format %{ "ADD $src1,$con,$dst" %}
7274 opcode(Assembler::add_op3, Assembler::arith_op);
7275 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7276 ins_pipe(ialu_reg_imm);
7277 %}
7278
7279 //----------Conditional_store--------------------------------------------------
7280 // Conditional-store of the updated heap-top.
7281 // Used during allocation of the shared heap.
7282 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7283
7284 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7285 instruct loadPLocked(iRegP dst, memory mem) %{
7286 match(Set dst (LoadPLocked mem));
7287 ins_cost(MEMORY_REF_COST);
7288
7289 #ifndef _LP64
7290 size(4);
7291 format %{ "LDUW $mem,$dst\t! ptr" %}
7292 opcode(Assembler::lduw_op3, 0, REGP_OP);
7293 #else
7294 format %{ "LDX $mem,$dst\t! ptr" %}
7295 opcode(Assembler::ldx_op3, 0, REGP_OP);
7296 #endif
7297 ins_encode( form3_mem_reg( mem, dst ) );
7298 ins_pipe(iload_mem);
7299 %}
7300
7301 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7302 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7303 effect( KILL newval );
7304 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7305 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7306 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7307 ins_pipe( long_memory_op );
7308 %}
7309
7310 // Conditional-store of an int value.
7311 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7312 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7313 effect( KILL newval );
7314 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7315 "CMP $oldval,$newval\t\t! See if we made progress" %}
7316 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7317 ins_pipe( long_memory_op );
7318 %}
7319
7320 // Conditional-store of a long value.
7321 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7322 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7323 effect( KILL newval );
7324 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7325 "CMP $oldval,$newval\t\t! See if we made progress" %}
7326 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7327 ins_pipe( long_memory_op );
7328 %}
7329
7330 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7331
7332 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7333 predicate(VM_Version::supports_cx8());
7334 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7335 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7336 format %{
7337 "MOV $newval,O7\n\t"
7338 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7339 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7340 "MOV 1,$res\n\t"
7341 "MOVne xcc,R_G0,$res"
7342 %}
7343 ins_encode( enc_casx(mem_ptr, oldval, newval),
7344 enc_lflags_ne_to_boolean(res) );
7345 ins_pipe( long_memory_op );
7346 %}
7347
7348
7349 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7350 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7351 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7352 format %{
7353 "MOV $newval,O7\n\t"
7354 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7355 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7356 "MOV 1,$res\n\t"
7357 "MOVne icc,R_G0,$res"
7358 %}
7359 ins_encode( enc_casi(mem_ptr, oldval, newval),
7360 enc_iflags_ne_to_boolean(res) );
7361 ins_pipe( long_memory_op );
7362 %}
7363
7364 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7365 #ifdef _LP64
7366 predicate(VM_Version::supports_cx8());
7367 #endif
7368 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7369 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7370 format %{
7371 "MOV $newval,O7\n\t"
7372 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7373 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7374 "MOV 1,$res\n\t"
7375 "MOVne xcc,R_G0,$res"
7376 %}
7377 #ifdef _LP64
7378 ins_encode( enc_casx(mem_ptr, oldval, newval),
7379 enc_lflags_ne_to_boolean(res) );
7380 #else
7381 ins_encode( enc_casi(mem_ptr, oldval, newval),
7382 enc_iflags_ne_to_boolean(res) );
7383 #endif
7384 ins_pipe( long_memory_op );
7385 %}
7386
7387 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7388 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7389 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7390 format %{
7391 "MOV $newval,O7\n\t"
7392 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7393 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7394 "MOV 1,$res\n\t"
7395 "MOVne icc,R_G0,$res"
7396 %}
7397 ins_encode( enc_casi(mem_ptr, oldval, newval),
7398 enc_iflags_ne_to_boolean(res) );
7399 ins_pipe( long_memory_op );
7400 %}
7401
7402 instruct xchgI( memory mem, iRegI newval) %{
7403 match(Set newval (GetAndSetI mem newval));
7404 format %{ "SWAP [$mem],$newval" %}
7405 size(4);
7406 ins_encode %{
7407 __ swap($mem$$Address, $newval$$Register);
7408 %}
7409 ins_pipe( long_memory_op );
7410 %}
7411
7412 #ifndef _LP64
7413 instruct xchgP( memory mem, iRegP newval) %{
7414 match(Set newval (GetAndSetP mem newval));
7415 format %{ "SWAP [$mem],$newval" %}
7416 size(4);
7417 ins_encode %{
7418 __ swap($mem$$Address, $newval$$Register);
7419 %}
7420 ins_pipe( long_memory_op );
7421 %}
7422 #endif
7423
7424 instruct xchgN( memory mem, iRegN newval) %{
7425 match(Set newval (GetAndSetN mem newval));
7426 format %{ "SWAP [$mem],$newval" %}
7427 size(4);
7428 ins_encode %{
7429 __ swap($mem$$Address, $newval$$Register);
7430 %}
7431 ins_pipe( long_memory_op );
7432 %}
7433
7434 //---------------------
7435 // Subtraction Instructions
7436 // Register Subtraction
7437 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7438 match(Set dst (SubI src1 src2));
7439
7440 size(4);
7441 format %{ "SUB $src1,$src2,$dst" %}
7442 opcode(Assembler::sub_op3, Assembler::arith_op);
7443 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7444 ins_pipe(ialu_reg_reg);
7445 %}
7446
7447 // Immediate Subtraction
7448 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7449 match(Set dst (SubI src1 src2));
7450
7451 size(4);
7452 format %{ "SUB $src1,$src2,$dst" %}
7453 opcode(Assembler::sub_op3, Assembler::arith_op);
7454 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7455 ins_pipe(ialu_reg_imm);
7456 %}
7457
7458 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7459 match(Set dst (SubI zero src2));
7460
7461 size(4);
7462 format %{ "NEG $src2,$dst" %}
7463 opcode(Assembler::sub_op3, Assembler::arith_op);
7464 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7465 ins_pipe(ialu_zero_reg);
7466 %}
7467
7468 // Long subtraction
7469 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7470 match(Set dst (SubL src1 src2));
7471
7472 size(4);
7473 format %{ "SUB $src1,$src2,$dst\t! long" %}
7474 opcode(Assembler::sub_op3, Assembler::arith_op);
7475 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7476 ins_pipe(ialu_reg_reg);
7477 %}
7478
7479 // Immediate Subtraction
7480 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7481 match(Set dst (SubL src1 con));
7482
7483 size(4);
7484 format %{ "SUB $src1,$con,$dst\t! long" %}
7485 opcode(Assembler::sub_op3, Assembler::arith_op);
7486 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7487 ins_pipe(ialu_reg_imm);
7488 %}
7489
7490 // Long negation
7491 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7492 match(Set dst (SubL zero src2));
7493
7494 size(4);
7495 format %{ "NEG $src2,$dst\t! long" %}
7496 opcode(Assembler::sub_op3, Assembler::arith_op);
7497 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7498 ins_pipe(ialu_zero_reg);
7499 %}
7500
7501 // Multiplication Instructions
7502 // Integer Multiplication
7503 // Register Multiplication
7504 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7505 match(Set dst (MulI src1 src2));
7506
7507 size(4);
7508 format %{ "MULX $src1,$src2,$dst" %}
7509 opcode(Assembler::mulx_op3, Assembler::arith_op);
7510 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7511 ins_pipe(imul_reg_reg);
7512 %}
7513
7514 // Immediate Multiplication
7515 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7516 match(Set dst (MulI src1 src2));
7517
7518 size(4);
7519 format %{ "MULX $src1,$src2,$dst" %}
7520 opcode(Assembler::mulx_op3, Assembler::arith_op);
7521 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7522 ins_pipe(imul_reg_imm);
7523 %}
7524
7525 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7526 match(Set dst (MulL src1 src2));
7527 ins_cost(DEFAULT_COST * 5);
7528 size(4);
7529 format %{ "MULX $src1,$src2,$dst\t! long" %}
7530 opcode(Assembler::mulx_op3, Assembler::arith_op);
7531 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7532 ins_pipe(mulL_reg_reg);
7533 %}
7534
7535 // Immediate Multiplication
7536 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7537 match(Set dst (MulL src1 src2));
7538 ins_cost(DEFAULT_COST * 5);
7539 size(4);
7540 format %{ "MULX $src1,$src2,$dst" %}
7541 opcode(Assembler::mulx_op3, Assembler::arith_op);
7542 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7543 ins_pipe(mulL_reg_imm);
7544 %}
7545
7546 // Integer Division
7547 // Register Division
7548 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7549 match(Set dst (DivI src1 src2));
7550 ins_cost((2+71)*DEFAULT_COST);
7551
7552 format %{ "SRA $src2,0,$src2\n\t"
7553 "SRA $src1,0,$src1\n\t"
7554 "SDIVX $src1,$src2,$dst" %}
7555 ins_encode( idiv_reg( src1, src2, dst ) );
7556 ins_pipe(sdiv_reg_reg);
7557 %}
7558
7559 // Immediate Division
7560 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7561 match(Set dst (DivI src1 src2));
7562 ins_cost((2+71)*DEFAULT_COST);
7563
7564 format %{ "SRA $src1,0,$src1\n\t"
7565 "SDIVX $src1,$src2,$dst" %}
7566 ins_encode( idiv_imm( src1, src2, dst ) );
7567 ins_pipe(sdiv_reg_imm);
7568 %}
7569
7570 //----------Div-By-10-Expansion------------------------------------------------
7571 // Extract hi bits of a 32x32->64 bit multiply.
7572 // Expand rule only, not matched
7573 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7574 effect( DEF dst, USE src1, USE src2 );
7575 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7576 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7577 ins_encode( enc_mul_hi(dst,src1,src2));
7578 ins_pipe(sdiv_reg_reg);
7579 %}
7580
7581 // Magic constant, reciprocal of 10
7582 instruct loadConI_x66666667(iRegIsafe dst) %{
7583 effect( DEF dst );
7584
7585 size(8);
7586 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7587 ins_encode( Set32(0x66666667, dst) );
7588 ins_pipe(ialu_hi_lo_reg);
7589 %}
7590
7591 // Register Shift Right Arithmetic Long by 32-63
7592 instruct sra_31( iRegI dst, iRegI src ) %{
7593 effect( DEF dst, USE src );
7594 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7595 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7596 ins_pipe(ialu_reg_reg);
7597 %}
7598
7599 // Arithmetic Shift Right by 8-bit immediate
7600 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7601 effect( DEF dst, USE src );
7602 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7603 opcode(Assembler::sra_op3, Assembler::arith_op);
7604 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7605 ins_pipe(ialu_reg_imm);
7606 %}
7607
7608 // Integer DIV with 10
7609 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7610 match(Set dst (DivI src div));
7611 ins_cost((6+6)*DEFAULT_COST);
7612 expand %{
7613 iRegIsafe tmp1; // Killed temps;
7614 iRegIsafe tmp2; // Killed temps;
7615 iRegI tmp3; // Killed temps;
7616 iRegI tmp4; // Killed temps;
7617 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7618 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7619 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7620 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7621 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7622 %}
7623 %}
7624
7625 // Register Long Division
7626 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7627 match(Set dst (DivL src1 src2));
7628 ins_cost(DEFAULT_COST*71);
7629 size(4);
7630 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7631 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7632 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7633 ins_pipe(divL_reg_reg);
7634 %}
7635
7636 // Register Long Division
7637 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7638 match(Set dst (DivL src1 src2));
7639 ins_cost(DEFAULT_COST*71);
7640 size(4);
7641 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7642 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7643 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7644 ins_pipe(divL_reg_imm);
7645 %}
7646
7647 // Integer Remainder
7648 // Register Remainder
7649 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7650 match(Set dst (ModI src1 src2));
7651 effect( KILL ccr, KILL temp);
7652
7653 format %{ "SREM $src1,$src2,$dst" %}
7654 ins_encode( irem_reg(src1, src2, dst, temp) );
7655 ins_pipe(sdiv_reg_reg);
7656 %}
7657
7658 // Immediate Remainder
7659 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7660 match(Set dst (ModI src1 src2));
7661 effect( KILL ccr, KILL temp);
7662
7663 format %{ "SREM $src1,$src2,$dst" %}
7664 ins_encode( irem_imm(src1, src2, dst, temp) );
7665 ins_pipe(sdiv_reg_imm);
7666 %}
7667
7668 // Register Long Remainder
7669 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7670 effect(DEF dst, USE src1, USE src2);
7671 size(4);
7672 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7673 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7674 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7675 ins_pipe(divL_reg_reg);
7676 %}
7677
7678 // Register Long Division
7679 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7680 effect(DEF dst, USE src1, USE src2);
7681 size(4);
7682 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7683 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7684 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7685 ins_pipe(divL_reg_imm);
7686 %}
7687
7688 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7689 effect(DEF dst, USE src1, USE src2);
7690 size(4);
7691 format %{ "MULX $src1,$src2,$dst\t! long" %}
7692 opcode(Assembler::mulx_op3, Assembler::arith_op);
7693 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7694 ins_pipe(mulL_reg_reg);
7695 %}
7696
7697 // Immediate Multiplication
7698 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7699 effect(DEF dst, USE src1, USE src2);
7700 size(4);
7701 format %{ "MULX $src1,$src2,$dst" %}
7702 opcode(Assembler::mulx_op3, Assembler::arith_op);
7703 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7704 ins_pipe(mulL_reg_imm);
7705 %}
7706
7707 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7708 effect(DEF dst, USE src1, USE src2);
7709 size(4);
7710 format %{ "SUB $src1,$src2,$dst\t! long" %}
7711 opcode(Assembler::sub_op3, Assembler::arith_op);
7712 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7713 ins_pipe(ialu_reg_reg);
7714 %}
7715
7716 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7717 effect(DEF dst, USE src1, USE src2);
7718 size(4);
7719 format %{ "SUB $src1,$src2,$dst\t! long" %}
7720 opcode(Assembler::sub_op3, Assembler::arith_op);
7721 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7722 ins_pipe(ialu_reg_reg);
7723 %}
7724
7725 // Register Long Remainder
7726 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7727 match(Set dst (ModL src1 src2));
7728 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7729 expand %{
7730 iRegL tmp1;
7731 iRegL tmp2;
7732 divL_reg_reg_1(tmp1, src1, src2);
7733 mulL_reg_reg_1(tmp2, tmp1, src2);
7734 subL_reg_reg_1(dst, src1, tmp2);
7735 %}
7736 %}
7737
7738 // Register Long Remainder
7739 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7740 match(Set dst (ModL src1 src2));
7741 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7742 expand %{
7743 iRegL tmp1;
7744 iRegL tmp2;
7745 divL_reg_imm13_1(tmp1, src1, src2);
7746 mulL_reg_imm13_1(tmp2, tmp1, src2);
7747 subL_reg_reg_2 (dst, src1, tmp2);
7748 %}
7749 %}
7750
7751 // Integer Shift Instructions
7752 // Register Shift Left
7753 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7754 match(Set dst (LShiftI src1 src2));
7755
7756 size(4);
7757 format %{ "SLL $src1,$src2,$dst" %}
7758 opcode(Assembler::sll_op3, Assembler::arith_op);
7759 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7760 ins_pipe(ialu_reg_reg);
7761 %}
7762
7763 // Register Shift Left Immediate
7764 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7765 match(Set dst (LShiftI src1 src2));
7766
7767 size(4);
7768 format %{ "SLL $src1,$src2,$dst" %}
7769 opcode(Assembler::sll_op3, Assembler::arith_op);
7770 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7771 ins_pipe(ialu_reg_imm);
7772 %}
7773
7774 // Register Shift Left
7775 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7776 match(Set dst (LShiftL src1 src2));
7777
7778 size(4);
7779 format %{ "SLLX $src1,$src2,$dst" %}
7780 opcode(Assembler::sllx_op3, Assembler::arith_op);
7781 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7782 ins_pipe(ialu_reg_reg);
7783 %}
7784
7785 // Register Shift Left Immediate
7786 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7787 match(Set dst (LShiftL src1 src2));
7788
7789 size(4);
7790 format %{ "SLLX $src1,$src2,$dst" %}
7791 opcode(Assembler::sllx_op3, Assembler::arith_op);
7792 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7793 ins_pipe(ialu_reg_imm);
7794 %}
7795
7796 // Register Arithmetic Shift Right
7797 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7798 match(Set dst (RShiftI src1 src2));
7799 size(4);
7800 format %{ "SRA $src1,$src2,$dst" %}
7801 opcode(Assembler::sra_op3, Assembler::arith_op);
7802 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7803 ins_pipe(ialu_reg_reg);
7804 %}
7805
7806 // Register Arithmetic Shift Right Immediate
7807 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7808 match(Set dst (RShiftI src1 src2));
7809
7810 size(4);
7811 format %{ "SRA $src1,$src2,$dst" %}
7812 opcode(Assembler::sra_op3, Assembler::arith_op);
7813 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7814 ins_pipe(ialu_reg_imm);
7815 %}
7816
7817 // Register Shift Right Arithmatic Long
7818 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7819 match(Set dst (RShiftL src1 src2));
7820
7821 size(4);
7822 format %{ "SRAX $src1,$src2,$dst" %}
7823 opcode(Assembler::srax_op3, Assembler::arith_op);
7824 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7825 ins_pipe(ialu_reg_reg);
7826 %}
7827
7828 // Register Shift Left Immediate
7829 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7830 match(Set dst (RShiftL src1 src2));
7831
7832 size(4);
7833 format %{ "SRAX $src1,$src2,$dst" %}
7834 opcode(Assembler::srax_op3, Assembler::arith_op);
7835 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7836 ins_pipe(ialu_reg_imm);
7837 %}
7838
7839 // Register Shift Right
7840 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7841 match(Set dst (URShiftI src1 src2));
7842
7843 size(4);
7844 format %{ "SRL $src1,$src2,$dst" %}
7845 opcode(Assembler::srl_op3, Assembler::arith_op);
7846 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7847 ins_pipe(ialu_reg_reg);
7848 %}
7849
7850 // Register Shift Right Immediate
7851 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7852 match(Set dst (URShiftI src1 src2));
7853
7854 size(4);
7855 format %{ "SRL $src1,$src2,$dst" %}
7856 opcode(Assembler::srl_op3, Assembler::arith_op);
7857 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7858 ins_pipe(ialu_reg_imm);
7859 %}
7860
7861 // Register Shift Right
7862 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7863 match(Set dst (URShiftL src1 src2));
7864
7865 size(4);
7866 format %{ "SRLX $src1,$src2,$dst" %}
7867 opcode(Assembler::srlx_op3, Assembler::arith_op);
7868 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7869 ins_pipe(ialu_reg_reg);
7870 %}
7871
7872 // Register Shift Right Immediate
7873 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7874 match(Set dst (URShiftL src1 src2));
7875
7876 size(4);
7877 format %{ "SRLX $src1,$src2,$dst" %}
7878 opcode(Assembler::srlx_op3, Assembler::arith_op);
7879 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7880 ins_pipe(ialu_reg_imm);
7881 %}
7882
7883 // Register Shift Right Immediate with a CastP2X
7884 #ifdef _LP64
7885 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7886 match(Set dst (URShiftL (CastP2X src1) src2));
7887 size(4);
7888 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7889 opcode(Assembler::srlx_op3, Assembler::arith_op);
7890 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7891 ins_pipe(ialu_reg_imm);
7892 %}
7893 #else
7894 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7895 match(Set dst (URShiftI (CastP2X src1) src2));
7896 size(4);
7897 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7898 opcode(Assembler::srl_op3, Assembler::arith_op);
7899 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7900 ins_pipe(ialu_reg_imm);
7901 %}
7902 #endif
7903
7904
7905 //----------Floating Point Arithmetic Instructions-----------------------------
7906
7907 // Add float single precision
7908 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7909 match(Set dst (AddF src1 src2));
7910
7911 size(4);
7912 format %{ "FADDS $src1,$src2,$dst" %}
7913 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7914 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7915 ins_pipe(faddF_reg_reg);
7916 %}
7917
7918 // Add float double precision
7919 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7920 match(Set dst (AddD src1 src2));
7921
7922 size(4);
7923 format %{ "FADDD $src1,$src2,$dst" %}
7924 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7925 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7926 ins_pipe(faddD_reg_reg);
7927 %}
7928
7929 // Sub float single precision
7930 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7931 match(Set dst (SubF src1 src2));
7932
7933 size(4);
7934 format %{ "FSUBS $src1,$src2,$dst" %}
7935 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7936 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7937 ins_pipe(faddF_reg_reg);
7938 %}
7939
7940 // Sub float double precision
7941 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7942 match(Set dst (SubD src1 src2));
7943
7944 size(4);
7945 format %{ "FSUBD $src1,$src2,$dst" %}
7946 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7947 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7948 ins_pipe(faddD_reg_reg);
7949 %}
7950
7951 // Mul float single precision
7952 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7953 match(Set dst (MulF src1 src2));
7954
7955 size(4);
7956 format %{ "FMULS $src1,$src2,$dst" %}
7957 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7958 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7959 ins_pipe(fmulF_reg_reg);
7960 %}
7961
7962 // Mul float double precision
7963 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7964 match(Set dst (MulD src1 src2));
7965
7966 size(4);
7967 format %{ "FMULD $src1,$src2,$dst" %}
7968 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7969 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7970 ins_pipe(fmulD_reg_reg);
7971 %}
7972
7973 // Div float single precision
7974 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7975 match(Set dst (DivF src1 src2));
7976
7977 size(4);
7978 format %{ "FDIVS $src1,$src2,$dst" %}
7979 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7980 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7981 ins_pipe(fdivF_reg_reg);
7982 %}
7983
7984 // Div float double precision
7985 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7986 match(Set dst (DivD src1 src2));
7987
7988 size(4);
7989 format %{ "FDIVD $src1,$src2,$dst" %}
7990 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7991 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7992 ins_pipe(fdivD_reg_reg);
7993 %}
7994
7995 // Absolute float double precision
7996 instruct absD_reg(regD dst, regD src) %{
7997 match(Set dst (AbsD src));
7998
7999 format %{ "FABSd $src,$dst" %}
8000 ins_encode(fabsd(dst, src));
8001 ins_pipe(faddD_reg);
8002 %}
8003
8004 // Absolute float single precision
8005 instruct absF_reg(regF dst, regF src) %{
8006 match(Set dst (AbsF src));
8007
8008 format %{ "FABSs $src,$dst" %}
8009 ins_encode(fabss(dst, src));
8010 ins_pipe(faddF_reg);
8011 %}
8012
8013 instruct negF_reg(regF dst, regF src) %{
8014 match(Set dst (NegF src));
8015
8016 size(4);
8017 format %{ "FNEGs $src,$dst" %}
8018 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
8019 ins_encode(form3_opf_rs2F_rdF(src, dst));
8020 ins_pipe(faddF_reg);
8021 %}
8022
8023 instruct negD_reg(regD dst, regD src) %{
8024 match(Set dst (NegD src));
8025
8026 format %{ "FNEGd $src,$dst" %}
8027 ins_encode(fnegd(dst, src));
8028 ins_pipe(faddD_reg);
8029 %}
8030
8031 // Sqrt float double precision
8032 instruct sqrtF_reg_reg(regF dst, regF src) %{
8033 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8034
8035 size(4);
8036 format %{ "FSQRTS $src,$dst" %}
8037 ins_encode(fsqrts(dst, src));
8038 ins_pipe(fdivF_reg_reg);
8039 %}
8040
8041 // Sqrt float double precision
8042 instruct sqrtD_reg_reg(regD dst, regD src) %{
8043 match(Set dst (SqrtD src));
8044
8045 size(4);
8046 format %{ "FSQRTD $src,$dst" %}
8047 ins_encode(fsqrtd(dst, src));
8048 ins_pipe(fdivD_reg_reg);
8049 %}
8050
8051 //----------Logical Instructions-----------------------------------------------
8052 // And Instructions
8053 // Register And
8054 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8055 match(Set dst (AndI src1 src2));
8056
8057 size(4);
8058 format %{ "AND $src1,$src2,$dst" %}
8059 opcode(Assembler::and_op3, Assembler::arith_op);
8060 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8061 ins_pipe(ialu_reg_reg);
8062 %}
8063
8064 // Immediate And
8065 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8066 match(Set dst (AndI src1 src2));
8067
8068 size(4);
8069 format %{ "AND $src1,$src2,$dst" %}
8070 opcode(Assembler::and_op3, Assembler::arith_op);
8071 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8072 ins_pipe(ialu_reg_imm);
8073 %}
8074
8075 // Register And Long
8076 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8077 match(Set dst (AndL src1 src2));
8078
8079 ins_cost(DEFAULT_COST);
8080 size(4);
8081 format %{ "AND $src1,$src2,$dst\t! long" %}
8082 opcode(Assembler::and_op3, Assembler::arith_op);
8083 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8084 ins_pipe(ialu_reg_reg);
8085 %}
8086
8087 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8088 match(Set dst (AndL src1 con));
8089
8090 ins_cost(DEFAULT_COST);
8091 size(4);
8092 format %{ "AND $src1,$con,$dst\t! long" %}
8093 opcode(Assembler::and_op3, Assembler::arith_op);
8094 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8095 ins_pipe(ialu_reg_imm);
8096 %}
8097
8098 // Or Instructions
8099 // Register Or
8100 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8101 match(Set dst (OrI src1 src2));
8102
8103 size(4);
8104 format %{ "OR $src1,$src2,$dst" %}
8105 opcode(Assembler::or_op3, Assembler::arith_op);
8106 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8107 ins_pipe(ialu_reg_reg);
8108 %}
8109
8110 // Immediate Or
8111 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8112 match(Set dst (OrI src1 src2));
8113
8114 size(4);
8115 format %{ "OR $src1,$src2,$dst" %}
8116 opcode(Assembler::or_op3, Assembler::arith_op);
8117 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8118 ins_pipe(ialu_reg_imm);
8119 %}
8120
8121 // Register Or Long
8122 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8123 match(Set dst (OrL src1 src2));
8124
8125 ins_cost(DEFAULT_COST);
8126 size(4);
8127 format %{ "OR $src1,$src2,$dst\t! long" %}
8128 opcode(Assembler::or_op3, Assembler::arith_op);
8129 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8134 match(Set dst (OrL src1 con));
8135 ins_cost(DEFAULT_COST*2);
8136
8137 ins_cost(DEFAULT_COST);
8138 size(4);
8139 format %{ "OR $src1,$con,$dst\t! long" %}
8140 opcode(Assembler::or_op3, Assembler::arith_op);
8141 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8142 ins_pipe(ialu_reg_imm);
8143 %}
8144
8145 #ifndef _LP64
8146
8147 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8148 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8149 match(Set dst (OrI src1 (CastP2X src2)));
8150
8151 size(4);
8152 format %{ "OR $src1,$src2,$dst" %}
8153 opcode(Assembler::or_op3, Assembler::arith_op);
8154 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8155 ins_pipe(ialu_reg_reg);
8156 %}
8157
8158 #else
8159
8160 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8161 match(Set dst (OrL src1 (CastP2X src2)));
8162
8163 ins_cost(DEFAULT_COST);
8164 size(4);
8165 format %{ "OR $src1,$src2,$dst\t! long" %}
8166 opcode(Assembler::or_op3, Assembler::arith_op);
8167 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8168 ins_pipe(ialu_reg_reg);
8169 %}
8170
8171 #endif
8172
8173 // Xor Instructions
8174 // Register Xor
8175 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8176 match(Set dst (XorI src1 src2));
8177
8178 size(4);
8179 format %{ "XOR $src1,$src2,$dst" %}
8180 opcode(Assembler::xor_op3, Assembler::arith_op);
8181 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8182 ins_pipe(ialu_reg_reg);
8183 %}
8184
8185 // Immediate Xor
8186 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8187 match(Set dst (XorI src1 src2));
8188
8189 size(4);
8190 format %{ "XOR $src1,$src2,$dst" %}
8191 opcode(Assembler::xor_op3, Assembler::arith_op);
8192 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8193 ins_pipe(ialu_reg_imm);
8194 %}
8195
8196 // Register Xor Long
8197 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8198 match(Set dst (XorL src1 src2));
8199
8200 ins_cost(DEFAULT_COST);
8201 size(4);
8202 format %{ "XOR $src1,$src2,$dst\t! long" %}
8203 opcode(Assembler::xor_op3, Assembler::arith_op);
8204 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8205 ins_pipe(ialu_reg_reg);
8206 %}
8207
8208 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8209 match(Set dst (XorL src1 con));
8210
8211 ins_cost(DEFAULT_COST);
8212 size(4);
8213 format %{ "XOR $src1,$con,$dst\t! long" %}
8214 opcode(Assembler::xor_op3, Assembler::arith_op);
8215 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8216 ins_pipe(ialu_reg_imm);
8217 %}
8218
8219 //----------Convert to Boolean-------------------------------------------------
8220 // Nice hack for 32-bit tests but doesn't work for
8221 // 64-bit pointers.
8222 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8223 match(Set dst (Conv2B src));
8224 effect( KILL ccr );
8225 ins_cost(DEFAULT_COST*2);
8226 format %{ "CMP R_G0,$src\n\t"
8227 "ADDX R_G0,0,$dst" %}
8228 ins_encode( enc_to_bool( src, dst ) );
8229 ins_pipe(ialu_reg_ialu);
8230 %}
8231
8232 #ifndef _LP64
8233 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8234 match(Set dst (Conv2B src));
8235 effect( KILL ccr );
8236 ins_cost(DEFAULT_COST*2);
8237 format %{ "CMP R_G0,$src\n\t"
8238 "ADDX R_G0,0,$dst" %}
8239 ins_encode( enc_to_bool( src, dst ) );
8240 ins_pipe(ialu_reg_ialu);
8241 %}
8242 #else
8243 instruct convP2B( iRegI dst, iRegP src ) %{
8244 match(Set dst (Conv2B src));
8245 ins_cost(DEFAULT_COST*2);
8246 format %{ "MOV $src,$dst\n\t"
8247 "MOVRNZ $src,1,$dst" %}
8248 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8249 ins_pipe(ialu_clr_and_mover);
8250 %}
8251 #endif
8252
8253 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8254 match(Set dst (CmpLTMask src zero));
8255 effect(KILL ccr);
8256 size(4);
8257 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8258 ins_encode %{
8259 __ sra($src$$Register, 31, $dst$$Register);
8260 %}
8261 ins_pipe(ialu_reg_imm);
8262 %}
8263
8264 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8265 match(Set dst (CmpLTMask p q));
8266 effect( KILL ccr );
8267 ins_cost(DEFAULT_COST*4);
8268 format %{ "CMP $p,$q\n\t"
8269 "MOV #0,$dst\n\t"
8270 "BLT,a .+8\n\t"
8271 "MOV #-1,$dst" %}
8272 ins_encode( enc_ltmask(p,q,dst) );
8273 ins_pipe(ialu_reg_reg_ialu);
8274 %}
8275
8276 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8277 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8278 effect(KILL ccr, TEMP tmp);
8279 ins_cost(DEFAULT_COST*3);
8280
8281 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8282 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8283 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8284 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
8285 ins_pipe( cadd_cmpltmask );
8286 %}
8287
8288
8289 //-----------------------------------------------------------------
8290 // Direct raw moves between float and general registers using VIS3.
8291
8292 // ins_pipe(faddF_reg);
8293 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8294 predicate(UseVIS >= 3);
8295 match(Set dst (MoveF2I src));
8296
8297 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8298 ins_encode %{
8299 __ movstouw($src$$FloatRegister, $dst$$Register);
8300 %}
8301 ins_pipe(ialu_reg_reg);
8302 %}
8303
8304 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8305 predicate(UseVIS >= 3);
8306 match(Set dst (MoveI2F src));
8307
8308 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8309 ins_encode %{
8310 __ movwtos($src$$Register, $dst$$FloatRegister);
8311 %}
8312 ins_pipe(ialu_reg_reg);
8313 %}
8314
8315 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8316 predicate(UseVIS >= 3);
8317 match(Set dst (MoveD2L src));
8318
8319 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8320 ins_encode %{
8321 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8322 %}
8323 ins_pipe(ialu_reg_reg);
8324 %}
8325
8326 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8327 predicate(UseVIS >= 3);
8328 match(Set dst (MoveL2D src));
8329
8330 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8331 ins_encode %{
8332 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8333 %}
8334 ins_pipe(ialu_reg_reg);
8335 %}
8336
8337
8338 // Raw moves between float and general registers using stack.
8339
8340 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8341 match(Set dst (MoveF2I src));
8342 effect(DEF dst, USE src);
8343 ins_cost(MEMORY_REF_COST);
8344
8345 size(4);
8346 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8347 opcode(Assembler::lduw_op3);
8348 ins_encode(simple_form3_mem_reg( src, dst ) );
8349 ins_pipe(iload_mem);
8350 %}
8351
8352 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8353 match(Set dst (MoveI2F src));
8354 effect(DEF dst, USE src);
8355 ins_cost(MEMORY_REF_COST);
8356
8357 size(4);
8358 format %{ "LDF $src,$dst\t! MoveI2F" %}
8359 opcode(Assembler::ldf_op3);
8360 ins_encode(simple_form3_mem_reg(src, dst));
8361 ins_pipe(floadF_stk);
8362 %}
8363
8364 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8365 match(Set dst (MoveD2L src));
8366 effect(DEF dst, USE src);
8367 ins_cost(MEMORY_REF_COST);
8368
8369 size(4);
8370 format %{ "LDX $src,$dst\t! MoveD2L" %}
8371 opcode(Assembler::ldx_op3);
8372 ins_encode(simple_form3_mem_reg( src, dst ) );
8373 ins_pipe(iload_mem);
8374 %}
8375
8376 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8377 match(Set dst (MoveL2D src));
8378 effect(DEF dst, USE src);
8379 ins_cost(MEMORY_REF_COST);
8380
8381 size(4);
8382 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8383 opcode(Assembler::lddf_op3);
8384 ins_encode(simple_form3_mem_reg(src, dst));
8385 ins_pipe(floadD_stk);
8386 %}
8387
8388 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8389 match(Set dst (MoveF2I src));
8390 effect(DEF dst, USE src);
8391 ins_cost(MEMORY_REF_COST);
8392
8393 size(4);
8394 format %{ "STF $src,$dst\t! MoveF2I" %}
8395 opcode(Assembler::stf_op3);
8396 ins_encode(simple_form3_mem_reg(dst, src));
8397 ins_pipe(fstoreF_stk_reg);
8398 %}
8399
8400 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8401 match(Set dst (MoveI2F src));
8402 effect(DEF dst, USE src);
8403 ins_cost(MEMORY_REF_COST);
8404
8405 size(4);
8406 format %{ "STW $src,$dst\t! MoveI2F" %}
8407 opcode(Assembler::stw_op3);
8408 ins_encode(simple_form3_mem_reg( dst, src ) );
8409 ins_pipe(istore_mem_reg);
8410 %}
8411
8412 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8413 match(Set dst (MoveD2L src));
8414 effect(DEF dst, USE src);
8415 ins_cost(MEMORY_REF_COST);
8416
8417 size(4);
8418 format %{ "STDF $src,$dst\t! MoveD2L" %}
8419 opcode(Assembler::stdf_op3);
8420 ins_encode(simple_form3_mem_reg(dst, src));
8421 ins_pipe(fstoreD_stk_reg);
8422 %}
8423
8424 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8425 match(Set dst (MoveL2D src));
8426 effect(DEF dst, USE src);
8427 ins_cost(MEMORY_REF_COST);
8428
8429 size(4);
8430 format %{ "STX $src,$dst\t! MoveL2D" %}
8431 opcode(Assembler::stx_op3);
8432 ins_encode(simple_form3_mem_reg( dst, src ) );
8433 ins_pipe(istore_mem_reg);
8434 %}
8435
8436
8437 //----------Arithmetic Conversion Instructions---------------------------------
8438 // The conversions operations are all Alpha sorted. Please keep it that way!
8439
8440 instruct convD2F_reg(regF dst, regD src) %{
8441 match(Set dst (ConvD2F src));
8442 size(4);
8443 format %{ "FDTOS $src,$dst" %}
8444 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8445 ins_encode(form3_opf_rs2D_rdF(src, dst));
8446 ins_pipe(fcvtD2F);
8447 %}
8448
8449
8450 // Convert a double to an int in a float register.
8451 // If the double is a NAN, stuff a zero in instead.
8452 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8453 effect(DEF dst, USE src, KILL fcc0);
8454 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8455 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8456 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8457 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8458 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8459 "skip:" %}
8460 ins_encode(form_d2i_helper(src,dst));
8461 ins_pipe(fcvtD2I);
8462 %}
8463
8464 instruct convD2I_stk(stackSlotI dst, regD src) %{
8465 match(Set dst (ConvD2I src));
8466 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8467 expand %{
8468 regF tmp;
8469 convD2I_helper(tmp, src);
8470 regF_to_stkI(dst, tmp);
8471 %}
8472 %}
8473
8474 instruct convD2I_reg(iRegI dst, regD src) %{
8475 predicate(UseVIS >= 3);
8476 match(Set dst (ConvD2I src));
8477 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8478 expand %{
8479 regF tmp;
8480 convD2I_helper(tmp, src);
8481 MoveF2I_reg_reg(dst, tmp);
8482 %}
8483 %}
8484
8485
8486 // Convert a double to a long in a double register.
8487 // If the double is a NAN, stuff a zero in instead.
8488 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8489 effect(DEF dst, USE src, KILL fcc0);
8490 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8491 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8492 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8493 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8494 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8495 "skip:" %}
8496 ins_encode(form_d2l_helper(src,dst));
8497 ins_pipe(fcvtD2L);
8498 %}
8499
8500 instruct convD2L_stk(stackSlotL dst, regD src) %{
8501 match(Set dst (ConvD2L src));
8502 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8503 expand %{
8504 regD tmp;
8505 convD2L_helper(tmp, src);
8506 regD_to_stkL(dst, tmp);
8507 %}
8508 %}
8509
8510 instruct convD2L_reg(iRegL dst, regD src) %{
8511 predicate(UseVIS >= 3);
8512 match(Set dst (ConvD2L src));
8513 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8514 expand %{
8515 regD tmp;
8516 convD2L_helper(tmp, src);
8517 MoveD2L_reg_reg(dst, tmp);
8518 %}
8519 %}
8520
8521
8522 instruct convF2D_reg(regD dst, regF src) %{
8523 match(Set dst (ConvF2D src));
8524 format %{ "FSTOD $src,$dst" %}
8525 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8526 ins_encode(form3_opf_rs2F_rdD(src, dst));
8527 ins_pipe(fcvtF2D);
8528 %}
8529
8530
8531 // Convert a float to an int in a float register.
8532 // If the float is a NAN, stuff a zero in instead.
8533 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8534 effect(DEF dst, USE src, KILL fcc0);
8535 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8536 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8537 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8538 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8539 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8540 "skip:" %}
8541 ins_encode(form_f2i_helper(src,dst));
8542 ins_pipe(fcvtF2I);
8543 %}
8544
8545 instruct convF2I_stk(stackSlotI dst, regF src) %{
8546 match(Set dst (ConvF2I src));
8547 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8548 expand %{
8549 regF tmp;
8550 convF2I_helper(tmp, src);
8551 regF_to_stkI(dst, tmp);
8552 %}
8553 %}
8554
8555 instruct convF2I_reg(iRegI dst, regF src) %{
8556 predicate(UseVIS >= 3);
8557 match(Set dst (ConvF2I src));
8558 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8559 expand %{
8560 regF tmp;
8561 convF2I_helper(tmp, src);
8562 MoveF2I_reg_reg(dst, tmp);
8563 %}
8564 %}
8565
8566
8567 // Convert a float to a long in a float register.
8568 // If the float is a NAN, stuff a zero in instead.
8569 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8570 effect(DEF dst, USE src, KILL fcc0);
8571 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8572 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8573 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8574 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8575 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8576 "skip:" %}
8577 ins_encode(form_f2l_helper(src,dst));
8578 ins_pipe(fcvtF2L);
8579 %}
8580
8581 instruct convF2L_stk(stackSlotL dst, regF src) %{
8582 match(Set dst (ConvF2L src));
8583 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8584 expand %{
8585 regD tmp;
8586 convF2L_helper(tmp, src);
8587 regD_to_stkL(dst, tmp);
8588 %}
8589 %}
8590
8591 instruct convF2L_reg(iRegL dst, regF src) %{
8592 predicate(UseVIS >= 3);
8593 match(Set dst (ConvF2L src));
8594 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8595 expand %{
8596 regD tmp;
8597 convF2L_helper(tmp, src);
8598 MoveD2L_reg_reg(dst, tmp);
8599 %}
8600 %}
8601
8602
8603 instruct convI2D_helper(regD dst, regF tmp) %{
8604 effect(USE tmp, DEF dst);
8605 format %{ "FITOD $tmp,$dst" %}
8606 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8607 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8608 ins_pipe(fcvtI2D);
8609 %}
8610
8611 instruct convI2D_stk(stackSlotI src, regD dst) %{
8612 match(Set dst (ConvI2D src));
8613 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8614 expand %{
8615 regF tmp;
8616 stkI_to_regF(tmp, src);
8617 convI2D_helper(dst, tmp);
8618 %}
8619 %}
8620
8621 instruct convI2D_reg(regD_low dst, iRegI src) %{
8622 predicate(UseVIS >= 3);
8623 match(Set dst (ConvI2D src));
8624 expand %{
8625 regF tmp;
8626 MoveI2F_reg_reg(tmp, src);
8627 convI2D_helper(dst, tmp);
8628 %}
8629 %}
8630
8631 instruct convI2D_mem(regD_low dst, memory mem) %{
8632 match(Set dst (ConvI2D (LoadI mem)));
8633 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8634 size(8);
8635 format %{ "LDF $mem,$dst\n\t"
8636 "FITOD $dst,$dst" %}
8637 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8638 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8639 ins_pipe(floadF_mem);
8640 %}
8641
8642
8643 instruct convI2F_helper(regF dst, regF tmp) %{
8644 effect(DEF dst, USE tmp);
8645 format %{ "FITOS $tmp,$dst" %}
8646 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8647 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8648 ins_pipe(fcvtI2F);
8649 %}
8650
8651 instruct convI2F_stk(regF dst, stackSlotI src) %{
8652 match(Set dst (ConvI2F src));
8653 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8654 expand %{
8655 regF tmp;
8656 stkI_to_regF(tmp,src);
8657 convI2F_helper(dst, tmp);
8658 %}
8659 %}
8660
8661 instruct convI2F_reg(regF dst, iRegI src) %{
8662 predicate(UseVIS >= 3);
8663 match(Set dst (ConvI2F src));
8664 ins_cost(DEFAULT_COST);
8665 expand %{
8666 regF tmp;
8667 MoveI2F_reg_reg(tmp, src);
8668 convI2F_helper(dst, tmp);
8669 %}
8670 %}
8671
8672 instruct convI2F_mem( regF dst, memory mem ) %{
8673 match(Set dst (ConvI2F (LoadI mem)));
8674 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8675 size(8);
8676 format %{ "LDF $mem,$dst\n\t"
8677 "FITOS $dst,$dst" %}
8678 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8679 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8680 ins_pipe(floadF_mem);
8681 %}
8682
8683
8684 instruct convI2L_reg(iRegL dst, iRegI src) %{
8685 match(Set dst (ConvI2L src));
8686 size(4);
8687 format %{ "SRA $src,0,$dst\t! int->long" %}
8688 opcode(Assembler::sra_op3, Assembler::arith_op);
8689 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8690 ins_pipe(ialu_reg_reg);
8691 %}
8692
8693 // Zero-extend convert int to long
8694 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8695 match(Set dst (AndL (ConvI2L src) mask) );
8696 size(4);
8697 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8698 opcode(Assembler::srl_op3, Assembler::arith_op);
8699 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8700 ins_pipe(ialu_reg_reg);
8701 %}
8702
8703 // Zero-extend long
8704 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8705 match(Set dst (AndL src mask) );
8706 size(4);
8707 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8708 opcode(Assembler::srl_op3, Assembler::arith_op);
8709 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8710 ins_pipe(ialu_reg_reg);
8711 %}
8712
8713
8714 //-----------
8715 // Long to Double conversion using V8 opcodes.
8716 // Still useful because cheetah traps and becomes
8717 // amazingly slow for some common numbers.
8718
8719 // Magic constant, 0x43300000
8720 instruct loadConI_x43300000(iRegI dst) %{
8721 effect(DEF dst);
8722 size(4);
8723 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8724 ins_encode(SetHi22(0x43300000, dst));
8725 ins_pipe(ialu_none);
8726 %}
8727
8728 // Magic constant, 0x41f00000
8729 instruct loadConI_x41f00000(iRegI dst) %{
8730 effect(DEF dst);
8731 size(4);
8732 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8733 ins_encode(SetHi22(0x41f00000, dst));
8734 ins_pipe(ialu_none);
8735 %}
8736
8737 // Construct a double from two float halves
8738 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8739 effect(DEF dst, USE src1, USE src2);
8740 size(8);
8741 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8742 "FMOVS $src2.lo,$dst.lo" %}
8743 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8744 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8745 ins_pipe(faddD_reg_reg);
8746 %}
8747
8748 // Convert integer in high half of a double register (in the lower half of
8749 // the double register file) to double
8750 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8751 effect(DEF dst, USE src);
8752 size(4);
8753 format %{ "FITOD $src,$dst" %}
8754 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8755 ins_encode(form3_opf_rs2D_rdD(src, dst));
8756 ins_pipe(fcvtLHi2D);
8757 %}
8758
8759 // Add float double precision
8760 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8761 effect(DEF dst, USE src1, USE src2);
8762 size(4);
8763 format %{ "FADDD $src1,$src2,$dst" %}
8764 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8765 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8766 ins_pipe(faddD_reg_reg);
8767 %}
8768
8769 // Sub float double precision
8770 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8771 effect(DEF dst, USE src1, USE src2);
8772 size(4);
8773 format %{ "FSUBD $src1,$src2,$dst" %}
8774 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8775 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8776 ins_pipe(faddD_reg_reg);
8777 %}
8778
8779 // Mul float double precision
8780 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8781 effect(DEF dst, USE src1, USE src2);
8782 size(4);
8783 format %{ "FMULD $src1,$src2,$dst" %}
8784 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8785 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8786 ins_pipe(fmulD_reg_reg);
8787 %}
8788
8789 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8790 match(Set dst (ConvL2D src));
8791 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8792
8793 expand %{
8794 regD_low tmpsrc;
8795 iRegI ix43300000;
8796 iRegI ix41f00000;
8797 stackSlotL lx43300000;
8798 stackSlotL lx41f00000;
8799 regD_low dx43300000;
8800 regD dx41f00000;
8801 regD tmp1;
8802 regD_low tmp2;
8803 regD tmp3;
8804 regD tmp4;
8805
8806 stkL_to_regD(tmpsrc, src);
8807
8808 loadConI_x43300000(ix43300000);
8809 loadConI_x41f00000(ix41f00000);
8810 regI_to_stkLHi(lx43300000, ix43300000);
8811 regI_to_stkLHi(lx41f00000, ix41f00000);
8812 stkL_to_regD(dx43300000, lx43300000);
8813 stkL_to_regD(dx41f00000, lx41f00000);
8814
8815 convI2D_regDHi_regD(tmp1, tmpsrc);
8816 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8817 subD_regD_regD(tmp3, tmp2, dx43300000);
8818 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8819 addD_regD_regD(dst, tmp3, tmp4);
8820 %}
8821 %}
8822
8823 // Long to Double conversion using fast fxtof
8824 instruct convL2D_helper(regD dst, regD tmp) %{
8825 effect(DEF dst, USE tmp);
8826 size(4);
8827 format %{ "FXTOD $tmp,$dst" %}
8828 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8829 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8830 ins_pipe(fcvtL2D);
8831 %}
8832
8833 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8834 predicate(VM_Version::has_fast_fxtof());
8835 match(Set dst (ConvL2D src));
8836 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8837 expand %{
8838 regD tmp;
8839 stkL_to_regD(tmp, src);
8840 convL2D_helper(dst, tmp);
8841 %}
8842 %}
8843
8844 instruct convL2D_reg(regD dst, iRegL src) %{
8845 predicate(UseVIS >= 3);
8846 match(Set dst (ConvL2D src));
8847 expand %{
8848 regD tmp;
8849 MoveL2D_reg_reg(tmp, src);
8850 convL2D_helper(dst, tmp);
8851 %}
8852 %}
8853
8854 // Long to Float conversion using fast fxtof
8855 instruct convL2F_helper(regF dst, regD tmp) %{
8856 effect(DEF dst, USE tmp);
8857 size(4);
8858 format %{ "FXTOS $tmp,$dst" %}
8859 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8860 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8861 ins_pipe(fcvtL2F);
8862 %}
8863
8864 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8865 match(Set dst (ConvL2F src));
8866 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8867 expand %{
8868 regD tmp;
8869 stkL_to_regD(tmp, src);
8870 convL2F_helper(dst, tmp);
8871 %}
8872 %}
8873
8874 instruct convL2F_reg(regF dst, iRegL src) %{
8875 predicate(UseVIS >= 3);
8876 match(Set dst (ConvL2F src));
8877 ins_cost(DEFAULT_COST);
8878 expand %{
8879 regD tmp;
8880 MoveL2D_reg_reg(tmp, src);
8881 convL2F_helper(dst, tmp);
8882 %}
8883 %}
8884
8885 //-----------
8886
8887 instruct convL2I_reg(iRegI dst, iRegL src) %{
8888 match(Set dst (ConvL2I src));
8889 #ifndef _LP64
8890 format %{ "MOV $src.lo,$dst\t! long->int" %}
8891 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8892 ins_pipe(ialu_move_reg_I_to_L);
8893 #else
8894 size(4);
8895 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8896 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8897 ins_pipe(ialu_reg);
8898 #endif
8899 %}
8900
8901 // Register Shift Right Immediate
8902 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8903 match(Set dst (ConvL2I (RShiftL src cnt)));
8904
8905 size(4);
8906 format %{ "SRAX $src,$cnt,$dst" %}
8907 opcode(Assembler::srax_op3, Assembler::arith_op);
8908 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8909 ins_pipe(ialu_reg_imm);
8910 %}
8911
8912 //----------Control Flow Instructions------------------------------------------
8913 // Compare Instructions
8914 // Compare Integers
8915 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8916 match(Set icc (CmpI op1 op2));
8917 effect( DEF icc, USE op1, USE op2 );
8918
8919 size(4);
8920 format %{ "CMP $op1,$op2" %}
8921 opcode(Assembler::subcc_op3, Assembler::arith_op);
8922 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8923 ins_pipe(ialu_cconly_reg_reg);
8924 %}
8925
8926 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8927 match(Set icc (CmpU op1 op2));
8928
8929 size(4);
8930 format %{ "CMP $op1,$op2\t! unsigned" %}
8931 opcode(Assembler::subcc_op3, Assembler::arith_op);
8932 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8933 ins_pipe(ialu_cconly_reg_reg);
8934 %}
8935
8936 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8937 match(Set icc (CmpI op1 op2));
8938 effect( DEF icc, USE op1 );
8939
8940 size(4);
8941 format %{ "CMP $op1,$op2" %}
8942 opcode(Assembler::subcc_op3, Assembler::arith_op);
8943 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8944 ins_pipe(ialu_cconly_reg_imm);
8945 %}
8946
8947 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8948 match(Set icc (CmpI (AndI op1 op2) zero));
8949
8950 size(4);
8951 format %{ "BTST $op2,$op1" %}
8952 opcode(Assembler::andcc_op3, Assembler::arith_op);
8953 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8954 ins_pipe(ialu_cconly_reg_reg_zero);
8955 %}
8956
8957 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8958 match(Set icc (CmpI (AndI op1 op2) zero));
8959
8960 size(4);
8961 format %{ "BTST $op2,$op1" %}
8962 opcode(Assembler::andcc_op3, Assembler::arith_op);
8963 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8964 ins_pipe(ialu_cconly_reg_imm_zero);
8965 %}
8966
8967 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8968 match(Set xcc (CmpL op1 op2));
8969 effect( DEF xcc, USE op1, USE op2 );
8970
8971 size(4);
8972 format %{ "CMP $op1,$op2\t\t! long" %}
8973 opcode(Assembler::subcc_op3, Assembler::arith_op);
8974 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8975 ins_pipe(ialu_cconly_reg_reg);
8976 %}
8977
8978 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8979 match(Set xcc (CmpL op1 con));
8980 effect( DEF xcc, USE op1, USE con );
8981
8982 size(4);
8983 format %{ "CMP $op1,$con\t\t! long" %}
8984 opcode(Assembler::subcc_op3, Assembler::arith_op);
8985 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8986 ins_pipe(ialu_cconly_reg_reg);
8987 %}
8988
8989 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8990 match(Set xcc (CmpL (AndL op1 op2) zero));
8991 effect( DEF xcc, USE op1, USE op2 );
8992
8993 size(4);
8994 format %{ "BTST $op1,$op2\t\t! long" %}
8995 opcode(Assembler::andcc_op3, Assembler::arith_op);
8996 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8997 ins_pipe(ialu_cconly_reg_reg);
8998 %}
8999
9000 // useful for checking the alignment of a pointer:
9001 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9002 match(Set xcc (CmpL (AndL op1 con) zero));
9003 effect( DEF xcc, USE op1, USE con );
9004
9005 size(4);
9006 format %{ "BTST $op1,$con\t\t! long" %}
9007 opcode(Assembler::andcc_op3, Assembler::arith_op);
9008 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9009 ins_pipe(ialu_cconly_reg_reg);
9010 %}
9011
9012 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
9013 match(Set icc (CmpU op1 op2));
9014
9015 size(4);
9016 format %{ "CMP $op1,$op2\t! unsigned" %}
9017 opcode(Assembler::subcc_op3, Assembler::arith_op);
9018 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9019 ins_pipe(ialu_cconly_reg_imm);
9020 %}
9021
9022 // Compare Pointers
9023 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9024 match(Set pcc (CmpP op1 op2));
9025
9026 size(4);
9027 format %{ "CMP $op1,$op2\t! ptr" %}
9028 opcode(Assembler::subcc_op3, Assembler::arith_op);
9029 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9030 ins_pipe(ialu_cconly_reg_reg);
9031 %}
9032
9033 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9034 match(Set pcc (CmpP op1 op2));
9035
9036 size(4);
9037 format %{ "CMP $op1,$op2\t! ptr" %}
9038 opcode(Assembler::subcc_op3, Assembler::arith_op);
9039 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9040 ins_pipe(ialu_cconly_reg_imm);
9041 %}
9042
9043 // Compare Narrow oops
9044 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9045 match(Set icc (CmpN op1 op2));
9046
9047 size(4);
9048 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9049 opcode(Assembler::subcc_op3, Assembler::arith_op);
9050 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9051 ins_pipe(ialu_cconly_reg_reg);
9052 %}
9053
9054 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9055 match(Set icc (CmpN op1 op2));
9056
9057 size(4);
9058 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9059 opcode(Assembler::subcc_op3, Assembler::arith_op);
9060 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9061 ins_pipe(ialu_cconly_reg_imm);
9062 %}
9063
9064 //----------Max and Min--------------------------------------------------------
9065 // Min Instructions
9066 // Conditional move for min
9067 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9068 effect( USE_DEF op2, USE op1, USE icc );
9069
9070 size(4);
9071 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9072 opcode(Assembler::less);
9073 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9074 ins_pipe(ialu_reg_flags);
9075 %}
9076
9077 // Min Register with Register.
9078 instruct minI_eReg(iRegI op1, iRegI op2) %{
9079 match(Set op2 (MinI op1 op2));
9080 ins_cost(DEFAULT_COST*2);
9081 expand %{
9082 flagsReg icc;
9083 compI_iReg(icc,op1,op2);
9084 cmovI_reg_lt(op2,op1,icc);
9085 %}
9086 %}
9087
9088 // Max Instructions
9089 // Conditional move for max
9090 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9091 effect( USE_DEF op2, USE op1, USE icc );
9092 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9093 opcode(Assembler::greater);
9094 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9095 ins_pipe(ialu_reg_flags);
9096 %}
9097
9098 // Max Register with Register
9099 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9100 match(Set op2 (MaxI op1 op2));
9101 ins_cost(DEFAULT_COST*2);
9102 expand %{
9103 flagsReg icc;
9104 compI_iReg(icc,op1,op2);
9105 cmovI_reg_gt(op2,op1,icc);
9106 %}
9107 %}
9108
9109
9110 //----------Float Compares----------------------------------------------------
9111 // Compare floating, generate condition code
9112 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9113 match(Set fcc (CmpF src1 src2));
9114
9115 size(4);
9116 format %{ "FCMPs $fcc,$src1,$src2" %}
9117 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9118 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9119 ins_pipe(faddF_fcc_reg_reg_zero);
9120 %}
9121
9122 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9123 match(Set fcc (CmpD src1 src2));
9124
9125 size(4);
9126 format %{ "FCMPd $fcc,$src1,$src2" %}
9127 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9128 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9129 ins_pipe(faddD_fcc_reg_reg_zero);
9130 %}
9131
9132
9133 // Compare floating, generate -1,0,1
9134 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9135 match(Set dst (CmpF3 src1 src2));
9136 effect(KILL fcc0);
9137 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9138 format %{ "fcmpl $dst,$src1,$src2" %}
9139 // Primary = float
9140 opcode( true );
9141 ins_encode( floating_cmp( dst, src1, src2 ) );
9142 ins_pipe( floating_cmp );
9143 %}
9144
9145 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9146 match(Set dst (CmpD3 src1 src2));
9147 effect(KILL fcc0);
9148 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9149 format %{ "dcmpl $dst,$src1,$src2" %}
9150 // Primary = double (not float)
9151 opcode( false );
9152 ins_encode( floating_cmp( dst, src1, src2 ) );
9153 ins_pipe( floating_cmp );
9154 %}
9155
9156 //----------Branches---------------------------------------------------------
9157 // Jump
9158 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9159 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9160 match(Jump switch_val);
9161 effect(TEMP table);
9162
9163 ins_cost(350);
9164
9165 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9166 "LD [O7 + $switch_val], O7\n\t"
9167 "JUMP O7" %}
9168 ins_encode %{
9169 // Calculate table address into a register.
9170 Register table_reg;
9171 Register label_reg = O7;
9172 // If we are calculating the size of this instruction don't trust
9173 // zero offsets because they might change when
9174 // MachConstantBaseNode decides to optimize the constant table
9175 // base.
9176 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9177 table_reg = $constanttablebase;
9178 } else {
9179 table_reg = O7;
9180 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9181 __ add($constanttablebase, con_offset, table_reg);
9182 }
9183
9184 // Jump to base address + switch value
9185 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9186 __ jmp(label_reg, G0);
9187 __ delayed()->nop();
9188 %}
9189 ins_pipe(ialu_reg_reg);
9190 %}
9191
9192 // Direct Branch. Use V8 version with longer range.
9193 instruct branch(label labl) %{
9194 match(Goto);
9195 effect(USE labl);
9196
9197 size(8);
9198 ins_cost(BRANCH_COST);
9199 format %{ "BA $labl" %}
9200 ins_encode %{
9201 Label* L = $labl$$label;
9202 __ ba(*L);
9203 __ delayed()->nop();
9204 %}
9205 ins_pipe(br);
9206 %}
9207
9208 // Direct Branch, short with no delay slot
9209 instruct branch_short(label labl) %{
9210 match(Goto);
9211 predicate(UseCBCond);
9212 effect(USE labl);
9213
9214 size(4);
9215 ins_cost(BRANCH_COST);
9216 format %{ "BA $labl\t! short branch" %}
9217 ins_encode %{
9218 Label* L = $labl$$label;
9219 assert(__ use_cbcond(*L), "back to back cbcond");
9220 __ ba_short(*L);
9221 %}
9222 ins_short_branch(1);
9223 ins_avoid_back_to_back(1);
9224 ins_pipe(cbcond_reg_imm);
9225 %}
9226
9227 // Conditional Direct Branch
9228 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9229 match(If cmp icc);
9230 effect(USE labl);
9231
9232 size(8);
9233 ins_cost(BRANCH_COST);
9234 format %{ "BP$cmp $icc,$labl" %}
9235 // Prim = bits 24-22, Secnd = bits 31-30
9236 ins_encode( enc_bp( labl, cmp, icc ) );
9237 ins_pipe(br_cc);
9238 %}
9239
9240 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9241 match(If cmp icc);
9242 effect(USE labl);
9243
9244 ins_cost(BRANCH_COST);
9245 format %{ "BP$cmp $icc,$labl" %}
9246 // Prim = bits 24-22, Secnd = bits 31-30
9247 ins_encode( enc_bp( labl, cmp, icc ) );
9248 ins_pipe(br_cc);
9249 %}
9250
9251 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9252 match(If cmp pcc);
9253 effect(USE labl);
9254
9255 size(8);
9256 ins_cost(BRANCH_COST);
9257 format %{ "BP$cmp $pcc,$labl" %}
9258 ins_encode %{
9259 Label* L = $labl$$label;
9260 Assembler::Predict predict_taken =
9261 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9262
9263 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9264 __ delayed()->nop();
9265 %}
9266 ins_pipe(br_cc);
9267 %}
9268
9269 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9270 match(If cmp fcc);
9271 effect(USE labl);
9272
9273 size(8);
9274 ins_cost(BRANCH_COST);
9275 format %{ "FBP$cmp $fcc,$labl" %}
9276 ins_encode %{
9277 Label* L = $labl$$label;
9278 Assembler::Predict predict_taken =
9279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9280
9281 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9282 __ delayed()->nop();
9283 %}
9284 ins_pipe(br_fcc);
9285 %}
9286
9287 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9288 match(CountedLoopEnd cmp icc);
9289 effect(USE labl);
9290
9291 size(8);
9292 ins_cost(BRANCH_COST);
9293 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9294 // Prim = bits 24-22, Secnd = bits 31-30
9295 ins_encode( enc_bp( labl, cmp, icc ) );
9296 ins_pipe(br_cc);
9297 %}
9298
9299 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9300 match(CountedLoopEnd cmp icc);
9301 effect(USE labl);
9302
9303 size(8);
9304 ins_cost(BRANCH_COST);
9305 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9306 // Prim = bits 24-22, Secnd = bits 31-30
9307 ins_encode( enc_bp( labl, cmp, icc ) );
9308 ins_pipe(br_cc);
9309 %}
9310
9311 // Compare and branch instructions
9312 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9313 match(If cmp (CmpI op1 op2));
9314 effect(USE labl, KILL icc);
9315
9316 size(12);
9317 ins_cost(BRANCH_COST);
9318 format %{ "CMP $op1,$op2\t! int\n\t"
9319 "BP$cmp $labl" %}
9320 ins_encode %{
9321 Label* L = $labl$$label;
9322 Assembler::Predict predict_taken =
9323 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9324 __ cmp($op1$$Register, $op2$$Register);
9325 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9326 __ delayed()->nop();
9327 %}
9328 ins_pipe(cmp_br_reg_reg);
9329 %}
9330
9331 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9332 match(If cmp (CmpI op1 op2));
9333 effect(USE labl, KILL icc);
9334
9335 size(12);
9336 ins_cost(BRANCH_COST);
9337 format %{ "CMP $op1,$op2\t! int\n\t"
9338 "BP$cmp $labl" %}
9339 ins_encode %{
9340 Label* L = $labl$$label;
9341 Assembler::Predict predict_taken =
9342 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9343 __ cmp($op1$$Register, $op2$$constant);
9344 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9345 __ delayed()->nop();
9346 %}
9347 ins_pipe(cmp_br_reg_imm);
9348 %}
9349
9350 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9351 match(If cmp (CmpU op1 op2));
9352 effect(USE labl, KILL icc);
9353
9354 size(12);
9355 ins_cost(BRANCH_COST);
9356 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9357 "BP$cmp $labl" %}
9358 ins_encode %{
9359 Label* L = $labl$$label;
9360 Assembler::Predict predict_taken =
9361 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9362 __ cmp($op1$$Register, $op2$$Register);
9363 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9364 __ delayed()->nop();
9365 %}
9366 ins_pipe(cmp_br_reg_reg);
9367 %}
9368
9369 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9370 match(If cmp (CmpU op1 op2));
9371 effect(USE labl, KILL icc);
9372
9373 size(12);
9374 ins_cost(BRANCH_COST);
9375 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9376 "BP$cmp $labl" %}
9377 ins_encode %{
9378 Label* L = $labl$$label;
9379 Assembler::Predict predict_taken =
9380 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9381 __ cmp($op1$$Register, $op2$$constant);
9382 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9383 __ delayed()->nop();
9384 %}
9385 ins_pipe(cmp_br_reg_imm);
9386 %}
9387
9388 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9389 match(If cmp (CmpL op1 op2));
9390 effect(USE labl, KILL xcc);
9391
9392 size(12);
9393 ins_cost(BRANCH_COST);
9394 format %{ "CMP $op1,$op2\t! long\n\t"
9395 "BP$cmp $labl" %}
9396 ins_encode %{
9397 Label* L = $labl$$label;
9398 Assembler::Predict predict_taken =
9399 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9400 __ cmp($op1$$Register, $op2$$Register);
9401 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9402 __ delayed()->nop();
9403 %}
9404 ins_pipe(cmp_br_reg_reg);
9405 %}
9406
9407 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9408 match(If cmp (CmpL op1 op2));
9409 effect(USE labl, KILL xcc);
9410
9411 size(12);
9412 ins_cost(BRANCH_COST);
9413 format %{ "CMP $op1,$op2\t! long\n\t"
9414 "BP$cmp $labl" %}
9415 ins_encode %{
9416 Label* L = $labl$$label;
9417 Assembler::Predict predict_taken =
9418 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9419 __ cmp($op1$$Register, $op2$$constant);
9420 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9421 __ delayed()->nop();
9422 %}
9423 ins_pipe(cmp_br_reg_imm);
9424 %}
9425
9426 // Compare Pointers and branch
9427 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9428 match(If cmp (CmpP op1 op2));
9429 effect(USE labl, KILL pcc);
9430
9431 size(12);
9432 ins_cost(BRANCH_COST);
9433 format %{ "CMP $op1,$op2\t! ptr\n\t"
9434 "B$cmp $labl" %}
9435 ins_encode %{
9436 Label* L = $labl$$label;
9437 Assembler::Predict predict_taken =
9438 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9439 __ cmp($op1$$Register, $op2$$Register);
9440 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9441 __ delayed()->nop();
9442 %}
9443 ins_pipe(cmp_br_reg_reg);
9444 %}
9445
9446 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9447 match(If cmp (CmpP op1 null));
9448 effect(USE labl, KILL pcc);
9449
9450 size(12);
9451 ins_cost(BRANCH_COST);
9452 format %{ "CMP $op1,0\t! ptr\n\t"
9453 "B$cmp $labl" %}
9454 ins_encode %{
9455 Label* L = $labl$$label;
9456 Assembler::Predict predict_taken =
9457 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9458 __ cmp($op1$$Register, G0);
9459 // bpr() is not used here since it has shorter distance.
9460 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9461 __ delayed()->nop();
9462 %}
9463 ins_pipe(cmp_br_reg_reg);
9464 %}
9465
9466 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9467 match(If cmp (CmpN op1 op2));
9468 effect(USE labl, KILL icc);
9469
9470 size(12);
9471 ins_cost(BRANCH_COST);
9472 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9473 "BP$cmp $labl" %}
9474 ins_encode %{
9475 Label* L = $labl$$label;
9476 Assembler::Predict predict_taken =
9477 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9478 __ cmp($op1$$Register, $op2$$Register);
9479 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9480 __ delayed()->nop();
9481 %}
9482 ins_pipe(cmp_br_reg_reg);
9483 %}
9484
9485 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9486 match(If cmp (CmpN op1 null));
9487 effect(USE labl, KILL icc);
9488
9489 size(12);
9490 ins_cost(BRANCH_COST);
9491 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9492 "BP$cmp $labl" %}
9493 ins_encode %{
9494 Label* L = $labl$$label;
9495 Assembler::Predict predict_taken =
9496 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9497 __ cmp($op1$$Register, G0);
9498 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9499 __ delayed()->nop();
9500 %}
9501 ins_pipe(cmp_br_reg_reg);
9502 %}
9503
9504 // Loop back branch
9505 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9506 match(CountedLoopEnd cmp (CmpI op1 op2));
9507 effect(USE labl, KILL icc);
9508
9509 size(12);
9510 ins_cost(BRANCH_COST);
9511 format %{ "CMP $op1,$op2\t! int\n\t"
9512 "BP$cmp $labl\t! Loop end" %}
9513 ins_encode %{
9514 Label* L = $labl$$label;
9515 Assembler::Predict predict_taken =
9516 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9517 __ cmp($op1$$Register, $op2$$Register);
9518 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9519 __ delayed()->nop();
9520 %}
9521 ins_pipe(cmp_br_reg_reg);
9522 %}
9523
9524 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9525 match(CountedLoopEnd cmp (CmpI op1 op2));
9526 effect(USE labl, KILL icc);
9527
9528 size(12);
9529 ins_cost(BRANCH_COST);
9530 format %{ "CMP $op1,$op2\t! int\n\t"
9531 "BP$cmp $labl\t! Loop end" %}
9532 ins_encode %{
9533 Label* L = $labl$$label;
9534 Assembler::Predict predict_taken =
9535 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9536 __ cmp($op1$$Register, $op2$$constant);
9537 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9538 __ delayed()->nop();
9539 %}
9540 ins_pipe(cmp_br_reg_imm);
9541 %}
9542
9543 // Short compare and branch instructions
9544 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9545 match(If cmp (CmpI op1 op2));
9546 predicate(UseCBCond);
9547 effect(USE labl, KILL icc);
9548
9549 size(4);
9550 ins_cost(BRANCH_COST);
9551 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9552 ins_encode %{
9553 Label* L = $labl$$label;
9554 assert(__ use_cbcond(*L), "back to back cbcond");
9555 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9556 %}
9557 ins_short_branch(1);
9558 ins_avoid_back_to_back(1);
9559 ins_pipe(cbcond_reg_reg);
9560 %}
9561
9562 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9563 match(If cmp (CmpI op1 op2));
9564 predicate(UseCBCond);
9565 effect(USE labl, KILL icc);
9566
9567 size(4);
9568 ins_cost(BRANCH_COST);
9569 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9570 ins_encode %{
9571 Label* L = $labl$$label;
9572 assert(__ use_cbcond(*L), "back to back cbcond");
9573 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9574 %}
9575 ins_short_branch(1);
9576 ins_avoid_back_to_back(1);
9577 ins_pipe(cbcond_reg_imm);
9578 %}
9579
9580 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9581 match(If cmp (CmpU op1 op2));
9582 predicate(UseCBCond);
9583 effect(USE labl, KILL icc);
9584
9585 size(4);
9586 ins_cost(BRANCH_COST);
9587 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9588 ins_encode %{
9589 Label* L = $labl$$label;
9590 assert(__ use_cbcond(*L), "back to back cbcond");
9591 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9592 %}
9593 ins_short_branch(1);
9594 ins_avoid_back_to_back(1);
9595 ins_pipe(cbcond_reg_reg);
9596 %}
9597
9598 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9599 match(If cmp (CmpU op1 op2));
9600 predicate(UseCBCond);
9601 effect(USE labl, KILL icc);
9602
9603 size(4);
9604 ins_cost(BRANCH_COST);
9605 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9606 ins_encode %{
9607 Label* L = $labl$$label;
9608 assert(__ use_cbcond(*L), "back to back cbcond");
9609 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9610 %}
9611 ins_short_branch(1);
9612 ins_avoid_back_to_back(1);
9613 ins_pipe(cbcond_reg_imm);
9614 %}
9615
9616 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9617 match(If cmp (CmpL op1 op2));
9618 predicate(UseCBCond);
9619 effect(USE labl, KILL xcc);
9620
9621 size(4);
9622 ins_cost(BRANCH_COST);
9623 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9624 ins_encode %{
9625 Label* L = $labl$$label;
9626 assert(__ use_cbcond(*L), "back to back cbcond");
9627 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9628 %}
9629 ins_short_branch(1);
9630 ins_avoid_back_to_back(1);
9631 ins_pipe(cbcond_reg_reg);
9632 %}
9633
9634 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9635 match(If cmp (CmpL op1 op2));
9636 predicate(UseCBCond);
9637 effect(USE labl, KILL xcc);
9638
9639 size(4);
9640 ins_cost(BRANCH_COST);
9641 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9642 ins_encode %{
9643 Label* L = $labl$$label;
9644 assert(__ use_cbcond(*L), "back to back cbcond");
9645 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9646 %}
9647 ins_short_branch(1);
9648 ins_avoid_back_to_back(1);
9649 ins_pipe(cbcond_reg_imm);
9650 %}
9651
9652 // Compare Pointers and branch
9653 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9654 match(If cmp (CmpP op1 op2));
9655 predicate(UseCBCond);
9656 effect(USE labl, KILL pcc);
9657
9658 size(4);
9659 ins_cost(BRANCH_COST);
9660 #ifdef _LP64
9661 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9662 #else
9663 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9664 #endif
9665 ins_encode %{
9666 Label* L = $labl$$label;
9667 assert(__ use_cbcond(*L), "back to back cbcond");
9668 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9669 %}
9670 ins_short_branch(1);
9671 ins_avoid_back_to_back(1);
9672 ins_pipe(cbcond_reg_reg);
9673 %}
9674
9675 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9676 match(If cmp (CmpP op1 null));
9677 predicate(UseCBCond);
9678 effect(USE labl, KILL pcc);
9679
9680 size(4);
9681 ins_cost(BRANCH_COST);
9682 #ifdef _LP64
9683 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9684 #else
9685 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9686 #endif
9687 ins_encode %{
9688 Label* L = $labl$$label;
9689 assert(__ use_cbcond(*L), "back to back cbcond");
9690 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9691 %}
9692 ins_short_branch(1);
9693 ins_avoid_back_to_back(1);
9694 ins_pipe(cbcond_reg_reg);
9695 %}
9696
9697 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9698 match(If cmp (CmpN op1 op2));
9699 predicate(UseCBCond);
9700 effect(USE labl, KILL icc);
9701
9702 size(4);
9703 ins_cost(BRANCH_COST);
9704 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %}
9705 ins_encode %{
9706 Label* L = $labl$$label;
9707 assert(__ use_cbcond(*L), "back to back cbcond");
9708 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9709 %}
9710 ins_short_branch(1);
9711 ins_avoid_back_to_back(1);
9712 ins_pipe(cbcond_reg_reg);
9713 %}
9714
9715 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9716 match(If cmp (CmpN op1 null));
9717 predicate(UseCBCond);
9718 effect(USE labl, KILL icc);
9719
9720 size(4);
9721 ins_cost(BRANCH_COST);
9722 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9723 ins_encode %{
9724 Label* L = $labl$$label;
9725 assert(__ use_cbcond(*L), "back to back cbcond");
9726 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9727 %}
9728 ins_short_branch(1);
9729 ins_avoid_back_to_back(1);
9730 ins_pipe(cbcond_reg_reg);
9731 %}
9732
9733 // Loop back branch
9734 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9735 match(CountedLoopEnd cmp (CmpI op1 op2));
9736 predicate(UseCBCond);
9737 effect(USE labl, KILL icc);
9738
9739 size(4);
9740 ins_cost(BRANCH_COST);
9741 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9742 ins_encode %{
9743 Label* L = $labl$$label;
9744 assert(__ use_cbcond(*L), "back to back cbcond");
9745 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9746 %}
9747 ins_short_branch(1);
9748 ins_avoid_back_to_back(1);
9749 ins_pipe(cbcond_reg_reg);
9750 %}
9751
9752 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9753 match(CountedLoopEnd cmp (CmpI op1 op2));
9754 predicate(UseCBCond);
9755 effect(USE labl, KILL icc);
9756
9757 size(4);
9758 ins_cost(BRANCH_COST);
9759 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9760 ins_encode %{
9761 Label* L = $labl$$label;
9762 assert(__ use_cbcond(*L), "back to back cbcond");
9763 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9764 %}
9765 ins_short_branch(1);
9766 ins_avoid_back_to_back(1);
9767 ins_pipe(cbcond_reg_imm);
9768 %}
9769
9770 // Branch-on-register tests all 64 bits. We assume that values
9771 // in 64-bit registers always remains zero or sign extended
9772 // unless our code munges the high bits. Interrupts can chop
9773 // the high order bits to zero or sign at any time.
9774 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9775 match(If cmp (CmpI op1 zero));
9776 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9777 effect(USE labl);
9778
9779 size(8);
9780 ins_cost(BRANCH_COST);
9781 format %{ "BR$cmp $op1,$labl" %}
9782 ins_encode( enc_bpr( labl, cmp, op1 ) );
9783 ins_pipe(br_reg);
9784 %}
9785
9786 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9787 match(If cmp (CmpP op1 null));
9788 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9789 effect(USE labl);
9790
9791 size(8);
9792 ins_cost(BRANCH_COST);
9793 format %{ "BR$cmp $op1,$labl" %}
9794 ins_encode( enc_bpr( labl, cmp, op1 ) );
9795 ins_pipe(br_reg);
9796 %}
9797
9798 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9799 match(If cmp (CmpL op1 zero));
9800 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9801 effect(USE labl);
9802
9803 size(8);
9804 ins_cost(BRANCH_COST);
9805 format %{ "BR$cmp $op1,$labl" %}
9806 ins_encode( enc_bpr( labl, cmp, op1 ) );
9807 ins_pipe(br_reg);
9808 %}
9809
9810
9811 // ============================================================================
9812 // Long Compare
9813 //
9814 // Currently we hold longs in 2 registers. Comparing such values efficiently
9815 // is tricky. The flavor of compare used depends on whether we are testing
9816 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9817 // The GE test is the negated LT test. The LE test can be had by commuting
9818 // the operands (yielding a GE test) and then negating; negate again for the
9819 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9820 // NE test is negated from that.
9821
9822 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9823 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9824 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9825 // are collapsed internally in the ADLC's dfa-gen code. The match for
9826 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9827 // foo match ends up with the wrong leaf. One fix is to not match both
9828 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9829 // both forms beat the trinary form of long-compare and both are very useful
9830 // on Intel which has so few registers.
9831
9832 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9833 match(If cmp xcc);
9834 effect(USE labl);
9835
9836 size(8);
9837 ins_cost(BRANCH_COST);
9838 format %{ "BP$cmp $xcc,$labl" %}
9839 ins_encode %{
9840 Label* L = $labl$$label;
9841 Assembler::Predict predict_taken =
9842 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9843
9844 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9845 __ delayed()->nop();
9846 %}
9847 ins_pipe(br_cc);
9848 %}
9849
9850 // Manifest a CmpL3 result in an integer register. Very painful.
9851 // This is the test to avoid.
9852 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9853 match(Set dst (CmpL3 src1 src2) );
9854 effect( KILL ccr );
9855 ins_cost(6*DEFAULT_COST);
9856 size(24);
9857 format %{ "CMP $src1,$src2\t\t! long\n"
9858 "\tBLT,a,pn done\n"
9859 "\tMOV -1,$dst\t! delay slot\n"
9860 "\tBGT,a,pn done\n"
9861 "\tMOV 1,$dst\t! delay slot\n"
9862 "\tCLR $dst\n"
9863 "done:" %}
9864 ins_encode( cmpl_flag(src1,src2,dst) );
9865 ins_pipe(cmpL_reg);
9866 %}
9867
9868 // Conditional move
9869 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9870 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9871 ins_cost(150);
9872 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9873 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9874 ins_pipe(ialu_reg);
9875 %}
9876
9877 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9878 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9879 ins_cost(140);
9880 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9881 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9882 ins_pipe(ialu_imm);
9883 %}
9884
9885 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9886 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9887 ins_cost(150);
9888 format %{ "MOV$cmp $xcc,$src,$dst" %}
9889 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9890 ins_pipe(ialu_reg);
9891 %}
9892
9893 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9894 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9895 ins_cost(140);
9896 format %{ "MOV$cmp $xcc,$src,$dst" %}
9897 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9898 ins_pipe(ialu_imm);
9899 %}
9900
9901 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9902 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9903 ins_cost(150);
9904 format %{ "MOV$cmp $xcc,$src,$dst" %}
9905 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9906 ins_pipe(ialu_reg);
9907 %}
9908
9909 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9910 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9911 ins_cost(150);
9912 format %{ "MOV$cmp $xcc,$src,$dst" %}
9913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9914 ins_pipe(ialu_reg);
9915 %}
9916
9917 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9918 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9919 ins_cost(140);
9920 format %{ "MOV$cmp $xcc,$src,$dst" %}
9921 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9922 ins_pipe(ialu_imm);
9923 %}
9924
9925 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9926 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9927 ins_cost(150);
9928 opcode(0x101);
9929 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9930 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9931 ins_pipe(int_conditional_float_move);
9932 %}
9933
9934 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9935 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9936 ins_cost(150);
9937 opcode(0x102);
9938 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9940 ins_pipe(int_conditional_float_move);
9941 %}
9942
9943 // ============================================================================
9944 // Safepoint Instruction
9945 instruct safePoint_poll(iRegP poll) %{
9946 match(SafePoint poll);
9947 effect(USE poll);
9948
9949 size(4);
9950 #ifdef _LP64
9951 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9952 #else
9953 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9954 #endif
9955 ins_encode %{
9956 __ relocate(relocInfo::poll_type);
9957 __ ld_ptr($poll$$Register, 0, G0);
9958 %}
9959 ins_pipe(loadPollP);
9960 %}
9961
9962 // ============================================================================
9963 // Call Instructions
9964 // Call Java Static Instruction
9965 instruct CallStaticJavaDirect( method meth ) %{
9966 match(CallStaticJava);
9967 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9968 effect(USE meth);
9969
9970 size(8);
9971 ins_cost(CALL_COST);
9972 format %{ "CALL,static ; NOP ==> " %}
9973 ins_encode( Java_Static_Call( meth ), call_epilog );
9974 ins_pipe(simple_call);
9975 %}
9976
9977 // Call Java Static Instruction (method handle version)
9978 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9979 match(CallStaticJava);
9980 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9981 effect(USE meth, KILL l7_mh_SP_save);
9982
9983 size(16);
9984 ins_cost(CALL_COST);
9985 format %{ "CALL,static/MethodHandle" %}
9986 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9987 ins_pipe(simple_call);
9988 %}
9989
9990 // Call Java Dynamic Instruction
9991 instruct CallDynamicJavaDirect( method meth ) %{
9992 match(CallDynamicJava);
9993 effect(USE meth);
9994
9995 ins_cost(CALL_COST);
9996 format %{ "SET (empty),R_G5\n\t"
9997 "CALL,dynamic ; NOP ==> " %}
9998 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9999 ins_pipe(call);
10000 %}
10001
10002 // Call Runtime Instruction
10003 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10004 match(CallRuntime);
10005 effect(USE meth, KILL l7);
10006 ins_cost(CALL_COST);
10007 format %{ "CALL,runtime" %}
10008 ins_encode( Java_To_Runtime( meth ),
10009 call_epilog, adjust_long_from_native_call );
10010 ins_pipe(simple_call);
10011 %}
10012
10013 // Call runtime without safepoint - same as CallRuntime
10014 instruct CallLeafDirect(method meth, l7RegP l7) %{
10015 match(CallLeaf);
10016 effect(USE meth, KILL l7);
10017 ins_cost(CALL_COST);
10018 format %{ "CALL,runtime leaf" %}
10019 ins_encode( Java_To_Runtime( meth ),
10020 call_epilog,
10021 adjust_long_from_native_call );
10022 ins_pipe(simple_call);
10023 %}
10024
10025 // Call runtime without safepoint - same as CallLeaf
10026 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10027 match(CallLeafNoFP);
10028 effect(USE meth, KILL l7);
10029 ins_cost(CALL_COST);
10030 format %{ "CALL,runtime leaf nofp" %}
10031 ins_encode( Java_To_Runtime( meth ),
10032 call_epilog,
10033 adjust_long_from_native_call );
10034 ins_pipe(simple_call);
10035 %}
10036
10037 // Tail Call; Jump from runtime stub to Java code.
10038 // Also known as an 'interprocedural jump'.
10039 // Target of jump will eventually return to caller.
10040 // TailJump below removes the return address.
10041 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10042 match(TailCall jump_target method_oop );
10043
10044 ins_cost(CALL_COST);
10045 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10046 ins_encode(form_jmpl(jump_target));
10047 ins_pipe(tail_call);
10048 %}
10049
10050
10051 // Return Instruction
10052 instruct Ret() %{
10053 match(Return);
10054
10055 // The epilogue node did the ret already.
10056 size(0);
10057 format %{ "! return" %}
10058 ins_encode();
10059 ins_pipe(empty);
10060 %}
10061
10062
10063 // Tail Jump; remove the return address; jump to target.
10064 // TailCall above leaves the return address around.
10065 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10066 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10067 // "restore" before this instruction (in Epilogue), we need to materialize it
10068 // in %i0.
10069 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10070 match( TailJump jump_target ex_oop );
10071 ins_cost(CALL_COST);
10072 format %{ "! discard R_O7\n\t"
10073 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10074 ins_encode(form_jmpl_set_exception_pc(jump_target));
10075 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10076 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10077 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10078 ins_pipe(tail_call);
10079 %}
10080
10081 // Create exception oop: created by stack-crawling runtime code.
10082 // Created exception is now available to this handler, and is setup
10083 // just prior to jumping to this handler. No code emitted.
10084 instruct CreateException( o0RegP ex_oop )
10085 %{
10086 match(Set ex_oop (CreateEx));
10087 ins_cost(0);
10088
10089 size(0);
10090 // use the following format syntax
10091 format %{ "! exception oop is in R_O0; no code emitted" %}
10092 ins_encode();
10093 ins_pipe(empty);
10094 %}
10095
10096
10097 // Rethrow exception:
10098 // The exception oop will come in the first argument position.
10099 // Then JUMP (not call) to the rethrow stub code.
10100 instruct RethrowException()
10101 %{
10102 match(Rethrow);
10103 ins_cost(CALL_COST);
10104
10105 // use the following format syntax
10106 format %{ "Jmp rethrow_stub" %}
10107 ins_encode(enc_rethrow);
10108 ins_pipe(tail_call);
10109 %}
10110
10111
10112 // Die now
10113 instruct ShouldNotReachHere( )
10114 %{
10115 match(Halt);
10116 ins_cost(CALL_COST);
10117
10118 size(4);
10119 // Use the following format syntax
10120 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10121 ins_encode( form2_illtrap() );
10122 ins_pipe(tail_call);
10123 %}
10124
10125 // ============================================================================
10126 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10127 // array for an instance of the superklass. Set a hidden internal cache on a
10128 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10129 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10130 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10131 match(Set index (PartialSubtypeCheck sub super));
10132 effect( KILL pcc, KILL o7 );
10133 ins_cost(DEFAULT_COST*10);
10134 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10135 ins_encode( enc_PartialSubtypeCheck() );
10136 ins_pipe(partial_subtype_check_pipe);
10137 %}
10138
10139 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10140 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10141 effect( KILL idx, KILL o7 );
10142 ins_cost(DEFAULT_COST*10);
10143 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10144 ins_encode( enc_PartialSubtypeCheck() );
10145 ins_pipe(partial_subtype_check_pipe);
10146 %}
10147
10148
10149 // ============================================================================
10150 // inlined locking and unlocking
10151
10152 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10153 match(Set pcc (FastLock object box));
10154
10155 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10156 ins_cost(100);
10157
10158 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10159 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10160 ins_pipe(long_memory_op);
10161 %}
10162
10163
10164 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10165 match(Set pcc (FastUnlock object box));
10166 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10167 ins_cost(100);
10168
10169 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10170 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10171 ins_pipe(long_memory_op);
10172 %}
10173
10174 // The encodings are generic.
10175 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10176 predicate(!use_block_zeroing(n->in(2)) );
10177 match(Set dummy (ClearArray cnt base));
10178 effect(TEMP temp, KILL ccr);
10179 ins_cost(300);
10180 format %{ "MOV $cnt,$temp\n"
10181 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10182 " BRge loop\t\t! Clearing loop\n"
10183 " STX G0,[$base+$temp]\t! delay slot" %}
10184
10185 ins_encode %{
10186 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10187 Register nof_bytes_arg = $cnt$$Register;
10188 Register nof_bytes_tmp = $temp$$Register;
10189 Register base_pointer_arg = $base$$Register;
10190
10191 Label loop;
10192 __ mov(nof_bytes_arg, nof_bytes_tmp);
10193
10194 // Loop and clear, walking backwards through the array.
10195 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10196 __ bind(loop);
10197 __ deccc(nof_bytes_tmp, 8);
10198 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10199 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10200 // %%%% this mini-loop must not cross a cache boundary!
10201 %}
10202 ins_pipe(long_memory_op);
10203 %}
10204
10205 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10206 predicate(use_block_zeroing(n->in(2)));
10207 match(Set dummy (ClearArray cnt base));
10208 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10209 ins_cost(300);
10210 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10211
10212 ins_encode %{
10213
10214 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10215 Register to = $base$$Register;
10216 Register count = $cnt$$Register;
10217
10218 Label Ldone;
10219 __ nop(); // Separate short branches
10220 // Use BIS for zeroing (temp is not used).
10221 __ bis_zeroing(to, count, G0, Ldone);
10222 __ bind(Ldone);
10223
10224 %}
10225 ins_pipe(long_memory_op);
10226 %}
10227
10228 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10229 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10230 match(Set dummy (ClearArray cnt base));
10231 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10232 ins_cost(300);
10233 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10234
10235 ins_encode %{
10236
10237 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10238 Register to = $base$$Register;
10239 Register count = $cnt$$Register;
10240 Register temp = $tmp$$Register;
10241
10242 Label Ldone;
10243 __ nop(); // Separate short branches
10244 // Use BIS for zeroing
10245 __ bis_zeroing(to, count, temp, Ldone);
10246 __ bind(Ldone);
10247
10248 %}
10249 ins_pipe(long_memory_op);
10250 %}
10251
10252 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10253 o7RegI tmp, flagsReg ccr) %{
10254 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10255 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10256 ins_cost(300);
10257 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10258 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10259 ins_pipe(long_memory_op);
10260 %}
10261
10262 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10263 o7RegI tmp, flagsReg ccr) %{
10264 match(Set result (StrEquals (Binary str1 str2) cnt));
10265 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10266 ins_cost(300);
10267 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10268 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10269 ins_pipe(long_memory_op);
10270 %}
10271
10272 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10273 o7RegI tmp2, flagsReg ccr) %{
10274 match(Set result (AryEq ary1 ary2));
10275 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10276 ins_cost(300);
10277 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10278 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10279 ins_pipe(long_memory_op);
10280 %}
10281
10282
10283 //---------- Zeros Count Instructions ------------------------------------------
10284
10285 instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10286 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10287 match(Set dst (CountLeadingZerosI src));
10288 effect(TEMP dst, TEMP tmp, KILL cr);
10289
10290 // x |= (x >> 1);
10291 // x |= (x >> 2);
10292 // x |= (x >> 4);
10293 // x |= (x >> 8);
10294 // x |= (x >> 16);
10295 // return (WORDBITS - popc(x));
10296 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10297 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10298 "OR $dst,$tmp,$dst\n\t"
10299 "SRL $dst,2,$tmp\n\t"
10300 "OR $dst,$tmp,$dst\n\t"
10301 "SRL $dst,4,$tmp\n\t"
10302 "OR $dst,$tmp,$dst\n\t"
10303 "SRL $dst,8,$tmp\n\t"
10304 "OR $dst,$tmp,$dst\n\t"
10305 "SRL $dst,16,$tmp\n\t"
10306 "OR $dst,$tmp,$dst\n\t"
10307 "POPC $dst,$dst\n\t"
10308 "MOV 32,$tmp\n\t"
10309 "SUB $tmp,$dst,$dst" %}
10310 ins_encode %{
10311 Register Rdst = $dst$$Register;
10312 Register Rsrc = $src$$Register;
10313 Register Rtmp = $tmp$$Register;
10314 __ srl(Rsrc, 1, Rtmp);
10315 __ srl(Rsrc, 0, Rdst);
10316 __ or3(Rdst, Rtmp, Rdst);
10317 __ srl(Rdst, 2, Rtmp);
10318 __ or3(Rdst, Rtmp, Rdst);
10319 __ srl(Rdst, 4, Rtmp);
10320 __ or3(Rdst, Rtmp, Rdst);
10321 __ srl(Rdst, 8, Rtmp);
10322 __ or3(Rdst, Rtmp, Rdst);
10323 __ srl(Rdst, 16, Rtmp);
10324 __ or3(Rdst, Rtmp, Rdst);
10325 __ popc(Rdst, Rdst);
10326 __ mov(BitsPerInt, Rtmp);
10327 __ sub(Rtmp, Rdst, Rdst);
10328 %}
10329 ins_pipe(ialu_reg);
10330 %}
10331
10332 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10333 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10334 match(Set dst (CountLeadingZerosL src));
10335 effect(TEMP dst, TEMP tmp, KILL cr);
10336
10337 // x |= (x >> 1);
10338 // x |= (x >> 2);
10339 // x |= (x >> 4);
10340 // x |= (x >> 8);
10341 // x |= (x >> 16);
10342 // x |= (x >> 32);
10343 // return (WORDBITS - popc(x));
10344 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10345 "OR $src,$tmp,$dst\n\t"
10346 "SRLX $dst,2,$tmp\n\t"
10347 "OR $dst,$tmp,$dst\n\t"
10348 "SRLX $dst,4,$tmp\n\t"
10349 "OR $dst,$tmp,$dst\n\t"
10350 "SRLX $dst,8,$tmp\n\t"
10351 "OR $dst,$tmp,$dst\n\t"
10352 "SRLX $dst,16,$tmp\n\t"
10353 "OR $dst,$tmp,$dst\n\t"
10354 "SRLX $dst,32,$tmp\n\t"
10355 "OR $dst,$tmp,$dst\n\t"
10356 "POPC $dst,$dst\n\t"
10357 "MOV 64,$tmp\n\t"
10358 "SUB $tmp,$dst,$dst" %}
10359 ins_encode %{
10360 Register Rdst = $dst$$Register;
10361 Register Rsrc = $src$$Register;
10362 Register Rtmp = $tmp$$Register;
10363 __ srlx(Rsrc, 1, Rtmp);
10364 __ or3( Rsrc, Rtmp, Rdst);
10365 __ srlx(Rdst, 2, Rtmp);
10366 __ or3( Rdst, Rtmp, Rdst);
10367 __ srlx(Rdst, 4, Rtmp);
10368 __ or3( Rdst, Rtmp, Rdst);
10369 __ srlx(Rdst, 8, Rtmp);
10370 __ or3( Rdst, Rtmp, Rdst);
10371 __ srlx(Rdst, 16, Rtmp);
10372 __ or3( Rdst, Rtmp, Rdst);
10373 __ srlx(Rdst, 32, Rtmp);
10374 __ or3( Rdst, Rtmp, Rdst);
10375 __ popc(Rdst, Rdst);
10376 __ mov(BitsPerLong, Rtmp);
10377 __ sub(Rtmp, Rdst, Rdst);
10378 %}
10379 ins_pipe(ialu_reg);
10380 %}
10381
10382 instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
10383 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10384 match(Set dst (CountTrailingZerosI src));
10385 effect(TEMP dst, KILL cr);
10386
10387 // return popc(~x & (x - 1));
10388 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10389 "ANDN $dst,$src,$dst\n\t"
10390 "SRL $dst,R_G0,$dst\n\t"
10391 "POPC $dst,$dst" %}
10392 ins_encode %{
10393 Register Rdst = $dst$$Register;
10394 Register Rsrc = $src$$Register;
10395 __ sub(Rsrc, 1, Rdst);
10396 __ andn(Rdst, Rsrc, Rdst);
10397 __ srl(Rdst, G0, Rdst);
10398 __ popc(Rdst, Rdst);
10399 %}
10400 ins_pipe(ialu_reg);
10401 %}
10402
10403 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10404 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10405 match(Set dst (CountTrailingZerosL src));
10406 effect(TEMP dst, KILL cr);
10407
10408 // return popc(~x & (x - 1));
10409 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10410 "ANDN $dst,$src,$dst\n\t"
10411 "POPC $dst,$dst" %}
10412 ins_encode %{
10413 Register Rdst = $dst$$Register;
10414 Register Rsrc = $src$$Register;
10415 __ sub(Rsrc, 1, Rdst);
10416 __ andn(Rdst, Rsrc, Rdst);
10417 __ popc(Rdst, Rdst);
10418 %}
10419 ins_pipe(ialu_reg);
10420 %}
10421
10422
10423 //---------- Population Count Instructions -------------------------------------
10424
10425 instruct popCountI(iRegI dst, iRegI src) %{
10426 predicate(UsePopCountInstruction);
10427 match(Set dst (PopCountI src));
10428
10429 format %{ "POPC $src, $dst" %}
10430 ins_encode %{
10431 __ popc($src$$Register, $dst$$Register);
10432 %}
10433 ins_pipe(ialu_reg);
10434 %}
10435
10436 // Note: Long.bitCount(long) returns an int.
10437 instruct popCountL(iRegI dst, iRegL src) %{
10438 predicate(UsePopCountInstruction);
10439 match(Set dst (PopCountL src));
10440
10441 format %{ "POPC $src, $dst" %}
10442 ins_encode %{
10443 __ popc($src$$Register, $dst$$Register);
10444 %}
10445 ins_pipe(ialu_reg);
10446 %}
10447
10448
10449 // ============================================================================
10450 //------------Bytes reverse--------------------------------------------------
10451
10452 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10453 match(Set dst (ReverseBytesI src));
10454
10455 // Op cost is artificially doubled to make sure that load or store
10456 // instructions are preferred over this one which requires a spill
10457 // onto a stack slot.
10458 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10459 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10460
10461 ins_encode %{
10462 __ set($src$$disp + STACK_BIAS, O7);
10463 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10464 %}
10465 ins_pipe( iload_mem );
10466 %}
10467
10468 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10469 match(Set dst (ReverseBytesL src));
10470
10471 // Op cost is artificially doubled to make sure that load or store
10472 // instructions are preferred over this one which requires a spill
10473 // onto a stack slot.
10474 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10475 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10476
10477 ins_encode %{
10478 __ set($src$$disp + STACK_BIAS, O7);
10479 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10480 %}
10481 ins_pipe( iload_mem );
10482 %}
10483
10484 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10485 match(Set dst (ReverseBytesUS src));
10486
10487 // Op cost is artificially doubled to make sure that load or store
10488 // instructions are preferred over this one which requires a spill
10489 // onto a stack slot.
10490 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10491 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10492
10493 ins_encode %{
10494 // the value was spilled as an int so bias the load
10495 __ set($src$$disp + STACK_BIAS + 2, O7);
10496 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10497 %}
10498 ins_pipe( iload_mem );
10499 %}
10500
10501 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10502 match(Set dst (ReverseBytesS src));
10503
10504 // Op cost is artificially doubled to make sure that load or store
10505 // instructions are preferred over this one which requires a spill
10506 // onto a stack slot.
10507 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10508 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10509
10510 ins_encode %{
10511 // the value was spilled as an int so bias the load
10512 __ set($src$$disp + STACK_BIAS + 2, O7);
10513 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10514 %}
10515 ins_pipe( iload_mem );
10516 %}
10517
10518 // Load Integer reversed byte order
10519 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10520 match(Set dst (ReverseBytesI (LoadI src)));
10521
10522 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10523 size(4);
10524 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10525
10526 ins_encode %{
10527 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10528 %}
10529 ins_pipe(iload_mem);
10530 %}
10531
10532 // Load Long - aligned and reversed
10533 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10534 match(Set dst (ReverseBytesL (LoadL src)));
10535
10536 ins_cost(MEMORY_REF_COST);
10537 size(4);
10538 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10539
10540 ins_encode %{
10541 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10542 %}
10543 ins_pipe(iload_mem);
10544 %}
10545
10546 // Load unsigned short / char reversed byte order
10547 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10548 match(Set dst (ReverseBytesUS (LoadUS src)));
10549
10550 ins_cost(MEMORY_REF_COST);
10551 size(4);
10552 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10553
10554 ins_encode %{
10555 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10556 %}
10557 ins_pipe(iload_mem);
10558 %}
10559
10560 // Load short reversed byte order
10561 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10562 match(Set dst (ReverseBytesS (LoadS src)));
10563
10564 ins_cost(MEMORY_REF_COST);
10565 size(4);
10566 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10567
10568 ins_encode %{
10569 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10570 %}
10571 ins_pipe(iload_mem);
10572 %}
10573
10574 // Store Integer reversed byte order
10575 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10576 match(Set dst (StoreI dst (ReverseBytesI src)));
10577
10578 ins_cost(MEMORY_REF_COST);
10579 size(4);
10580 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10581
10582 ins_encode %{
10583 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10584 %}
10585 ins_pipe(istore_mem_reg);
10586 %}
10587
10588 // Store Long reversed byte order
10589 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10590 match(Set dst (StoreL dst (ReverseBytesL src)));
10591
10592 ins_cost(MEMORY_REF_COST);
10593 size(4);
10594 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10595
10596 ins_encode %{
10597 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10598 %}
10599 ins_pipe(istore_mem_reg);
10600 %}
10601
10602 // Store unsighed short/char reversed byte order
10603 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10604 match(Set dst (StoreC dst (ReverseBytesUS src)));
10605
10606 ins_cost(MEMORY_REF_COST);
10607 size(4);
10608 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10609
10610 ins_encode %{
10611 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10612 %}
10613 ins_pipe(istore_mem_reg);
10614 %}
10615
10616 // Store short reversed byte order
10617 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10618 match(Set dst (StoreC dst (ReverseBytesS src)));
10619
10620 ins_cost(MEMORY_REF_COST);
10621 size(4);
10622 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10623
10624 ins_encode %{
10625 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10626 %}
10627 ins_pipe(istore_mem_reg);
10628 %}
10629
10630 // ====================VECTOR INSTRUCTIONS=====================================
10631
10632 // Load Aligned Packed values into a Double Register
10633 instruct loadV8(regD dst, memory mem) %{
10634 predicate(n->as_LoadVector()->memory_size() == 8);
10635 match(Set dst (LoadVector mem));
10636 ins_cost(MEMORY_REF_COST);
10637 size(4);
10638 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10639 ins_encode %{
10640 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10641 %}
10642 ins_pipe(floadD_mem);
10643 %}
10644
10645 // Store Vector in Double register to memory
10646 instruct storeV8(memory mem, regD src) %{
10647 predicate(n->as_StoreVector()->memory_size() == 8);
10648 match(Set mem (StoreVector mem src));
10649 ins_cost(MEMORY_REF_COST);
10650 size(4);
10651 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10652 ins_encode %{
10653 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10654 %}
10655 ins_pipe(fstoreD_mem_reg);
10656 %}
10657
10658 // Store Zero into vector in memory
10659 instruct storeV8B_zero(memory mem, immI0 zero) %{
10660 predicate(n->as_StoreVector()->memory_size() == 8);
10661 match(Set mem (StoreVector mem (ReplicateB zero)));
10662 ins_cost(MEMORY_REF_COST);
10663 size(4);
10664 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10665 ins_encode %{
10666 __ stx(G0, $mem$$Address);
10667 %}
10668 ins_pipe(fstoreD_mem_zero);
10669 %}
10670
10671 instruct storeV4S_zero(memory mem, immI0 zero) %{
10672 predicate(n->as_StoreVector()->memory_size() == 8);
10673 match(Set mem (StoreVector mem (ReplicateS zero)));
10674 ins_cost(MEMORY_REF_COST);
10675 size(4);
10676 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10677 ins_encode %{
10678 __ stx(G0, $mem$$Address);
10679 %}
10680 ins_pipe(fstoreD_mem_zero);
10681 %}
10682
10683 instruct storeV2I_zero(memory mem, immI0 zero) %{
10684 predicate(n->as_StoreVector()->memory_size() == 8);
10685 match(Set mem (StoreVector mem (ReplicateI zero)));
10686 ins_cost(MEMORY_REF_COST);
10687 size(4);
10688 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10689 ins_encode %{
10690 __ stx(G0, $mem$$Address);
10691 %}
10692 ins_pipe(fstoreD_mem_zero);
10693 %}
10694
10695 instruct storeV2F_zero(memory mem, immF0 zero) %{
10696 predicate(n->as_StoreVector()->memory_size() == 8);
10697 match(Set mem (StoreVector mem (ReplicateF zero)));
10698 ins_cost(MEMORY_REF_COST);
10699 size(4);
10700 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10701 ins_encode %{
10702 __ stx(G0, $mem$$Address);
10703 %}
10704 ins_pipe(fstoreD_mem_zero);
10705 %}
10706
10707 // Replicate scalar to packed byte values into Double register
10708 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10709 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10710 match(Set dst (ReplicateB src));
10711 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10712 format %{ "SLLX $src,56,$tmp\n\t"
10713 "SRLX $tmp, 8,$tmp2\n\t"
10714 "OR $tmp,$tmp2,$tmp\n\t"
10715 "SRLX $tmp,16,$tmp2\n\t"
10716 "OR $tmp,$tmp2,$tmp\n\t"
10717 "SRLX $tmp,32,$tmp2\n\t"
10718 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10719 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10720 ins_encode %{
10721 Register Rsrc = $src$$Register;
10722 Register Rtmp = $tmp$$Register;
10723 Register Rtmp2 = $tmp2$$Register;
10724 __ sllx(Rsrc, 56, Rtmp);
10725 __ srlx(Rtmp, 8, Rtmp2);
10726 __ or3 (Rtmp, Rtmp2, Rtmp);
10727 __ srlx(Rtmp, 16, Rtmp2);
10728 __ or3 (Rtmp, Rtmp2, Rtmp);
10729 __ srlx(Rtmp, 32, Rtmp2);
10730 __ or3 (Rtmp, Rtmp2, Rtmp);
10731 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10732 %}
10733 ins_pipe(ialu_reg);
10734 %}
10735
10736 // Replicate scalar to packed byte values into Double stack
10737 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10738 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10739 match(Set dst (ReplicateB src));
10740 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10741 format %{ "SLLX $src,56,$tmp\n\t"
10742 "SRLX $tmp, 8,$tmp2\n\t"
10743 "OR $tmp,$tmp2,$tmp\n\t"
10744 "SRLX $tmp,16,$tmp2\n\t"
10745 "OR $tmp,$tmp2,$tmp\n\t"
10746 "SRLX $tmp,32,$tmp2\n\t"
10747 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10748 "STX $tmp,$dst\t! regL to stkD" %}
10749 ins_encode %{
10750 Register Rsrc = $src$$Register;
10751 Register Rtmp = $tmp$$Register;
10752 Register Rtmp2 = $tmp2$$Register;
10753 __ sllx(Rsrc, 56, Rtmp);
10754 __ srlx(Rtmp, 8, Rtmp2);
10755 __ or3 (Rtmp, Rtmp2, Rtmp);
10756 __ srlx(Rtmp, 16, Rtmp2);
10757 __ or3 (Rtmp, Rtmp2, Rtmp);
10758 __ srlx(Rtmp, 32, Rtmp2);
10759 __ or3 (Rtmp, Rtmp2, Rtmp);
10760 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10761 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10762 %}
10763 ins_pipe(ialu_reg);
10764 %}
10765
10766 // Replicate scalar constant to packed byte values in Double register
10767 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10768 predicate(n->as_Vector()->length() == 8);
10769 match(Set dst (ReplicateB con));
10770 effect(KILL tmp);
10771 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10772 ins_encode %{
10773 // XXX This is a quick fix for 6833573.
10774 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10775 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10776 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10777 %}
10778 ins_pipe(loadConFD);
10779 %}
10780
10781 // Replicate scalar to packed char/short values into Double register
10782 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10783 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10784 match(Set dst (ReplicateS src));
10785 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10786 format %{ "SLLX $src,48,$tmp\n\t"
10787 "SRLX $tmp,16,$tmp2\n\t"
10788 "OR $tmp,$tmp2,$tmp\n\t"
10789 "SRLX $tmp,32,$tmp2\n\t"
10790 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10791 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10792 ins_encode %{
10793 Register Rsrc = $src$$Register;
10794 Register Rtmp = $tmp$$Register;
10795 Register Rtmp2 = $tmp2$$Register;
10796 __ sllx(Rsrc, 48, Rtmp);
10797 __ srlx(Rtmp, 16, Rtmp2);
10798 __ or3 (Rtmp, Rtmp2, Rtmp);
10799 __ srlx(Rtmp, 32, Rtmp2);
10800 __ or3 (Rtmp, Rtmp2, Rtmp);
10801 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10802 %}
10803 ins_pipe(ialu_reg);
10804 %}
10805
10806 // Replicate scalar to packed char/short values into Double stack
10807 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10808 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10809 match(Set dst (ReplicateS src));
10810 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10811 format %{ "SLLX $src,48,$tmp\n\t"
10812 "SRLX $tmp,16,$tmp2\n\t"
10813 "OR $tmp,$tmp2,$tmp\n\t"
10814 "SRLX $tmp,32,$tmp2\n\t"
10815 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10816 "STX $tmp,$dst\t! regL to stkD" %}
10817 ins_encode %{
10818 Register Rsrc = $src$$Register;
10819 Register Rtmp = $tmp$$Register;
10820 Register Rtmp2 = $tmp2$$Register;
10821 __ sllx(Rsrc, 48, Rtmp);
10822 __ srlx(Rtmp, 16, Rtmp2);
10823 __ or3 (Rtmp, Rtmp2, Rtmp);
10824 __ srlx(Rtmp, 32, Rtmp2);
10825 __ or3 (Rtmp, Rtmp2, Rtmp);
10826 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10827 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10828 %}
10829 ins_pipe(ialu_reg);
10830 %}
10831
10832 // Replicate scalar constant to packed char/short values in Double register
10833 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10834 predicate(n->as_Vector()->length() == 4);
10835 match(Set dst (ReplicateS con));
10836 effect(KILL tmp);
10837 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10838 ins_encode %{
10839 // XXX This is a quick fix for 6833573.
10840 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10841 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10842 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10843 %}
10844 ins_pipe(loadConFD);
10845 %}
10846
10847 // Replicate scalar to packed int values into Double register
10848 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10849 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10850 match(Set dst (ReplicateI src));
10851 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10852 format %{ "SLLX $src,32,$tmp\n\t"
10853 "SRLX $tmp,32,$tmp2\n\t"
10854 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10855 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10856 ins_encode %{
10857 Register Rsrc = $src$$Register;
10858 Register Rtmp = $tmp$$Register;
10859 Register Rtmp2 = $tmp2$$Register;
10860 __ sllx(Rsrc, 32, Rtmp);
10861 __ srlx(Rtmp, 32, Rtmp2);
10862 __ or3 (Rtmp, Rtmp2, Rtmp);
10863 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10864 %}
10865 ins_pipe(ialu_reg);
10866 %}
10867
10868 // Replicate scalar to packed int values into Double stack
10869 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10870 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10871 match(Set dst (ReplicateI src));
10872 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10873 format %{ "SLLX $src,32,$tmp\n\t"
10874 "SRLX $tmp,32,$tmp2\n\t"
10875 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10876 "STX $tmp,$dst\t! regL to stkD" %}
10877 ins_encode %{
10878 Register Rsrc = $src$$Register;
10879 Register Rtmp = $tmp$$Register;
10880 Register Rtmp2 = $tmp2$$Register;
10881 __ sllx(Rsrc, 32, Rtmp);
10882 __ srlx(Rtmp, 32, Rtmp2);
10883 __ or3 (Rtmp, Rtmp2, Rtmp);
10884 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10885 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10886 %}
10887 ins_pipe(ialu_reg);
10888 %}
10889
10890 // Replicate scalar zero constant to packed int values in Double register
10891 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10892 predicate(n->as_Vector()->length() == 2);
10893 match(Set dst (ReplicateI con));
10894 effect(KILL tmp);
10895 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10896 ins_encode %{
10897 // XXX This is a quick fix for 6833573.
10898 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10899 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10900 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10901 %}
10902 ins_pipe(loadConFD);
10903 %}
10904
10905 // Replicate scalar to packed float values into Double stack
10906 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10907 predicate(n->as_Vector()->length() == 2);
10908 match(Set dst (ReplicateF src));
10909 ins_cost(MEMORY_REF_COST*2);
10910 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10911 "STF $src,$dst.lo" %}
10912 opcode(Assembler::stf_op3);
10913 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10914 ins_pipe(fstoreF_stk_reg);
10915 %}
10916
10917 // Replicate scalar zero constant to packed float values in Double register
10918 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10919 predicate(n->as_Vector()->length() == 2);
10920 match(Set dst (ReplicateF con));
10921 effect(KILL tmp);
10922 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10923 ins_encode %{
10924 // XXX This is a quick fix for 6833573.
10925 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10926 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10927 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10928 %}
10929 ins_pipe(loadConFD);
10930 %}
10931
10932 //----------PEEPHOLE RULES-----------------------------------------------------
10933 // These must follow all instruction definitions as they use the names
10934 // defined in the instructions definitions.
10935 //
10936 // peepmatch ( root_instr_name [preceding_instruction]* );
10937 //
10938 // peepconstraint %{
10939 // (instruction_number.operand_name relational_op instruction_number.operand_name
10940 // [, ...] );
10941 // // instruction numbers are zero-based using left to right order in peepmatch
10942 //
10943 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10944 // // provide an instruction_number.operand_name for each operand that appears
10945 // // in the replacement instruction's match rule
10946 //
10947 // ---------VM FLAGS---------------------------------------------------------
10948 //
10949 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10950 //
10951 // Each peephole rule is given an identifying number starting with zero and
10952 // increasing by one in the order seen by the parser. An individual peephole
10953 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10954 // on the command-line.
10955 //
10956 // ---------CURRENT LIMITATIONS----------------------------------------------
10957 //
10958 // Only match adjacent instructions in same basic block
10959 // Only equality constraints
10960 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10961 // Only one replacement instruction
10962 //
10963 // ---------EXAMPLE----------------------------------------------------------
10964 //
10965 // // pertinent parts of existing instructions in architecture description
10966 // instruct movI(eRegI dst, eRegI src) %{
10967 // match(Set dst (CopyI src));
10968 // %}
10969 //
10970 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10971 // match(Set dst (AddI dst src));
10972 // effect(KILL cr);
10973 // %}
10974 //
10975 // // Change (inc mov) to lea
10976 // peephole %{
10977 // // increment preceeded by register-register move
10978 // peepmatch ( incI_eReg movI );
10979 // // require that the destination register of the increment
10980 // // match the destination register of the move
10981 // peepconstraint ( 0.dst == 1.dst );
10982 // // construct a replacement instruction that sets
10983 // // the destination to ( move's source register + one )
10984 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10985 // %}
10986 //
10987
10988 // // Change load of spilled value to only a spill
10989 // instruct storeI(memory mem, eRegI src) %{
10990 // match(Set mem (StoreI mem src));
10991 // %}
10992 //
10993 // instruct loadI(eRegI dst, memory mem) %{
10994 // match(Set dst (LoadI mem));
10995 // %}
10996 //
10997 // peephole %{
10998 // peepmatch ( loadI storeI );
10999 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11000 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11001 // %}
11002
11003 //----------SMARTSPILL RULES---------------------------------------------------
11004 // These must follow all instruction definitions as they use the names
11005 // defined in the instructions definitions.
11006 //
11007 // SPARC will probably not have any of these rules due to RISC instruction set.
11008
11009 //----------PIPELINE-----------------------------------------------------------
11010 // Rules which define the behavior of the target architectures pipeline.