1 // 2 // Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 // 5 // This code is free software; you can redistribute it and/or modify it 6 // under the terms of the GNU General Public License version 2 only, as 7 // published by the Free Software Foundation. 8 // 9 // This code is distributed in the hope that it will be useful, but WITHOUT 10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 // version 2 for more details (a copy is included in the LICENSE file that 13 // accompanied this code). 14 // 15 // You should have received a copy of the GNU General Public License version 16 // 2 along with this work; if not, write to the Free Software Foundation, 17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 // 19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 // or visit www.oracle.com if you need additional information or have any 21 // questions. 22 // 23 // 24 25 // X86 Architecture Description File 26 27 //----------REGISTER DEFINITION BLOCK------------------------------------------ 28 // This information is used by the matcher and the register allocator to 29 // describe individual registers and classes of registers within the target 30 // archtecture. 31 32 register %{ 33 //----------Architecture Description Register Definitions---------------------- 34 // General Registers 35 // "reg_def" name ( register save type, C convention save type, 36 // ideal register type, encoding ); 37 // Register Save Types: 38 // 39 // NS = No-Save: The register allocator assumes that these registers 40 // can be used without saving upon entry to the method, & 41 // that they do not need to be saved at call sites. 42 // 43 // SOC = Save-On-Call: The register allocator assumes that these registers 44 // can be used without saving upon entry to the method, 45 // but that they must be saved at call sites. 46 // 47 // SOE = Save-On-Entry: The register allocator assumes that these registers 48 // must be saved before using them upon entry to the 49 // method, but they do not need to be saved at call 50 // sites. 51 // 52 // AS = Always-Save: The register allocator assumes that these registers 53 // must be saved before using them upon entry to the 54 // method, & that they must be saved at call sites. 55 // 56 // Ideal Register Type is used to determine how to save & restore a 57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59 // 60 // The encoding number is the actual bit-pattern placed into the opcodes. 61 62 // General Registers 63 // Previously set EBX, ESI, and EDI as save-on-entry for java code 64 // Turn off SOE in java-code due to frequent use of uncommon-traps. 65 // Now that allocator is better, turn on ESI and EDI as SOE registers. 66 67 reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 68 reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 69 reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 70 reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 71 // now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code 72 reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 73 reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 74 reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 75 reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 76 77 // Float registers. We treat TOS/FPR0 special. It is invisible to the 78 // allocator, and only shows up in the encodings. 79 reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 80 reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 81 // Ok so here's the trick FPR1 is really st(0) except in the midst 82 // of emission of assembly for a machnode. During the emission the fpu stack 83 // is pushed making FPR1 == st(1) temporarily. However at any safepoint 84 // the stack will not have this element so FPR1 == st(0) from the 85 // oopMap viewpoint. This same weirdness with numbering causes 86 // instruction encoding to have to play games with the register 87 // encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation 88 // where it does flt->flt moves to see an example 89 // 90 reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); 91 reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); 92 reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); 93 reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); 94 reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); 95 reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); 96 reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); 97 reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); 98 reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); 99 reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); 100 reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 101 reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 102 reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 103 reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 104 105 // Specify priority of register selection within phases of register 106 // allocation. Highest priority is first. A useful heuristic is to 107 // give registers a low priority when they are required by machine 108 // instructions, like EAX and EDX. Registers which are used as 109 // pairs must fall on an even boundary (witness the FPR#L's in this list). 110 // For the Intel integer registers, the equivalent Long pairs are 111 // EDX:EAX, EBX:ECX, and EDI:EBP. 112 alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 113 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 114 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 115 FPR6L, FPR6H, FPR7L, FPR7H ); 116 117 118 //----------Architecture Description Register Classes-------------------------- 119 // Several register classes are automatically defined based upon information in 120 // this architecture description. 121 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 122 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 123 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 124 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 125 // 126 // Class for all registers 127 reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 128 // Class for general registers 129 reg_class int_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 130 // Class for general registers which may be used for implicit null checks on win95 131 // Also safe for use by tailjump. We don't want to allocate in rbp, 132 reg_class int_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 133 // Class of "X" registers 134 reg_class int_x_reg(EBX, ECX, EDX, EAX); 135 // Class of registers that can appear in an address with no offset. 136 // EBP and ESP require an extra instruction byte for zero offset. 137 // Used in fast-unlock 138 reg_class p_reg(EDX, EDI, ESI, EBX); 139 // Class for general registers not including ECX 140 reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); 141 // Class for general registers not including EAX 142 reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); 143 // Class for general registers not including EAX or EBX. 144 reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); 145 // Class of EAX (for multiply and divide operations) 146 reg_class eax_reg(EAX); 147 // Class of EBX (for atomic add) 148 reg_class ebx_reg(EBX); 149 // Class of ECX (for shift and JCXZ operations and cmpLTMask) 150 reg_class ecx_reg(ECX); 151 // Class of EDX (for multiply and divide operations) 152 reg_class edx_reg(EDX); 153 // Class of EDI (for synchronization) 154 reg_class edi_reg(EDI); 155 // Class of ESI (for synchronization) 156 reg_class esi_reg(ESI); 157 // Singleton class for interpreter's stack pointer 158 reg_class ebp_reg(EBP); 159 // Singleton class for stack pointer 160 reg_class sp_reg(ESP); 161 // Singleton class for instruction pointer 162 // reg_class ip_reg(EIP); 163 // Class of integer register pairs 164 reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 165 // Class of integer register pairs that aligns with calling convention 166 reg_class eadx_reg( EAX,EDX ); 167 reg_class ebcx_reg( ECX,EBX ); 168 // Not AX or DX, used in divides 169 reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 170 171 // Floating point registers. Notice FPR0 is not a choice. 172 // FPR0 is not ever allocated; we use clever encodings to fake 173 // a 2-address instructions out of Intels FP stack. 174 reg_class fp_flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 175 176 reg_class fp_dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 177 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 178 FPR7L,FPR7H ); 179 180 reg_class fp_flt_reg0( FPR1L ); 181 reg_class fp_dbl_reg0( FPR1L,FPR1H ); 182 reg_class fp_dbl_reg1( FPR2L,FPR2H ); 183 reg_class fp_dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, 184 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); 185 186 %} 187 188 189 //----------SOURCE BLOCK------------------------------------------------------- 190 // This is a block of C++ code which provides values, functions, and 191 // definitions necessary in the rest of the architecture description 192 source_hpp %{ 193 // Must be visible to the DFA in dfa_x86_32.cpp 194 extern bool is_operand_hi32_zero(Node* n); 195 %} 196 197 source %{ 198 #define RELOC_IMM32 Assembler::imm_operand 199 #define RELOC_DISP32 Assembler::disp32_operand 200 201 #define __ _masm. 202 203 // How to find the high register of a Long pair, given the low register 204 #define HIGH_FROM_LOW(x) ((x)+2) 205 206 // These masks are used to provide 128-bit aligned bitmasks to the XMM 207 // instructions, to allow sign-masking or sign-bit flipping. They allow 208 // fast versions of NegF/NegD and AbsF/AbsD. 209 210 // Note: 'double' and 'long long' have 32-bits alignment on x86. 211 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 212 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 213 // of 128-bits operands for SSE instructions. 214 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); 215 // Store the value to a 128-bits operand. 216 operand[0] = lo; 217 operand[1] = hi; 218 return operand; 219 } 220 221 // Buffer for 128-bits masks used by SSE instructions. 222 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 223 224 // Static initialization during VM startup. 225 static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 226 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 227 static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 228 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 229 230 // Offset hacking within calls. 231 static int pre_call_FPU_size() { 232 if (Compile::current()->in_24_bit_fp_mode()) 233 return 6; // fldcw 234 return 0; 235 } 236 237 static int preserve_SP_size() { 238 return 2; // op, rm(reg/reg) 239 } 240 241 // !!!!! Special hack to get all type of calls to specify the byte offset 242 // from the start of the call to the point where the return address 243 // will point. 244 int MachCallStaticJavaNode::ret_addr_offset() { 245 int offset = 5 + pre_call_FPU_size(); // 5 bytes from start of call to where return address points 246 if (_method_handle_invoke) 247 offset += preserve_SP_size(); 248 return offset; 249 } 250 251 int MachCallDynamicJavaNode::ret_addr_offset() { 252 return 10 + pre_call_FPU_size(); // 10 bytes from start of call to where return address points 253 } 254 255 static int sizeof_FFree_Float_Stack_All = -1; 256 257 int MachCallRuntimeNode::ret_addr_offset() { 258 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); 259 return sizeof_FFree_Float_Stack_All + 5 + pre_call_FPU_size(); 260 } 261 262 // Indicate if the safepoint node needs the polling page as an input. 263 // Since x86 does have absolute addressing, it doesn't. 264 bool SafePointNode::needs_polling_address_input() { 265 return false; 266 } 267 268 // 269 // Compute padding required for nodes which need alignment 270 // 271 272 // The address of the call instruction needs to be 4-byte aligned to 273 // ensure that it does not span a cache line so that it can be patched. 274 int CallStaticJavaDirectNode::compute_padding(int current_offset) const { 275 current_offset += pre_call_FPU_size(); // skip fldcw, if any 276 current_offset += 1; // skip call opcode byte 277 return round_to(current_offset, alignment_required()) - current_offset; 278 } 279 280 // The address of the call instruction needs to be 4-byte aligned to 281 // ensure that it does not span a cache line so that it can be patched. 282 int CallStaticJavaHandleNode::compute_padding(int current_offset) const { 283 current_offset += pre_call_FPU_size(); // skip fldcw, if any 284 current_offset += preserve_SP_size(); // skip mov rbp, rsp 285 current_offset += 1; // skip call opcode byte 286 return round_to(current_offset, alignment_required()) - current_offset; 287 } 288 289 // The address of the call instruction needs to be 4-byte aligned to 290 // ensure that it does not span a cache line so that it can be patched. 291 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { 292 current_offset += pre_call_FPU_size(); // skip fldcw, if any 293 current_offset += 5; // skip MOV instruction 294 current_offset += 1; // skip call opcode byte 295 return round_to(current_offset, alignment_required()) - current_offset; 296 } 297 298 // EMIT_RM() 299 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 300 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 301 cbuf.insts()->emit_int8(c); 302 } 303 304 // EMIT_CC() 305 void emit_cc(CodeBuffer &cbuf, int f1, int f2) { 306 unsigned char c = (unsigned char)( f1 | f2 ); 307 cbuf.insts()->emit_int8(c); 308 } 309 310 // EMIT_OPCODE() 311 void emit_opcode(CodeBuffer &cbuf, int code) { 312 cbuf.insts()->emit_int8((unsigned char) code); 313 } 314 315 // EMIT_OPCODE() w/ relocation information 316 void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { 317 cbuf.relocate(cbuf.insts_mark() + offset, reloc); 318 emit_opcode(cbuf, code); 319 } 320 321 // EMIT_D8() 322 void emit_d8(CodeBuffer &cbuf, int d8) { 323 cbuf.insts()->emit_int8((unsigned char) d8); 324 } 325 326 // EMIT_D16() 327 void emit_d16(CodeBuffer &cbuf, int d16) { 328 cbuf.insts()->emit_int16(d16); 329 } 330 331 // EMIT_D32() 332 void emit_d32(CodeBuffer &cbuf, int d32) { 333 cbuf.insts()->emit_int32(d32); 334 } 335 336 // emit 32 bit value and construct relocation entry from relocInfo::relocType 337 void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, 338 int format) { 339 cbuf.relocate(cbuf.insts_mark(), reloc, format); 340 cbuf.insts()->emit_int32(d32); 341 } 342 343 // emit 32 bit value and construct relocation entry from RelocationHolder 344 void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, 345 int format) { 346 #ifdef ASSERT 347 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { 348 assert(oop(d32)->is_oop() && (ScavengeRootsInCode || !oop(d32)->is_scavengable()), "cannot embed scavengable oops in code"); 349 } 350 #endif 351 cbuf.relocate(cbuf.insts_mark(), rspec, format); 352 cbuf.insts()->emit_int32(d32); 353 } 354 355 // Access stack slot for load or store 356 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { 357 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) 358 if( -128 <= disp && disp <= 127 ) { 359 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte 360 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 361 emit_d8 (cbuf, disp); // Displacement // R/M byte 362 } else { 363 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte 364 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 365 emit_d32(cbuf, disp); // Displacement // R/M byte 366 } 367 } 368 369 // rRegI ereg, memory mem) %{ // emit_reg_mem 370 void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, relocInfo::relocType disp_reloc ) { 371 // There is no index & no scale, use form without SIB byte 372 if ((index == 0x4) && 373 (scale == 0) && (base != ESP_enc)) { 374 // If no displacement, mode is 0x0; unless base is [EBP] 375 if ( (displace == 0) && (base != EBP_enc) ) { 376 emit_rm(cbuf, 0x0, reg_encoding, base); 377 } 378 else { // If 8-bit displacement, mode 0x1 379 if ((displace >= -128) && (displace <= 127) 380 && (disp_reloc == relocInfo::none) ) { 381 emit_rm(cbuf, 0x1, reg_encoding, base); 382 emit_d8(cbuf, displace); 383 } 384 else { // If 32-bit displacement 385 if (base == -1) { // Special flag for absolute address 386 emit_rm(cbuf, 0x0, reg_encoding, 0x5); 387 // (manual lies; no SIB needed here) 388 if ( disp_reloc != relocInfo::none ) { 389 emit_d32_reloc(cbuf, displace, disp_reloc, 1); 390 } else { 391 emit_d32 (cbuf, displace); 392 } 393 } 394 else { // Normal base + offset 395 emit_rm(cbuf, 0x2, reg_encoding, base); 396 if ( disp_reloc != relocInfo::none ) { 397 emit_d32_reloc(cbuf, displace, disp_reloc, 1); 398 } else { 399 emit_d32 (cbuf, displace); 400 } 401 } 402 } 403 } 404 } 405 else { // Else, encode with the SIB byte 406 // If no displacement, mode is 0x0; unless base is [EBP] 407 if (displace == 0 && (base != EBP_enc)) { // If no displacement 408 emit_rm(cbuf, 0x0, reg_encoding, 0x4); 409 emit_rm(cbuf, scale, index, base); 410 } 411 else { // If 8-bit displacement, mode 0x1 412 if ((displace >= -128) && (displace <= 127) 413 && (disp_reloc == relocInfo::none) ) { 414 emit_rm(cbuf, 0x1, reg_encoding, 0x4); 415 emit_rm(cbuf, scale, index, base); 416 emit_d8(cbuf, displace); 417 } 418 else { // If 32-bit displacement 419 if (base == 0x04 ) { 420 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 421 emit_rm(cbuf, scale, index, 0x04); 422 } else { 423 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 424 emit_rm(cbuf, scale, index, base); 425 } 426 if ( disp_reloc != relocInfo::none ) { 427 emit_d32_reloc(cbuf, displace, disp_reloc, 1); 428 } else { 429 emit_d32 (cbuf, displace); 430 } 431 } 432 } 433 } 434 } 435 436 437 void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 438 if( dst_encoding == src_encoding ) { 439 // reg-reg copy, use an empty encoding 440 } else { 441 emit_opcode( cbuf, 0x8B ); 442 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); 443 } 444 } 445 446 void emit_cmpfp_fixup(MacroAssembler& _masm) { 447 Label exit; 448 __ jccb(Assembler::noParity, exit); 449 __ pushf(); 450 // 451 // comiss/ucomiss instructions set ZF,PF,CF flags and 452 // zero OF,AF,SF for NaN values. 453 // Fixup flags by zeroing ZF,PF so that compare of NaN 454 // values returns 'less than' result (CF is set). 455 // Leave the rest of flags unchanged. 456 // 457 // 7 6 5 4 3 2 1 0 458 // |S|Z|r|A|r|P|r|C| (r - reserved bit) 459 // 0 0 1 0 1 0 1 1 (0x2B) 460 // 461 __ andl(Address(rsp, 0), 0xffffff2b); 462 __ popf(); 463 __ bind(exit); 464 } 465 466 void emit_cmpfp3(MacroAssembler& _masm, Register dst) { 467 Label done; 468 __ movl(dst, -1); 469 __ jcc(Assembler::parity, done); 470 __ jcc(Assembler::below, done); 471 __ setb(Assembler::notEqual, dst); 472 __ movzbl(dst, dst); 473 __ bind(done); 474 } 475 476 477 //============================================================================= 478 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty; 479 480 int Compile::ConstantTable::calculate_table_base_offset() const { 481 return 0; // absolute addressing, no offset 482 } 483 484 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 485 // Empty encoding 486 } 487 488 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 489 return 0; 490 } 491 492 #ifndef PRODUCT 493 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 494 st->print("# MachConstantBaseNode (empty encoding)"); 495 } 496 #endif 497 498 499 //============================================================================= 500 #ifndef PRODUCT 501 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 502 Compile* C = ra_->C; 503 504 int framesize = C->frame_slots() << LogBytesPerInt; 505 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 506 // Remove wordSize for return addr which is already pushed. 507 framesize -= wordSize; 508 509 if (C->need_stack_bang(framesize)) { 510 framesize -= wordSize; 511 st->print("# stack bang"); 512 st->print("\n\t"); 513 st->print("PUSH EBP\t# Save EBP"); 514 if (framesize) { 515 st->print("\n\t"); 516 st->print("SUB ESP, #%d\t# Create frame",framesize); 517 } 518 } else { 519 st->print("SUB ESP, #%d\t# Create frame",framesize); 520 st->print("\n\t"); 521 framesize -= wordSize; 522 st->print("MOV [ESP + #%d], EBP\t# Save EBP",framesize); 523 } 524 525 if (VerifyStackAtCalls) { 526 st->print("\n\t"); 527 framesize -= wordSize; 528 st->print("MOV [ESP + #%d], 0xBADB100D\t# Majik cookie for stack depth check",framesize); 529 } 530 531 if( C->in_24_bit_fp_mode() ) { 532 st->print("\n\t"); 533 st->print("FLDCW \t# load 24 bit fpu control word"); 534 } 535 if (UseSSE >= 2 && VerifyFPU) { 536 st->print("\n\t"); 537 st->print("# verify FPU stack (must be clean on entry)"); 538 } 539 540 #ifdef ASSERT 541 if (VerifyStackAtCalls) { 542 st->print("\n\t"); 543 st->print("# stack alignment check"); 544 } 545 #endif 546 st->cr(); 547 } 548 #endif 549 550 551 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 552 Compile* C = ra_->C; 553 MacroAssembler _masm(&cbuf); 554 555 int framesize = C->frame_slots() << LogBytesPerInt; 556 557 __ verified_entry(framesize, C->need_stack_bang(framesize), C->in_24_bit_fp_mode()); 558 559 C->set_frame_complete(cbuf.insts_size()); 560 561 if (C->has_mach_constant_base_node()) { 562 // NOTE: We set the table base offset here because users might be 563 // emitted before MachConstantBaseNode. 564 Compile::ConstantTable& constant_table = C->constant_table(); 565 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 566 } 567 } 568 569 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 570 return MachNode::size(ra_); // too many variables; just compute it the hard way 571 } 572 573 int MachPrologNode::reloc() const { 574 return 0; // a large enough number 575 } 576 577 //============================================================================= 578 #ifndef PRODUCT 579 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 580 Compile *C = ra_->C; 581 int framesize = C->frame_slots() << LogBytesPerInt; 582 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 583 // Remove two words for return addr and rbp, 584 framesize -= 2*wordSize; 585 586 if( C->in_24_bit_fp_mode() ) { 587 st->print("FLDCW standard control word"); 588 st->cr(); st->print("\t"); 589 } 590 if( framesize ) { 591 st->print("ADD ESP,%d\t# Destroy frame",framesize); 592 st->cr(); st->print("\t"); 593 } 594 st->print_cr("POPL EBP"); st->print("\t"); 595 if( do_polling() && C->is_method_compilation() ) { 596 st->print("TEST PollPage,EAX\t! Poll Safepoint"); 597 st->cr(); st->print("\t"); 598 } 599 } 600 #endif 601 602 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 603 Compile *C = ra_->C; 604 605 // If method set FPU control word, restore to standard control word 606 if( C->in_24_bit_fp_mode() ) { 607 MacroAssembler masm(&cbuf); 608 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 609 } 610 611 int framesize = C->frame_slots() << LogBytesPerInt; 612 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 613 // Remove two words for return addr and rbp, 614 framesize -= 2*wordSize; 615 616 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 617 618 if( framesize >= 128 ) { 619 emit_opcode(cbuf, 0x81); // add SP, #framesize 620 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 621 emit_d32(cbuf, framesize); 622 } 623 else if( framesize ) { 624 emit_opcode(cbuf, 0x83); // add SP, #framesize 625 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 626 emit_d8(cbuf, framesize); 627 } 628 629 emit_opcode(cbuf, 0x58 | EBP_enc); 630 631 if( do_polling() && C->is_method_compilation() ) { 632 cbuf.relocate(cbuf.insts_end(), relocInfo::poll_return_type, 0); 633 emit_opcode(cbuf,0x85); 634 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX 635 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 636 } 637 } 638 639 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 640 Compile *C = ra_->C; 641 // If method set FPU control word, restore to standard control word 642 int size = C->in_24_bit_fp_mode() ? 6 : 0; 643 if( do_polling() && C->is_method_compilation() ) size += 6; 644 645 int framesize = C->frame_slots() << LogBytesPerInt; 646 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 647 // Remove two words for return addr and rbp, 648 framesize -= 2*wordSize; 649 650 size++; // popl rbp, 651 652 if( framesize >= 128 ) { 653 size += 6; 654 } else { 655 size += framesize ? 3 : 0; 656 } 657 return size; 658 } 659 660 int MachEpilogNode::reloc() const { 661 return 0; // a large enough number 662 } 663 664 const Pipeline * MachEpilogNode::pipeline() const { 665 return MachNode::pipeline_class(); 666 } 667 668 int MachEpilogNode::safepoint_offset() const { return 0; } 669 670 //============================================================================= 671 672 enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; 673 static enum RC rc_class( OptoReg::Name reg ) { 674 675 if( !OptoReg::is_valid(reg) ) return rc_bad; 676 if (OptoReg::is_stack(reg)) return rc_stack; 677 678 VMReg r = OptoReg::as_VMReg(reg); 679 if (r->is_Register()) return rc_int; 680 if (r->is_FloatRegister()) { 681 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); 682 return rc_float; 683 } 684 assert(r->is_XMMRegister(), "must be"); 685 return rc_xmm; 686 } 687 688 static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, 689 int opcode, const char *op_str, int size, outputStream* st ) { 690 if( cbuf ) { 691 emit_opcode (*cbuf, opcode ); 692 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, relocInfo::none); 693 #ifndef PRODUCT 694 } else if( !do_size ) { 695 if( size != 0 ) st->print("\n\t"); 696 if( opcode == 0x8B || opcode == 0x89 ) { // MOV 697 if( is_load ) st->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 698 else st->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); 699 } else { // FLD, FST, PUSH, POP 700 st->print("%s [ESP + #%d]",op_str,offset); 701 } 702 #endif 703 } 704 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 705 return size+3+offset_size; 706 } 707 708 // Helper for XMM registers. Extra opcode bits, limited syntax. 709 static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, 710 int offset, int reg_lo, int reg_hi, int size, outputStream* st ) { 711 if (cbuf) { 712 MacroAssembler _masm(cbuf); 713 if (reg_lo+1 == reg_hi) { // double move? 714 if (is_load) { 715 __ movdbl(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); 716 } else { 717 __ movdbl(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); 718 } 719 } else { 720 if (is_load) { 721 __ movflt(as_XMMRegister(Matcher::_regEncode[reg_lo]), Address(rsp, offset)); 722 } else { 723 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[reg_lo])); 724 } 725 } 726 #ifndef PRODUCT 727 } else if (!do_size) { 728 if (size != 0) st->print("\n\t"); 729 if (reg_lo+1 == reg_hi) { // double move? 730 if (is_load) st->print("%s %s,[ESP + #%d]", 731 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", 732 Matcher::regName[reg_lo], offset); 733 else st->print("MOVSD [ESP + #%d],%s", 734 offset, Matcher::regName[reg_lo]); 735 } else { 736 if (is_load) st->print("MOVSS %s,[ESP + #%d]", 737 Matcher::regName[reg_lo], offset); 738 else st->print("MOVSS [ESP + #%d],%s", 739 offset, Matcher::regName[reg_lo]); 740 } 741 #endif 742 } 743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 744 // VEX_2bytes prefix is used if UseAVX > 0, so it takes the same 2 bytes as SIMD prefix. 745 return size+5+offset_size; 746 } 747 748 749 static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 750 int src_hi, int dst_hi, int size, outputStream* st ) { 751 if (cbuf) { 752 MacroAssembler _masm(cbuf); 753 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? 754 __ movdbl(as_XMMRegister(Matcher::_regEncode[dst_lo]), 755 as_XMMRegister(Matcher::_regEncode[src_lo])); 756 } else { 757 __ movflt(as_XMMRegister(Matcher::_regEncode[dst_lo]), 758 as_XMMRegister(Matcher::_regEncode[src_lo])); 759 } 760 #ifndef PRODUCT 761 } else if (!do_size) { 762 if (size != 0) st->print("\n\t"); 763 if (UseXmmRegToRegMoveAll) {//Use movaps,movapd to move between xmm registers 764 if (src_lo+1 == src_hi && dst_lo+1 == dst_hi) { // double move? 765 st->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 766 } else { 767 st->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 768 } 769 } else { 770 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 771 st->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 772 } else { 773 st->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 774 } 775 } 776 #endif 777 } 778 // VEX_2bytes prefix is used if UseAVX > 0, and it takes the same 2 bytes as SIMD prefix. 779 // Only MOVAPS SSE prefix uses 1 byte. 780 int sz = 4; 781 if (!(src_lo+1 == src_hi && dst_lo+1 == dst_hi) && 782 UseXmmRegToRegMoveAll && (UseAVX == 0)) sz = 3; 783 return size + sz; 784 } 785 786 static int impl_movgpr2x_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 787 int src_hi, int dst_hi, int size, outputStream* st ) { 788 // 32-bit 789 if (cbuf) { 790 MacroAssembler _masm(cbuf); 791 __ movdl(as_XMMRegister(Matcher::_regEncode[dst_lo]), 792 as_Register(Matcher::_regEncode[src_lo])); 793 #ifndef PRODUCT 794 } else if (!do_size) { 795 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 796 #endif 797 } 798 return 4; 799 } 800 801 802 static int impl_movx2gpr_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 803 int src_hi, int dst_hi, int size, outputStream* st ) { 804 // 32-bit 805 if (cbuf) { 806 MacroAssembler _masm(cbuf); 807 __ movdl(as_Register(Matcher::_regEncode[dst_lo]), 808 as_XMMRegister(Matcher::_regEncode[src_lo])); 809 #ifndef PRODUCT 810 } else if (!do_size) { 811 st->print("movdl %s, %s\t# spill", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 812 #endif 813 } 814 return 4; 815 } 816 817 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size, outputStream* st ) { 818 if( cbuf ) { 819 emit_opcode(*cbuf, 0x8B ); 820 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); 821 #ifndef PRODUCT 822 } else if( !do_size ) { 823 if( size != 0 ) st->print("\n\t"); 824 st->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); 825 #endif 826 } 827 return size+2; 828 } 829 830 static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, 831 int offset, int size, outputStream* st ) { 832 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there 833 if( cbuf ) { 834 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) 835 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); 836 #ifndef PRODUCT 837 } else if( !do_size ) { 838 if( size != 0 ) st->print("\n\t"); 839 st->print("FLD %s",Matcher::regName[src_lo]); 840 #endif 841 } 842 size += 2; 843 } 844 845 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; 846 const char *op_str; 847 int op; 848 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? 849 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; 850 op = 0xDD; 851 } else { // 32-bit store 852 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; 853 op = 0xD9; 854 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); 855 } 856 857 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size, st); 858 } 859 860 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad. 861 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 862 int src_hi, int dst_hi, uint ireg, outputStream* st); 863 864 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load, 865 int stack_offset, int reg, uint ireg, outputStream* st); 866 867 static int vec_stack_to_stack_helper(CodeBuffer *cbuf, bool do_size, int src_offset, 868 int dst_offset, uint ireg, outputStream* st) { 869 int calc_size = 0; 870 int src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); 871 int dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); 872 switch (ireg) { 873 case Op_VecS: 874 calc_size = 3+src_offset_size + 3+dst_offset_size; 875 break; 876 case Op_VecD: 877 calc_size = 3+src_offset_size + 3+dst_offset_size; 878 src_offset += 4; 879 dst_offset += 4; 880 src_offset_size = (src_offset == 0) ? 0 : ((src_offset < 0x80) ? 1 : 4); 881 dst_offset_size = (dst_offset == 0) ? 0 : ((dst_offset < 0x80) ? 1 : 4); 882 calc_size += 3+src_offset_size + 3+dst_offset_size; 883 break; 884 case Op_VecX: 885 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; 886 break; 887 case Op_VecY: 888 calc_size = 6 + 6 + 5+src_offset_size + 5+dst_offset_size; 889 break; 890 default: 891 ShouldNotReachHere(); 892 } 893 if (cbuf) { 894 MacroAssembler _masm(cbuf); 895 int offset = __ offset(); 896 switch (ireg) { 897 case Op_VecS: 898 __ pushl(Address(rsp, src_offset)); 899 __ popl (Address(rsp, dst_offset)); 900 break; 901 case Op_VecD: 902 __ pushl(Address(rsp, src_offset)); 903 __ popl (Address(rsp, dst_offset)); 904 __ pushl(Address(rsp, src_offset+4)); 905 __ popl (Address(rsp, dst_offset+4)); 906 break; 907 case Op_VecX: 908 __ movdqu(Address(rsp, -16), xmm0); 909 __ movdqu(xmm0, Address(rsp, src_offset)); 910 __ movdqu(Address(rsp, dst_offset), xmm0); 911 __ movdqu(xmm0, Address(rsp, -16)); 912 break; 913 case Op_VecY: 914 __ vmovdqu(Address(rsp, -32), xmm0); 915 __ vmovdqu(xmm0, Address(rsp, src_offset)); 916 __ vmovdqu(Address(rsp, dst_offset), xmm0); 917 __ vmovdqu(xmm0, Address(rsp, -32)); 918 break; 919 default: 920 ShouldNotReachHere(); 921 } 922 int size = __ offset() - offset; 923 assert(size == calc_size, "incorrect size calculattion"); 924 return size; 925 #ifndef PRODUCT 926 } else if (!do_size) { 927 switch (ireg) { 928 case Op_VecS: 929 st->print("pushl [rsp + #%d]\t# 32-bit mem-mem spill\n\t" 930 "popl [rsp + #%d]", 931 src_offset, dst_offset); 932 break; 933 case Op_VecD: 934 st->print("pushl [rsp + #%d]\t# 64-bit mem-mem spill\n\t" 935 "popq [rsp + #%d]\n\t" 936 "pushl [rsp + #%d]\n\t" 937 "popq [rsp + #%d]", 938 src_offset, dst_offset, src_offset+4, dst_offset+4); 939 break; 940 case Op_VecX: 941 st->print("movdqu [rsp - #16], xmm0\t# 128-bit mem-mem spill\n\t" 942 "movdqu xmm0, [rsp + #%d]\n\t" 943 "movdqu [rsp + #%d], xmm0\n\t" 944 "movdqu xmm0, [rsp - #16]", 945 src_offset, dst_offset); 946 break; 947 case Op_VecY: 948 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t" 949 "vmovdqu xmm0, [rsp + #%d]\n\t" 950 "vmovdqu [rsp + #%d], xmm0\n\t" 951 "vmovdqu xmm0, [rsp - #32]", 952 src_offset, dst_offset); 953 break; 954 default: 955 ShouldNotReachHere(); 956 } 957 #endif 958 } 959 return calc_size; 960 } 961 962 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 963 // Get registers to move 964 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 965 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 966 OptoReg::Name dst_second = ra_->get_reg_second(this ); 967 OptoReg::Name dst_first = ra_->get_reg_first(this ); 968 969 enum RC src_second_rc = rc_class(src_second); 970 enum RC src_first_rc = rc_class(src_first); 971 enum RC dst_second_rc = rc_class(dst_second); 972 enum RC dst_first_rc = rc_class(dst_first); 973 974 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 975 976 // Generate spill code! 977 int size = 0; 978 979 if( src_first == dst_first && src_second == dst_second ) 980 return size; // Self copy, no move 981 982 if (bottom_type()->isa_vect() != NULL) { 983 uint ireg = ideal_reg(); 984 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity"); 985 assert((src_first_rc != rc_float && dst_first_rc != rc_float), "sanity"); 986 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity"); 987 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 988 // mem -> mem 989 int src_offset = ra_->reg2offset(src_first); 990 int dst_offset = ra_->reg2offset(dst_first); 991 return vec_stack_to_stack_helper(cbuf, do_size, src_offset, dst_offset, ireg, st); 992 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 993 return vec_mov_helper(cbuf, do_size, src_first, dst_first, src_second, dst_second, ireg, st); 994 } else if (src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 995 int stack_offset = ra_->reg2offset(dst_first); 996 return vec_spill_helper(cbuf, do_size, false, stack_offset, src_first, ireg, st); 997 } else if (src_first_rc == rc_stack && dst_first_rc == rc_xmm ) { 998 int stack_offset = ra_->reg2offset(src_first); 999 return vec_spill_helper(cbuf, do_size, true, stack_offset, dst_first, ireg, st); 1000 } else { 1001 ShouldNotReachHere(); 1002 } 1003 } 1004 1005 // -------------------------------------- 1006 // Check for mem-mem move. push/pop to move. 1007 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1008 if( src_second == dst_first ) { // overlapping stack copy ranges 1009 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); 1010 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 1011 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 1012 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits 1013 } 1014 // move low bits 1015 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size, st); 1016 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size, st); 1017 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits 1018 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size, st); 1019 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size, st); 1020 } 1021 return size; 1022 } 1023 1024 // -------------------------------------- 1025 // Check for integer reg-reg copy 1026 if( src_first_rc == rc_int && dst_first_rc == rc_int ) 1027 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size, st); 1028 1029 // Check for integer store 1030 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) 1031 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size, st); 1032 1033 // Check for integer load 1034 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) 1035 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size, st); 1036 1037 // Check for integer reg-xmm reg copy 1038 if( src_first_rc == rc_int && dst_first_rc == rc_xmm ) { 1039 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), 1040 "no 64 bit integer-float reg moves" ); 1041 return impl_movgpr2x_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1042 } 1043 // -------------------------------------- 1044 // Check for float reg-reg copy 1045 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1046 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 1047 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); 1048 if( cbuf ) { 1049 1050 // Note the mucking with the register encode to compensate for the 0/1 1051 // indexing issue mentioned in a comment in the reg_def sections 1052 // for FPR registers many lines above here. 1053 1054 if( src_first != FPR1L_num ) { 1055 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) 1056 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); 1057 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 1058 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 1059 } else { 1060 emit_opcode (*cbuf, 0xDD ); // FST ST(i) 1061 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); 1062 } 1063 #ifndef PRODUCT 1064 } else if( !do_size ) { 1065 if( size != 0 ) st->print("\n\t"); 1066 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); 1067 else st->print( "FST %s", Matcher::regName[dst_first]); 1068 #endif 1069 } 1070 return size + ((src_first != FPR1L_num) ? 2+2 : 2); 1071 } 1072 1073 // Check for float store 1074 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1075 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size, st); 1076 } 1077 1078 // Check for float load 1079 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1080 int offset = ra_->reg2offset(src_first); 1081 const char *op_str; 1082 int op; 1083 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? 1084 op_str = "FLD_D"; 1085 op = 0xDD; 1086 } else { // 32-bit load 1087 op_str = "FLD_S"; 1088 op = 0xD9; 1089 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 1090 } 1091 if( cbuf ) { 1092 emit_opcode (*cbuf, op ); 1093 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, relocInfo::none); 1094 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 1095 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 1096 #ifndef PRODUCT 1097 } else if( !do_size ) { 1098 if( size != 0 ) st->print("\n\t"); 1099 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); 1100 #endif 1101 } 1102 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 1103 return size + 3+offset_size+2; 1104 } 1105 1106 // Check for xmm reg-reg copy 1107 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 1108 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 1109 (src_first+1 == src_second && dst_first+1 == dst_second), 1110 "no non-adjacent float-moves" ); 1111 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1112 } 1113 1114 // Check for xmm reg-integer reg copy 1115 if( src_first_rc == rc_xmm && dst_first_rc == rc_int ) { 1116 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad), 1117 "no 64 bit float-integer reg moves" ); 1118 return impl_movx2gpr_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size, st); 1119 } 1120 1121 // Check for xmm store 1122 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 1123 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size, st); 1124 } 1125 1126 // Check for float xmm load 1127 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { 1128 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size, st); 1129 } 1130 1131 // Copy from float reg to xmm reg 1132 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { 1133 // copy to the top of stack from floating point reg 1134 // and use LEA to preserve flags 1135 if( cbuf ) { 1136 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] 1137 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1138 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1139 emit_d8(*cbuf,0xF8); 1140 #ifndef PRODUCT 1141 } else if( !do_size ) { 1142 if( size != 0 ) st->print("\n\t"); 1143 st->print("LEA ESP,[ESP-8]"); 1144 #endif 1145 } 1146 size += 4; 1147 1148 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size, st); 1149 1150 // Copy from the temp memory to the xmm reg. 1151 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size, st); 1152 1153 if( cbuf ) { 1154 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] 1155 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1156 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1157 emit_d8(*cbuf,0x08); 1158 #ifndef PRODUCT 1159 } else if( !do_size ) { 1160 if( size != 0 ) st->print("\n\t"); 1161 st->print("LEA ESP,[ESP+8]"); 1162 #endif 1163 } 1164 size += 4; 1165 return size; 1166 } 1167 1168 assert( size > 0, "missed a case" ); 1169 1170 // -------------------------------------------------------------------- 1171 // Check for second bits still needing moving. 1172 if( src_second == dst_second ) 1173 return size; // Self copy; no move 1174 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1175 1176 // Check for second word int-int move 1177 if( src_second_rc == rc_int && dst_second_rc == rc_int ) 1178 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size, st); 1179 1180 // Check for second word integer store 1181 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1182 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size, st); 1183 1184 // Check for second word integer load 1185 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1186 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size, st); 1187 1188 1189 Unimplemented(); 1190 } 1191 1192 #ifndef PRODUCT 1193 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const { 1194 implementation( NULL, ra_, false, st ); 1195 } 1196 #endif 1197 1198 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1199 implementation( &cbuf, ra_, false, NULL ); 1200 } 1201 1202 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1203 return implementation( NULL, ra_, true, NULL ); 1204 } 1205 1206 1207 //============================================================================= 1208 #ifndef PRODUCT 1209 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1210 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1211 int reg = ra_->get_reg_first(this); 1212 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); 1213 } 1214 #endif 1215 1216 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1217 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1218 int reg = ra_->get_encode(this); 1219 if( offset >= 128 ) { 1220 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1221 emit_rm(cbuf, 0x2, reg, 0x04); 1222 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1223 emit_d32(cbuf, offset); 1224 } 1225 else { 1226 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1227 emit_rm(cbuf, 0x1, reg, 0x04); 1228 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1229 emit_d8(cbuf, offset); 1230 } 1231 } 1232 1233 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1234 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1235 if( offset >= 128 ) { 1236 return 7; 1237 } 1238 else { 1239 return 4; 1240 } 1241 } 1242 1243 //============================================================================= 1244 1245 // emit call stub, compiled java to interpreter 1246 void emit_java_to_interp(CodeBuffer &cbuf ) { 1247 // Stub is fixed up when the corresponding call is converted from calling 1248 // compiled code to calling interpreted code. 1249 // mov rbx,0 1250 // jmp -1 1251 1252 address mark = cbuf.insts_mark(); // get mark within main instrs section 1253 1254 // Note that the code buffer's insts_mark is always relative to insts. 1255 // That's why we must use the macroassembler to generate a stub. 1256 MacroAssembler _masm(&cbuf); 1257 1258 address base = 1259 __ start_a_stub(Compile::MAX_stubs_size); 1260 if (base == NULL) return; // CodeBuffer::expand failed 1261 // static stub relocation stores the instruction address of the call 1262 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1263 // static stub relocation also tags the Method* in the code-stream. 1264 __ mov_metadata(rbx, (Metadata*)NULL); // method is zapped till fixup time 1265 // This is recognized as unresolved by relocs/nativeInst/ic code 1266 __ jump(RuntimeAddress(__ pc())); 1267 1268 __ end_a_stub(); 1269 // Update current stubs pointer and restore insts_end. 1270 } 1271 // size of call stub, compiled java to interpretor 1272 uint size_java_to_interp() { 1273 return 10; // movl; jmp 1274 } 1275 // relocation entries for call stub, compiled java to interpretor 1276 uint reloc_java_to_interp() { 1277 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call 1278 } 1279 1280 //============================================================================= 1281 #ifndef PRODUCT 1282 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1283 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); 1284 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); 1285 st->print_cr("\tNOP"); 1286 st->print_cr("\tNOP"); 1287 if( !OptoBreakpoint ) 1288 st->print_cr("\tNOP"); 1289 } 1290 #endif 1291 1292 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1293 MacroAssembler masm(&cbuf); 1294 #ifdef ASSERT 1295 uint insts_size = cbuf.insts_size(); 1296 #endif 1297 masm.cmpptr(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); 1298 masm.jump_cc(Assembler::notEqual, 1299 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1300 /* WARNING these NOPs are critical so that verified entry point is properly 1301 aligned for patching by NativeJump::patch_verified_entry() */ 1302 int nops_cnt = 2; 1303 if( !OptoBreakpoint ) // Leave space for int3 1304 nops_cnt += 1; 1305 masm.nop(nops_cnt); 1306 1307 assert(cbuf.insts_size() - insts_size == size(ra_), "checking code size of inline cache node"); 1308 } 1309 1310 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1311 return OptoBreakpoint ? 11 : 12; 1312 } 1313 1314 1315 //============================================================================= 1316 uint size_exception_handler() { 1317 // NativeCall instruction size is the same as NativeJump. 1318 // exception handler starts out as jump and can be patched to 1319 // a call be deoptimization. (4932387) 1320 // Note that this value is also credited (in output.cpp) to 1321 // the size of the code section. 1322 return NativeJump::instruction_size; 1323 } 1324 1325 // Emit exception handler code. Stuff framesize into a register 1326 // and call a VM stub routine. 1327 int emit_exception_handler(CodeBuffer& cbuf) { 1328 1329 // Note that the code buffer's insts_mark is always relative to insts. 1330 // That's why we must use the macroassembler to generate a handler. 1331 MacroAssembler _masm(&cbuf); 1332 address base = 1333 __ start_a_stub(size_exception_handler()); 1334 if (base == NULL) return 0; // CodeBuffer::expand failed 1335 int offset = __ offset(); 1336 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->entry_point())); 1337 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1338 __ end_a_stub(); 1339 return offset; 1340 } 1341 1342 uint size_deopt_handler() { 1343 // NativeCall instruction size is the same as NativeJump. 1344 // exception handler starts out as jump and can be patched to 1345 // a call be deoptimization. (4932387) 1346 // Note that this value is also credited (in output.cpp) to 1347 // the size of the code section. 1348 return 5 + NativeJump::instruction_size; // pushl(); jmp; 1349 } 1350 1351 // Emit deopt handler code. 1352 int emit_deopt_handler(CodeBuffer& cbuf) { 1353 1354 // Note that the code buffer's insts_mark is always relative to insts. 1355 // That's why we must use the macroassembler to generate a handler. 1356 MacroAssembler _masm(&cbuf); 1357 address base = 1358 __ start_a_stub(size_exception_handler()); 1359 if (base == NULL) return 0; // CodeBuffer::expand failed 1360 int offset = __ offset(); 1361 InternalAddress here(__ pc()); 1362 __ pushptr(here.addr()); 1363 1364 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 1365 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1366 __ end_a_stub(); 1367 return offset; 1368 } 1369 1370 int Matcher::regnum_to_fpu_offset(int regnum) { 1371 return regnum - 32; // The FP registers are in the second chunk 1372 } 1373 1374 // This is UltraSparc specific, true just means we have fast l2f conversion 1375 const bool Matcher::convL2FSupported(void) { 1376 return true; 1377 } 1378 1379 // Is this branch offset short enough that a short branch can be used? 1380 // 1381 // NOTE: If the platform does not provide any short branch variants, then 1382 // this method should return false for offset 0. 1383 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1384 // The passed offset is relative to address of the branch. 1385 // On 86 a branch displacement is calculated relative to address 1386 // of a next instruction. 1387 offset -= br_size; 1388 1389 // the short version of jmpConUCF2 contains multiple branches, 1390 // making the reach slightly less 1391 if (rule == jmpConUCF2_rule) 1392 return (-126 <= offset && offset <= 125); 1393 return (-128 <= offset && offset <= 127); 1394 } 1395 1396 const bool Matcher::isSimpleConstant64(jlong value) { 1397 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1398 return false; 1399 } 1400 1401 // The ecx parameter to rep stos for the ClearArray node is in dwords. 1402 const bool Matcher::init_array_count_is_in_bytes = false; 1403 1404 // Threshold size for cleararray. 1405 const int Matcher::init_array_short_size = 8 * BytesPerLong; 1406 1407 // Needs 2 CMOV's for longs. 1408 const int Matcher::long_cmove_cost() { return 1; } 1409 1410 // No CMOVF/CMOVD with SSE/SSE2 1411 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; } 1412 1413 // Should the Matcher clone shifts on addressing modes, expecting them to 1414 // be subsumed into complex addressing expressions or compute them into 1415 // registers? True for Intel but false for most RISCs 1416 const bool Matcher::clone_shift_expressions = true; 1417 1418 // Do we need to mask the count passed to shift instructions or does 1419 // the cpu only look at the lower 5/6 bits anyway? 1420 const bool Matcher::need_masked_shift_count = false; 1421 1422 bool Matcher::narrow_oop_use_complex_address() { 1423 ShouldNotCallThis(); 1424 return true; 1425 } 1426 1427 bool Matcher::narrow_klass_use_complex_address() { 1428 ShouldNotCallThis(); 1429 return true; 1430 } 1431 1432 1433 // Is it better to copy float constants, or load them directly from memory? 1434 // Intel can load a float constant from a direct address, requiring no 1435 // extra registers. Most RISCs will have to materialize an address into a 1436 // register first, so they would do better to copy the constant from stack. 1437 const bool Matcher::rematerialize_float_constants = true; 1438 1439 // If CPU can load and store mis-aligned doubles directly then no fixup is 1440 // needed. Else we split the double into 2 integer pieces and move it 1441 // piece-by-piece. Only happens when passing doubles into C code as the 1442 // Java calling convention forces doubles to be aligned. 1443 const bool Matcher::misaligned_doubles_ok = true; 1444 1445 1446 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1447 // Get the memory operand from the node 1448 uint numopnds = node->num_opnds(); // Virtual call for number of operands 1449 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far 1450 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); 1451 uint opcnt = 1; // First operand 1452 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand 1453 while( idx >= skipped+num_edges ) { 1454 skipped += num_edges; 1455 opcnt++; // Bump operand count 1456 assert( opcnt < numopnds, "Accessing non-existent operand" ); 1457 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand 1458 } 1459 1460 MachOper *memory = node->_opnds[opcnt]; 1461 MachOper *new_memory = NULL; 1462 switch (memory->opcode()) { 1463 case DIRECT: 1464 case INDOFFSET32X: 1465 // No transformation necessary. 1466 return; 1467 case INDIRECT: 1468 new_memory = new (C) indirect_win95_safeOper( ); 1469 break; 1470 case INDOFFSET8: 1471 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); 1472 break; 1473 case INDOFFSET32: 1474 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); 1475 break; 1476 case INDINDEXOFFSET: 1477 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); 1478 break; 1479 case INDINDEXSCALE: 1480 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); 1481 break; 1482 case INDINDEXSCALEOFFSET: 1483 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); 1484 break; 1485 case LOAD_LONG_INDIRECT: 1486 case LOAD_LONG_INDOFFSET32: 1487 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} 1488 return; 1489 default: 1490 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); 1491 return; 1492 } 1493 node->_opnds[opcnt] = new_memory; 1494 } 1495 1496 // Advertise here if the CPU requires explicit rounding operations 1497 // to implement the UseStrictFP mode. 1498 const bool Matcher::strict_fp_requires_explicit_rounding = true; 1499 1500 // Are floats conerted to double when stored to stack during deoptimization? 1501 // On x32 it is stored with convertion only when FPU is used for floats. 1502 bool Matcher::float_in_double() { return (UseSSE == 0); } 1503 1504 // Do ints take an entire long register or just half? 1505 const bool Matcher::int_in_long = false; 1506 1507 // Return whether or not this register is ever used as an argument. This 1508 // function is used on startup to build the trampoline stubs in generateOptoStub. 1509 // Registers not mentioned will be killed by the VM call in the trampoline, and 1510 // arguments in those registers not be available to the callee. 1511 bool Matcher::can_be_java_arg( int reg ) { 1512 if( reg == ECX_num || reg == EDX_num ) return true; 1513 if( (reg == XMM0_num || reg == XMM1_num ) && UseSSE>=1 ) return true; 1514 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1515 return false; 1516 } 1517 1518 bool Matcher::is_spillable_arg( int reg ) { 1519 return can_be_java_arg(reg); 1520 } 1521 1522 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1523 // Use hardware integer DIV instruction when 1524 // it is faster than a code which use multiply. 1525 // Only when constant divisor fits into 32 bit 1526 // (min_jint is excluded to get only correct 1527 // positive 32 bit values from negative). 1528 return VM_Version::has_fast_idiv() && 1529 (divisor == (int)divisor && divisor != min_jint); 1530 } 1531 1532 // Register for DIVI projection of divmodI 1533 RegMask Matcher::divI_proj_mask() { 1534 return EAX_REG_mask(); 1535 } 1536 1537 // Register for MODI projection of divmodI 1538 RegMask Matcher::modI_proj_mask() { 1539 return EDX_REG_mask(); 1540 } 1541 1542 // Register for DIVL projection of divmodL 1543 RegMask Matcher::divL_proj_mask() { 1544 ShouldNotReachHere(); 1545 return RegMask(); 1546 } 1547 1548 // Register for MODL projection of divmodL 1549 RegMask Matcher::modL_proj_mask() { 1550 ShouldNotReachHere(); 1551 return RegMask(); 1552 } 1553 1554 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1555 return EBP_REG_mask(); 1556 } 1557 1558 // Returns true if the high 32 bits of the value is known to be zero. 1559 bool is_operand_hi32_zero(Node* n) { 1560 int opc = n->Opcode(); 1561 if (opc == Op_AndL) { 1562 Node* o2 = n->in(2); 1563 if (o2->is_Con() && (o2->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { 1564 return true; 1565 } 1566 } 1567 if (opc == Op_ConL && (n->get_long() & 0xFFFFFFFF00000000LL) == 0LL) { 1568 return true; 1569 } 1570 return false; 1571 } 1572 1573 %} 1574 1575 //----------ENCODING BLOCK----------------------------------------------------- 1576 // This block specifies the encoding classes used by the compiler to output 1577 // byte streams. Encoding classes generate functions which are called by 1578 // Machine Instruction Nodes in order to generate the bit encoding of the 1579 // instruction. Operands specify their base encoding interface with the 1580 // interface keyword. There are currently supported four interfaces, 1581 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1582 // operand to generate a function which returns its register number when 1583 // queried. CONST_INTER causes an operand to generate a function which 1584 // returns the value of the constant when queried. MEMORY_INTER causes an 1585 // operand to generate four functions which return the Base Register, the 1586 // Index Register, the Scale Value, and the Offset Value of the operand when 1587 // queried. COND_INTER causes an operand to generate six functions which 1588 // return the encoding code (ie - encoding bits for the instruction) 1589 // associated with each basic boolean condition for a conditional instruction. 1590 // Instructions specify two basic values for encoding. They use the 1591 // ins_encode keyword to specify their encoding class (which must be one of 1592 // the class names specified in the encoding block), and they use the 1593 // opcode keyword to specify, in order, their primary, secondary, and 1594 // tertiary opcode. Only the opcode sections which a particular instruction 1595 // needs for encoding need to be specified. 1596 encode %{ 1597 // Build emit functions for each basic byte or larger field in the intel 1598 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ 1599 // code in the enc_class source block. Emit functions will live in the 1600 // main source block for now. In future, we can generalize this by 1601 // adding a syntax that specifies the sizes of fields in an order, 1602 // so that the adlc can build the emit functions automagically 1603 1604 // Emit primary opcode 1605 enc_class OpcP %{ 1606 emit_opcode(cbuf, $primary); 1607 %} 1608 1609 // Emit secondary opcode 1610 enc_class OpcS %{ 1611 emit_opcode(cbuf, $secondary); 1612 %} 1613 1614 // Emit opcode directly 1615 enc_class Opcode(immI d8) %{ 1616 emit_opcode(cbuf, $d8$$constant); 1617 %} 1618 1619 enc_class SizePrefix %{ 1620 emit_opcode(cbuf,0x66); 1621 %} 1622 1623 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) 1624 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1625 %} 1626 1627 enc_class OpcRegReg (immI opcode, rRegI dst, rRegI src) %{ // OpcRegReg(Many) 1628 emit_opcode(cbuf,$opcode$$constant); 1629 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1630 %} 1631 1632 enc_class mov_r32_imm0( rRegI dst ) %{ 1633 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1634 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1635 %} 1636 1637 enc_class cdq_enc %{ 1638 // Full implementation of Java idiv and irem; checks for 1639 // special case as described in JVM spec., p.243 & p.271. 1640 // 1641 // normal case special case 1642 // 1643 // input : rax,: dividend min_int 1644 // reg: divisor -1 1645 // 1646 // output: rax,: quotient (= rax, idiv reg) min_int 1647 // rdx: remainder (= rax, irem reg) 0 1648 // 1649 // Code sequnce: 1650 // 1651 // 81 F8 00 00 00 80 cmp rax,80000000h 1652 // 0F 85 0B 00 00 00 jne normal_case 1653 // 33 D2 xor rdx,edx 1654 // 83 F9 FF cmp rcx,0FFh 1655 // 0F 84 03 00 00 00 je done 1656 // normal_case: 1657 // 99 cdq 1658 // F7 F9 idiv rax,ecx 1659 // done: 1660 // 1661 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); 1662 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); 1663 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h 1664 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); 1665 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); 1666 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case 1667 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx 1668 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh 1669 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); 1670 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); 1671 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done 1672 // normal_case: 1673 emit_opcode(cbuf,0x99); // cdq 1674 // idiv (note: must be emitted by the user of this rule) 1675 // normal: 1676 %} 1677 1678 // Dense encoding for older common ops 1679 enc_class Opc_plus(immI opcode, rRegI reg) %{ 1680 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1681 %} 1682 1683 1684 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1685 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit 1686 // Check for 8-bit immediate, and set sign extend bit in opcode 1687 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1688 emit_opcode(cbuf, $primary | 0x02); 1689 } 1690 else { // If 32-bit immediate 1691 emit_opcode(cbuf, $primary); 1692 } 1693 %} 1694 1695 enc_class OpcSErm (rRegI dst, immI imm) %{ // OpcSEr/m 1696 // Emit primary opcode and set sign-extend bit 1697 // Check for 8-bit immediate, and set sign extend bit in opcode 1698 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1699 emit_opcode(cbuf, $primary | 0x02); } 1700 else { // If 32-bit immediate 1701 emit_opcode(cbuf, $primary); 1702 } 1703 // Emit r/m byte with secondary opcode, after primary opcode. 1704 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1705 %} 1706 1707 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits 1708 // Check for 8-bit immediate, and set sign extend bit in opcode 1709 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1710 $$$emit8$imm$$constant; 1711 } 1712 else { // If 32-bit immediate 1713 // Output immediate 1714 $$$emit32$imm$$constant; 1715 } 1716 %} 1717 1718 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ 1719 // Emit primary opcode and set sign-extend bit 1720 // Check for 8-bit immediate, and set sign extend bit in opcode 1721 int con = (int)$imm$$constant; // Throw away top bits 1722 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1723 // Emit r/m byte with secondary opcode, after primary opcode. 1724 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1725 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1726 else emit_d32(cbuf,con); 1727 %} 1728 1729 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ 1730 // Emit primary opcode and set sign-extend bit 1731 // Check for 8-bit immediate, and set sign extend bit in opcode 1732 int con = (int)($imm$$constant >> 32); // Throw away bottom bits 1733 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1734 // Emit r/m byte with tertiary opcode, after primary opcode. 1735 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1736 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1737 else emit_d32(cbuf,con); 1738 %} 1739 1740 enc_class OpcSReg (rRegI dst) %{ // BSWAP 1741 emit_cc(cbuf, $secondary, $dst$$reg ); 1742 %} 1743 1744 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1745 int destlo = $dst$$reg; 1746 int desthi = HIGH_FROM_LOW(destlo); 1747 // bswap lo 1748 emit_opcode(cbuf, 0x0F); 1749 emit_cc(cbuf, 0xC8, destlo); 1750 // bswap hi 1751 emit_opcode(cbuf, 0x0F); 1752 emit_cc(cbuf, 0xC8, desthi); 1753 // xchg lo and hi 1754 emit_opcode(cbuf, 0x87); 1755 emit_rm(cbuf, 0x3, destlo, desthi); 1756 %} 1757 1758 enc_class RegOpc (rRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1759 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1760 %} 1761 1762 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1763 $$$emit8$primary; 1764 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1765 %} 1766 1767 enc_class enc_cmov_dpr(cmpOp cop, regDPR src ) %{ // CMOV 1768 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); 1769 emit_d8(cbuf, op >> 8 ); 1770 emit_d8(cbuf, op & 255); 1771 %} 1772 1773 // emulate a CMOV with a conditional branch around a MOV 1774 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV 1775 // Invert sense of branch from sense of CMOV 1776 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); 1777 emit_d8( cbuf, $brOffs$$constant ); 1778 %} 1779 1780 enc_class enc_PartialSubtypeCheck( ) %{ 1781 Register Redi = as_Register(EDI_enc); // result register 1782 Register Reax = as_Register(EAX_enc); // super class 1783 Register Recx = as_Register(ECX_enc); // killed 1784 Register Resi = as_Register(ESI_enc); // sub class 1785 Label miss; 1786 1787 MacroAssembler _masm(&cbuf); 1788 __ check_klass_subtype_slow_path(Resi, Reax, Recx, Redi, 1789 NULL, &miss, 1790 /*set_cond_codes:*/ true); 1791 if ($primary) { 1792 __ xorptr(Redi, Redi); 1793 } 1794 __ bind(miss); 1795 %} 1796 1797 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All 1798 MacroAssembler masm(&cbuf); 1799 int start = masm.offset(); 1800 if (UseSSE >= 2) { 1801 if (VerifyFPU) { 1802 masm.verify_FPU(0, "must be empty in SSE2+ mode"); 1803 } 1804 } else { 1805 // External c_calling_convention expects the FPU stack to be 'clean'. 1806 // Compiled code leaves it dirty. Do cleanup now. 1807 masm.empty_FPU_stack(); 1808 } 1809 if (sizeof_FFree_Float_Stack_All == -1) { 1810 sizeof_FFree_Float_Stack_All = masm.offset() - start; 1811 } else { 1812 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); 1813 } 1814 %} 1815 1816 enc_class Verify_FPU_For_Leaf %{ 1817 if( VerifyFPU ) { 1818 MacroAssembler masm(&cbuf); 1819 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); 1820 } 1821 %} 1822 1823 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf 1824 // This is the instruction starting address for relocation info. 1825 cbuf.set_insts_mark(); 1826 $$$emit8$primary; 1827 // CALL directly to the runtime 1828 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1829 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1830 1831 if (UseSSE >= 2) { 1832 MacroAssembler _masm(&cbuf); 1833 BasicType rt = tf()->return_type(); 1834 1835 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { 1836 // A C runtime call where the return value is unused. In SSE2+ 1837 // mode the result needs to be removed from the FPU stack. It's 1838 // likely that this function call could be removed by the 1839 // optimizer if the C function is a pure function. 1840 __ ffree(0); 1841 } else if (rt == T_FLOAT) { 1842 __ lea(rsp, Address(rsp, -4)); 1843 __ fstp_s(Address(rsp, 0)); 1844 __ movflt(xmm0, Address(rsp, 0)); 1845 __ lea(rsp, Address(rsp, 4)); 1846 } else if (rt == T_DOUBLE) { 1847 __ lea(rsp, Address(rsp, -8)); 1848 __ fstp_d(Address(rsp, 0)); 1849 __ movdbl(xmm0, Address(rsp, 0)); 1850 __ lea(rsp, Address(rsp, 8)); 1851 } 1852 } 1853 %} 1854 1855 1856 enc_class pre_call_FPU %{ 1857 // If method sets FPU control word restore it here 1858 debug_only(int off0 = cbuf.insts_size()); 1859 if( Compile::current()->in_24_bit_fp_mode() ) { 1860 MacroAssembler masm(&cbuf); 1861 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1862 } 1863 debug_only(int off1 = cbuf.insts_size()); 1864 assert(off1 - off0 == pre_call_FPU_size(), "correct size prediction"); 1865 %} 1866 1867 enc_class post_call_FPU %{ 1868 // If method sets FPU control word do it here also 1869 if( Compile::current()->in_24_bit_fp_mode() ) { 1870 MacroAssembler masm(&cbuf); 1871 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1872 } 1873 %} 1874 1875 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1876 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1877 // who we intended to call. 1878 cbuf.set_insts_mark(); 1879 $$$emit8$primary; 1880 if ( !_method ) { 1881 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1882 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1883 } else if(_optimized_virtual) { 1884 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1885 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); 1886 } else { 1887 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.insts_end()) - 4), 1888 static_call_Relocation::spec(), RELOC_IMM32 ); 1889 } 1890 if( _method ) { // Emit stub for static call 1891 emit_java_to_interp(cbuf); 1892 } 1893 %} 1894 1895 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1896 MacroAssembler _masm(&cbuf); 1897 __ ic_call((address)$meth$$method); 1898 %} 1899 1900 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1901 int disp = in_bytes(Method::from_compiled_offset()); 1902 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1903 1904 // CALL *[EAX+in_bytes(Method::from_compiled_code_entry_point_offset())] 1905 cbuf.set_insts_mark(); 1906 $$$emit8$primary; 1907 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1908 emit_d8(cbuf, disp); // Displacement 1909 1910 %} 1911 1912 // Following encoding is no longer used, but may be restored if calling 1913 // convention changes significantly. 1914 // Became: Xor_Reg(EBP), Java_To_Runtime( labl ) 1915 // 1916 // enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL 1917 // // int ic_reg = Matcher::inline_cache_reg(); 1918 // // int ic_encode = Matcher::_regEncode[ic_reg]; 1919 // // int imo_reg = Matcher::interpreter_method_oop_reg(); 1920 // // int imo_encode = Matcher::_regEncode[imo_reg]; 1921 // 1922 // // // Interpreter expects method_oop in EBX, currently a callee-saved register, 1923 // // // so we load it immediately before the call 1924 // // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop 1925 // // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte 1926 // 1927 // // xor rbp,ebp 1928 // emit_opcode(cbuf, 0x33); 1929 // emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); 1930 // 1931 // // CALL to interpreter. 1932 // cbuf.set_insts_mark(); 1933 // $$$emit8$primary; 1934 // emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.insts_end()) - 4), 1935 // runtime_call_Relocation::spec(), RELOC_IMM32 ); 1936 // %} 1937 1938 enc_class RegOpcImm (rRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1939 $$$emit8$primary; 1940 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1941 $$$emit8$shift$$constant; 1942 %} 1943 1944 enc_class LdImmI (rRegI dst, immI src) %{ // Load Immediate 1945 // Load immediate does not have a zero or sign extended version 1946 // for 8-bit immediates 1947 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1948 $$$emit32$src$$constant; 1949 %} 1950 1951 enc_class LdImmP (rRegI dst, immI src) %{ // Load Immediate 1952 // Load immediate does not have a zero or sign extended version 1953 // for 8-bit immediates 1954 emit_opcode(cbuf, $primary + $dst$$reg); 1955 $$$emit32$src$$constant; 1956 %} 1957 1958 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate 1959 // Load immediate does not have a zero or sign extended version 1960 // for 8-bit immediates 1961 int dst_enc = $dst$$reg; 1962 int src_con = $src$$constant & 0x0FFFFFFFFL; 1963 if (src_con == 0) { 1964 // xor dst, dst 1965 emit_opcode(cbuf, 0x33); 1966 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1967 } else { 1968 emit_opcode(cbuf, $primary + dst_enc); 1969 emit_d32(cbuf, src_con); 1970 } 1971 %} 1972 1973 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate 1974 // Load immediate does not have a zero or sign extended version 1975 // for 8-bit immediates 1976 int dst_enc = $dst$$reg + 2; 1977 int src_con = ((julong)($src$$constant)) >> 32; 1978 if (src_con == 0) { 1979 // xor dst, dst 1980 emit_opcode(cbuf, 0x33); 1981 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1982 } else { 1983 emit_opcode(cbuf, $primary + dst_enc); 1984 emit_d32(cbuf, src_con); 1985 } 1986 %} 1987 1988 1989 // Encode a reg-reg copy. If it is useless, then empty encoding. 1990 enc_class enc_Copy( rRegI dst, rRegI src ) %{ 1991 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 1992 %} 1993 1994 enc_class enc_CopyL_Lo( rRegI dst, eRegL src ) %{ 1995 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 1996 %} 1997 1998 enc_class RegReg (rRegI dst, rRegI src) %{ // RegReg(Many) 1999 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2000 %} 2001 2002 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2003 $$$emit8$primary; 2004 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2005 %} 2006 2007 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) 2008 $$$emit8$secondary; 2009 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2010 %} 2011 2012 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) 2013 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2014 %} 2015 2016 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2017 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2018 %} 2019 2020 enc_class RegReg_HiLo( eRegL src, rRegI dst ) %{ 2021 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2022 %} 2023 2024 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2025 // Output immediate 2026 $$$emit32$src$$constant; 2027 %} 2028 2029 enc_class Con32FPR_as_bits(immFPR src) %{ // storeF_imm 2030 // Output Float immediate bits 2031 jfloat jf = $src$$constant; 2032 int jf_as_bits = jint_cast( jf ); 2033 emit_d32(cbuf, jf_as_bits); 2034 %} 2035 2036 enc_class Con32F_as_bits(immF src) %{ // storeX_imm 2037 // Output Float immediate bits 2038 jfloat jf = $src$$constant; 2039 int jf_as_bits = jint_cast( jf ); 2040 emit_d32(cbuf, jf_as_bits); 2041 %} 2042 2043 enc_class Con16 (immI src) %{ // Con16(storeImmI) 2044 // Output immediate 2045 $$$emit16$src$$constant; 2046 %} 2047 2048 enc_class Con_d32(immI src) %{ 2049 emit_d32(cbuf,$src$$constant); 2050 %} 2051 2052 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) 2053 // Output immediate memory reference 2054 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2055 emit_d32(cbuf, 0x00); 2056 %} 2057 2058 enc_class lock_prefix( ) %{ 2059 if( os::is_MP() ) 2060 emit_opcode(cbuf,0xF0); // [Lock] 2061 %} 2062 2063 // Cmp-xchg long value. 2064 // Note: we need to swap rbx, and rcx before and after the 2065 // cmpxchg8 instruction because the instruction uses 2066 // rcx as the high order word of the new value to store but 2067 // our register encoding uses rbx,. 2068 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ 2069 2070 // XCHG rbx,ecx 2071 emit_opcode(cbuf,0x87); 2072 emit_opcode(cbuf,0xD9); 2073 // [Lock] 2074 if( os::is_MP() ) 2075 emit_opcode(cbuf,0xF0); 2076 // CMPXCHG8 [Eptr] 2077 emit_opcode(cbuf,0x0F); 2078 emit_opcode(cbuf,0xC7); 2079 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2080 // XCHG rbx,ecx 2081 emit_opcode(cbuf,0x87); 2082 emit_opcode(cbuf,0xD9); 2083 %} 2084 2085 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ 2086 // [Lock] 2087 if( os::is_MP() ) 2088 emit_opcode(cbuf,0xF0); 2089 2090 // CMPXCHG [Eptr] 2091 emit_opcode(cbuf,0x0F); 2092 emit_opcode(cbuf,0xB1); 2093 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2094 %} 2095 2096 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ 2097 int res_encoding = $res$$reg; 2098 2099 // MOV res,0 2100 emit_opcode( cbuf, 0xB8 + res_encoding); 2101 emit_d32( cbuf, 0 ); 2102 // JNE,s fail 2103 emit_opcode(cbuf,0x75); 2104 emit_d8(cbuf, 5 ); 2105 // MOV res,1 2106 emit_opcode( cbuf, 0xB8 + res_encoding); 2107 emit_d32( cbuf, 1 ); 2108 // fail: 2109 %} 2110 2111 enc_class set_instruction_start( ) %{ 2112 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2113 %} 2114 2115 enc_class RegMem (rRegI ereg, memory mem) %{ // emit_reg_mem 2116 int reg_encoding = $ereg$$reg; 2117 int base = $mem$$base; 2118 int index = $mem$$index; 2119 int scale = $mem$$scale; 2120 int displace = $mem$$disp; 2121 relocInfo::relocType disp_reloc = $mem->disp_reloc(); 2122 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); 2123 %} 2124 2125 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2126 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2127 int base = $mem$$base; 2128 int index = $mem$$index; 2129 int scale = $mem$$scale; 2130 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2131 assert( $mem->disp_reloc() == relocInfo::none, "Cannot add 4 to oop" ); 2132 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, relocInfo::none); 2133 %} 2134 2135 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2136 int r1, r2; 2137 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2138 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2139 emit_opcode(cbuf,0x0F); 2140 emit_opcode(cbuf,$tertiary); 2141 emit_rm(cbuf, 0x3, r1, r2); 2142 emit_d8(cbuf,$cnt$$constant); 2143 emit_d8(cbuf,$primary); 2144 emit_rm(cbuf, 0x3, $secondary, r1); 2145 emit_d8(cbuf,$cnt$$constant); 2146 %} 2147 2148 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ 2149 emit_opcode( cbuf, 0x8B ); // Move 2150 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2151 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2152 emit_d8(cbuf,$primary); 2153 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 2154 emit_d8(cbuf,$cnt$$constant-32); 2155 } 2156 emit_d8(cbuf,$primary); 2157 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); 2158 emit_d8(cbuf,31); 2159 %} 2160 2161 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ 2162 int r1, r2; 2163 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2164 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2165 2166 emit_opcode( cbuf, 0x8B ); // Move r1,r2 2167 emit_rm(cbuf, 0x3, r1, r2); 2168 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2169 emit_opcode(cbuf,$primary); 2170 emit_rm(cbuf, 0x3, $secondary, r1); 2171 emit_d8(cbuf,$cnt$$constant-32); 2172 } 2173 emit_opcode(cbuf,0x33); // XOR r2,r2 2174 emit_rm(cbuf, 0x3, r2, r2); 2175 %} 2176 2177 // Clone of RegMem but accepts an extra parameter to access each 2178 // half of a double in memory; it never needs relocation info. 2179 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, rRegI rm_reg) %{ 2180 emit_opcode(cbuf,$opcode$$constant); 2181 int reg_encoding = $rm_reg$$reg; 2182 int base = $mem$$base; 2183 int index = $mem$$index; 2184 int scale = $mem$$scale; 2185 int displace = $mem$$disp + $disp_for_half$$constant; 2186 relocInfo::relocType disp_reloc = relocInfo::none; 2187 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); 2188 %} 2189 2190 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2191 // 2192 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2193 // and it never needs relocation information. 2194 // Frequently used to move data between FPU's Stack Top and memory. 2195 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ 2196 int rm_byte_opcode = $rm_opcode$$constant; 2197 int base = $mem$$base; 2198 int index = $mem$$index; 2199 int scale = $mem$$scale; 2200 int displace = $mem$$disp; 2201 assert( $mem->disp_reloc() == relocInfo::none, "No oops here because no reloc info allowed" ); 2202 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, relocInfo::none); 2203 %} 2204 2205 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2206 int rm_byte_opcode = $rm_opcode$$constant; 2207 int base = $mem$$base; 2208 int index = $mem$$index; 2209 int scale = $mem$$scale; 2210 int displace = $mem$$disp; 2211 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals 2212 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); 2213 %} 2214 2215 enc_class RegLea (rRegI dst, rRegI src0, immI src1 ) %{ // emit_reg_lea 2216 int reg_encoding = $dst$$reg; 2217 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2218 int index = 0x04; // 0x04 indicates no index 2219 int scale = 0x00; // 0x00 indicates no scale 2220 int displace = $src1$$constant; // 0x00 indicates no displacement 2221 relocInfo::relocType disp_reloc = relocInfo::none; 2222 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); 2223 %} 2224 2225 enc_class min_enc (rRegI dst, rRegI src) %{ // MIN 2226 // Compare dst,src 2227 emit_opcode(cbuf,0x3B); 2228 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2229 // jmp dst < src around move 2230 emit_opcode(cbuf,0x7C); 2231 emit_d8(cbuf,2); 2232 // move dst,src 2233 emit_opcode(cbuf,0x8B); 2234 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2235 %} 2236 2237 enc_class max_enc (rRegI dst, rRegI src) %{ // MAX 2238 // Compare dst,src 2239 emit_opcode(cbuf,0x3B); 2240 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2241 // jmp dst > src around move 2242 emit_opcode(cbuf,0x7F); 2243 emit_d8(cbuf,2); 2244 // move dst,src 2245 emit_opcode(cbuf,0x8B); 2246 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2247 %} 2248 2249 enc_class enc_FPR_store(memory mem, regDPR src) %{ 2250 // If src is FPR1, we can just FST to store it. 2251 // Else we need to FLD it to FPR1, then FSTP to store/pop it. 2252 int reg_encoding = 0x2; // Just store 2253 int base = $mem$$base; 2254 int index = $mem$$index; 2255 int scale = $mem$$scale; 2256 int displace = $mem$$disp; 2257 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals 2258 if( $src$$reg != FPR1L_enc ) { 2259 reg_encoding = 0x3; // Store & pop 2260 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2261 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2262 } 2263 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2264 emit_opcode(cbuf,$primary); 2265 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); 2266 %} 2267 2268 enc_class neg_reg(rRegI dst) %{ 2269 // NEG $dst 2270 emit_opcode(cbuf,0xF7); 2271 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2272 %} 2273 2274 enc_class setLT_reg(eCXRegI dst) %{ 2275 // SETLT $dst 2276 emit_opcode(cbuf,0x0F); 2277 emit_opcode(cbuf,0x9C); 2278 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); 2279 %} 2280 2281 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT 2282 int tmpReg = $tmp$$reg; 2283 2284 // SUB $p,$q 2285 emit_opcode(cbuf,0x2B); 2286 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2287 // SBB $tmp,$tmp 2288 emit_opcode(cbuf,0x1B); 2289 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2290 // AND $tmp,$y 2291 emit_opcode(cbuf,0x23); 2292 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); 2293 // ADD $p,$tmp 2294 emit_opcode(cbuf,0x03); 2295 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2296 %} 2297 2298 enc_class enc_cmpLTP_mem(rRegI p, rRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2299 int tmpReg = $tmp$$reg; 2300 2301 // SUB $p,$q 2302 emit_opcode(cbuf,0x2B); 2303 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2304 // SBB $tmp,$tmp 2305 emit_opcode(cbuf,0x1B); 2306 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2307 // AND $tmp,$y 2308 cbuf.set_insts_mark(); // Mark start of opcode for reloc info in mem operand 2309 emit_opcode(cbuf,0x23); 2310 int reg_encoding = tmpReg; 2311 int base = $mem$$base; 2312 int index = $mem$$index; 2313 int scale = $mem$$scale; 2314 int displace = $mem$$disp; 2315 relocInfo::relocType disp_reloc = $mem->disp_reloc(); 2316 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_reloc); 2317 // ADD $p,$tmp 2318 emit_opcode(cbuf,0x03); 2319 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2320 %} 2321 2322 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ 2323 // TEST shift,32 2324 emit_opcode(cbuf,0xF7); 2325 emit_rm(cbuf, 0x3, 0, ECX_enc); 2326 emit_d32(cbuf,0x20); 2327 // JEQ,s small 2328 emit_opcode(cbuf, 0x74); 2329 emit_d8(cbuf, 0x04); 2330 // MOV $dst.hi,$dst.lo 2331 emit_opcode( cbuf, 0x8B ); 2332 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2333 // CLR $dst.lo 2334 emit_opcode(cbuf, 0x33); 2335 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 2336 // small: 2337 // SHLD $dst.hi,$dst.lo,$shift 2338 emit_opcode(cbuf,0x0F); 2339 emit_opcode(cbuf,0xA5); 2340 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2341 // SHL $dst.lo,$shift" 2342 emit_opcode(cbuf,0xD3); 2343 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); 2344 %} 2345 2346 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ 2347 // TEST shift,32 2348 emit_opcode(cbuf,0xF7); 2349 emit_rm(cbuf, 0x3, 0, ECX_enc); 2350 emit_d32(cbuf,0x20); 2351 // JEQ,s small 2352 emit_opcode(cbuf, 0x74); 2353 emit_d8(cbuf, 0x04); 2354 // MOV $dst.lo,$dst.hi 2355 emit_opcode( cbuf, 0x8B ); 2356 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2357 // CLR $dst.hi 2358 emit_opcode(cbuf, 0x33); 2359 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); 2360 // small: 2361 // SHRD $dst.lo,$dst.hi,$shift 2362 emit_opcode(cbuf,0x0F); 2363 emit_opcode(cbuf,0xAD); 2364 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2365 // SHR $dst.hi,$shift" 2366 emit_opcode(cbuf,0xD3); 2367 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); 2368 %} 2369 2370 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ 2371 // TEST shift,32 2372 emit_opcode(cbuf,0xF7); 2373 emit_rm(cbuf, 0x3, 0, ECX_enc); 2374 emit_d32(cbuf,0x20); 2375 // JEQ,s small 2376 emit_opcode(cbuf, 0x74); 2377 emit_d8(cbuf, 0x05); 2378 // MOV $dst.lo,$dst.hi 2379 emit_opcode( cbuf, 0x8B ); 2380 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2381 // SAR $dst.hi,31 2382 emit_opcode(cbuf, 0xC1); 2383 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); 2384 emit_d8(cbuf, 0x1F ); 2385 // small: 2386 // SHRD $dst.lo,$dst.hi,$shift 2387 emit_opcode(cbuf,0x0F); 2388 emit_opcode(cbuf,0xAD); 2389 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2390 // SAR $dst.hi,$shift" 2391 emit_opcode(cbuf,0xD3); 2392 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); 2393 %} 2394 2395 2396 // ----------------- Encodings for floating point unit ----------------- 2397 // May leave result in FPU-TOS or FPU reg depending on opcodes 2398 enc_class OpcReg_FPR(regFPR src) %{ // FMUL, FDIV 2399 $$$emit8$primary; 2400 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); 2401 %} 2402 2403 // Pop argument in FPR0 with FSTP ST(0) 2404 enc_class PopFPU() %{ 2405 emit_opcode( cbuf, 0xDD ); 2406 emit_d8( cbuf, 0xD8 ); 2407 %} 2408 2409 // !!!!! equivalent to Pop_Reg_F 2410 enc_class Pop_Reg_DPR( regDPR dst ) %{ 2411 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2412 emit_d8( cbuf, 0xD8+$dst$$reg ); 2413 %} 2414 2415 enc_class Push_Reg_DPR( regDPR dst ) %{ 2416 emit_opcode( cbuf, 0xD9 ); 2417 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) 2418 %} 2419 2420 enc_class strictfp_bias1( regDPR dst ) %{ 2421 emit_opcode( cbuf, 0xDB ); // FLD m80real 2422 emit_opcode( cbuf, 0x2D ); 2423 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); 2424 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2425 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2426 %} 2427 2428 enc_class strictfp_bias2( regDPR dst ) %{ 2429 emit_opcode( cbuf, 0xDB ); // FLD m80real 2430 emit_opcode( cbuf, 0x2D ); 2431 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); 2432 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2433 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2434 %} 2435 2436 // Special case for moving an integer register to a stack slot. 2437 enc_class OpcPRegSS( stackSlotI dst, rRegI src ) %{ // RegSS 2438 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2439 %} 2440 2441 // Special case for moving a register to a stack slot. 2442 enc_class RegSS( stackSlotI dst, rRegI src ) %{ // RegSS 2443 // Opcode already emitted 2444 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2445 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2446 emit_d32(cbuf, $dst$$disp); // Displacement 2447 %} 2448 2449 // Push the integer in stackSlot 'src' onto FP-stack 2450 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] 2451 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); 2452 %} 2453 2454 // Push FPU's TOS float to a stack-slot, and pop FPU-stack 2455 enc_class Pop_Mem_FPR( stackSlotF dst ) %{ // FSTP_S [ESP+dst] 2456 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); 2457 %} 2458 2459 // Same as Pop_Mem_F except for opcode 2460 // Push FPU's TOS double to a stack-slot, and pop FPU-stack 2461 enc_class Pop_Mem_DPR( stackSlotD dst ) %{ // FSTP_D [ESP+dst] 2462 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); 2463 %} 2464 2465 enc_class Pop_Reg_FPR( regFPR dst ) %{ 2466 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2467 emit_d8( cbuf, 0xD8+$dst$$reg ); 2468 %} 2469 2470 enc_class Push_Reg_FPR( regFPR dst ) %{ 2471 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2472 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2473 %} 2474 2475 // Push FPU's float to a stack-slot, and pop FPU-stack 2476 enc_class Pop_Mem_Reg_FPR( stackSlotF dst, regFPR src ) %{ 2477 int pop = 0x02; 2478 if ($src$$reg != FPR1L_enc) { 2479 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2480 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2481 pop = 0x03; 2482 } 2483 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] 2484 %} 2485 2486 // Push FPU's double to a stack-slot, and pop FPU-stack 2487 enc_class Pop_Mem_Reg_DPR( stackSlotD dst, regDPR src ) %{ 2488 int pop = 0x02; 2489 if ($src$$reg != FPR1L_enc) { 2490 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2491 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2492 pop = 0x03; 2493 } 2494 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] 2495 %} 2496 2497 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack 2498 enc_class Pop_Reg_Reg_DPR( regDPR dst, regFPR src ) %{ 2499 int pop = 0xD0 - 1; // -1 since we skip FLD 2500 if ($src$$reg != FPR1L_enc) { 2501 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) 2502 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2503 pop = 0xD8; 2504 } 2505 emit_opcode( cbuf, 0xDD ); 2506 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) 2507 %} 2508 2509 2510 enc_class Push_Reg_Mod_DPR( regDPR dst, regDPR src) %{ 2511 // load dst in FPR0 2512 emit_opcode( cbuf, 0xD9 ); 2513 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2514 if ($src$$reg != FPR1L_enc) { 2515 // fincstp 2516 emit_opcode (cbuf, 0xD9); 2517 emit_opcode (cbuf, 0xF7); 2518 // swap src with FPR1: 2519 // FXCH FPR1 with src 2520 emit_opcode(cbuf, 0xD9); 2521 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2522 // fdecstp 2523 emit_opcode (cbuf, 0xD9); 2524 emit_opcode (cbuf, 0xF6); 2525 } 2526 %} 2527 2528 enc_class Push_ModD_encoding(regD src0, regD src1) %{ 2529 MacroAssembler _masm(&cbuf); 2530 __ subptr(rsp, 8); 2531 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); 2532 __ fld_d(Address(rsp, 0)); 2533 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); 2534 __ fld_d(Address(rsp, 0)); 2535 %} 2536 2537 enc_class Push_ModF_encoding(regF src0, regF src1) %{ 2538 MacroAssembler _masm(&cbuf); 2539 __ subptr(rsp, 4); 2540 __ movflt(Address(rsp, 0), $src1$$XMMRegister); 2541 __ fld_s(Address(rsp, 0)); 2542 __ movflt(Address(rsp, 0), $src0$$XMMRegister); 2543 __ fld_s(Address(rsp, 0)); 2544 %} 2545 2546 enc_class Push_ResultD(regD dst) %{ 2547 MacroAssembler _masm(&cbuf); 2548 __ fstp_d(Address(rsp, 0)); 2549 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); 2550 __ addptr(rsp, 8); 2551 %} 2552 2553 enc_class Push_ResultF(regF dst, immI d8) %{ 2554 MacroAssembler _masm(&cbuf); 2555 __ fstp_s(Address(rsp, 0)); 2556 __ movflt($dst$$XMMRegister, Address(rsp, 0)); 2557 __ addptr(rsp, $d8$$constant); 2558 %} 2559 2560 enc_class Push_SrcD(regD src) %{ 2561 MacroAssembler _masm(&cbuf); 2562 __ subptr(rsp, 8); 2563 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 2564 __ fld_d(Address(rsp, 0)); 2565 %} 2566 2567 enc_class push_stack_temp_qword() %{ 2568 MacroAssembler _masm(&cbuf); 2569 __ subptr(rsp, 8); 2570 %} 2571 2572 enc_class pop_stack_temp_qword() %{ 2573 MacroAssembler _masm(&cbuf); 2574 __ addptr(rsp, 8); 2575 %} 2576 2577 enc_class push_xmm_to_fpr1(regD src) %{ 2578 MacroAssembler _masm(&cbuf); 2579 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 2580 __ fld_d(Address(rsp, 0)); 2581 %} 2582 2583 enc_class Push_Result_Mod_DPR( regDPR src) %{ 2584 if ($src$$reg != FPR1L_enc) { 2585 // fincstp 2586 emit_opcode (cbuf, 0xD9); 2587 emit_opcode (cbuf, 0xF7); 2588 // FXCH FPR1 with src 2589 emit_opcode(cbuf, 0xD9); 2590 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2591 // fdecstp 2592 emit_opcode (cbuf, 0xD9); 2593 emit_opcode (cbuf, 0xF6); 2594 } 2595 // // following asm replaced with Pop_Reg_F or Pop_Mem_F 2596 // // FSTP FPR$dst$$reg 2597 // emit_opcode( cbuf, 0xDD ); 2598 // emit_d8( cbuf, 0xD8+$dst$$reg ); 2599 %} 2600 2601 enc_class fnstsw_sahf_skip_parity() %{ 2602 // fnstsw ax 2603 emit_opcode( cbuf, 0xDF ); 2604 emit_opcode( cbuf, 0xE0 ); 2605 // sahf 2606 emit_opcode( cbuf, 0x9E ); 2607 // jnp ::skip 2608 emit_opcode( cbuf, 0x7B ); 2609 emit_opcode( cbuf, 0x05 ); 2610 %} 2611 2612 enc_class emitModDPR() %{ 2613 // fprem must be iterative 2614 // :: loop 2615 // fprem 2616 emit_opcode( cbuf, 0xD9 ); 2617 emit_opcode( cbuf, 0xF8 ); 2618 // wait 2619 emit_opcode( cbuf, 0x9b ); 2620 // fnstsw ax 2621 emit_opcode( cbuf, 0xDF ); 2622 emit_opcode( cbuf, 0xE0 ); 2623 // sahf 2624 emit_opcode( cbuf, 0x9E ); 2625 // jp ::loop 2626 emit_opcode( cbuf, 0x0F ); 2627 emit_opcode( cbuf, 0x8A ); 2628 emit_opcode( cbuf, 0xF4 ); 2629 emit_opcode( cbuf, 0xFF ); 2630 emit_opcode( cbuf, 0xFF ); 2631 emit_opcode( cbuf, 0xFF ); 2632 %} 2633 2634 enc_class fpu_flags() %{ 2635 // fnstsw_ax 2636 emit_opcode( cbuf, 0xDF); 2637 emit_opcode( cbuf, 0xE0); 2638 // test ax,0x0400 2639 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate 2640 emit_opcode( cbuf, 0xA9 ); 2641 emit_d16 ( cbuf, 0x0400 ); 2642 // // // This sequence works, but stalls for 12-16 cycles on PPro 2643 // // test rax,0x0400 2644 // emit_opcode( cbuf, 0xA9 ); 2645 // emit_d32 ( cbuf, 0x00000400 ); 2646 // 2647 // jz exit (no unordered comparison) 2648 emit_opcode( cbuf, 0x74 ); 2649 emit_d8 ( cbuf, 0x02 ); 2650 // mov ah,1 - treat as LT case (set carry flag) 2651 emit_opcode( cbuf, 0xB4 ); 2652 emit_d8 ( cbuf, 0x01 ); 2653 // sahf 2654 emit_opcode( cbuf, 0x9E); 2655 %} 2656 2657 enc_class cmpF_P6_fixup() %{ 2658 // Fixup the integer flags in case comparison involved a NaN 2659 // 2660 // JNP exit (no unordered comparison, P-flag is set by NaN) 2661 emit_opcode( cbuf, 0x7B ); 2662 emit_d8 ( cbuf, 0x03 ); 2663 // MOV AH,1 - treat as LT case (set carry flag) 2664 emit_opcode( cbuf, 0xB4 ); 2665 emit_d8 ( cbuf, 0x01 ); 2666 // SAHF 2667 emit_opcode( cbuf, 0x9E); 2668 // NOP // target for branch to avoid branch to branch 2669 emit_opcode( cbuf, 0x90); 2670 %} 2671 2672 // fnstsw_ax(); 2673 // sahf(); 2674 // movl(dst, nan_result); 2675 // jcc(Assembler::parity, exit); 2676 // movl(dst, less_result); 2677 // jcc(Assembler::below, exit); 2678 // movl(dst, equal_result); 2679 // jcc(Assembler::equal, exit); 2680 // movl(dst, greater_result); 2681 2682 // less_result = 1; 2683 // greater_result = -1; 2684 // equal_result = 0; 2685 // nan_result = -1; 2686 2687 enc_class CmpF_Result(rRegI dst) %{ 2688 // fnstsw_ax(); 2689 emit_opcode( cbuf, 0xDF); 2690 emit_opcode( cbuf, 0xE0); 2691 // sahf 2692 emit_opcode( cbuf, 0x9E); 2693 // movl(dst, nan_result); 2694 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2695 emit_d32( cbuf, -1 ); 2696 // jcc(Assembler::parity, exit); 2697 emit_opcode( cbuf, 0x7A ); 2698 emit_d8 ( cbuf, 0x13 ); 2699 // movl(dst, less_result); 2700 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2701 emit_d32( cbuf, -1 ); 2702 // jcc(Assembler::below, exit); 2703 emit_opcode( cbuf, 0x72 ); 2704 emit_d8 ( cbuf, 0x0C ); 2705 // movl(dst, equal_result); 2706 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2707 emit_d32( cbuf, 0 ); 2708 // jcc(Assembler::equal, exit); 2709 emit_opcode( cbuf, 0x74 ); 2710 emit_d8 ( cbuf, 0x05 ); 2711 // movl(dst, greater_result); 2712 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2713 emit_d32( cbuf, 1 ); 2714 %} 2715 2716 2717 // Compare the longs and set flags 2718 // BROKEN! Do Not use as-is 2719 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ 2720 // CMP $src1.hi,$src2.hi 2721 emit_opcode( cbuf, 0x3B ); 2722 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2723 // JNE,s done 2724 emit_opcode(cbuf,0x75); 2725 emit_d8(cbuf, 2 ); 2726 // CMP $src1.lo,$src2.lo 2727 emit_opcode( cbuf, 0x3B ); 2728 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2729 // done: 2730 %} 2731 2732 enc_class convert_int_long( regL dst, rRegI src ) %{ 2733 // mov $dst.lo,$src 2734 int dst_encoding = $dst$$reg; 2735 int src_encoding = $src$$reg; 2736 encode_Copy( cbuf, dst_encoding , src_encoding ); 2737 // mov $dst.hi,$src 2738 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); 2739 // sar $dst.hi,31 2740 emit_opcode( cbuf, 0xC1 ); 2741 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); 2742 emit_d8(cbuf, 0x1F ); 2743 %} 2744 2745 enc_class convert_long_double( eRegL src ) %{ 2746 // push $src.hi 2747 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2748 // push $src.lo 2749 emit_opcode(cbuf, 0x50+$src$$reg ); 2750 // fild 64-bits at [SP] 2751 emit_opcode(cbuf,0xdf); 2752 emit_d8(cbuf, 0x6C); 2753 emit_d8(cbuf, 0x24); 2754 emit_d8(cbuf, 0x00); 2755 // pop stack 2756 emit_opcode(cbuf, 0x83); // add SP, #8 2757 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2758 emit_d8(cbuf, 0x8); 2759 %} 2760 2761 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ 2762 // IMUL EDX:EAX,$src1 2763 emit_opcode( cbuf, 0xF7 ); 2764 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); 2765 // SAR EDX,$cnt-32 2766 int shift_count = ((int)$cnt$$constant) - 32; 2767 if (shift_count > 0) { 2768 emit_opcode(cbuf, 0xC1); 2769 emit_rm(cbuf, 0x3, 7, $dst$$reg ); 2770 emit_d8(cbuf, shift_count); 2771 } 2772 %} 2773 2774 // this version doesn't have add sp, 8 2775 enc_class convert_long_double2( eRegL src ) %{ 2776 // push $src.hi 2777 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2778 // push $src.lo 2779 emit_opcode(cbuf, 0x50+$src$$reg ); 2780 // fild 64-bits at [SP] 2781 emit_opcode(cbuf,0xdf); 2782 emit_d8(cbuf, 0x6C); 2783 emit_d8(cbuf, 0x24); 2784 emit_d8(cbuf, 0x00); 2785 %} 2786 2787 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ 2788 // Basic idea: long = (long)int * (long)int 2789 // IMUL EDX:EAX, src 2790 emit_opcode( cbuf, 0xF7 ); 2791 emit_rm( cbuf, 0x3, 0x5, $src$$reg); 2792 %} 2793 2794 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ 2795 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 2796 // MUL EDX:EAX, src 2797 emit_opcode( cbuf, 0xF7 ); 2798 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2799 %} 2800 2801 enc_class long_multiply( eADXRegL dst, eRegL src, rRegI tmp ) %{ 2802 // Basic idea: lo(result) = lo(x_lo * y_lo) 2803 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2804 // MOV $tmp,$src.lo 2805 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2806 // IMUL $tmp,EDX 2807 emit_opcode( cbuf, 0x0F ); 2808 emit_opcode( cbuf, 0xAF ); 2809 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2810 // MOV EDX,$src.hi 2811 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); 2812 // IMUL EDX,EAX 2813 emit_opcode( cbuf, 0x0F ); 2814 emit_opcode( cbuf, 0xAF ); 2815 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2816 // ADD $tmp,EDX 2817 emit_opcode( cbuf, 0x03 ); 2818 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2819 // MUL EDX:EAX,$src.lo 2820 emit_opcode( cbuf, 0xF7 ); 2821 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); 2822 // ADD EDX,ESI 2823 emit_opcode( cbuf, 0x03 ); 2824 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 2825 %} 2826 2827 enc_class long_multiply_con( eADXRegL dst, immL_127 src, rRegI tmp ) %{ 2828 // Basic idea: lo(result) = lo(src * y_lo) 2829 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 2830 // IMUL $tmp,EDX,$src 2831 emit_opcode( cbuf, 0x6B ); 2832 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2833 emit_d8( cbuf, (int)$src$$constant ); 2834 // MOV EDX,$src 2835 emit_opcode(cbuf, 0xB8 + EDX_enc); 2836 emit_d32( cbuf, (int)$src$$constant ); 2837 // MUL EDX:EAX,EDX 2838 emit_opcode( cbuf, 0xF7 ); 2839 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); 2840 // ADD EDX,ESI 2841 emit_opcode( cbuf, 0x03 ); 2842 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); 2843 %} 2844 2845 enc_class long_div( eRegL src1, eRegL src2 ) %{ 2846 // PUSH src1.hi 2847 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 2848 // PUSH src1.lo 2849 emit_opcode(cbuf, 0x50+$src1$$reg ); 2850 // PUSH src2.hi 2851 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 2852 // PUSH src2.lo 2853 emit_opcode(cbuf, 0x50+$src2$$reg ); 2854 // CALL directly to the runtime 2855 cbuf.set_insts_mark(); 2856 emit_opcode(cbuf,0xE8); // Call into runtime 2857 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 2858 // Restore stack 2859 emit_opcode(cbuf, 0x83); // add SP, #framesize 2860 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2861 emit_d8(cbuf, 4*4); 2862 %} 2863 2864 enc_class long_mod( eRegL src1, eRegL src2 ) %{ 2865 // PUSH src1.hi 2866 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 2867 // PUSH src1.lo 2868 emit_opcode(cbuf, 0x50+$src1$$reg ); 2869 // PUSH src2.hi 2870 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 2871 // PUSH src2.lo 2872 emit_opcode(cbuf, 0x50+$src2$$reg ); 2873 // CALL directly to the runtime 2874 cbuf.set_insts_mark(); 2875 emit_opcode(cbuf,0xE8); // Call into runtime 2876 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 2877 // Restore stack 2878 emit_opcode(cbuf, 0x83); // add SP, #framesize 2879 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2880 emit_d8(cbuf, 4*4); 2881 %} 2882 2883 enc_class long_cmp_flags0( eRegL src, rRegI tmp ) %{ 2884 // MOV $tmp,$src.lo 2885 emit_opcode(cbuf, 0x8B); 2886 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2887 // OR $tmp,$src.hi 2888 emit_opcode(cbuf, 0x0B); 2889 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 2890 %} 2891 2892 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ 2893 // CMP $src1.lo,$src2.lo 2894 emit_opcode( cbuf, 0x3B ); 2895 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2896 // JNE,s skip 2897 emit_cc(cbuf, 0x70, 0x5); 2898 emit_d8(cbuf,2); 2899 // CMP $src1.hi,$src2.hi 2900 emit_opcode( cbuf, 0x3B ); 2901 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2902 %} 2903 2904 enc_class long_cmp_flags2( eRegL src1, eRegL src2, rRegI tmp ) %{ 2905 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 2906 emit_opcode( cbuf, 0x3B ); 2907 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2908 // MOV $tmp,$src1.hi 2909 emit_opcode( cbuf, 0x8B ); 2910 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); 2911 // SBB $tmp,$src2.hi\t! Compute flags for long compare 2912 emit_opcode( cbuf, 0x1B ); 2913 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 2914 %} 2915 2916 enc_class long_cmp_flags3( eRegL src, rRegI tmp ) %{ 2917 // XOR $tmp,$tmp 2918 emit_opcode(cbuf,0x33); // XOR 2919 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 2920 // CMP $tmp,$src.lo 2921 emit_opcode( cbuf, 0x3B ); 2922 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); 2923 // SBB $tmp,$src.hi 2924 emit_opcode( cbuf, 0x1B ); 2925 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); 2926 %} 2927 2928 // Sniff, sniff... smells like Gnu Superoptimizer 2929 enc_class neg_long( eRegL dst ) %{ 2930 emit_opcode(cbuf,0xF7); // NEG hi 2931 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 2932 emit_opcode(cbuf,0xF7); // NEG lo 2933 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); 2934 emit_opcode(cbuf,0x83); // SBB hi,0 2935 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 2936 emit_d8 (cbuf,0 ); 2937 %} 2938 2939 2940 // Because the transitions from emitted code to the runtime 2941 // monitorenter/exit helper stubs are so slow it's critical that 2942 // we inline both the stack-locking fast-path and the inflated fast path. 2943 // 2944 // See also: cmpFastLock and cmpFastUnlock. 2945 // 2946 // What follows is a specialized inline transliteration of the code 2947 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 2948 // another option would be to emit TrySlowEnter and TrySlowExit methods 2949 // at startup-time. These methods would accept arguments as 2950 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 2951 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 2952 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 2953 // In practice, however, the # of lock sites is bounded and is usually small. 2954 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 2955 // if the processor uses simple bimodal branch predictors keyed by EIP 2956 // Since the helper routines would be called from multiple synchronization 2957 // sites. 2958 // 2959 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 2960 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 2961 // to those specialized methods. That'd give us a mostly platform-independent 2962 // implementation that the JITs could optimize and inline at their pleasure. 2963 // Done correctly, the only time we'd need to cross to native could would be 2964 // to park() or unpark() threads. We'd also need a few more unsafe operators 2965 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 2966 // (b) explicit barriers or fence operations. 2967 // 2968 // TODO: 2969 // 2970 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 2971 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 2972 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 2973 // the lock operators would typically be faster than reifying Self. 2974 // 2975 // * Ideally I'd define the primitives as: 2976 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 2977 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 2978 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 2979 // Instead, we're stuck with a rather awkward and brittle register assignments below. 2980 // Furthermore the register assignments are overconstrained, possibly resulting in 2981 // sub-optimal code near the synchronization site. 2982 // 2983 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 2984 // Alternately, use a better sp-proximity test. 2985 // 2986 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 2987 // Either one is sufficient to uniquely identify a thread. 2988 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 2989 // 2990 // * Intrinsify notify() and notifyAll() for the common cases where the 2991 // object is locked by the calling thread but the waitlist is empty. 2992 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 2993 // 2994 // * use jccb and jmpb instead of jcc and jmp to improve code density. 2995 // But beware of excessive branch density on AMD Opterons. 2996 // 2997 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 2998 // or failure of the fast-path. If the fast-path fails then we pass 2999 // control to the slow-path, typically in C. In Fast_Lock and 3000 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 3001 // will emit a conditional branch immediately after the node. 3002 // So we have branches to branches and lots of ICC.ZF games. 3003 // Instead, it might be better to have C2 pass a "FailureLabel" 3004 // into Fast_Lock and Fast_Unlock. In the case of success, control 3005 // will drop through the node. ICC.ZF is undefined at exit. 3006 // In the case of failure, the node will branch directly to the 3007 // FailureLabel 3008 3009 3010 // obj: object to lock 3011 // box: on-stack box address (displaced header location) - KILLED 3012 // rax,: tmp -- KILLED 3013 // scr: tmp -- KILLED 3014 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ 3015 3016 Register objReg = as_Register($obj$$reg); 3017 Register boxReg = as_Register($box$$reg); 3018 Register tmpReg = as_Register($tmp$$reg); 3019 Register scrReg = as_Register($scr$$reg); 3020 3021 // Ensure the register assignents are disjoint 3022 guarantee (objReg != boxReg, "") ; 3023 guarantee (objReg != tmpReg, "") ; 3024 guarantee (objReg != scrReg, "") ; 3025 guarantee (boxReg != tmpReg, "") ; 3026 guarantee (boxReg != scrReg, "") ; 3027 guarantee (tmpReg == as_Register(EAX_enc), "") ; 3028 3029 MacroAssembler masm(&cbuf); 3030 3031 if (_counters != NULL) { 3032 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); 3033 } 3034 if (EmitSync & 1) { 3035 // set box->dhw = unused_mark (3) 3036 // Force all sync thru slow-path: slow_enter() and slow_exit() 3037 masm.movptr (Address(boxReg, 0), int32_t(markOopDesc::unused_mark())) ; 3038 masm.cmpptr (rsp, (int32_t)0) ; 3039 } else 3040 if (EmitSync & 2) { 3041 Label DONE_LABEL ; 3042 if (UseBiasedLocking) { 3043 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. 3044 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3045 } 3046 3047 masm.movptr(tmpReg, Address(objReg, 0)) ; // fetch markword 3048 masm.orptr (tmpReg, 0x1); 3049 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3050 if (os::is_MP()) { masm.lock(); } 3051 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3052 masm.jcc(Assembler::equal, DONE_LABEL); 3053 // Recursive locking 3054 masm.subptr(tmpReg, rsp); 3055 masm.andptr(tmpReg, (int32_t) 0xFFFFF003 ); 3056 masm.movptr(Address(boxReg, 0), tmpReg); 3057 masm.bind(DONE_LABEL) ; 3058 } else { 3059 // Possible cases that we'll encounter in fast_lock 3060 // ------------------------------------------------ 3061 // * Inflated 3062 // -- unlocked 3063 // -- Locked 3064 // = by self 3065 // = by other 3066 // * biased 3067 // -- by Self 3068 // -- by other 3069 // * neutral 3070 // * stack-locked 3071 // -- by self 3072 // = sp-proximity test hits 3073 // = sp-proximity test generates false-negative 3074 // -- by other 3075 // 3076 3077 Label IsInflated, DONE_LABEL, PopDone ; 3078 3079 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 3080 // order to reduce the number of conditional branches in the most common cases. 3081 // Beware -- there's a subtle invariant that fetch of the markword 3082 // at [FETCH], below, will never observe a biased encoding (*101b). 3083 // If this invariant is not held we risk exclusion (safety) failure. 3084 if (UseBiasedLocking && !UseOptoBiasInlining) { 3085 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3086 } 3087 3088 masm.movptr(tmpReg, Address(objReg, 0)) ; // [FETCH] 3089 masm.testptr(tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) 3090 masm.jccb (Assembler::notZero, IsInflated) ; 3091 3092 // Attempt stack-locking ... 3093 masm.orptr (tmpReg, 0x1); 3094 masm.movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3095 if (os::is_MP()) { masm.lock(); } 3096 masm.cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 3097 if (_counters != NULL) { 3098 masm.cond_inc32(Assembler::equal, 3099 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3100 } 3101 masm.jccb (Assembler::equal, DONE_LABEL); 3102 3103 // Recursive locking 3104 masm.subptr(tmpReg, rsp); 3105 masm.andptr(tmpReg, 0xFFFFF003 ); 3106 masm.movptr(Address(boxReg, 0), tmpReg); 3107 if (_counters != NULL) { 3108 masm.cond_inc32(Assembler::equal, 3109 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3110 } 3111 masm.jmp (DONE_LABEL) ; 3112 3113 masm.bind (IsInflated) ; 3114 3115 // The object is inflated. 3116 // 3117 // TODO-FIXME: eliminate the ugly use of manifest constants: 3118 // Use markOopDesc::monitor_value instead of "2". 3119 // use markOop::unused_mark() instead of "3". 3120 // The tmpReg value is an objectMonitor reference ORed with 3121 // markOopDesc::monitor_value (2). We can either convert tmpReg to an 3122 // objectmonitor pointer by masking off the "2" bit or we can just 3123 // use tmpReg as an objectmonitor pointer but bias the objectmonitor 3124 // field offsets with "-2" to compensate for and annul the low-order tag bit. 3125 // 3126 // I use the latter as it avoids AGI stalls. 3127 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" 3128 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". 3129 // 3130 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) 3131 3132 // boxReg refers to the on-stack BasicLock in the current frame. 3133 // We'd like to write: 3134 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. 3135 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 3136 // additional latency as we have another ST in the store buffer that must drain. 3137 3138 if (EmitSync & 8192) { 3139 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3140 masm.get_thread (scrReg) ; 3141 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3142 masm.movptr(tmpReg, NULL_WORD); // consider: xor vs mov 3143 if (os::is_MP()) { masm.lock(); } 3144 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3145 } else 3146 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3147 masm.movptr(scrReg, boxReg) ; 3148 masm.movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 3149 3150 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3151 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3152 // prefetchw [eax + Offset(_owner)-2] 3153 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3154 } 3155 3156 if ((EmitSync & 64) == 0) { 3157 // Optimistic form: consider XORL tmpReg,tmpReg 3158 masm.movptr(tmpReg, NULL_WORD) ; 3159 } else { 3160 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3161 // Test-And-CAS instead of CAS 3162 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3163 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3164 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3165 } 3166 3167 // Appears unlocked - try to swing _owner from null to non-null. 3168 // Ideally, I'd manifest "Self" with get_thread and then attempt 3169 // to CAS the register containing Self into m->Owner. 3170 // But we don't have enough registers, so instead we can either try to CAS 3171 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 3172 // we later store "Self" into m->Owner. Transiently storing a stack address 3173 // (rsp or the address of the box) into m->owner is harmless. 3174 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3175 if (os::is_MP()) { masm.lock(); } 3176 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3177 masm.movptr(Address(scrReg, 0), 3) ; // box->_displaced_header = 3 3178 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3179 masm.get_thread (scrReg) ; // beware: clobbers ICCs 3180 masm.movptr(Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 3181 masm.xorptr(boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success 3182 3183 // If the CAS fails we can either retry or pass control to the slow-path. 3184 // We use the latter tactic. 3185 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3186 // If the CAS was successful ... 3187 // Self has acquired the lock 3188 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3189 // Intentional fall-through into DONE_LABEL ... 3190 } else { 3191 masm.movptr(Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3192 masm.movptr(boxReg, tmpReg) ; 3193 3194 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3195 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3196 // prefetchw [eax + Offset(_owner)-2] 3197 masm.prefetchw(Address(rax, ObjectMonitor::owner_offset_in_bytes()-2)); 3198 } 3199 3200 if ((EmitSync & 64) == 0) { 3201 // Optimistic form 3202 masm.xorptr (tmpReg, tmpReg) ; 3203 } else { 3204 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3205 masm.movptr(tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3206 masm.testptr(tmpReg, tmpReg) ; // Locked ? 3207 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3208 } 3209 3210 // Appears unlocked - try to swing _owner from null to non-null. 3211 // Use either "Self" (in scr) or rsp as thread identity in _owner. 3212 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3213 masm.get_thread (scrReg) ; 3214 if (os::is_MP()) { masm.lock(); } 3215 masm.cmpxchgptr(scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3216 3217 // If the CAS fails we can either retry or pass control to the slow-path. 3218 // We use the latter tactic. 3219 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3220 // If the CAS was successful ... 3221 // Self has acquired the lock 3222 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3223 // Intentional fall-through into DONE_LABEL ... 3224 } 3225 3226 // DONE_LABEL is a hot target - we'd really like to place it at the 3227 // start of cache line by padding with NOPs. 3228 // See the AMD and Intel software optimization manuals for the 3229 // most efficient "long" NOP encodings. 3230 // Unfortunately none of our alignment mechanisms suffice. 3231 masm.bind(DONE_LABEL); 3232 3233 // Avoid branch-to-branch on AMD processors 3234 // This appears to be superstition. 3235 if (EmitSync & 32) masm.nop() ; 3236 3237 3238 // At DONE_LABEL the icc ZFlag is set as follows ... 3239 // Fast_Unlock uses the same protocol. 3240 // ZFlag == 1 -> Success 3241 // ZFlag == 0 -> Failure - force control through the slow-path 3242 } 3243 %} 3244 3245 // obj: object to unlock 3246 // box: box address (displaced header location), killed. Must be EAX. 3247 // rbx,: killed tmp; cannot be obj nor box. 3248 // 3249 // Some commentary on balanced locking: 3250 // 3251 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 3252 // Methods that don't have provably balanced locking are forced to run in the 3253 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 3254 // The interpreter provides two properties: 3255 // I1: At return-time the interpreter automatically and quietly unlocks any 3256 // objects acquired the current activation (frame). Recall that the 3257 // interpreter maintains an on-stack list of locks currently held by 3258 // a frame. 3259 // I2: If a method attempts to unlock an object that is not held by the 3260 // the frame the interpreter throws IMSX. 3261 // 3262 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 3263 // B() doesn't have provably balanced locking so it runs in the interpreter. 3264 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 3265 // is still locked by A(). 3266 // 3267 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 3268 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 3269 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 3270 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 3271 3272 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ 3273 3274 Register objReg = as_Register($obj$$reg); 3275 Register boxReg = as_Register($box$$reg); 3276 Register tmpReg = as_Register($tmp$$reg); 3277 3278 guarantee (objReg != boxReg, "") ; 3279 guarantee (objReg != tmpReg, "") ; 3280 guarantee (boxReg != tmpReg, "") ; 3281 guarantee (boxReg == as_Register(EAX_enc), "") ; 3282 MacroAssembler masm(&cbuf); 3283 3284 if (EmitSync & 4) { 3285 // Disable - inhibit all inlining. Force control through the slow-path 3286 masm.cmpptr (rsp, 0) ; 3287 } else 3288 if (EmitSync & 8) { 3289 Label DONE_LABEL ; 3290 if (UseBiasedLocking) { 3291 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3292 } 3293 // classic stack-locking code ... 3294 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3295 masm.testptr(tmpReg, tmpReg) ; 3296 masm.jcc (Assembler::zero, DONE_LABEL) ; 3297 if (os::is_MP()) { masm.lock(); } 3298 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3299 masm.bind(DONE_LABEL); 3300 } else { 3301 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; 3302 3303 // Critically, the biased locking test must have precedence over 3304 // and appear before the (box->dhw == 0) recursive stack-lock test. 3305 if (UseBiasedLocking && !UseOptoBiasInlining) { 3306 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3307 } 3308 3309 masm.cmpptr(Address(boxReg, 0), 0) ; // Examine the displaced header 3310 masm.movptr(tmpReg, Address(objReg, 0)) ; // Examine the object's markword 3311 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock 3312 3313 masm.testptr(tmpReg, 0x02) ; // Inflated? 3314 masm.jccb (Assembler::zero, Stacked) ; 3315 3316 masm.bind (Inflated) ; 3317 // It's inflated. 3318 // Despite our balanced locking property we still check that m->_owner == Self 3319 // as java routines or native JNI code called by this thread might 3320 // have released the lock. 3321 // Refer to the comments in synchronizer.cpp for how we might encode extra 3322 // state in _succ so we can avoid fetching EntryList|cxq. 3323 // 3324 // I'd like to add more cases in fast_lock() and fast_unlock() -- 3325 // such as recursive enter and exit -- but we have to be wary of 3326 // I$ bloat, T$ effects and BP$ effects. 3327 // 3328 // If there's no contention try a 1-0 exit. That is, exit without 3329 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 3330 // we detect and recover from the race that the 1-0 exit admits. 3331 // 3332 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 3333 // before it STs null into _owner, releasing the lock. Updates 3334 // to data protected by the critical section must be visible before 3335 // we drop the lock (and thus before any other thread could acquire 3336 // the lock and observe the fields protected by the lock). 3337 // IA32's memory-model is SPO, so STs are ordered with respect to 3338 // each other and there's no need for an explicit barrier (fence). 3339 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3340 3341 masm.get_thread (boxReg) ; 3342 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 3343 // prefetchw [ebx + Offset(_owner)-2] 3344 masm.prefetchw(Address(rbx, ObjectMonitor::owner_offset_in_bytes()-2)); 3345 } 3346 3347 // Note that we could employ various encoding schemes to reduce 3348 // the number of loads below (currently 4) to just 2 or 3. 3349 // Refer to the comments in synchronizer.cpp. 3350 // In practice the chain of fetches doesn't seem to impact performance, however. 3351 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 3352 // Attempt to reduce branch density - AMD's branch predictor. 3353 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3354 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3355 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3356 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3357 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3358 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3359 masm.jmpb (DONE_LABEL) ; 3360 } else { 3361 masm.xorptr(boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3362 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3363 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3364 masm.movptr(boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3365 masm.orptr(boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3366 masm.jccb (Assembler::notZero, CheckSucc) ; 3367 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3368 masm.jmpb (DONE_LABEL) ; 3369 } 3370 3371 // The Following code fragment (EmitSync & 65536) improves the performance of 3372 // contended applications and contended synchronization microbenchmarks. 3373 // Unfortunately the emission of the code - even though not executed - causes regressions 3374 // in scimark and jetstream, evidently because of $ effects. Replacing the code 3375 // with an equal number of never-executed NOPs results in the same regression. 3376 // We leave it off by default. 3377 3378 if ((EmitSync & 65536) != 0) { 3379 Label LSuccess, LGoSlowPath ; 3380 3381 masm.bind (CheckSucc) ; 3382 3383 // Optional pre-test ... it's safe to elide this 3384 if ((EmitSync & 16) == 0) { 3385 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3386 masm.jccb (Assembler::zero, LGoSlowPath) ; 3387 } 3388 3389 // We have a classic Dekker-style idiom: 3390 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 3391 // There are a number of ways to implement the barrier: 3392 // (1) lock:andl &m->_owner, 0 3393 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 3394 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 3395 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 3396 // (2) If supported, an explicit MFENCE is appealing. 3397 // In older IA32 processors MFENCE is slower than lock:add or xchg 3398 // particularly if the write-buffer is full as might be the case if 3399 // if stores closely precede the fence or fence-equivalent instruction. 3400 // In more modern implementations MFENCE appears faster, however. 3401 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 3402 // The $lines underlying the top-of-stack should be in M-state. 3403 // The locked add instruction is serializing, of course. 3404 // (4) Use xchg, which is serializing 3405 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 3406 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 3407 // The integer condition codes will tell us if succ was 0. 3408 // Since _succ and _owner should reside in the same $line and 3409 // we just stored into _owner, it's likely that the $line 3410 // remains in M-state for the lock:orl. 3411 // 3412 // We currently use (3), although it's likely that switching to (2) 3413 // is correct for the future. 3414 3415 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), NULL_WORD) ; 3416 if (os::is_MP()) { 3417 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 3418 masm.mfence(); 3419 } else { 3420 masm.lock () ; masm.addptr(Address(rsp, 0), 0) ; 3421 } 3422 } 3423 // Ratify _succ remains non-null 3424 masm.cmpptr(Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3425 masm.jccb (Assembler::notZero, LSuccess) ; 3426 3427 masm.xorptr(boxReg, boxReg) ; // box is really EAX 3428 if (os::is_MP()) { masm.lock(); } 3429 masm.cmpxchgptr(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); 3430 masm.jccb (Assembler::notEqual, LSuccess) ; 3431 // Since we're low on registers we installed rsp as a placeholding in _owner. 3432 // Now install Self over rsp. This is safe as we're transitioning from 3433 // non-null to non=null 3434 masm.get_thread (boxReg) ; 3435 masm.movptr(Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; 3436 // Intentional fall-through into LGoSlowPath ... 3437 3438 masm.bind (LGoSlowPath) ; 3439 masm.orptr(boxReg, 1) ; // set ICC.ZF=0 to indicate failure 3440 masm.jmpb (DONE_LABEL) ; 3441 3442 masm.bind (LSuccess) ; 3443 masm.xorptr(boxReg, boxReg) ; // set ICC.ZF=1 to indicate success 3444 masm.jmpb (DONE_LABEL) ; 3445 } 3446 3447 masm.bind (Stacked) ; 3448 // It's not inflated and it's not recursively stack-locked and it's not biased. 3449 // It must be stack-locked. 3450 // Try to reset the header to displaced header. 3451 // The "box" value on the stack is stable, so we can reload 3452 // and be assured we observe the same value as above. 3453 masm.movptr(tmpReg, Address(boxReg, 0)) ; 3454 if (os::is_MP()) { masm.lock(); } 3455 masm.cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3456 // Intention fall-thru into DONE_LABEL 3457 3458 3459 // DONE_LABEL is a hot target - we'd really like to place it at the 3460 // start of cache line by padding with NOPs. 3461 // See the AMD and Intel software optimization manuals for the 3462 // most efficient "long" NOP encodings. 3463 // Unfortunately none of our alignment mechanisms suffice. 3464 if ((EmitSync & 65536) == 0) { 3465 masm.bind (CheckSucc) ; 3466 } 3467 masm.bind(DONE_LABEL); 3468 3469 // Avoid branch to branch on AMD processors 3470 if (EmitSync & 32768) { masm.nop() ; } 3471 } 3472 %} 3473 3474 3475 enc_class enc_pop_rdx() %{ 3476 emit_opcode(cbuf,0x5A); 3477 %} 3478 3479 enc_class enc_rethrow() %{ 3480 cbuf.set_insts_mark(); 3481 emit_opcode(cbuf, 0xE9); // jmp entry 3482 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.insts_end())-4, 3483 runtime_call_Relocation::spec(), RELOC_IMM32 ); 3484 %} 3485 3486 3487 // Convert a double to an int. Java semantics require we do complex 3488 // manglelations in the corner cases. So we set the rounding mode to 3489 // 'zero', store the darned double down as an int, and reset the 3490 // rounding mode to 'nearest'. The hardware throws an exception which 3491 // patches up the correct value directly to the stack. 3492 enc_class DPR2I_encoding( regDPR src ) %{ 3493 // Flip to round-to-zero mode. We attempted to allow invalid-op 3494 // exceptions here, so that a NAN or other corner-case value will 3495 // thrown an exception (but normal values get converted at full speed). 3496 // However, I2C adapters and other float-stack manglers leave pending 3497 // invalid-op exceptions hanging. We would have to clear them before 3498 // enabling them and that is more expensive than just testing for the 3499 // invalid value Intel stores down in the corner cases. 3500 emit_opcode(cbuf,0xD9); // FLDCW trunc 3501 emit_opcode(cbuf,0x2D); 3502 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3503 // Allocate a word 3504 emit_opcode(cbuf,0x83); // SUB ESP,4 3505 emit_opcode(cbuf,0xEC); 3506 emit_d8(cbuf,0x04); 3507 // Encoding assumes a double has been pushed into FPR0. 3508 // Store down the double as an int, popping the FPU stack 3509 emit_opcode(cbuf,0xDB); // FISTP [ESP] 3510 emit_opcode(cbuf,0x1C); 3511 emit_d8(cbuf,0x24); 3512 // Restore the rounding mode; mask the exception 3513 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3514 emit_opcode(cbuf,0x2D); 3515 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3516 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3517 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3518 3519 // Load the converted int; adjust CPU stack 3520 emit_opcode(cbuf,0x58); // POP EAX 3521 emit_opcode(cbuf,0x3D); // CMP EAX,imm 3522 emit_d32 (cbuf,0x80000000); // 0x80000000 3523 emit_opcode(cbuf,0x75); // JNE around_slow_call 3524 emit_d8 (cbuf,0x07); // Size of slow_call 3525 // Push src onto stack slow-path 3526 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3527 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3528 // CALL directly to the runtime 3529 cbuf.set_insts_mark(); 3530 emit_opcode(cbuf,0xE8); // Call into runtime 3531 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3532 // Carry on here... 3533 %} 3534 3535 enc_class DPR2L_encoding( regDPR src ) %{ 3536 emit_opcode(cbuf,0xD9); // FLDCW trunc 3537 emit_opcode(cbuf,0x2D); 3538 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3539 // Allocate a word 3540 emit_opcode(cbuf,0x83); // SUB ESP,8 3541 emit_opcode(cbuf,0xEC); 3542 emit_d8(cbuf,0x08); 3543 // Encoding assumes a double has been pushed into FPR0. 3544 // Store down the double as a long, popping the FPU stack 3545 emit_opcode(cbuf,0xDF); // FISTP [ESP] 3546 emit_opcode(cbuf,0x3C); 3547 emit_d8(cbuf,0x24); 3548 // Restore the rounding mode; mask the exception 3549 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3550 emit_opcode(cbuf,0x2D); 3551 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3552 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3553 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3554 3555 // Load the converted int; adjust CPU stack 3556 emit_opcode(cbuf,0x58); // POP EAX 3557 emit_opcode(cbuf,0x5A); // POP EDX 3558 emit_opcode(cbuf,0x81); // CMP EDX,imm 3559 emit_d8 (cbuf,0xFA); // rdx 3560 emit_d32 (cbuf,0x80000000); // 0x80000000 3561 emit_opcode(cbuf,0x75); // JNE around_slow_call 3562 emit_d8 (cbuf,0x07+4); // Size of slow_call 3563 emit_opcode(cbuf,0x85); // TEST EAX,EAX 3564 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 3565 emit_opcode(cbuf,0x75); // JNE around_slow_call 3566 emit_d8 (cbuf,0x07); // Size of slow_call 3567 // Push src onto stack slow-path 3568 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3569 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3570 // CALL directly to the runtime 3571 cbuf.set_insts_mark(); 3572 emit_opcode(cbuf,0xE8); // Call into runtime 3573 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.insts_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3574 // Carry on here... 3575 %} 3576 3577 enc_class FMul_ST_reg( eRegFPR src1 ) %{ 3578 // Operand was loaded from memory into fp ST (stack top) 3579 // FMUL ST,$src /* D8 C8+i */ 3580 emit_opcode(cbuf, 0xD8); 3581 emit_opcode(cbuf, 0xC8 + $src1$$reg); 3582 %} 3583 3584 enc_class FAdd_ST_reg( eRegFPR src2 ) %{ 3585 // FADDP ST,src2 /* D8 C0+i */ 3586 emit_opcode(cbuf, 0xD8); 3587 emit_opcode(cbuf, 0xC0 + $src2$$reg); 3588 //could use FADDP src2,fpST /* DE C0+i */ 3589 %} 3590 3591 enc_class FAddP_reg_ST( eRegFPR src2 ) %{ 3592 // FADDP src2,ST /* DE C0+i */ 3593 emit_opcode(cbuf, 0xDE); 3594 emit_opcode(cbuf, 0xC0 + $src2$$reg); 3595 %} 3596 3597 enc_class subFPR_divFPR_encode( eRegFPR src1, eRegFPR src2) %{ 3598 // Operand has been loaded into fp ST (stack top) 3599 // FSUB ST,$src1 3600 emit_opcode(cbuf, 0xD8); 3601 emit_opcode(cbuf, 0xE0 + $src1$$reg); 3602 3603 // FDIV 3604 emit_opcode(cbuf, 0xD8); 3605 emit_opcode(cbuf, 0xF0 + $src2$$reg); 3606 %} 3607 3608 enc_class MulFAddF (eRegFPR src1, eRegFPR src2) %{ 3609 // Operand was loaded from memory into fp ST (stack top) 3610 // FADD ST,$src /* D8 C0+i */ 3611 emit_opcode(cbuf, 0xD8); 3612 emit_opcode(cbuf, 0xC0 + $src1$$reg); 3613 3614 // FMUL ST,src2 /* D8 C*+i */ 3615 emit_opcode(cbuf, 0xD8); 3616 emit_opcode(cbuf, 0xC8 + $src2$$reg); 3617 %} 3618 3619 3620 enc_class MulFAddFreverse (eRegFPR src1, eRegFPR src2) %{ 3621 // Operand was loaded from memory into fp ST (stack top) 3622 // FADD ST,$src /* D8 C0+i */ 3623 emit_opcode(cbuf, 0xD8); 3624 emit_opcode(cbuf, 0xC0 + $src1$$reg); 3625 3626 // FMULP src2,ST /* DE C8+i */ 3627 emit_opcode(cbuf, 0xDE); 3628 emit_opcode(cbuf, 0xC8 + $src2$$reg); 3629 %} 3630 3631 // Atomically load the volatile long 3632 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ 3633 emit_opcode(cbuf,0xDF); 3634 int rm_byte_opcode = 0x05; 3635 int base = $mem$$base; 3636 int index = $mem$$index; 3637 int scale = $mem$$scale; 3638 int displace = $mem$$disp; 3639 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals 3640 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); 3641 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 3642 %} 3643 3644 // Volatile Store Long. Must be atomic, so move it into 3645 // the FP TOS and then do a 64-bit FIST. Has to probe the 3646 // target address before the store (for null-ptr checks) 3647 // so the memory operand is used twice in the encoding. 3648 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ 3649 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); 3650 cbuf.set_insts_mark(); // Mark start of FIST in case $mem has an oop 3651 emit_opcode(cbuf,0xDF); 3652 int rm_byte_opcode = 0x07; 3653 int base = $mem$$base; 3654 int index = $mem$$index; 3655 int scale = $mem$$scale; 3656 int displace = $mem$$disp; 3657 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when working with static globals 3658 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_reloc); 3659 %} 3660 3661 // Safepoint Poll. This polls the safepoint page, and causes an 3662 // exception if it is not readable. Unfortunately, it kills the condition code 3663 // in the process 3664 // We current use TESTL [spp],EDI 3665 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 3666 3667 enc_class Safepoint_Poll() %{ 3668 cbuf.relocate(cbuf.insts_mark(), relocInfo::poll_type, 0); 3669 emit_opcode(cbuf,0x85); 3670 emit_rm (cbuf, 0x0, 0x7, 0x5); 3671 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 3672 %} 3673 %} 3674 3675 3676 //----------FRAME-------------------------------------------------------------- 3677 // Definition of frame structure and management information. 3678 // 3679 // S T A C K L A Y O U T Allocators stack-slot number 3680 // | (to get allocators register number 3681 // G Owned by | | v add OptoReg::stack0()) 3682 // r CALLER | | 3683 // o | +--------+ pad to even-align allocators stack-slot 3684 // w V | pad0 | numbers; owned by CALLER 3685 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3686 // h ^ | in | 5 3687 // | | args | 4 Holes in incoming args owned by SELF 3688 // | | | | 3 3689 // | | +--------+ 3690 // V | | old out| Empty on Intel, window on Sparc 3691 // | old |preserve| Must be even aligned. 3692 // | SP-+--------+----> Matcher::_old_SP, even aligned 3693 // | | in | 3 area for Intel ret address 3694 // Owned by |preserve| Empty on Sparc. 3695 // SELF +--------+ 3696 // | | pad2 | 2 pad to align old SP 3697 // | +--------+ 1 3698 // | | locks | 0 3699 // | +--------+----> OptoReg::stack0(), even aligned 3700 // | | pad1 | 11 pad to align new SP 3701 // | +--------+ 3702 // | | | 10 3703 // | | spills | 9 spills 3704 // V | | 8 (pad0 slot for callee) 3705 // -----------+--------+----> Matcher::_out_arg_limit, unaligned 3706 // ^ | out | 7 3707 // | | args | 6 Holes in outgoing args owned by CALLEE 3708 // Owned by +--------+ 3709 // CALLEE | new out| 6 Empty on Intel, window on Sparc 3710 // | new |preserve| Must be even-aligned. 3711 // | SP-+--------+----> Matcher::_new_SP, even aligned 3712 // | | | 3713 // 3714 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3715 // known from SELF's arguments and the Java calling convention. 3716 // Region 6-7 is determined per call site. 3717 // Note 2: If the calling convention leaves holes in the incoming argument 3718 // area, those holes are owned by SELF. Holes in the outgoing area 3719 // are owned by the CALLEE. Holes should not be nessecary in the 3720 // incoming area, as the Java calling convention is completely under 3721 // the control of the AD file. Doubles can be sorted and packed to 3722 // avoid holes. Holes in the outgoing arguments may be nessecary for 3723 // varargs C calling conventions. 3724 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3725 // even aligned with pad0 as needed. 3726 // Region 6 is even aligned. Region 6-7 is NOT even aligned; 3727 // region 6-11 is even aligned; it may be padded out more so that 3728 // the region from SP to FP meets the minimum stack alignment. 3729 3730 frame %{ 3731 // What direction does stack grow in (assumed to be same for C & Java) 3732 stack_direction(TOWARDS_LOW); 3733 3734 // These three registers define part of the calling convention 3735 // between compiled code and the interpreter. 3736 inline_cache_reg(EAX); // Inline Cache Register 3737 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter 3738 3739 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3740 cisc_spilling_operand_name(indOffset32); 3741 3742 // Number of stack slots consumed by locking an object 3743 sync_stack_slots(1); 3744 3745 // Compiled code's Frame Pointer 3746 frame_pointer(ESP); 3747 // Interpreter stores its frame pointer in a register which is 3748 // stored to the stack by I2CAdaptors. 3749 // I2CAdaptors convert from interpreted java to compiled java. 3750 interpreter_frame_pointer(EBP); 3751 3752 // Stack alignment requirement 3753 // Alignment size in bytes (128-bit -> 16 bytes) 3754 stack_alignment(StackAlignmentInBytes); 3755 3756 // Number of stack slots between incoming argument block and the start of 3757 // a new frame. The PROLOG must add this many slots to the stack. The 3758 // EPILOG must remove this many slots. Intel needs one slot for 3759 // return address and one for rbp, (must save rbp) 3760 in_preserve_stack_slots(2+VerifyStackAtCalls); 3761 3762 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3763 // for calls to C. Supports the var-args backing area for register parms. 3764 varargs_C_out_slots_killed(0); 3765 3766 // The after-PROLOG location of the return address. Location of 3767 // return address specifies a type (REG or STACK) and a number 3768 // representing the register number (i.e. - use a register name) or 3769 // stack slot. 3770 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 3771 // Otherwise, it is above the locks and verification slot and alignment word 3772 return_addr(STACK - 1 + 3773 round_to((Compile::current()->in_preserve_stack_slots() + 3774 Compile::current()->fixed_slots()), 3775 stack_alignment_in_slots())); 3776 3777 // Body of function which returns an integer array locating 3778 // arguments either in registers or in stack slots. Passed an array 3779 // of ideal registers called "sig" and a "length" count. Stack-slot 3780 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3781 // arguments for a CALLEE. Incoming stack arguments are 3782 // automatically biased by the preserve_stack_slots field above. 3783 calling_convention %{ 3784 // No difference between ingoing/outgoing just pass false 3785 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3786 %} 3787 3788 3789 // Body of function which returns an integer array locating 3790 // arguments either in registers or in stack slots. Passed an array 3791 // of ideal registers called "sig" and a "length" count. Stack-slot 3792 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3793 // arguments for a CALLEE. Incoming stack arguments are 3794 // automatically biased by the preserve_stack_slots field above. 3795 c_calling_convention %{ 3796 // This is obviously always outgoing 3797 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3798 %} 3799 3800 // Location of C & interpreter return values 3801 c_return_value %{ 3802 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3803 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 3804 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3805 3806 // in SSE2+ mode we want to keep the FPU stack clean so pretend 3807 // that C functions return float and double results in XMM0. 3808 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3809 return OptoRegPair(XMM0b_num,XMM0_num); 3810 if( ideal_reg == Op_RegF && UseSSE>=2 ) 3811 return OptoRegPair(OptoReg::Bad,XMM0_num); 3812 3813 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3814 %} 3815 3816 // Location of return values 3817 return_value %{ 3818 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3819 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 3820 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 3821 if( ideal_reg == Op_RegD && UseSSE>=2 ) 3822 return OptoRegPair(XMM0b_num,XMM0_num); 3823 if( ideal_reg == Op_RegF && UseSSE>=1 ) 3824 return OptoRegPair(OptoReg::Bad,XMM0_num); 3825 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 3826 %} 3827 3828 %} 3829 3830 //----------ATTRIBUTES--------------------------------------------------------- 3831 //----------Operand Attributes------------------------------------------------- 3832 op_attrib op_cost(0); // Required cost attribute 3833 3834 //----------Instruction Attributes--------------------------------------------- 3835 ins_attrib ins_cost(100); // Required cost attribute 3836 ins_attrib ins_size(8); // Required size attribute (in bits) 3837 ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3838 // non-matching short branch variant of some 3839 // long branch? 3840 ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) 3841 // specifies the alignment that some part of the instruction (not 3842 // necessarily the start) requires. If > 1, a compute_padding() 3843 // function must be provided for the instruction 3844 3845 //----------OPERANDS----------------------------------------------------------- 3846 // Operand definitions must precede instruction definitions for correct parsing 3847 // in the ADLC because operands constitute user defined types which are used in 3848 // instruction definitions. 3849 3850 //----------Simple Operands---------------------------------------------------- 3851 // Immediate Operands 3852 // Integer Immediate 3853 operand immI() %{ 3854 match(ConI); 3855 3856 op_cost(10); 3857 format %{ %} 3858 interface(CONST_INTER); 3859 %} 3860 3861 // Constant for test vs zero 3862 operand immI0() %{ 3863 predicate(n->get_int() == 0); 3864 match(ConI); 3865 3866 op_cost(0); 3867 format %{ %} 3868 interface(CONST_INTER); 3869 %} 3870 3871 // Constant for increment 3872 operand immI1() %{ 3873 predicate(n->get_int() == 1); 3874 match(ConI); 3875 3876 op_cost(0); 3877 format %{ %} 3878 interface(CONST_INTER); 3879 %} 3880 3881 // Constant for decrement 3882 operand immI_M1() %{ 3883 predicate(n->get_int() == -1); 3884 match(ConI); 3885 3886 op_cost(0); 3887 format %{ %} 3888 interface(CONST_INTER); 3889 %} 3890 3891 // Valid scale values for addressing modes 3892 operand immI2() %{ 3893 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 3894 match(ConI); 3895 3896 format %{ %} 3897 interface(CONST_INTER); 3898 %} 3899 3900 operand immI8() %{ 3901 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); 3902 match(ConI); 3903 3904 op_cost(5); 3905 format %{ %} 3906 interface(CONST_INTER); 3907 %} 3908 3909 operand immI16() %{ 3910 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 3911 match(ConI); 3912 3913 op_cost(10); 3914 format %{ %} 3915 interface(CONST_INTER); 3916 %} 3917 3918 // Constant for long shifts 3919 operand immI_32() %{ 3920 predicate( n->get_int() == 32 ); 3921 match(ConI); 3922 3923 op_cost(0); 3924 format %{ %} 3925 interface(CONST_INTER); 3926 %} 3927 3928 operand immI_1_31() %{ 3929 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 3930 match(ConI); 3931 3932 op_cost(0); 3933 format %{ %} 3934 interface(CONST_INTER); 3935 %} 3936 3937 operand immI_32_63() %{ 3938 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); 3939 match(ConI); 3940 op_cost(0); 3941 3942 format %{ %} 3943 interface(CONST_INTER); 3944 %} 3945 3946 operand immI_1() %{ 3947 predicate( n->get_int() == 1 ); 3948 match(ConI); 3949 3950 op_cost(0); 3951 format %{ %} 3952 interface(CONST_INTER); 3953 %} 3954 3955 operand immI_2() %{ 3956 predicate( n->get_int() == 2 ); 3957 match(ConI); 3958 3959 op_cost(0); 3960 format %{ %} 3961 interface(CONST_INTER); 3962 %} 3963 3964 operand immI_3() %{ 3965 predicate( n->get_int() == 3 ); 3966 match(ConI); 3967 3968 op_cost(0); 3969 format %{ %} 3970 interface(CONST_INTER); 3971 %} 3972 3973 // Pointer Immediate 3974 operand immP() %{ 3975 match(ConP); 3976 3977 op_cost(10); 3978 format %{ %} 3979 interface(CONST_INTER); 3980 %} 3981 3982 // NULL Pointer Immediate 3983 operand immP0() %{ 3984 predicate( n->get_ptr() == 0 ); 3985 match(ConP); 3986 op_cost(0); 3987 3988 format %{ %} 3989 interface(CONST_INTER); 3990 %} 3991 3992 // Long Immediate 3993 operand immL() %{ 3994 match(ConL); 3995 3996 op_cost(20); 3997 format %{ %} 3998 interface(CONST_INTER); 3999 %} 4000 4001 // Long Immediate zero 4002 operand immL0() %{ 4003 predicate( n->get_long() == 0L ); 4004 match(ConL); 4005 op_cost(0); 4006 4007 format %{ %} 4008 interface(CONST_INTER); 4009 %} 4010 4011 // Long Immediate zero 4012 operand immL_M1() %{ 4013 predicate( n->get_long() == -1L ); 4014 match(ConL); 4015 op_cost(0); 4016 4017 format %{ %} 4018 interface(CONST_INTER); 4019 %} 4020 4021 // Long immediate from 0 to 127. 4022 // Used for a shorter form of long mul by 10. 4023 operand immL_127() %{ 4024 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); 4025 match(ConL); 4026 op_cost(0); 4027 4028 format %{ %} 4029 interface(CONST_INTER); 4030 %} 4031 4032 // Long Immediate: low 32-bit mask 4033 operand immL_32bits() %{ 4034 predicate(n->get_long() == 0xFFFFFFFFL); 4035 match(ConL); 4036 op_cost(0); 4037 4038 format %{ %} 4039 interface(CONST_INTER); 4040 %} 4041 4042 // Long Immediate: low 32-bit mask 4043 operand immL32() %{ 4044 predicate(n->get_long() == (int)(n->get_long())); 4045 match(ConL); 4046 op_cost(20); 4047 4048 format %{ %} 4049 interface(CONST_INTER); 4050 %} 4051 4052 //Double Immediate zero 4053 operand immDPR0() %{ 4054 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4055 // bug that generates code such that NaNs compare equal to 0.0 4056 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); 4057 match(ConD); 4058 4059 op_cost(5); 4060 format %{ %} 4061 interface(CONST_INTER); 4062 %} 4063 4064 // Double Immediate one 4065 operand immDPR1() %{ 4066 predicate( UseSSE<=1 && n->getd() == 1.0 ); 4067 match(ConD); 4068 4069 op_cost(5); 4070 format %{ %} 4071 interface(CONST_INTER); 4072 %} 4073 4074 // Double Immediate 4075 operand immDPR() %{ 4076 predicate(UseSSE<=1); 4077 match(ConD); 4078 4079 op_cost(5); 4080 format %{ %} 4081 interface(CONST_INTER); 4082 %} 4083 4084 operand immD() %{ 4085 predicate(UseSSE>=2); 4086 match(ConD); 4087 4088 op_cost(5); 4089 format %{ %} 4090 interface(CONST_INTER); 4091 %} 4092 4093 // Double Immediate zero 4094 operand immD0() %{ 4095 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4096 // bug that generates code such that NaNs compare equal to 0.0 AND do not 4097 // compare equal to -0.0. 4098 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); 4099 match(ConD); 4100 4101 format %{ %} 4102 interface(CONST_INTER); 4103 %} 4104 4105 // Float Immediate zero 4106 operand immFPR0() %{ 4107 predicate(UseSSE == 0 && n->getf() == 0.0F); 4108 match(ConF); 4109 4110 op_cost(5); 4111 format %{ %} 4112 interface(CONST_INTER); 4113 %} 4114 4115 // Float Immediate one 4116 operand immFPR1() %{ 4117 predicate(UseSSE == 0 && n->getf() == 1.0F); 4118 match(ConF); 4119 4120 op_cost(5); 4121 format %{ %} 4122 interface(CONST_INTER); 4123 %} 4124 4125 // Float Immediate 4126 operand immFPR() %{ 4127 predicate( UseSSE == 0 ); 4128 match(ConF); 4129 4130 op_cost(5); 4131 format %{ %} 4132 interface(CONST_INTER); 4133 %} 4134 4135 // Float Immediate 4136 operand immF() %{ 4137 predicate(UseSSE >= 1); 4138 match(ConF); 4139 4140 op_cost(5); 4141 format %{ %} 4142 interface(CONST_INTER); 4143 %} 4144 4145 // Float Immediate zero. Zero and not -0.0 4146 operand immF0() %{ 4147 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); 4148 match(ConF); 4149 4150 op_cost(5); 4151 format %{ %} 4152 interface(CONST_INTER); 4153 %} 4154 4155 // Immediates for special shifts (sign extend) 4156 4157 // Constants for increment 4158 operand immI_16() %{ 4159 predicate( n->get_int() == 16 ); 4160 match(ConI); 4161 4162 format %{ %} 4163 interface(CONST_INTER); 4164 %} 4165 4166 operand immI_24() %{ 4167 predicate( n->get_int() == 24 ); 4168 match(ConI); 4169 4170 format %{ %} 4171 interface(CONST_INTER); 4172 %} 4173 4174 // Constant for byte-wide masking 4175 operand immI_255() %{ 4176 predicate( n->get_int() == 255 ); 4177 match(ConI); 4178 4179 format %{ %} 4180 interface(CONST_INTER); 4181 %} 4182 4183 // Constant for short-wide masking 4184 operand immI_65535() %{ 4185 predicate(n->get_int() == 65535); 4186 match(ConI); 4187 4188 format %{ %} 4189 interface(CONST_INTER); 4190 %} 4191 4192 // Register Operands 4193 // Integer Register 4194 operand rRegI() %{ 4195 constraint(ALLOC_IN_RC(int_reg)); 4196 match(RegI); 4197 match(xRegI); 4198 match(eAXRegI); 4199 match(eBXRegI); 4200 match(eCXRegI); 4201 match(eDXRegI); 4202 match(eDIRegI); 4203 match(eSIRegI); 4204 4205 format %{ %} 4206 interface(REG_INTER); 4207 %} 4208 4209 // Subset of Integer Register 4210 operand xRegI(rRegI reg) %{ 4211 constraint(ALLOC_IN_RC(int_x_reg)); 4212 match(reg); 4213 match(eAXRegI); 4214 match(eBXRegI); 4215 match(eCXRegI); 4216 match(eDXRegI); 4217 4218 format %{ %} 4219 interface(REG_INTER); 4220 %} 4221 4222 // Special Registers 4223 operand eAXRegI(xRegI reg) %{ 4224 constraint(ALLOC_IN_RC(eax_reg)); 4225 match(reg); 4226 match(rRegI); 4227 4228 format %{ "EAX" %} 4229 interface(REG_INTER); 4230 %} 4231 4232 // Special Registers 4233 operand eBXRegI(xRegI reg) %{ 4234 constraint(ALLOC_IN_RC(ebx_reg)); 4235 match(reg); 4236 match(rRegI); 4237 4238 format %{ "EBX" %} 4239 interface(REG_INTER); 4240 %} 4241 4242 operand eCXRegI(xRegI reg) %{ 4243 constraint(ALLOC_IN_RC(ecx_reg)); 4244 match(reg); 4245 match(rRegI); 4246 4247 format %{ "ECX" %} 4248 interface(REG_INTER); 4249 %} 4250 4251 operand eDXRegI(xRegI reg) %{ 4252 constraint(ALLOC_IN_RC(edx_reg)); 4253 match(reg); 4254 match(rRegI); 4255 4256 format %{ "EDX" %} 4257 interface(REG_INTER); 4258 %} 4259 4260 operand eDIRegI(xRegI reg) %{ 4261 constraint(ALLOC_IN_RC(edi_reg)); 4262 match(reg); 4263 match(rRegI); 4264 4265 format %{ "EDI" %} 4266 interface(REG_INTER); 4267 %} 4268 4269 operand naxRegI() %{ 4270 constraint(ALLOC_IN_RC(nax_reg)); 4271 match(RegI); 4272 match(eCXRegI); 4273 match(eDXRegI); 4274 match(eSIRegI); 4275 match(eDIRegI); 4276 4277 format %{ %} 4278 interface(REG_INTER); 4279 %} 4280 4281 operand nadxRegI() %{ 4282 constraint(ALLOC_IN_RC(nadx_reg)); 4283 match(RegI); 4284 match(eBXRegI); 4285 match(eCXRegI); 4286 match(eSIRegI); 4287 match(eDIRegI); 4288 4289 format %{ %} 4290 interface(REG_INTER); 4291 %} 4292 4293 operand ncxRegI() %{ 4294 constraint(ALLOC_IN_RC(ncx_reg)); 4295 match(RegI); 4296 match(eAXRegI); 4297 match(eDXRegI); 4298 match(eSIRegI); 4299 match(eDIRegI); 4300 4301 format %{ %} 4302 interface(REG_INTER); 4303 %} 4304 4305 // // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 4306 // // 4307 operand eSIRegI(xRegI reg) %{ 4308 constraint(ALLOC_IN_RC(esi_reg)); 4309 match(reg); 4310 match(rRegI); 4311 4312 format %{ "ESI" %} 4313 interface(REG_INTER); 4314 %} 4315 4316 // Pointer Register 4317 operand anyRegP() %{ 4318 constraint(ALLOC_IN_RC(any_reg)); 4319 match(RegP); 4320 match(eAXRegP); 4321 match(eBXRegP); 4322 match(eCXRegP); 4323 match(eDIRegP); 4324 match(eRegP); 4325 4326 format %{ %} 4327 interface(REG_INTER); 4328 %} 4329 4330 operand eRegP() %{ 4331 constraint(ALLOC_IN_RC(int_reg)); 4332 match(RegP); 4333 match(eAXRegP); 4334 match(eBXRegP); 4335 match(eCXRegP); 4336 match(eDIRegP); 4337 4338 format %{ %} 4339 interface(REG_INTER); 4340 %} 4341 4342 // On windows95, EBP is not safe to use for implicit null tests. 4343 operand eRegP_no_EBP() %{ 4344 constraint(ALLOC_IN_RC(int_reg_no_rbp)); 4345 match(RegP); 4346 match(eAXRegP); 4347 match(eBXRegP); 4348 match(eCXRegP); 4349 match(eDIRegP); 4350 4351 op_cost(100); 4352 format %{ %} 4353 interface(REG_INTER); 4354 %} 4355 4356 operand naxRegP() %{ 4357 constraint(ALLOC_IN_RC(nax_reg)); 4358 match(RegP); 4359 match(eBXRegP); 4360 match(eDXRegP); 4361 match(eCXRegP); 4362 match(eSIRegP); 4363 match(eDIRegP); 4364 4365 format %{ %} 4366 interface(REG_INTER); 4367 %} 4368 4369 operand nabxRegP() %{ 4370 constraint(ALLOC_IN_RC(nabx_reg)); 4371 match(RegP); 4372 match(eCXRegP); 4373 match(eDXRegP); 4374 match(eSIRegP); 4375 match(eDIRegP); 4376 4377 format %{ %} 4378 interface(REG_INTER); 4379 %} 4380 4381 operand pRegP() %{ 4382 constraint(ALLOC_IN_RC(p_reg)); 4383 match(RegP); 4384 match(eBXRegP); 4385 match(eDXRegP); 4386 match(eSIRegP); 4387 match(eDIRegP); 4388 4389 format %{ %} 4390 interface(REG_INTER); 4391 %} 4392 4393 // Special Registers 4394 // Return a pointer value 4395 operand eAXRegP(eRegP reg) %{ 4396 constraint(ALLOC_IN_RC(eax_reg)); 4397 match(reg); 4398 format %{ "EAX" %} 4399 interface(REG_INTER); 4400 %} 4401 4402 // Used in AtomicAdd 4403 operand eBXRegP(eRegP reg) %{ 4404 constraint(ALLOC_IN_RC(ebx_reg)); 4405 match(reg); 4406 format %{ "EBX" %} 4407 interface(REG_INTER); 4408 %} 4409 4410 // Tail-call (interprocedural jump) to interpreter 4411 operand eCXRegP(eRegP reg) %{ 4412 constraint(ALLOC_IN_RC(ecx_reg)); 4413 match(reg); 4414 format %{ "ECX" %} 4415 interface(REG_INTER); 4416 %} 4417 4418 operand eSIRegP(eRegP reg) %{ 4419 constraint(ALLOC_IN_RC(esi_reg)); 4420 match(reg); 4421 format %{ "ESI" %} 4422 interface(REG_INTER); 4423 %} 4424 4425 // Used in rep stosw 4426 operand eDIRegP(eRegP reg) %{ 4427 constraint(ALLOC_IN_RC(edi_reg)); 4428 match(reg); 4429 format %{ "EDI" %} 4430 interface(REG_INTER); 4431 %} 4432 4433 operand eBPRegP() %{ 4434 constraint(ALLOC_IN_RC(ebp_reg)); 4435 match(RegP); 4436 format %{ "EBP" %} 4437 interface(REG_INTER); 4438 %} 4439 4440 operand eRegL() %{ 4441 constraint(ALLOC_IN_RC(long_reg)); 4442 match(RegL); 4443 match(eADXRegL); 4444 4445 format %{ %} 4446 interface(REG_INTER); 4447 %} 4448 4449 operand eADXRegL( eRegL reg ) %{ 4450 constraint(ALLOC_IN_RC(eadx_reg)); 4451 match(reg); 4452 4453 format %{ "EDX:EAX" %} 4454 interface(REG_INTER); 4455 %} 4456 4457 operand eBCXRegL( eRegL reg ) %{ 4458 constraint(ALLOC_IN_RC(ebcx_reg)); 4459 match(reg); 4460 4461 format %{ "EBX:ECX" %} 4462 interface(REG_INTER); 4463 %} 4464 4465 // Special case for integer high multiply 4466 operand eADXRegL_low_only() %{ 4467 constraint(ALLOC_IN_RC(eadx_reg)); 4468 match(RegL); 4469 4470 format %{ "EAX" %} 4471 interface(REG_INTER); 4472 %} 4473 4474 // Flags register, used as output of compare instructions 4475 operand eFlagsReg() %{ 4476 constraint(ALLOC_IN_RC(int_flags)); 4477 match(RegFlags); 4478 4479 format %{ "EFLAGS" %} 4480 interface(REG_INTER); 4481 %} 4482 4483 // Flags register, used as output of FLOATING POINT compare instructions 4484 operand eFlagsRegU() %{ 4485 constraint(ALLOC_IN_RC(int_flags)); 4486 match(RegFlags); 4487 4488 format %{ "EFLAGS_U" %} 4489 interface(REG_INTER); 4490 %} 4491 4492 operand eFlagsRegUCF() %{ 4493 constraint(ALLOC_IN_RC(int_flags)); 4494 match(RegFlags); 4495 predicate(false); 4496 4497 format %{ "EFLAGS_U_CF" %} 4498 interface(REG_INTER); 4499 %} 4500 4501 // Condition Code Register used by long compare 4502 operand flagsReg_long_LTGE() %{ 4503 constraint(ALLOC_IN_RC(int_flags)); 4504 match(RegFlags); 4505 format %{ "FLAGS_LTGE" %} 4506 interface(REG_INTER); 4507 %} 4508 operand flagsReg_long_EQNE() %{ 4509 constraint(ALLOC_IN_RC(int_flags)); 4510 match(RegFlags); 4511 format %{ "FLAGS_EQNE" %} 4512 interface(REG_INTER); 4513 %} 4514 operand flagsReg_long_LEGT() %{ 4515 constraint(ALLOC_IN_RC(int_flags)); 4516 match(RegFlags); 4517 format %{ "FLAGS_LEGT" %} 4518 interface(REG_INTER); 4519 %} 4520 4521 // Float register operands 4522 operand regDPR() %{ 4523 predicate( UseSSE < 2 ); 4524 constraint(ALLOC_IN_RC(fp_dbl_reg)); 4525 match(RegD); 4526 match(regDPR1); 4527 match(regDPR2); 4528 format %{ %} 4529 interface(REG_INTER); 4530 %} 4531 4532 operand regDPR1(regDPR reg) %{ 4533 predicate( UseSSE < 2 ); 4534 constraint(ALLOC_IN_RC(fp_dbl_reg0)); 4535 match(reg); 4536 format %{ "FPR1" %} 4537 interface(REG_INTER); 4538 %} 4539 4540 operand regDPR2(regDPR reg) %{ 4541 predicate( UseSSE < 2 ); 4542 constraint(ALLOC_IN_RC(fp_dbl_reg1)); 4543 match(reg); 4544 format %{ "FPR2" %} 4545 interface(REG_INTER); 4546 %} 4547 4548 operand regnotDPR1(regDPR reg) %{ 4549 predicate( UseSSE < 2 ); 4550 constraint(ALLOC_IN_RC(fp_dbl_notreg0)); 4551 match(reg); 4552 format %{ %} 4553 interface(REG_INTER); 4554 %} 4555 4556 // Float register operands 4557 operand regFPR() %{ 4558 predicate( UseSSE < 2 ); 4559 constraint(ALLOC_IN_RC(fp_flt_reg)); 4560 match(RegF); 4561 match(regFPR1); 4562 format %{ %} 4563 interface(REG_INTER); 4564 %} 4565 4566 // Float register operands 4567 operand regFPR1(regFPR reg) %{ 4568 predicate( UseSSE < 2 ); 4569 constraint(ALLOC_IN_RC(fp_flt_reg0)); 4570 match(reg); 4571 format %{ "FPR1" %} 4572 interface(REG_INTER); 4573 %} 4574 4575 // XMM Float register operands 4576 operand regF() %{ 4577 predicate( UseSSE>=1 ); 4578 constraint(ALLOC_IN_RC(float_reg)); 4579 match(RegF); 4580 format %{ %} 4581 interface(REG_INTER); 4582 %} 4583 4584 // XMM Double register operands 4585 operand regD() %{ 4586 predicate( UseSSE>=2 ); 4587 constraint(ALLOC_IN_RC(double_reg)); 4588 match(RegD); 4589 format %{ %} 4590 interface(REG_INTER); 4591 %} 4592 4593 4594 //----------Memory Operands---------------------------------------------------- 4595 // Direct Memory Operand 4596 operand direct(immP addr) %{ 4597 match(addr); 4598 4599 format %{ "[$addr]" %} 4600 interface(MEMORY_INTER) %{ 4601 base(0xFFFFFFFF); 4602 index(0x4); 4603 scale(0x0); 4604 disp($addr); 4605 %} 4606 %} 4607 4608 // Indirect Memory Operand 4609 operand indirect(eRegP reg) %{ 4610 constraint(ALLOC_IN_RC(int_reg)); 4611 match(reg); 4612 4613 format %{ "[$reg]" %} 4614 interface(MEMORY_INTER) %{ 4615 base($reg); 4616 index(0x4); 4617 scale(0x0); 4618 disp(0x0); 4619 %} 4620 %} 4621 4622 // Indirect Memory Plus Short Offset Operand 4623 operand indOffset8(eRegP reg, immI8 off) %{ 4624 match(AddP reg off); 4625 4626 format %{ "[$reg + $off]" %} 4627 interface(MEMORY_INTER) %{ 4628 base($reg); 4629 index(0x4); 4630 scale(0x0); 4631 disp($off); 4632 %} 4633 %} 4634 4635 // Indirect Memory Plus Long Offset Operand 4636 operand indOffset32(eRegP reg, immI off) %{ 4637 match(AddP reg off); 4638 4639 format %{ "[$reg + $off]" %} 4640 interface(MEMORY_INTER) %{ 4641 base($reg); 4642 index(0x4); 4643 scale(0x0); 4644 disp($off); 4645 %} 4646 %} 4647 4648 // Indirect Memory Plus Long Offset Operand 4649 operand indOffset32X(rRegI reg, immP off) %{ 4650 match(AddP off reg); 4651 4652 format %{ "[$reg + $off]" %} 4653 interface(MEMORY_INTER) %{ 4654 base($reg); 4655 index(0x4); 4656 scale(0x0); 4657 disp($off); 4658 %} 4659 %} 4660 4661 // Indirect Memory Plus Index Register Plus Offset Operand 4662 operand indIndexOffset(eRegP reg, rRegI ireg, immI off) %{ 4663 match(AddP (AddP reg ireg) off); 4664 4665 op_cost(10); 4666 format %{"[$reg + $off + $ireg]" %} 4667 interface(MEMORY_INTER) %{ 4668 base($reg); 4669 index($ireg); 4670 scale(0x0); 4671 disp($off); 4672 %} 4673 %} 4674 4675 // Indirect Memory Plus Index Register Plus Offset Operand 4676 operand indIndex(eRegP reg, rRegI ireg) %{ 4677 match(AddP reg ireg); 4678 4679 op_cost(10); 4680 format %{"[$reg + $ireg]" %} 4681 interface(MEMORY_INTER) %{ 4682 base($reg); 4683 index($ireg); 4684 scale(0x0); 4685 disp(0x0); 4686 %} 4687 %} 4688 4689 // // ------------------------------------------------------------------------- 4690 // // 486 architecture doesn't support "scale * index + offset" with out a base 4691 // // ------------------------------------------------------------------------- 4692 // // Scaled Memory Operands 4693 // // Indirect Memory Times Scale Plus Offset Operand 4694 // operand indScaleOffset(immP off, rRegI ireg, immI2 scale) %{ 4695 // match(AddP off (LShiftI ireg scale)); 4696 // 4697 // op_cost(10); 4698 // format %{"[$off + $ireg << $scale]" %} 4699 // interface(MEMORY_INTER) %{ 4700 // base(0x4); 4701 // index($ireg); 4702 // scale($scale); 4703 // disp($off); 4704 // %} 4705 // %} 4706 4707 // Indirect Memory Times Scale Plus Index Register 4708 operand indIndexScale(eRegP reg, rRegI ireg, immI2 scale) %{ 4709 match(AddP reg (LShiftI ireg scale)); 4710 4711 op_cost(10); 4712 format %{"[$reg + $ireg << $scale]" %} 4713 interface(MEMORY_INTER) %{ 4714 base($reg); 4715 index($ireg); 4716 scale($scale); 4717 disp(0x0); 4718 %} 4719 %} 4720 4721 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4722 operand indIndexScaleOffset(eRegP reg, immI off, rRegI ireg, immI2 scale) %{ 4723 match(AddP (AddP reg (LShiftI ireg scale)) off); 4724 4725 op_cost(10); 4726 format %{"[$reg + $off + $ireg << $scale]" %} 4727 interface(MEMORY_INTER) %{ 4728 base($reg); 4729 index($ireg); 4730 scale($scale); 4731 disp($off); 4732 %} 4733 %} 4734 4735 //----------Load Long Memory Operands------------------------------------------ 4736 // The load-long idiom will use it's address expression again after loading 4737 // the first word of the long. If the load-long destination overlaps with 4738 // registers used in the addressing expression, the 2nd half will be loaded 4739 // from a clobbered address. Fix this by requiring that load-long use 4740 // address registers that do not overlap with the load-long target. 4741 4742 // load-long support 4743 operand load_long_RegP() %{ 4744 constraint(ALLOC_IN_RC(esi_reg)); 4745 match(RegP); 4746 match(eSIRegP); 4747 op_cost(100); 4748 format %{ %} 4749 interface(REG_INTER); 4750 %} 4751 4752 // Indirect Memory Operand Long 4753 operand load_long_indirect(load_long_RegP reg) %{ 4754 constraint(ALLOC_IN_RC(esi_reg)); 4755 match(reg); 4756 4757 format %{ "[$reg]" %} 4758 interface(MEMORY_INTER) %{ 4759 base($reg); 4760 index(0x4); 4761 scale(0x0); 4762 disp(0x0); 4763 %} 4764 %} 4765 4766 // Indirect Memory Plus Long Offset Operand 4767 operand load_long_indOffset32(load_long_RegP reg, immI off) %{ 4768 match(AddP reg off); 4769 4770 format %{ "[$reg + $off]" %} 4771 interface(MEMORY_INTER) %{ 4772 base($reg); 4773 index(0x4); 4774 scale(0x0); 4775 disp($off); 4776 %} 4777 %} 4778 4779 opclass load_long_memory(load_long_indirect, load_long_indOffset32); 4780 4781 4782 //----------Special Memory Operands-------------------------------------------- 4783 // Stack Slot Operand - This operand is used for loading and storing temporary 4784 // values on the stack where a match requires a value to 4785 // flow through memory. 4786 operand stackSlotP(sRegP reg) %{ 4787 constraint(ALLOC_IN_RC(stack_slots)); 4788 // No match rule because this operand is only generated in matching 4789 format %{ "[$reg]" %} 4790 interface(MEMORY_INTER) %{ 4791 base(0x4); // ESP 4792 index(0x4); // No Index 4793 scale(0x0); // No Scale 4794 disp($reg); // Stack Offset 4795 %} 4796 %} 4797 4798 operand stackSlotI(sRegI reg) %{ 4799 constraint(ALLOC_IN_RC(stack_slots)); 4800 // No match rule because this operand is only generated in matching 4801 format %{ "[$reg]" %} 4802 interface(MEMORY_INTER) %{ 4803 base(0x4); // ESP 4804 index(0x4); // No Index 4805 scale(0x0); // No Scale 4806 disp($reg); // Stack Offset 4807 %} 4808 %} 4809 4810 operand stackSlotF(sRegF reg) %{ 4811 constraint(ALLOC_IN_RC(stack_slots)); 4812 // No match rule because this operand is only generated in matching 4813 format %{ "[$reg]" %} 4814 interface(MEMORY_INTER) %{ 4815 base(0x4); // ESP 4816 index(0x4); // No Index 4817 scale(0x0); // No Scale 4818 disp($reg); // Stack Offset 4819 %} 4820 %} 4821 4822 operand stackSlotD(sRegD reg) %{ 4823 constraint(ALLOC_IN_RC(stack_slots)); 4824 // No match rule because this operand is only generated in matching 4825 format %{ "[$reg]" %} 4826 interface(MEMORY_INTER) %{ 4827 base(0x4); // ESP 4828 index(0x4); // No Index 4829 scale(0x0); // No Scale 4830 disp($reg); // Stack Offset 4831 %} 4832 %} 4833 4834 operand stackSlotL(sRegL reg) %{ 4835 constraint(ALLOC_IN_RC(stack_slots)); 4836 // No match rule because this operand is only generated in matching 4837 format %{ "[$reg]" %} 4838 interface(MEMORY_INTER) %{ 4839 base(0x4); // ESP 4840 index(0x4); // No Index 4841 scale(0x0); // No Scale 4842 disp($reg); // Stack Offset 4843 %} 4844 %} 4845 4846 //----------Memory Operands - Win95 Implicit Null Variants---------------- 4847 // Indirect Memory Operand 4848 operand indirect_win95_safe(eRegP_no_EBP reg) 4849 %{ 4850 constraint(ALLOC_IN_RC(int_reg)); 4851 match(reg); 4852 4853 op_cost(100); 4854 format %{ "[$reg]" %} 4855 interface(MEMORY_INTER) %{ 4856 base($reg); 4857 index(0x4); 4858 scale(0x0); 4859 disp(0x0); 4860 %} 4861 %} 4862 4863 // Indirect Memory Plus Short Offset Operand 4864 operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) 4865 %{ 4866 match(AddP reg off); 4867 4868 op_cost(100); 4869 format %{ "[$reg + $off]" %} 4870 interface(MEMORY_INTER) %{ 4871 base($reg); 4872 index(0x4); 4873 scale(0x0); 4874 disp($off); 4875 %} 4876 %} 4877 4878 // Indirect Memory Plus Long Offset Operand 4879 operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) 4880 %{ 4881 match(AddP reg off); 4882 4883 op_cost(100); 4884 format %{ "[$reg + $off]" %} 4885 interface(MEMORY_INTER) %{ 4886 base($reg); 4887 index(0x4); 4888 scale(0x0); 4889 disp($off); 4890 %} 4891 %} 4892 4893 // Indirect Memory Plus Index Register Plus Offset Operand 4894 operand indIndexOffset_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI off) 4895 %{ 4896 match(AddP (AddP reg ireg) off); 4897 4898 op_cost(100); 4899 format %{"[$reg + $off + $ireg]" %} 4900 interface(MEMORY_INTER) %{ 4901 base($reg); 4902 index($ireg); 4903 scale(0x0); 4904 disp($off); 4905 %} 4906 %} 4907 4908 // Indirect Memory Times Scale Plus Index Register 4909 operand indIndexScale_win95_safe(eRegP_no_EBP reg, rRegI ireg, immI2 scale) 4910 %{ 4911 match(AddP reg (LShiftI ireg scale)); 4912 4913 op_cost(100); 4914 format %{"[$reg + $ireg << $scale]" %} 4915 interface(MEMORY_INTER) %{ 4916 base($reg); 4917 index($ireg); 4918 scale($scale); 4919 disp(0x0); 4920 %} 4921 %} 4922 4923 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand 4924 operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, rRegI ireg, immI2 scale) 4925 %{ 4926 match(AddP (AddP reg (LShiftI ireg scale)) off); 4927 4928 op_cost(100); 4929 format %{"[$reg + $off + $ireg << $scale]" %} 4930 interface(MEMORY_INTER) %{ 4931 base($reg); 4932 index($ireg); 4933 scale($scale); 4934 disp($off); 4935 %} 4936 %} 4937 4938 //----------Conditional Branch Operands---------------------------------------- 4939 // Comparison Op - This is the operation of the comparison, and is limited to 4940 // the following set of codes: 4941 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4942 // 4943 // Other attributes of the comparison, such as unsignedness, are specified 4944 // by the comparison instruction that sets a condition code flags register. 4945 // That result is represented by a flags operand whose subtype is appropriate 4946 // to the unsignedness (etc.) of the comparison. 4947 // 4948 // Later, the instruction which matches both the Comparison Op (a Bool) and 4949 // the flags (produced by the Cmp) specifies the coding of the comparison op 4950 // by matching a specific subtype of Bool operand below, such as cmpOpU. 4951 4952 // Comparision Code 4953 operand cmpOp() %{ 4954 match(Bool); 4955 4956 format %{ "" %} 4957 interface(COND_INTER) %{ 4958 equal(0x4, "e"); 4959 not_equal(0x5, "ne"); 4960 less(0xC, "l"); 4961 greater_equal(0xD, "ge"); 4962 less_equal(0xE, "le"); 4963 greater(0xF, "g"); 4964 %} 4965 %} 4966 4967 // Comparison Code, unsigned compare. Used by FP also, with 4968 // C2 (unordered) turned into GT or LT already. The other bits 4969 // C0 and C3 are turned into Carry & Zero flags. 4970 operand cmpOpU() %{ 4971 match(Bool); 4972 4973 format %{ "" %} 4974 interface(COND_INTER) %{ 4975 equal(0x4, "e"); 4976 not_equal(0x5, "ne"); 4977 less(0x2, "b"); 4978 greater_equal(0x3, "nb"); 4979 less_equal(0x6, "be"); 4980 greater(0x7, "nbe"); 4981 %} 4982 %} 4983 4984 // Floating comparisons that don't require any fixup for the unordered case 4985 operand cmpOpUCF() %{ 4986 match(Bool); 4987 predicate(n->as_Bool()->_test._test == BoolTest::lt || 4988 n->as_Bool()->_test._test == BoolTest::ge || 4989 n->as_Bool()->_test._test == BoolTest::le || 4990 n->as_Bool()->_test._test == BoolTest::gt); 4991 format %{ "" %} 4992 interface(COND_INTER) %{ 4993 equal(0x4, "e"); 4994 not_equal(0x5, "ne"); 4995 less(0x2, "b"); 4996 greater_equal(0x3, "nb"); 4997 less_equal(0x6, "be"); 4998 greater(0x7, "nbe"); 4999 %} 5000 %} 5001 5002 5003 // Floating comparisons that can be fixed up with extra conditional jumps 5004 operand cmpOpUCF2() %{ 5005 match(Bool); 5006 predicate(n->as_Bool()->_test._test == BoolTest::ne || 5007 n->as_Bool()->_test._test == BoolTest::eq); 5008 format %{ "" %} 5009 interface(COND_INTER) %{ 5010 equal(0x4, "e"); 5011 not_equal(0x5, "ne"); 5012 less(0x2, "b"); 5013 greater_equal(0x3, "nb"); 5014 less_equal(0x6, "be"); 5015 greater(0x7, "nbe"); 5016 %} 5017 %} 5018 5019 // Comparison Code for FP conditional move 5020 operand cmpOp_fcmov() %{ 5021 match(Bool); 5022 5023 format %{ "" %} 5024 interface(COND_INTER) %{ 5025 equal (0x0C8); 5026 not_equal (0x1C8); 5027 less (0x0C0); 5028 greater_equal(0x1C0); 5029 less_equal (0x0D0); 5030 greater (0x1D0); 5031 %} 5032 %} 5033 5034 // Comparision Code used in long compares 5035 operand cmpOp_commute() %{ 5036 match(Bool); 5037 5038 format %{ "" %} 5039 interface(COND_INTER) %{ 5040 equal(0x4, "e"); 5041 not_equal(0x5, "ne"); 5042 less(0xF, "g"); 5043 greater_equal(0xE, "le"); 5044 less_equal(0xD, "ge"); 5045 greater(0xC, "l"); 5046 %} 5047 %} 5048 5049 //----------OPERAND CLASSES---------------------------------------------------- 5050 // Operand Classes are groups of operands that are used as to simplify 5051 // instruction definitions by not requiring the AD writer to specify separate 5052 // instructions for every form of operand when the instruction accepts 5053 // multiple operand types with the same basic encoding and format. The classic 5054 // case of this is memory operands. 5055 5056 opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 5057 indIndex, indIndexScale, indIndexScaleOffset); 5058 5059 // Long memory operations are encoded in 2 instructions and a +4 offset. 5060 // This means some kind of offset is always required and you cannot use 5061 // an oop as the offset (done when working on static globals). 5062 opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, 5063 indIndex, indIndexScale, indIndexScaleOffset); 5064 5065 5066 //----------PIPELINE----------------------------------------------------------- 5067 // Rules which define the behavior of the target architectures pipeline. 5068 pipeline %{ 5069 5070 //----------ATTRIBUTES--------------------------------------------------------- 5071 attributes %{ 5072 variable_size_instructions; // Fixed size instructions 5073 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 5074 instruction_unit_size = 1; // An instruction is 1 bytes long 5075 instruction_fetch_unit_size = 16; // The processor fetches one line 5076 instruction_fetch_units = 1; // of 16 bytes 5077 5078 // List of nop instructions 5079 nops( MachNop ); 5080 %} 5081 5082 //----------RESOURCES---------------------------------------------------------- 5083 // Resources are the functional units available to the machine 5084 5085 // Generic P2/P3 pipeline 5086 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of 5087 // 3 instructions decoded per cycle. 5088 // 2 load/store ops per cycle, 1 branch, 1 FPU, 5089 // 2 ALU op, only ALU0 handles mul/div instructions. 5090 resources( D0, D1, D2, DECODE = D0 | D1 | D2, 5091 MS0, MS1, MEM = MS0 | MS1, 5092 BR, FPU, 5093 ALU0, ALU1, ALU = ALU0 | ALU1 ); 5094 5095 //----------PIPELINE DESCRIPTION----------------------------------------------- 5096 // Pipeline Description specifies the stages in the machine's pipeline 5097 5098 // Generic P2/P3 pipeline 5099 pipe_desc(S0, S1, S2, S3, S4, S5); 5100 5101 //----------PIPELINE CLASSES--------------------------------------------------- 5102 // Pipeline Classes describe the stages in which input and output are 5103 // referenced by the hardware pipeline. 5104 5105 // Naming convention: ialu or fpu 5106 // Then: _reg 5107 // Then: _reg if there is a 2nd register 5108 // Then: _long if it's a pair of instructions implementing a long 5109 // Then: _fat if it requires the big decoder 5110 // Or: _mem if it requires the big decoder and a memory unit. 5111 5112 // Integer ALU reg operation 5113 pipe_class ialu_reg(rRegI dst) %{ 5114 single_instruction; 5115 dst : S4(write); 5116 dst : S3(read); 5117 DECODE : S0; // any decoder 5118 ALU : S3; // any alu 5119 %} 5120 5121 // Long ALU reg operation 5122 pipe_class ialu_reg_long(eRegL dst) %{ 5123 instruction_count(2); 5124 dst : S4(write); 5125 dst : S3(read); 5126 DECODE : S0(2); // any 2 decoders 5127 ALU : S3(2); // both alus 5128 %} 5129 5130 // Integer ALU reg operation using big decoder 5131 pipe_class ialu_reg_fat(rRegI dst) %{ 5132 single_instruction; 5133 dst : S4(write); 5134 dst : S3(read); 5135 D0 : S0; // big decoder only 5136 ALU : S3; // any alu 5137 %} 5138 5139 // Long ALU reg operation using big decoder 5140 pipe_class ialu_reg_long_fat(eRegL dst) %{ 5141 instruction_count(2); 5142 dst : S4(write); 5143 dst : S3(read); 5144 D0 : S0(2); // big decoder only; twice 5145 ALU : S3(2); // any 2 alus 5146 %} 5147 5148 // Integer ALU reg-reg operation 5149 pipe_class ialu_reg_reg(rRegI dst, rRegI src) %{ 5150 single_instruction; 5151 dst : S4(write); 5152 src : S3(read); 5153 DECODE : S0; // any decoder 5154 ALU : S3; // any alu 5155 %} 5156 5157 // Long ALU reg-reg operation 5158 pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ 5159 instruction_count(2); 5160 dst : S4(write); 5161 src : S3(read); 5162 DECODE : S0(2); // any 2 decoders 5163 ALU : S3(2); // both alus 5164 %} 5165 5166 // Integer ALU reg-reg operation 5167 pipe_class ialu_reg_reg_fat(rRegI dst, memory src) %{ 5168 single_instruction; 5169 dst : S4(write); 5170 src : S3(read); 5171 D0 : S0; // big decoder only 5172 ALU : S3; // any alu 5173 %} 5174 5175 // Long ALU reg-reg operation 5176 pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ 5177 instruction_count(2); 5178 dst : S4(write); 5179 src : S3(read); 5180 D0 : S0(2); // big decoder only; twice 5181 ALU : S3(2); // both alus 5182 %} 5183 5184 // Integer ALU reg-mem operation 5185 pipe_class ialu_reg_mem(rRegI dst, memory mem) %{ 5186 single_instruction; 5187 dst : S5(write); 5188 mem : S3(read); 5189 D0 : S0; // big decoder only 5190 ALU : S4; // any alu 5191 MEM : S3; // any mem 5192 %} 5193 5194 // Long ALU reg-mem operation 5195 pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ 5196 instruction_count(2); 5197 dst : S5(write); 5198 mem : S3(read); 5199 D0 : S0(2); // big decoder only; twice 5200 ALU : S4(2); // any 2 alus 5201 MEM : S3(2); // both mems 5202 %} 5203 5204 // Integer mem operation (prefetch) 5205 pipe_class ialu_mem(memory mem) 5206 %{ 5207 single_instruction; 5208 mem : S3(read); 5209 D0 : S0; // big decoder only 5210 MEM : S3; // any mem 5211 %} 5212 5213 // Integer Store to Memory 5214 pipe_class ialu_mem_reg(memory mem, rRegI src) %{ 5215 single_instruction; 5216 mem : S3(read); 5217 src : S5(read); 5218 D0 : S0; // big decoder only 5219 ALU : S4; // any alu 5220 MEM : S3; 5221 %} 5222 5223 // Long Store to Memory 5224 pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ 5225 instruction_count(2); 5226 mem : S3(read); 5227 src : S5(read); 5228 D0 : S0(2); // big decoder only; twice 5229 ALU : S4(2); // any 2 alus 5230 MEM : S3(2); // Both mems 5231 %} 5232 5233 // Integer Store to Memory 5234 pipe_class ialu_mem_imm(memory mem) %{ 5235 single_instruction; 5236 mem : S3(read); 5237 D0 : S0; // big decoder only 5238 ALU : S4; // any alu 5239 MEM : S3; 5240 %} 5241 5242 // Integer ALU0 reg-reg operation 5243 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src) %{ 5244 single_instruction; 5245 dst : S4(write); 5246 src : S3(read); 5247 D0 : S0; // Big decoder only 5248 ALU0 : S3; // only alu0 5249 %} 5250 5251 // Integer ALU0 reg-mem operation 5252 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem) %{ 5253 single_instruction; 5254 dst : S5(write); 5255 mem : S3(read); 5256 D0 : S0; // big decoder only 5257 ALU0 : S4; // ALU0 only 5258 MEM : S3; // any mem 5259 %} 5260 5261 // Integer ALU reg-reg operation 5262 pipe_class ialu_cr_reg_reg(eFlagsReg cr, rRegI src1, rRegI src2) %{ 5263 single_instruction; 5264 cr : S4(write); 5265 src1 : S3(read); 5266 src2 : S3(read); 5267 DECODE : S0; // any decoder 5268 ALU : S3; // any alu 5269 %} 5270 5271 // Integer ALU reg-imm operation 5272 pipe_class ialu_cr_reg_imm(eFlagsReg cr, rRegI src1) %{ 5273 single_instruction; 5274 cr : S4(write); 5275 src1 : S3(read); 5276 DECODE : S0; // any decoder 5277 ALU : S3; // any alu 5278 %} 5279 5280 // Integer ALU reg-mem operation 5281 pipe_class ialu_cr_reg_mem(eFlagsReg cr, rRegI src1, memory src2) %{ 5282 single_instruction; 5283 cr : S4(write); 5284 src1 : S3(read); 5285 src2 : S3(read); 5286 D0 : S0; // big decoder only 5287 ALU : S4; // any alu 5288 MEM : S3; 5289 %} 5290 5291 // Conditional move reg-reg 5292 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y ) %{ 5293 instruction_count(4); 5294 y : S4(read); 5295 q : S3(read); 5296 p : S3(read); 5297 DECODE : S0(4); // any decoder 5298 %} 5299 5300 // Conditional move reg-reg 5301 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, eFlagsReg cr ) %{ 5302 single_instruction; 5303 dst : S4(write); 5304 src : S3(read); 5305 cr : S3(read); 5306 DECODE : S0; // any decoder 5307 %} 5308 5309 // Conditional move reg-mem 5310 pipe_class pipe_cmov_mem( eFlagsReg cr, rRegI dst, memory src) %{ 5311 single_instruction; 5312 dst : S4(write); 5313 src : S3(read); 5314 cr : S3(read); 5315 DECODE : S0; // any decoder 5316 MEM : S3; 5317 %} 5318 5319 // Conditional move reg-reg long 5320 pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ 5321 single_instruction; 5322 dst : S4(write); 5323 src : S3(read); 5324 cr : S3(read); 5325 DECODE : S0(2); // any 2 decoders 5326 %} 5327 5328 // Conditional move double reg-reg 5329 pipe_class pipe_cmovDPR_reg( eFlagsReg cr, regDPR1 dst, regDPR src) %{ 5330 single_instruction; 5331 dst : S4(write); 5332 src : S3(read); 5333 cr : S3(read); 5334 DECODE : S0; // any decoder 5335 %} 5336 5337 // Float reg-reg operation 5338 pipe_class fpu_reg(regDPR dst) %{ 5339 instruction_count(2); 5340 dst : S3(read); 5341 DECODE : S0(2); // any 2 decoders 5342 FPU : S3; 5343 %} 5344 5345 // Float reg-reg operation 5346 pipe_class fpu_reg_reg(regDPR dst, regDPR src) %{ 5347 instruction_count(2); 5348 dst : S4(write); 5349 src : S3(read); 5350 DECODE : S0(2); // any 2 decoders 5351 FPU : S3; 5352 %} 5353 5354 // Float reg-reg operation 5355 pipe_class fpu_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2) %{ 5356 instruction_count(3); 5357 dst : S4(write); 5358 src1 : S3(read); 5359 src2 : S3(read); 5360 DECODE : S0(3); // any 3 decoders 5361 FPU : S3(2); 5362 %} 5363 5364 // Float reg-reg operation 5365 pipe_class fpu_reg_reg_reg_reg(regDPR dst, regDPR src1, regDPR src2, regDPR src3) %{ 5366 instruction_count(4); 5367 dst : S4(write); 5368 src1 : S3(read); 5369 src2 : S3(read); 5370 src3 : S3(read); 5371 DECODE : S0(4); // any 3 decoders 5372 FPU : S3(2); 5373 %} 5374 5375 // Float reg-reg operation 5376 pipe_class fpu_reg_mem_reg_reg(regDPR dst, memory src1, regDPR src2, regDPR src3) %{ 5377 instruction_count(4); 5378 dst : S4(write); 5379 src1 : S3(read); 5380 src2 : S3(read); 5381 src3 : S3(read); 5382 DECODE : S1(3); // any 3 decoders 5383 D0 : S0; // Big decoder only 5384 FPU : S3(2); 5385 MEM : S3; 5386 %} 5387 5388 // Float reg-mem operation 5389 pipe_class fpu_reg_mem(regDPR dst, memory mem) %{ 5390 instruction_count(2); 5391 dst : S5(write); 5392 mem : S3(read); 5393 D0 : S0; // big decoder only 5394 DECODE : S1; // any decoder for FPU POP 5395 FPU : S4; 5396 MEM : S3; // any mem 5397 %} 5398 5399 // Float reg-mem operation 5400 pipe_class fpu_reg_reg_mem(regDPR dst, regDPR src1, memory mem) %{ 5401 instruction_count(3); 5402 dst : S5(write); 5403 src1 : S3(read); 5404 mem : S3(read); 5405 D0 : S0; // big decoder only 5406 DECODE : S1(2); // any decoder for FPU POP 5407 FPU : S4; 5408 MEM : S3; // any mem 5409 %} 5410 5411 // Float mem-reg operation 5412 pipe_class fpu_mem_reg(memory mem, regDPR src) %{ 5413 instruction_count(2); 5414 src : S5(read); 5415 mem : S3(read); 5416 DECODE : S0; // any decoder for FPU PUSH 5417 D0 : S1; // big decoder only 5418 FPU : S4; 5419 MEM : S3; // any mem 5420 %} 5421 5422 pipe_class fpu_mem_reg_reg(memory mem, regDPR src1, regDPR src2) %{ 5423 instruction_count(3); 5424 src1 : S3(read); 5425 src2 : S3(read); 5426 mem : S3(read); 5427 DECODE : S0(2); // any decoder for FPU PUSH 5428 D0 : S1; // big decoder only 5429 FPU : S4; 5430 MEM : S3; // any mem 5431 %} 5432 5433 pipe_class fpu_mem_reg_mem(memory mem, regDPR src1, memory src2) %{ 5434 instruction_count(3); 5435 src1 : S3(read); 5436 src2 : S3(read); 5437 mem : S4(read); 5438 DECODE : S0; // any decoder for FPU PUSH 5439 D0 : S0(2); // big decoder only 5440 FPU : S4; 5441 MEM : S3(2); // any mem 5442 %} 5443 5444 pipe_class fpu_mem_mem(memory dst, memory src1) %{ 5445 instruction_count(2); 5446 src1 : S3(read); 5447 dst : S4(read); 5448 D0 : S0(2); // big decoder only 5449 MEM : S3(2); // any mem 5450 %} 5451 5452 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ 5453 instruction_count(3); 5454 src1 : S3(read); 5455 src2 : S3(read); 5456 dst : S4(read); 5457 D0 : S0(3); // big decoder only 5458 FPU : S4; 5459 MEM : S3(3); // any mem 5460 %} 5461 5462 pipe_class fpu_mem_reg_con(memory mem, regDPR src1) %{ 5463 instruction_count(3); 5464 src1 : S4(read); 5465 mem : S4(read); 5466 DECODE : S0; // any decoder for FPU PUSH 5467 D0 : S0(2); // big decoder only 5468 FPU : S4; 5469 MEM : S3(2); // any mem 5470 %} 5471 5472 // Float load constant 5473 pipe_class fpu_reg_con(regDPR dst) %{ 5474 instruction_count(2); 5475 dst : S5(write); 5476 D0 : S0; // big decoder only for the load 5477 DECODE : S1; // any decoder for FPU POP 5478 FPU : S4; 5479 MEM : S3; // any mem 5480 %} 5481 5482 // Float load constant 5483 pipe_class fpu_reg_reg_con(regDPR dst, regDPR src) %{ 5484 instruction_count(3); 5485 dst : S5(write); 5486 src : S3(read); 5487 D0 : S0; // big decoder only for the load 5488 DECODE : S1(2); // any decoder for FPU POP 5489 FPU : S4; 5490 MEM : S3; // any mem 5491 %} 5492 5493 // UnConditional branch 5494 pipe_class pipe_jmp( label labl ) %{ 5495 single_instruction; 5496 BR : S3; 5497 %} 5498 5499 // Conditional branch 5500 pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ 5501 single_instruction; 5502 cr : S1(read); 5503 BR : S3; 5504 %} 5505 5506 // Allocation idiom 5507 pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ 5508 instruction_count(1); force_serialization; 5509 fixed_latency(6); 5510 heap_ptr : S3(read); 5511 DECODE : S0(3); 5512 D0 : S2; 5513 MEM : S3; 5514 ALU : S3(2); 5515 dst : S5(write); 5516 BR : S5; 5517 %} 5518 5519 // Generic big/slow expanded idiom 5520 pipe_class pipe_slow( ) %{ 5521 instruction_count(10); multiple_bundles; force_serialization; 5522 fixed_latency(100); 5523 D0 : S0(2); 5524 MEM : S3(2); 5525 %} 5526 5527 // The real do-nothing guy 5528 pipe_class empty( ) %{ 5529 instruction_count(0); 5530 %} 5531 5532 // Define the class for the Nop node 5533 define %{ 5534 MachNop = empty; 5535 %} 5536 5537 %} 5538 5539 //----------INSTRUCTIONS------------------------------------------------------- 5540 // 5541 // match -- States which machine-independent subtree may be replaced 5542 // by this instruction. 5543 // ins_cost -- The estimated cost of this instruction is used by instruction 5544 // selection to identify a minimum cost tree of machine 5545 // instructions that matches a tree of machine-independent 5546 // instructions. 5547 // format -- A string providing the disassembly for this instruction. 5548 // The value of an instruction's operand may be inserted 5549 // by referring to it with a '$' prefix. 5550 // opcode -- Three instruction opcodes may be provided. These are referred 5551 // to within an encode class as $primary, $secondary, and $tertiary 5552 // respectively. The primary opcode is commonly used to 5553 // indicate the type of machine instruction, while secondary 5554 // and tertiary are often used for prefix options or addressing 5555 // modes. 5556 // ins_encode -- A list of encode classes with parameters. The encode class 5557 // name must have been defined in an 'enc_class' specification 5558 // in the encode section of the architecture description. 5559 5560 //----------BSWAP-Instruction-------------------------------------------------- 5561 instruct bytes_reverse_int(rRegI dst) %{ 5562 match(Set dst (ReverseBytesI dst)); 5563 5564 format %{ "BSWAP $dst" %} 5565 opcode(0x0F, 0xC8); 5566 ins_encode( OpcP, OpcSReg(dst) ); 5567 ins_pipe( ialu_reg ); 5568 %} 5569 5570 instruct bytes_reverse_long(eRegL dst) %{ 5571 match(Set dst (ReverseBytesL dst)); 5572 5573 format %{ "BSWAP $dst.lo\n\t" 5574 "BSWAP $dst.hi\n\t" 5575 "XCHG $dst.lo $dst.hi" %} 5576 5577 ins_cost(125); 5578 ins_encode( bswap_long_bytes(dst) ); 5579 ins_pipe( ialu_reg_reg); 5580 %} 5581 5582 instruct bytes_reverse_unsigned_short(rRegI dst, eFlagsReg cr) %{ 5583 match(Set dst (ReverseBytesUS dst)); 5584 effect(KILL cr); 5585 5586 format %{ "BSWAP $dst\n\t" 5587 "SHR $dst,16\n\t" %} 5588 ins_encode %{ 5589 __ bswapl($dst$$Register); 5590 __ shrl($dst$$Register, 16); 5591 %} 5592 ins_pipe( ialu_reg ); 5593 %} 5594 5595 instruct bytes_reverse_short(rRegI dst, eFlagsReg cr) %{ 5596 match(Set dst (ReverseBytesS dst)); 5597 effect(KILL cr); 5598 5599 format %{ "BSWAP $dst\n\t" 5600 "SAR $dst,16\n\t" %} 5601 ins_encode %{ 5602 __ bswapl($dst$$Register); 5603 __ sarl($dst$$Register, 16); 5604 %} 5605 ins_pipe( ialu_reg ); 5606 %} 5607 5608 5609 //---------- Zeros Count Instructions ------------------------------------------ 5610 5611 instruct countLeadingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ 5612 predicate(UseCountLeadingZerosInstruction); 5613 match(Set dst (CountLeadingZerosI src)); 5614 effect(KILL cr); 5615 5616 format %{ "LZCNT $dst, $src\t# count leading zeros (int)" %} 5617 ins_encode %{ 5618 __ lzcntl($dst$$Register, $src$$Register); 5619 %} 5620 ins_pipe(ialu_reg); 5621 %} 5622 5623 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, eFlagsReg cr) %{ 5624 predicate(!UseCountLeadingZerosInstruction); 5625 match(Set dst (CountLeadingZerosI src)); 5626 effect(KILL cr); 5627 5628 format %{ "BSR $dst, $src\t# count leading zeros (int)\n\t" 5629 "JNZ skip\n\t" 5630 "MOV $dst, -1\n" 5631 "skip:\n\t" 5632 "NEG $dst\n\t" 5633 "ADD $dst, 31" %} 5634 ins_encode %{ 5635 Register Rdst = $dst$$Register; 5636 Register Rsrc = $src$$Register; 5637 Label skip; 5638 __ bsrl(Rdst, Rsrc); 5639 __ jccb(Assembler::notZero, skip); 5640 __ movl(Rdst, -1); 5641 __ bind(skip); 5642 __ negl(Rdst); 5643 __ addl(Rdst, BitsPerInt - 1); 5644 %} 5645 ins_pipe(ialu_reg); 5646 %} 5647 5648 instruct countLeadingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ 5649 predicate(UseCountLeadingZerosInstruction); 5650 match(Set dst (CountLeadingZerosL src)); 5651 effect(TEMP dst, KILL cr); 5652 5653 format %{ "LZCNT $dst, $src.hi\t# count leading zeros (long)\n\t" 5654 "JNC done\n\t" 5655 "LZCNT $dst, $src.lo\n\t" 5656 "ADD $dst, 32\n" 5657 "done:" %} 5658 ins_encode %{ 5659 Register Rdst = $dst$$Register; 5660 Register Rsrc = $src$$Register; 5661 Label done; 5662 __ lzcntl(Rdst, HIGH_FROM_LOW(Rsrc)); 5663 __ jccb(Assembler::carryClear, done); 5664 __ lzcntl(Rdst, Rsrc); 5665 __ addl(Rdst, BitsPerInt); 5666 __ bind(done); 5667 %} 5668 ins_pipe(ialu_reg); 5669 %} 5670 5671 instruct countLeadingZerosL_bsr(rRegI dst, eRegL src, eFlagsReg cr) %{ 5672 predicate(!UseCountLeadingZerosInstruction); 5673 match(Set dst (CountLeadingZerosL src)); 5674 effect(TEMP dst, KILL cr); 5675 5676 format %{ "BSR $dst, $src.hi\t# count leading zeros (long)\n\t" 5677 "JZ msw_is_zero\n\t" 5678 "ADD $dst, 32\n\t" 5679 "JMP not_zero\n" 5680 "msw_is_zero:\n\t" 5681 "BSR $dst, $src.lo\n\t" 5682 "JNZ not_zero\n\t" 5683 "MOV $dst, -1\n" 5684 "not_zero:\n\t" 5685 "NEG $dst\n\t" 5686 "ADD $dst, 63\n" %} 5687 ins_encode %{ 5688 Register Rdst = $dst$$Register; 5689 Register Rsrc = $src$$Register; 5690 Label msw_is_zero; 5691 Label not_zero; 5692 __ bsrl(Rdst, HIGH_FROM_LOW(Rsrc)); 5693 __ jccb(Assembler::zero, msw_is_zero); 5694 __ addl(Rdst, BitsPerInt); 5695 __ jmpb(not_zero); 5696 __ bind(msw_is_zero); 5697 __ bsrl(Rdst, Rsrc); 5698 __ jccb(Assembler::notZero, not_zero); 5699 __ movl(Rdst, -1); 5700 __ bind(not_zero); 5701 __ negl(Rdst); 5702 __ addl(Rdst, BitsPerLong - 1); 5703 %} 5704 ins_pipe(ialu_reg); 5705 %} 5706 5707 instruct countTrailingZerosI(rRegI dst, rRegI src, eFlagsReg cr) %{ 5708 match(Set dst (CountTrailingZerosI src)); 5709 effect(KILL cr); 5710 5711 format %{ "BSF $dst, $src\t# count trailing zeros (int)\n\t" 5712 "JNZ done\n\t" 5713 "MOV $dst, 32\n" 5714 "done:" %} 5715 ins_encode %{ 5716 Register Rdst = $dst$$Register; 5717 Label done; 5718 __ bsfl(Rdst, $src$$Register); 5719 __ jccb(Assembler::notZero, done); 5720 __ movl(Rdst, BitsPerInt); 5721 __ bind(done); 5722 %} 5723 ins_pipe(ialu_reg); 5724 %} 5725 5726 instruct countTrailingZerosL(rRegI dst, eRegL src, eFlagsReg cr) %{ 5727 match(Set dst (CountTrailingZerosL src)); 5728 effect(TEMP dst, KILL cr); 5729 5730 format %{ "BSF $dst, $src.lo\t# count trailing zeros (long)\n\t" 5731 "JNZ done\n\t" 5732 "BSF $dst, $src.hi\n\t" 5733 "JNZ msw_not_zero\n\t" 5734 "MOV $dst, 32\n" 5735 "msw_not_zero:\n\t" 5736 "ADD $dst, 32\n" 5737 "done:" %} 5738 ins_encode %{ 5739 Register Rdst = $dst$$Register; 5740 Register Rsrc = $src$$Register; 5741 Label msw_not_zero; 5742 Label done; 5743 __ bsfl(Rdst, Rsrc); 5744 __ jccb(Assembler::notZero, done); 5745 __ bsfl(Rdst, HIGH_FROM_LOW(Rsrc)); 5746 __ jccb(Assembler::notZero, msw_not_zero); 5747 __ movl(Rdst, BitsPerInt); 5748 __ bind(msw_not_zero); 5749 __ addl(Rdst, BitsPerInt); 5750 __ bind(done); 5751 %} 5752 ins_pipe(ialu_reg); 5753 %} 5754 5755 5756 //---------- Population Count Instructions ------------------------------------- 5757 5758 instruct popCountI(rRegI dst, rRegI src, eFlagsReg cr) %{ 5759 predicate(UsePopCountInstruction); 5760 match(Set dst (PopCountI src)); 5761 effect(KILL cr); 5762 5763 format %{ "POPCNT $dst, $src" %} 5764 ins_encode %{ 5765 __ popcntl($dst$$Register, $src$$Register); 5766 %} 5767 ins_pipe(ialu_reg); 5768 %} 5769 5770 instruct popCountI_mem(rRegI dst, memory mem, eFlagsReg cr) %{ 5771 predicate(UsePopCountInstruction); 5772 match(Set dst (PopCountI (LoadI mem))); 5773 effect(KILL cr); 5774 5775 format %{ "POPCNT $dst, $mem" %} 5776 ins_encode %{ 5777 __ popcntl($dst$$Register, $mem$$Address); 5778 %} 5779 ins_pipe(ialu_reg); 5780 %} 5781 5782 // Note: Long.bitCount(long) returns an int. 5783 instruct popCountL(rRegI dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ 5784 predicate(UsePopCountInstruction); 5785 match(Set dst (PopCountL src)); 5786 effect(KILL cr, TEMP tmp, TEMP dst); 5787 5788 format %{ "POPCNT $dst, $src.lo\n\t" 5789 "POPCNT $tmp, $src.hi\n\t" 5790 "ADD $dst, $tmp" %} 5791 ins_encode %{ 5792 __ popcntl($dst$$Register, $src$$Register); 5793 __ popcntl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); 5794 __ addl($dst$$Register, $tmp$$Register); 5795 %} 5796 ins_pipe(ialu_reg); 5797 %} 5798 5799 // Note: Long.bitCount(long) returns an int. 5800 instruct popCountL_mem(rRegI dst, memory mem, rRegI tmp, eFlagsReg cr) %{ 5801 predicate(UsePopCountInstruction); 5802 match(Set dst (PopCountL (LoadL mem))); 5803 effect(KILL cr, TEMP tmp, TEMP dst); 5804 5805 format %{ "POPCNT $dst, $mem\n\t" 5806 "POPCNT $tmp, $mem+4\n\t" 5807 "ADD $dst, $tmp" %} 5808 ins_encode %{ 5809 //__ popcntl($dst$$Register, $mem$$Address$$first); 5810 //__ popcntl($tmp$$Register, $mem$$Address$$second); 5811 __ popcntl($dst$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none)); 5812 __ popcntl($tmp$$Register, Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none)); 5813 __ addl($dst$$Register, $tmp$$Register); 5814 %} 5815 ins_pipe(ialu_reg); 5816 %} 5817 5818 5819 //----------Load/Store/Move Instructions--------------------------------------- 5820 //----------Load Instructions-------------------------------------------------- 5821 // Load Byte (8bit signed) 5822 instruct loadB(xRegI dst, memory mem) %{ 5823 match(Set dst (LoadB mem)); 5824 5825 ins_cost(125); 5826 format %{ "MOVSX8 $dst,$mem\t# byte" %} 5827 5828 ins_encode %{ 5829 __ movsbl($dst$$Register, $mem$$Address); 5830 %} 5831 5832 ins_pipe(ialu_reg_mem); 5833 %} 5834 5835 // Load Byte (8bit signed) into Long Register 5836 instruct loadB2L(eRegL dst, memory mem, eFlagsReg cr) %{ 5837 match(Set dst (ConvI2L (LoadB mem))); 5838 effect(KILL cr); 5839 5840 ins_cost(375); 5841 format %{ "MOVSX8 $dst.lo,$mem\t# byte -> long\n\t" 5842 "MOV $dst.hi,$dst.lo\n\t" 5843 "SAR $dst.hi,7" %} 5844 5845 ins_encode %{ 5846 __ movsbl($dst$$Register, $mem$$Address); 5847 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 5848 __ sarl(HIGH_FROM_LOW($dst$$Register), 7); // 24+1 MSB are already signed extended. 5849 %} 5850 5851 ins_pipe(ialu_reg_mem); 5852 %} 5853 5854 // Load Byte (8 bit signed) with mask into Long Register 5855 instruct loadB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ 5856 match(Set dst (ConvI2L (AndI (LoadB mem) mask))); 5857 effect(KILL cr); 5858 5859 format %{ "MOVZX8 $dst.lo,$mem\t# byte & 8-bit mask -> long\n\t" 5860 "XOR $dst.hi,$dst.hi\n\t" 5861 "AND $dst.lo,$mask" %} 5862 ins_encode %{ 5863 Register Rdst = $dst$$Register; 5864 __ movzbl(Rdst, $mem$$Address); 5865 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5866 __ andl(Rdst, $mask$$constant); 5867 %} 5868 ins_pipe(ialu_reg_mem); 5869 %} 5870 5871 // Load Unsigned Byte (8bit UNsigned) 5872 instruct loadUB(xRegI dst, memory mem) %{ 5873 match(Set dst (LoadUB mem)); 5874 5875 ins_cost(125); 5876 format %{ "MOVZX8 $dst,$mem\t# ubyte -> int" %} 5877 5878 ins_encode %{ 5879 __ movzbl($dst$$Register, $mem$$Address); 5880 %} 5881 5882 ins_pipe(ialu_reg_mem); 5883 %} 5884 5885 // Load Unsigned Byte (8 bit UNsigned) into Long Register 5886 instruct loadUB2L(eRegL dst, memory mem, eFlagsReg cr) %{ 5887 match(Set dst (ConvI2L (LoadUB mem))); 5888 effect(KILL cr); 5889 5890 ins_cost(250); 5891 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte -> long\n\t" 5892 "XOR $dst.hi,$dst.hi" %} 5893 5894 ins_encode %{ 5895 Register Rdst = $dst$$Register; 5896 __ movzbl(Rdst, $mem$$Address); 5897 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5898 %} 5899 5900 ins_pipe(ialu_reg_mem); 5901 %} 5902 5903 // Load Unsigned Byte (8 bit UNsigned) with mask into Long Register 5904 instruct loadUB2L_immI8(eRegL dst, memory mem, immI8 mask, eFlagsReg cr) %{ 5905 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5906 effect(KILL cr); 5907 5908 format %{ "MOVZX8 $dst.lo,$mem\t# ubyte & 8-bit mask -> long\n\t" 5909 "XOR $dst.hi,$dst.hi\n\t" 5910 "AND $dst.lo,$mask" %} 5911 ins_encode %{ 5912 Register Rdst = $dst$$Register; 5913 __ movzbl(Rdst, $mem$$Address); 5914 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5915 __ andl(Rdst, $mask$$constant); 5916 %} 5917 ins_pipe(ialu_reg_mem); 5918 %} 5919 5920 // Load Short (16bit signed) 5921 instruct loadS(rRegI dst, memory mem) %{ 5922 match(Set dst (LoadS mem)); 5923 5924 ins_cost(125); 5925 format %{ "MOVSX $dst,$mem\t# short" %} 5926 5927 ins_encode %{ 5928 __ movswl($dst$$Register, $mem$$Address); 5929 %} 5930 5931 ins_pipe(ialu_reg_mem); 5932 %} 5933 5934 // Load Short (16 bit signed) to Byte (8 bit signed) 5935 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 5936 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5937 5938 ins_cost(125); 5939 format %{ "MOVSX $dst, $mem\t# short -> byte" %} 5940 ins_encode %{ 5941 __ movsbl($dst$$Register, $mem$$Address); 5942 %} 5943 ins_pipe(ialu_reg_mem); 5944 %} 5945 5946 // Load Short (16bit signed) into Long Register 5947 instruct loadS2L(eRegL dst, memory mem, eFlagsReg cr) %{ 5948 match(Set dst (ConvI2L (LoadS mem))); 5949 effect(KILL cr); 5950 5951 ins_cost(375); 5952 format %{ "MOVSX $dst.lo,$mem\t# short -> long\n\t" 5953 "MOV $dst.hi,$dst.lo\n\t" 5954 "SAR $dst.hi,15" %} 5955 5956 ins_encode %{ 5957 __ movswl($dst$$Register, $mem$$Address); 5958 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 5959 __ sarl(HIGH_FROM_LOW($dst$$Register), 15); // 16+1 MSB are already signed extended. 5960 %} 5961 5962 ins_pipe(ialu_reg_mem); 5963 %} 5964 5965 // Load Short (16 bit signed) with mask 0xFF into Long Register 5966 instruct loadS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ 5967 match(Set dst (ConvI2L (AndI (LoadS mem) mask))); 5968 effect(KILL cr); 5969 5970 format %{ "MOVZX8 $dst.lo,$mem\t# short & 0xFF -> long\n\t" 5971 "XOR $dst.hi,$dst.hi" %} 5972 ins_encode %{ 5973 Register Rdst = $dst$$Register; 5974 __ movzbl(Rdst, $mem$$Address); 5975 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5976 %} 5977 ins_pipe(ialu_reg_mem); 5978 %} 5979 5980 // Load Short (16 bit signed) with a 16-bit mask into Long Register 5981 instruct loadS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ 5982 match(Set dst (ConvI2L (AndI (LoadS mem) mask))); 5983 effect(KILL cr); 5984 5985 format %{ "MOVZX $dst.lo, $mem\t# short & 16-bit mask -> long\n\t" 5986 "XOR $dst.hi,$dst.hi\n\t" 5987 "AND $dst.lo,$mask" %} 5988 ins_encode %{ 5989 Register Rdst = $dst$$Register; 5990 __ movzwl(Rdst, $mem$$Address); 5991 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 5992 __ andl(Rdst, $mask$$constant); 5993 %} 5994 ins_pipe(ialu_reg_mem); 5995 %} 5996 5997 // Load Unsigned Short/Char (16bit unsigned) 5998 instruct loadUS(rRegI dst, memory mem) %{ 5999 match(Set dst (LoadUS mem)); 6000 6001 ins_cost(125); 6002 format %{ "MOVZX $dst,$mem\t# ushort/char -> int" %} 6003 6004 ins_encode %{ 6005 __ movzwl($dst$$Register, $mem$$Address); 6006 %} 6007 6008 ins_pipe(ialu_reg_mem); 6009 %} 6010 6011 // Load Unsigned Short/Char (16 bit UNsigned) shifting left & right by 16-bit 6012 instruct loadUS_shiftLR_16(rRegI dst, memory mem, immI_16 sixteen) 6013 %{ 6014 match(Set dst (RShiftI (LShiftI (LoadUS mem) sixteen) sixteen)); 6015 6016 ins_cost(125); 6017 format %{ "MOVSX $dst,$mem\t# (ushort/char << 16 ) >> 16" %} 6018 6019 ins_encode %{ 6020 __ movswl($dst$$Register, $mem$$Address); 6021 %} 6022 6023 ins_pipe(ialu_reg_reg); 6024 %} 6025 6026 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 6027 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 6028 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 6029 6030 ins_cost(125); 6031 format %{ "MOVSX $dst, $mem\t# ushort -> byte" %} 6032 ins_encode %{ 6033 __ movsbl($dst$$Register, $mem$$Address); 6034 %} 6035 ins_pipe(ialu_reg_mem); 6036 %} 6037 6038 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register 6039 instruct loadUS2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6040 match(Set dst (ConvI2L (LoadUS mem))); 6041 effect(KILL cr); 6042 6043 ins_cost(250); 6044 format %{ "MOVZX $dst.lo,$mem\t# ushort/char -> long\n\t" 6045 "XOR $dst.hi,$dst.hi" %} 6046 6047 ins_encode %{ 6048 __ movzwl($dst$$Register, $mem$$Address); 6049 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6050 %} 6051 6052 ins_pipe(ialu_reg_mem); 6053 %} 6054 6055 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register 6056 instruct loadUS2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ 6057 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 6058 effect(KILL cr); 6059 6060 format %{ "MOVZX8 $dst.lo,$mem\t# ushort/char & 0xFF -> long\n\t" 6061 "XOR $dst.hi,$dst.hi" %} 6062 ins_encode %{ 6063 Register Rdst = $dst$$Register; 6064 __ movzbl(Rdst, $mem$$Address); 6065 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6066 %} 6067 ins_pipe(ialu_reg_mem); 6068 %} 6069 6070 // Load Unsigned Short/Char (16 bit UNsigned) with a 16-bit mask into Long Register 6071 instruct loadUS2L_immI16(eRegL dst, memory mem, immI16 mask, eFlagsReg cr) %{ 6072 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 6073 effect(KILL cr); 6074 6075 format %{ "MOVZX $dst.lo, $mem\t# ushort/char & 16-bit mask -> long\n\t" 6076 "XOR $dst.hi,$dst.hi\n\t" 6077 "AND $dst.lo,$mask" %} 6078 ins_encode %{ 6079 Register Rdst = $dst$$Register; 6080 __ movzwl(Rdst, $mem$$Address); 6081 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6082 __ andl(Rdst, $mask$$constant); 6083 %} 6084 ins_pipe(ialu_reg_mem); 6085 %} 6086 6087 // Load Integer 6088 instruct loadI(rRegI dst, memory mem) %{ 6089 match(Set dst (LoadI mem)); 6090 6091 ins_cost(125); 6092 format %{ "MOV $dst,$mem\t# int" %} 6093 6094 ins_encode %{ 6095 __ movl($dst$$Register, $mem$$Address); 6096 %} 6097 6098 ins_pipe(ialu_reg_mem); 6099 %} 6100 6101 // Load Integer (32 bit signed) to Byte (8 bit signed) 6102 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{ 6103 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 6104 6105 ins_cost(125); 6106 format %{ "MOVSX $dst, $mem\t# int -> byte" %} 6107 ins_encode %{ 6108 __ movsbl($dst$$Register, $mem$$Address); 6109 %} 6110 ins_pipe(ialu_reg_mem); 6111 %} 6112 6113 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned) 6114 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{ 6115 match(Set dst (AndI (LoadI mem) mask)); 6116 6117 ins_cost(125); 6118 format %{ "MOVZX $dst, $mem\t# int -> ubyte" %} 6119 ins_encode %{ 6120 __ movzbl($dst$$Register, $mem$$Address); 6121 %} 6122 ins_pipe(ialu_reg_mem); 6123 %} 6124 6125 // Load Integer (32 bit signed) to Short (16 bit signed) 6126 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{ 6127 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 6128 6129 ins_cost(125); 6130 format %{ "MOVSX $dst, $mem\t# int -> short" %} 6131 ins_encode %{ 6132 __ movswl($dst$$Register, $mem$$Address); 6133 %} 6134 ins_pipe(ialu_reg_mem); 6135 %} 6136 6137 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned) 6138 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{ 6139 match(Set dst (AndI (LoadI mem) mask)); 6140 6141 ins_cost(125); 6142 format %{ "MOVZX $dst, $mem\t# int -> ushort/char" %} 6143 ins_encode %{ 6144 __ movzwl($dst$$Register, $mem$$Address); 6145 %} 6146 ins_pipe(ialu_reg_mem); 6147 %} 6148 6149 // Load Integer into Long Register 6150 instruct loadI2L(eRegL dst, memory mem, eFlagsReg cr) %{ 6151 match(Set dst (ConvI2L (LoadI mem))); 6152 effect(KILL cr); 6153 6154 ins_cost(375); 6155 format %{ "MOV $dst.lo,$mem\t# int -> long\n\t" 6156 "MOV $dst.hi,$dst.lo\n\t" 6157 "SAR $dst.hi,31" %} 6158 6159 ins_encode %{ 6160 __ movl($dst$$Register, $mem$$Address); 6161 __ movl(HIGH_FROM_LOW($dst$$Register), $dst$$Register); // This is always a different register. 6162 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); 6163 %} 6164 6165 ins_pipe(ialu_reg_mem); 6166 %} 6167 6168 // Load Integer with mask 0xFF into Long Register 6169 instruct loadI2L_immI_255(eRegL dst, memory mem, immI_255 mask, eFlagsReg cr) %{ 6170 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6171 effect(KILL cr); 6172 6173 format %{ "MOVZX8 $dst.lo,$mem\t# int & 0xFF -> long\n\t" 6174 "XOR $dst.hi,$dst.hi" %} 6175 ins_encode %{ 6176 Register Rdst = $dst$$Register; 6177 __ movzbl(Rdst, $mem$$Address); 6178 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6179 %} 6180 ins_pipe(ialu_reg_mem); 6181 %} 6182 6183 // Load Integer with mask 0xFFFF into Long Register 6184 instruct loadI2L_immI_65535(eRegL dst, memory mem, immI_65535 mask, eFlagsReg cr) %{ 6185 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6186 effect(KILL cr); 6187 6188 format %{ "MOVZX $dst.lo,$mem\t# int & 0xFFFF -> long\n\t" 6189 "XOR $dst.hi,$dst.hi" %} 6190 ins_encode %{ 6191 Register Rdst = $dst$$Register; 6192 __ movzwl(Rdst, $mem$$Address); 6193 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6194 %} 6195 ins_pipe(ialu_reg_mem); 6196 %} 6197 6198 // Load Integer with 32-bit mask into Long Register 6199 instruct loadI2L_immI(eRegL dst, memory mem, immI mask, eFlagsReg cr) %{ 6200 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 6201 effect(KILL cr); 6202 6203 format %{ "MOV $dst.lo,$mem\t# int & 32-bit mask -> long\n\t" 6204 "XOR $dst.hi,$dst.hi\n\t" 6205 "AND $dst.lo,$mask" %} 6206 ins_encode %{ 6207 Register Rdst = $dst$$Register; 6208 __ movl(Rdst, $mem$$Address); 6209 __ xorl(HIGH_FROM_LOW(Rdst), HIGH_FROM_LOW(Rdst)); 6210 __ andl(Rdst, $mask$$constant); 6211 %} 6212 ins_pipe(ialu_reg_mem); 6213 %} 6214 6215 // Load Unsigned Integer into Long Register 6216 instruct loadUI2L(eRegL dst, memory mem, immL_32bits mask, eFlagsReg cr) %{ 6217 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 6218 effect(KILL cr); 6219 6220 ins_cost(250); 6221 format %{ "MOV $dst.lo,$mem\t# uint -> long\n\t" 6222 "XOR $dst.hi,$dst.hi" %} 6223 6224 ins_encode %{ 6225 __ movl($dst$$Register, $mem$$Address); 6226 __ xorl(HIGH_FROM_LOW($dst$$Register), HIGH_FROM_LOW($dst$$Register)); 6227 %} 6228 6229 ins_pipe(ialu_reg_mem); 6230 %} 6231 6232 // Load Long. Cannot clobber address while loading, so restrict address 6233 // register to ESI 6234 instruct loadL(eRegL dst, load_long_memory mem) %{ 6235 predicate(!((LoadLNode*)n)->require_atomic_access()); 6236 match(Set dst (LoadL mem)); 6237 6238 ins_cost(250); 6239 format %{ "MOV $dst.lo,$mem\t# long\n\t" 6240 "MOV $dst.hi,$mem+4" %} 6241 6242 ins_encode %{ 6243 Address Amemlo = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp, relocInfo::none); 6244 Address Amemhi = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp + 4, relocInfo::none); 6245 __ movl($dst$$Register, Amemlo); 6246 __ movl(HIGH_FROM_LOW($dst$$Register), Amemhi); 6247 %} 6248 6249 ins_pipe(ialu_reg_long_mem); 6250 %} 6251 6252 // Volatile Load Long. Must be atomic, so do 64-bit FILD 6253 // then store it down to the stack and reload on the int 6254 // side. 6255 instruct loadL_volatile(stackSlotL dst, memory mem) %{ 6256 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); 6257 match(Set dst (LoadL mem)); 6258 6259 ins_cost(200); 6260 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 6261 "FISTp $dst" %} 6262 ins_encode(enc_loadL_volatile(mem,dst)); 6263 ins_pipe( fpu_reg_mem ); 6264 %} 6265 6266 instruct loadLX_volatile(stackSlotL dst, memory mem, regD tmp) %{ 6267 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6268 match(Set dst (LoadL mem)); 6269 effect(TEMP tmp); 6270 ins_cost(180); 6271 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6272 "MOVSD $dst,$tmp" %} 6273 ins_encode %{ 6274 __ movdbl($tmp$$XMMRegister, $mem$$Address); 6275 __ movdbl(Address(rsp, $dst$$disp), $tmp$$XMMRegister); 6276 %} 6277 ins_pipe( pipe_slow ); 6278 %} 6279 6280 instruct loadLX_reg_volatile(eRegL dst, memory mem, regD tmp) %{ 6281 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6282 match(Set dst (LoadL mem)); 6283 effect(TEMP tmp); 6284 ins_cost(160); 6285 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6286 "MOVD $dst.lo,$tmp\n\t" 6287 "PSRLQ $tmp,32\n\t" 6288 "MOVD $dst.hi,$tmp" %} 6289 ins_encode %{ 6290 __ movdbl($tmp$$XMMRegister, $mem$$Address); 6291 __ movdl($dst$$Register, $tmp$$XMMRegister); 6292 __ psrlq($tmp$$XMMRegister, 32); 6293 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); 6294 %} 6295 ins_pipe( pipe_slow ); 6296 %} 6297 6298 // Load Range 6299 instruct loadRange(rRegI dst, memory mem) %{ 6300 match(Set dst (LoadRange mem)); 6301 6302 ins_cost(125); 6303 format %{ "MOV $dst,$mem" %} 6304 opcode(0x8B); 6305 ins_encode( OpcP, RegMem(dst,mem)); 6306 ins_pipe( ialu_reg_mem ); 6307 %} 6308 6309 6310 // Load Pointer 6311 instruct loadP(eRegP dst, memory mem) %{ 6312 match(Set dst (LoadP mem)); 6313 6314 ins_cost(125); 6315 format %{ "MOV $dst,$mem" %} 6316 opcode(0x8B); 6317 ins_encode( OpcP, RegMem(dst,mem)); 6318 ins_pipe( ialu_reg_mem ); 6319 %} 6320 6321 // Load Klass Pointer 6322 instruct loadKlass(eRegP dst, memory mem) %{ 6323 match(Set dst (LoadKlass mem)); 6324 6325 ins_cost(125); 6326 format %{ "MOV $dst,$mem" %} 6327 opcode(0x8B); 6328 ins_encode( OpcP, RegMem(dst,mem)); 6329 ins_pipe( ialu_reg_mem ); 6330 %} 6331 6332 // Load Double 6333 instruct loadDPR(regDPR dst, memory mem) %{ 6334 predicate(UseSSE<=1); 6335 match(Set dst (LoadD mem)); 6336 6337 ins_cost(150); 6338 format %{ "FLD_D ST,$mem\n\t" 6339 "FSTP $dst" %} 6340 opcode(0xDD); /* DD /0 */ 6341 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6342 Pop_Reg_DPR(dst) ); 6343 ins_pipe( fpu_reg_mem ); 6344 %} 6345 6346 // Load Double to XMM 6347 instruct loadD(regD dst, memory mem) %{ 6348 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 6349 match(Set dst (LoadD mem)); 6350 ins_cost(145); 6351 format %{ "MOVSD $dst,$mem" %} 6352 ins_encode %{ 6353 __ movdbl ($dst$$XMMRegister, $mem$$Address); 6354 %} 6355 ins_pipe( pipe_slow ); 6356 %} 6357 6358 instruct loadD_partial(regD dst, memory mem) %{ 6359 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 6360 match(Set dst (LoadD mem)); 6361 ins_cost(145); 6362 format %{ "MOVLPD $dst,$mem" %} 6363 ins_encode %{ 6364 __ movdbl ($dst$$XMMRegister, $mem$$Address); 6365 %} 6366 ins_pipe( pipe_slow ); 6367 %} 6368 6369 // Load to XMM register (single-precision floating point) 6370 // MOVSS instruction 6371 instruct loadF(regF dst, memory mem) %{ 6372 predicate(UseSSE>=1); 6373 match(Set dst (LoadF mem)); 6374 ins_cost(145); 6375 format %{ "MOVSS $dst,$mem" %} 6376 ins_encode %{ 6377 __ movflt ($dst$$XMMRegister, $mem$$Address); 6378 %} 6379 ins_pipe( pipe_slow ); 6380 %} 6381 6382 // Load Float 6383 instruct loadFPR(regFPR dst, memory mem) %{ 6384 predicate(UseSSE==0); 6385 match(Set dst (LoadF mem)); 6386 6387 ins_cost(150); 6388 format %{ "FLD_S ST,$mem\n\t" 6389 "FSTP $dst" %} 6390 opcode(0xD9); /* D9 /0 */ 6391 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6392 Pop_Reg_FPR(dst) ); 6393 ins_pipe( fpu_reg_mem ); 6394 %} 6395 6396 // Load Effective Address 6397 instruct leaP8(eRegP dst, indOffset8 mem) %{ 6398 match(Set dst mem); 6399 6400 ins_cost(110); 6401 format %{ "LEA $dst,$mem" %} 6402 opcode(0x8D); 6403 ins_encode( OpcP, RegMem(dst,mem)); 6404 ins_pipe( ialu_reg_reg_fat ); 6405 %} 6406 6407 instruct leaP32(eRegP dst, indOffset32 mem) %{ 6408 match(Set dst mem); 6409 6410 ins_cost(110); 6411 format %{ "LEA $dst,$mem" %} 6412 opcode(0x8D); 6413 ins_encode( OpcP, RegMem(dst,mem)); 6414 ins_pipe( ialu_reg_reg_fat ); 6415 %} 6416 6417 instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ 6418 match(Set dst mem); 6419 6420 ins_cost(110); 6421 format %{ "LEA $dst,$mem" %} 6422 opcode(0x8D); 6423 ins_encode( OpcP, RegMem(dst,mem)); 6424 ins_pipe( ialu_reg_reg_fat ); 6425 %} 6426 6427 instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ 6428 match(Set dst mem); 6429 6430 ins_cost(110); 6431 format %{ "LEA $dst,$mem" %} 6432 opcode(0x8D); 6433 ins_encode( OpcP, RegMem(dst,mem)); 6434 ins_pipe( ialu_reg_reg_fat ); 6435 %} 6436 6437 instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ 6438 match(Set dst mem); 6439 6440 ins_cost(110); 6441 format %{ "LEA $dst,$mem" %} 6442 opcode(0x8D); 6443 ins_encode( OpcP, RegMem(dst,mem)); 6444 ins_pipe( ialu_reg_reg_fat ); 6445 %} 6446 6447 // Load Constant 6448 instruct loadConI(rRegI dst, immI src) %{ 6449 match(Set dst src); 6450 6451 format %{ "MOV $dst,$src" %} 6452 ins_encode( LdImmI(dst, src) ); 6453 ins_pipe( ialu_reg_fat ); 6454 %} 6455 6456 // Load Constant zero 6457 instruct loadConI0(rRegI dst, immI0 src, eFlagsReg cr) %{ 6458 match(Set dst src); 6459 effect(KILL cr); 6460 6461 ins_cost(50); 6462 format %{ "XOR $dst,$dst" %} 6463 opcode(0x33); /* + rd */ 6464 ins_encode( OpcP, RegReg( dst, dst ) ); 6465 ins_pipe( ialu_reg ); 6466 %} 6467 6468 instruct loadConP(eRegP dst, immP src) %{ 6469 match(Set dst src); 6470 6471 format %{ "MOV $dst,$src" %} 6472 opcode(0xB8); /* + rd */ 6473 ins_encode( LdImmP(dst, src) ); 6474 ins_pipe( ialu_reg_fat ); 6475 %} 6476 6477 instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ 6478 match(Set dst src); 6479 effect(KILL cr); 6480 ins_cost(200); 6481 format %{ "MOV $dst.lo,$src.lo\n\t" 6482 "MOV $dst.hi,$src.hi" %} 6483 opcode(0xB8); 6484 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); 6485 ins_pipe( ialu_reg_long_fat ); 6486 %} 6487 6488 instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ 6489 match(Set dst src); 6490 effect(KILL cr); 6491 ins_cost(150); 6492 format %{ "XOR $dst.lo,$dst.lo\n\t" 6493 "XOR $dst.hi,$dst.hi" %} 6494 opcode(0x33,0x33); 6495 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); 6496 ins_pipe( ialu_reg_long ); 6497 %} 6498 6499 // The instruction usage is guarded by predicate in operand immFPR(). 6500 instruct loadConFPR(regFPR dst, immFPR con) %{ 6501 match(Set dst con); 6502 ins_cost(125); 6503 format %{ "FLD_S ST,[$constantaddress]\t# load from constant table: float=$con\n\t" 6504 "FSTP $dst" %} 6505 ins_encode %{ 6506 __ fld_s($constantaddress($con)); 6507 __ fstp_d($dst$$reg); 6508 %} 6509 ins_pipe(fpu_reg_con); 6510 %} 6511 6512 // The instruction usage is guarded by predicate in operand immFPR0(). 6513 instruct loadConFPR0(regFPR dst, immFPR0 con) %{ 6514 match(Set dst con); 6515 ins_cost(125); 6516 format %{ "FLDZ ST\n\t" 6517 "FSTP $dst" %} 6518 ins_encode %{ 6519 __ fldz(); 6520 __ fstp_d($dst$$reg); 6521 %} 6522 ins_pipe(fpu_reg_con); 6523 %} 6524 6525 // The instruction usage is guarded by predicate in operand immFPR1(). 6526 instruct loadConFPR1(regFPR dst, immFPR1 con) %{ 6527 match(Set dst con); 6528 ins_cost(125); 6529 format %{ "FLD1 ST\n\t" 6530 "FSTP $dst" %} 6531 ins_encode %{ 6532 __ fld1(); 6533 __ fstp_d($dst$$reg); 6534 %} 6535 ins_pipe(fpu_reg_con); 6536 %} 6537 6538 // The instruction usage is guarded by predicate in operand immF(). 6539 instruct loadConF(regF dst, immF con) %{ 6540 match(Set dst con); 6541 ins_cost(125); 6542 format %{ "MOVSS $dst,[$constantaddress]\t# load from constant table: float=$con" %} 6543 ins_encode %{ 6544 __ movflt($dst$$XMMRegister, $constantaddress($con)); 6545 %} 6546 ins_pipe(pipe_slow); 6547 %} 6548 6549 // The instruction usage is guarded by predicate in operand immF0(). 6550 instruct loadConF0(regF dst, immF0 src) %{ 6551 match(Set dst src); 6552 ins_cost(100); 6553 format %{ "XORPS $dst,$dst\t# float 0.0" %} 6554 ins_encode %{ 6555 __ xorps($dst$$XMMRegister, $dst$$XMMRegister); 6556 %} 6557 ins_pipe(pipe_slow); 6558 %} 6559 6560 // The instruction usage is guarded by predicate in operand immDPR(). 6561 instruct loadConDPR(regDPR dst, immDPR con) %{ 6562 match(Set dst con); 6563 ins_cost(125); 6564 6565 format %{ "FLD_D ST,[$constantaddress]\t# load from constant table: double=$con\n\t" 6566 "FSTP $dst" %} 6567 ins_encode %{ 6568 __ fld_d($constantaddress($con)); 6569 __ fstp_d($dst$$reg); 6570 %} 6571 ins_pipe(fpu_reg_con); 6572 %} 6573 6574 // The instruction usage is guarded by predicate in operand immDPR0(). 6575 instruct loadConDPR0(regDPR dst, immDPR0 con) %{ 6576 match(Set dst con); 6577 ins_cost(125); 6578 6579 format %{ "FLDZ ST\n\t" 6580 "FSTP $dst" %} 6581 ins_encode %{ 6582 __ fldz(); 6583 __ fstp_d($dst$$reg); 6584 %} 6585 ins_pipe(fpu_reg_con); 6586 %} 6587 6588 // The instruction usage is guarded by predicate in operand immDPR1(). 6589 instruct loadConDPR1(regDPR dst, immDPR1 con) %{ 6590 match(Set dst con); 6591 ins_cost(125); 6592 6593 format %{ "FLD1 ST\n\t" 6594 "FSTP $dst" %} 6595 ins_encode %{ 6596 __ fld1(); 6597 __ fstp_d($dst$$reg); 6598 %} 6599 ins_pipe(fpu_reg_con); 6600 %} 6601 6602 // The instruction usage is guarded by predicate in operand immD(). 6603 instruct loadConD(regD dst, immD con) %{ 6604 match(Set dst con); 6605 ins_cost(125); 6606 format %{ "MOVSD $dst,[$constantaddress]\t# load from constant table: double=$con" %} 6607 ins_encode %{ 6608 __ movdbl($dst$$XMMRegister, $constantaddress($con)); 6609 %} 6610 ins_pipe(pipe_slow); 6611 %} 6612 6613 // The instruction usage is guarded by predicate in operand immD0(). 6614 instruct loadConD0(regD dst, immD0 src) %{ 6615 match(Set dst src); 6616 ins_cost(100); 6617 format %{ "XORPD $dst,$dst\t# double 0.0" %} 6618 ins_encode %{ 6619 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister); 6620 %} 6621 ins_pipe( pipe_slow ); 6622 %} 6623 6624 // Load Stack Slot 6625 instruct loadSSI(rRegI dst, stackSlotI src) %{ 6626 match(Set dst src); 6627 ins_cost(125); 6628 6629 format %{ "MOV $dst,$src" %} 6630 opcode(0x8B); 6631 ins_encode( OpcP, RegMem(dst,src)); 6632 ins_pipe( ialu_reg_mem ); 6633 %} 6634 6635 instruct loadSSL(eRegL dst, stackSlotL src) %{ 6636 match(Set dst src); 6637 6638 ins_cost(200); 6639 format %{ "MOV $dst,$src.lo\n\t" 6640 "MOV $dst+4,$src.hi" %} 6641 opcode(0x8B, 0x8B); 6642 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); 6643 ins_pipe( ialu_mem_long_reg ); 6644 %} 6645 6646 // Load Stack Slot 6647 instruct loadSSP(eRegP dst, stackSlotP src) %{ 6648 match(Set dst src); 6649 ins_cost(125); 6650 6651 format %{ "MOV $dst,$src" %} 6652 opcode(0x8B); 6653 ins_encode( OpcP, RegMem(dst,src)); 6654 ins_pipe( ialu_reg_mem ); 6655 %} 6656 6657 // Load Stack Slot 6658 instruct loadSSF(regFPR dst, stackSlotF src) %{ 6659 match(Set dst src); 6660 ins_cost(125); 6661 6662 format %{ "FLD_S $src\n\t" 6663 "FSTP $dst" %} 6664 opcode(0xD9); /* D9 /0, FLD m32real */ 6665 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6666 Pop_Reg_FPR(dst) ); 6667 ins_pipe( fpu_reg_mem ); 6668 %} 6669 6670 // Load Stack Slot 6671 instruct loadSSD(regDPR dst, stackSlotD src) %{ 6672 match(Set dst src); 6673 ins_cost(125); 6674 6675 format %{ "FLD_D $src\n\t" 6676 "FSTP $dst" %} 6677 opcode(0xDD); /* DD /0, FLD m64real */ 6678 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6679 Pop_Reg_DPR(dst) ); 6680 ins_pipe( fpu_reg_mem ); 6681 %} 6682 6683 // Prefetch instructions. 6684 // Must be safe to execute with invalid address (cannot fault). 6685 6686 instruct prefetchr0( memory mem ) %{ 6687 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); 6688 match(PrefetchRead mem); 6689 ins_cost(0); 6690 size(0); 6691 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 6692 ins_encode(); 6693 ins_pipe(empty); 6694 %} 6695 6696 instruct prefetchr( memory mem ) %{ 6697 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch() || ReadPrefetchInstr==3); 6698 match(PrefetchRead mem); 6699 ins_cost(100); 6700 6701 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 6702 ins_encode %{ 6703 __ prefetchr($mem$$Address); 6704 %} 6705 ins_pipe(ialu_mem); 6706 %} 6707 6708 instruct prefetchrNTA( memory mem ) %{ 6709 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 6710 match(PrefetchRead mem); 6711 ins_cost(100); 6712 6713 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 6714 ins_encode %{ 6715 __ prefetchnta($mem$$Address); 6716 %} 6717 ins_pipe(ialu_mem); 6718 %} 6719 6720 instruct prefetchrT0( memory mem ) %{ 6721 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 6722 match(PrefetchRead mem); 6723 ins_cost(100); 6724 6725 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 6726 ins_encode %{ 6727 __ prefetcht0($mem$$Address); 6728 %} 6729 ins_pipe(ialu_mem); 6730 %} 6731 6732 instruct prefetchrT2( memory mem ) %{ 6733 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 6734 match(PrefetchRead mem); 6735 ins_cost(100); 6736 6737 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 6738 ins_encode %{ 6739 __ prefetcht2($mem$$Address); 6740 %} 6741 ins_pipe(ialu_mem); 6742 %} 6743 6744 instruct prefetchw0( memory mem ) %{ 6745 predicate(UseSSE==0 && !VM_Version::supports_3dnow_prefetch()); 6746 match(PrefetchWrite mem); 6747 ins_cost(0); 6748 size(0); 6749 format %{ "Prefetch (non-SSE is empty encoding)" %} 6750 ins_encode(); 6751 ins_pipe(empty); 6752 %} 6753 6754 instruct prefetchw( memory mem ) %{ 6755 predicate(UseSSE==0 && VM_Version::supports_3dnow_prefetch()); 6756 match( PrefetchWrite mem ); 6757 ins_cost(100); 6758 6759 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 6760 ins_encode %{ 6761 __ prefetchw($mem$$Address); 6762 %} 6763 ins_pipe(ialu_mem); 6764 %} 6765 6766 instruct prefetchwNTA( memory mem ) %{ 6767 predicate(UseSSE>=1); 6768 match(PrefetchWrite mem); 6769 ins_cost(100); 6770 6771 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 6772 ins_encode %{ 6773 __ prefetchnta($mem$$Address); 6774 %} 6775 ins_pipe(ialu_mem); 6776 %} 6777 6778 // Prefetch instructions for allocation. 6779 6780 instruct prefetchAlloc0( memory mem ) %{ 6781 predicate(UseSSE==0 && AllocatePrefetchInstr!=3); 6782 match(PrefetchAllocation mem); 6783 ins_cost(0); 6784 size(0); 6785 format %{ "Prefetch allocation (non-SSE is empty encoding)" %} 6786 ins_encode(); 6787 ins_pipe(empty); 6788 %} 6789 6790 instruct prefetchAlloc( memory mem ) %{ 6791 predicate(AllocatePrefetchInstr==3); 6792 match( PrefetchAllocation mem ); 6793 ins_cost(100); 6794 6795 format %{ "PREFETCHW $mem\t! Prefetch allocation into L1 cache and mark modified" %} 6796 ins_encode %{ 6797 __ prefetchw($mem$$Address); 6798 %} 6799 ins_pipe(ialu_mem); 6800 %} 6801 6802 instruct prefetchAllocNTA( memory mem ) %{ 6803 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 6804 match(PrefetchAllocation mem); 6805 ins_cost(100); 6806 6807 format %{ "PREFETCHNTA $mem\t! Prefetch allocation into non-temporal cache for write" %} 6808 ins_encode %{ 6809 __ prefetchnta($mem$$Address); 6810 %} 6811 ins_pipe(ialu_mem); 6812 %} 6813 6814 instruct prefetchAllocT0( memory mem ) %{ 6815 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 6816 match(PrefetchAllocation mem); 6817 ins_cost(100); 6818 6819 format %{ "PREFETCHT0 $mem\t! Prefetch allocation into L1 and L2 caches for write" %} 6820 ins_encode %{ 6821 __ prefetcht0($mem$$Address); 6822 %} 6823 ins_pipe(ialu_mem); 6824 %} 6825 6826 instruct prefetchAllocT2( memory mem ) %{ 6827 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 6828 match(PrefetchAllocation mem); 6829 ins_cost(100); 6830 6831 format %{ "PREFETCHT2 $mem\t! Prefetch allocation into L2 cache for write" %} 6832 ins_encode %{ 6833 __ prefetcht2($mem$$Address); 6834 %} 6835 ins_pipe(ialu_mem); 6836 %} 6837 6838 //----------Store Instructions------------------------------------------------- 6839 6840 // Store Byte 6841 instruct storeB(memory mem, xRegI src) %{ 6842 match(Set mem (StoreB mem src)); 6843 6844 ins_cost(125); 6845 format %{ "MOV8 $mem,$src" %} 6846 opcode(0x88); 6847 ins_encode( OpcP, RegMem( src, mem ) ); 6848 ins_pipe( ialu_mem_reg ); 6849 %} 6850 6851 // Store Char/Short 6852 instruct storeC(memory mem, rRegI src) %{ 6853 match(Set mem (StoreC mem src)); 6854 6855 ins_cost(125); 6856 format %{ "MOV16 $mem,$src" %} 6857 opcode(0x89, 0x66); 6858 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 6859 ins_pipe( ialu_mem_reg ); 6860 %} 6861 6862 // Store Integer 6863 instruct storeI(memory mem, rRegI src) %{ 6864 match(Set mem (StoreI mem src)); 6865 6866 ins_cost(125); 6867 format %{ "MOV $mem,$src" %} 6868 opcode(0x89); 6869 ins_encode( OpcP, RegMem( src, mem ) ); 6870 ins_pipe( ialu_mem_reg ); 6871 %} 6872 6873 // Store Long 6874 instruct storeL(long_memory mem, eRegL src) %{ 6875 predicate(!((StoreLNode*)n)->require_atomic_access()); 6876 match(Set mem (StoreL mem src)); 6877 6878 ins_cost(200); 6879 format %{ "MOV $mem,$src.lo\n\t" 6880 "MOV $mem+4,$src.hi" %} 6881 opcode(0x89, 0x89); 6882 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 6883 ins_pipe( ialu_mem_long_reg ); 6884 %} 6885 6886 // Store Long to Integer 6887 instruct storeL2I(memory mem, eRegL src) %{ 6888 match(Set mem (StoreI mem (ConvL2I src))); 6889 6890 format %{ "MOV $mem,$src.lo\t# long -> int" %} 6891 ins_encode %{ 6892 __ movl($mem$$Address, $src$$Register); 6893 %} 6894 ins_pipe(ialu_mem_reg); 6895 %} 6896 6897 // Volatile Store Long. Must be atomic, so move it into 6898 // the FP TOS and then do a 64-bit FIST. Has to probe the 6899 // target address before the store (for null-ptr checks) 6900 // so the memory operand is used twice in the encoding. 6901 instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ 6902 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); 6903 match(Set mem (StoreL mem src)); 6904 effect( KILL cr ); 6905 ins_cost(400); 6906 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6907 "FILD $src\n\t" 6908 "FISTp $mem\t # 64-bit atomic volatile long store" %} 6909 opcode(0x3B); 6910 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); 6911 ins_pipe( fpu_reg_mem ); 6912 %} 6913 6914 instruct storeLX_volatile(memory mem, stackSlotL src, regD tmp, eFlagsReg cr) %{ 6915 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 6916 match(Set mem (StoreL mem src)); 6917 effect( TEMP tmp, KILL cr ); 6918 ins_cost(380); 6919 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6920 "MOVSD $tmp,$src\n\t" 6921 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 6922 ins_encode %{ 6923 __ cmpl(rax, $mem$$Address); 6924 __ movdbl($tmp$$XMMRegister, Address(rsp, $src$$disp)); 6925 __ movdbl($mem$$Address, $tmp$$XMMRegister); 6926 %} 6927 ins_pipe( pipe_slow ); 6928 %} 6929 6930 instruct storeLX_reg_volatile(memory mem, eRegL src, regD tmp2, regD tmp, eFlagsReg cr) %{ 6931 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 6932 match(Set mem (StoreL mem src)); 6933 effect( TEMP tmp2 , TEMP tmp, KILL cr ); 6934 ins_cost(360); 6935 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6936 "MOVD $tmp,$src.lo\n\t" 6937 "MOVD $tmp2,$src.hi\n\t" 6938 "PUNPCKLDQ $tmp,$tmp2\n\t" 6939 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 6940 ins_encode %{ 6941 __ cmpl(rax, $mem$$Address); 6942 __ movdl($tmp$$XMMRegister, $src$$Register); 6943 __ movdl($tmp2$$XMMRegister, HIGH_FROM_LOW($src$$Register)); 6944 __ punpckldq($tmp$$XMMRegister, $tmp2$$XMMRegister); 6945 __ movdbl($mem$$Address, $tmp$$XMMRegister); 6946 %} 6947 ins_pipe( pipe_slow ); 6948 %} 6949 6950 // Store Pointer; for storing unknown oops and raw pointers 6951 instruct storeP(memory mem, anyRegP src) %{ 6952 match(Set mem (StoreP mem src)); 6953 6954 ins_cost(125); 6955 format %{ "MOV $mem,$src" %} 6956 opcode(0x89); 6957 ins_encode( OpcP, RegMem( src, mem ) ); 6958 ins_pipe( ialu_mem_reg ); 6959 %} 6960 6961 // Store Integer Immediate 6962 instruct storeImmI(memory mem, immI src) %{ 6963 match(Set mem (StoreI mem src)); 6964 6965 ins_cost(150); 6966 format %{ "MOV $mem,$src" %} 6967 opcode(0xC7); /* C7 /0 */ 6968 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 6969 ins_pipe( ialu_mem_imm ); 6970 %} 6971 6972 // Store Short/Char Immediate 6973 instruct storeImmI16(memory mem, immI16 src) %{ 6974 predicate(UseStoreImmI16); 6975 match(Set mem (StoreC mem src)); 6976 6977 ins_cost(150); 6978 format %{ "MOV16 $mem,$src" %} 6979 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 6980 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); 6981 ins_pipe( ialu_mem_imm ); 6982 %} 6983 6984 // Store Pointer Immediate; null pointers or constant oops that do not 6985 // need card-mark barriers. 6986 instruct storeImmP(memory mem, immP src) %{ 6987 match(Set mem (StoreP mem src)); 6988 6989 ins_cost(150); 6990 format %{ "MOV $mem,$src" %} 6991 opcode(0xC7); /* C7 /0 */ 6992 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 6993 ins_pipe( ialu_mem_imm ); 6994 %} 6995 6996 // Store Byte Immediate 6997 instruct storeImmB(memory mem, immI8 src) %{ 6998 match(Set mem (StoreB mem src)); 6999 7000 ins_cost(150); 7001 format %{ "MOV8 $mem,$src" %} 7002 opcode(0xC6); /* C6 /0 */ 7003 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7004 ins_pipe( ialu_mem_imm ); 7005 %} 7006 7007 // Store CMS card-mark Immediate 7008 instruct storeImmCM(memory mem, immI8 src) %{ 7009 match(Set mem (StoreCM mem src)); 7010 7011 ins_cost(150); 7012 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 7013 opcode(0xC6); /* C6 /0 */ 7014 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7015 ins_pipe( ialu_mem_imm ); 7016 %} 7017 7018 // Store Double 7019 instruct storeDPR( memory mem, regDPR1 src) %{ 7020 predicate(UseSSE<=1); 7021 match(Set mem (StoreD mem src)); 7022 7023 ins_cost(100); 7024 format %{ "FST_D $mem,$src" %} 7025 opcode(0xDD); /* DD /2 */ 7026 ins_encode( enc_FPR_store(mem,src) ); 7027 ins_pipe( fpu_mem_reg ); 7028 %} 7029 7030 // Store double does rounding on x86 7031 instruct storeDPR_rounded( memory mem, regDPR1 src) %{ 7032 predicate(UseSSE<=1); 7033 match(Set mem (StoreD mem (RoundDouble src))); 7034 7035 ins_cost(100); 7036 format %{ "FST_D $mem,$src\t# round" %} 7037 opcode(0xDD); /* DD /2 */ 7038 ins_encode( enc_FPR_store(mem,src) ); 7039 ins_pipe( fpu_mem_reg ); 7040 %} 7041 7042 // Store XMM register to memory (double-precision floating points) 7043 // MOVSD instruction 7044 instruct storeD(memory mem, regD src) %{ 7045 predicate(UseSSE>=2); 7046 match(Set mem (StoreD mem src)); 7047 ins_cost(95); 7048 format %{ "MOVSD $mem,$src" %} 7049 ins_encode %{ 7050 __ movdbl($mem$$Address, $src$$XMMRegister); 7051 %} 7052 ins_pipe( pipe_slow ); 7053 %} 7054 7055 // Store XMM register to memory (single-precision floating point) 7056 // MOVSS instruction 7057 instruct storeF(memory mem, regF src) %{ 7058 predicate(UseSSE>=1); 7059 match(Set mem (StoreF mem src)); 7060 ins_cost(95); 7061 format %{ "MOVSS $mem,$src" %} 7062 ins_encode %{ 7063 __ movflt($mem$$Address, $src$$XMMRegister); 7064 %} 7065 ins_pipe( pipe_slow ); 7066 %} 7067 7068 // Store Float 7069 instruct storeFPR( memory mem, regFPR1 src) %{ 7070 predicate(UseSSE==0); 7071 match(Set mem (StoreF mem src)); 7072 7073 ins_cost(100); 7074 format %{ "FST_S $mem,$src" %} 7075 opcode(0xD9); /* D9 /2 */ 7076 ins_encode( enc_FPR_store(mem,src) ); 7077 ins_pipe( fpu_mem_reg ); 7078 %} 7079 7080 // Store Float does rounding on x86 7081 instruct storeFPR_rounded( memory mem, regFPR1 src) %{ 7082 predicate(UseSSE==0); 7083 match(Set mem (StoreF mem (RoundFloat src))); 7084 7085 ins_cost(100); 7086 format %{ "FST_S $mem,$src\t# round" %} 7087 opcode(0xD9); /* D9 /2 */ 7088 ins_encode( enc_FPR_store(mem,src) ); 7089 ins_pipe( fpu_mem_reg ); 7090 %} 7091 7092 // Store Float does rounding on x86 7093 instruct storeFPR_Drounded( memory mem, regDPR1 src) %{ 7094 predicate(UseSSE<=1); 7095 match(Set mem (StoreF mem (ConvD2F src))); 7096 7097 ins_cost(100); 7098 format %{ "FST_S $mem,$src\t# D-round" %} 7099 opcode(0xD9); /* D9 /2 */ 7100 ins_encode( enc_FPR_store(mem,src) ); 7101 ins_pipe( fpu_mem_reg ); 7102 %} 7103 7104 // Store immediate Float value (it is faster than store from FPU register) 7105 // The instruction usage is guarded by predicate in operand immFPR(). 7106 instruct storeFPR_imm( memory mem, immFPR src) %{ 7107 match(Set mem (StoreF mem src)); 7108 7109 ins_cost(50); 7110 format %{ "MOV $mem,$src\t# store float" %} 7111 opcode(0xC7); /* C7 /0 */ 7112 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32FPR_as_bits( src )); 7113 ins_pipe( ialu_mem_imm ); 7114 %} 7115 7116 // Store immediate Float value (it is faster than store from XMM register) 7117 // The instruction usage is guarded by predicate in operand immF(). 7118 instruct storeF_imm( memory mem, immF src) %{ 7119 match(Set mem (StoreF mem src)); 7120 7121 ins_cost(50); 7122 format %{ "MOV $mem,$src\t# store float" %} 7123 opcode(0xC7); /* C7 /0 */ 7124 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7125 ins_pipe( ialu_mem_imm ); 7126 %} 7127 7128 // Store Integer to stack slot 7129 instruct storeSSI(stackSlotI dst, rRegI src) %{ 7130 match(Set dst src); 7131 7132 ins_cost(100); 7133 format %{ "MOV $dst,$src" %} 7134 opcode(0x89); 7135 ins_encode( OpcPRegSS( dst, src ) ); 7136 ins_pipe( ialu_mem_reg ); 7137 %} 7138 7139 // Store Integer to stack slot 7140 instruct storeSSP(stackSlotP dst, eRegP src) %{ 7141 match(Set dst src); 7142 7143 ins_cost(100); 7144 format %{ "MOV $dst,$src" %} 7145 opcode(0x89); 7146 ins_encode( OpcPRegSS( dst, src ) ); 7147 ins_pipe( ialu_mem_reg ); 7148 %} 7149 7150 // Store Long to stack slot 7151 instruct storeSSL(stackSlotL dst, eRegL src) %{ 7152 match(Set dst src); 7153 7154 ins_cost(200); 7155 format %{ "MOV $dst,$src.lo\n\t" 7156 "MOV $dst+4,$src.hi" %} 7157 opcode(0x89, 0x89); 7158 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 7159 ins_pipe( ialu_mem_long_reg ); 7160 %} 7161 7162 //----------MemBar Instructions----------------------------------------------- 7163 // Memory barrier flavors 7164 7165 instruct membar_acquire() %{ 7166 match(MemBarAcquire); 7167 ins_cost(400); 7168 7169 size(0); 7170 format %{ "MEMBAR-acquire ! (empty encoding)" %} 7171 ins_encode(); 7172 ins_pipe(empty); 7173 %} 7174 7175 instruct membar_acquire_lock() %{ 7176 match(MemBarAcquireLock); 7177 ins_cost(0); 7178 7179 size(0); 7180 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 7181 ins_encode( ); 7182 ins_pipe(empty); 7183 %} 7184 7185 instruct membar_release() %{ 7186 match(MemBarRelease); 7187 ins_cost(400); 7188 7189 size(0); 7190 format %{ "MEMBAR-release ! (empty encoding)" %} 7191 ins_encode( ); 7192 ins_pipe(empty); 7193 %} 7194 7195 instruct membar_release_lock() %{ 7196 match(MemBarReleaseLock); 7197 ins_cost(0); 7198 7199 size(0); 7200 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 7201 ins_encode( ); 7202 ins_pipe(empty); 7203 %} 7204 7205 instruct membar_volatile(eFlagsReg cr) %{ 7206 match(MemBarVolatile); 7207 effect(KILL cr); 7208 ins_cost(400); 7209 7210 format %{ 7211 $$template 7212 if (os::is_MP()) { 7213 $$emit$$"LOCK ADDL [ESP + #0], 0\t! membar_volatile" 7214 } else { 7215 $$emit$$"MEMBAR-volatile ! (empty encoding)" 7216 } 7217 %} 7218 ins_encode %{ 7219 __ membar(Assembler::StoreLoad); 7220 %} 7221 ins_pipe(pipe_slow); 7222 %} 7223 7224 instruct unnecessary_membar_volatile() %{ 7225 match(MemBarVolatile); 7226 predicate(Matcher::post_store_load_barrier(n)); 7227 ins_cost(0); 7228 7229 size(0); 7230 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 7231 ins_encode( ); 7232 ins_pipe(empty); 7233 %} 7234 7235 instruct membar_storestore() %{ 7236 match(MemBarStoreStore); 7237 ins_cost(0); 7238 7239 size(0); 7240 format %{ "MEMBAR-storestore (empty encoding)" %} 7241 ins_encode( ); 7242 ins_pipe(empty); 7243 %} 7244 7245 //----------Move Instructions-------------------------------------------------- 7246 instruct castX2P(eAXRegP dst, eAXRegI src) %{ 7247 match(Set dst (CastX2P src)); 7248 format %{ "# X2P $dst, $src" %} 7249 ins_encode( /*empty encoding*/ ); 7250 ins_cost(0); 7251 ins_pipe(empty); 7252 %} 7253 7254 instruct castP2X(rRegI dst, eRegP src ) %{ 7255 match(Set dst (CastP2X src)); 7256 ins_cost(50); 7257 format %{ "MOV $dst, $src\t# CastP2X" %} 7258 ins_encode( enc_Copy( dst, src) ); 7259 ins_pipe( ialu_reg_reg ); 7260 %} 7261 7262 //----------Conditional Move--------------------------------------------------- 7263 // Conditional move 7264 instruct jmovI_reg(cmpOp cop, eFlagsReg cr, rRegI dst, rRegI src) %{ 7265 predicate(!VM_Version::supports_cmov() ); 7266 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7267 ins_cost(200); 7268 format %{ "J$cop,us skip\t# signed cmove\n\t" 7269 "MOV $dst,$src\n" 7270 "skip:" %} 7271 ins_encode %{ 7272 Label Lskip; 7273 // Invert sense of branch from sense of CMOV 7274 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7275 __ movl($dst$$Register, $src$$Register); 7276 __ bind(Lskip); 7277 %} 7278 ins_pipe( pipe_cmov_reg ); 7279 %} 7280 7281 instruct jmovI_regU(cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src) %{ 7282 predicate(!VM_Version::supports_cmov() ); 7283 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7284 ins_cost(200); 7285 format %{ "J$cop,us skip\t# unsigned cmove\n\t" 7286 "MOV $dst,$src\n" 7287 "skip:" %} 7288 ins_encode %{ 7289 Label Lskip; 7290 // Invert sense of branch from sense of CMOV 7291 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip); 7292 __ movl($dst$$Register, $src$$Register); 7293 __ bind(Lskip); 7294 %} 7295 ins_pipe( pipe_cmov_reg ); 7296 %} 7297 7298 instruct cmovI_reg(rRegI dst, rRegI src, eFlagsReg cr, cmpOp cop ) %{ 7299 predicate(VM_Version::supports_cmov() ); 7300 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7301 ins_cost(200); 7302 format %{ "CMOV$cop $dst,$src" %} 7303 opcode(0x0F,0x40); 7304 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7305 ins_pipe( pipe_cmov_reg ); 7306 %} 7307 7308 instruct cmovI_regU( cmpOpU cop, eFlagsRegU cr, rRegI dst, rRegI src ) %{ 7309 predicate(VM_Version::supports_cmov() ); 7310 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7311 ins_cost(200); 7312 format %{ "CMOV$cop $dst,$src" %} 7313 opcode(0x0F,0x40); 7314 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7315 ins_pipe( pipe_cmov_reg ); 7316 %} 7317 7318 instruct cmovI_regUCF( cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, rRegI src ) %{ 7319 predicate(VM_Version::supports_cmov() ); 7320 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7321 ins_cost(200); 7322 expand %{ 7323 cmovI_regU(cop, cr, dst, src); 7324 %} 7325 %} 7326 7327 // Conditional move 7328 instruct cmovI_mem(cmpOp cop, eFlagsReg cr, rRegI dst, memory src) %{ 7329 predicate(VM_Version::supports_cmov() ); 7330 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7331 ins_cost(250); 7332 format %{ "CMOV$cop $dst,$src" %} 7333 opcode(0x0F,0x40); 7334 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7335 ins_pipe( pipe_cmov_mem ); 7336 %} 7337 7338 // Conditional move 7339 instruct cmovI_memU(cmpOpU cop, eFlagsRegU cr, rRegI dst, memory src) %{ 7340 predicate(VM_Version::supports_cmov() ); 7341 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7342 ins_cost(250); 7343 format %{ "CMOV$cop $dst,$src" %} 7344 opcode(0x0F,0x40); 7345 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7346 ins_pipe( pipe_cmov_mem ); 7347 %} 7348 7349 instruct cmovI_memUCF(cmpOpUCF cop, eFlagsRegUCF cr, rRegI dst, memory src) %{ 7350 predicate(VM_Version::supports_cmov() ); 7351 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7352 ins_cost(250); 7353 expand %{ 7354 cmovI_memU(cop, cr, dst, src); 7355 %} 7356 %} 7357 7358 // Conditional move 7359 instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7360 predicate(VM_Version::supports_cmov() ); 7361 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7362 ins_cost(200); 7363 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7364 opcode(0x0F,0x40); 7365 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7366 ins_pipe( pipe_cmov_reg ); 7367 %} 7368 7369 // Conditional move (non-P6 version) 7370 // Note: a CMoveP is generated for stubs and native wrappers 7371 // regardless of whether we are on a P6, so we 7372 // emulate a cmov here 7373 instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7374 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7375 ins_cost(300); 7376 format %{ "Jn$cop skip\n\t" 7377 "MOV $dst,$src\t# pointer\n" 7378 "skip:" %} 7379 opcode(0x8b); 7380 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); 7381 ins_pipe( pipe_cmov_reg ); 7382 %} 7383 7384 // Conditional move 7385 instruct cmovP_regU(cmpOpU cop, eFlagsRegU cr, eRegP dst, eRegP src ) %{ 7386 predicate(VM_Version::supports_cmov() ); 7387 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7388 ins_cost(200); 7389 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7390 opcode(0x0F,0x40); 7391 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7392 ins_pipe( pipe_cmov_reg ); 7393 %} 7394 7395 instruct cmovP_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegP dst, eRegP src ) %{ 7396 predicate(VM_Version::supports_cmov() ); 7397 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7398 ins_cost(200); 7399 expand %{ 7400 cmovP_regU(cop, cr, dst, src); 7401 %} 7402 %} 7403 7404 // DISABLED: Requires the ADLC to emit a bottom_type call that 7405 // correctly meets the two pointer arguments; one is an incoming 7406 // register but the other is a memory operand. ALSO appears to 7407 // be buggy with implicit null checks. 7408 // 7409 //// Conditional move 7410 //instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ 7411 // predicate(VM_Version::supports_cmov() ); 7412 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7413 // ins_cost(250); 7414 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 7415 // opcode(0x0F,0x40); 7416 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7417 // ins_pipe( pipe_cmov_mem ); 7418 //%} 7419 // 7420 //// Conditional move 7421 //instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ 7422 // predicate(VM_Version::supports_cmov() ); 7423 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7424 // ins_cost(250); 7425 // format %{ "CMOV$cop $dst,$src\t# ptr" %} 7426 // opcode(0x0F,0x40); 7427 // ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7428 // ins_pipe( pipe_cmov_mem ); 7429 //%} 7430 7431 // Conditional move 7432 instruct fcmovDPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regDPR src) %{ 7433 predicate(UseSSE<=1); 7434 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7435 ins_cost(200); 7436 format %{ "FCMOV$cop $dst,$src\t# double" %} 7437 opcode(0xDA); 7438 ins_encode( enc_cmov_dpr(cop,src) ); 7439 ins_pipe( pipe_cmovDPR_reg ); 7440 %} 7441 7442 // Conditional move 7443 instruct fcmovFPR_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regFPR src) %{ 7444 predicate(UseSSE==0); 7445 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7446 ins_cost(200); 7447 format %{ "FCMOV$cop $dst,$src\t# float" %} 7448 opcode(0xDA); 7449 ins_encode( enc_cmov_dpr(cop,src) ); 7450 ins_pipe( pipe_cmovDPR_reg ); 7451 %} 7452 7453 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7454 instruct fcmovDPR_regS(cmpOp cop, eFlagsReg cr, regDPR dst, regDPR src) %{ 7455 predicate(UseSSE<=1); 7456 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7457 ins_cost(200); 7458 format %{ "Jn$cop skip\n\t" 7459 "MOV $dst,$src\t# double\n" 7460 "skip:" %} 7461 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7462 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_DPR(src), OpcP, RegOpc(dst) ); 7463 ins_pipe( pipe_cmovDPR_reg ); 7464 %} 7465 7466 // Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7467 instruct fcmovFPR_regS(cmpOp cop, eFlagsReg cr, regFPR dst, regFPR src) %{ 7468 predicate(UseSSE==0); 7469 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7470 ins_cost(200); 7471 format %{ "Jn$cop skip\n\t" 7472 "MOV $dst,$src\t# float\n" 7473 "skip:" %} 7474 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7475 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_FPR(src), OpcP, RegOpc(dst) ); 7476 ins_pipe( pipe_cmovDPR_reg ); 7477 %} 7478 7479 // No CMOVE with SSE/SSE2 7480 instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ 7481 predicate (UseSSE>=1); 7482 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7483 ins_cost(200); 7484 format %{ "Jn$cop skip\n\t" 7485 "MOVSS $dst,$src\t# float\n" 7486 "skip:" %} 7487 ins_encode %{ 7488 Label skip; 7489 // Invert sense of branch from sense of CMOV 7490 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7491 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7492 __ bind(skip); 7493 %} 7494 ins_pipe( pipe_slow ); 7495 %} 7496 7497 // No CMOVE with SSE/SSE2 7498 instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ 7499 predicate (UseSSE>=2); 7500 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7501 ins_cost(200); 7502 format %{ "Jn$cop skip\n\t" 7503 "MOVSD $dst,$src\t# float\n" 7504 "skip:" %} 7505 ins_encode %{ 7506 Label skip; 7507 // Invert sense of branch from sense of CMOV 7508 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7509 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7510 __ bind(skip); 7511 %} 7512 ins_pipe( pipe_slow ); 7513 %} 7514 7515 // unsigned version 7516 instruct fcmovF_regU(cmpOpU cop, eFlagsRegU cr, regF dst, regF src) %{ 7517 predicate (UseSSE>=1); 7518 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7519 ins_cost(200); 7520 format %{ "Jn$cop skip\n\t" 7521 "MOVSS $dst,$src\t# float\n" 7522 "skip:" %} 7523 ins_encode %{ 7524 Label skip; 7525 // Invert sense of branch from sense of CMOV 7526 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7527 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7528 __ bind(skip); 7529 %} 7530 ins_pipe( pipe_slow ); 7531 %} 7532 7533 instruct fcmovF_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regF dst, regF src) %{ 7534 predicate (UseSSE>=1); 7535 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7536 ins_cost(200); 7537 expand %{ 7538 fcmovF_regU(cop, cr, dst, src); 7539 %} 7540 %} 7541 7542 // unsigned version 7543 instruct fcmovD_regU(cmpOpU cop, eFlagsRegU cr, regD dst, regD src) %{ 7544 predicate (UseSSE>=2); 7545 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7546 ins_cost(200); 7547 format %{ "Jn$cop skip\n\t" 7548 "MOVSD $dst,$src\t# float\n" 7549 "skip:" %} 7550 ins_encode %{ 7551 Label skip; 7552 // Invert sense of branch from sense of CMOV 7553 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7554 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7555 __ bind(skip); 7556 %} 7557 ins_pipe( pipe_slow ); 7558 %} 7559 7560 instruct fcmovD_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, regD dst, regD src) %{ 7561 predicate (UseSSE>=2); 7562 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7563 ins_cost(200); 7564 expand %{ 7565 fcmovD_regU(cop, cr, dst, src); 7566 %} 7567 %} 7568 7569 instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ 7570 predicate(VM_Version::supports_cmov() ); 7571 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7572 ins_cost(200); 7573 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7574 "CMOV$cop $dst.hi,$src.hi" %} 7575 opcode(0x0F,0x40); 7576 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7577 ins_pipe( pipe_cmov_reg_long ); 7578 %} 7579 7580 instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ 7581 predicate(VM_Version::supports_cmov() ); 7582 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7583 ins_cost(200); 7584 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7585 "CMOV$cop $dst.hi,$src.hi" %} 7586 opcode(0x0F,0x40); 7587 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7588 ins_pipe( pipe_cmov_reg_long ); 7589 %} 7590 7591 instruct cmovL_regUCF(cmpOpUCF cop, eFlagsRegUCF cr, eRegL dst, eRegL src) %{ 7592 predicate(VM_Version::supports_cmov() ); 7593 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7594 ins_cost(200); 7595 expand %{ 7596 cmovL_regU(cop, cr, dst, src); 7597 %} 7598 %} 7599 7600 //----------Arithmetic Instructions-------------------------------------------- 7601 //----------Addition Instructions---------------------------------------------- 7602 // Integer Addition Instructions 7603 instruct addI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7604 match(Set dst (AddI dst src)); 7605 effect(KILL cr); 7606 7607 size(2); 7608 format %{ "ADD $dst,$src" %} 7609 opcode(0x03); 7610 ins_encode( OpcP, RegReg( dst, src) ); 7611 ins_pipe( ialu_reg_reg ); 7612 %} 7613 7614 instruct addI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ 7615 match(Set dst (AddI dst src)); 7616 effect(KILL cr); 7617 7618 format %{ "ADD $dst,$src" %} 7619 opcode(0x81, 0x00); /* /0 id */ 7620 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7621 ins_pipe( ialu_reg ); 7622 %} 7623 7624 instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ 7625 predicate(UseIncDec); 7626 match(Set dst (AddI dst src)); 7627 effect(KILL cr); 7628 7629 size(1); 7630 format %{ "INC $dst" %} 7631 opcode(0x40); /* */ 7632 ins_encode( Opc_plus( primary, dst ) ); 7633 ins_pipe( ialu_reg ); 7634 %} 7635 7636 instruct leaI_eReg_immI(rRegI dst, rRegI src0, immI src1) %{ 7637 match(Set dst (AddI src0 src1)); 7638 ins_cost(110); 7639 7640 format %{ "LEA $dst,[$src0 + $src1]" %} 7641 opcode(0x8D); /* 0x8D /r */ 7642 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7643 ins_pipe( ialu_reg_reg ); 7644 %} 7645 7646 instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ 7647 match(Set dst (AddP src0 src1)); 7648 ins_cost(110); 7649 7650 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} 7651 opcode(0x8D); /* 0x8D /r */ 7652 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7653 ins_pipe( ialu_reg_reg ); 7654 %} 7655 7656 instruct decI_eReg(rRegI dst, immI_M1 src, eFlagsReg cr) %{ 7657 predicate(UseIncDec); 7658 match(Set dst (AddI dst src)); 7659 effect(KILL cr); 7660 7661 size(1); 7662 format %{ "DEC $dst" %} 7663 opcode(0x48); /* */ 7664 ins_encode( Opc_plus( primary, dst ) ); 7665 ins_pipe( ialu_reg ); 7666 %} 7667 7668 instruct addP_eReg(eRegP dst, rRegI src, eFlagsReg cr) %{ 7669 match(Set dst (AddP dst src)); 7670 effect(KILL cr); 7671 7672 size(2); 7673 format %{ "ADD $dst,$src" %} 7674 opcode(0x03); 7675 ins_encode( OpcP, RegReg( dst, src) ); 7676 ins_pipe( ialu_reg_reg ); 7677 %} 7678 7679 instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ 7680 match(Set dst (AddP dst src)); 7681 effect(KILL cr); 7682 7683 format %{ "ADD $dst,$src" %} 7684 opcode(0x81,0x00); /* Opcode 81 /0 id */ 7685 // ins_encode( RegImm( dst, src) ); 7686 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7687 ins_pipe( ialu_reg ); 7688 %} 7689 7690 instruct addI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ 7691 match(Set dst (AddI dst (LoadI src))); 7692 effect(KILL cr); 7693 7694 ins_cost(125); 7695 format %{ "ADD $dst,$src" %} 7696 opcode(0x03); 7697 ins_encode( OpcP, RegMem( dst, src) ); 7698 ins_pipe( ialu_reg_mem ); 7699 %} 7700 7701 instruct addI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ 7702 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7703 effect(KILL cr); 7704 7705 ins_cost(150); 7706 format %{ "ADD $dst,$src" %} 7707 opcode(0x01); /* Opcode 01 /r */ 7708 ins_encode( OpcP, RegMem( src, dst ) ); 7709 ins_pipe( ialu_mem_reg ); 7710 %} 7711 7712 // Add Memory with Immediate 7713 instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 7714 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7715 effect(KILL cr); 7716 7717 ins_cost(125); 7718 format %{ "ADD $dst,$src" %} 7719 opcode(0x81); /* Opcode 81 /0 id */ 7720 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); 7721 ins_pipe( ialu_mem_imm ); 7722 %} 7723 7724 instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ 7725 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7726 effect(KILL cr); 7727 7728 ins_cost(125); 7729 format %{ "INC $dst" %} 7730 opcode(0xFF); /* Opcode FF /0 */ 7731 ins_encode( OpcP, RMopc_Mem(0x00,dst)); 7732 ins_pipe( ialu_mem_imm ); 7733 %} 7734 7735 instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ 7736 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7737 effect(KILL cr); 7738 7739 ins_cost(125); 7740 format %{ "DEC $dst" %} 7741 opcode(0xFF); /* Opcode FF /1 */ 7742 ins_encode( OpcP, RMopc_Mem(0x01,dst)); 7743 ins_pipe( ialu_mem_imm ); 7744 %} 7745 7746 7747 instruct checkCastPP( eRegP dst ) %{ 7748 match(Set dst (CheckCastPP dst)); 7749 7750 size(0); 7751 format %{ "#checkcastPP of $dst" %} 7752 ins_encode( /*empty encoding*/ ); 7753 ins_pipe( empty ); 7754 %} 7755 7756 instruct castPP( eRegP dst ) %{ 7757 match(Set dst (CastPP dst)); 7758 format %{ "#castPP of $dst" %} 7759 ins_encode( /*empty encoding*/ ); 7760 ins_pipe( empty ); 7761 %} 7762 7763 instruct castII( rRegI dst ) %{ 7764 match(Set dst (CastII dst)); 7765 format %{ "#castII of $dst" %} 7766 ins_encode( /*empty encoding*/ ); 7767 ins_cost(0); 7768 ins_pipe( empty ); 7769 %} 7770 7771 7772 // Load-locked - same as a regular pointer load when used with compare-swap 7773 instruct loadPLocked(eRegP dst, memory mem) %{ 7774 match(Set dst (LoadPLocked mem)); 7775 7776 ins_cost(125); 7777 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 7778 opcode(0x8B); 7779 ins_encode( OpcP, RegMem(dst,mem)); 7780 ins_pipe( ialu_reg_mem ); 7781 %} 7782 7783 // Conditional-store of the updated heap-top. 7784 // Used during allocation of the shared heap. 7785 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7786 instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ 7787 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 7788 // EAX is killed if there is contention, but then it's also unused. 7789 // In the common case of no contention, EAX holds the new oop address. 7790 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} 7791 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); 7792 ins_pipe( pipe_cmpxchg ); 7793 %} 7794 7795 // Conditional-store of an int value. 7796 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG on Intel. 7797 instruct storeIConditional( memory mem, eAXRegI oldval, rRegI newval, eFlagsReg cr ) %{ 7798 match(Set cr (StoreIConditional mem (Binary oldval newval))); 7799 effect(KILL oldval); 7800 format %{ "CMPXCHG $mem,$newval\t# If EAX==$mem Then store $newval into $mem" %} 7801 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval, mem) ); 7802 ins_pipe( pipe_cmpxchg ); 7803 %} 7804 7805 // Conditional-store of a long value. 7806 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. 7807 instruct storeLConditional( memory mem, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7808 match(Set cr (StoreLConditional mem (Binary oldval newval))); 7809 effect(KILL oldval); 7810 format %{ "XCHG EBX,ECX\t# correct order for CMPXCHG8 instruction\n\t" 7811 "CMPXCHG8 $mem,ECX:EBX\t# If EDX:EAX==$mem Then store ECX:EBX into $mem\n\t" 7812 "XCHG EBX,ECX" 7813 %} 7814 ins_encode %{ 7815 // Note: we need to swap rbx, and rcx before and after the 7816 // cmpxchg8 instruction because the instruction uses 7817 // rcx as the high order word of the new value to store but 7818 // our register encoding uses rbx. 7819 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 7820 if( os::is_MP() ) 7821 __ lock(); 7822 __ cmpxchg8($mem$$Address); 7823 __ xchgl(as_Register(EBX_enc), as_Register(ECX_enc)); 7824 %} 7825 ins_pipe( pipe_cmpxchg ); 7826 %} 7827 7828 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7829 7830 instruct compareAndSwapL( rRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7831 predicate(VM_Version::supports_cx8()); 7832 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7833 effect(KILL cr, KILL oldval); 7834 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7835 "MOV $res,0\n\t" 7836 "JNE,s fail\n\t" 7837 "MOV $res,1\n" 7838 "fail:" %} 7839 ins_encode( enc_cmpxchg8(mem_ptr), 7840 enc_flags_ne_to_boolean(res) ); 7841 ins_pipe( pipe_cmpxchg ); 7842 %} 7843 7844 instruct compareAndSwapP( rRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 7845 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7846 effect(KILL cr, KILL oldval); 7847 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7848 "MOV $res,0\n\t" 7849 "JNE,s fail\n\t" 7850 "MOV $res,1\n" 7851 "fail:" %} 7852 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7853 ins_pipe( pipe_cmpxchg ); 7854 %} 7855 7856 instruct compareAndSwapI( rRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 7857 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7858 effect(KILL cr, KILL oldval); 7859 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7860 "MOV $res,0\n\t" 7861 "JNE,s fail\n\t" 7862 "MOV $res,1\n" 7863 "fail:" %} 7864 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7865 ins_pipe( pipe_cmpxchg ); 7866 %} 7867 7868 instruct xaddI_no_res( memory mem, Universe dummy, immI add, eFlagsReg cr) %{ 7869 predicate(n->as_LoadStore()->result_not_used()); 7870 match(Set dummy (GetAndAddI mem add)); 7871 effect(KILL cr); 7872 format %{ "ADDL [$mem],$add" %} 7873 ins_encode %{ 7874 if (os::is_MP()) { __ lock(); } 7875 __ addl($mem$$Address, $add$$constant); 7876 %} 7877 ins_pipe( pipe_cmpxchg ); 7878 %} 7879 7880 instruct xaddI( memory mem, rRegI newval, eFlagsReg cr) %{ 7881 match(Set newval (GetAndAddI mem newval)); 7882 effect(KILL cr); 7883 format %{ "XADDL [$mem],$newval" %} 7884 ins_encode %{ 7885 if (os::is_MP()) { __ lock(); } 7886 __ xaddl($mem$$Address, $newval$$Register); 7887 %} 7888 ins_pipe( pipe_cmpxchg ); 7889 %} 7890 7891 instruct xchgI( memory mem, rRegI newval) %{ 7892 match(Set newval (GetAndSetI mem newval)); 7893 format %{ "XCHGL $newval,[$mem]" %} 7894 ins_encode %{ 7895 __ xchgl($newval$$Register, $mem$$Address); 7896 %} 7897 ins_pipe( pipe_cmpxchg ); 7898 %} 7899 7900 instruct xchgP( memory mem, pRegP newval) %{ 7901 match(Set newval (GetAndSetP mem newval)); 7902 format %{ "XCHGL $newval,[$mem]" %} 7903 ins_encode %{ 7904 __ xchgl($newval$$Register, $mem$$Address); 7905 %} 7906 ins_pipe( pipe_cmpxchg ); 7907 %} 7908 7909 //----------Subtraction Instructions------------------------------------------- 7910 // Integer Subtraction Instructions 7911 instruct subI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7912 match(Set dst (SubI dst src)); 7913 effect(KILL cr); 7914 7915 size(2); 7916 format %{ "SUB $dst,$src" %} 7917 opcode(0x2B); 7918 ins_encode( OpcP, RegReg( dst, src) ); 7919 ins_pipe( ialu_reg_reg ); 7920 %} 7921 7922 instruct subI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ 7923 match(Set dst (SubI dst src)); 7924 effect(KILL cr); 7925 7926 format %{ "SUB $dst,$src" %} 7927 opcode(0x81,0x05); /* Opcode 81 /5 */ 7928 // ins_encode( RegImm( dst, src) ); 7929 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7930 ins_pipe( ialu_reg ); 7931 %} 7932 7933 instruct subI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ 7934 match(Set dst (SubI dst (LoadI src))); 7935 effect(KILL cr); 7936 7937 ins_cost(125); 7938 format %{ "SUB $dst,$src" %} 7939 opcode(0x2B); 7940 ins_encode( OpcP, RegMem( dst, src) ); 7941 ins_pipe( ialu_reg_mem ); 7942 %} 7943 7944 instruct subI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ 7945 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 7946 effect(KILL cr); 7947 7948 ins_cost(150); 7949 format %{ "SUB $dst,$src" %} 7950 opcode(0x29); /* Opcode 29 /r */ 7951 ins_encode( OpcP, RegMem( src, dst ) ); 7952 ins_pipe( ialu_mem_reg ); 7953 %} 7954 7955 // Subtract from a pointer 7956 instruct subP_eReg(eRegP dst, rRegI src, immI0 zero, eFlagsReg cr) %{ 7957 match(Set dst (AddP dst (SubI zero src))); 7958 effect(KILL cr); 7959 7960 size(2); 7961 format %{ "SUB $dst,$src" %} 7962 opcode(0x2B); 7963 ins_encode( OpcP, RegReg( dst, src) ); 7964 ins_pipe( ialu_reg_reg ); 7965 %} 7966 7967 instruct negI_eReg(rRegI dst, immI0 zero, eFlagsReg cr) %{ 7968 match(Set dst (SubI zero dst)); 7969 effect(KILL cr); 7970 7971 size(2); 7972 format %{ "NEG $dst" %} 7973 opcode(0xF7,0x03); // Opcode F7 /3 7974 ins_encode( OpcP, RegOpc( dst ) ); 7975 ins_pipe( ialu_reg ); 7976 %} 7977 7978 7979 //----------Multiplication/Division Instructions------------------------------- 7980 // Integer Multiplication Instructions 7981 // Multiply Register 7982 instruct mulI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 7983 match(Set dst (MulI dst src)); 7984 effect(KILL cr); 7985 7986 size(3); 7987 ins_cost(300); 7988 format %{ "IMUL $dst,$src" %} 7989 opcode(0xAF, 0x0F); 7990 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 7991 ins_pipe( ialu_reg_reg_alu0 ); 7992 %} 7993 7994 // Multiply 32-bit Immediate 7995 instruct mulI_eReg_imm(rRegI dst, rRegI src, immI imm, eFlagsReg cr) %{ 7996 match(Set dst (MulI src imm)); 7997 effect(KILL cr); 7998 7999 ins_cost(300); 8000 format %{ "IMUL $dst,$src,$imm" %} 8001 opcode(0x69); /* 69 /r id */ 8002 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); 8003 ins_pipe( ialu_reg_reg_alu0 ); 8004 %} 8005 8006 instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ 8007 match(Set dst src); 8008 effect(KILL cr); 8009 8010 // Note that this is artificially increased to make it more expensive than loadConL 8011 ins_cost(250); 8012 format %{ "MOV EAX,$src\t// low word only" %} 8013 opcode(0xB8); 8014 ins_encode( LdImmL_Lo(dst, src) ); 8015 ins_pipe( ialu_reg_fat ); 8016 %} 8017 8018 // Multiply by 32-bit Immediate, taking the shifted high order results 8019 // (special case for shift by 32) 8020 instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ 8021 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8022 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8023 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8024 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8025 effect(USE src1, KILL cr); 8026 8027 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8028 ins_cost(0*100 + 1*400 - 150); 8029 format %{ "IMUL EDX:EAX,$src1" %} 8030 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8031 ins_pipe( pipe_slow ); 8032 %} 8033 8034 // Multiply by 32-bit Immediate, taking the shifted high order results 8035 instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ 8036 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8037 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8038 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8039 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8040 effect(USE src1, KILL cr); 8041 8042 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8043 ins_cost(1*100 + 1*400 - 150); 8044 format %{ "IMUL EDX:EAX,$src1\n\t" 8045 "SAR EDX,$cnt-32" %} 8046 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8047 ins_pipe( pipe_slow ); 8048 %} 8049 8050 // Multiply Memory 32-bit Immediate 8051 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, eFlagsReg cr) %{ 8052 match(Set dst (MulI (LoadI src) imm)); 8053 effect(KILL cr); 8054 8055 ins_cost(300); 8056 format %{ "IMUL $dst,$src,$imm" %} 8057 opcode(0x69); /* 69 /r id */ 8058 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 8059 ins_pipe( ialu_reg_mem_alu0 ); 8060 %} 8061 8062 // Multiply Memory 8063 instruct mulI(rRegI dst, memory src, eFlagsReg cr) %{ 8064 match(Set dst (MulI dst (LoadI src))); 8065 effect(KILL cr); 8066 8067 ins_cost(350); 8068 format %{ "IMUL $dst,$src" %} 8069 opcode(0xAF, 0x0F); 8070 ins_encode( OpcS, OpcP, RegMem( dst, src) ); 8071 ins_pipe( ialu_reg_mem_alu0 ); 8072 %} 8073 8074 // Multiply Register Int to Long 8075 instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ 8076 // Basic Idea: long = (long)int * (long)int 8077 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); 8078 effect(DEF dst, USE src, USE src1, KILL flags); 8079 8080 ins_cost(300); 8081 format %{ "IMUL $dst,$src1" %} 8082 8083 ins_encode( long_int_multiply( dst, src1 ) ); 8084 ins_pipe( ialu_reg_reg_alu0 ); 8085 %} 8086 8087 instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ 8088 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 8089 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); 8090 effect(KILL flags); 8091 8092 ins_cost(300); 8093 format %{ "MUL $dst,$src1" %} 8094 8095 ins_encode( long_uint_multiply(dst, src1) ); 8096 ins_pipe( ialu_reg_reg_alu0 ); 8097 %} 8098 8099 // Multiply Register Long 8100 instruct mulL_eReg(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ 8101 match(Set dst (MulL dst src)); 8102 effect(KILL cr, TEMP tmp); 8103 ins_cost(4*100+3*400); 8104 // Basic idea: lo(result) = lo(x_lo * y_lo) 8105 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 8106 format %{ "MOV $tmp,$src.lo\n\t" 8107 "IMUL $tmp,EDX\n\t" 8108 "MOV EDX,$src.hi\n\t" 8109 "IMUL EDX,EAX\n\t" 8110 "ADD $tmp,EDX\n\t" 8111 "MUL EDX:EAX,$src.lo\n\t" 8112 "ADD EDX,$tmp" %} 8113 ins_encode( long_multiply( dst, src, tmp ) ); 8114 ins_pipe( pipe_slow ); 8115 %} 8116 8117 // Multiply Register Long where the left operand's high 32 bits are zero 8118 instruct mulL_eReg_lhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ 8119 predicate(is_operand_hi32_zero(n->in(1))); 8120 match(Set dst (MulL dst src)); 8121 effect(KILL cr, TEMP tmp); 8122 ins_cost(2*100+2*400); 8123 // Basic idea: lo(result) = lo(x_lo * y_lo) 8124 // hi(result) = hi(x_lo * y_lo) + lo(x_lo * y_hi) where lo(x_hi * y_lo) = 0 because x_hi = 0 8125 format %{ "MOV $tmp,$src.hi\n\t" 8126 "IMUL $tmp,EAX\n\t" 8127 "MUL EDX:EAX,$src.lo\n\t" 8128 "ADD EDX,$tmp" %} 8129 ins_encode %{ 8130 __ movl($tmp$$Register, HIGH_FROM_LOW($src$$Register)); 8131 __ imull($tmp$$Register, rax); 8132 __ mull($src$$Register); 8133 __ addl(rdx, $tmp$$Register); 8134 %} 8135 ins_pipe( pipe_slow ); 8136 %} 8137 8138 // Multiply Register Long where the right operand's high 32 bits are zero 8139 instruct mulL_eReg_rhi0(eADXRegL dst, eRegL src, rRegI tmp, eFlagsReg cr) %{ 8140 predicate(is_operand_hi32_zero(n->in(2))); 8141 match(Set dst (MulL dst src)); 8142 effect(KILL cr, TEMP tmp); 8143 ins_cost(2*100+2*400); 8144 // Basic idea: lo(result) = lo(x_lo * y_lo) 8145 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) where lo(x_lo * y_hi) = 0 because y_hi = 0 8146 format %{ "MOV $tmp,$src.lo\n\t" 8147 "IMUL $tmp,EDX\n\t" 8148 "MUL EDX:EAX,$src.lo\n\t" 8149 "ADD EDX,$tmp" %} 8150 ins_encode %{ 8151 __ movl($tmp$$Register, $src$$Register); 8152 __ imull($tmp$$Register, rdx); 8153 __ mull($src$$Register); 8154 __ addl(rdx, $tmp$$Register); 8155 %} 8156 ins_pipe( pipe_slow ); 8157 %} 8158 8159 // Multiply Register Long where the left and the right operands' high 32 bits are zero 8160 instruct mulL_eReg_hi0(eADXRegL dst, eRegL src, eFlagsReg cr) %{ 8161 predicate(is_operand_hi32_zero(n->in(1)) && is_operand_hi32_zero(n->in(2))); 8162 match(Set dst (MulL dst src)); 8163 effect(KILL cr); 8164 ins_cost(1*400); 8165 // Basic idea: lo(result) = lo(x_lo * y_lo) 8166 // hi(result) = hi(x_lo * y_lo) where lo(x_hi * y_lo) = 0 and lo(x_lo * y_hi) = 0 because x_hi = 0 and y_hi = 0 8167 format %{ "MUL EDX:EAX,$src.lo\n\t" %} 8168 ins_encode %{ 8169 __ mull($src$$Register); 8170 %} 8171 ins_pipe( pipe_slow ); 8172 %} 8173 8174 // Multiply Register Long by small constant 8175 instruct mulL_eReg_con(eADXRegL dst, immL_127 src, rRegI tmp, eFlagsReg cr) %{ 8176 match(Set dst (MulL dst src)); 8177 effect(KILL cr, TEMP tmp); 8178 ins_cost(2*100+2*400); 8179 size(12); 8180 // Basic idea: lo(result) = lo(src * EAX) 8181 // hi(result) = hi(src * EAX) + lo(src * EDX) 8182 format %{ "IMUL $tmp,EDX,$src\n\t" 8183 "MOV EDX,$src\n\t" 8184 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8185 "ADD EDX,$tmp" %} 8186 ins_encode( long_multiply_con( dst, src, tmp ) ); 8187 ins_pipe( pipe_slow ); 8188 %} 8189 8190 // Integer DIV with Register 8191 instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8192 match(Set rax (DivI rax div)); 8193 effect(KILL rdx, KILL cr); 8194 size(26); 8195 ins_cost(30*100+10*100); 8196 format %{ "CMP EAX,0x80000000\n\t" 8197 "JNE,s normal\n\t" 8198 "XOR EDX,EDX\n\t" 8199 "CMP ECX,-1\n\t" 8200 "JE,s done\n" 8201 "normal: CDQ\n\t" 8202 "IDIV $div\n\t" 8203 "done:" %} 8204 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8205 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8206 ins_pipe( ialu_reg_reg_alu0 ); 8207 %} 8208 8209 // Divide Register Long 8210 instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8211 match(Set dst (DivL src1 src2)); 8212 effect( KILL cr, KILL cx, KILL bx ); 8213 ins_cost(10000); 8214 format %{ "PUSH $src1.hi\n\t" 8215 "PUSH $src1.lo\n\t" 8216 "PUSH $src2.hi\n\t" 8217 "PUSH $src2.lo\n\t" 8218 "CALL SharedRuntime::ldiv\n\t" 8219 "ADD ESP,16" %} 8220 ins_encode( long_div(src1,src2) ); 8221 ins_pipe( pipe_slow ); 8222 %} 8223 8224 // Integer DIVMOD with Register, both quotient and mod results 8225 instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8226 match(DivModI rax div); 8227 effect(KILL cr); 8228 size(26); 8229 ins_cost(30*100+10*100); 8230 format %{ "CMP EAX,0x80000000\n\t" 8231 "JNE,s normal\n\t" 8232 "XOR EDX,EDX\n\t" 8233 "CMP ECX,-1\n\t" 8234 "JE,s done\n" 8235 "normal: CDQ\n\t" 8236 "IDIV $div\n\t" 8237 "done:" %} 8238 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8239 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8240 ins_pipe( pipe_slow ); 8241 %} 8242 8243 // Integer MOD with Register 8244 instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ 8245 match(Set rdx (ModI rax div)); 8246 effect(KILL rax, KILL cr); 8247 8248 size(26); 8249 ins_cost(300); 8250 format %{ "CDQ\n\t" 8251 "IDIV $div" %} 8252 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8253 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8254 ins_pipe( ialu_reg_reg_alu0 ); 8255 %} 8256 8257 // Remainder Register Long 8258 instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8259 match(Set dst (ModL src1 src2)); 8260 effect( KILL cr, KILL cx, KILL bx ); 8261 ins_cost(10000); 8262 format %{ "PUSH $src1.hi\n\t" 8263 "PUSH $src1.lo\n\t" 8264 "PUSH $src2.hi\n\t" 8265 "PUSH $src2.lo\n\t" 8266 "CALL SharedRuntime::lrem\n\t" 8267 "ADD ESP,16" %} 8268 ins_encode( long_mod(src1,src2) ); 8269 ins_pipe( pipe_slow ); 8270 %} 8271 8272 // Divide Register Long (no special case since divisor != -1) 8273 instruct divL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ 8274 match(Set dst (DivL dst imm)); 8275 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8276 ins_cost(1000); 8277 format %{ "MOV $tmp,abs($imm) # ldiv EDX:EAX,$imm\n\t" 8278 "XOR $tmp2,$tmp2\n\t" 8279 "CMP $tmp,EDX\n\t" 8280 "JA,s fast\n\t" 8281 "MOV $tmp2,EAX\n\t" 8282 "MOV EAX,EDX\n\t" 8283 "MOV EDX,0\n\t" 8284 "JLE,s pos\n\t" 8285 "LNEG EAX : $tmp2\n\t" 8286 "DIV $tmp # unsigned division\n\t" 8287 "XCHG EAX,$tmp2\n\t" 8288 "DIV $tmp\n\t" 8289 "LNEG $tmp2 : EAX\n\t" 8290 "JMP,s done\n" 8291 "pos:\n\t" 8292 "DIV $tmp\n\t" 8293 "XCHG EAX,$tmp2\n" 8294 "fast:\n\t" 8295 "DIV $tmp\n" 8296 "done:\n\t" 8297 "MOV EDX,$tmp2\n\t" 8298 "NEG EDX:EAX # if $imm < 0" %} 8299 ins_encode %{ 8300 int con = (int)$imm$$constant; 8301 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); 8302 int pcon = (con > 0) ? con : -con; 8303 Label Lfast, Lpos, Ldone; 8304 8305 __ movl($tmp$$Register, pcon); 8306 __ xorl($tmp2$$Register,$tmp2$$Register); 8307 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); 8308 __ jccb(Assembler::above, Lfast); // result fits into 32 bit 8309 8310 __ movl($tmp2$$Register, $dst$$Register); // save 8311 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8312 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags 8313 __ jccb(Assembler::lessEqual, Lpos); // result is positive 8314 8315 // Negative dividend. 8316 // convert value to positive to use unsigned division 8317 __ lneg($dst$$Register, $tmp2$$Register); 8318 __ divl($tmp$$Register); 8319 __ xchgl($dst$$Register, $tmp2$$Register); 8320 __ divl($tmp$$Register); 8321 // revert result back to negative 8322 __ lneg($tmp2$$Register, $dst$$Register); 8323 __ jmpb(Ldone); 8324 8325 __ bind(Lpos); 8326 __ divl($tmp$$Register); // Use unsigned division 8327 __ xchgl($dst$$Register, $tmp2$$Register); 8328 // Fallthrow for final divide, tmp2 has 32 bit hi result 8329 8330 __ bind(Lfast); 8331 // fast path: src is positive 8332 __ divl($tmp$$Register); // Use unsigned division 8333 8334 __ bind(Ldone); 8335 __ movl(HIGH_FROM_LOW($dst$$Register),$tmp2$$Register); 8336 if (con < 0) { 8337 __ lneg(HIGH_FROM_LOW($dst$$Register), $dst$$Register); 8338 } 8339 %} 8340 ins_pipe( pipe_slow ); 8341 %} 8342 8343 // Remainder Register Long (remainder fit into 32 bits) 8344 instruct modL_eReg_imm32( eADXRegL dst, immL32 imm, rRegI tmp, rRegI tmp2, eFlagsReg cr ) %{ 8345 match(Set dst (ModL dst imm)); 8346 effect( TEMP tmp, TEMP tmp2, KILL cr ); 8347 ins_cost(1000); 8348 format %{ "MOV $tmp,abs($imm) # lrem EDX:EAX,$imm\n\t" 8349 "CMP $tmp,EDX\n\t" 8350 "JA,s fast\n\t" 8351 "MOV $tmp2,EAX\n\t" 8352 "MOV EAX,EDX\n\t" 8353 "MOV EDX,0\n\t" 8354 "JLE,s pos\n\t" 8355 "LNEG EAX : $tmp2\n\t" 8356 "DIV $tmp # unsigned division\n\t" 8357 "MOV EAX,$tmp2\n\t" 8358 "DIV $tmp\n\t" 8359 "NEG EDX\n\t" 8360 "JMP,s done\n" 8361 "pos:\n\t" 8362 "DIV $tmp\n\t" 8363 "MOV EAX,$tmp2\n" 8364 "fast:\n\t" 8365 "DIV $tmp\n" 8366 "done:\n\t" 8367 "MOV EAX,EDX\n\t" 8368 "SAR EDX,31\n\t" %} 8369 ins_encode %{ 8370 int con = (int)$imm$$constant; 8371 assert(con != 0 && con != -1 && con != min_jint, "wrong divisor"); 8372 int pcon = (con > 0) ? con : -con; 8373 Label Lfast, Lpos, Ldone; 8374 8375 __ movl($tmp$$Register, pcon); 8376 __ cmpl($tmp$$Register, HIGH_FROM_LOW($dst$$Register)); 8377 __ jccb(Assembler::above, Lfast); // src is positive and result fits into 32 bit 8378 8379 __ movl($tmp2$$Register, $dst$$Register); // save 8380 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8381 __ movl(HIGH_FROM_LOW($dst$$Register),0); // preserve flags 8382 __ jccb(Assembler::lessEqual, Lpos); // result is positive 8383 8384 // Negative dividend. 8385 // convert value to positive to use unsigned division 8386 __ lneg($dst$$Register, $tmp2$$Register); 8387 __ divl($tmp$$Register); 8388 __ movl($dst$$Register, $tmp2$$Register); 8389 __ divl($tmp$$Register); 8390 // revert remainder back to negative 8391 __ negl(HIGH_FROM_LOW($dst$$Register)); 8392 __ jmpb(Ldone); 8393 8394 __ bind(Lpos); 8395 __ divl($tmp$$Register); 8396 __ movl($dst$$Register, $tmp2$$Register); 8397 8398 __ bind(Lfast); 8399 // fast path: src is positive 8400 __ divl($tmp$$Register); 8401 8402 __ bind(Ldone); 8403 __ movl($dst$$Register, HIGH_FROM_LOW($dst$$Register)); 8404 __ sarl(HIGH_FROM_LOW($dst$$Register), 31); // result sign 8405 8406 %} 8407 ins_pipe( pipe_slow ); 8408 %} 8409 8410 // Integer Shift Instructions 8411 // Shift Left by one 8412 instruct shlI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ 8413 match(Set dst (LShiftI dst shift)); 8414 effect(KILL cr); 8415 8416 size(2); 8417 format %{ "SHL $dst,$shift" %} 8418 opcode(0xD1, 0x4); /* D1 /4 */ 8419 ins_encode( OpcP, RegOpc( dst ) ); 8420 ins_pipe( ialu_reg ); 8421 %} 8422 8423 // Shift Left by 8-bit immediate 8424 instruct salI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ 8425 match(Set dst (LShiftI dst shift)); 8426 effect(KILL cr); 8427 8428 size(3); 8429 format %{ "SHL $dst,$shift" %} 8430 opcode(0xC1, 0x4); /* C1 /4 ib */ 8431 ins_encode( RegOpcImm( dst, shift) ); 8432 ins_pipe( ialu_reg ); 8433 %} 8434 8435 // Shift Left by variable 8436 instruct salI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8437 match(Set dst (LShiftI dst shift)); 8438 effect(KILL cr); 8439 8440 size(2); 8441 format %{ "SHL $dst,$shift" %} 8442 opcode(0xD3, 0x4); /* D3 /4 */ 8443 ins_encode( OpcP, RegOpc( dst ) ); 8444 ins_pipe( ialu_reg_reg ); 8445 %} 8446 8447 // Arithmetic shift right by one 8448 instruct sarI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ 8449 match(Set dst (RShiftI dst shift)); 8450 effect(KILL cr); 8451 8452 size(2); 8453 format %{ "SAR $dst,$shift" %} 8454 opcode(0xD1, 0x7); /* D1 /7 */ 8455 ins_encode( OpcP, RegOpc( dst ) ); 8456 ins_pipe( ialu_reg ); 8457 %} 8458 8459 // Arithmetic shift right by one 8460 instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ 8461 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8462 effect(KILL cr); 8463 format %{ "SAR $dst,$shift" %} 8464 opcode(0xD1, 0x7); /* D1 /7 */ 8465 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8466 ins_pipe( ialu_mem_imm ); 8467 %} 8468 8469 // Arithmetic Shift Right by 8-bit immediate 8470 instruct sarI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ 8471 match(Set dst (RShiftI dst shift)); 8472 effect(KILL cr); 8473 8474 size(3); 8475 format %{ "SAR $dst,$shift" %} 8476 opcode(0xC1, 0x7); /* C1 /7 ib */ 8477 ins_encode( RegOpcImm( dst, shift ) ); 8478 ins_pipe( ialu_mem_imm ); 8479 %} 8480 8481 // Arithmetic Shift Right by 8-bit immediate 8482 instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ 8483 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8484 effect(KILL cr); 8485 8486 format %{ "SAR $dst,$shift" %} 8487 opcode(0xC1, 0x7); /* C1 /7 ib */ 8488 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8489 ins_pipe( ialu_mem_imm ); 8490 %} 8491 8492 // Arithmetic Shift Right by variable 8493 instruct sarI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8494 match(Set dst (RShiftI dst shift)); 8495 effect(KILL cr); 8496 8497 size(2); 8498 format %{ "SAR $dst,$shift" %} 8499 opcode(0xD3, 0x7); /* D3 /7 */ 8500 ins_encode( OpcP, RegOpc( dst ) ); 8501 ins_pipe( ialu_reg_reg ); 8502 %} 8503 8504 // Logical shift right by one 8505 instruct shrI_eReg_1(rRegI dst, immI1 shift, eFlagsReg cr) %{ 8506 match(Set dst (URShiftI dst shift)); 8507 effect(KILL cr); 8508 8509 size(2); 8510 format %{ "SHR $dst,$shift" %} 8511 opcode(0xD1, 0x5); /* D1 /5 */ 8512 ins_encode( OpcP, RegOpc( dst ) ); 8513 ins_pipe( ialu_reg ); 8514 %} 8515 8516 // Logical Shift Right by 8-bit immediate 8517 instruct shrI_eReg_imm(rRegI dst, immI8 shift, eFlagsReg cr) %{ 8518 match(Set dst (URShiftI dst shift)); 8519 effect(KILL cr); 8520 8521 size(3); 8522 format %{ "SHR $dst,$shift" %} 8523 opcode(0xC1, 0x5); /* C1 /5 ib */ 8524 ins_encode( RegOpcImm( dst, shift) ); 8525 ins_pipe( ialu_reg ); 8526 %} 8527 8528 8529 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8530 // This idiom is used by the compiler for the i2b bytecode. 8531 instruct i2b(rRegI dst, xRegI src, immI_24 twentyfour) %{ 8532 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8533 8534 size(3); 8535 format %{ "MOVSX $dst,$src :8" %} 8536 ins_encode %{ 8537 __ movsbl($dst$$Register, $src$$Register); 8538 %} 8539 ins_pipe(ialu_reg_reg); 8540 %} 8541 8542 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8543 // This idiom is used by the compiler the i2s bytecode. 8544 instruct i2s(rRegI dst, xRegI src, immI_16 sixteen) %{ 8545 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8546 8547 size(3); 8548 format %{ "MOVSX $dst,$src :16" %} 8549 ins_encode %{ 8550 __ movswl($dst$$Register, $src$$Register); 8551 %} 8552 ins_pipe(ialu_reg_reg); 8553 %} 8554 8555 8556 // Logical Shift Right by variable 8557 instruct shrI_eReg_CL(rRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8558 match(Set dst (URShiftI dst shift)); 8559 effect(KILL cr); 8560 8561 size(2); 8562 format %{ "SHR $dst,$shift" %} 8563 opcode(0xD3, 0x5); /* D3 /5 */ 8564 ins_encode( OpcP, RegOpc( dst ) ); 8565 ins_pipe( ialu_reg_reg ); 8566 %} 8567 8568 8569 //----------Logical Instructions----------------------------------------------- 8570 //----------Integer Logical Instructions--------------------------------------- 8571 // And Instructions 8572 // And Register with Register 8573 instruct andI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 8574 match(Set dst (AndI dst src)); 8575 effect(KILL cr); 8576 8577 size(2); 8578 format %{ "AND $dst,$src" %} 8579 opcode(0x23); 8580 ins_encode( OpcP, RegReg( dst, src) ); 8581 ins_pipe( ialu_reg_reg ); 8582 %} 8583 8584 // And Register with Immediate 8585 instruct andI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ 8586 match(Set dst (AndI dst src)); 8587 effect(KILL cr); 8588 8589 format %{ "AND $dst,$src" %} 8590 opcode(0x81,0x04); /* Opcode 81 /4 */ 8591 // ins_encode( RegImm( dst, src) ); 8592 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8593 ins_pipe( ialu_reg ); 8594 %} 8595 8596 // And Register with Memory 8597 instruct andI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ 8598 match(Set dst (AndI dst (LoadI src))); 8599 effect(KILL cr); 8600 8601 ins_cost(125); 8602 format %{ "AND $dst,$src" %} 8603 opcode(0x23); 8604 ins_encode( OpcP, RegMem( dst, src) ); 8605 ins_pipe( ialu_reg_mem ); 8606 %} 8607 8608 // And Memory with Register 8609 instruct andI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ 8610 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8611 effect(KILL cr); 8612 8613 ins_cost(150); 8614 format %{ "AND $dst,$src" %} 8615 opcode(0x21); /* Opcode 21 /r */ 8616 ins_encode( OpcP, RegMem( src, dst ) ); 8617 ins_pipe( ialu_mem_reg ); 8618 %} 8619 8620 // And Memory with Immediate 8621 instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8622 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8623 effect(KILL cr); 8624 8625 ins_cost(125); 8626 format %{ "AND $dst,$src" %} 8627 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 8628 // ins_encode( MemImm( dst, src) ); 8629 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8630 ins_pipe( ialu_mem_imm ); 8631 %} 8632 8633 // Or Instructions 8634 // Or Register with Register 8635 instruct orI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 8636 match(Set dst (OrI dst src)); 8637 effect(KILL cr); 8638 8639 size(2); 8640 format %{ "OR $dst,$src" %} 8641 opcode(0x0B); 8642 ins_encode( OpcP, RegReg( dst, src) ); 8643 ins_pipe( ialu_reg_reg ); 8644 %} 8645 8646 instruct orI_eReg_castP2X(rRegI dst, eRegP src, eFlagsReg cr) %{ 8647 match(Set dst (OrI dst (CastP2X src))); 8648 effect(KILL cr); 8649 8650 size(2); 8651 format %{ "OR $dst,$src" %} 8652 opcode(0x0B); 8653 ins_encode( OpcP, RegReg( dst, src) ); 8654 ins_pipe( ialu_reg_reg ); 8655 %} 8656 8657 8658 // Or Register with Immediate 8659 instruct orI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ 8660 match(Set dst (OrI dst src)); 8661 effect(KILL cr); 8662 8663 format %{ "OR $dst,$src" %} 8664 opcode(0x81,0x01); /* Opcode 81 /1 id */ 8665 // ins_encode( RegImm( dst, src) ); 8666 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8667 ins_pipe( ialu_reg ); 8668 %} 8669 8670 // Or Register with Memory 8671 instruct orI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ 8672 match(Set dst (OrI dst (LoadI src))); 8673 effect(KILL cr); 8674 8675 ins_cost(125); 8676 format %{ "OR $dst,$src" %} 8677 opcode(0x0B); 8678 ins_encode( OpcP, RegMem( dst, src) ); 8679 ins_pipe( ialu_reg_mem ); 8680 %} 8681 8682 // Or Memory with Register 8683 instruct orI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ 8684 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8685 effect(KILL cr); 8686 8687 ins_cost(150); 8688 format %{ "OR $dst,$src" %} 8689 opcode(0x09); /* Opcode 09 /r */ 8690 ins_encode( OpcP, RegMem( src, dst ) ); 8691 ins_pipe( ialu_mem_reg ); 8692 %} 8693 8694 // Or Memory with Immediate 8695 instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8696 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8697 effect(KILL cr); 8698 8699 ins_cost(125); 8700 format %{ "OR $dst,$src" %} 8701 opcode(0x81,0x1); /* Opcode 81 /1 id */ 8702 // ins_encode( MemImm( dst, src) ); 8703 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8704 ins_pipe( ialu_mem_imm ); 8705 %} 8706 8707 // ROL/ROR 8708 // ROL expand 8709 instruct rolI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ 8710 effect(USE_DEF dst, USE shift, KILL cr); 8711 8712 format %{ "ROL $dst, $shift" %} 8713 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 8714 ins_encode( OpcP, RegOpc( dst )); 8715 ins_pipe( ialu_reg ); 8716 %} 8717 8718 instruct rolI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ 8719 effect(USE_DEF dst, USE shift, KILL cr); 8720 8721 format %{ "ROL $dst, $shift" %} 8722 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 8723 ins_encode( RegOpcImm(dst, shift) ); 8724 ins_pipe(ialu_reg); 8725 %} 8726 8727 instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8728 effect(USE_DEF dst, USE shift, KILL cr); 8729 8730 format %{ "ROL $dst, $shift" %} 8731 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 8732 ins_encode(OpcP, RegOpc(dst)); 8733 ins_pipe( ialu_reg_reg ); 8734 %} 8735 // end of ROL expand 8736 8737 // ROL 32bit by one once 8738 instruct rolI_eReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 8739 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8740 8741 expand %{ 8742 rolI_eReg_imm1(dst, lshift, cr); 8743 %} 8744 %} 8745 8746 // ROL 32bit var by imm8 once 8747 instruct rolI_eReg_i8(rRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 8748 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8749 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8750 8751 expand %{ 8752 rolI_eReg_imm8(dst, lshift, cr); 8753 %} 8754 %} 8755 8756 // ROL 32bit var by var once 8757 instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8758 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 8759 8760 expand %{ 8761 rolI_eReg_CL(dst, shift, cr); 8762 %} 8763 %} 8764 8765 // ROL 32bit var by var once 8766 instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8767 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 8768 8769 expand %{ 8770 rolI_eReg_CL(dst, shift, cr); 8771 %} 8772 %} 8773 8774 // ROR expand 8775 instruct rorI_eReg_imm1(rRegI dst, immI1 shift, eFlagsReg cr) %{ 8776 effect(USE_DEF dst, USE shift, KILL cr); 8777 8778 format %{ "ROR $dst, $shift" %} 8779 opcode(0xD1,0x1); /* Opcode D1 /1 */ 8780 ins_encode( OpcP, RegOpc( dst ) ); 8781 ins_pipe( ialu_reg ); 8782 %} 8783 8784 instruct rorI_eReg_imm8(rRegI dst, immI8 shift, eFlagsReg cr) %{ 8785 effect (USE_DEF dst, USE shift, KILL cr); 8786 8787 format %{ "ROR $dst, $shift" %} 8788 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 8789 ins_encode( RegOpcImm(dst, shift) ); 8790 ins_pipe( ialu_reg ); 8791 %} 8792 8793 instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ 8794 effect(USE_DEF dst, USE shift, KILL cr); 8795 8796 format %{ "ROR $dst, $shift" %} 8797 opcode(0xD3, 0x1); /* Opcode D3 /1 */ 8798 ins_encode(OpcP, RegOpc(dst)); 8799 ins_pipe( ialu_reg_reg ); 8800 %} 8801 // end of ROR expand 8802 8803 // ROR right once 8804 instruct rorI_eReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 8805 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8806 8807 expand %{ 8808 rorI_eReg_imm1(dst, rshift, cr); 8809 %} 8810 %} 8811 8812 // ROR 32bit by immI8 once 8813 instruct rorI_eReg_i8(rRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 8814 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8815 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8816 8817 expand %{ 8818 rorI_eReg_imm8(dst, rshift, cr); 8819 %} 8820 %} 8821 8822 // ROR 32bit var by var once 8823 instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8824 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 8825 8826 expand %{ 8827 rorI_eReg_CL(dst, shift, cr); 8828 %} 8829 %} 8830 8831 // ROR 32bit var by var once 8832 instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8833 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 8834 8835 expand %{ 8836 rorI_eReg_CL(dst, shift, cr); 8837 %} 8838 %} 8839 8840 // Xor Instructions 8841 // Xor Register with Register 8842 instruct xorI_eReg(rRegI dst, rRegI src, eFlagsReg cr) %{ 8843 match(Set dst (XorI dst src)); 8844 effect(KILL cr); 8845 8846 size(2); 8847 format %{ "XOR $dst,$src" %} 8848 opcode(0x33); 8849 ins_encode( OpcP, RegReg( dst, src) ); 8850 ins_pipe( ialu_reg_reg ); 8851 %} 8852 8853 // Xor Register with Immediate -1 8854 instruct xorI_eReg_im1(rRegI dst, immI_M1 imm) %{ 8855 match(Set dst (XorI dst imm)); 8856 8857 size(2); 8858 format %{ "NOT $dst" %} 8859 ins_encode %{ 8860 __ notl($dst$$Register); 8861 %} 8862 ins_pipe( ialu_reg ); 8863 %} 8864 8865 // Xor Register with Immediate 8866 instruct xorI_eReg_imm(rRegI dst, immI src, eFlagsReg cr) %{ 8867 match(Set dst (XorI dst src)); 8868 effect(KILL cr); 8869 8870 format %{ "XOR $dst,$src" %} 8871 opcode(0x81,0x06); /* Opcode 81 /6 id */ 8872 // ins_encode( RegImm( dst, src) ); 8873 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8874 ins_pipe( ialu_reg ); 8875 %} 8876 8877 // Xor Register with Memory 8878 instruct xorI_eReg_mem(rRegI dst, memory src, eFlagsReg cr) %{ 8879 match(Set dst (XorI dst (LoadI src))); 8880 effect(KILL cr); 8881 8882 ins_cost(125); 8883 format %{ "XOR $dst,$src" %} 8884 opcode(0x33); 8885 ins_encode( OpcP, RegMem(dst, src) ); 8886 ins_pipe( ialu_reg_mem ); 8887 %} 8888 8889 // Xor Memory with Register 8890 instruct xorI_mem_eReg(memory dst, rRegI src, eFlagsReg cr) %{ 8891 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8892 effect(KILL cr); 8893 8894 ins_cost(150); 8895 format %{ "XOR $dst,$src" %} 8896 opcode(0x31); /* Opcode 31 /r */ 8897 ins_encode( OpcP, RegMem( src, dst ) ); 8898 ins_pipe( ialu_mem_reg ); 8899 %} 8900 8901 // Xor Memory with Immediate 8902 instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8903 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8904 effect(KILL cr); 8905 8906 ins_cost(125); 8907 format %{ "XOR $dst,$src" %} 8908 opcode(0x81,0x6); /* Opcode 81 /6 id */ 8909 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8910 ins_pipe( ialu_mem_imm ); 8911 %} 8912 8913 //----------Convert Int to Boolean--------------------------------------------- 8914 8915 instruct movI_nocopy(rRegI dst, rRegI src) %{ 8916 effect( DEF dst, USE src ); 8917 format %{ "MOV $dst,$src" %} 8918 ins_encode( enc_Copy( dst, src) ); 8919 ins_pipe( ialu_reg_reg ); 8920 %} 8921 8922 instruct ci2b( rRegI dst, rRegI src, eFlagsReg cr ) %{ 8923 effect( USE_DEF dst, USE src, KILL cr ); 8924 8925 size(4); 8926 format %{ "NEG $dst\n\t" 8927 "ADC $dst,$src" %} 8928 ins_encode( neg_reg(dst), 8929 OpcRegReg(0x13,dst,src) ); 8930 ins_pipe( ialu_reg_reg_long ); 8931 %} 8932 8933 instruct convI2B( rRegI dst, rRegI src, eFlagsReg cr ) %{ 8934 match(Set dst (Conv2B src)); 8935 8936 expand %{ 8937 movI_nocopy(dst,src); 8938 ci2b(dst,src,cr); 8939 %} 8940 %} 8941 8942 instruct movP_nocopy(rRegI dst, eRegP src) %{ 8943 effect( DEF dst, USE src ); 8944 format %{ "MOV $dst,$src" %} 8945 ins_encode( enc_Copy( dst, src) ); 8946 ins_pipe( ialu_reg_reg ); 8947 %} 8948 8949 instruct cp2b( rRegI dst, eRegP src, eFlagsReg cr ) %{ 8950 effect( USE_DEF dst, USE src, KILL cr ); 8951 format %{ "NEG $dst\n\t" 8952 "ADC $dst,$src" %} 8953 ins_encode( neg_reg(dst), 8954 OpcRegReg(0x13,dst,src) ); 8955 ins_pipe( ialu_reg_reg_long ); 8956 %} 8957 8958 instruct convP2B( rRegI dst, eRegP src, eFlagsReg cr ) %{ 8959 match(Set dst (Conv2B src)); 8960 8961 expand %{ 8962 movP_nocopy(dst,src); 8963 cp2b(dst,src,cr); 8964 %} 8965 %} 8966 8967 instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ 8968 match(Set dst (CmpLTMask p q)); 8969 effect( KILL cr ); 8970 ins_cost(400); 8971 8972 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination 8973 format %{ "XOR $dst,$dst\n\t" 8974 "CMP $p,$q\n\t" 8975 "SETlt $dst\n\t" 8976 "NEG $dst" %} 8977 ins_encode( OpcRegReg(0x33,dst,dst), 8978 OpcRegReg(0x3B,p,q), 8979 setLT_reg(dst), neg_reg(dst) ); 8980 ins_pipe( pipe_slow ); 8981 %} 8982 8983 instruct cmpLTMask0( rRegI dst, immI0 zero, eFlagsReg cr ) %{ 8984 match(Set dst (CmpLTMask dst zero)); 8985 effect( DEF dst, KILL cr ); 8986 ins_cost(100); 8987 8988 format %{ "SAR $dst,31" %} 8989 opcode(0xC1, 0x7); /* C1 /7 ib */ 8990 ins_encode( RegOpcImm( dst, 0x1F ) ); 8991 ins_pipe( ialu_reg ); 8992 %} 8993 8994 8995 instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ 8996 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8997 effect( KILL tmp, KILL cr ); 8998 ins_cost(400); 8999 // annoyingly, $tmp has no edges so you cant ask for it in 9000 // any format or encoding 9001 format %{ "SUB $p,$q\n\t" 9002 "SBB ECX,ECX\n\t" 9003 "AND ECX,$y\n\t" 9004 "ADD $p,ECX" %} 9005 ins_encode( enc_cmpLTP(p,q,y,tmp) ); 9006 ins_pipe( pipe_cmplt ); 9007 %} 9008 9009 /* If I enable this, I encourage spilling in the inner loop of compress. 9010 instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ 9011 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); 9012 effect( USE_KILL tmp, KILL cr ); 9013 ins_cost(400); 9014 9015 format %{ "SUB $p,$q\n\t" 9016 "SBB ECX,ECX\n\t" 9017 "AND ECX,$y\n\t" 9018 "ADD $p,ECX" %} 9019 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); 9020 %} 9021 */ 9022 9023 //----------Long Instructions------------------------------------------------ 9024 // Add Long Register with Register 9025 instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9026 match(Set dst (AddL dst src)); 9027 effect(KILL cr); 9028 ins_cost(200); 9029 format %{ "ADD $dst.lo,$src.lo\n\t" 9030 "ADC $dst.hi,$src.hi" %} 9031 opcode(0x03, 0x13); 9032 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9033 ins_pipe( ialu_reg_reg_long ); 9034 %} 9035 9036 // Add Long Register with Immediate 9037 instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9038 match(Set dst (AddL dst src)); 9039 effect(KILL cr); 9040 format %{ "ADD $dst.lo,$src.lo\n\t" 9041 "ADC $dst.hi,$src.hi" %} 9042 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ 9043 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9044 ins_pipe( ialu_reg_long ); 9045 %} 9046 9047 // Add Long Register with Memory 9048 instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9049 match(Set dst (AddL dst (LoadL mem))); 9050 effect(KILL cr); 9051 ins_cost(125); 9052 format %{ "ADD $dst.lo,$mem\n\t" 9053 "ADC $dst.hi,$mem+4" %} 9054 opcode(0x03, 0x13); 9055 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9056 ins_pipe( ialu_reg_long_mem ); 9057 %} 9058 9059 // Subtract Long Register with Register. 9060 instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9061 match(Set dst (SubL dst src)); 9062 effect(KILL cr); 9063 ins_cost(200); 9064 format %{ "SUB $dst.lo,$src.lo\n\t" 9065 "SBB $dst.hi,$src.hi" %} 9066 opcode(0x2B, 0x1B); 9067 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 9068 ins_pipe( ialu_reg_reg_long ); 9069 %} 9070 9071 // Subtract Long Register with Immediate 9072 instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9073 match(Set dst (SubL dst src)); 9074 effect(KILL cr); 9075 format %{ "SUB $dst.lo,$src.lo\n\t" 9076 "SBB $dst.hi,$src.hi" %} 9077 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ 9078 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9079 ins_pipe( ialu_reg_long ); 9080 %} 9081 9082 // Subtract Long Register with Memory 9083 instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9084 match(Set dst (SubL dst (LoadL mem))); 9085 effect(KILL cr); 9086 ins_cost(125); 9087 format %{ "SUB $dst.lo,$mem\n\t" 9088 "SBB $dst.hi,$mem+4" %} 9089 opcode(0x2B, 0x1B); 9090 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9091 ins_pipe( ialu_reg_long_mem ); 9092 %} 9093 9094 instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ 9095 match(Set dst (SubL zero dst)); 9096 effect(KILL cr); 9097 ins_cost(300); 9098 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} 9099 ins_encode( neg_long(dst) ); 9100 ins_pipe( ialu_reg_reg_long ); 9101 %} 9102 9103 // And Long Register with Register 9104 instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9105 match(Set dst (AndL dst src)); 9106 effect(KILL cr); 9107 format %{ "AND $dst.lo,$src.lo\n\t" 9108 "AND $dst.hi,$src.hi" %} 9109 opcode(0x23,0x23); 9110 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9111 ins_pipe( ialu_reg_reg_long ); 9112 %} 9113 9114 // And Long Register with Immediate 9115 instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9116 match(Set dst (AndL dst src)); 9117 effect(KILL cr); 9118 format %{ "AND $dst.lo,$src.lo\n\t" 9119 "AND $dst.hi,$src.hi" %} 9120 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ 9121 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9122 ins_pipe( ialu_reg_long ); 9123 %} 9124 9125 // And Long Register with Memory 9126 instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9127 match(Set dst (AndL dst (LoadL mem))); 9128 effect(KILL cr); 9129 ins_cost(125); 9130 format %{ "AND $dst.lo,$mem\n\t" 9131 "AND $dst.hi,$mem+4" %} 9132 opcode(0x23, 0x23); 9133 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9134 ins_pipe( ialu_reg_long_mem ); 9135 %} 9136 9137 // Or Long Register with Register 9138 instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9139 match(Set dst (OrL dst src)); 9140 effect(KILL cr); 9141 format %{ "OR $dst.lo,$src.lo\n\t" 9142 "OR $dst.hi,$src.hi" %} 9143 opcode(0x0B,0x0B); 9144 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9145 ins_pipe( ialu_reg_reg_long ); 9146 %} 9147 9148 // Or Long Register with Immediate 9149 instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9150 match(Set dst (OrL dst src)); 9151 effect(KILL cr); 9152 format %{ "OR $dst.lo,$src.lo\n\t" 9153 "OR $dst.hi,$src.hi" %} 9154 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ 9155 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9156 ins_pipe( ialu_reg_long ); 9157 %} 9158 9159 // Or Long Register with Memory 9160 instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9161 match(Set dst (OrL dst (LoadL mem))); 9162 effect(KILL cr); 9163 ins_cost(125); 9164 format %{ "OR $dst.lo,$mem\n\t" 9165 "OR $dst.hi,$mem+4" %} 9166 opcode(0x0B,0x0B); 9167 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9168 ins_pipe( ialu_reg_long_mem ); 9169 %} 9170 9171 // Xor Long Register with Register 9172 instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 9173 match(Set dst (XorL dst src)); 9174 effect(KILL cr); 9175 format %{ "XOR $dst.lo,$src.lo\n\t" 9176 "XOR $dst.hi,$src.hi" %} 9177 opcode(0x33,0x33); 9178 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 9179 ins_pipe( ialu_reg_reg_long ); 9180 %} 9181 9182 // Xor Long Register with Immediate -1 9183 instruct xorl_eReg_im1(eRegL dst, immL_M1 imm) %{ 9184 match(Set dst (XorL dst imm)); 9185 format %{ "NOT $dst.lo\n\t" 9186 "NOT $dst.hi" %} 9187 ins_encode %{ 9188 __ notl($dst$$Register); 9189 __ notl(HIGH_FROM_LOW($dst$$Register)); 9190 %} 9191 ins_pipe( ialu_reg_long ); 9192 %} 9193 9194 // Xor Long Register with Immediate 9195 instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 9196 match(Set dst (XorL dst src)); 9197 effect(KILL cr); 9198 format %{ "XOR $dst.lo,$src.lo\n\t" 9199 "XOR $dst.hi,$src.hi" %} 9200 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ 9201 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 9202 ins_pipe( ialu_reg_long ); 9203 %} 9204 9205 // Xor Long Register with Memory 9206 instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 9207 match(Set dst (XorL dst (LoadL mem))); 9208 effect(KILL cr); 9209 ins_cost(125); 9210 format %{ "XOR $dst.lo,$mem\n\t" 9211 "XOR $dst.hi,$mem+4" %} 9212 opcode(0x33,0x33); 9213 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 9214 ins_pipe( ialu_reg_long_mem ); 9215 %} 9216 9217 // Shift Left Long by 1 9218 instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ 9219 predicate(UseNewLongLShift); 9220 match(Set dst (LShiftL dst cnt)); 9221 effect(KILL cr); 9222 ins_cost(100); 9223 format %{ "ADD $dst.lo,$dst.lo\n\t" 9224 "ADC $dst.hi,$dst.hi" %} 9225 ins_encode %{ 9226 __ addl($dst$$Register,$dst$$Register); 9227 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9228 %} 9229 ins_pipe( ialu_reg_long ); 9230 %} 9231 9232 // Shift Left Long by 2 9233 instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ 9234 predicate(UseNewLongLShift); 9235 match(Set dst (LShiftL dst cnt)); 9236 effect(KILL cr); 9237 ins_cost(100); 9238 format %{ "ADD $dst.lo,$dst.lo\n\t" 9239 "ADC $dst.hi,$dst.hi\n\t" 9240 "ADD $dst.lo,$dst.lo\n\t" 9241 "ADC $dst.hi,$dst.hi" %} 9242 ins_encode %{ 9243 __ addl($dst$$Register,$dst$$Register); 9244 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9245 __ addl($dst$$Register,$dst$$Register); 9246 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9247 %} 9248 ins_pipe( ialu_reg_long ); 9249 %} 9250 9251 // Shift Left Long by 3 9252 instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ 9253 predicate(UseNewLongLShift); 9254 match(Set dst (LShiftL dst cnt)); 9255 effect(KILL cr); 9256 ins_cost(100); 9257 format %{ "ADD $dst.lo,$dst.lo\n\t" 9258 "ADC $dst.hi,$dst.hi\n\t" 9259 "ADD $dst.lo,$dst.lo\n\t" 9260 "ADC $dst.hi,$dst.hi\n\t" 9261 "ADD $dst.lo,$dst.lo\n\t" 9262 "ADC $dst.hi,$dst.hi" %} 9263 ins_encode %{ 9264 __ addl($dst$$Register,$dst$$Register); 9265 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9266 __ addl($dst$$Register,$dst$$Register); 9267 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9268 __ addl($dst$$Register,$dst$$Register); 9269 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9270 %} 9271 ins_pipe( ialu_reg_long ); 9272 %} 9273 9274 // Shift Left Long by 1-31 9275 instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9276 match(Set dst (LShiftL dst cnt)); 9277 effect(KILL cr); 9278 ins_cost(200); 9279 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" 9280 "SHL $dst.lo,$cnt" %} 9281 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ 9282 ins_encode( move_long_small_shift(dst,cnt) ); 9283 ins_pipe( ialu_reg_long ); 9284 %} 9285 9286 // Shift Left Long by 32-63 9287 instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9288 match(Set dst (LShiftL dst cnt)); 9289 effect(KILL cr); 9290 ins_cost(300); 9291 format %{ "MOV $dst.hi,$dst.lo\n" 9292 "\tSHL $dst.hi,$cnt-32\n" 9293 "\tXOR $dst.lo,$dst.lo" %} 9294 opcode(0xC1, 0x4); /* C1 /4 ib */ 9295 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9296 ins_pipe( ialu_reg_long ); 9297 %} 9298 9299 // Shift Left Long by variable 9300 instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9301 match(Set dst (LShiftL dst shift)); 9302 effect(KILL cr); 9303 ins_cost(500+200); 9304 size(17); 9305 format %{ "TEST $shift,32\n\t" 9306 "JEQ,s small\n\t" 9307 "MOV $dst.hi,$dst.lo\n\t" 9308 "XOR $dst.lo,$dst.lo\n" 9309 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" 9310 "SHL $dst.lo,$shift" %} 9311 ins_encode( shift_left_long( dst, shift ) ); 9312 ins_pipe( pipe_slow ); 9313 %} 9314 9315 // Shift Right Long by 1-31 9316 instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9317 match(Set dst (URShiftL dst cnt)); 9318 effect(KILL cr); 9319 ins_cost(200); 9320 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9321 "SHR $dst.hi,$cnt" %} 9322 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ 9323 ins_encode( move_long_small_shift(dst,cnt) ); 9324 ins_pipe( ialu_reg_long ); 9325 %} 9326 9327 // Shift Right Long by 32-63 9328 instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9329 match(Set dst (URShiftL dst cnt)); 9330 effect(KILL cr); 9331 ins_cost(300); 9332 format %{ "MOV $dst.lo,$dst.hi\n" 9333 "\tSHR $dst.lo,$cnt-32\n" 9334 "\tXOR $dst.hi,$dst.hi" %} 9335 opcode(0xC1, 0x5); /* C1 /5 ib */ 9336 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9337 ins_pipe( ialu_reg_long ); 9338 %} 9339 9340 // Shift Right Long by variable 9341 instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9342 match(Set dst (URShiftL dst shift)); 9343 effect(KILL cr); 9344 ins_cost(600); 9345 size(17); 9346 format %{ "TEST $shift,32\n\t" 9347 "JEQ,s small\n\t" 9348 "MOV $dst.lo,$dst.hi\n\t" 9349 "XOR $dst.hi,$dst.hi\n" 9350 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9351 "SHR $dst.hi,$shift" %} 9352 ins_encode( shift_right_long( dst, shift ) ); 9353 ins_pipe( pipe_slow ); 9354 %} 9355 9356 // Shift Right Long by 1-31 9357 instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9358 match(Set dst (RShiftL dst cnt)); 9359 effect(KILL cr); 9360 ins_cost(200); 9361 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9362 "SAR $dst.hi,$cnt" %} 9363 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ 9364 ins_encode( move_long_small_shift(dst,cnt) ); 9365 ins_pipe( ialu_reg_long ); 9366 %} 9367 9368 // Shift Right Long by 32-63 9369 instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9370 match(Set dst (RShiftL dst cnt)); 9371 effect(KILL cr); 9372 ins_cost(300); 9373 format %{ "MOV $dst.lo,$dst.hi\n" 9374 "\tSAR $dst.lo,$cnt-32\n" 9375 "\tSAR $dst.hi,31" %} 9376 opcode(0xC1, 0x7); /* C1 /7 ib */ 9377 ins_encode( move_long_big_shift_sign(dst,cnt) ); 9378 ins_pipe( ialu_reg_long ); 9379 %} 9380 9381 // Shift Right arithmetic Long by variable 9382 instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9383 match(Set dst (RShiftL dst shift)); 9384 effect(KILL cr); 9385 ins_cost(600); 9386 size(18); 9387 format %{ "TEST $shift,32\n\t" 9388 "JEQ,s small\n\t" 9389 "MOV $dst.lo,$dst.hi\n\t" 9390 "SAR $dst.hi,31\n" 9391 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9392 "SAR $dst.hi,$shift" %} 9393 ins_encode( shift_right_arith_long( dst, shift ) ); 9394 ins_pipe( pipe_slow ); 9395 %} 9396 9397 9398 //----------Double Instructions------------------------------------------------ 9399 // Double Math 9400 9401 // Compare & branch 9402 9403 // P6 version of float compare, sets condition codes in EFLAGS 9404 instruct cmpDPR_cc_P6(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ 9405 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9406 match(Set cr (CmpD src1 src2)); 9407 effect(KILL rax); 9408 ins_cost(150); 9409 format %{ "FLD $src1\n\t" 9410 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9411 "JNP exit\n\t" 9412 "MOV ah,1 // saw a NaN, set CF\n\t" 9413 "SAHF\n" 9414 "exit:\tNOP // avoid branch to branch" %} 9415 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9416 ins_encode( Push_Reg_DPR(src1), 9417 OpcP, RegOpc(src2), 9418 cmpF_P6_fixup ); 9419 ins_pipe( pipe_slow ); 9420 %} 9421 9422 instruct cmpDPR_cc_P6CF(eFlagsRegUCF cr, regDPR src1, regDPR src2) %{ 9423 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9424 match(Set cr (CmpD src1 src2)); 9425 ins_cost(150); 9426 format %{ "FLD $src1\n\t" 9427 "FUCOMIP ST,$src2 // P6 instruction" %} 9428 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9429 ins_encode( Push_Reg_DPR(src1), 9430 OpcP, RegOpc(src2)); 9431 ins_pipe( pipe_slow ); 9432 %} 9433 9434 // Compare & branch 9435 instruct cmpDPR_cc(eFlagsRegU cr, regDPR src1, regDPR src2, eAXRegI rax) %{ 9436 predicate(UseSSE<=1); 9437 match(Set cr (CmpD src1 src2)); 9438 effect(KILL rax); 9439 ins_cost(200); 9440 format %{ "FLD $src1\n\t" 9441 "FCOMp $src2\n\t" 9442 "FNSTSW AX\n\t" 9443 "TEST AX,0x400\n\t" 9444 "JZ,s flags\n\t" 9445 "MOV AH,1\t# unordered treat as LT\n" 9446 "flags:\tSAHF" %} 9447 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9448 ins_encode( Push_Reg_DPR(src1), 9449 OpcP, RegOpc(src2), 9450 fpu_flags); 9451 ins_pipe( pipe_slow ); 9452 %} 9453 9454 // Compare vs zero into -1,0,1 9455 instruct cmpDPR_0(rRegI dst, regDPR src1, immDPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 9456 predicate(UseSSE<=1); 9457 match(Set dst (CmpD3 src1 zero)); 9458 effect(KILL cr, KILL rax); 9459 ins_cost(280); 9460 format %{ "FTSTD $dst,$src1" %} 9461 opcode(0xE4, 0xD9); 9462 ins_encode( Push_Reg_DPR(src1), 9463 OpcS, OpcP, PopFPU, 9464 CmpF_Result(dst)); 9465 ins_pipe( pipe_slow ); 9466 %} 9467 9468 // Compare into -1,0,1 9469 instruct cmpDPR_reg(rRegI dst, regDPR src1, regDPR src2, eAXRegI rax, eFlagsReg cr) %{ 9470 predicate(UseSSE<=1); 9471 match(Set dst (CmpD3 src1 src2)); 9472 effect(KILL cr, KILL rax); 9473 ins_cost(300); 9474 format %{ "FCMPD $dst,$src1,$src2" %} 9475 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9476 ins_encode( Push_Reg_DPR(src1), 9477 OpcP, RegOpc(src2), 9478 CmpF_Result(dst)); 9479 ins_pipe( pipe_slow ); 9480 %} 9481 9482 // float compare and set condition codes in EFLAGS by XMM regs 9483 instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2) %{ 9484 predicate(UseSSE>=2); 9485 match(Set cr (CmpD src1 src2)); 9486 ins_cost(145); 9487 format %{ "UCOMISD $src1,$src2\n\t" 9488 "JNP,s exit\n\t" 9489 "PUSHF\t# saw NaN, set CF\n\t" 9490 "AND [rsp], #0xffffff2b\n\t" 9491 "POPF\n" 9492 "exit:" %} 9493 ins_encode %{ 9494 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9495 emit_cmpfp_fixup(_masm); 9496 %} 9497 ins_pipe( pipe_slow ); 9498 %} 9499 9500 instruct cmpD_ccCF(eFlagsRegUCF cr, regD src1, regD src2) %{ 9501 predicate(UseSSE>=2); 9502 match(Set cr (CmpD src1 src2)); 9503 ins_cost(100); 9504 format %{ "UCOMISD $src1,$src2" %} 9505 ins_encode %{ 9506 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9507 %} 9508 ins_pipe( pipe_slow ); 9509 %} 9510 9511 // float compare and set condition codes in EFLAGS by XMM regs 9512 instruct cmpD_ccmem(eFlagsRegU cr, regD src1, memory src2) %{ 9513 predicate(UseSSE>=2); 9514 match(Set cr (CmpD src1 (LoadD src2))); 9515 ins_cost(145); 9516 format %{ "UCOMISD $src1,$src2\n\t" 9517 "JNP,s exit\n\t" 9518 "PUSHF\t# saw NaN, set CF\n\t" 9519 "AND [rsp], #0xffffff2b\n\t" 9520 "POPF\n" 9521 "exit:" %} 9522 ins_encode %{ 9523 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9524 emit_cmpfp_fixup(_masm); 9525 %} 9526 ins_pipe( pipe_slow ); 9527 %} 9528 9529 instruct cmpD_ccmemCF(eFlagsRegUCF cr, regD src1, memory src2) %{ 9530 predicate(UseSSE>=2); 9531 match(Set cr (CmpD src1 (LoadD src2))); 9532 ins_cost(100); 9533 format %{ "UCOMISD $src1,$src2" %} 9534 ins_encode %{ 9535 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9536 %} 9537 ins_pipe( pipe_slow ); 9538 %} 9539 9540 // Compare into -1,0,1 in XMM 9541 instruct cmpD_reg(xRegI dst, regD src1, regD src2, eFlagsReg cr) %{ 9542 predicate(UseSSE>=2); 9543 match(Set dst (CmpD3 src1 src2)); 9544 effect(KILL cr); 9545 ins_cost(255); 9546 format %{ "UCOMISD $src1, $src2\n\t" 9547 "MOV $dst, #-1\n\t" 9548 "JP,s done\n\t" 9549 "JB,s done\n\t" 9550 "SETNE $dst\n\t" 9551 "MOVZB $dst, $dst\n" 9552 "done:" %} 9553 ins_encode %{ 9554 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister); 9555 emit_cmpfp3(_masm, $dst$$Register); 9556 %} 9557 ins_pipe( pipe_slow ); 9558 %} 9559 9560 // Compare into -1,0,1 in XMM and memory 9561 instruct cmpD_regmem(xRegI dst, regD src1, memory src2, eFlagsReg cr) %{ 9562 predicate(UseSSE>=2); 9563 match(Set dst (CmpD3 src1 (LoadD src2))); 9564 effect(KILL cr); 9565 ins_cost(275); 9566 format %{ "UCOMISD $src1, $src2\n\t" 9567 "MOV $dst, #-1\n\t" 9568 "JP,s done\n\t" 9569 "JB,s done\n\t" 9570 "SETNE $dst\n\t" 9571 "MOVZB $dst, $dst\n" 9572 "done:" %} 9573 ins_encode %{ 9574 __ ucomisd($src1$$XMMRegister, $src2$$Address); 9575 emit_cmpfp3(_masm, $dst$$Register); 9576 %} 9577 ins_pipe( pipe_slow ); 9578 %} 9579 9580 9581 instruct subDPR_reg(regDPR dst, regDPR src) %{ 9582 predicate (UseSSE <=1); 9583 match(Set dst (SubD dst src)); 9584 9585 format %{ "FLD $src\n\t" 9586 "DSUBp $dst,ST" %} 9587 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 9588 ins_cost(150); 9589 ins_encode( Push_Reg_DPR(src), 9590 OpcP, RegOpc(dst) ); 9591 ins_pipe( fpu_reg_reg ); 9592 %} 9593 9594 instruct subDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 9595 predicate (UseSSE <=1); 9596 match(Set dst (RoundDouble (SubD src1 src2))); 9597 ins_cost(250); 9598 9599 format %{ "FLD $src2\n\t" 9600 "DSUB ST,$src1\n\t" 9601 "FSTP_D $dst\t# D-round" %} 9602 opcode(0xD8, 0x5); 9603 ins_encode( Push_Reg_DPR(src2), 9604 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); 9605 ins_pipe( fpu_mem_reg_reg ); 9606 %} 9607 9608 9609 instruct subDPR_reg_mem(regDPR dst, memory src) %{ 9610 predicate (UseSSE <=1); 9611 match(Set dst (SubD dst (LoadD src))); 9612 ins_cost(150); 9613 9614 format %{ "FLD $src\n\t" 9615 "DSUBp $dst,ST" %} 9616 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9617 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9618 OpcP, RegOpc(dst) ); 9619 ins_pipe( fpu_reg_mem ); 9620 %} 9621 9622 instruct absDPR_reg(regDPR1 dst, regDPR1 src) %{ 9623 predicate (UseSSE<=1); 9624 match(Set dst (AbsD src)); 9625 ins_cost(100); 9626 format %{ "FABS" %} 9627 opcode(0xE1, 0xD9); 9628 ins_encode( OpcS, OpcP ); 9629 ins_pipe( fpu_reg_reg ); 9630 %} 9631 9632 instruct negDPR_reg(regDPR1 dst, regDPR1 src) %{ 9633 predicate(UseSSE<=1); 9634 match(Set dst (NegD src)); 9635 ins_cost(100); 9636 format %{ "FCHS" %} 9637 opcode(0xE0, 0xD9); 9638 ins_encode( OpcS, OpcP ); 9639 ins_pipe( fpu_reg_reg ); 9640 %} 9641 9642 instruct addDPR_reg(regDPR dst, regDPR src) %{ 9643 predicate(UseSSE<=1); 9644 match(Set dst (AddD dst src)); 9645 format %{ "FLD $src\n\t" 9646 "DADD $dst,ST" %} 9647 size(4); 9648 ins_cost(150); 9649 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 9650 ins_encode( Push_Reg_DPR(src), 9651 OpcP, RegOpc(dst) ); 9652 ins_pipe( fpu_reg_reg ); 9653 %} 9654 9655 9656 instruct addDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 9657 predicate(UseSSE<=1); 9658 match(Set dst (RoundDouble (AddD src1 src2))); 9659 ins_cost(250); 9660 9661 format %{ "FLD $src2\n\t" 9662 "DADD ST,$src1\n\t" 9663 "FSTP_D $dst\t# D-round" %} 9664 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ 9665 ins_encode( Push_Reg_DPR(src2), 9666 OpcP, RegOpc(src1), Pop_Mem_DPR(dst) ); 9667 ins_pipe( fpu_mem_reg_reg ); 9668 %} 9669 9670 9671 instruct addDPR_reg_mem(regDPR dst, memory src) %{ 9672 predicate(UseSSE<=1); 9673 match(Set dst (AddD dst (LoadD src))); 9674 ins_cost(150); 9675 9676 format %{ "FLD $src\n\t" 9677 "DADDp $dst,ST" %} 9678 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9679 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9680 OpcP, RegOpc(dst) ); 9681 ins_pipe( fpu_reg_mem ); 9682 %} 9683 9684 // add-to-memory 9685 instruct addDPR_mem_reg(memory dst, regDPR src) %{ 9686 predicate(UseSSE<=1); 9687 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); 9688 ins_cost(150); 9689 9690 format %{ "FLD_D $dst\n\t" 9691 "DADD ST,$src\n\t" 9692 "FST_D $dst" %} 9693 opcode(0xDD, 0x0); 9694 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), 9695 Opcode(0xD8), RegOpc(src), 9696 set_instruction_start, 9697 Opcode(0xDD), RMopc_Mem(0x03,dst) ); 9698 ins_pipe( fpu_reg_mem ); 9699 %} 9700 9701 instruct addDPR_reg_imm1(regDPR dst, immDPR1 con) %{ 9702 predicate(UseSSE<=1); 9703 match(Set dst (AddD dst con)); 9704 ins_cost(125); 9705 format %{ "FLD1\n\t" 9706 "DADDp $dst,ST" %} 9707 ins_encode %{ 9708 __ fld1(); 9709 __ faddp($dst$$reg); 9710 %} 9711 ins_pipe(fpu_reg); 9712 %} 9713 9714 instruct addDPR_reg_imm(regDPR dst, immDPR con) %{ 9715 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9716 match(Set dst (AddD dst con)); 9717 ins_cost(200); 9718 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9719 "DADDp $dst,ST" %} 9720 ins_encode %{ 9721 __ fld_d($constantaddress($con)); 9722 __ faddp($dst$$reg); 9723 %} 9724 ins_pipe(fpu_reg_mem); 9725 %} 9726 9727 instruct addDPR_reg_imm_round(stackSlotD dst, regDPR src, immDPR con) %{ 9728 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); 9729 match(Set dst (RoundDouble (AddD src con))); 9730 ins_cost(200); 9731 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9732 "DADD ST,$src\n\t" 9733 "FSTP_D $dst\t# D-round" %} 9734 ins_encode %{ 9735 __ fld_d($constantaddress($con)); 9736 __ fadd($src$$reg); 9737 __ fstp_d(Address(rsp, $dst$$disp)); 9738 %} 9739 ins_pipe(fpu_mem_reg_con); 9740 %} 9741 9742 instruct mulDPR_reg(regDPR dst, regDPR src) %{ 9743 predicate(UseSSE<=1); 9744 match(Set dst (MulD dst src)); 9745 format %{ "FLD $src\n\t" 9746 "DMULp $dst,ST" %} 9747 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9748 ins_cost(150); 9749 ins_encode( Push_Reg_DPR(src), 9750 OpcP, RegOpc(dst) ); 9751 ins_pipe( fpu_reg_reg ); 9752 %} 9753 9754 // Strict FP instruction biases argument before multiply then 9755 // biases result to avoid double rounding of subnormals. 9756 // 9757 // scale arg1 by multiplying arg1 by 2^(-15360) 9758 // load arg2 9759 // multiply scaled arg1 by arg2 9760 // rescale product by 2^(15360) 9761 // 9762 instruct strictfp_mulDPR_reg(regDPR1 dst, regnotDPR1 src) %{ 9763 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9764 match(Set dst (MulD dst src)); 9765 ins_cost(1); // Select this instruction for all strict FP double multiplies 9766 9767 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9768 "DMULp $dst,ST\n\t" 9769 "FLD $src\n\t" 9770 "DMULp $dst,ST\n\t" 9771 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9772 "DMULp $dst,ST\n\t" %} 9773 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9774 ins_encode( strictfp_bias1(dst), 9775 Push_Reg_DPR(src), 9776 OpcP, RegOpc(dst), 9777 strictfp_bias2(dst) ); 9778 ins_pipe( fpu_reg_reg ); 9779 %} 9780 9781 instruct mulDPR_reg_imm(regDPR dst, immDPR con) %{ 9782 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9783 match(Set dst (MulD dst con)); 9784 ins_cost(200); 9785 format %{ "FLD_D [$constantaddress]\t# load from constant table: double=$con\n\t" 9786 "DMULp $dst,ST" %} 9787 ins_encode %{ 9788 __ fld_d($constantaddress($con)); 9789 __ fmulp($dst$$reg); 9790 %} 9791 ins_pipe(fpu_reg_mem); 9792 %} 9793 9794 9795 instruct mulDPR_reg_mem(regDPR dst, memory src) %{ 9796 predicate( UseSSE<=1 ); 9797 match(Set dst (MulD dst (LoadD src))); 9798 ins_cost(200); 9799 format %{ "FLD_D $src\n\t" 9800 "DMULp $dst,ST" %} 9801 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ 9802 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9803 OpcP, RegOpc(dst) ); 9804 ins_pipe( fpu_reg_mem ); 9805 %} 9806 9807 // 9808 // Cisc-alternate to reg-reg multiply 9809 instruct mulDPR_reg_mem_cisc(regDPR dst, regDPR src, memory mem) %{ 9810 predicate( UseSSE<=1 ); 9811 match(Set dst (MulD src (LoadD mem))); 9812 ins_cost(250); 9813 format %{ "FLD_D $mem\n\t" 9814 "DMUL ST,$src\n\t" 9815 "FSTP_D $dst" %} 9816 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ 9817 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), 9818 OpcReg_FPR(src), 9819 Pop_Reg_DPR(dst) ); 9820 ins_pipe( fpu_reg_reg_mem ); 9821 %} 9822 9823 9824 // MACRO3 -- addDPR a mulDPR 9825 // This instruction is a '2-address' instruction in that the result goes 9826 // back to src2. This eliminates a move from the macro; possibly the 9827 // register allocator will have to add it back (and maybe not). 9828 instruct addDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ 9829 predicate( UseSSE<=1 ); 9830 match(Set src2 (AddD (MulD src0 src1) src2)); 9831 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9832 "DMUL ST,$src1\n\t" 9833 "DADDp $src2,ST" %} 9834 ins_cost(250); 9835 opcode(0xDD); /* LoadD DD /0 */ 9836 ins_encode( Push_Reg_FPR(src0), 9837 FMul_ST_reg(src1), 9838 FAddP_reg_ST(src2) ); 9839 ins_pipe( fpu_reg_reg_reg ); 9840 %} 9841 9842 9843 // MACRO3 -- subDPR a mulDPR 9844 instruct subDPR_mulDPR_reg(regDPR src2, regDPR src1, regDPR src0) %{ 9845 predicate( UseSSE<=1 ); 9846 match(Set src2 (SubD (MulD src0 src1) src2)); 9847 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9848 "DMUL ST,$src1\n\t" 9849 "DSUBRp $src2,ST" %} 9850 ins_cost(250); 9851 ins_encode( Push_Reg_FPR(src0), 9852 FMul_ST_reg(src1), 9853 Opcode(0xDE), Opc_plus(0xE0,src2)); 9854 ins_pipe( fpu_reg_reg_reg ); 9855 %} 9856 9857 9858 instruct divDPR_reg(regDPR dst, regDPR src) %{ 9859 predicate( UseSSE<=1 ); 9860 match(Set dst (DivD dst src)); 9861 9862 format %{ "FLD $src\n\t" 9863 "FDIVp $dst,ST" %} 9864 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9865 ins_cost(150); 9866 ins_encode( Push_Reg_DPR(src), 9867 OpcP, RegOpc(dst) ); 9868 ins_pipe( fpu_reg_reg ); 9869 %} 9870 9871 // Strict FP instruction biases argument before division then 9872 // biases result, to avoid double rounding of subnormals. 9873 // 9874 // scale dividend by multiplying dividend by 2^(-15360) 9875 // load divisor 9876 // divide scaled dividend by divisor 9877 // rescale quotient by 2^(15360) 9878 // 9879 instruct strictfp_divDPR_reg(regDPR1 dst, regnotDPR1 src) %{ 9880 predicate (UseSSE<=1); 9881 match(Set dst (DivD dst src)); 9882 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9883 ins_cost(01); 9884 9885 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9886 "DMULp $dst,ST\n\t" 9887 "FLD $src\n\t" 9888 "FDIVp $dst,ST\n\t" 9889 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9890 "DMULp $dst,ST\n\t" %} 9891 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9892 ins_encode( strictfp_bias1(dst), 9893 Push_Reg_DPR(src), 9894 OpcP, RegOpc(dst), 9895 strictfp_bias2(dst) ); 9896 ins_pipe( fpu_reg_reg ); 9897 %} 9898 9899 instruct divDPR_reg_round(stackSlotD dst, regDPR src1, regDPR src2) %{ 9900 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); 9901 match(Set dst (RoundDouble (DivD src1 src2))); 9902 9903 format %{ "FLD $src1\n\t" 9904 "FDIV ST,$src2\n\t" 9905 "FSTP_D $dst\t# D-round" %} 9906 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ 9907 ins_encode( Push_Reg_DPR(src1), 9908 OpcP, RegOpc(src2), Pop_Mem_DPR(dst) ); 9909 ins_pipe( fpu_mem_reg_reg ); 9910 %} 9911 9912 9913 instruct modDPR_reg(regDPR dst, regDPR src, eAXRegI rax, eFlagsReg cr) %{ 9914 predicate(UseSSE<=1); 9915 match(Set dst (ModD dst src)); 9916 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 9917 9918 format %{ "DMOD $dst,$src" %} 9919 ins_cost(250); 9920 ins_encode(Push_Reg_Mod_DPR(dst, src), 9921 emitModDPR(), 9922 Push_Result_Mod_DPR(src), 9923 Pop_Reg_DPR(dst)); 9924 ins_pipe( pipe_slow ); 9925 %} 9926 9927 instruct modD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eFlagsReg cr) %{ 9928 predicate(UseSSE>=2); 9929 match(Set dst (ModD src0 src1)); 9930 effect(KILL rax, KILL cr); 9931 9932 format %{ "SUB ESP,8\t # DMOD\n" 9933 "\tMOVSD [ESP+0],$src1\n" 9934 "\tFLD_D [ESP+0]\n" 9935 "\tMOVSD [ESP+0],$src0\n" 9936 "\tFLD_D [ESP+0]\n" 9937 "loop:\tFPREM\n" 9938 "\tFWAIT\n" 9939 "\tFNSTSW AX\n" 9940 "\tSAHF\n" 9941 "\tJP loop\n" 9942 "\tFSTP_D [ESP+0]\n" 9943 "\tMOVSD $dst,[ESP+0]\n" 9944 "\tADD ESP,8\n" 9945 "\tFSTP ST0\t # Restore FPU Stack" 9946 %} 9947 ins_cost(250); 9948 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU); 9949 ins_pipe( pipe_slow ); 9950 %} 9951 9952 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{ 9953 predicate (UseSSE<=1); 9954 match(Set dst (SinD src)); 9955 ins_cost(1800); 9956 format %{ "DSIN $dst" %} 9957 opcode(0xD9, 0xFE); 9958 ins_encode( OpcP, OpcS ); 9959 ins_pipe( pipe_slow ); 9960 %} 9961 9962 instruct sinD_reg(regD dst, eFlagsReg cr) %{ 9963 predicate (UseSSE>=2); 9964 match(Set dst (SinD dst)); 9965 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 9966 ins_cost(1800); 9967 format %{ "DSIN $dst" %} 9968 opcode(0xD9, 0xFE); 9969 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); 9970 ins_pipe( pipe_slow ); 9971 %} 9972 9973 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{ 9974 predicate (UseSSE<=1); 9975 match(Set dst (CosD src)); 9976 ins_cost(1800); 9977 format %{ "DCOS $dst" %} 9978 opcode(0xD9, 0xFF); 9979 ins_encode( OpcP, OpcS ); 9980 ins_pipe( pipe_slow ); 9981 %} 9982 9983 instruct cosD_reg(regD dst, eFlagsReg cr) %{ 9984 predicate (UseSSE>=2); 9985 match(Set dst (CosD dst)); 9986 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 9987 ins_cost(1800); 9988 format %{ "DCOS $dst" %} 9989 opcode(0xD9, 0xFF); 9990 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) ); 9991 ins_pipe( pipe_slow ); 9992 %} 9993 9994 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{ 9995 predicate (UseSSE<=1); 9996 match(Set dst(TanD src)); 9997 format %{ "DTAN $dst" %} 9998 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan 9999 Opcode(0xDD), Opcode(0xD8)); // fstp st 10000 ins_pipe( pipe_slow ); 10001 %} 10002 10003 instruct tanD_reg(regD dst, eFlagsReg cr) %{ 10004 predicate (UseSSE>=2); 10005 match(Set dst(TanD dst)); 10006 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10007 format %{ "DTAN $dst" %} 10008 ins_encode( Push_SrcD(dst), 10009 Opcode(0xD9), Opcode(0xF2), // fptan 10010 Opcode(0xDD), Opcode(0xD8), // fstp st 10011 Push_ResultD(dst) ); 10012 ins_pipe( pipe_slow ); 10013 %} 10014 10015 instruct atanDPR_reg(regDPR dst, regDPR src) %{ 10016 predicate (UseSSE<=1); 10017 match(Set dst(AtanD dst src)); 10018 format %{ "DATA $dst,$src" %} 10019 opcode(0xD9, 0xF3); 10020 ins_encode( Push_Reg_DPR(src), 10021 OpcP, OpcS, RegOpc(dst) ); 10022 ins_pipe( pipe_slow ); 10023 %} 10024 10025 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{ 10026 predicate (UseSSE>=2); 10027 match(Set dst(AtanD dst src)); 10028 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8" 10029 format %{ "DATA $dst,$src" %} 10030 opcode(0xD9, 0xF3); 10031 ins_encode( Push_SrcD(src), 10032 OpcP, OpcS, Push_ResultD(dst) ); 10033 ins_pipe( pipe_slow ); 10034 %} 10035 10036 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{ 10037 predicate (UseSSE<=1); 10038 match(Set dst (SqrtD src)); 10039 format %{ "DSQRT $dst,$src" %} 10040 opcode(0xFA, 0xD9); 10041 ins_encode( Push_Reg_DPR(src), 10042 OpcS, OpcP, Pop_Reg_DPR(dst) ); 10043 ins_pipe( pipe_slow ); 10044 %} 10045 10046 instruct powDPR_reg(regDPR X, regDPR1 Y, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ 10047 predicate (UseSSE<=1); 10048 match(Set Y (PowD X Y)); // Raise X to the Yth power 10049 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); 10050 format %{ "fast_pow $X $Y -> $Y // KILL $rax, $rcx, $rdx" %} 10051 ins_encode %{ 10052 __ subptr(rsp, 8); 10053 __ fld_s($X$$reg - 1); 10054 __ fast_pow(); 10055 __ addptr(rsp, 8); 10056 %} 10057 ins_pipe( pipe_slow ); 10058 %} 10059 10060 instruct powD_reg(regD dst, regD src0, regD src1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ 10061 predicate (UseSSE>=2); 10062 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power 10063 effect(KILL rax, KILL rdx, KILL rcx, KILL cr); 10064 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %} 10065 ins_encode %{ 10066 __ subptr(rsp, 8); 10067 __ movdbl(Address(rsp, 0), $src1$$XMMRegister); 10068 __ fld_d(Address(rsp, 0)); 10069 __ movdbl(Address(rsp, 0), $src0$$XMMRegister); 10070 __ fld_d(Address(rsp, 0)); 10071 __ fast_pow(); 10072 __ fstp_d(Address(rsp, 0)); 10073 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); 10074 __ addptr(rsp, 8); 10075 %} 10076 ins_pipe( pipe_slow ); 10077 %} 10078 10079 10080 instruct expDPR_reg(regDPR1 dpr1, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ 10081 predicate (UseSSE<=1); 10082 match(Set dpr1 (ExpD dpr1)); 10083 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); 10084 format %{ "fast_exp $dpr1 -> $dpr1 // KILL $rax, $rcx, $rdx" %} 10085 ins_encode %{ 10086 __ fast_exp(); 10087 %} 10088 ins_pipe( pipe_slow ); 10089 %} 10090 10091 instruct expD_reg(regD dst, regD src, eAXRegI rax, eDXRegI rdx, eCXRegI rcx, eFlagsReg cr) %{ 10092 predicate (UseSSE>=2); 10093 match(Set dst (ExpD src)); 10094 effect(KILL rax, KILL rcx, KILL rdx, KILL cr); 10095 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %} 10096 ins_encode %{ 10097 __ subptr(rsp, 8); 10098 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 10099 __ fld_d(Address(rsp, 0)); 10100 __ fast_exp(); 10101 __ fstp_d(Address(rsp, 0)); 10102 __ movdbl($dst$$XMMRegister, Address(rsp, 0)); 10103 __ addptr(rsp, 8); 10104 %} 10105 ins_pipe( pipe_slow ); 10106 %} 10107 10108 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{ 10109 predicate (UseSSE<=1); 10110 // The source Double operand on FPU stack 10111 match(Set dst (Log10D src)); 10112 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10113 // fxch ; swap ST(0) with ST(1) 10114 // fyl2x ; compute log_10(2) * log_2(x) 10115 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10116 "FXCH \n\t" 10117 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10118 %} 10119 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10120 Opcode(0xD9), Opcode(0xC9), // fxch 10121 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10122 10123 ins_pipe( pipe_slow ); 10124 %} 10125 10126 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{ 10127 predicate (UseSSE>=2); 10128 effect(KILL cr); 10129 match(Set dst (Log10D src)); 10130 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10131 // fyl2x ; compute log_10(2) * log_2(x) 10132 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10133 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10134 %} 10135 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10136 Push_SrcD(src), 10137 Opcode(0xD9), Opcode(0xF1), // fyl2x 10138 Push_ResultD(dst)); 10139 10140 ins_pipe( pipe_slow ); 10141 %} 10142 10143 instruct logDPR_reg(regDPR1 dst, regDPR1 src) %{ 10144 predicate (UseSSE<=1); 10145 // The source Double operand on FPU stack 10146 match(Set dst (LogD src)); 10147 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10148 // fxch ; swap ST(0) with ST(1) 10149 // fyl2x ; compute log_e(2) * log_2(x) 10150 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10151 "FXCH \n\t" 10152 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10153 %} 10154 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10155 Opcode(0xD9), Opcode(0xC9), // fxch 10156 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10157 10158 ins_pipe( pipe_slow ); 10159 %} 10160 10161 instruct logD_reg(regD dst, regD src, eFlagsReg cr) %{ 10162 predicate (UseSSE>=2); 10163 effect(KILL cr); 10164 // The source and result Double operands in XMM registers 10165 match(Set dst (LogD src)); 10166 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10167 // fyl2x ; compute log_e(2) * log_2(x) 10168 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10169 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10170 %} 10171 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10172 Push_SrcD(src), 10173 Opcode(0xD9), Opcode(0xF1), // fyl2x 10174 Push_ResultD(dst)); 10175 ins_pipe( pipe_slow ); 10176 %} 10177 10178 //-------------Float Instructions------------------------------- 10179 // Float Math 10180 10181 // Code for float compare: 10182 // fcompp(); 10183 // fwait(); fnstsw_ax(); 10184 // sahf(); 10185 // movl(dst, unordered_result); 10186 // jcc(Assembler::parity, exit); 10187 // movl(dst, less_result); 10188 // jcc(Assembler::below, exit); 10189 // movl(dst, equal_result); 10190 // jcc(Assembler::equal, exit); 10191 // movl(dst, greater_result); 10192 // exit: 10193 10194 // P6 version of float compare, sets condition codes in EFLAGS 10195 instruct cmpFPR_cc_P6(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ 10196 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10197 match(Set cr (CmpF src1 src2)); 10198 effect(KILL rax); 10199 ins_cost(150); 10200 format %{ "FLD $src1\n\t" 10201 "FUCOMIP ST,$src2 // P6 instruction\n\t" 10202 "JNP exit\n\t" 10203 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" 10204 "SAHF\n" 10205 "exit:\tNOP // avoid branch to branch" %} 10206 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10207 ins_encode( Push_Reg_DPR(src1), 10208 OpcP, RegOpc(src2), 10209 cmpF_P6_fixup ); 10210 ins_pipe( pipe_slow ); 10211 %} 10212 10213 instruct cmpFPR_cc_P6CF(eFlagsRegUCF cr, regFPR src1, regFPR src2) %{ 10214 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10215 match(Set cr (CmpF src1 src2)); 10216 ins_cost(100); 10217 format %{ "FLD $src1\n\t" 10218 "FUCOMIP ST,$src2 // P6 instruction" %} 10219 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10220 ins_encode( Push_Reg_DPR(src1), 10221 OpcP, RegOpc(src2)); 10222 ins_pipe( pipe_slow ); 10223 %} 10224 10225 10226 // Compare & branch 10227 instruct cmpFPR_cc(eFlagsRegU cr, regFPR src1, regFPR src2, eAXRegI rax) %{ 10228 predicate(UseSSE == 0); 10229 match(Set cr (CmpF src1 src2)); 10230 effect(KILL rax); 10231 ins_cost(200); 10232 format %{ "FLD $src1\n\t" 10233 "FCOMp $src2\n\t" 10234 "FNSTSW AX\n\t" 10235 "TEST AX,0x400\n\t" 10236 "JZ,s flags\n\t" 10237 "MOV AH,1\t# unordered treat as LT\n" 10238 "flags:\tSAHF" %} 10239 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10240 ins_encode( Push_Reg_DPR(src1), 10241 OpcP, RegOpc(src2), 10242 fpu_flags); 10243 ins_pipe( pipe_slow ); 10244 %} 10245 10246 // Compare vs zero into -1,0,1 10247 instruct cmpFPR_0(rRegI dst, regFPR src1, immFPR0 zero, eAXRegI rax, eFlagsReg cr) %{ 10248 predicate(UseSSE == 0); 10249 match(Set dst (CmpF3 src1 zero)); 10250 effect(KILL cr, KILL rax); 10251 ins_cost(280); 10252 format %{ "FTSTF $dst,$src1" %} 10253 opcode(0xE4, 0xD9); 10254 ins_encode( Push_Reg_DPR(src1), 10255 OpcS, OpcP, PopFPU, 10256 CmpF_Result(dst)); 10257 ins_pipe( pipe_slow ); 10258 %} 10259 10260 // Compare into -1,0,1 10261 instruct cmpFPR_reg(rRegI dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ 10262 predicate(UseSSE == 0); 10263 match(Set dst (CmpF3 src1 src2)); 10264 effect(KILL cr, KILL rax); 10265 ins_cost(300); 10266 format %{ "FCMPF $dst,$src1,$src2" %} 10267 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10268 ins_encode( Push_Reg_DPR(src1), 10269 OpcP, RegOpc(src2), 10270 CmpF_Result(dst)); 10271 ins_pipe( pipe_slow ); 10272 %} 10273 10274 // float compare and set condition codes in EFLAGS by XMM regs 10275 instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2) %{ 10276 predicate(UseSSE>=1); 10277 match(Set cr (CmpF src1 src2)); 10278 ins_cost(145); 10279 format %{ "UCOMISS $src1,$src2\n\t" 10280 "JNP,s exit\n\t" 10281 "PUSHF\t# saw NaN, set CF\n\t" 10282 "AND [rsp], #0xffffff2b\n\t" 10283 "POPF\n" 10284 "exit:" %} 10285 ins_encode %{ 10286 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10287 emit_cmpfp_fixup(_masm); 10288 %} 10289 ins_pipe( pipe_slow ); 10290 %} 10291 10292 instruct cmpF_ccCF(eFlagsRegUCF cr, regF src1, regF src2) %{ 10293 predicate(UseSSE>=1); 10294 match(Set cr (CmpF src1 src2)); 10295 ins_cost(100); 10296 format %{ "UCOMISS $src1,$src2" %} 10297 ins_encode %{ 10298 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10299 %} 10300 ins_pipe( pipe_slow ); 10301 %} 10302 10303 // float compare and set condition codes in EFLAGS by XMM regs 10304 instruct cmpF_ccmem(eFlagsRegU cr, regF src1, memory src2) %{ 10305 predicate(UseSSE>=1); 10306 match(Set cr (CmpF src1 (LoadF src2))); 10307 ins_cost(165); 10308 format %{ "UCOMISS $src1,$src2\n\t" 10309 "JNP,s exit\n\t" 10310 "PUSHF\t# saw NaN, set CF\n\t" 10311 "AND [rsp], #0xffffff2b\n\t" 10312 "POPF\n" 10313 "exit:" %} 10314 ins_encode %{ 10315 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10316 emit_cmpfp_fixup(_masm); 10317 %} 10318 ins_pipe( pipe_slow ); 10319 %} 10320 10321 instruct cmpF_ccmemCF(eFlagsRegUCF cr, regF src1, memory src2) %{ 10322 predicate(UseSSE>=1); 10323 match(Set cr (CmpF src1 (LoadF src2))); 10324 ins_cost(100); 10325 format %{ "UCOMISS $src1,$src2" %} 10326 ins_encode %{ 10327 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10328 %} 10329 ins_pipe( pipe_slow ); 10330 %} 10331 10332 // Compare into -1,0,1 in XMM 10333 instruct cmpF_reg(xRegI dst, regF src1, regF src2, eFlagsReg cr) %{ 10334 predicate(UseSSE>=1); 10335 match(Set dst (CmpF3 src1 src2)); 10336 effect(KILL cr); 10337 ins_cost(255); 10338 format %{ "UCOMISS $src1, $src2\n\t" 10339 "MOV $dst, #-1\n\t" 10340 "JP,s done\n\t" 10341 "JB,s done\n\t" 10342 "SETNE $dst\n\t" 10343 "MOVZB $dst, $dst\n" 10344 "done:" %} 10345 ins_encode %{ 10346 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister); 10347 emit_cmpfp3(_masm, $dst$$Register); 10348 %} 10349 ins_pipe( pipe_slow ); 10350 %} 10351 10352 // Compare into -1,0,1 in XMM and memory 10353 instruct cmpF_regmem(xRegI dst, regF src1, memory src2, eFlagsReg cr) %{ 10354 predicate(UseSSE>=1); 10355 match(Set dst (CmpF3 src1 (LoadF src2))); 10356 effect(KILL cr); 10357 ins_cost(275); 10358 format %{ "UCOMISS $src1, $src2\n\t" 10359 "MOV $dst, #-1\n\t" 10360 "JP,s done\n\t" 10361 "JB,s done\n\t" 10362 "SETNE $dst\n\t" 10363 "MOVZB $dst, $dst\n" 10364 "done:" %} 10365 ins_encode %{ 10366 __ ucomiss($src1$$XMMRegister, $src2$$Address); 10367 emit_cmpfp3(_masm, $dst$$Register); 10368 %} 10369 ins_pipe( pipe_slow ); 10370 %} 10371 10372 // Spill to obtain 24-bit precision 10373 instruct subFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10374 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10375 match(Set dst (SubF src1 src2)); 10376 10377 format %{ "FSUB $dst,$src1 - $src2" %} 10378 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ 10379 ins_encode( Push_Reg_FPR(src1), 10380 OpcReg_FPR(src2), 10381 Pop_Mem_FPR(dst) ); 10382 ins_pipe( fpu_mem_reg_reg ); 10383 %} 10384 // 10385 // This instruction does not round to 24-bits 10386 instruct subFPR_reg(regFPR dst, regFPR src) %{ 10387 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10388 match(Set dst (SubF dst src)); 10389 10390 format %{ "FSUB $dst,$src" %} 10391 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 10392 ins_encode( Push_Reg_FPR(src), 10393 OpcP, RegOpc(dst) ); 10394 ins_pipe( fpu_reg_reg ); 10395 %} 10396 10397 // Spill to obtain 24-bit precision 10398 instruct addFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10399 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10400 match(Set dst (AddF src1 src2)); 10401 10402 format %{ "FADD $dst,$src1,$src2" %} 10403 opcode(0xD8, 0x0); /* D8 C0+i */ 10404 ins_encode( Push_Reg_FPR(src2), 10405 OpcReg_FPR(src1), 10406 Pop_Mem_FPR(dst) ); 10407 ins_pipe( fpu_mem_reg_reg ); 10408 %} 10409 // 10410 // This instruction does not round to 24-bits 10411 instruct addFPR_reg(regFPR dst, regFPR src) %{ 10412 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10413 match(Set dst (AddF dst src)); 10414 10415 format %{ "FLD $src\n\t" 10416 "FADDp $dst,ST" %} 10417 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 10418 ins_encode( Push_Reg_FPR(src), 10419 OpcP, RegOpc(dst) ); 10420 ins_pipe( fpu_reg_reg ); 10421 %} 10422 10423 instruct absFPR_reg(regFPR1 dst, regFPR1 src) %{ 10424 predicate(UseSSE==0); 10425 match(Set dst (AbsF src)); 10426 ins_cost(100); 10427 format %{ "FABS" %} 10428 opcode(0xE1, 0xD9); 10429 ins_encode( OpcS, OpcP ); 10430 ins_pipe( fpu_reg_reg ); 10431 %} 10432 10433 instruct negFPR_reg(regFPR1 dst, regFPR1 src) %{ 10434 predicate(UseSSE==0); 10435 match(Set dst (NegF src)); 10436 ins_cost(100); 10437 format %{ "FCHS" %} 10438 opcode(0xE0, 0xD9); 10439 ins_encode( OpcS, OpcP ); 10440 ins_pipe( fpu_reg_reg ); 10441 %} 10442 10443 // Cisc-alternate to addFPR_reg 10444 // Spill to obtain 24-bit precision 10445 instruct addFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ 10446 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10447 match(Set dst (AddF src1 (LoadF src2))); 10448 10449 format %{ "FLD $src2\n\t" 10450 "FADD ST,$src1\n\t" 10451 "FSTP_S $dst" %} 10452 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10453 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10454 OpcReg_FPR(src1), 10455 Pop_Mem_FPR(dst) ); 10456 ins_pipe( fpu_mem_reg_mem ); 10457 %} 10458 // 10459 // Cisc-alternate to addFPR_reg 10460 // This instruction does not round to 24-bits 10461 instruct addFPR_reg_mem(regFPR dst, memory src) %{ 10462 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10463 match(Set dst (AddF dst (LoadF src))); 10464 10465 format %{ "FADD $dst,$src" %} 10466 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ 10467 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10468 OpcP, RegOpc(dst) ); 10469 ins_pipe( fpu_reg_mem ); 10470 %} 10471 10472 // // Following two instructions for _222_mpegaudio 10473 // Spill to obtain 24-bit precision 10474 instruct addFPR24_mem_reg(stackSlotF dst, regFPR src2, memory src1 ) %{ 10475 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10476 match(Set dst (AddF src1 src2)); 10477 10478 format %{ "FADD $dst,$src1,$src2" %} 10479 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10480 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), 10481 OpcReg_FPR(src2), 10482 Pop_Mem_FPR(dst) ); 10483 ins_pipe( fpu_mem_reg_mem ); 10484 %} 10485 10486 // Cisc-spill variant 10487 // Spill to obtain 24-bit precision 10488 instruct addFPR24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ 10489 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10490 match(Set dst (AddF src1 (LoadF src2))); 10491 10492 format %{ "FADD $dst,$src1,$src2 cisc" %} 10493 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10494 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10495 set_instruction_start, 10496 OpcP, RMopc_Mem(secondary,src1), 10497 Pop_Mem_FPR(dst) ); 10498 ins_pipe( fpu_mem_mem_mem ); 10499 %} 10500 10501 // Spill to obtain 24-bit precision 10502 instruct addFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10503 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10504 match(Set dst (AddF src1 src2)); 10505 10506 format %{ "FADD $dst,$src1,$src2" %} 10507 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ 10508 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10509 set_instruction_start, 10510 OpcP, RMopc_Mem(secondary,src1), 10511 Pop_Mem_FPR(dst) ); 10512 ins_pipe( fpu_mem_mem_mem ); 10513 %} 10514 10515 10516 // Spill to obtain 24-bit precision 10517 instruct addFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ 10518 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10519 match(Set dst (AddF src con)); 10520 format %{ "FLD $src\n\t" 10521 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10522 "FSTP_S $dst" %} 10523 ins_encode %{ 10524 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10525 __ fadd_s($constantaddress($con)); 10526 __ fstp_s(Address(rsp, $dst$$disp)); 10527 %} 10528 ins_pipe(fpu_mem_reg_con); 10529 %} 10530 // 10531 // This instruction does not round to 24-bits 10532 instruct addFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ 10533 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10534 match(Set dst (AddF src con)); 10535 format %{ "FLD $src\n\t" 10536 "FADD_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10537 "FSTP $dst" %} 10538 ins_encode %{ 10539 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10540 __ fadd_s($constantaddress($con)); 10541 __ fstp_d($dst$$reg); 10542 %} 10543 ins_pipe(fpu_reg_reg_con); 10544 %} 10545 10546 // Spill to obtain 24-bit precision 10547 instruct mulFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10548 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10549 match(Set dst (MulF src1 src2)); 10550 10551 format %{ "FLD $src1\n\t" 10552 "FMUL $src2\n\t" 10553 "FSTP_S $dst" %} 10554 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ 10555 ins_encode( Push_Reg_FPR(src1), 10556 OpcReg_FPR(src2), 10557 Pop_Mem_FPR(dst) ); 10558 ins_pipe( fpu_mem_reg_reg ); 10559 %} 10560 // 10561 // This instruction does not round to 24-bits 10562 instruct mulFPR_reg(regFPR dst, regFPR src1, regFPR src2) %{ 10563 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10564 match(Set dst (MulF src1 src2)); 10565 10566 format %{ "FLD $src1\n\t" 10567 "FMUL $src2\n\t" 10568 "FSTP_S $dst" %} 10569 opcode(0xD8, 0x1); /* D8 C8+i */ 10570 ins_encode( Push_Reg_FPR(src2), 10571 OpcReg_FPR(src1), 10572 Pop_Reg_FPR(dst) ); 10573 ins_pipe( fpu_reg_reg_reg ); 10574 %} 10575 10576 10577 // Spill to obtain 24-bit precision 10578 // Cisc-alternate to reg-reg multiply 10579 instruct mulFPR24_reg_mem(stackSlotF dst, regFPR src1, memory src2) %{ 10580 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10581 match(Set dst (MulF src1 (LoadF src2))); 10582 10583 format %{ "FLD_S $src2\n\t" 10584 "FMUL $src1\n\t" 10585 "FSTP_S $dst" %} 10586 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ 10587 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10588 OpcReg_FPR(src1), 10589 Pop_Mem_FPR(dst) ); 10590 ins_pipe( fpu_mem_reg_mem ); 10591 %} 10592 // 10593 // This instruction does not round to 24-bits 10594 // Cisc-alternate to reg-reg multiply 10595 instruct mulFPR_reg_mem(regFPR dst, regFPR src1, memory src2) %{ 10596 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10597 match(Set dst (MulF src1 (LoadF src2))); 10598 10599 format %{ "FMUL $dst,$src1,$src2" %} 10600 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ 10601 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10602 OpcReg_FPR(src1), 10603 Pop_Reg_FPR(dst) ); 10604 ins_pipe( fpu_reg_reg_mem ); 10605 %} 10606 10607 // Spill to obtain 24-bit precision 10608 instruct mulFPR24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10609 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10610 match(Set dst (MulF src1 src2)); 10611 10612 format %{ "FMUL $dst,$src1,$src2" %} 10613 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ 10614 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10615 set_instruction_start, 10616 OpcP, RMopc_Mem(secondary,src1), 10617 Pop_Mem_FPR(dst) ); 10618 ins_pipe( fpu_mem_mem_mem ); 10619 %} 10620 10621 // Spill to obtain 24-bit precision 10622 instruct mulFPR24_reg_imm(stackSlotF dst, regFPR src, immFPR con) %{ 10623 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10624 match(Set dst (MulF src con)); 10625 10626 format %{ "FLD $src\n\t" 10627 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10628 "FSTP_S $dst" %} 10629 ins_encode %{ 10630 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10631 __ fmul_s($constantaddress($con)); 10632 __ fstp_s(Address(rsp, $dst$$disp)); 10633 %} 10634 ins_pipe(fpu_mem_reg_con); 10635 %} 10636 // 10637 // This instruction does not round to 24-bits 10638 instruct mulFPR_reg_imm(regFPR dst, regFPR src, immFPR con) %{ 10639 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10640 match(Set dst (MulF src con)); 10641 10642 format %{ "FLD $src\n\t" 10643 "FMUL_S [$constantaddress]\t# load from constant table: float=$con\n\t" 10644 "FSTP $dst" %} 10645 ins_encode %{ 10646 __ fld_s($src$$reg - 1); // FLD ST(i-1) 10647 __ fmul_s($constantaddress($con)); 10648 __ fstp_d($dst$$reg); 10649 %} 10650 ins_pipe(fpu_reg_reg_con); 10651 %} 10652 10653 10654 // 10655 // MACRO1 -- subsume unshared load into mulFPR 10656 // This instruction does not round to 24-bits 10657 instruct mulFPR_reg_load1(regFPR dst, regFPR src, memory mem1 ) %{ 10658 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10659 match(Set dst (MulF (LoadF mem1) src)); 10660 10661 format %{ "FLD $mem1 ===MACRO1===\n\t" 10662 "FMUL ST,$src\n\t" 10663 "FSTP $dst" %} 10664 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ 10665 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), 10666 OpcReg_FPR(src), 10667 Pop_Reg_FPR(dst) ); 10668 ins_pipe( fpu_reg_reg_mem ); 10669 %} 10670 // 10671 // MACRO2 -- addFPR a mulFPR which subsumed an unshared load 10672 // This instruction does not round to 24-bits 10673 instruct addFPR_mulFPR_reg_load1(regFPR dst, memory mem1, regFPR src1, regFPR src2) %{ 10674 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10675 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); 10676 ins_cost(95); 10677 10678 format %{ "FLD $mem1 ===MACRO2===\n\t" 10679 "FMUL ST,$src1 subsume mulFPR left load\n\t" 10680 "FADD ST,$src2\n\t" 10681 "FSTP $dst" %} 10682 opcode(0xD9); /* LoadF D9 /0 */ 10683 ins_encode( OpcP, RMopc_Mem(0x00,mem1), 10684 FMul_ST_reg(src1), 10685 FAdd_ST_reg(src2), 10686 Pop_Reg_FPR(dst) ); 10687 ins_pipe( fpu_reg_mem_reg_reg ); 10688 %} 10689 10690 // MACRO3 -- addFPR a mulFPR 10691 // This instruction does not round to 24-bits. It is a '2-address' 10692 // instruction in that the result goes back to src2. This eliminates 10693 // a move from the macro; possibly the register allocator will have 10694 // to add it back (and maybe not). 10695 instruct addFPR_mulFPR_reg(regFPR src2, regFPR src1, regFPR src0) %{ 10696 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10697 match(Set src2 (AddF (MulF src0 src1) src2)); 10698 10699 format %{ "FLD $src0 ===MACRO3===\n\t" 10700 "FMUL ST,$src1\n\t" 10701 "FADDP $src2,ST" %} 10702 opcode(0xD9); /* LoadF D9 /0 */ 10703 ins_encode( Push_Reg_FPR(src0), 10704 FMul_ST_reg(src1), 10705 FAddP_reg_ST(src2) ); 10706 ins_pipe( fpu_reg_reg_reg ); 10707 %} 10708 10709 // MACRO4 -- divFPR subFPR 10710 // This instruction does not round to 24-bits 10711 instruct subFPR_divFPR_reg(regFPR dst, regFPR src1, regFPR src2, regFPR src3) %{ 10712 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10713 match(Set dst (DivF (SubF src2 src1) src3)); 10714 10715 format %{ "FLD $src2 ===MACRO4===\n\t" 10716 "FSUB ST,$src1\n\t" 10717 "FDIV ST,$src3\n\t" 10718 "FSTP $dst" %} 10719 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10720 ins_encode( Push_Reg_FPR(src2), 10721 subFPR_divFPR_encode(src1,src3), 10722 Pop_Reg_FPR(dst) ); 10723 ins_pipe( fpu_reg_reg_reg_reg ); 10724 %} 10725 10726 // Spill to obtain 24-bit precision 10727 instruct divFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2) %{ 10728 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10729 match(Set dst (DivF src1 src2)); 10730 10731 format %{ "FDIV $dst,$src1,$src2" %} 10732 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ 10733 ins_encode( Push_Reg_FPR(src1), 10734 OpcReg_FPR(src2), 10735 Pop_Mem_FPR(dst) ); 10736 ins_pipe( fpu_mem_reg_reg ); 10737 %} 10738 // 10739 // This instruction does not round to 24-bits 10740 instruct divFPR_reg(regFPR dst, regFPR src) %{ 10741 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10742 match(Set dst (DivF dst src)); 10743 10744 format %{ "FDIV $dst,$src" %} 10745 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10746 ins_encode( Push_Reg_FPR(src), 10747 OpcP, RegOpc(dst) ); 10748 ins_pipe( fpu_reg_reg ); 10749 %} 10750 10751 10752 // Spill to obtain 24-bit precision 10753 instruct modFPR24_reg(stackSlotF dst, regFPR src1, regFPR src2, eAXRegI rax, eFlagsReg cr) %{ 10754 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 10755 match(Set dst (ModF src1 src2)); 10756 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 10757 10758 format %{ "FMOD $dst,$src1,$src2" %} 10759 ins_encode( Push_Reg_Mod_DPR(src1, src2), 10760 emitModDPR(), 10761 Push_Result_Mod_DPR(src2), 10762 Pop_Mem_FPR(dst)); 10763 ins_pipe( pipe_slow ); 10764 %} 10765 // 10766 // This instruction does not round to 24-bits 10767 instruct modFPR_reg(regFPR dst, regFPR src, eAXRegI rax, eFlagsReg cr) %{ 10768 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10769 match(Set dst (ModF dst src)); 10770 effect(KILL rax, KILL cr); // emitModDPR() uses EAX and EFLAGS 10771 10772 format %{ "FMOD $dst,$src" %} 10773 ins_encode(Push_Reg_Mod_DPR(dst, src), 10774 emitModDPR(), 10775 Push_Result_Mod_DPR(src), 10776 Pop_Reg_FPR(dst)); 10777 ins_pipe( pipe_slow ); 10778 %} 10779 10780 instruct modF_reg(regF dst, regF src0, regF src1, eAXRegI rax, eFlagsReg cr) %{ 10781 predicate(UseSSE>=1); 10782 match(Set dst (ModF src0 src1)); 10783 effect(KILL rax, KILL cr); 10784 format %{ "SUB ESP,4\t # FMOD\n" 10785 "\tMOVSS [ESP+0],$src1\n" 10786 "\tFLD_S [ESP+0]\n" 10787 "\tMOVSS [ESP+0],$src0\n" 10788 "\tFLD_S [ESP+0]\n" 10789 "loop:\tFPREM\n" 10790 "\tFWAIT\n" 10791 "\tFNSTSW AX\n" 10792 "\tSAHF\n" 10793 "\tJP loop\n" 10794 "\tFSTP_S [ESP+0]\n" 10795 "\tMOVSS $dst,[ESP+0]\n" 10796 "\tADD ESP,4\n" 10797 "\tFSTP ST0\t # Restore FPU Stack" 10798 %} 10799 ins_cost(250); 10800 ins_encode( Push_ModF_encoding(src0, src1), emitModDPR(), Push_ResultF(dst,0x4), PopFPU); 10801 ins_pipe( pipe_slow ); 10802 %} 10803 10804 10805 //----------Arithmetic Conversion Instructions--------------------------------- 10806 // The conversions operations are all Alpha sorted. Please keep it that way! 10807 10808 instruct roundFloat_mem_reg(stackSlotF dst, regFPR src) %{ 10809 predicate(UseSSE==0); 10810 match(Set dst (RoundFloat src)); 10811 ins_cost(125); 10812 format %{ "FST_S $dst,$src\t# F-round" %} 10813 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); 10814 ins_pipe( fpu_mem_reg ); 10815 %} 10816 10817 instruct roundDouble_mem_reg(stackSlotD dst, regDPR src) %{ 10818 predicate(UseSSE<=1); 10819 match(Set dst (RoundDouble src)); 10820 ins_cost(125); 10821 format %{ "FST_D $dst,$src\t# D-round" %} 10822 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); 10823 ins_pipe( fpu_mem_reg ); 10824 %} 10825 10826 // Force rounding to 24-bit precision and 6-bit exponent 10827 instruct convDPR2FPR_reg(stackSlotF dst, regDPR src) %{ 10828 predicate(UseSSE==0); 10829 match(Set dst (ConvD2F src)); 10830 format %{ "FST_S $dst,$src\t# F-round" %} 10831 expand %{ 10832 roundFloat_mem_reg(dst,src); 10833 %} 10834 %} 10835 10836 // Force rounding to 24-bit precision and 6-bit exponent 10837 instruct convDPR2F_reg(regF dst, regDPR src, eFlagsReg cr) %{ 10838 predicate(UseSSE==1); 10839 match(Set dst (ConvD2F src)); 10840 effect( KILL cr ); 10841 format %{ "SUB ESP,4\n\t" 10842 "FST_S [ESP],$src\t# F-round\n\t" 10843 "MOVSS $dst,[ESP]\n\t" 10844 "ADD ESP,4" %} 10845 ins_encode %{ 10846 __ subptr(rsp, 4); 10847 if ($src$$reg != FPR1L_enc) { 10848 __ fld_s($src$$reg-1); 10849 __ fstp_s(Address(rsp, 0)); 10850 } else { 10851 __ fst_s(Address(rsp, 0)); 10852 } 10853 __ movflt($dst$$XMMRegister, Address(rsp, 0)); 10854 __ addptr(rsp, 4); 10855 %} 10856 ins_pipe( pipe_slow ); 10857 %} 10858 10859 // Force rounding double precision to single precision 10860 instruct convD2F_reg(regF dst, regD src) %{ 10861 predicate(UseSSE>=2); 10862 match(Set dst (ConvD2F src)); 10863 format %{ "CVTSD2SS $dst,$src\t# F-round" %} 10864 ins_encode %{ 10865 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister); 10866 %} 10867 ins_pipe( pipe_slow ); 10868 %} 10869 10870 instruct convFPR2DPR_reg_reg(regDPR dst, regFPR src) %{ 10871 predicate(UseSSE==0); 10872 match(Set dst (ConvF2D src)); 10873 format %{ "FST_S $dst,$src\t# D-round" %} 10874 ins_encode( Pop_Reg_Reg_DPR(dst, src)); 10875 ins_pipe( fpu_reg_reg ); 10876 %} 10877 10878 instruct convFPR2D_reg(stackSlotD dst, regFPR src) %{ 10879 predicate(UseSSE==1); 10880 match(Set dst (ConvF2D src)); 10881 format %{ "FST_D $dst,$src\t# D-round" %} 10882 expand %{ 10883 roundDouble_mem_reg(dst,src); 10884 %} 10885 %} 10886 10887 instruct convF2DPR_reg(regDPR dst, regF src, eFlagsReg cr) %{ 10888 predicate(UseSSE==1); 10889 match(Set dst (ConvF2D src)); 10890 effect( KILL cr ); 10891 format %{ "SUB ESP,4\n\t" 10892 "MOVSS [ESP] $src\n\t" 10893 "FLD_S [ESP]\n\t" 10894 "ADD ESP,4\n\t" 10895 "FSTP $dst\t# D-round" %} 10896 ins_encode %{ 10897 __ subptr(rsp, 4); 10898 __ movflt(Address(rsp, 0), $src$$XMMRegister); 10899 __ fld_s(Address(rsp, 0)); 10900 __ addptr(rsp, 4); 10901 __ fstp_d($dst$$reg); 10902 %} 10903 ins_pipe( pipe_slow ); 10904 %} 10905 10906 instruct convF2D_reg(regD dst, regF src) %{ 10907 predicate(UseSSE>=2); 10908 match(Set dst (ConvF2D src)); 10909 format %{ "CVTSS2SD $dst,$src\t# D-round" %} 10910 ins_encode %{ 10911 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister); 10912 %} 10913 ins_pipe( pipe_slow ); 10914 %} 10915 10916 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10917 instruct convDPR2I_reg_reg( eAXRegI dst, eDXRegI tmp, regDPR src, eFlagsReg cr ) %{ 10918 predicate(UseSSE<=1); 10919 match(Set dst (ConvD2I src)); 10920 effect( KILL tmp, KILL cr ); 10921 format %{ "FLD $src\t# Convert double to int \n\t" 10922 "FLDCW trunc mode\n\t" 10923 "SUB ESP,4\n\t" 10924 "FISTp [ESP + #0]\n\t" 10925 "FLDCW std/24-bit mode\n\t" 10926 "POP EAX\n\t" 10927 "CMP EAX,0x80000000\n\t" 10928 "JNE,s fast\n\t" 10929 "FLD_D $src\n\t" 10930 "CALL d2i_wrapper\n" 10931 "fast:" %} 10932 ins_encode( Push_Reg_DPR(src), DPR2I_encoding(src) ); 10933 ins_pipe( pipe_slow ); 10934 %} 10935 10936 // Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10937 instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ 10938 predicate(UseSSE>=2); 10939 match(Set dst (ConvD2I src)); 10940 effect( KILL tmp, KILL cr ); 10941 format %{ "CVTTSD2SI $dst, $src\n\t" 10942 "CMP $dst,0x80000000\n\t" 10943 "JNE,s fast\n\t" 10944 "SUB ESP, 8\n\t" 10945 "MOVSD [ESP], $src\n\t" 10946 "FLD_D [ESP]\n\t" 10947 "ADD ESP, 8\n\t" 10948 "CALL d2i_wrapper\n" 10949 "fast:" %} 10950 ins_encode %{ 10951 Label fast; 10952 __ cvttsd2sil($dst$$Register, $src$$XMMRegister); 10953 __ cmpl($dst$$Register, 0x80000000); 10954 __ jccb(Assembler::notEqual, fast); 10955 __ subptr(rsp, 8); 10956 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 10957 __ fld_d(Address(rsp, 0)); 10958 __ addptr(rsp, 8); 10959 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); 10960 __ bind(fast); 10961 %} 10962 ins_pipe( pipe_slow ); 10963 %} 10964 10965 instruct convDPR2L_reg_reg( eADXRegL dst, regDPR src, eFlagsReg cr ) %{ 10966 predicate(UseSSE<=1); 10967 match(Set dst (ConvD2L src)); 10968 effect( KILL cr ); 10969 format %{ "FLD $src\t# Convert double to long\n\t" 10970 "FLDCW trunc mode\n\t" 10971 "SUB ESP,8\n\t" 10972 "FISTp [ESP + #0]\n\t" 10973 "FLDCW std/24-bit mode\n\t" 10974 "POP EAX\n\t" 10975 "POP EDX\n\t" 10976 "CMP EDX,0x80000000\n\t" 10977 "JNE,s fast\n\t" 10978 "TEST EAX,EAX\n\t" 10979 "JNE,s fast\n\t" 10980 "FLD $src\n\t" 10981 "CALL d2l_wrapper\n" 10982 "fast:" %} 10983 ins_encode( Push_Reg_DPR(src), DPR2L_encoding(src) ); 10984 ins_pipe( pipe_slow ); 10985 %} 10986 10987 // XMM lacks a float/double->long conversion, so use the old FPU stack. 10988 instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ 10989 predicate (UseSSE>=2); 10990 match(Set dst (ConvD2L src)); 10991 effect( KILL cr ); 10992 format %{ "SUB ESP,8\t# Convert double to long\n\t" 10993 "MOVSD [ESP],$src\n\t" 10994 "FLD_D [ESP]\n\t" 10995 "FLDCW trunc mode\n\t" 10996 "FISTp [ESP + #0]\n\t" 10997 "FLDCW std/24-bit mode\n\t" 10998 "POP EAX\n\t" 10999 "POP EDX\n\t" 11000 "CMP EDX,0x80000000\n\t" 11001 "JNE,s fast\n\t" 11002 "TEST EAX,EAX\n\t" 11003 "JNE,s fast\n\t" 11004 "SUB ESP,8\n\t" 11005 "MOVSD [ESP],$src\n\t" 11006 "FLD_D [ESP]\n\t" 11007 "ADD ESP,8\n\t" 11008 "CALL d2l_wrapper\n" 11009 "fast:" %} 11010 ins_encode %{ 11011 Label fast; 11012 __ subptr(rsp, 8); 11013 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 11014 __ fld_d(Address(rsp, 0)); 11015 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 11016 __ fistp_d(Address(rsp, 0)); 11017 // Restore the rounding mode, mask the exception 11018 if (Compile::current()->in_24_bit_fp_mode()) { 11019 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 11020 } else { 11021 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 11022 } 11023 // Load the converted long, adjust CPU stack 11024 __ pop(rax); 11025 __ pop(rdx); 11026 __ cmpl(rdx, 0x80000000); 11027 __ jccb(Assembler::notEqual, fast); 11028 __ testl(rax, rax); 11029 __ jccb(Assembler::notEqual, fast); 11030 __ subptr(rsp, 8); 11031 __ movdbl(Address(rsp, 0), $src$$XMMRegister); 11032 __ fld_d(Address(rsp, 0)); 11033 __ addptr(rsp, 8); 11034 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); 11035 __ bind(fast); 11036 %} 11037 ins_pipe( pipe_slow ); 11038 %} 11039 11040 // Convert a double to an int. Java semantics require we do complex 11041 // manglations in the corner cases. So we set the rounding mode to 11042 // 'zero', store the darned double down as an int, and reset the 11043 // rounding mode to 'nearest'. The hardware stores a flag value down 11044 // if we would overflow or converted a NAN; we check for this and 11045 // and go the slow path if needed. 11046 instruct convFPR2I_reg_reg(eAXRegI dst, eDXRegI tmp, regFPR src, eFlagsReg cr ) %{ 11047 predicate(UseSSE==0); 11048 match(Set dst (ConvF2I src)); 11049 effect( KILL tmp, KILL cr ); 11050 format %{ "FLD $src\t# Convert float to int \n\t" 11051 "FLDCW trunc mode\n\t" 11052 "SUB ESP,4\n\t" 11053 "FISTp [ESP + #0]\n\t" 11054 "FLDCW std/24-bit mode\n\t" 11055 "POP EAX\n\t" 11056 "CMP EAX,0x80000000\n\t" 11057 "JNE,s fast\n\t" 11058 "FLD $src\n\t" 11059 "CALL d2i_wrapper\n" 11060 "fast:" %} 11061 // DPR2I_encoding works for FPR2I 11062 ins_encode( Push_Reg_FPR(src), DPR2I_encoding(src) ); 11063 ins_pipe( pipe_slow ); 11064 %} 11065 11066 // Convert a float in xmm to an int reg. 11067 instruct convF2I_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ 11068 predicate(UseSSE>=1); 11069 match(Set dst (ConvF2I src)); 11070 effect( KILL tmp, KILL cr ); 11071 format %{ "CVTTSS2SI $dst, $src\n\t" 11072 "CMP $dst,0x80000000\n\t" 11073 "JNE,s fast\n\t" 11074 "SUB ESP, 4\n\t" 11075 "MOVSS [ESP], $src\n\t" 11076 "FLD [ESP]\n\t" 11077 "ADD ESP, 4\n\t" 11078 "CALL d2i_wrapper\n" 11079 "fast:" %} 11080 ins_encode %{ 11081 Label fast; 11082 __ cvttss2sil($dst$$Register, $src$$XMMRegister); 11083 __ cmpl($dst$$Register, 0x80000000); 11084 __ jccb(Assembler::notEqual, fast); 11085 __ subptr(rsp, 4); 11086 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11087 __ fld_s(Address(rsp, 0)); 11088 __ addptr(rsp, 4); 11089 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2i_wrapper()))); 11090 __ bind(fast); 11091 %} 11092 ins_pipe( pipe_slow ); 11093 %} 11094 11095 instruct convFPR2L_reg_reg( eADXRegL dst, regFPR src, eFlagsReg cr ) %{ 11096 predicate(UseSSE==0); 11097 match(Set dst (ConvF2L src)); 11098 effect( KILL cr ); 11099 format %{ "FLD $src\t# Convert float to long\n\t" 11100 "FLDCW trunc mode\n\t" 11101 "SUB ESP,8\n\t" 11102 "FISTp [ESP + #0]\n\t" 11103 "FLDCW std/24-bit mode\n\t" 11104 "POP EAX\n\t" 11105 "POP EDX\n\t" 11106 "CMP EDX,0x80000000\n\t" 11107 "JNE,s fast\n\t" 11108 "TEST EAX,EAX\n\t" 11109 "JNE,s fast\n\t" 11110 "FLD $src\n\t" 11111 "CALL d2l_wrapper\n" 11112 "fast:" %} 11113 // DPR2L_encoding works for FPR2L 11114 ins_encode( Push_Reg_FPR(src), DPR2L_encoding(src) ); 11115 ins_pipe( pipe_slow ); 11116 %} 11117 11118 // XMM lacks a float/double->long conversion, so use the old FPU stack. 11119 instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ 11120 predicate (UseSSE>=1); 11121 match(Set dst (ConvF2L src)); 11122 effect( KILL cr ); 11123 format %{ "SUB ESP,8\t# Convert float to long\n\t" 11124 "MOVSS [ESP],$src\n\t" 11125 "FLD_S [ESP]\n\t" 11126 "FLDCW trunc mode\n\t" 11127 "FISTp [ESP + #0]\n\t" 11128 "FLDCW std/24-bit mode\n\t" 11129 "POP EAX\n\t" 11130 "POP EDX\n\t" 11131 "CMP EDX,0x80000000\n\t" 11132 "JNE,s fast\n\t" 11133 "TEST EAX,EAX\n\t" 11134 "JNE,s fast\n\t" 11135 "SUB ESP,4\t# Convert float to long\n\t" 11136 "MOVSS [ESP],$src\n\t" 11137 "FLD_S [ESP]\n\t" 11138 "ADD ESP,4\n\t" 11139 "CALL d2l_wrapper\n" 11140 "fast:" %} 11141 ins_encode %{ 11142 Label fast; 11143 __ subptr(rsp, 8); 11144 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11145 __ fld_s(Address(rsp, 0)); 11146 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 11147 __ fistp_d(Address(rsp, 0)); 11148 // Restore the rounding mode, mask the exception 11149 if (Compile::current()->in_24_bit_fp_mode()) { 11150 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 11151 } else { 11152 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 11153 } 11154 // Load the converted long, adjust CPU stack 11155 __ pop(rax); 11156 __ pop(rdx); 11157 __ cmpl(rdx, 0x80000000); 11158 __ jccb(Assembler::notEqual, fast); 11159 __ testl(rax, rax); 11160 __ jccb(Assembler::notEqual, fast); 11161 __ subptr(rsp, 4); 11162 __ movflt(Address(rsp, 0), $src$$XMMRegister); 11163 __ fld_s(Address(rsp, 0)); 11164 __ addptr(rsp, 4); 11165 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::d2l_wrapper()))); 11166 __ bind(fast); 11167 %} 11168 ins_pipe( pipe_slow ); 11169 %} 11170 11171 instruct convI2DPR_reg(regDPR dst, stackSlotI src) %{ 11172 predicate( UseSSE<=1 ); 11173 match(Set dst (ConvI2D src)); 11174 format %{ "FILD $src\n\t" 11175 "FSTP $dst" %} 11176 opcode(0xDB, 0x0); /* DB /0 */ 11177 ins_encode(Push_Mem_I(src), Pop_Reg_DPR(dst)); 11178 ins_pipe( fpu_reg_mem ); 11179 %} 11180 11181 instruct convI2D_reg(regD dst, rRegI src) %{ 11182 predicate( UseSSE>=2 && !UseXmmI2D ); 11183 match(Set dst (ConvI2D src)); 11184 format %{ "CVTSI2SD $dst,$src" %} 11185 ins_encode %{ 11186 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register); 11187 %} 11188 ins_pipe( pipe_slow ); 11189 %} 11190 11191 instruct convI2D_mem(regD dst, memory mem) %{ 11192 predicate( UseSSE>=2 ); 11193 match(Set dst (ConvI2D (LoadI mem))); 11194 format %{ "CVTSI2SD $dst,$mem" %} 11195 ins_encode %{ 11196 __ cvtsi2sdl ($dst$$XMMRegister, $mem$$Address); 11197 %} 11198 ins_pipe( pipe_slow ); 11199 %} 11200 11201 instruct convXI2D_reg(regD dst, rRegI src) 11202 %{ 11203 predicate( UseSSE>=2 && UseXmmI2D ); 11204 match(Set dst (ConvI2D src)); 11205 11206 format %{ "MOVD $dst,$src\n\t" 11207 "CVTDQ2PD $dst,$dst\t# i2d" %} 11208 ins_encode %{ 11209 __ movdl($dst$$XMMRegister, $src$$Register); 11210 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 11211 %} 11212 ins_pipe(pipe_slow); // XXX 11213 %} 11214 11215 instruct convI2DPR_mem(regDPR dst, memory mem) %{ 11216 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11217 match(Set dst (ConvI2D (LoadI mem))); 11218 format %{ "FILD $mem\n\t" 11219 "FSTP $dst" %} 11220 opcode(0xDB); /* DB /0 */ 11221 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11222 Pop_Reg_DPR(dst)); 11223 ins_pipe( fpu_reg_mem ); 11224 %} 11225 11226 // Convert a byte to a float; no rounding step needed. 11227 instruct conv24I2FPR_reg(regFPR dst, stackSlotI src) %{ 11228 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); 11229 match(Set dst (ConvI2F src)); 11230 format %{ "FILD $src\n\t" 11231 "FSTP $dst" %} 11232 11233 opcode(0xDB, 0x0); /* DB /0 */ 11234 ins_encode(Push_Mem_I(src), Pop_Reg_FPR(dst)); 11235 ins_pipe( fpu_reg_mem ); 11236 %} 11237 11238 // In 24-bit mode, force exponent rounding by storing back out 11239 instruct convI2FPR_SSF(stackSlotF dst, stackSlotI src) %{ 11240 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11241 match(Set dst (ConvI2F src)); 11242 ins_cost(200); 11243 format %{ "FILD $src\n\t" 11244 "FSTP_S $dst" %} 11245 opcode(0xDB, 0x0); /* DB /0 */ 11246 ins_encode( Push_Mem_I(src), 11247 Pop_Mem_FPR(dst)); 11248 ins_pipe( fpu_mem_mem ); 11249 %} 11250 11251 // In 24-bit mode, force exponent rounding by storing back out 11252 instruct convI2FPR_SSF_mem(stackSlotF dst, memory mem) %{ 11253 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11254 match(Set dst (ConvI2F (LoadI mem))); 11255 ins_cost(200); 11256 format %{ "FILD $mem\n\t" 11257 "FSTP_S $dst" %} 11258 opcode(0xDB); /* DB /0 */ 11259 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11260 Pop_Mem_FPR(dst)); 11261 ins_pipe( fpu_mem_mem ); 11262 %} 11263 11264 // This instruction does not round to 24-bits 11265 instruct convI2FPR_reg(regFPR dst, stackSlotI src) %{ 11266 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11267 match(Set dst (ConvI2F src)); 11268 format %{ "FILD $src\n\t" 11269 "FSTP $dst" %} 11270 opcode(0xDB, 0x0); /* DB /0 */ 11271 ins_encode( Push_Mem_I(src), 11272 Pop_Reg_FPR(dst)); 11273 ins_pipe( fpu_reg_mem ); 11274 %} 11275 11276 // This instruction does not round to 24-bits 11277 instruct convI2FPR_mem(regFPR dst, memory mem) %{ 11278 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11279 match(Set dst (ConvI2F (LoadI mem))); 11280 format %{ "FILD $mem\n\t" 11281 "FSTP $dst" %} 11282 opcode(0xDB); /* DB /0 */ 11283 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11284 Pop_Reg_FPR(dst)); 11285 ins_pipe( fpu_reg_mem ); 11286 %} 11287 11288 // Convert an int to a float in xmm; no rounding step needed. 11289 instruct convI2F_reg(regF dst, rRegI src) %{ 11290 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 11291 match(Set dst (ConvI2F src)); 11292 format %{ "CVTSI2SS $dst, $src" %} 11293 ins_encode %{ 11294 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register); 11295 %} 11296 ins_pipe( pipe_slow ); 11297 %} 11298 11299 instruct convXI2F_reg(regF dst, rRegI src) 11300 %{ 11301 predicate( UseSSE>=2 && UseXmmI2F ); 11302 match(Set dst (ConvI2F src)); 11303 11304 format %{ "MOVD $dst,$src\n\t" 11305 "CVTDQ2PS $dst,$dst\t# i2f" %} 11306 ins_encode %{ 11307 __ movdl($dst$$XMMRegister, $src$$Register); 11308 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 11309 %} 11310 ins_pipe(pipe_slow); // XXX 11311 %} 11312 11313 instruct convI2L_reg( eRegL dst, rRegI src, eFlagsReg cr) %{ 11314 match(Set dst (ConvI2L src)); 11315 effect(KILL cr); 11316 ins_cost(375); 11317 format %{ "MOV $dst.lo,$src\n\t" 11318 "MOV $dst.hi,$src\n\t" 11319 "SAR $dst.hi,31" %} 11320 ins_encode(convert_int_long(dst,src)); 11321 ins_pipe( ialu_reg_reg_long ); 11322 %} 11323 11324 // Zero-extend convert int to long 11325 instruct convI2L_reg_zex(eRegL dst, rRegI src, immL_32bits mask, eFlagsReg flags ) %{ 11326 match(Set dst (AndL (ConvI2L src) mask) ); 11327 effect( KILL flags ); 11328 ins_cost(250); 11329 format %{ "MOV $dst.lo,$src\n\t" 11330 "XOR $dst.hi,$dst.hi" %} 11331 opcode(0x33); // XOR 11332 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11333 ins_pipe( ialu_reg_reg_long ); 11334 %} 11335 11336 // Zero-extend long 11337 instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ 11338 match(Set dst (AndL src mask) ); 11339 effect( KILL flags ); 11340 ins_cost(250); 11341 format %{ "MOV $dst.lo,$src.lo\n\t" 11342 "XOR $dst.hi,$dst.hi\n\t" %} 11343 opcode(0x33); // XOR 11344 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11345 ins_pipe( ialu_reg_reg_long ); 11346 %} 11347 11348 instruct convL2DPR_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ 11349 predicate (UseSSE<=1); 11350 match(Set dst (ConvL2D src)); 11351 effect( KILL cr ); 11352 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11353 "PUSH $src.lo\n\t" 11354 "FILD ST,[ESP + #0]\n\t" 11355 "ADD ESP,8\n\t" 11356 "FSTP_D $dst\t# D-round" %} 11357 opcode(0xDF, 0x5); /* DF /5 */ 11358 ins_encode(convert_long_double(src), Pop_Mem_DPR(dst)); 11359 ins_pipe( pipe_slow ); 11360 %} 11361 11362 instruct convL2D_reg( regD dst, eRegL src, eFlagsReg cr) %{ 11363 predicate (UseSSE>=2); 11364 match(Set dst (ConvL2D src)); 11365 effect( KILL cr ); 11366 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11367 "PUSH $src.lo\n\t" 11368 "FILD_D [ESP]\n\t" 11369 "FSTP_D [ESP]\n\t" 11370 "MOVSD $dst,[ESP]\n\t" 11371 "ADD ESP,8" %} 11372 opcode(0xDF, 0x5); /* DF /5 */ 11373 ins_encode(convert_long_double2(src), Push_ResultD(dst)); 11374 ins_pipe( pipe_slow ); 11375 %} 11376 11377 instruct convL2F_reg( regF dst, eRegL src, eFlagsReg cr) %{ 11378 predicate (UseSSE>=1); 11379 match(Set dst (ConvL2F src)); 11380 effect( KILL cr ); 11381 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11382 "PUSH $src.lo\n\t" 11383 "FILD_D [ESP]\n\t" 11384 "FSTP_S [ESP]\n\t" 11385 "MOVSS $dst,[ESP]\n\t" 11386 "ADD ESP,8" %} 11387 opcode(0xDF, 0x5); /* DF /5 */ 11388 ins_encode(convert_long_double2(src), Push_ResultF(dst,0x8)); 11389 ins_pipe( pipe_slow ); 11390 %} 11391 11392 instruct convL2FPR_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ 11393 match(Set dst (ConvL2F src)); 11394 effect( KILL cr ); 11395 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11396 "PUSH $src.lo\n\t" 11397 "FILD ST,[ESP + #0]\n\t" 11398 "ADD ESP,8\n\t" 11399 "FSTP_S $dst\t# F-round" %} 11400 opcode(0xDF, 0x5); /* DF /5 */ 11401 ins_encode(convert_long_double(src), Pop_Mem_FPR(dst)); 11402 ins_pipe( pipe_slow ); 11403 %} 11404 11405 instruct convL2I_reg( rRegI dst, eRegL src ) %{ 11406 match(Set dst (ConvL2I src)); 11407 effect( DEF dst, USE src ); 11408 format %{ "MOV $dst,$src.lo" %} 11409 ins_encode(enc_CopyL_Lo(dst,src)); 11410 ins_pipe( ialu_reg_reg ); 11411 %} 11412 11413 11414 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{ 11415 match(Set dst (MoveF2I src)); 11416 effect( DEF dst, USE src ); 11417 ins_cost(100); 11418 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 11419 ins_encode %{ 11420 __ movl($dst$$Register, Address(rsp, $src$$disp)); 11421 %} 11422 ins_pipe( ialu_reg_mem ); 11423 %} 11424 11425 instruct MoveFPR2I_reg_stack(stackSlotI dst, regFPR src) %{ 11426 predicate(UseSSE==0); 11427 match(Set dst (MoveF2I src)); 11428 effect( DEF dst, USE src ); 11429 11430 ins_cost(125); 11431 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} 11432 ins_encode( Pop_Mem_Reg_FPR(dst, src) ); 11433 ins_pipe( fpu_mem_reg ); 11434 %} 11435 11436 instruct MoveF2I_reg_stack_sse(stackSlotI dst, regF src) %{ 11437 predicate(UseSSE>=1); 11438 match(Set dst (MoveF2I src)); 11439 effect( DEF dst, USE src ); 11440 11441 ins_cost(95); 11442 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} 11443 ins_encode %{ 11444 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister); 11445 %} 11446 ins_pipe( pipe_slow ); 11447 %} 11448 11449 instruct MoveF2I_reg_reg_sse(rRegI dst, regF src) %{ 11450 predicate(UseSSE>=2); 11451 match(Set dst (MoveF2I src)); 11452 effect( DEF dst, USE src ); 11453 ins_cost(85); 11454 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 11455 ins_encode %{ 11456 __ movdl($dst$$Register, $src$$XMMRegister); 11457 %} 11458 ins_pipe( pipe_slow ); 11459 %} 11460 11461 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{ 11462 match(Set dst (MoveI2F src)); 11463 effect( DEF dst, USE src ); 11464 11465 ins_cost(100); 11466 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 11467 ins_encode %{ 11468 __ movl(Address(rsp, $dst$$disp), $src$$Register); 11469 %} 11470 ins_pipe( ialu_mem_reg ); 11471 %} 11472 11473 11474 instruct MoveI2FPR_stack_reg(regFPR dst, stackSlotI src) %{ 11475 predicate(UseSSE==0); 11476 match(Set dst (MoveI2F src)); 11477 effect(DEF dst, USE src); 11478 11479 ins_cost(125); 11480 format %{ "FLD_S $src\n\t" 11481 "FSTP $dst\t# MoveI2F_stack_reg" %} 11482 opcode(0xD9); /* D9 /0, FLD m32real */ 11483 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11484 Pop_Reg_FPR(dst) ); 11485 ins_pipe( fpu_reg_mem ); 11486 %} 11487 11488 instruct MoveI2F_stack_reg_sse(regF dst, stackSlotI src) %{ 11489 predicate(UseSSE>=1); 11490 match(Set dst (MoveI2F src)); 11491 effect( DEF dst, USE src ); 11492 11493 ins_cost(95); 11494 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} 11495 ins_encode %{ 11496 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp)); 11497 %} 11498 ins_pipe( pipe_slow ); 11499 %} 11500 11501 instruct MoveI2F_reg_reg_sse(regF dst, rRegI src) %{ 11502 predicate(UseSSE>=2); 11503 match(Set dst (MoveI2F src)); 11504 effect( DEF dst, USE src ); 11505 11506 ins_cost(85); 11507 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} 11508 ins_encode %{ 11509 __ movdl($dst$$XMMRegister, $src$$Register); 11510 %} 11511 ins_pipe( pipe_slow ); 11512 %} 11513 11514 instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ 11515 match(Set dst (MoveD2L src)); 11516 effect(DEF dst, USE src); 11517 11518 ins_cost(250); 11519 format %{ "MOV $dst.lo,$src\n\t" 11520 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} 11521 opcode(0x8B, 0x8B); 11522 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); 11523 ins_pipe( ialu_mem_long_reg ); 11524 %} 11525 11526 instruct MoveDPR2L_reg_stack(stackSlotL dst, regDPR src) %{ 11527 predicate(UseSSE<=1); 11528 match(Set dst (MoveD2L src)); 11529 effect(DEF dst, USE src); 11530 11531 ins_cost(125); 11532 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} 11533 ins_encode( Pop_Mem_Reg_DPR(dst, src) ); 11534 ins_pipe( fpu_mem_reg ); 11535 %} 11536 11537 instruct MoveD2L_reg_stack_sse(stackSlotL dst, regD src) %{ 11538 predicate(UseSSE>=2); 11539 match(Set dst (MoveD2L src)); 11540 effect(DEF dst, USE src); 11541 ins_cost(95); 11542 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} 11543 ins_encode %{ 11544 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister); 11545 %} 11546 ins_pipe( pipe_slow ); 11547 %} 11548 11549 instruct MoveD2L_reg_reg_sse(eRegL dst, regD src, regD tmp) %{ 11550 predicate(UseSSE>=2); 11551 match(Set dst (MoveD2L src)); 11552 effect(DEF dst, USE src, TEMP tmp); 11553 ins_cost(85); 11554 format %{ "MOVD $dst.lo,$src\n\t" 11555 "PSHUFLW $tmp,$src,0x4E\n\t" 11556 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} 11557 ins_encode %{ 11558 __ movdl($dst$$Register, $src$$XMMRegister); 11559 __ pshuflw($tmp$$XMMRegister, $src$$XMMRegister, 0x4e); 11560 __ movdl(HIGH_FROM_LOW($dst$$Register), $tmp$$XMMRegister); 11561 %} 11562 ins_pipe( pipe_slow ); 11563 %} 11564 11565 instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ 11566 match(Set dst (MoveL2D src)); 11567 effect(DEF dst, USE src); 11568 11569 ins_cost(200); 11570 format %{ "MOV $dst,$src.lo\n\t" 11571 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} 11572 opcode(0x89, 0x89); 11573 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 11574 ins_pipe( ialu_mem_long_reg ); 11575 %} 11576 11577 11578 instruct MoveL2DPR_stack_reg(regDPR dst, stackSlotL src) %{ 11579 predicate(UseSSE<=1); 11580 match(Set dst (MoveL2D src)); 11581 effect(DEF dst, USE src); 11582 ins_cost(125); 11583 11584 format %{ "FLD_D $src\n\t" 11585 "FSTP $dst\t# MoveL2D_stack_reg" %} 11586 opcode(0xDD); /* DD /0, FLD m64real */ 11587 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11588 Pop_Reg_DPR(dst) ); 11589 ins_pipe( fpu_reg_mem ); 11590 %} 11591 11592 11593 instruct MoveL2D_stack_reg_sse(regD dst, stackSlotL src) %{ 11594 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 11595 match(Set dst (MoveL2D src)); 11596 effect(DEF dst, USE src); 11597 11598 ins_cost(95); 11599 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11600 ins_encode %{ 11601 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 11602 %} 11603 ins_pipe( pipe_slow ); 11604 %} 11605 11606 instruct MoveL2D_stack_reg_sse_partial(regD dst, stackSlotL src) %{ 11607 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 11608 match(Set dst (MoveL2D src)); 11609 effect(DEF dst, USE src); 11610 11611 ins_cost(95); 11612 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11613 ins_encode %{ 11614 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp)); 11615 %} 11616 ins_pipe( pipe_slow ); 11617 %} 11618 11619 instruct MoveL2D_reg_reg_sse(regD dst, eRegL src, regD tmp) %{ 11620 predicate(UseSSE>=2); 11621 match(Set dst (MoveL2D src)); 11622 effect(TEMP dst, USE src, TEMP tmp); 11623 ins_cost(85); 11624 format %{ "MOVD $dst,$src.lo\n\t" 11625 "MOVD $tmp,$src.hi\n\t" 11626 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} 11627 ins_encode %{ 11628 __ movdl($dst$$XMMRegister, $src$$Register); 11629 __ movdl($tmp$$XMMRegister, HIGH_FROM_LOW($src$$Register)); 11630 __ punpckldq($dst$$XMMRegister, $tmp$$XMMRegister); 11631 %} 11632 ins_pipe( pipe_slow ); 11633 %} 11634 11635 11636 // ======================================================================= 11637 // fast clearing of an array 11638 instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 11639 match(Set dummy (ClearArray cnt base)); 11640 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); 11641 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" 11642 "XOR EAX,EAX\n\t" 11643 "REP STOS\t# store EAX into [EDI++] while ECX--" %} 11644 opcode(0,0x4); 11645 ins_encode( Opcode(0xD1), RegOpc(ECX), 11646 OpcRegReg(0x33,EAX,EAX), 11647 Opcode(0xF3), Opcode(0xAB) ); 11648 ins_pipe( pipe_slow ); 11649 %} 11650 11651 instruct string_compare(eDIRegP str1, eCXRegI cnt1, eSIRegP str2, eDXRegI cnt2, 11652 eAXRegI result, regD tmp1, eFlagsReg cr) %{ 11653 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11654 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr); 11655 11656 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %} 11657 ins_encode %{ 11658 __ string_compare($str1$$Register, $str2$$Register, 11659 $cnt1$$Register, $cnt2$$Register, $result$$Register, 11660 $tmp1$$XMMRegister); 11661 %} 11662 ins_pipe( pipe_slow ); 11663 %} 11664 11665 // fast string equals 11666 instruct string_equals(eDIRegP str1, eSIRegP str2, eCXRegI cnt, eAXRegI result, 11667 regD tmp1, regD tmp2, eBXRegI tmp3, eFlagsReg cr) %{ 11668 match(Set result (StrEquals (Binary str1 str2) cnt)); 11669 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr); 11670 11671 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %} 11672 ins_encode %{ 11673 __ char_arrays_equals(false, $str1$$Register, $str2$$Register, 11674 $cnt$$Register, $result$$Register, $tmp3$$Register, 11675 $tmp1$$XMMRegister, $tmp2$$XMMRegister); 11676 %} 11677 ins_pipe( pipe_slow ); 11678 %} 11679 11680 // fast search of substring with known size. 11681 instruct string_indexof_con(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, immI int_cnt2, 11682 eBXRegI result, regD vec, eAXRegI cnt2, eCXRegI tmp, eFlagsReg cr) %{ 11683 predicate(UseSSE42Intrinsics); 11684 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2))); 11685 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr); 11686 11687 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %} 11688 ins_encode %{ 11689 int icnt2 = (int)$int_cnt2$$constant; 11690 if (icnt2 >= 8) { 11691 // IndexOf for constant substrings with size >= 8 elements 11692 // which don't need to be loaded through stack. 11693 __ string_indexofC8($str1$$Register, $str2$$Register, 11694 $cnt1$$Register, $cnt2$$Register, 11695 icnt2, $result$$Register, 11696 $vec$$XMMRegister, $tmp$$Register); 11697 } else { 11698 // Small strings are loaded through stack if they cross page boundary. 11699 __ string_indexof($str1$$Register, $str2$$Register, 11700 $cnt1$$Register, $cnt2$$Register, 11701 icnt2, $result$$Register, 11702 $vec$$XMMRegister, $tmp$$Register); 11703 } 11704 %} 11705 ins_pipe( pipe_slow ); 11706 %} 11707 11708 instruct string_indexof(eDIRegP str1, eDXRegI cnt1, eSIRegP str2, eAXRegI cnt2, 11709 eBXRegI result, regD vec, eCXRegI tmp, eFlagsReg cr) %{ 11710 predicate(UseSSE42Intrinsics); 11711 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2))); 11712 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr); 11713 11714 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %} 11715 ins_encode %{ 11716 __ string_indexof($str1$$Register, $str2$$Register, 11717 $cnt1$$Register, $cnt2$$Register, 11718 (-1), $result$$Register, 11719 $vec$$XMMRegister, $tmp$$Register); 11720 %} 11721 ins_pipe( pipe_slow ); 11722 %} 11723 11724 // fast array equals 11725 instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI result, 11726 regD tmp1, regD tmp2, eCXRegI tmp3, eBXRegI tmp4, eFlagsReg cr) 11727 %{ 11728 match(Set result (AryEq ary1 ary2)); 11729 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr); 11730 //ins_cost(300); 11731 11732 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %} 11733 ins_encode %{ 11734 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register, 11735 $tmp3$$Register, $result$$Register, $tmp4$$Register, 11736 $tmp1$$XMMRegister, $tmp2$$XMMRegister); 11737 %} 11738 ins_pipe( pipe_slow ); 11739 %} 11740 11741 //----------Control Flow Instructions------------------------------------------ 11742 // Signed compare Instructions 11743 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{ 11744 match(Set cr (CmpI op1 op2)); 11745 effect( DEF cr, USE op1, USE op2 ); 11746 format %{ "CMP $op1,$op2" %} 11747 opcode(0x3B); /* Opcode 3B /r */ 11748 ins_encode( OpcP, RegReg( op1, op2) ); 11749 ins_pipe( ialu_cr_reg_reg ); 11750 %} 11751 11752 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{ 11753 match(Set cr (CmpI op1 op2)); 11754 effect( DEF cr, USE op1 ); 11755 format %{ "CMP $op1,$op2" %} 11756 opcode(0x81,0x07); /* Opcode 81 /7 */ 11757 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 11758 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11759 ins_pipe( ialu_cr_reg_imm ); 11760 %} 11761 11762 // Cisc-spilled version of cmpI_eReg 11763 instruct compI_eReg_mem(eFlagsReg cr, rRegI op1, memory op2) %{ 11764 match(Set cr (CmpI op1 (LoadI op2))); 11765 11766 format %{ "CMP $op1,$op2" %} 11767 ins_cost(500); 11768 opcode(0x3B); /* Opcode 3B /r */ 11769 ins_encode( OpcP, RegMem( op1, op2) ); 11770 ins_pipe( ialu_cr_reg_mem ); 11771 %} 11772 11773 instruct testI_reg( eFlagsReg cr, rRegI src, immI0 zero ) %{ 11774 match(Set cr (CmpI src zero)); 11775 effect( DEF cr, USE src ); 11776 11777 format %{ "TEST $src,$src" %} 11778 opcode(0x85); 11779 ins_encode( OpcP, RegReg( src, src ) ); 11780 ins_pipe( ialu_cr_reg_imm ); 11781 %} 11782 11783 instruct testI_reg_imm( eFlagsReg cr, rRegI src, immI con, immI0 zero ) %{ 11784 match(Set cr (CmpI (AndI src con) zero)); 11785 11786 format %{ "TEST $src,$con" %} 11787 opcode(0xF7,0x00); 11788 ins_encode( OpcP, RegOpc(src), Con32(con) ); 11789 ins_pipe( ialu_cr_reg_imm ); 11790 %} 11791 11792 instruct testI_reg_mem( eFlagsReg cr, rRegI src, memory mem, immI0 zero ) %{ 11793 match(Set cr (CmpI (AndI src mem) zero)); 11794 11795 format %{ "TEST $src,$mem" %} 11796 opcode(0x85); 11797 ins_encode( OpcP, RegMem( src, mem ) ); 11798 ins_pipe( ialu_cr_reg_mem ); 11799 %} 11800 11801 // Unsigned compare Instructions; really, same as signed except they 11802 // produce an eFlagsRegU instead of eFlagsReg. 11803 instruct compU_eReg(eFlagsRegU cr, rRegI op1, rRegI op2) %{ 11804 match(Set cr (CmpU op1 op2)); 11805 11806 format %{ "CMPu $op1,$op2" %} 11807 opcode(0x3B); /* Opcode 3B /r */ 11808 ins_encode( OpcP, RegReg( op1, op2) ); 11809 ins_pipe( ialu_cr_reg_reg ); 11810 %} 11811 11812 instruct compU_eReg_imm(eFlagsRegU cr, rRegI op1, immI op2) %{ 11813 match(Set cr (CmpU op1 op2)); 11814 11815 format %{ "CMPu $op1,$op2" %} 11816 opcode(0x81,0x07); /* Opcode 81 /7 */ 11817 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11818 ins_pipe( ialu_cr_reg_imm ); 11819 %} 11820 11821 // // Cisc-spilled version of cmpU_eReg 11822 instruct compU_eReg_mem(eFlagsRegU cr, rRegI op1, memory op2) %{ 11823 match(Set cr (CmpU op1 (LoadI op2))); 11824 11825 format %{ "CMPu $op1,$op2" %} 11826 ins_cost(500); 11827 opcode(0x3B); /* Opcode 3B /r */ 11828 ins_encode( OpcP, RegMem( op1, op2) ); 11829 ins_pipe( ialu_cr_reg_mem ); 11830 %} 11831 11832 // // Cisc-spilled version of cmpU_eReg 11833 //instruct compU_mem_eReg(eFlagsRegU cr, memory op1, rRegI op2) %{ 11834 // match(Set cr (CmpU (LoadI op1) op2)); 11835 // 11836 // format %{ "CMPu $op1,$op2" %} 11837 // ins_cost(500); 11838 // opcode(0x39); /* Opcode 39 /r */ 11839 // ins_encode( OpcP, RegMem( op1, op2) ); 11840 //%} 11841 11842 instruct testU_reg( eFlagsRegU cr, rRegI src, immI0 zero ) %{ 11843 match(Set cr (CmpU src zero)); 11844 11845 format %{ "TESTu $src,$src" %} 11846 opcode(0x85); 11847 ins_encode( OpcP, RegReg( src, src ) ); 11848 ins_pipe( ialu_cr_reg_imm ); 11849 %} 11850 11851 // Unsigned pointer compare Instructions 11852 instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ 11853 match(Set cr (CmpP op1 op2)); 11854 11855 format %{ "CMPu $op1,$op2" %} 11856 opcode(0x3B); /* Opcode 3B /r */ 11857 ins_encode( OpcP, RegReg( op1, op2) ); 11858 ins_pipe( ialu_cr_reg_reg ); 11859 %} 11860 11861 instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ 11862 match(Set cr (CmpP op1 op2)); 11863 11864 format %{ "CMPu $op1,$op2" %} 11865 opcode(0x81,0x07); /* Opcode 81 /7 */ 11866 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11867 ins_pipe( ialu_cr_reg_imm ); 11868 %} 11869 11870 // // Cisc-spilled version of cmpP_eReg 11871 instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ 11872 match(Set cr (CmpP op1 (LoadP op2))); 11873 11874 format %{ "CMPu $op1,$op2" %} 11875 ins_cost(500); 11876 opcode(0x3B); /* Opcode 3B /r */ 11877 ins_encode( OpcP, RegMem( op1, op2) ); 11878 ins_pipe( ialu_cr_reg_mem ); 11879 %} 11880 11881 // // Cisc-spilled version of cmpP_eReg 11882 //instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ 11883 // match(Set cr (CmpP (LoadP op1) op2)); 11884 // 11885 // format %{ "CMPu $op1,$op2" %} 11886 // ins_cost(500); 11887 // opcode(0x39); /* Opcode 39 /r */ 11888 // ins_encode( OpcP, RegMem( op1, op2) ); 11889 //%} 11890 11891 // Compare raw pointer (used in out-of-heap check). 11892 // Only works because non-oop pointers must be raw pointers 11893 // and raw pointers have no anti-dependencies. 11894 instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 11895 predicate( n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none ); 11896 match(Set cr (CmpP op1 (LoadP op2))); 11897 11898 format %{ "CMPu $op1,$op2" %} 11899 opcode(0x3B); /* Opcode 3B /r */ 11900 ins_encode( OpcP, RegMem( op1, op2) ); 11901 ins_pipe( ialu_cr_reg_mem ); 11902 %} 11903 11904 // 11905 // This will generate a signed flags result. This should be ok 11906 // since any compare to a zero should be eq/neq. 11907 instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ 11908 match(Set cr (CmpP src zero)); 11909 11910 format %{ "TEST $src,$src" %} 11911 opcode(0x85); 11912 ins_encode( OpcP, RegReg( src, src ) ); 11913 ins_pipe( ialu_cr_reg_imm ); 11914 %} 11915 11916 // Cisc-spilled version of testP_reg 11917 // This will generate a signed flags result. This should be ok 11918 // since any compare to a zero should be eq/neq. 11919 instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ 11920 match(Set cr (CmpP (LoadP op) zero)); 11921 11922 format %{ "TEST $op,0xFFFFFFFF" %} 11923 ins_cost(500); 11924 opcode(0xF7); /* Opcode F7 /0 */ 11925 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); 11926 ins_pipe( ialu_cr_reg_imm ); 11927 %} 11928 11929 // Yanked all unsigned pointer compare operations. 11930 // Pointer compares are done with CmpP which is already unsigned. 11931 11932 //----------Max and Min-------------------------------------------------------- 11933 // Min Instructions 11934 //// 11935 // *** Min and Max using the conditional move are slower than the 11936 // *** branch version on a Pentium III. 11937 // // Conditional move for min 11938 //instruct cmovI_reg_lt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ 11939 // effect( USE_DEF op2, USE op1, USE cr ); 11940 // format %{ "CMOVlt $op2,$op1\t! min" %} 11941 // opcode(0x4C,0x0F); 11942 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11943 // ins_pipe( pipe_cmov_reg ); 11944 //%} 11945 // 11946 //// Min Register with Register (P6 version) 11947 //instruct minI_eReg_p6( rRegI op1, rRegI op2 ) %{ 11948 // predicate(VM_Version::supports_cmov() ); 11949 // match(Set op2 (MinI op1 op2)); 11950 // ins_cost(200); 11951 // expand %{ 11952 // eFlagsReg cr; 11953 // compI_eReg(cr,op1,op2); 11954 // cmovI_reg_lt(op2,op1,cr); 11955 // %} 11956 //%} 11957 11958 // Min Register with Register (generic version) 11959 instruct minI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ 11960 match(Set dst (MinI dst src)); 11961 effect(KILL flags); 11962 ins_cost(300); 11963 11964 format %{ "MIN $dst,$src" %} 11965 opcode(0xCC); 11966 ins_encode( min_enc(dst,src) ); 11967 ins_pipe( pipe_slow ); 11968 %} 11969 11970 // Max Register with Register 11971 // *** Min and Max using the conditional move are slower than the 11972 // *** branch version on a Pentium III. 11973 // // Conditional move for max 11974 //instruct cmovI_reg_gt( rRegI op2, rRegI op1, eFlagsReg cr ) %{ 11975 // effect( USE_DEF op2, USE op1, USE cr ); 11976 // format %{ "CMOVgt $op2,$op1\t! max" %} 11977 // opcode(0x4F,0x0F); 11978 // ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11979 // ins_pipe( pipe_cmov_reg ); 11980 //%} 11981 // 11982 // // Max Register with Register (P6 version) 11983 //instruct maxI_eReg_p6( rRegI op1, rRegI op2 ) %{ 11984 // predicate(VM_Version::supports_cmov() ); 11985 // match(Set op2 (MaxI op1 op2)); 11986 // ins_cost(200); 11987 // expand %{ 11988 // eFlagsReg cr; 11989 // compI_eReg(cr,op1,op2); 11990 // cmovI_reg_gt(op2,op1,cr); 11991 // %} 11992 //%} 11993 11994 // Max Register with Register (generic version) 11995 instruct maxI_eReg(rRegI dst, rRegI src, eFlagsReg flags) %{ 11996 match(Set dst (MaxI dst src)); 11997 effect(KILL flags); 11998 ins_cost(300); 11999 12000 format %{ "MAX $dst,$src" %} 12001 opcode(0xCC); 12002 ins_encode( max_enc(dst,src) ); 12003 ins_pipe( pipe_slow ); 12004 %} 12005 12006 // ============================================================================ 12007 // Counted Loop limit node which represents exact final iterator value. 12008 // Note: the resulting value should fit into integer range since 12009 // counted loops have limit check on overflow. 12010 instruct loopLimit_eReg(eAXRegI limit, nadxRegI init, immI stride, eDXRegI limit_hi, nadxRegI tmp, eFlagsReg flags) %{ 12011 match(Set limit (LoopLimit (Binary init limit) stride)); 12012 effect(TEMP limit_hi, TEMP tmp, KILL flags); 12013 ins_cost(300); 12014 12015 format %{ "loopLimit $init,$limit,$stride # $limit = $init + $stride *( $limit - $init + $stride -1)/ $stride, kills $limit_hi" %} 12016 ins_encode %{ 12017 int strd = (int)$stride$$constant; 12018 assert(strd != 1 && strd != -1, "sanity"); 12019 int m1 = (strd > 0) ? 1 : -1; 12020 // Convert limit to long (EAX:EDX) 12021 __ cdql(); 12022 // Convert init to long (init:tmp) 12023 __ movl($tmp$$Register, $init$$Register); 12024 __ sarl($tmp$$Register, 31); 12025 // $limit - $init 12026 __ subl($limit$$Register, $init$$Register); 12027 __ sbbl($limit_hi$$Register, $tmp$$Register); 12028 // + ($stride - 1) 12029 if (strd > 0) { 12030 __ addl($limit$$Register, (strd - 1)); 12031 __ adcl($limit_hi$$Register, 0); 12032 __ movl($tmp$$Register, strd); 12033 } else { 12034 __ addl($limit$$Register, (strd + 1)); 12035 __ adcl($limit_hi$$Register, -1); 12036 __ lneg($limit_hi$$Register, $limit$$Register); 12037 __ movl($tmp$$Register, -strd); 12038 } 12039 // signed devision: (EAX:EDX) / pos_stride 12040 __ idivl($tmp$$Register); 12041 if (strd < 0) { 12042 // restore sign 12043 __ negl($tmp$$Register); 12044 } 12045 // (EAX) * stride 12046 __ mull($tmp$$Register); 12047 // + init (ignore upper bits) 12048 __ addl($limit$$Register, $init$$Register); 12049 %} 12050 ins_pipe( pipe_slow ); 12051 %} 12052 12053 // ============================================================================ 12054 // Branch Instructions 12055 // Jump Table 12056 instruct jumpXtnd(rRegI switch_val) %{ 12057 match(Jump switch_val); 12058 ins_cost(350); 12059 format %{ "JMP [$constantaddress](,$switch_val,1)\n\t" %} 12060 ins_encode %{ 12061 // Jump to Address(table_base + switch_reg) 12062 Address index(noreg, $switch_val$$Register, Address::times_1); 12063 __ jump(ArrayAddress($constantaddress, index)); 12064 %} 12065 ins_pipe(pipe_jmp); 12066 %} 12067 12068 // Jump Direct - Label defines a relative address from JMP+1 12069 instruct jmpDir(label labl) %{ 12070 match(Goto); 12071 effect(USE labl); 12072 12073 ins_cost(300); 12074 format %{ "JMP $labl" %} 12075 size(5); 12076 ins_encode %{ 12077 Label* L = $labl$$label; 12078 __ jmp(*L, false); // Always long jump 12079 %} 12080 ins_pipe( pipe_jmp ); 12081 %} 12082 12083 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12084 instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ 12085 match(If cop cr); 12086 effect(USE labl); 12087 12088 ins_cost(300); 12089 format %{ "J$cop $labl" %} 12090 size(6); 12091 ins_encode %{ 12092 Label* L = $labl$$label; 12093 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12094 %} 12095 ins_pipe( pipe_jcc ); 12096 %} 12097 12098 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12099 instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ 12100 match(CountedLoopEnd cop cr); 12101 effect(USE labl); 12102 12103 ins_cost(300); 12104 format %{ "J$cop $labl\t# Loop end" %} 12105 size(6); 12106 ins_encode %{ 12107 Label* L = $labl$$label; 12108 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12109 %} 12110 ins_pipe( pipe_jcc ); 12111 %} 12112 12113 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12114 instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12115 match(CountedLoopEnd cop cmp); 12116 effect(USE labl); 12117 12118 ins_cost(300); 12119 format %{ "J$cop,u $labl\t# Loop end" %} 12120 size(6); 12121 ins_encode %{ 12122 Label* L = $labl$$label; 12123 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12124 %} 12125 ins_pipe( pipe_jcc ); 12126 %} 12127 12128 instruct jmpLoopEndUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12129 match(CountedLoopEnd cop cmp); 12130 effect(USE labl); 12131 12132 ins_cost(200); 12133 format %{ "J$cop,u $labl\t# Loop end" %} 12134 size(6); 12135 ins_encode %{ 12136 Label* L = $labl$$label; 12137 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12138 %} 12139 ins_pipe( pipe_jcc ); 12140 %} 12141 12142 // Jump Direct Conditional - using unsigned comparison 12143 instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12144 match(If cop cmp); 12145 effect(USE labl); 12146 12147 ins_cost(300); 12148 format %{ "J$cop,u $labl" %} 12149 size(6); 12150 ins_encode %{ 12151 Label* L = $labl$$label; 12152 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12153 %} 12154 ins_pipe(pipe_jcc); 12155 %} 12156 12157 instruct jmpConUCF(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12158 match(If cop cmp); 12159 effect(USE labl); 12160 12161 ins_cost(200); 12162 format %{ "J$cop,u $labl" %} 12163 size(6); 12164 ins_encode %{ 12165 Label* L = $labl$$label; 12166 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump 12167 %} 12168 ins_pipe(pipe_jcc); 12169 %} 12170 12171 instruct jmpConUCF2(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 12172 match(If cop cmp); 12173 effect(USE labl); 12174 12175 ins_cost(200); 12176 format %{ $$template 12177 if ($cop$$cmpcode == Assembler::notEqual) { 12178 $$emit$$"JP,u $labl\n\t" 12179 $$emit$$"J$cop,u $labl" 12180 } else { 12181 $$emit$$"JP,u done\n\t" 12182 $$emit$$"J$cop,u $labl\n\t" 12183 $$emit$$"done:" 12184 } 12185 %} 12186 ins_encode %{ 12187 Label* l = $labl$$label; 12188 if ($cop$$cmpcode == Assembler::notEqual) { 12189 __ jcc(Assembler::parity, *l, false); 12190 __ jcc(Assembler::notEqual, *l, false); 12191 } else if ($cop$$cmpcode == Assembler::equal) { 12192 Label done; 12193 __ jccb(Assembler::parity, done); 12194 __ jcc(Assembler::equal, *l, false); 12195 __ bind(done); 12196 } else { 12197 ShouldNotReachHere(); 12198 } 12199 %} 12200 ins_pipe(pipe_jcc); 12201 %} 12202 12203 // ============================================================================ 12204 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 12205 // array for an instance of the superklass. Set a hidden internal cache on a 12206 // hit (cache is checked with exposed code in gen_subtype_check()). Return 12207 // NZ for a miss or zero for a hit. The encoding ALSO sets flags. 12208 instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ 12209 match(Set result (PartialSubtypeCheck sub super)); 12210 effect( KILL rcx, KILL cr ); 12211 12212 ins_cost(1100); // slightly larger than the next version 12213 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12214 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" 12215 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12216 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12217 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" 12218 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" 12219 "XOR $result,$result\t\t Hit: EDI zero\n\t" 12220 "miss:\t" %} 12221 12222 opcode(0x1); // Force a XOR of EDI 12223 ins_encode( enc_PartialSubtypeCheck() ); 12224 ins_pipe( pipe_slow ); 12225 %} 12226 12227 instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ 12228 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 12229 effect( KILL rcx, KILL result ); 12230 12231 ins_cost(1000); 12232 format %{ "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12233 "MOV ECX,[EDI+ArrayKlass::length]\t# length to scan\n\t" 12234 "ADD EDI,ArrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12235 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12236 "JNE,s miss\t\t# Missed: flags NZ\n\t" 12237 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" 12238 "miss:\t" %} 12239 12240 opcode(0x0); // No need to XOR EDI 12241 ins_encode( enc_PartialSubtypeCheck() ); 12242 ins_pipe( pipe_slow ); 12243 %} 12244 12245 // ============================================================================ 12246 // Branch Instructions -- short offset versions 12247 // 12248 // These instructions are used to replace jumps of a long offset (the default 12249 // match) with jumps of a shorter offset. These instructions are all tagged 12250 // with the ins_short_branch attribute, which causes the ADLC to suppress the 12251 // match rules in general matching. Instead, the ADLC generates a conversion 12252 // method in the MachNode which can be used to do in-place replacement of the 12253 // long variant with the shorter variant. The compiler will determine if a 12254 // branch can be taken by the is_short_branch_offset() predicate in the machine 12255 // specific code section of the file. 12256 12257 // Jump Direct - Label defines a relative address from JMP+1 12258 instruct jmpDir_short(label labl) %{ 12259 match(Goto); 12260 effect(USE labl); 12261 12262 ins_cost(300); 12263 format %{ "JMP,s $labl" %} 12264 size(2); 12265 ins_encode %{ 12266 Label* L = $labl$$label; 12267 __ jmpb(*L); 12268 %} 12269 ins_pipe( pipe_jmp ); 12270 ins_short_branch(1); 12271 %} 12272 12273 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12274 instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12275 match(If cop cr); 12276 effect(USE labl); 12277 12278 ins_cost(300); 12279 format %{ "J$cop,s $labl" %} 12280 size(2); 12281 ins_encode %{ 12282 Label* L = $labl$$label; 12283 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12284 %} 12285 ins_pipe( pipe_jcc ); 12286 ins_short_branch(1); 12287 %} 12288 12289 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12290 instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12291 match(CountedLoopEnd cop cr); 12292 effect(USE labl); 12293 12294 ins_cost(300); 12295 format %{ "J$cop,s $labl\t# Loop end" %} 12296 size(2); 12297 ins_encode %{ 12298 Label* L = $labl$$label; 12299 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12300 %} 12301 ins_pipe( pipe_jcc ); 12302 ins_short_branch(1); 12303 %} 12304 12305 // Jump Direct Conditional - Label defines a relative address from Jcc+1 12306 instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12307 match(CountedLoopEnd cop cmp); 12308 effect(USE labl); 12309 12310 ins_cost(300); 12311 format %{ "J$cop,us $labl\t# Loop end" %} 12312 size(2); 12313 ins_encode %{ 12314 Label* L = $labl$$label; 12315 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12316 %} 12317 ins_pipe( pipe_jcc ); 12318 ins_short_branch(1); 12319 %} 12320 12321 instruct jmpLoopEndUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12322 match(CountedLoopEnd cop cmp); 12323 effect(USE labl); 12324 12325 ins_cost(300); 12326 format %{ "J$cop,us $labl\t# Loop end" %} 12327 size(2); 12328 ins_encode %{ 12329 Label* L = $labl$$label; 12330 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12331 %} 12332 ins_pipe( pipe_jcc ); 12333 ins_short_branch(1); 12334 %} 12335 12336 // Jump Direct Conditional - using unsigned comparison 12337 instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12338 match(If cop cmp); 12339 effect(USE labl); 12340 12341 ins_cost(300); 12342 format %{ "J$cop,us $labl" %} 12343 size(2); 12344 ins_encode %{ 12345 Label* L = $labl$$label; 12346 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12347 %} 12348 ins_pipe( pipe_jcc ); 12349 ins_short_branch(1); 12350 %} 12351 12352 instruct jmpConUCF_short(cmpOpUCF cop, eFlagsRegUCF cmp, label labl) %{ 12353 match(If cop cmp); 12354 effect(USE labl); 12355 12356 ins_cost(300); 12357 format %{ "J$cop,us $labl" %} 12358 size(2); 12359 ins_encode %{ 12360 Label* L = $labl$$label; 12361 __ jccb((Assembler::Condition)($cop$$cmpcode), *L); 12362 %} 12363 ins_pipe( pipe_jcc ); 12364 ins_short_branch(1); 12365 %} 12366 12367 instruct jmpConUCF2_short(cmpOpUCF2 cop, eFlagsRegUCF cmp, label labl) %{ 12368 match(If cop cmp); 12369 effect(USE labl); 12370 12371 ins_cost(300); 12372 format %{ $$template 12373 if ($cop$$cmpcode == Assembler::notEqual) { 12374 $$emit$$"JP,u,s $labl\n\t" 12375 $$emit$$"J$cop,u,s $labl" 12376 } else { 12377 $$emit$$"JP,u,s done\n\t" 12378 $$emit$$"J$cop,u,s $labl\n\t" 12379 $$emit$$"done:" 12380 } 12381 %} 12382 size(4); 12383 ins_encode %{ 12384 Label* l = $labl$$label; 12385 if ($cop$$cmpcode == Assembler::notEqual) { 12386 __ jccb(Assembler::parity, *l); 12387 __ jccb(Assembler::notEqual, *l); 12388 } else if ($cop$$cmpcode == Assembler::equal) { 12389 Label done; 12390 __ jccb(Assembler::parity, done); 12391 __ jccb(Assembler::equal, *l); 12392 __ bind(done); 12393 } else { 12394 ShouldNotReachHere(); 12395 } 12396 %} 12397 ins_pipe(pipe_jcc); 12398 ins_short_branch(1); 12399 %} 12400 12401 // ============================================================================ 12402 // Long Compare 12403 // 12404 // Currently we hold longs in 2 registers. Comparing such values efficiently 12405 // is tricky. The flavor of compare used depends on whether we are testing 12406 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 12407 // The GE test is the negated LT test. The LE test can be had by commuting 12408 // the operands (yielding a GE test) and then negating; negate again for the 12409 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the 12410 // NE test is negated from that. 12411 12412 // Due to a shortcoming in the ADLC, it mixes up expressions like: 12413 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 12414 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections 12415 // are collapsed internally in the ADLC's dfa-gen code. The match for 12416 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 12417 // foo match ends up with the wrong leaf. One fix is to not match both 12418 // reg-reg and reg-zero forms of long-compare. This is unfortunate because 12419 // both forms beat the trinary form of long-compare and both are very useful 12420 // on Intel which has so few registers. 12421 12422 // Manifest a CmpL result in an integer register. Very painful. 12423 // This is the test to avoid. 12424 instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ 12425 match(Set dst (CmpL3 src1 src2)); 12426 effect( KILL flags ); 12427 ins_cost(1000); 12428 format %{ "XOR $dst,$dst\n\t" 12429 "CMP $src1.hi,$src2.hi\n\t" 12430 "JLT,s m_one\n\t" 12431 "JGT,s p_one\n\t" 12432 "CMP $src1.lo,$src2.lo\n\t" 12433 "JB,s m_one\n\t" 12434 "JEQ,s done\n" 12435 "p_one:\tINC $dst\n\t" 12436 "JMP,s done\n" 12437 "m_one:\tDEC $dst\n" 12438 "done:" %} 12439 ins_encode %{ 12440 Label p_one, m_one, done; 12441 __ xorptr($dst$$Register, $dst$$Register); 12442 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); 12443 __ jccb(Assembler::less, m_one); 12444 __ jccb(Assembler::greater, p_one); 12445 __ cmpl($src1$$Register, $src2$$Register); 12446 __ jccb(Assembler::below, m_one); 12447 __ jccb(Assembler::equal, done); 12448 __ bind(p_one); 12449 __ incrementl($dst$$Register); 12450 __ jmpb(done); 12451 __ bind(m_one); 12452 __ decrementl($dst$$Register); 12453 __ bind(done); 12454 %} 12455 ins_pipe( pipe_slow ); 12456 %} 12457 12458 //====== 12459 // Manifest a CmpL result in the normal flags. Only good for LT or GE 12460 // compares. Can be used for LE or GT compares by reversing arguments. 12461 // NOT GOOD FOR EQ/NE tests. 12462 instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ 12463 match( Set flags (CmpL src zero )); 12464 ins_cost(100); 12465 format %{ "TEST $src.hi,$src.hi" %} 12466 opcode(0x85); 12467 ins_encode( OpcP, RegReg_Hi2( src, src ) ); 12468 ins_pipe( ialu_cr_reg_reg ); 12469 %} 12470 12471 // Manifest a CmpL result in the normal flags. Only good for LT or GE 12472 // compares. Can be used for LE or GT compares by reversing arguments. 12473 // NOT GOOD FOR EQ/NE tests. 12474 instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, rRegI tmp ) %{ 12475 match( Set flags (CmpL src1 src2 )); 12476 effect( TEMP tmp ); 12477 ins_cost(300); 12478 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12479 "MOV $tmp,$src1.hi\n\t" 12480 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} 12481 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); 12482 ins_pipe( ialu_cr_reg_reg ); 12483 %} 12484 12485 // Long compares reg < zero/req OR reg >= zero/req. 12486 // Just a wrapper for a normal branch, plus the predicate test. 12487 instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ 12488 match(If cmp flags); 12489 effect(USE labl); 12490 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12491 expand %{ 12492 jmpCon(cmp,flags,labl); // JLT or JGE... 12493 %} 12494 %} 12495 12496 // Compare 2 longs and CMOVE longs. 12497 instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ 12498 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12499 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12500 ins_cost(400); 12501 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12502 "CMOV$cmp $dst.hi,$src.hi" %} 12503 opcode(0x0F,0x40); 12504 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12505 ins_pipe( pipe_cmov_reg_long ); 12506 %} 12507 12508 instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ 12509 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12510 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12511 ins_cost(500); 12512 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12513 "CMOV$cmp $dst.hi,$src.hi" %} 12514 opcode(0x0F,0x40); 12515 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12516 ins_pipe( pipe_cmov_reg_long ); 12517 %} 12518 12519 // Compare 2 longs and CMOVE ints. 12520 instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, rRegI src) %{ 12521 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12522 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12523 ins_cost(200); 12524 format %{ "CMOV$cmp $dst,$src" %} 12525 opcode(0x0F,0x40); 12526 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12527 ins_pipe( pipe_cmov_reg ); 12528 %} 12529 12530 instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, rRegI dst, memory src) %{ 12531 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12532 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12533 ins_cost(250); 12534 format %{ "CMOV$cmp $dst,$src" %} 12535 opcode(0x0F,0x40); 12536 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12537 ins_pipe( pipe_cmov_mem ); 12538 %} 12539 12540 // Compare 2 longs and CMOVE ints. 12541 instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ 12542 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12543 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12544 ins_cost(200); 12545 format %{ "CMOV$cmp $dst,$src" %} 12546 opcode(0x0F,0x40); 12547 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12548 ins_pipe( pipe_cmov_reg ); 12549 %} 12550 12551 // Compare 2 longs and CMOVE doubles 12552 instruct cmovDDPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regDPR dst, regDPR src) %{ 12553 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12554 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12555 ins_cost(200); 12556 expand %{ 12557 fcmovDPR_regS(cmp,flags,dst,src); 12558 %} 12559 %} 12560 12561 // Compare 2 longs and CMOVE doubles 12562 instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ 12563 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12564 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12565 ins_cost(200); 12566 expand %{ 12567 fcmovD_regS(cmp,flags,dst,src); 12568 %} 12569 %} 12570 12571 instruct cmovFFPR_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regFPR dst, regFPR src) %{ 12572 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12573 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12574 ins_cost(200); 12575 expand %{ 12576 fcmovFPR_regS(cmp,flags,dst,src); 12577 %} 12578 %} 12579 12580 instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ 12581 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12582 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12583 ins_cost(200); 12584 expand %{ 12585 fcmovF_regS(cmp,flags,dst,src); 12586 %} 12587 %} 12588 12589 //====== 12590 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12591 instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, rRegI tmp ) %{ 12592 match( Set flags (CmpL src zero )); 12593 effect(TEMP tmp); 12594 ins_cost(200); 12595 format %{ "MOV $tmp,$src.lo\n\t" 12596 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 12597 ins_encode( long_cmp_flags0( src, tmp ) ); 12598 ins_pipe( ialu_reg_reg_long ); 12599 %} 12600 12601 // Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12602 instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ 12603 match( Set flags (CmpL src1 src2 )); 12604 ins_cost(200+300); 12605 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12606 "JNE,s skip\n\t" 12607 "CMP $src1.hi,$src2.hi\n\t" 12608 "skip:\t" %} 12609 ins_encode( long_cmp_flags1( src1, src2 ) ); 12610 ins_pipe( ialu_cr_reg_reg ); 12611 %} 12612 12613 // Long compare reg == zero/reg OR reg != zero/reg 12614 // Just a wrapper for a normal branch, plus the predicate test. 12615 instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ 12616 match(If cmp flags); 12617 effect(USE labl); 12618 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12619 expand %{ 12620 jmpCon(cmp,flags,labl); // JEQ or JNE... 12621 %} 12622 %} 12623 12624 // Compare 2 longs and CMOVE longs. 12625 instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ 12626 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12627 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12628 ins_cost(400); 12629 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12630 "CMOV$cmp $dst.hi,$src.hi" %} 12631 opcode(0x0F,0x40); 12632 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12633 ins_pipe( pipe_cmov_reg_long ); 12634 %} 12635 12636 instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ 12637 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12638 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12639 ins_cost(500); 12640 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12641 "CMOV$cmp $dst.hi,$src.hi" %} 12642 opcode(0x0F,0x40); 12643 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12644 ins_pipe( pipe_cmov_reg_long ); 12645 %} 12646 12647 // Compare 2 longs and CMOVE ints. 12648 instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, rRegI src) %{ 12649 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12650 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12651 ins_cost(200); 12652 format %{ "CMOV$cmp $dst,$src" %} 12653 opcode(0x0F,0x40); 12654 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12655 ins_pipe( pipe_cmov_reg ); 12656 %} 12657 12658 instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, rRegI dst, memory src) %{ 12659 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12660 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12661 ins_cost(250); 12662 format %{ "CMOV$cmp $dst,$src" %} 12663 opcode(0x0F,0x40); 12664 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12665 ins_pipe( pipe_cmov_mem ); 12666 %} 12667 12668 // Compare 2 longs and CMOVE ints. 12669 instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ 12670 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12671 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12672 ins_cost(200); 12673 format %{ "CMOV$cmp $dst,$src" %} 12674 opcode(0x0F,0x40); 12675 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12676 ins_pipe( pipe_cmov_reg ); 12677 %} 12678 12679 // Compare 2 longs and CMOVE doubles 12680 instruct cmovDDPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regDPR dst, regDPR src) %{ 12681 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12682 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12683 ins_cost(200); 12684 expand %{ 12685 fcmovDPR_regS(cmp,flags,dst,src); 12686 %} 12687 %} 12688 12689 // Compare 2 longs and CMOVE doubles 12690 instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ 12691 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12692 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12693 ins_cost(200); 12694 expand %{ 12695 fcmovD_regS(cmp,flags,dst,src); 12696 %} 12697 %} 12698 12699 instruct cmovFFPR_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regFPR dst, regFPR src) %{ 12700 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12701 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12702 ins_cost(200); 12703 expand %{ 12704 fcmovFPR_regS(cmp,flags,dst,src); 12705 %} 12706 %} 12707 12708 instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ 12709 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12710 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12711 ins_cost(200); 12712 expand %{ 12713 fcmovF_regS(cmp,flags,dst,src); 12714 %} 12715 %} 12716 12717 //====== 12718 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12719 // Same as cmpL_reg_flags_LEGT except must negate src 12720 instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, rRegI tmp ) %{ 12721 match( Set flags (CmpL src zero )); 12722 effect( TEMP tmp ); 12723 ins_cost(300); 12724 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 12725 "CMP $tmp,$src.lo\n\t" 12726 "SBB $tmp,$src.hi\n\t" %} 12727 ins_encode( long_cmp_flags3(src, tmp) ); 12728 ins_pipe( ialu_reg_reg_long ); 12729 %} 12730 12731 // Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12732 // Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 12733 // requires a commuted test to get the same result. 12734 instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, rRegI tmp ) %{ 12735 match( Set flags (CmpL src1 src2 )); 12736 effect( TEMP tmp ); 12737 ins_cost(300); 12738 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 12739 "MOV $tmp,$src2.hi\n\t" 12740 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} 12741 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); 12742 ins_pipe( ialu_cr_reg_reg ); 12743 %} 12744 12745 // Long compares reg < zero/req OR reg >= zero/req. 12746 // Just a wrapper for a normal branch, plus the predicate test 12747 instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ 12748 match(If cmp flags); 12749 effect(USE labl); 12750 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); 12751 ins_cost(300); 12752 expand %{ 12753 jmpCon(cmp,flags,labl); // JGT or JLE... 12754 %} 12755 %} 12756 12757 // Compare 2 longs and CMOVE longs. 12758 instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ 12759 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12760 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12761 ins_cost(400); 12762 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12763 "CMOV$cmp $dst.hi,$src.hi" %} 12764 opcode(0x0F,0x40); 12765 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12766 ins_pipe( pipe_cmov_reg_long ); 12767 %} 12768 12769 instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ 12770 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12771 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12772 ins_cost(500); 12773 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12774 "CMOV$cmp $dst.hi,$src.hi+4" %} 12775 opcode(0x0F,0x40); 12776 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12777 ins_pipe( pipe_cmov_reg_long ); 12778 %} 12779 12780 // Compare 2 longs and CMOVE ints. 12781 instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, rRegI src) %{ 12782 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12783 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12784 ins_cost(200); 12785 format %{ "CMOV$cmp $dst,$src" %} 12786 opcode(0x0F,0x40); 12787 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12788 ins_pipe( pipe_cmov_reg ); 12789 %} 12790 12791 instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, rRegI dst, memory src) %{ 12792 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12793 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12794 ins_cost(250); 12795 format %{ "CMOV$cmp $dst,$src" %} 12796 opcode(0x0F,0x40); 12797 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12798 ins_pipe( pipe_cmov_mem ); 12799 %} 12800 12801 // Compare 2 longs and CMOVE ptrs. 12802 instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ 12803 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12804 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12805 ins_cost(200); 12806 format %{ "CMOV$cmp $dst,$src" %} 12807 opcode(0x0F,0x40); 12808 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12809 ins_pipe( pipe_cmov_reg ); 12810 %} 12811 12812 // Compare 2 longs and CMOVE doubles 12813 instruct cmovDDPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regDPR dst, regDPR src) %{ 12814 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12815 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12816 ins_cost(200); 12817 expand %{ 12818 fcmovDPR_regS(cmp,flags,dst,src); 12819 %} 12820 %} 12821 12822 // Compare 2 longs and CMOVE doubles 12823 instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ 12824 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12825 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12826 ins_cost(200); 12827 expand %{ 12828 fcmovD_regS(cmp,flags,dst,src); 12829 %} 12830 %} 12831 12832 instruct cmovFFPR_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regFPR dst, regFPR src) %{ 12833 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12834 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12835 ins_cost(200); 12836 expand %{ 12837 fcmovFPR_regS(cmp,flags,dst,src); 12838 %} 12839 %} 12840 12841 12842 instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ 12843 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12844 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12845 ins_cost(200); 12846 expand %{ 12847 fcmovF_regS(cmp,flags,dst,src); 12848 %} 12849 %} 12850 12851 12852 // ============================================================================ 12853 // Procedure Call/Return Instructions 12854 // Call Java Static Instruction 12855 // Note: If this code changes, the corresponding ret_addr_offset() and 12856 // compute_padding() functions will have to be adjusted. 12857 instruct CallStaticJavaDirect(method meth) %{ 12858 match(CallStaticJava); 12859 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 12860 effect(USE meth); 12861 12862 ins_cost(300); 12863 format %{ "CALL,static " %} 12864 opcode(0xE8); /* E8 cd */ 12865 ins_encode( pre_call_FPU, 12866 Java_Static_Call( meth ), 12867 call_epilog, 12868 post_call_FPU ); 12869 ins_pipe( pipe_slow ); 12870 ins_alignment(4); 12871 %} 12872 12873 // Call Java Static Instruction (method handle version) 12874 // Note: If this code changes, the corresponding ret_addr_offset() and 12875 // compute_padding() functions will have to be adjusted. 12876 instruct CallStaticJavaHandle(method meth, eBPRegP ebp_mh_SP_save) %{ 12877 match(CallStaticJava); 12878 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 12879 effect(USE meth); 12880 // EBP is saved by all callees (for interpreter stack correction). 12881 // We use it here for a similar purpose, in {preserve,restore}_SP. 12882 12883 ins_cost(300); 12884 format %{ "CALL,static/MethodHandle " %} 12885 opcode(0xE8); /* E8 cd */ 12886 ins_encode( pre_call_FPU, 12887 preserve_SP, 12888 Java_Static_Call( meth ), 12889 restore_SP, 12890 call_epilog, 12891 post_call_FPU ); 12892 ins_pipe( pipe_slow ); 12893 ins_alignment(4); 12894 %} 12895 12896 // Call Java Dynamic Instruction 12897 // Note: If this code changes, the corresponding ret_addr_offset() and 12898 // compute_padding() functions will have to be adjusted. 12899 instruct CallDynamicJavaDirect(method meth) %{ 12900 match(CallDynamicJava); 12901 effect(USE meth); 12902 12903 ins_cost(300); 12904 format %{ "MOV EAX,(oop)-1\n\t" 12905 "CALL,dynamic" %} 12906 opcode(0xE8); /* E8 cd */ 12907 ins_encode( pre_call_FPU, 12908 Java_Dynamic_Call( meth ), 12909 call_epilog, 12910 post_call_FPU ); 12911 ins_pipe( pipe_slow ); 12912 ins_alignment(4); 12913 %} 12914 12915 // Call Runtime Instruction 12916 instruct CallRuntimeDirect(method meth) %{ 12917 match(CallRuntime ); 12918 effect(USE meth); 12919 12920 ins_cost(300); 12921 format %{ "CALL,runtime " %} 12922 opcode(0xE8); /* E8 cd */ 12923 // Use FFREEs to clear entries in float stack 12924 ins_encode( pre_call_FPU, 12925 FFree_Float_Stack_All, 12926 Java_To_Runtime( meth ), 12927 post_call_FPU ); 12928 ins_pipe( pipe_slow ); 12929 %} 12930 12931 // Call runtime without safepoint 12932 instruct CallLeafDirect(method meth) %{ 12933 match(CallLeaf); 12934 effect(USE meth); 12935 12936 ins_cost(300); 12937 format %{ "CALL_LEAF,runtime " %} 12938 opcode(0xE8); /* E8 cd */ 12939 ins_encode( pre_call_FPU, 12940 FFree_Float_Stack_All, 12941 Java_To_Runtime( meth ), 12942 Verify_FPU_For_Leaf, post_call_FPU ); 12943 ins_pipe( pipe_slow ); 12944 %} 12945 12946 instruct CallLeafNoFPDirect(method meth) %{ 12947 match(CallLeafNoFP); 12948 effect(USE meth); 12949 12950 ins_cost(300); 12951 format %{ "CALL_LEAF_NOFP,runtime " %} 12952 opcode(0xE8); /* E8 cd */ 12953 ins_encode(Java_To_Runtime(meth)); 12954 ins_pipe( pipe_slow ); 12955 %} 12956 12957 12958 // Return Instruction 12959 // Remove the return address & jump to it. 12960 instruct Ret() %{ 12961 match(Return); 12962 format %{ "RET" %} 12963 opcode(0xC3); 12964 ins_encode(OpcP); 12965 ins_pipe( pipe_jmp ); 12966 %} 12967 12968 // Tail Call; Jump from runtime stub to Java code. 12969 // Also known as an 'interprocedural jump'. 12970 // Target of jump will eventually return to caller. 12971 // TailJump below removes the return address. 12972 instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ 12973 match(TailCall jump_target method_oop ); 12974 ins_cost(300); 12975 format %{ "JMP $jump_target \t# EBX holds method oop" %} 12976 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12977 ins_encode( OpcP, RegOpc(jump_target) ); 12978 ins_pipe( pipe_jmp ); 12979 %} 12980 12981 12982 // Tail Jump; remove the return address; jump to target. 12983 // TailCall above leaves the return address around. 12984 instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ 12985 match( TailJump jump_target ex_oop ); 12986 ins_cost(300); 12987 format %{ "POP EDX\t# pop return address into dummy\n\t" 12988 "JMP $jump_target " %} 12989 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12990 ins_encode( enc_pop_rdx, 12991 OpcP, RegOpc(jump_target) ); 12992 ins_pipe( pipe_jmp ); 12993 %} 12994 12995 // Create exception oop: created by stack-crawling runtime code. 12996 // Created exception is now available to this handler, and is setup 12997 // just prior to jumping to this handler. No code emitted. 12998 instruct CreateException( eAXRegP ex_oop ) 12999 %{ 13000 match(Set ex_oop (CreateEx)); 13001 13002 size(0); 13003 // use the following format syntax 13004 format %{ "# exception oop is in EAX; no code emitted" %} 13005 ins_encode(); 13006 ins_pipe( empty ); 13007 %} 13008 13009 13010 // Rethrow exception: 13011 // The exception oop will come in the first argument position. 13012 // Then JUMP (not call) to the rethrow stub code. 13013 instruct RethrowException() 13014 %{ 13015 match(Rethrow); 13016 13017 // use the following format syntax 13018 format %{ "JMP rethrow_stub" %} 13019 ins_encode(enc_rethrow); 13020 ins_pipe( pipe_jmp ); 13021 %} 13022 13023 // inlined locking and unlocking 13024 13025 13026 instruct cmpFastLock( eFlagsReg cr, eRegP object, eBXRegP box, eAXRegI tmp, eRegP scr) %{ 13027 match( Set cr (FastLock object box) ); 13028 effect( TEMP tmp, TEMP scr, USE_KILL box ); 13029 ins_cost(300); 13030 format %{ "FASTLOCK $object,$box\t! kills $box,$tmp,$scr" %} 13031 ins_encode( Fast_Lock(object,box,tmp,scr) ); 13032 ins_pipe( pipe_slow ); 13033 %} 13034 13035 instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ 13036 match( Set cr (FastUnlock object box) ); 13037 effect( TEMP tmp, USE_KILL box ); 13038 ins_cost(300); 13039 format %{ "FASTUNLOCK $object,$box\t! kills $box,$tmp" %} 13040 ins_encode( Fast_Unlock(object,box,tmp) ); 13041 ins_pipe( pipe_slow ); 13042 %} 13043 13044 13045 13046 // ============================================================================ 13047 // Safepoint Instruction 13048 instruct safePoint_poll(eFlagsReg cr) %{ 13049 match(SafePoint); 13050 effect(KILL cr); 13051 13052 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. 13053 // On SPARC that might be acceptable as we can generate the address with 13054 // just a sethi, saving an or. By polling at offset 0 we can end up 13055 // putting additional pressure on the index-0 in the D$. Because of 13056 // alignment (just like the situation at hand) the lower indices tend 13057 // to see more traffic. It'd be better to change the polling address 13058 // to offset 0 of the last $line in the polling page. 13059 13060 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} 13061 ins_cost(125); 13062 size(6) ; 13063 ins_encode( Safepoint_Poll() ); 13064 ins_pipe( ialu_reg_mem ); 13065 %} 13066 13067 13068 // ============================================================================ 13069 // This name is KNOWN by the ADLC and cannot be changed. 13070 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type 13071 // for this guy. 13072 instruct tlsLoadP(eRegP dst, eFlagsReg cr) %{ 13073 match(Set dst (ThreadLocal)); 13074 effect(DEF dst, KILL cr); 13075 13076 format %{ "MOV $dst, Thread::current()" %} 13077 ins_encode %{ 13078 Register dstReg = as_Register($dst$$reg); 13079 __ get_thread(dstReg); 13080 %} 13081 ins_pipe( ialu_reg_fat ); 13082 %} 13083 13084 13085 13086 //----------PEEPHOLE RULES----------------------------------------------------- 13087 // These must follow all instruction definitions as they use the names 13088 // defined in the instructions definitions. 13089 // 13090 // peepmatch ( root_instr_name [preceding_instruction]* ); 13091 // 13092 // peepconstraint %{ 13093 // (instruction_number.operand_name relational_op instruction_number.operand_name 13094 // [, ...] ); 13095 // // instruction numbers are zero-based using left to right order in peepmatch 13096 // 13097 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 13098 // // provide an instruction_number.operand_name for each operand that appears 13099 // // in the replacement instruction's match rule 13100 // 13101 // ---------VM FLAGS--------------------------------------------------------- 13102 // 13103 // All peephole optimizations can be turned off using -XX:-OptoPeephole 13104 // 13105 // Each peephole rule is given an identifying number starting with zero and 13106 // increasing by one in the order seen by the parser. An individual peephole 13107 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 13108 // on the command-line. 13109 // 13110 // ---------CURRENT LIMITATIONS---------------------------------------------- 13111 // 13112 // Only match adjacent instructions in same basic block 13113 // Only equality constraints 13114 // Only constraints between operands, not (0.dest_reg == EAX_enc) 13115 // Only one replacement instruction 13116 // 13117 // ---------EXAMPLE---------------------------------------------------------- 13118 // 13119 // // pertinent parts of existing instructions in architecture description 13120 // instruct movI(rRegI dst, rRegI src) %{ 13121 // match(Set dst (CopyI src)); 13122 // %} 13123 // 13124 // instruct incI_eReg(rRegI dst, immI1 src, eFlagsReg cr) %{ 13125 // match(Set dst (AddI dst src)); 13126 // effect(KILL cr); 13127 // %} 13128 // 13129 // // Change (inc mov) to lea 13130 // peephole %{ 13131 // // increment preceeded by register-register move 13132 // peepmatch ( incI_eReg movI ); 13133 // // require that the destination register of the increment 13134 // // match the destination register of the move 13135 // peepconstraint ( 0.dst == 1.dst ); 13136 // // construct a replacement instruction that sets 13137 // // the destination to ( move's source register + one ) 13138 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13139 // %} 13140 // 13141 // Implementation no longer uses movX instructions since 13142 // machine-independent system no longer uses CopyX nodes. 13143 // 13144 // peephole %{ 13145 // peepmatch ( incI_eReg movI ); 13146 // peepconstraint ( 0.dst == 1.dst ); 13147 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13148 // %} 13149 // 13150 // peephole %{ 13151 // peepmatch ( decI_eReg movI ); 13152 // peepconstraint ( 0.dst == 1.dst ); 13153 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13154 // %} 13155 // 13156 // peephole %{ 13157 // peepmatch ( addI_eReg_imm movI ); 13158 // peepconstraint ( 0.dst == 1.dst ); 13159 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 13160 // %} 13161 // 13162 // peephole %{ 13163 // peepmatch ( addP_eReg_imm movP ); 13164 // peepconstraint ( 0.dst == 1.dst ); 13165 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 13166 // %} 13167 13168 // // Change load of spilled value to only a spill 13169 // instruct storeI(memory mem, rRegI src) %{ 13170 // match(Set mem (StoreI mem src)); 13171 // %} 13172 // 13173 // instruct loadI(rRegI dst, memory mem) %{ 13174 // match(Set dst (LoadI mem)); 13175 // %} 13176 // 13177 peephole %{ 13178 peepmatch ( loadI storeI ); 13179 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 13180 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 13181 %} 13182 13183 //----------SMARTSPILL RULES--------------------------------------------------- 13184 // These must follow all instruction definitions as they use the names 13185 // defined in the instructions definitions.