931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if( !OptoReg::is_valid(reg) ) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1354 if (cbuf) {
1355 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1356 }
1357 #ifndef PRODUCT
1358 else if (!do_size) {
1359 if (size != 0) st->print("\n\t");
1360 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1361 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1362 }
1363 #endif
1364 return size+4;
1365 }
1366
1367 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1368 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1369 #ifndef PRODUCT
1370 else if( !do_size ) {
1371 if( size != 0 ) st->print("\n\t");
1372 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1373 }
1374 #endif
1375 return size+4;
1376 }
1377
1378 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1379 PhaseRegAlloc *ra_,
1380 bool do_size,
1381 outputStream* st ) const {
1382 // Get registers to move
1383 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1384 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1385 OptoReg::Name dst_second = ra_->get_reg_second(this );
1386 OptoReg::Name dst_first = ra_->get_reg_first(this );
1387
1388 enum RC src_second_rc = rc_class(src_second);
1389 enum RC src_first_rc = rc_class(src_first);
1390 enum RC dst_second_rc = rc_class(dst_second);
1391 enum RC dst_first_rc = rc_class(dst_first);
1392
1393 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1394
1395 // Generate spill code!
1396 int size = 0;
1397
1398 if( src_first == dst_first && src_second == dst_second )
1399 return size; // Self copy, no move
1400
1401 // --------------------------------------
1402 // Check for mem-mem move. Load into unused float registers and fall into
1403 // the float-store case.
1404 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1405 int offset = ra_->reg2offset(src_first);
1406 // Further check for aligned-adjacent pair, so we can use a double load
1407 if( (src_first&1)==0 && src_first+1 == src_second ) {
1408 src_second = OptoReg::Name(R_F31_num);
1409 src_second_rc = rc_float;
1410 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1411 } else {
1412 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1413 }
1414 src_first = OptoReg::Name(R_F30_num);
1415 src_first_rc = rc_float;
1416 }
1417
1418 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1419 int offset = ra_->reg2offset(src_second);
1420 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 }
1424
1425 // --------------------------------------
1426 // Check for float->int copy; requires a trip through memory
1427 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1428 int offset = frame::register_save_words*wordSize;
1429 if (cbuf) {
1430 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1431 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1432 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1433 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1434 }
1435 #ifndef PRODUCT
1436 else if (!do_size) {
1437 if (size != 0) st->print("\n\t");
1438 st->print( "SUB R_SP,16,R_SP\n");
1439 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1440 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1441 st->print("\tADD R_SP,16,R_SP\n");
1442 }
1443 #endif
1444 size += 16;
1445 }
1446
1447 // Check for float->int copy on T4
1448 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1449 // Further check for aligned-adjacent pair, so we can use a double move
1450 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1451 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1452 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1453 }
1454 // Check for int->float copy on T4
1455 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1456 // Further check for aligned-adjacent pair, so we can use a double move
1457 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1458 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1459 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1460 }
1461
1462 // --------------------------------------
1463 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1464 // In such cases, I have to do the big-endian swap. For aligned targets, the
1465 // hardware does the flop for me. Doubles are always aligned, so no problem
1466 // there. Misaligned sources only come from native-long-returns (handled
1467 // special below).
1468 #ifndef _LP64
1469 if( src_first_rc == rc_int && // source is already big-endian
1470 src_second_rc != rc_bad && // 64-bit move
1471 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1472 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1473 // Do the big-endian flop.
1474 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1475 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1476 }
1477 #endif
1478
1479 // --------------------------------------
1480 // Check for integer reg-reg copy
1481 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1482 #ifndef _LP64
1483 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1484 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1485 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1486 // operand contains the least significant word of the 64-bit value and vice versa.
1487 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1488 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1489 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1490 if( cbuf ) {
1491 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1492 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1493 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1494 #ifndef PRODUCT
1495 } else if( !do_size ) {
1496 if( size != 0 ) st->print("\n\t");
1497 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1498 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1499 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1500 #endif
1501 }
1502 return size+12;
1503 }
1504 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1505 // returning a long value in I0/I1
1506 // a SpillCopy must be able to target a return instruction's reg_class
1507 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1508 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1509 // operand contains the least significant word of the 64-bit value and vice versa.
1510 OptoReg::Name tdest = dst_first;
1511
1512 if (src_first == dst_first) {
1513 tdest = OptoReg::Name(R_O7_num);
1514 size += 4;
1515 }
1516
1517 if( cbuf ) {
1518 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1519 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1520 // ShrL_reg_imm6
1521 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1522 // ShrR_reg_imm6 src, 0, dst
1523 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1524 if (tdest != dst_first) {
1525 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1526 }
1527 }
1528 #ifndef PRODUCT
1529 else if( !do_size ) {
1530 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1531 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1532 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1533 if (tdest != dst_first) {
1534 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1535 }
1536 }
1537 #endif // PRODUCT
1538 return size+8;
1539 }
1540 #endif // !_LP64
1541 // Else normal reg-reg copy
1542 assert( src_second != dst_first, "smashed second before evacuating it" );
1543 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1544 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1545 // This moves an aligned adjacent pair.
1546 // See if we are done.
1547 if( src_first+1 == src_second && dst_first+1 == dst_second )
1548 return size;
1549 }
1550
1551 // Check for integer store
1552 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1553 int offset = ra_->reg2offset(dst_first);
1554 // Further check for aligned-adjacent pair, so we can use a double store
1555 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1556 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1557 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1558 }
1559
1560 // Check for integer load
1561 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1562 int offset = ra_->reg2offset(src_first);
1563 // Further check for aligned-adjacent pair, so we can use a double load
1564 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1565 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1566 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1567 }
1568
1569 // Check for float reg-reg copy
1570 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1571 // Further check for aligned-adjacent pair, so we can use a double move
1572 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1573 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1574 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1575 }
1576
1577 // Check for float store
1578 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1579 int offset = ra_->reg2offset(dst_first);
1580 // Further check for aligned-adjacent pair, so we can use a double store
1581 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1582 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1583 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1584 }
1585
1586 // Check for float load
1587 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1588 int offset = ra_->reg2offset(src_first);
1589 // Further check for aligned-adjacent pair, so we can use a double load
1590 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1591 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1592 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1593 }
1594
1595 // --------------------------------------------------------------------
1596 // Check for hi bits still needing moving. Only happens for misaligned
1597 // arguments to native calls.
1598 if( src_second == dst_second )
1599 return size; // Self copy; no move
1600 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1601
1602 #ifndef _LP64
1603 // In the LP64 build, all registers can be moved as aligned/adjacent
1604 // pairs, so there's never any need to move the high bits separately.
1605 // The 32-bit builds have to deal with the 32-bit ABI which can force
1606 // all sorts of silly alignment problems.
1607
1608 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1609 // 32-bits of a 64-bit register, but are needed in low bits of another
1610 // register (else it's a hi-bits-to-hi-bits copy which should have
1611 // happened already as part of a 64-bit move)
1612 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1613 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1614 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1615 // Shift src_second down to dst_second's low bits.
1616 if( cbuf ) {
1617 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1618 #ifndef PRODUCT
1619 } else if( !do_size ) {
1620 if( size != 0 ) st->print("\n\t");
1621 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1622 #endif
1623 }
1624 return size+4;
1625 }
1626
1627 // Check for high word integer store. Must down-shift the hi bits
1628 // into a temp register, then fall into the case of storing int bits.
1629 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1630 // Shift src_second down to dst_second's low bits.
1631 if( cbuf ) {
1632 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1633 #ifndef PRODUCT
1634 } else if( !do_size ) {
1635 if( size != 0 ) st->print("\n\t");
1636 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1637 #endif
1638 }
1639 size+=4;
1640 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1641 }
1642
1643 // Check for high word integer load
1644 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1646
1647 // Check for high word integer store
1648 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1650
1651 // Check for high word float store
1652 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1653 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1654
1655 #endif // !_LP64
1656
1657 Unimplemented();
1658 return 0;
1659 }
1660
1661 #ifndef PRODUCT
1662 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1663 implementation( NULL, ra_, false, st );
1664 }
1665 #endif
1666
1667 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1668 implementation( &cbuf, ra_, false, NULL );
1669 }
1670
1671 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1672 return implementation( NULL, ra_, true, NULL );
1673 }
1674
1675 //=============================================================================
1676 #ifndef PRODUCT
1677 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1678 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1679 }
1680 #endif
1681
1682 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1683 MacroAssembler _masm(&cbuf);
1684 for(int i = 0; i < _count; i += 1) {
1685 __ nop();
1686 }
1687 }
1688
1689 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1690 return 4 * _count;
1691 }
1692
1693
1694 //=============================================================================
1695 #ifndef PRODUCT
1696 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1697 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1698 int reg = ra_->get_reg_first(this);
1699 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1700 }
1701 #endif
1702
1703 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1704 MacroAssembler _masm(&cbuf);
5180 src2 : E(read);
5181 srcdst : E(read);
5182 IALU : R;
5183 BR : R;
5184 %}
5185
5186 // Define the class for the Nop node
5187 define %{
5188 MachNop = ialu_nop;
5189 %}
5190
5191 %}
5192
5193 //----------INSTRUCTIONS-------------------------------------------------------
5194
5195 //------------Special Stack Slot instructions - no match rules-----------------
5196 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5197 // No match rule to avoid chain rule match.
5198 effect(DEF dst, USE src);
5199 ins_cost(MEMORY_REF_COST);
5200 size(4);
5201 format %{ "LDF $src,$dst\t! stkI to regF" %}
5202 opcode(Assembler::ldf_op3);
5203 ins_encode(simple_form3_mem_reg(src, dst));
5204 ins_pipe(floadF_stk);
5205 %}
5206
5207 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5208 // No match rule to avoid chain rule match.
5209 effect(DEF dst, USE src);
5210 ins_cost(MEMORY_REF_COST);
5211 size(4);
5212 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5213 opcode(Assembler::lddf_op3);
5214 ins_encode(simple_form3_mem_reg(src, dst));
5215 ins_pipe(floadD_stk);
5216 %}
5217
5218 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5219 // No match rule to avoid chain rule match.
5220 effect(DEF dst, USE src);
5221 ins_cost(MEMORY_REF_COST);
5222 size(4);
5223 format %{ "STF $src,$dst\t! regF to stkI" %}
5224 opcode(Assembler::stf_op3);
5225 ins_encode(simple_form3_mem_reg(dst, src));
5226 ins_pipe(fstoreF_stk_reg);
5227 %}
5228
5229 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5230 // No match rule to avoid chain rule match.
5231 effect(DEF dst, USE src);
5232 ins_cost(MEMORY_REF_COST);
5233 size(4);
5234 format %{ "STDF $src,$dst\t! regD to stkL" %}
5235 opcode(Assembler::stdf_op3);
5236 ins_encode(simple_form3_mem_reg(dst, src));
5237 ins_pipe(fstoreD_stk_reg);
5238 %}
5239
5240 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5241 effect(DEF dst, USE src);
5242 ins_cost(MEMORY_REF_COST*2);
5243 size(8);
5244 format %{ "STW $src,$dst.hi\t! long\n\t"
5245 "STW R_G0,$dst.lo" %}
5246 opcode(Assembler::stw_op3);
5247 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5248 ins_pipe(lstoreI_stk_reg);
5249 %}
5250
5251 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5252 // No match rule to avoid chain rule match.
5253 effect(DEF dst, USE src);
5254 ins_cost(MEMORY_REF_COST);
5255 size(4);
5256 format %{ "STX $src,$dst\t! regL to stkD" %}
5257 opcode(Assembler::stx_op3);
5258 ins_encode(simple_form3_mem_reg( dst, src ) );
5259 ins_pipe(istore_stk_reg);
5260 %}
5261
5262 //---------- Chain stack slots between similar types --------
5263
5264 // Load integer from stack slot
5265 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5266 match(Set dst src);
5267 ins_cost(MEMORY_REF_COST);
5268
5269 size(4);
5270 format %{ "LDUW $src,$dst\t!stk" %}
5271 opcode(Assembler::lduw_op3);
5272 ins_encode(simple_form3_mem_reg( src, dst ) );
5273 ins_pipe(iload_mem);
5274 %}
5275
5276 // Store integer to stack slot
5277 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5278 match(Set dst src);
5279 ins_cost(MEMORY_REF_COST);
5280
5281 size(4);
5282 format %{ "STW $src,$dst\t!stk" %}
5283 opcode(Assembler::stw_op3);
5284 ins_encode(simple_form3_mem_reg( dst, src ) );
5285 ins_pipe(istore_mem_reg);
5286 %}
5287
5288 // Load long from stack slot
5289 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5290 match(Set dst src);
5291
5292 ins_cost(MEMORY_REF_COST);
5293 size(4);
5294 format %{ "LDX $src,$dst\t! long" %}
5295 opcode(Assembler::ldx_op3);
5296 ins_encode(simple_form3_mem_reg( src, dst ) );
5297 ins_pipe(iload_mem);
5298 %}
5299
5300 // Store long to stack slot
5301 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5302 match(Set dst src);
5303
5304 ins_cost(MEMORY_REF_COST);
5305 size(4);
5306 format %{ "STX $src,$dst\t! long" %}
5307 opcode(Assembler::stx_op3);
5308 ins_encode(simple_form3_mem_reg( dst, src ) );
5309 ins_pipe(istore_mem_reg);
5310 %}
5311
5312 #ifdef _LP64
5313 // Load pointer from stack slot, 64-bit encoding
5314 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5315 match(Set dst src);
5316 ins_cost(MEMORY_REF_COST);
5317 size(4);
5318 format %{ "LDX $src,$dst\t!ptr" %}
5319 opcode(Assembler::ldx_op3);
5320 ins_encode(simple_form3_mem_reg( src, dst ) );
5321 ins_pipe(iload_mem);
5322 %}
5323
5324 // Store pointer to stack slot
5325 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5326 match(Set dst src);
5327 ins_cost(MEMORY_REF_COST);
5328 size(4);
5329 format %{ "STX $src,$dst\t!ptr" %}
5330 opcode(Assembler::stx_op3);
5331 ins_encode(simple_form3_mem_reg( dst, src ) );
5332 ins_pipe(istore_mem_reg);
5333 %}
5334 #else // _LP64
5335 // Load pointer from stack slot, 32-bit encoding
5336 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5337 match(Set dst src);
5338 ins_cost(MEMORY_REF_COST);
5339 format %{ "LDUW $src,$dst\t!ptr" %}
5340 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5341 ins_encode(simple_form3_mem_reg( src, dst ) );
5342 ins_pipe(iload_mem);
5343 %}
5344
5345 // Store pointer to stack slot
5346 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5347 match(Set dst src);
5348 ins_cost(MEMORY_REF_COST);
5754 %}
5755
5756 // Load Long - aligned
5757 instruct loadL(iRegL dst, memory mem ) %{
5758 match(Set dst (LoadL mem));
5759 ins_cost(MEMORY_REF_COST);
5760
5761 size(4);
5762 format %{ "LDX $mem,$dst\t! long" %}
5763 ins_encode %{
5764 __ ldx($mem$$Address, $dst$$Register);
5765 %}
5766 ins_pipe(iload_mem);
5767 %}
5768
5769 // Load Long - UNaligned
5770 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5771 match(Set dst (LoadL_unaligned mem));
5772 effect(KILL tmp);
5773 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5774 size(16);
5775 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5776 "\tLDUW $mem ,$dst\n"
5777 "\tSLLX #32, $dst, $dst\n"
5778 "\tOR $dst, R_O7, $dst" %}
5779 opcode(Assembler::lduw_op3);
5780 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5781 ins_pipe(iload_mem);
5782 %}
5783
5784 // Load Range
5785 instruct loadRange(iRegI dst, memory mem) %{
5786 match(Set dst (LoadRange mem));
5787 ins_cost(MEMORY_REF_COST);
5788
5789 size(4);
5790 format %{ "LDUW $mem,$dst\t! range" %}
5791 opcode(Assembler::lduw_op3);
5792 ins_encode(simple_form3_mem_reg( mem, dst ) );
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Integer into %f register (for fitos/fitod)
5797 instruct loadI_freg(regF dst, memory mem) %{
5798 match(Set dst (LoadI mem));
5799 ins_cost(MEMORY_REF_COST);
5800 size(4);
5801
5802 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5803 opcode(Assembler::ldf_op3);
5804 ins_encode(simple_form3_mem_reg( mem, dst ) );
5805 ins_pipe(floadF_mem);
5806 %}
5807
5808 // Load Pointer
5809 instruct loadP(iRegP dst, memory mem) %{
5810 match(Set dst (LoadP mem));
5811 ins_cost(MEMORY_REF_COST);
5812 size(4);
5813
5814 #ifndef _LP64
5815 format %{ "LDUW $mem,$dst\t! ptr" %}
5816 ins_encode %{
5817 __ lduw($mem$$Address, $dst$$Register);
5818 %}
5819 #else
5820 format %{ "LDX $mem,$dst\t! ptr" %}
5859 %}
5860
5861 // Load narrow Klass Pointer
5862 instruct loadNKlass(iRegN dst, memory mem) %{
5863 match(Set dst (LoadNKlass mem));
5864 ins_cost(MEMORY_REF_COST);
5865 size(4);
5866
5867 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5868 ins_encode %{
5869 __ lduw($mem$$Address, $dst$$Register);
5870 %}
5871 ins_pipe(iload_mem);
5872 %}
5873
5874 // Load Double
5875 instruct loadD(regD dst, memory mem) %{
5876 match(Set dst (LoadD mem));
5877 ins_cost(MEMORY_REF_COST);
5878
5879 size(4);
5880 format %{ "LDDF $mem,$dst" %}
5881 opcode(Assembler::lddf_op3);
5882 ins_encode(simple_form3_mem_reg( mem, dst ) );
5883 ins_pipe(floadD_mem);
5884 %}
5885
5886 // Load Double - UNaligned
5887 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5888 match(Set dst (LoadD_unaligned mem));
5889 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5890 size(8);
5891 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5892 "\tLDF $mem+4,$dst.lo\t!" %}
5893 opcode(Assembler::ldf_op3);
5894 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5895 ins_pipe(iload_mem);
5896 %}
5897
5898 // Load Float
5899 instruct loadF(regF dst, memory mem) %{
5900 match(Set dst (LoadF mem));
5901 ins_cost(MEMORY_REF_COST);
5902
5903 size(4);
5904 format %{ "LDF $mem,$dst" %}
5905 opcode(Assembler::ldf_op3);
5906 ins_encode(simple_form3_mem_reg( mem, dst ) );
5907 ins_pipe(floadF_mem);
5908 %}
5909
5910 // Load Constant
5911 instruct loadConI( iRegI dst, immI src ) %{
5912 match(Set dst src);
5913 ins_cost(DEFAULT_COST * 3/2);
5914 format %{ "SET $src,$dst" %}
5915 ins_encode( Set32(src, dst) );
5916 ins_pipe(ialu_hi_lo_reg);
5917 %}
5918
5919 instruct loadConI13( iRegI dst, immI13 src ) %{
5920 match(Set dst src);
5921
5922 size(4);
5923 format %{ "MOV $src,$dst" %}
6102 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6103 match(Set dst con);
6104 effect(KILL tmp);
6105 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6106 ins_encode %{
6107 // XXX This is a quick fix for 6833573.
6108 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6109 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6110 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6111 %}
6112 ins_pipe(loadConFD);
6113 %}
6114
6115 // Prefetch instructions for allocation.
6116 // Must be safe to execute with invalid address (cannot fault).
6117
6118 instruct prefetchAlloc( memory mem ) %{
6119 predicate(AllocatePrefetchInstr == 0);
6120 match( PrefetchAllocation mem );
6121 ins_cost(MEMORY_REF_COST);
6122 size(4);
6123
6124 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6125 opcode(Assembler::prefetch_op3);
6126 ins_encode( form3_mem_prefetch_write( mem ) );
6127 ins_pipe(iload_mem);
6128 %}
6129
6130 // Use BIS instruction to prefetch for allocation.
6131 // Could fault, need space at the end of TLAB.
6132 instruct prefetchAlloc_bis( iRegP dst ) %{
6133 predicate(AllocatePrefetchInstr == 1);
6134 match( PrefetchAllocation dst );
6135 ins_cost(MEMORY_REF_COST);
6136 size(4);
6137
6138 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6139 ins_encode %{
6140 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6141 %}
6142 ins_pipe(istore_mem_reg);
6158 #else
6159 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6160 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6161 ins_cost(DEFAULT_COST);
6162 size(4);
6163
6164 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6165 ins_encode %{
6166 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6167 %}
6168 ins_pipe(ialu_reg_imm);
6169 %}
6170 #endif
6171
6172 //----------Store Instructions-------------------------------------------------
6173 // Store Byte
6174 instruct storeB(memory mem, iRegI src) %{
6175 match(Set mem (StoreB mem src));
6176 ins_cost(MEMORY_REF_COST);
6177
6178 size(4);
6179 format %{ "STB $src,$mem\t! byte" %}
6180 opcode(Assembler::stb_op3);
6181 ins_encode(simple_form3_mem_reg( mem, src ) );
6182 ins_pipe(istore_mem_reg);
6183 %}
6184
6185 instruct storeB0(memory mem, immI0 src) %{
6186 match(Set mem (StoreB mem src));
6187 ins_cost(MEMORY_REF_COST);
6188
6189 size(4);
6190 format %{ "STB $src,$mem\t! byte" %}
6191 opcode(Assembler::stb_op3);
6192 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6193 ins_pipe(istore_mem_zero);
6194 %}
6195
6196 instruct storeCM0(memory mem, immI0 src) %{
6197 match(Set mem (StoreCM mem src));
6198 ins_cost(MEMORY_REF_COST);
6199
6200 size(4);
6201 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6202 opcode(Assembler::stb_op3);
6203 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6204 ins_pipe(istore_mem_zero);
6205 %}
6206
6207 // Store Char/Short
6208 instruct storeC(memory mem, iRegI src) %{
6209 match(Set mem (StoreC mem src));
6210 ins_cost(MEMORY_REF_COST);
6211
6212 size(4);
6213 format %{ "STH $src,$mem\t! short" %}
6214 opcode(Assembler::sth_op3);
6215 ins_encode(simple_form3_mem_reg( mem, src ) );
6216 ins_pipe(istore_mem_reg);
6217 %}
6218
6219 instruct storeC0(memory mem, immI0 src) %{
6220 match(Set mem (StoreC mem src));
6221 ins_cost(MEMORY_REF_COST);
6222
6223 size(4);
6224 format %{ "STH $src,$mem\t! short" %}
6225 opcode(Assembler::sth_op3);
6226 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6227 ins_pipe(istore_mem_zero);
6228 %}
6229
6230 // Store Integer
6231 instruct storeI(memory mem, iRegI src) %{
6232 match(Set mem (StoreI mem src));
6233 ins_cost(MEMORY_REF_COST);
6234
6235 size(4);
6236 format %{ "STW $src,$mem" %}
6237 opcode(Assembler::stw_op3);
6238 ins_encode(simple_form3_mem_reg( mem, src ) );
6239 ins_pipe(istore_mem_reg);
6240 %}
6241
6242 // Store Long
6243 instruct storeL(memory mem, iRegL src) %{
6244 match(Set mem (StoreL mem src));
6245 ins_cost(MEMORY_REF_COST);
6246 size(4);
6247 format %{ "STX $src,$mem\t! long" %}
6248 opcode(Assembler::stx_op3);
6249 ins_encode(simple_form3_mem_reg( mem, src ) );
6250 ins_pipe(istore_mem_reg);
6251 %}
6252
6253 instruct storeI0(memory mem, immI0 src) %{
6254 match(Set mem (StoreI mem src));
6255 ins_cost(MEMORY_REF_COST);
6256
6257 size(4);
6258 format %{ "STW $src,$mem" %}
6259 opcode(Assembler::stw_op3);
6260 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6261 ins_pipe(istore_mem_zero);
6262 %}
6263
6264 instruct storeL0(memory mem, immL0 src) %{
6265 match(Set mem (StoreL mem src));
6266 ins_cost(MEMORY_REF_COST);
6267
6268 size(4);
6269 format %{ "STX $src,$mem" %}
6270 opcode(Assembler::stx_op3);
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272 ins_pipe(istore_mem_zero);
6273 %}
6274
6275 // Store Integer from float register (used after fstoi)
6276 instruct storeI_Freg(memory mem, regF src) %{
6277 match(Set mem (StoreI mem src));
6278 ins_cost(MEMORY_REF_COST);
6279
6280 size(4);
6281 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6282 opcode(Assembler::stf_op3);
6283 ins_encode(simple_form3_mem_reg( mem, src ) );
6284 ins_pipe(fstoreF_mem_reg);
6285 %}
6286
6287 // Store Pointer
6288 instruct storeP(memory dst, sp_ptr_RegP src) %{
6289 match(Set dst (StoreP dst src));
6290 ins_cost(MEMORY_REF_COST);
6291 size(4);
6292
6293 #ifndef _LP64
6294 format %{ "STW $src,$dst\t! ptr" %}
6295 opcode(Assembler::stw_op3, 0, REGP_OP);
6296 #else
6297 format %{ "STX $src,$dst\t! ptr" %}
6298 opcode(Assembler::stx_op3, 0, REGP_OP);
6299 #endif
6300 ins_encode( form3_mem_reg( dst, src ) );
6301 ins_pipe(istore_mem_spORreg);
6302 %}
6303
6304 instruct storeP0(memory dst, immP0 src) %{
6305 match(Set dst (StoreP dst src));
6306 ins_cost(MEMORY_REF_COST);
6307 size(4);
6308
6309 #ifndef _LP64
6310 format %{ "STW $src,$dst\t! ptr" %}
6311 opcode(Assembler::stw_op3, 0, REGP_OP);
6312 #else
6313 format %{ "STX $src,$dst\t! ptr" %}
6314 opcode(Assembler::stx_op3, 0, REGP_OP);
6315 #endif
6316 ins_encode( form3_mem_reg( dst, R_G0 ) );
6317 ins_pipe(istore_mem_zero);
6318 %}
6319
6320 // Store Compressed Pointer
6321 instruct storeN(memory dst, iRegN src) %{
6322 match(Set dst (StoreN dst src));
6323 ins_cost(MEMORY_REF_COST);
6324 size(4);
6325
6326 format %{ "STW $src,$dst\t! compressed ptr" %}
6327 ins_encode %{
6362 size(4);
6363
6364 format %{ "STW $src,$dst\t! compressed ptr" %}
6365 ins_encode %{
6366 Register base = as_Register($dst$$base);
6367 Register index = as_Register($dst$$index);
6368 if (index != G0) {
6369 __ stw(0, base, index);
6370 } else {
6371 __ stw(0, base, $dst$$disp);
6372 }
6373 %}
6374 ins_pipe(istore_mem_zero);
6375 %}
6376
6377 // Store Double
6378 instruct storeD( memory mem, regD src) %{
6379 match(Set mem (StoreD mem src));
6380 ins_cost(MEMORY_REF_COST);
6381
6382 size(4);
6383 format %{ "STDF $src,$mem" %}
6384 opcode(Assembler::stdf_op3);
6385 ins_encode(simple_form3_mem_reg( mem, src ) );
6386 ins_pipe(fstoreD_mem_reg);
6387 %}
6388
6389 instruct storeD0( memory mem, immD0 src) %{
6390 match(Set mem (StoreD mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 size(4);
6394 format %{ "STX $src,$mem" %}
6395 opcode(Assembler::stx_op3);
6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6397 ins_pipe(fstoreD_mem_zero);
6398 %}
6399
6400 // Store Float
6401 instruct storeF( memory mem, regF src) %{
6402 match(Set mem (StoreF mem src));
6403 ins_cost(MEMORY_REF_COST);
6404
6405 size(4);
6406 format %{ "STF $src,$mem" %}
6407 opcode(Assembler::stf_op3);
6408 ins_encode(simple_form3_mem_reg( mem, src ) );
6409 ins_pipe(fstoreF_mem_reg);
6410 %}
6411
6412 instruct storeF0( memory mem, immF0 src) %{
6413 match(Set mem (StoreF mem src));
6414 ins_cost(MEMORY_REF_COST);
6415
6416 size(4);
6417 format %{ "STW $src,$mem\t! storeF0" %}
6418 opcode(Assembler::stw_op3);
6419 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6420 ins_pipe(fstoreF_mem_zero);
6421 %}
6422
6423 // Convert oop pointer into compressed form
6424 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6425 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6426 match(Set dst (EncodeP src));
6427 format %{ "encode_heap_oop $src, $dst" %}
6428 ins_encode %{
6429 __ encode_heap_oop($src$$Register, $dst$$Register);
6430 %}
6431 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6432 ins_pipe(ialu_reg);
6433 %}
6434
6435 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6436 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7051 match(Set dst (AddL src1 con));
7052
7053 size(4);
7054 format %{ "ADD $src1,$con,$dst" %}
7055 opcode(Assembler::add_op3, Assembler::arith_op);
7056 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7057 ins_pipe(ialu_reg_imm);
7058 %}
7059
7060 //----------Conditional_store--------------------------------------------------
7061 // Conditional-store of the updated heap-top.
7062 // Used during allocation of the shared heap.
7063 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7064
7065 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7066 instruct loadPLocked(iRegP dst, memory mem) %{
7067 match(Set dst (LoadPLocked mem));
7068 ins_cost(MEMORY_REF_COST);
7069
7070 #ifndef _LP64
7071 size(4);
7072 format %{ "LDUW $mem,$dst\t! ptr" %}
7073 opcode(Assembler::lduw_op3, 0, REGP_OP);
7074 #else
7075 format %{ "LDX $mem,$dst\t! ptr" %}
7076 opcode(Assembler::ldx_op3, 0, REGP_OP);
7077 #endif
7078 ins_encode( form3_mem_reg( mem, dst ) );
7079 ins_pipe(iload_mem);
7080 %}
7081
7082 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7083 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7084 effect( KILL newval );
7085 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7086 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7087 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7088 ins_pipe( long_memory_op );
7089 %}
7090
7091 // Conditional-store of an int value.
8121
8122 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8123 predicate(UseVIS >= 3);
8124 match(Set dst (MoveL2D src));
8125
8126 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8127 ins_encode %{
8128 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8129 %}
8130 ins_pipe(ialu_reg_reg);
8131 %}
8132
8133
8134 // Raw moves between float and general registers using stack.
8135
8136 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8137 match(Set dst (MoveF2I src));
8138 effect(DEF dst, USE src);
8139 ins_cost(MEMORY_REF_COST);
8140
8141 size(4);
8142 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8143 opcode(Assembler::lduw_op3);
8144 ins_encode(simple_form3_mem_reg( src, dst ) );
8145 ins_pipe(iload_mem);
8146 %}
8147
8148 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8149 match(Set dst (MoveI2F src));
8150 effect(DEF dst, USE src);
8151 ins_cost(MEMORY_REF_COST);
8152
8153 size(4);
8154 format %{ "LDF $src,$dst\t! MoveI2F" %}
8155 opcode(Assembler::ldf_op3);
8156 ins_encode(simple_form3_mem_reg(src, dst));
8157 ins_pipe(floadF_stk);
8158 %}
8159
8160 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8161 match(Set dst (MoveD2L src));
8162 effect(DEF dst, USE src);
8163 ins_cost(MEMORY_REF_COST);
8164
8165 size(4);
8166 format %{ "LDX $src,$dst\t! MoveD2L" %}
8167 opcode(Assembler::ldx_op3);
8168 ins_encode(simple_form3_mem_reg( src, dst ) );
8169 ins_pipe(iload_mem);
8170 %}
8171
8172 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8173 match(Set dst (MoveL2D src));
8174 effect(DEF dst, USE src);
8175 ins_cost(MEMORY_REF_COST);
8176
8177 size(4);
8178 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8179 opcode(Assembler::lddf_op3);
8180 ins_encode(simple_form3_mem_reg(src, dst));
8181 ins_pipe(floadD_stk);
8182 %}
8183
8184 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8185 match(Set dst (MoveF2I src));
8186 effect(DEF dst, USE src);
8187 ins_cost(MEMORY_REF_COST);
8188
8189 size(4);
8190 format %{ "STF $src,$dst\t! MoveF2I" %}
8191 opcode(Assembler::stf_op3);
8192 ins_encode(simple_form3_mem_reg(dst, src));
8193 ins_pipe(fstoreF_stk_reg);
8194 %}
8195
8196 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8197 match(Set dst (MoveI2F src));
8198 effect(DEF dst, USE src);
8199 ins_cost(MEMORY_REF_COST);
8200
8201 size(4);
8202 format %{ "STW $src,$dst\t! MoveI2F" %}
8203 opcode(Assembler::stw_op3);
8204 ins_encode(simple_form3_mem_reg( dst, src ) );
8205 ins_pipe(istore_mem_reg);
8206 %}
8207
8208 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8209 match(Set dst (MoveD2L src));
8210 effect(DEF dst, USE src);
8211 ins_cost(MEMORY_REF_COST);
8212
8213 size(4);
8214 format %{ "STDF $src,$dst\t! MoveD2L" %}
8215 opcode(Assembler::stdf_op3);
8216 ins_encode(simple_form3_mem_reg(dst, src));
8217 ins_pipe(fstoreD_stk_reg);
8218 %}
8219
8220 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8221 match(Set dst (MoveL2D src));
8222 effect(DEF dst, USE src);
8223 ins_cost(MEMORY_REF_COST);
8224
8225 size(4);
8226 format %{ "STX $src,$dst\t! MoveL2D" %}
8227 opcode(Assembler::stx_op3);
8228 ins_encode(simple_form3_mem_reg( dst, src ) );
8229 ins_pipe(istore_mem_reg);
8230 %}
8231
8232
8233 //----------Arithmetic Conversion Instructions---------------------------------
8234 // The conversions operations are all Alpha sorted. Please keep it that way!
8235
8236 instruct convD2F_reg(regF dst, regD src) %{
8237 match(Set dst (ConvD2F src));
8238 size(4);
8239 format %{ "FDTOS $src,$dst" %}
8240 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8241 ins_encode(form3_opf_rs2D_rdF(src, dst));
8242 ins_pipe(fcvtD2F);
8243 %}
8244
8245
8410 expand %{
8411 regF tmp;
8412 stkI_to_regF(tmp, src);
8413 convI2D_helper(dst, tmp);
8414 %}
8415 %}
8416
8417 instruct convI2D_reg(regD_low dst, iRegI src) %{
8418 predicate(UseVIS >= 3);
8419 match(Set dst (ConvI2D src));
8420 expand %{
8421 regF tmp;
8422 MoveI2F_reg_reg(tmp, src);
8423 convI2D_helper(dst, tmp);
8424 %}
8425 %}
8426
8427 instruct convI2D_mem(regD_low dst, memory mem) %{
8428 match(Set dst (ConvI2D (LoadI mem)));
8429 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8430 size(8);
8431 format %{ "LDF $mem,$dst\n\t"
8432 "FITOD $dst,$dst" %}
8433 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8434 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8435 ins_pipe(floadF_mem);
8436 %}
8437
8438
8439 instruct convI2F_helper(regF dst, regF tmp) %{
8440 effect(DEF dst, USE tmp);
8441 format %{ "FITOS $tmp,$dst" %}
8442 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8443 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8444 ins_pipe(fcvtI2F);
8445 %}
8446
8447 instruct convI2F_stk(regF dst, stackSlotI src) %{
8448 match(Set dst (ConvI2F src));
8449 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8450 expand %{
8451 regF tmp;
8452 stkI_to_regF(tmp,src);
8453 convI2F_helper(dst, tmp);
8454 %}
8455 %}
8456
8457 instruct convI2F_reg(regF dst, iRegI src) %{
8458 predicate(UseVIS >= 3);
8459 match(Set dst (ConvI2F src));
8460 ins_cost(DEFAULT_COST);
8461 expand %{
8462 regF tmp;
8463 MoveI2F_reg_reg(tmp, src);
8464 convI2F_helper(dst, tmp);
8465 %}
8466 %}
8467
8468 instruct convI2F_mem( regF dst, memory mem ) %{
8469 match(Set dst (ConvI2F (LoadI mem)));
8470 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8471 size(8);
8472 format %{ "LDF $mem,$dst\n\t"
8473 "FITOS $dst,$dst" %}
8474 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8475 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8476 ins_pipe(floadF_mem);
8477 %}
8478
8479
8480 instruct convI2L_reg(iRegL dst, iRegI src) %{
8481 match(Set dst (ConvI2L src));
8482 size(4);
8483 format %{ "SRA $src,0,$dst\t! int->long" %}
8484 opcode(Assembler::sra_op3, Assembler::arith_op);
8485 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8486 ins_pipe(ialu_reg_reg);
8487 %}
8488
8489 // Zero-extend convert int to long
8490 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8491 match(Set dst (AndL (ConvI2L src) mask) );
|
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr = (Assembler::ldst_op << 30)
952 | (dst_enc << 25)
953 | (primary << 19)
954 | (src1_enc << 14);
955
956 uint index = src2_enc;
957 int disp = disp32;
958
959 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
960 disp += STACK_BIAS;
961 // Check that stack offset fits, load into O7 if not
962 if (!Assembler::is_simm13(disp)) {
963 MacroAssembler _masm(&cbuf);
964 __ set(disp, O7);
965 if (index != R_G0_enc) {
966 __ add(O7, reg_to_register_object(index), O7);
967 }
968 index = R_O7_enc;
969 disp = 0;
970 }
971 }
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 if (VerifyOops) {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if (!OptoReg::is_valid(reg)) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356 if (st->position() > 0) {
1357 st->cr();
1358 st->sp();
1359 }
1360 va_list ap;
1361 va_start(ap, format);
1362 st->vprint(format, ap);
1363 va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368 if (cbuf) {
1369 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370 }
1371 #ifndef PRODUCT
1372 else {
1373 if (is_load) {
1374 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375 } else {
1376 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377 }
1378 }
1379 #endif
1380 }
1381
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383 if (cbuf) {
1384 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385 }
1386 #ifndef PRODUCT
1387 else {
1388 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389 }
1390 #endif
1391 }
1392
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394 CodeBuffer *cbuf,
1395 PhaseRegAlloc *ra_,
1396 outputStream* st) {
1397 // Get registers to move
1398 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1400 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1402
1403 enum RC src_second_rc = rc_class(src_second);
1404 enum RC src_first_rc = rc_class(src_first);
1405 enum RC dst_second_rc = rc_class(dst_second);
1406 enum RC dst_first_rc = rc_class(dst_first);
1407
1408 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409
1410 if (src_first == dst_first && src_second == dst_second) {
1411 return; // Self copy, no move
1412 }
1413
1414 // --------------------------------------
1415 // Check for mem-mem move. Load into unused float registers and fall into
1416 // the float-store case.
1417 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if ((src_first&1) == 0 && src_first+1 == src_second) {
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424 } else {
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426 }
1427 src_first = OptoReg::Name(R_F30_num);
1428 src_first_rc = rc_float;
1429 }
1430
1431 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432 int offset = ra_->reg2offset(src_second);
1433 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434 src_second = OptoReg::Name(R_F31_num);
1435 src_second_rc = rc_float;
1436 }
1437
1438 // --------------------------------------
1439 // Check for float->int copy; requires a trip through memory
1440 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441 int offset = frame::register_save_words*wordSize;
1442 if (cbuf) {
1443 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447 }
1448 #ifndef PRODUCT
1449 else {
1450 print_helper(st, "SUB R_SP,16,R_SP");
1451 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1452 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453 print_helper(st, "ADD R_SP,16,R_SP");
1454 }
1455 #endif
1456 }
1457
1458 // Check for float->int copy on T4
1459 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460 // Further check for aligned-adjacent pair, so we can use a double move
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463 return;
1464 }
1465 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466 }
1467 // Check for int->float copy on T4
1468 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469 // Further check for aligned-adjacent pair, so we can use a double move
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472 return;
1473 }
1474 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475 }
1476
1477 // --------------------------------------
1478 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479 // In such cases, I have to do the big-endian swap. For aligned targets, the
1480 // hardware does the flop for me. Doubles are always aligned, so no problem
1481 // there. Misaligned sources only come from native-long-returns (handled
1482 // special below).
1483 #ifndef _LP64
1484 if (src_first_rc == rc_int && // source is already big-endian
1485 src_second_rc != rc_bad && // 64-bit move
1486 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488 // Do the big-endian flop.
1489 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1490 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491 }
1492 #endif
1493
1494 // --------------------------------------
1495 // Check for integer reg-reg copy
1496 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1499 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1501 // operand contains the least significant word of the 64-bit value and vice versa.
1502 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505 if ( cbuf ) {
1506 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510 } else {
1511 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515 }
1516 return;
1517 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518 // returning a long value in I0/I1
1519 // a SpillCopy must be able to target a return instruction's reg_class
1520 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1522 // operand contains the least significant word of the 64-bit value and vice versa.
1523 OptoReg::Name tdest = dst_first;
1524
1525 if (src_first == dst_first) {
1526 tdest = OptoReg::Name(R_O7_num);
1527 }
1528
1529 if (cbuf) {
1530 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532 // ShrL_reg_imm6
1533 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534 // ShrR_reg_imm6 src, 0, dst
1535 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536 if (tdest != dst_first) {
1537 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538 }
1539 }
1540 #ifndef PRODUCT
1541 else {
1542 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544 if (tdest != dst_first) {
1545 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546 }
1547 }
1548 #endif // PRODUCT
1549 return size+8;
1550 }
1551 #endif // !_LP64
1552 // Else normal reg-reg copy
1553 assert(src_second != dst_first, "smashed second before evacuating it");
1554 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1555 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556 // This moves an aligned adjacent pair.
1557 // See if we are done.
1558 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559 return;
1560 }
1561 }
1562
1563 // Check for integer store
1564 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565 int offset = ra_->reg2offset(dst_first);
1566 // Further check for aligned-adjacent pair, so we can use a double store
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569 return;
1570 }
1571 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572 }
1573
1574 // Check for integer load
1575 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576 int offset = ra_->reg2offset(src_first);
1577 // Further check for aligned-adjacent pair, so we can use a double load
1578 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580 return;
1581 }
1582 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583 }
1584
1585 // Check for float reg-reg copy
1586 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587 // Further check for aligned-adjacent pair, so we can use a double move
1588 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590 return;
1591 }
1592 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593 }
1594
1595 // Check for float store
1596 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597 int offset = ra_->reg2offset(dst_first);
1598 // Further check for aligned-adjacent pair, so we can use a double store
1599 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601 return;
1602 }
1603 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604 }
1605
1606 // Check for float load
1607 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608 int offset = ra_->reg2offset(src_first);
1609 // Further check for aligned-adjacent pair, so we can use a double load
1610 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612 return;
1613 }
1614 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615 }
1616
1617 // --------------------------------------------------------------------
1618 // Check for hi bits still needing moving. Only happens for misaligned
1619 // arguments to native calls.
1620 if (src_second == dst_second) {
1621 return; // Self copy; no move
1622 }
1623 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624
1625 #ifndef _LP64
1626 // In the LP64 build, all registers can be moved as aligned/adjacent
1627 // pairs, so there's never any need to move the high bits separately.
1628 // The 32-bit builds have to deal with the 32-bit ABI which can force
1629 // all sorts of silly alignment problems.
1630
1631 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1632 // 32-bits of a 64-bit register, but are needed in low bits of another
1633 // register (else it's a hi-bits-to-hi-bits copy which should have
1634 // happened already as part of a 64-bit move)
1635 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638 // Shift src_second down to dst_second's low bits.
1639 if (cbuf) {
1640 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642 } else {
1643 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645 }
1646 return;
1647 }
1648
1649 // Check for high word integer store. Must down-shift the hi bits
1650 // into a temp register, then fall into the case of storing int bits.
1651 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652 // Shift src_second down to dst_second's low bits.
1653 if (cbuf) {
1654 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656 } else {
1657 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659 }
1660 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661 }
1662
1663 // Check for high word integer load
1664 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666
1667 // Check for high word integer store
1668 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670
1671 // Check for high word float store
1672 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674
1675 #endif // !_LP64
1676
1677 Unimplemented();
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681 PhaseRegAlloc *ra_,
1682 bool do_size,
1683 outputStream* st) const {
1684 assert(!do_size, "not supported");
1685 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686 return 0;
1687 }
1688
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691 implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696 implementation( &cbuf, ra_, false, NULL );
1697 }
1698
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700 return MachNode::size(ra_);
1701 }
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711 MacroAssembler _masm(&cbuf);
1712 for (int i = 0; i < _count; i += 1) {
1713 __ nop();
1714 }
1715 }
1716
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718 return 4 * _count;
1719 }
1720
1721
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726 int reg = ra_->get_reg_first(this);
1727 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732 MacroAssembler _masm(&cbuf);
5208 src2 : E(read);
5209 srcdst : E(read);
5210 IALU : R;
5211 BR : R;
5212 %}
5213
5214 // Define the class for the Nop node
5215 define %{
5216 MachNop = ialu_nop;
5217 %}
5218
5219 %}
5220
5221 //----------INSTRUCTIONS-------------------------------------------------------
5222
5223 //------------Special Stack Slot instructions - no match rules-----------------
5224 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5225 // No match rule to avoid chain rule match.
5226 effect(DEF dst, USE src);
5227 ins_cost(MEMORY_REF_COST);
5228 format %{ "LDF $src,$dst\t! stkI to regF" %}
5229 opcode(Assembler::ldf_op3);
5230 ins_encode(simple_form3_mem_reg(src, dst));
5231 ins_pipe(floadF_stk);
5232 %}
5233
5234 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5235 // No match rule to avoid chain rule match.
5236 effect(DEF dst, USE src);
5237 ins_cost(MEMORY_REF_COST);
5238 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5239 opcode(Assembler::lddf_op3);
5240 ins_encode(simple_form3_mem_reg(src, dst));
5241 ins_pipe(floadD_stk);
5242 %}
5243
5244 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5245 // No match rule to avoid chain rule match.
5246 effect(DEF dst, USE src);
5247 ins_cost(MEMORY_REF_COST);
5248 format %{ "STF $src,$dst\t! regF to stkI" %}
5249 opcode(Assembler::stf_op3);
5250 ins_encode(simple_form3_mem_reg(dst, src));
5251 ins_pipe(fstoreF_stk_reg);
5252 %}
5253
5254 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5255 // No match rule to avoid chain rule match.
5256 effect(DEF dst, USE src);
5257 ins_cost(MEMORY_REF_COST);
5258 format %{ "STDF $src,$dst\t! regD to stkL" %}
5259 opcode(Assembler::stdf_op3);
5260 ins_encode(simple_form3_mem_reg(dst, src));
5261 ins_pipe(fstoreD_stk_reg);
5262 %}
5263
5264 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5265 effect(DEF dst, USE src);
5266 ins_cost(MEMORY_REF_COST*2);
5267 format %{ "STW $src,$dst.hi\t! long\n\t"
5268 "STW R_G0,$dst.lo" %}
5269 opcode(Assembler::stw_op3);
5270 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5271 ins_pipe(lstoreI_stk_reg);
5272 %}
5273
5274 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5275 // No match rule to avoid chain rule match.
5276 effect(DEF dst, USE src);
5277 ins_cost(MEMORY_REF_COST);
5278 format %{ "STX $src,$dst\t! regL to stkD" %}
5279 opcode(Assembler::stx_op3);
5280 ins_encode(simple_form3_mem_reg( dst, src ) );
5281 ins_pipe(istore_stk_reg);
5282 %}
5283
5284 //---------- Chain stack slots between similar types --------
5285
5286 // Load integer from stack slot
5287 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5288 match(Set dst src);
5289 ins_cost(MEMORY_REF_COST);
5290
5291 format %{ "LDUW $src,$dst\t!stk" %}
5292 opcode(Assembler::lduw_op3);
5293 ins_encode(simple_form3_mem_reg( src, dst ) );
5294 ins_pipe(iload_mem);
5295 %}
5296
5297 // Store integer to stack slot
5298 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5299 match(Set dst src);
5300 ins_cost(MEMORY_REF_COST);
5301
5302 format %{ "STW $src,$dst\t!stk" %}
5303 opcode(Assembler::stw_op3);
5304 ins_encode(simple_form3_mem_reg( dst, src ) );
5305 ins_pipe(istore_mem_reg);
5306 %}
5307
5308 // Load long from stack slot
5309 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5310 match(Set dst src);
5311
5312 ins_cost(MEMORY_REF_COST);
5313 format %{ "LDX $src,$dst\t! long" %}
5314 opcode(Assembler::ldx_op3);
5315 ins_encode(simple_form3_mem_reg( src, dst ) );
5316 ins_pipe(iload_mem);
5317 %}
5318
5319 // Store long to stack slot
5320 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5321 match(Set dst src);
5322
5323 ins_cost(MEMORY_REF_COST);
5324 format %{ "STX $src,$dst\t! long" %}
5325 opcode(Assembler::stx_op3);
5326 ins_encode(simple_form3_mem_reg( dst, src ) );
5327 ins_pipe(istore_mem_reg);
5328 %}
5329
5330 #ifdef _LP64
5331 // Load pointer from stack slot, 64-bit encoding
5332 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5333 match(Set dst src);
5334 ins_cost(MEMORY_REF_COST);
5335 format %{ "LDX $src,$dst\t!ptr" %}
5336 opcode(Assembler::ldx_op3);
5337 ins_encode(simple_form3_mem_reg( src, dst ) );
5338 ins_pipe(iload_mem);
5339 %}
5340
5341 // Store pointer to stack slot
5342 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5343 match(Set dst src);
5344 ins_cost(MEMORY_REF_COST);
5345 format %{ "STX $src,$dst\t!ptr" %}
5346 opcode(Assembler::stx_op3);
5347 ins_encode(simple_form3_mem_reg( dst, src ) );
5348 ins_pipe(istore_mem_reg);
5349 %}
5350 #else // _LP64
5351 // Load pointer from stack slot, 32-bit encoding
5352 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5353 match(Set dst src);
5354 ins_cost(MEMORY_REF_COST);
5355 format %{ "LDUW $src,$dst\t!ptr" %}
5356 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5357 ins_encode(simple_form3_mem_reg( src, dst ) );
5358 ins_pipe(iload_mem);
5359 %}
5360
5361 // Store pointer to stack slot
5362 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5363 match(Set dst src);
5364 ins_cost(MEMORY_REF_COST);
5770 %}
5771
5772 // Load Long - aligned
5773 instruct loadL(iRegL dst, memory mem ) %{
5774 match(Set dst (LoadL mem));
5775 ins_cost(MEMORY_REF_COST);
5776
5777 size(4);
5778 format %{ "LDX $mem,$dst\t! long" %}
5779 ins_encode %{
5780 __ ldx($mem$$Address, $dst$$Register);
5781 %}
5782 ins_pipe(iload_mem);
5783 %}
5784
5785 // Load Long - UNaligned
5786 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5787 match(Set dst (LoadL_unaligned mem));
5788 effect(KILL tmp);
5789 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5790 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5791 "\tLDUW $mem ,$dst\n"
5792 "\tSLLX #32, $dst, $dst\n"
5793 "\tOR $dst, R_O7, $dst" %}
5794 opcode(Assembler::lduw_op3);
5795 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5796 ins_pipe(iload_mem);
5797 %}
5798
5799 // Load Range
5800 instruct loadRange(iRegI dst, memory mem) %{
5801 match(Set dst (LoadRange mem));
5802 ins_cost(MEMORY_REF_COST);
5803
5804 format %{ "LDUW $mem,$dst\t! range" %}
5805 opcode(Assembler::lduw_op3);
5806 ins_encode(simple_form3_mem_reg( mem, dst ) );
5807 ins_pipe(iload_mem);
5808 %}
5809
5810 // Load Integer into %f register (for fitos/fitod)
5811 instruct loadI_freg(regF dst, memory mem) %{
5812 match(Set dst (LoadI mem));
5813 ins_cost(MEMORY_REF_COST);
5814
5815 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5816 opcode(Assembler::ldf_op3);
5817 ins_encode(simple_form3_mem_reg( mem, dst ) );
5818 ins_pipe(floadF_mem);
5819 %}
5820
5821 // Load Pointer
5822 instruct loadP(iRegP dst, memory mem) %{
5823 match(Set dst (LoadP mem));
5824 ins_cost(MEMORY_REF_COST);
5825 size(4);
5826
5827 #ifndef _LP64
5828 format %{ "LDUW $mem,$dst\t! ptr" %}
5829 ins_encode %{
5830 __ lduw($mem$$Address, $dst$$Register);
5831 %}
5832 #else
5833 format %{ "LDX $mem,$dst\t! ptr" %}
5872 %}
5873
5874 // Load narrow Klass Pointer
5875 instruct loadNKlass(iRegN dst, memory mem) %{
5876 match(Set dst (LoadNKlass mem));
5877 ins_cost(MEMORY_REF_COST);
5878 size(4);
5879
5880 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5881 ins_encode %{
5882 __ lduw($mem$$Address, $dst$$Register);
5883 %}
5884 ins_pipe(iload_mem);
5885 %}
5886
5887 // Load Double
5888 instruct loadD(regD dst, memory mem) %{
5889 match(Set dst (LoadD mem));
5890 ins_cost(MEMORY_REF_COST);
5891
5892 format %{ "LDDF $mem,$dst" %}
5893 opcode(Assembler::lddf_op3);
5894 ins_encode(simple_form3_mem_reg( mem, dst ) );
5895 ins_pipe(floadD_mem);
5896 %}
5897
5898 // Load Double - UNaligned
5899 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5900 match(Set dst (LoadD_unaligned mem));
5901 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5902 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5903 "\tLDF $mem+4,$dst.lo\t!" %}
5904 opcode(Assembler::ldf_op3);
5905 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5906 ins_pipe(iload_mem);
5907 %}
5908
5909 // Load Float
5910 instruct loadF(regF dst, memory mem) %{
5911 match(Set dst (LoadF mem));
5912 ins_cost(MEMORY_REF_COST);
5913
5914 format %{ "LDF $mem,$dst" %}
5915 opcode(Assembler::ldf_op3);
5916 ins_encode(simple_form3_mem_reg( mem, dst ) );
5917 ins_pipe(floadF_mem);
5918 %}
5919
5920 // Load Constant
5921 instruct loadConI( iRegI dst, immI src ) %{
5922 match(Set dst src);
5923 ins_cost(DEFAULT_COST * 3/2);
5924 format %{ "SET $src,$dst" %}
5925 ins_encode( Set32(src, dst) );
5926 ins_pipe(ialu_hi_lo_reg);
5927 %}
5928
5929 instruct loadConI13( iRegI dst, immI13 src ) %{
5930 match(Set dst src);
5931
5932 size(4);
5933 format %{ "MOV $src,$dst" %}
6112 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6113 match(Set dst con);
6114 effect(KILL tmp);
6115 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6116 ins_encode %{
6117 // XXX This is a quick fix for 6833573.
6118 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6119 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6120 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6121 %}
6122 ins_pipe(loadConFD);
6123 %}
6124
6125 // Prefetch instructions for allocation.
6126 // Must be safe to execute with invalid address (cannot fault).
6127
6128 instruct prefetchAlloc( memory mem ) %{
6129 predicate(AllocatePrefetchInstr == 0);
6130 match( PrefetchAllocation mem );
6131 ins_cost(MEMORY_REF_COST);
6132
6133 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6134 opcode(Assembler::prefetch_op3);
6135 ins_encode( form3_mem_prefetch_write( mem ) );
6136 ins_pipe(iload_mem);
6137 %}
6138
6139 // Use BIS instruction to prefetch for allocation.
6140 // Could fault, need space at the end of TLAB.
6141 instruct prefetchAlloc_bis( iRegP dst ) %{
6142 predicate(AllocatePrefetchInstr == 1);
6143 match( PrefetchAllocation dst );
6144 ins_cost(MEMORY_REF_COST);
6145 size(4);
6146
6147 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6148 ins_encode %{
6149 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6150 %}
6151 ins_pipe(istore_mem_reg);
6167 #else
6168 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6169 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6170 ins_cost(DEFAULT_COST);
6171 size(4);
6172
6173 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6174 ins_encode %{
6175 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6176 %}
6177 ins_pipe(ialu_reg_imm);
6178 %}
6179 #endif
6180
6181 //----------Store Instructions-------------------------------------------------
6182 // Store Byte
6183 instruct storeB(memory mem, iRegI src) %{
6184 match(Set mem (StoreB mem src));
6185 ins_cost(MEMORY_REF_COST);
6186
6187 format %{ "STB $src,$mem\t! byte" %}
6188 opcode(Assembler::stb_op3);
6189 ins_encode(simple_form3_mem_reg( mem, src ) );
6190 ins_pipe(istore_mem_reg);
6191 %}
6192
6193 instruct storeB0(memory mem, immI0 src) %{
6194 match(Set mem (StoreB mem src));
6195 ins_cost(MEMORY_REF_COST);
6196
6197 format %{ "STB $src,$mem\t! byte" %}
6198 opcode(Assembler::stb_op3);
6199 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6200 ins_pipe(istore_mem_zero);
6201 %}
6202
6203 instruct storeCM0(memory mem, immI0 src) %{
6204 match(Set mem (StoreCM mem src));
6205 ins_cost(MEMORY_REF_COST);
6206
6207 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6208 opcode(Assembler::stb_op3);
6209 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6210 ins_pipe(istore_mem_zero);
6211 %}
6212
6213 // Store Char/Short
6214 instruct storeC(memory mem, iRegI src) %{
6215 match(Set mem (StoreC mem src));
6216 ins_cost(MEMORY_REF_COST);
6217
6218 format %{ "STH $src,$mem\t! short" %}
6219 opcode(Assembler::sth_op3);
6220 ins_encode(simple_form3_mem_reg( mem, src ) );
6221 ins_pipe(istore_mem_reg);
6222 %}
6223
6224 instruct storeC0(memory mem, immI0 src) %{
6225 match(Set mem (StoreC mem src));
6226 ins_cost(MEMORY_REF_COST);
6227
6228 format %{ "STH $src,$mem\t! short" %}
6229 opcode(Assembler::sth_op3);
6230 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6231 ins_pipe(istore_mem_zero);
6232 %}
6233
6234 // Store Integer
6235 instruct storeI(memory mem, iRegI src) %{
6236 match(Set mem (StoreI mem src));
6237 ins_cost(MEMORY_REF_COST);
6238
6239 format %{ "STW $src,$mem" %}
6240 opcode(Assembler::stw_op3);
6241 ins_encode(simple_form3_mem_reg( mem, src ) );
6242 ins_pipe(istore_mem_reg);
6243 %}
6244
6245 // Store Long
6246 instruct storeL(memory mem, iRegL src) %{
6247 match(Set mem (StoreL mem src));
6248 ins_cost(MEMORY_REF_COST);
6249 format %{ "STX $src,$mem\t! long" %}
6250 opcode(Assembler::stx_op3);
6251 ins_encode(simple_form3_mem_reg( mem, src ) );
6252 ins_pipe(istore_mem_reg);
6253 %}
6254
6255 instruct storeI0(memory mem, immI0 src) %{
6256 match(Set mem (StoreI mem src));
6257 ins_cost(MEMORY_REF_COST);
6258
6259 format %{ "STW $src,$mem" %}
6260 opcode(Assembler::stw_op3);
6261 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6262 ins_pipe(istore_mem_zero);
6263 %}
6264
6265 instruct storeL0(memory mem, immL0 src) %{
6266 match(Set mem (StoreL mem src));
6267 ins_cost(MEMORY_REF_COST);
6268
6269 format %{ "STX $src,$mem" %}
6270 opcode(Assembler::stx_op3);
6271 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272 ins_pipe(istore_mem_zero);
6273 %}
6274
6275 // Store Integer from float register (used after fstoi)
6276 instruct storeI_Freg(memory mem, regF src) %{
6277 match(Set mem (StoreI mem src));
6278 ins_cost(MEMORY_REF_COST);
6279
6280 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6281 opcode(Assembler::stf_op3);
6282 ins_encode(simple_form3_mem_reg( mem, src ) );
6283 ins_pipe(fstoreF_mem_reg);
6284 %}
6285
6286 // Store Pointer
6287 instruct storeP(memory dst, sp_ptr_RegP src) %{
6288 match(Set dst (StoreP dst src));
6289 ins_cost(MEMORY_REF_COST);
6290
6291 #ifndef _LP64
6292 format %{ "STW $src,$dst\t! ptr" %}
6293 opcode(Assembler::stw_op3, 0, REGP_OP);
6294 #else
6295 format %{ "STX $src,$dst\t! ptr" %}
6296 opcode(Assembler::stx_op3, 0, REGP_OP);
6297 #endif
6298 ins_encode( form3_mem_reg( dst, src ) );
6299 ins_pipe(istore_mem_spORreg);
6300 %}
6301
6302 instruct storeP0(memory dst, immP0 src) %{
6303 match(Set dst (StoreP dst src));
6304 ins_cost(MEMORY_REF_COST);
6305
6306 #ifndef _LP64
6307 format %{ "STW $src,$dst\t! ptr" %}
6308 opcode(Assembler::stw_op3, 0, REGP_OP);
6309 #else
6310 format %{ "STX $src,$dst\t! ptr" %}
6311 opcode(Assembler::stx_op3, 0, REGP_OP);
6312 #endif
6313 ins_encode( form3_mem_reg( dst, R_G0 ) );
6314 ins_pipe(istore_mem_zero);
6315 %}
6316
6317 // Store Compressed Pointer
6318 instruct storeN(memory dst, iRegN src) %{
6319 match(Set dst (StoreN dst src));
6320 ins_cost(MEMORY_REF_COST);
6321 size(4);
6322
6323 format %{ "STW $src,$dst\t! compressed ptr" %}
6324 ins_encode %{
6359 size(4);
6360
6361 format %{ "STW $src,$dst\t! compressed ptr" %}
6362 ins_encode %{
6363 Register base = as_Register($dst$$base);
6364 Register index = as_Register($dst$$index);
6365 if (index != G0) {
6366 __ stw(0, base, index);
6367 } else {
6368 __ stw(0, base, $dst$$disp);
6369 }
6370 %}
6371 ins_pipe(istore_mem_zero);
6372 %}
6373
6374 // Store Double
6375 instruct storeD( memory mem, regD src) %{
6376 match(Set mem (StoreD mem src));
6377 ins_cost(MEMORY_REF_COST);
6378
6379 format %{ "STDF $src,$mem" %}
6380 opcode(Assembler::stdf_op3);
6381 ins_encode(simple_form3_mem_reg( mem, src ) );
6382 ins_pipe(fstoreD_mem_reg);
6383 %}
6384
6385 instruct storeD0( memory mem, immD0 src) %{
6386 match(Set mem (StoreD mem src));
6387 ins_cost(MEMORY_REF_COST);
6388
6389 format %{ "STX $src,$mem" %}
6390 opcode(Assembler::stx_op3);
6391 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6392 ins_pipe(fstoreD_mem_zero);
6393 %}
6394
6395 // Store Float
6396 instruct storeF( memory mem, regF src) %{
6397 match(Set mem (StoreF mem src));
6398 ins_cost(MEMORY_REF_COST);
6399
6400 format %{ "STF $src,$mem" %}
6401 opcode(Assembler::stf_op3);
6402 ins_encode(simple_form3_mem_reg( mem, src ) );
6403 ins_pipe(fstoreF_mem_reg);
6404 %}
6405
6406 instruct storeF0( memory mem, immF0 src) %{
6407 match(Set mem (StoreF mem src));
6408 ins_cost(MEMORY_REF_COST);
6409
6410 format %{ "STW $src,$mem\t! storeF0" %}
6411 opcode(Assembler::stw_op3);
6412 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6413 ins_pipe(fstoreF_mem_zero);
6414 %}
6415
6416 // Convert oop pointer into compressed form
6417 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6418 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6419 match(Set dst (EncodeP src));
6420 format %{ "encode_heap_oop $src, $dst" %}
6421 ins_encode %{
6422 __ encode_heap_oop($src$$Register, $dst$$Register);
6423 %}
6424 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6425 ins_pipe(ialu_reg);
6426 %}
6427
6428 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6429 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
7044 match(Set dst (AddL src1 con));
7045
7046 size(4);
7047 format %{ "ADD $src1,$con,$dst" %}
7048 opcode(Assembler::add_op3, Assembler::arith_op);
7049 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7050 ins_pipe(ialu_reg_imm);
7051 %}
7052
7053 //----------Conditional_store--------------------------------------------------
7054 // Conditional-store of the updated heap-top.
7055 // Used during allocation of the shared heap.
7056 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7057
7058 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7059 instruct loadPLocked(iRegP dst, memory mem) %{
7060 match(Set dst (LoadPLocked mem));
7061 ins_cost(MEMORY_REF_COST);
7062
7063 #ifndef _LP64
7064 format %{ "LDUW $mem,$dst\t! ptr" %}
7065 opcode(Assembler::lduw_op3, 0, REGP_OP);
7066 #else
7067 format %{ "LDX $mem,$dst\t! ptr" %}
7068 opcode(Assembler::ldx_op3, 0, REGP_OP);
7069 #endif
7070 ins_encode( form3_mem_reg( mem, dst ) );
7071 ins_pipe(iload_mem);
7072 %}
7073
7074 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7075 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7076 effect( KILL newval );
7077 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7078 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7079 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7080 ins_pipe( long_memory_op );
7081 %}
7082
7083 // Conditional-store of an int value.
8113
8114 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8115 predicate(UseVIS >= 3);
8116 match(Set dst (MoveL2D src));
8117
8118 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8119 ins_encode %{
8120 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8121 %}
8122 ins_pipe(ialu_reg_reg);
8123 %}
8124
8125
8126 // Raw moves between float and general registers using stack.
8127
8128 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8129 match(Set dst (MoveF2I src));
8130 effect(DEF dst, USE src);
8131 ins_cost(MEMORY_REF_COST);
8132
8133 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8134 opcode(Assembler::lduw_op3);
8135 ins_encode(simple_form3_mem_reg( src, dst ) );
8136 ins_pipe(iload_mem);
8137 %}
8138
8139 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8140 match(Set dst (MoveI2F src));
8141 effect(DEF dst, USE src);
8142 ins_cost(MEMORY_REF_COST);
8143
8144 format %{ "LDF $src,$dst\t! MoveI2F" %}
8145 opcode(Assembler::ldf_op3);
8146 ins_encode(simple_form3_mem_reg(src, dst));
8147 ins_pipe(floadF_stk);
8148 %}
8149
8150 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8151 match(Set dst (MoveD2L src));
8152 effect(DEF dst, USE src);
8153 ins_cost(MEMORY_REF_COST);
8154
8155 format %{ "LDX $src,$dst\t! MoveD2L" %}
8156 opcode(Assembler::ldx_op3);
8157 ins_encode(simple_form3_mem_reg( src, dst ) );
8158 ins_pipe(iload_mem);
8159 %}
8160
8161 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8162 match(Set dst (MoveL2D src));
8163 effect(DEF dst, USE src);
8164 ins_cost(MEMORY_REF_COST);
8165
8166 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8167 opcode(Assembler::lddf_op3);
8168 ins_encode(simple_form3_mem_reg(src, dst));
8169 ins_pipe(floadD_stk);
8170 %}
8171
8172 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8173 match(Set dst (MoveF2I src));
8174 effect(DEF dst, USE src);
8175 ins_cost(MEMORY_REF_COST);
8176
8177 format %{ "STF $src,$dst\t! MoveF2I" %}
8178 opcode(Assembler::stf_op3);
8179 ins_encode(simple_form3_mem_reg(dst, src));
8180 ins_pipe(fstoreF_stk_reg);
8181 %}
8182
8183 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8184 match(Set dst (MoveI2F src));
8185 effect(DEF dst, USE src);
8186 ins_cost(MEMORY_REF_COST);
8187
8188 format %{ "STW $src,$dst\t! MoveI2F" %}
8189 opcode(Assembler::stw_op3);
8190 ins_encode(simple_form3_mem_reg( dst, src ) );
8191 ins_pipe(istore_mem_reg);
8192 %}
8193
8194 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8195 match(Set dst (MoveD2L src));
8196 effect(DEF dst, USE src);
8197 ins_cost(MEMORY_REF_COST);
8198
8199 format %{ "STDF $src,$dst\t! MoveD2L" %}
8200 opcode(Assembler::stdf_op3);
8201 ins_encode(simple_form3_mem_reg(dst, src));
8202 ins_pipe(fstoreD_stk_reg);
8203 %}
8204
8205 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8206 match(Set dst (MoveL2D src));
8207 effect(DEF dst, USE src);
8208 ins_cost(MEMORY_REF_COST);
8209
8210 format %{ "STX $src,$dst\t! MoveL2D" %}
8211 opcode(Assembler::stx_op3);
8212 ins_encode(simple_form3_mem_reg( dst, src ) );
8213 ins_pipe(istore_mem_reg);
8214 %}
8215
8216
8217 //----------Arithmetic Conversion Instructions---------------------------------
8218 // The conversions operations are all Alpha sorted. Please keep it that way!
8219
8220 instruct convD2F_reg(regF dst, regD src) %{
8221 match(Set dst (ConvD2F src));
8222 size(4);
8223 format %{ "FDTOS $src,$dst" %}
8224 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8225 ins_encode(form3_opf_rs2D_rdF(src, dst));
8226 ins_pipe(fcvtD2F);
8227 %}
8228
8229
8394 expand %{
8395 regF tmp;
8396 stkI_to_regF(tmp, src);
8397 convI2D_helper(dst, tmp);
8398 %}
8399 %}
8400
8401 instruct convI2D_reg(regD_low dst, iRegI src) %{
8402 predicate(UseVIS >= 3);
8403 match(Set dst (ConvI2D src));
8404 expand %{
8405 regF tmp;
8406 MoveI2F_reg_reg(tmp, src);
8407 convI2D_helper(dst, tmp);
8408 %}
8409 %}
8410
8411 instruct convI2D_mem(regD_low dst, memory mem) %{
8412 match(Set dst (ConvI2D (LoadI mem)));
8413 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8414 format %{ "LDF $mem,$dst\n\t"
8415 "FITOD $dst,$dst" %}
8416 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8417 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8418 ins_pipe(floadF_mem);
8419 %}
8420
8421
8422 instruct convI2F_helper(regF dst, regF tmp) %{
8423 effect(DEF dst, USE tmp);
8424 format %{ "FITOS $tmp,$dst" %}
8425 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8426 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8427 ins_pipe(fcvtI2F);
8428 %}
8429
8430 instruct convI2F_stk(regF dst, stackSlotI src) %{
8431 match(Set dst (ConvI2F src));
8432 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8433 expand %{
8434 regF tmp;
8435 stkI_to_regF(tmp,src);
8436 convI2F_helper(dst, tmp);
8437 %}
8438 %}
8439
8440 instruct convI2F_reg(regF dst, iRegI src) %{
8441 predicate(UseVIS >= 3);
8442 match(Set dst (ConvI2F src));
8443 ins_cost(DEFAULT_COST);
8444 expand %{
8445 regF tmp;
8446 MoveI2F_reg_reg(tmp, src);
8447 convI2F_helper(dst, tmp);
8448 %}
8449 %}
8450
8451 instruct convI2F_mem( regF dst, memory mem ) %{
8452 match(Set dst (ConvI2F (LoadI mem)));
8453 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8454 format %{ "LDF $mem,$dst\n\t"
8455 "FITOS $dst,$dst" %}
8456 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8457 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8458 ins_pipe(floadF_mem);
8459 %}
8460
8461
8462 instruct convI2L_reg(iRegL dst, iRegI src) %{
8463 match(Set dst (ConvI2L src));
8464 size(4);
8465 format %{ "SRA $src,0,$dst\t! int->long" %}
8466 opcode(Assembler::sra_op3, Assembler::arith_op);
8467 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8468 ins_pipe(ialu_reg_reg);
8469 %}
8470
8471 // Zero-extend convert int to long
8472 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8473 match(Set dst (AndL (ConvI2L src) mask) );
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