1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/ad.hpp"
28 #include "opto/addnode.hpp"
29 #include "opto/callnode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/movenode.hpp"
34 #include "opto/opcodes.hpp"
35 #include "opto/regmask.hpp"
36 #include "opto/rootnode.hpp"
37 #include "opto/runtime.hpp"
38 #include "opto/type.hpp"
39 #include "opto/vectornode.hpp"
40 #include "runtime/os.hpp"
41 #include "runtime/sharedRuntime.hpp"
42
43 OptoReg::Name OptoReg::c_frame_pointer;
44
45 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
46 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
47 RegMask Matcher::STACK_ONLY_mask;
48 RegMask Matcher::c_frame_ptr_mask;
49 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
50 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
51
52 //---------------------------Matcher-------------------------------------------
53 Matcher::Matcher()
54 : PhaseTransform( Phase::Ins_Select ),
55 #ifdef ASSERT
56 _old2new_map(C->comp_arena()),
57 _new2old_map(C->comp_arena()),
58 #endif
59 _shared_nodes(C->comp_arena()),
60 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
61 _swallowed(swallowed),
62 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
63 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
64 _must_clone(must_clone),
65 _register_save_policy(register_save_policy),
66 _c_reg_save_policy(c_reg_save_policy),
67 _register_save_type(register_save_type),
68 _ruleName(ruleName),
69 _allocation_started(false),
70 _states_arena(Chunk::medium_size),
71 _visited(&_states_arena),
72 _shared(&_states_arena),
73 _dontcare(&_states_arena) {
74 C->set_matcher(this);
75
76 idealreg2spillmask [Op_RegI] = NULL;
77 idealreg2spillmask [Op_RegN] = NULL;
78 idealreg2spillmask [Op_RegL] = NULL;
79 idealreg2spillmask [Op_RegF] = NULL;
80 idealreg2spillmask [Op_RegD] = NULL;
81 idealreg2spillmask [Op_RegP] = NULL;
82 idealreg2spillmask [Op_VecS] = NULL;
83 idealreg2spillmask [Op_VecD] = NULL;
84 idealreg2spillmask [Op_VecX] = NULL;
85 idealreg2spillmask [Op_VecY] = NULL;
86 idealreg2spillmask [Op_VecZ] = NULL;
87
88 idealreg2debugmask [Op_RegI] = NULL;
89 idealreg2debugmask [Op_RegN] = NULL;
90 idealreg2debugmask [Op_RegL] = NULL;
91 idealreg2debugmask [Op_RegF] = NULL;
92 idealreg2debugmask [Op_RegD] = NULL;
93 idealreg2debugmask [Op_RegP] = NULL;
94 idealreg2debugmask [Op_VecS] = NULL;
95 idealreg2debugmask [Op_VecD] = NULL;
96 idealreg2debugmask [Op_VecX] = NULL;
97 idealreg2debugmask [Op_VecY] = NULL;
98 idealreg2debugmask [Op_VecZ] = NULL;
99
100 idealreg2mhdebugmask[Op_RegI] = NULL;
101 idealreg2mhdebugmask[Op_RegN] = NULL;
102 idealreg2mhdebugmask[Op_RegL] = NULL;
103 idealreg2mhdebugmask[Op_RegF] = NULL;
104 idealreg2mhdebugmask[Op_RegD] = NULL;
105 idealreg2mhdebugmask[Op_RegP] = NULL;
106 idealreg2mhdebugmask[Op_VecS] = NULL;
107 idealreg2mhdebugmask[Op_VecD] = NULL;
108 idealreg2mhdebugmask[Op_VecX] = NULL;
109 idealreg2mhdebugmask[Op_VecY] = NULL;
110 idealreg2mhdebugmask[Op_VecZ] = NULL;
111
112 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
113 }
114
115 //------------------------------warp_incoming_stk_arg------------------------
116 // This warps a VMReg into an OptoReg::Name
117 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
118 OptoReg::Name warped;
119 if( reg->is_stack() ) { // Stack slot argument?
120 warped = OptoReg::add(_old_SP, reg->reg2stack() );
121 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
122 if( warped >= _in_arg_limit )
123 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
124 if (!RegMask::can_represent_arg(warped)) {
125 // the compiler cannot represent this method's calling sequence
126 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
127 return OptoReg::Bad;
128 }
129 return warped;
130 }
131 return OptoReg::as_OptoReg(reg);
132 }
133
134 //---------------------------compute_old_SP------------------------------------
135 OptoReg::Name Compile::compute_old_SP() {
136 int fixed = fixed_slots();
137 int preserve = in_preserve_stack_slots();
138 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
139 }
140
141
142
143 #ifdef ASSERT
144 void Matcher::verify_new_nodes_only(Node* xroot) {
145 // Make sure that the new graph only references new nodes
146 ResourceMark rm;
147 Unique_Node_List worklist;
148 VectorSet visited(Thread::current()->resource_area());
149 worklist.push(xroot);
150 while (worklist.size() > 0) {
151 Node* n = worklist.pop();
152 visited <<= n->_idx;
153 assert(C->node_arena()->contains(n), "dead node");
154 for (uint j = 0; j < n->req(); j++) {
155 Node* in = n->in(j);
156 if (in != NULL) {
157 assert(C->node_arena()->contains(in), "dead node");
158 if (!visited.test(in->_idx)) {
159 worklist.push(in);
160 }
161 }
162 }
163 }
164 }
165 #endif
166
167
168 //---------------------------match---------------------------------------------
169 void Matcher::match( ) {
170 if( MaxLabelRootDepth < 100 ) { // Too small?
171 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
172 MaxLabelRootDepth = 100;
173 }
174 // One-time initialization of some register masks.
175 init_spill_mask( C->root()->in(1) );
176 _return_addr_mask = return_addr();
177 #ifdef _LP64
178 // Pointers take 2 slots in 64-bit land
179 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
180 #endif
181
182 // Map a Java-signature return type into return register-value
183 // machine registers for 0, 1 and 2 returned values.
184 const TypeTuple *range = C->tf()->range();
185 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
186 // Get ideal-register return type
187 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
188 // Get machine return register
189 uint sop = C->start()->Opcode();
190 OptoRegPair regs = return_value(ireg, false);
191
192 // And mask for same
193 _return_value_mask = RegMask(regs.first());
194 if( OptoReg::is_valid(regs.second()) )
195 _return_value_mask.Insert(regs.second());
196 }
197
198 // ---------------
199 // Frame Layout
200
201 // Need the method signature to determine the incoming argument types,
202 // because the types determine which registers the incoming arguments are
203 // in, and this affects the matched code.
204 const TypeTuple *domain = C->tf()->domain();
205 uint argcnt = domain->cnt() - TypeFunc::Parms;
206 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
207 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
208 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
209 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
210 uint i;
211 for( i = 0; i<argcnt; i++ ) {
212 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
213 }
214
215 // Pass array of ideal registers and length to USER code (from the AD file)
216 // that will convert this to an array of register numbers.
217 const StartNode *start = C->start();
218 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
219 #ifdef ASSERT
220 // Sanity check users' calling convention. Real handy while trying to
221 // get the initial port correct.
222 { for (uint i = 0; i<argcnt; i++) {
223 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
224 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
225 _parm_regs[i].set_bad();
226 continue;
227 }
228 VMReg parm_reg = vm_parm_regs[i].first();
229 assert(parm_reg->is_valid(), "invalid arg?");
230 if (parm_reg->is_reg()) {
231 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
232 assert(can_be_java_arg(opto_parm_reg) ||
233 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
234 opto_parm_reg == inline_cache_reg(),
235 "parameters in register must be preserved by runtime stubs");
236 }
237 for (uint j = 0; j < i; j++) {
238 assert(parm_reg != vm_parm_regs[j].first(),
239 "calling conv. must produce distinct regs");
240 }
241 }
242 }
243 #endif
244
245 // Do some initial frame layout.
246
247 // Compute the old incoming SP (may be called FP) as
248 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
249 _old_SP = C->compute_old_SP();
250 assert( is_even(_old_SP), "must be even" );
251
252 // Compute highest incoming stack argument as
253 // _old_SP + out_preserve_stack_slots + incoming argument size.
254 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
255 assert( is_even(_in_arg_limit), "out_preserve must be even" );
256 for( i = 0; i < argcnt; i++ ) {
257 // Permit args to have no register
258 _calling_convention_mask[i].Clear();
259 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
260 continue;
261 }
262 // calling_convention returns stack arguments as a count of
263 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
264 // the allocators point of view, taking into account all the
265 // preserve area, locks & pad2.
266
267 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
268 if( OptoReg::is_valid(reg1))
269 _calling_convention_mask[i].Insert(reg1);
270
271 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
272 if( OptoReg::is_valid(reg2))
273 _calling_convention_mask[i].Insert(reg2);
274
275 // Saved biased stack-slot register number
276 _parm_regs[i].set_pair(reg2, reg1);
277 }
278
279 // Finally, make sure the incoming arguments take up an even number of
280 // words, in case the arguments or locals need to contain doubleword stack
281 // slots. The rest of the system assumes that stack slot pairs (in
282 // particular, in the spill area) which look aligned will in fact be
283 // aligned relative to the stack pointer in the target machine. Double
284 // stack slots will always be allocated aligned.
285 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
286
287 // Compute highest outgoing stack argument as
288 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
289 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
290 assert( is_even(_out_arg_limit), "out_preserve must be even" );
291
292 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
293 // the compiler cannot represent this method's calling sequence
294 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
295 }
296
297 if (C->failing()) return; // bailed out on incoming arg failure
298
299 // ---------------
300 // Collect roots of matcher trees. Every node for which
301 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
302 // can be a valid interior of some tree.
303 find_shared( C->root() );
304 find_shared( C->top() );
305
306 C->print_method(PHASE_BEFORE_MATCHING);
307
308 // Create new ideal node ConP #NULL even if it does exist in old space
309 // to avoid false sharing if the corresponding mach node is not used.
310 // The corresponding mach node is only used in rare cases for derived
311 // pointers.
312 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
313
314 // Swap out to old-space; emptying new-space
315 Arena *old = C->node_arena()->move_contents(C->old_arena());
316
317 // Save debug and profile information for nodes in old space:
318 _old_node_note_array = C->node_note_array();
319 if (_old_node_note_array != NULL) {
320 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
321 (C->comp_arena(), _old_node_note_array->length(),
322 0, NULL));
323 }
324
325 // Pre-size the new_node table to avoid the need for range checks.
326 grow_new_node_array(C->unique());
327
328 // Reset node counter so MachNodes start with _idx at 0
329 int live_nodes = C->live_nodes();
330 C->set_unique(0);
331 C->reset_dead_node_list();
332
333 // Recursively match trees from old space into new space.
334 // Correct leaves of new-space Nodes; they point to old-space.
335 _visited.Clear(); // Clear visit bits for xform call
336 C->set_cached_top_node(xform( C->top(), live_nodes ));
337 if (!C->failing()) {
338 Node* xroot = xform( C->root(), 1 );
339 if (xroot == NULL) {
340 Matcher::soft_match_failure(); // recursive matching process failed
341 C->record_method_not_compilable("instruction match failed");
342 } else {
343 // During matching shared constants were attached to C->root()
344 // because xroot wasn't available yet, so transfer the uses to
345 // the xroot.
346 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
347 Node* n = C->root()->fast_out(j);
348 if (C->node_arena()->contains(n)) {
349 assert(n->in(0) == C->root(), "should be control user");
350 n->set_req(0, xroot);
351 --j;
352 --jmax;
353 }
354 }
355
356 // Generate new mach node for ConP #NULL
357 assert(new_ideal_null != NULL, "sanity");
358 _mach_null = match_tree(new_ideal_null);
359 // Don't set control, it will confuse GCM since there are no uses.
360 // The control will be set when this node is used first time
361 // in find_base_for_derived().
362 assert(_mach_null != NULL, "");
363
364 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
365
366 #ifdef ASSERT
367 verify_new_nodes_only(xroot);
368 #endif
369 }
370 }
371 if (C->top() == NULL || C->root() == NULL) {
372 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
373 }
374 if (C->failing()) {
375 // delete old;
376 old->destruct_contents();
377 return;
378 }
379 assert( C->top(), "" );
380 assert( C->root(), "" );
381 validate_null_checks();
382
383 // Now smoke old-space
384 NOT_DEBUG( old->destruct_contents() );
385
386 // ------------------------
387 // Set up save-on-entry registers
388 Fixup_Save_On_Entry( );
389 }
390
391
392 //------------------------------Fixup_Save_On_Entry----------------------------
393 // The stated purpose of this routine is to take care of save-on-entry
394 // registers. However, the overall goal of the Match phase is to convert into
395 // machine-specific instructions which have RegMasks to guide allocation.
396 // So what this procedure really does is put a valid RegMask on each input
397 // to the machine-specific variations of all Return, TailCall and Halt
398 // instructions. It also adds edgs to define the save-on-entry values (and of
399 // course gives them a mask).
400
401 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
402 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
403 // Do all the pre-defined register masks
404 rms[TypeFunc::Control ] = RegMask::Empty;
405 rms[TypeFunc::I_O ] = RegMask::Empty;
406 rms[TypeFunc::Memory ] = RegMask::Empty;
407 rms[TypeFunc::ReturnAdr] = ret_adr;
408 rms[TypeFunc::FramePtr ] = fp;
409 return rms;
410 }
411
412 //---------------------------init_first_stack_mask-----------------------------
413 // Create the initial stack mask used by values spilling to the stack.
414 // Disallow any debug info in outgoing argument areas by setting the
415 // initial mask accordingly.
416 void Matcher::init_first_stack_mask() {
417
418 // Allocate storage for spill masks as masks for the appropriate load type.
419 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
420
421 idealreg2spillmask [Op_RegN] = &rms[0];
422 idealreg2spillmask [Op_RegI] = &rms[1];
423 idealreg2spillmask [Op_RegL] = &rms[2];
424 idealreg2spillmask [Op_RegF] = &rms[3];
425 idealreg2spillmask [Op_RegD] = &rms[4];
426 idealreg2spillmask [Op_RegP] = &rms[5];
427
428 idealreg2debugmask [Op_RegN] = &rms[6];
429 idealreg2debugmask [Op_RegI] = &rms[7];
430 idealreg2debugmask [Op_RegL] = &rms[8];
431 idealreg2debugmask [Op_RegF] = &rms[9];
432 idealreg2debugmask [Op_RegD] = &rms[10];
433 idealreg2debugmask [Op_RegP] = &rms[11];
434
435 idealreg2mhdebugmask[Op_RegN] = &rms[12];
436 idealreg2mhdebugmask[Op_RegI] = &rms[13];
437 idealreg2mhdebugmask[Op_RegL] = &rms[14];
438 idealreg2mhdebugmask[Op_RegF] = &rms[15];
439 idealreg2mhdebugmask[Op_RegD] = &rms[16];
440 idealreg2mhdebugmask[Op_RegP] = &rms[17];
441
442 idealreg2spillmask [Op_VecS] = &rms[18];
443 idealreg2spillmask [Op_VecD] = &rms[19];
444 idealreg2spillmask [Op_VecX] = &rms[20];
445 idealreg2spillmask [Op_VecY] = &rms[21];
446 idealreg2spillmask [Op_VecZ] = &rms[22];
447
448 OptoReg::Name i;
449
450 // At first, start with the empty mask
451 C->FIRST_STACK_mask().Clear();
452
453 // Add in the incoming argument area
454 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
455 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
456 C->FIRST_STACK_mask().Insert(i);
457 }
458 // Add in all bits past the outgoing argument area
459 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
460 "must be able to represent all call arguments in reg mask");
461 OptoReg::Name init = _out_arg_limit;
462 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
463 C->FIRST_STACK_mask().Insert(i);
464 }
465 // Finally, set the "infinite stack" bit.
466 C->FIRST_STACK_mask().set_AllStack();
467
468 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
469 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
470 // Keep spill masks aligned.
471 aligned_stack_mask.clear_to_pairs();
472 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
473
474 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
475 #ifdef _LP64
476 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
477 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
478 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
479 #else
480 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
481 #endif
482 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
483 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
484 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
485 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
486 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
487 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
488 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
489 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
490
491 if (Matcher::vector_size_supported(T_BYTE,4)) {
492 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
493 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
494 }
495 if (Matcher::vector_size_supported(T_FLOAT,2)) {
496 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
497 // RA guarantees such alignment since it is needed for Double and Long values.
498 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
499 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
500 }
501 if (Matcher::vector_size_supported(T_FLOAT,4)) {
502 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
503 //
504 // RA can use input arguments stack slots for spills but until RA
505 // we don't know frame size and offset of input arg stack slots.
506 //
507 // Exclude last input arg stack slots to avoid spilling vectors there
508 // otherwise vector spills could stomp over stack slots in caller frame.
509 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
510 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
511 aligned_stack_mask.Remove(in);
512 in = OptoReg::add(in, -1);
513 }
514 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
515 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
516 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
517 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
518 }
519 if (Matcher::vector_size_supported(T_FLOAT,8)) {
520 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
521 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
522 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
523 aligned_stack_mask.Remove(in);
524 in = OptoReg::add(in, -1);
525 }
526 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
527 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
528 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
529 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
530 }
531 if (Matcher::vector_size_supported(T_FLOAT,16)) {
532 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
533 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
534 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
535 aligned_stack_mask.Remove(in);
536 in = OptoReg::add(in, -1);
537 }
538 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
539 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
540 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
541 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
542 }
543 if (UseFPUForSpilling) {
544 // This mask logic assumes that the spill operations are
545 // symmetric and that the registers involved are the same size.
546 // On sparc for instance we may have to use 64 bit moves will
547 // kill 2 registers when used with F0-F31.
548 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
549 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
550 #ifdef _LP64
551 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
552 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
553 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
554 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
555 #else
556 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
557 #ifdef ARM
558 // ARM has support for moving 64bit values between a pair of
559 // integer registers and a double register
560 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
561 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
562 #endif
563 #endif
564 }
565
566 // Make up debug masks. Any spill slot plus callee-save registers.
567 // Caller-save registers are assumed to be trashable by the various
568 // inline-cache fixup routines.
569 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
570 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
571 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
572 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
573 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
574 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
575
576 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
577 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
578 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
579 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
580 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
581 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
582
583 // Prevent stub compilations from attempting to reference
584 // callee-saved registers from debug info
585 bool exclude_soe = !Compile::current()->is_method_compilation();
586
587 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
588 // registers the caller has to save do not work
589 if( _register_save_policy[i] == 'C' ||
590 _register_save_policy[i] == 'A' ||
591 (_register_save_policy[i] == 'E' && exclude_soe) ) {
592 idealreg2debugmask [Op_RegN]->Remove(i);
593 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
594 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
595 idealreg2debugmask [Op_RegF]->Remove(i); // masks
596 idealreg2debugmask [Op_RegD]->Remove(i);
597 idealreg2debugmask [Op_RegP]->Remove(i);
598
599 idealreg2mhdebugmask[Op_RegN]->Remove(i);
600 idealreg2mhdebugmask[Op_RegI]->Remove(i);
601 idealreg2mhdebugmask[Op_RegL]->Remove(i);
602 idealreg2mhdebugmask[Op_RegF]->Remove(i);
603 idealreg2mhdebugmask[Op_RegD]->Remove(i);
604 idealreg2mhdebugmask[Op_RegP]->Remove(i);
605 }
606 }
607
608 // Subtract the register we use to save the SP for MethodHandle
609 // invokes to from the debug mask.
610 const RegMask save_mask = method_handle_invoke_SP_save_mask();
611 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
612 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
617 }
618
619 //---------------------------is_save_on_entry----------------------------------
620 bool Matcher::is_save_on_entry( int reg ) {
621 return
622 _register_save_policy[reg] == 'E' ||
623 _register_save_policy[reg] == 'A' || // Save-on-entry register?
624 // Also save argument registers in the trampolining stubs
625 (C->save_argument_registers() && is_spillable_arg(reg));
626 }
627
628 //---------------------------Fixup_Save_On_Entry-------------------------------
629 void Matcher::Fixup_Save_On_Entry( ) {
630 init_first_stack_mask();
631
632 Node *root = C->root(); // Short name for root
633 // Count number of save-on-entry registers.
634 uint soe_cnt = number_of_saved_registers();
635 uint i;
636
637 // Find the procedure Start Node
638 StartNode *start = C->start();
639 assert( start, "Expect a start node" );
640
641 // Save argument registers in the trampolining stubs
642 if( C->save_argument_registers() )
643 for( i = 0; i < _last_Mach_Reg; i++ )
644 if( is_spillable_arg(i) )
645 soe_cnt++;
646
647 // Input RegMask array shared by all Returns.
648 // The type for doubles and longs has a count of 2, but
649 // there is only 1 returned value
650 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
651 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
652 // Returns have 0 or 1 returned values depending on call signature.
653 // Return register is specified by return_value in the AD file.
654 if (ret_edge_cnt > TypeFunc::Parms)
655 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
656
657 // Input RegMask array shared by all Rethrows.
658 uint reth_edge_cnt = TypeFunc::Parms+1;
659 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
660 // Rethrow takes exception oop only, but in the argument 0 slot.
661 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
662 #ifdef _LP64
663 // Need two slots for ptrs in 64-bit land
664 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
665 #endif
666
667 // Input RegMask array shared by all TailCalls
668 uint tail_call_edge_cnt = TypeFunc::Parms+2;
669 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
670
671 // Input RegMask array shared by all TailJumps
672 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
673 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674
675 // TailCalls have 2 returned values (target & moop), whose masks come
676 // from the usual MachNode/MachOper mechanism. Find a sample
677 // TailCall to extract these masks and put the correct masks into
678 // the tail_call_rms array.
679 for( i=1; i < root->req(); i++ ) {
680 MachReturnNode *m = root->in(i)->as_MachReturn();
681 if( m->ideal_Opcode() == Op_TailCall ) {
682 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
683 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
684 break;
685 }
686 }
687
688 // TailJumps have 2 returned values (target & ex_oop), whose masks come
689 // from the usual MachNode/MachOper mechanism. Find a sample
690 // TailJump to extract these masks and put the correct masks into
691 // the tail_jump_rms array.
692 for( i=1; i < root->req(); i++ ) {
693 MachReturnNode *m = root->in(i)->as_MachReturn();
694 if( m->ideal_Opcode() == Op_TailJump ) {
695 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
696 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
697 break;
698 }
699 }
700
701 // Input RegMask array shared by all Halts
702 uint halt_edge_cnt = TypeFunc::Parms;
703 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
704
705 // Capture the return input masks into each exit flavor
706 for( i=1; i < root->req(); i++ ) {
707 MachReturnNode *exit = root->in(i)->as_MachReturn();
708 switch( exit->ideal_Opcode() ) {
709 case Op_Return : exit->_in_rms = ret_rms; break;
710 case Op_Rethrow : exit->_in_rms = reth_rms; break;
711 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
712 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
713 case Op_Halt : exit->_in_rms = halt_rms; break;
714 default : ShouldNotReachHere();
715 }
716 }
717
718 // Next unused projection number from Start.
719 int proj_cnt = C->tf()->domain()->cnt();
720
721 // Do all the save-on-entry registers. Make projections from Start for
722 // them, and give them a use at the exit points. To the allocator, they
723 // look like incoming register arguments.
724 for( i = 0; i < _last_Mach_Reg; i++ ) {
725 if( is_save_on_entry(i) ) {
726
727 // Add the save-on-entry to the mask array
728 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
729 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
730 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
731 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
732 // Halts need the SOE registers, but only in the stack as debug info.
733 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
734 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
735
736 Node *mproj;
737
738 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
739 // into a single RegD.
740 if( (i&1) == 0 &&
741 _register_save_type[i ] == Op_RegF &&
742 _register_save_type[i+1] == Op_RegF &&
743 is_save_on_entry(i+1) ) {
744 // Add other bit for double
745 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
746 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
747 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
748 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
749 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
750 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
751 proj_cnt += 2; // Skip 2 for doubles
752 }
753 else if( (i&1) == 1 && // Else check for high half of double
754 _register_save_type[i-1] == Op_RegF &&
755 _register_save_type[i ] == Op_RegF &&
756 is_save_on_entry(i-1) ) {
757 ret_rms [ ret_edge_cnt] = RegMask::Empty;
758 reth_rms [ reth_edge_cnt] = RegMask::Empty;
759 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
760 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
761 halt_rms [ halt_edge_cnt] = RegMask::Empty;
762 mproj = C->top();
763 }
764 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
765 // into a single RegL.
766 else if( (i&1) == 0 &&
767 _register_save_type[i ] == Op_RegI &&
768 _register_save_type[i+1] == Op_RegI &&
769 is_save_on_entry(i+1) ) {
770 // Add other bit for long
771 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
772 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
773 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
774 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
775 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
776 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
777 proj_cnt += 2; // Skip 2 for longs
778 }
779 else if( (i&1) == 1 && // Else check for high half of long
780 _register_save_type[i-1] == Op_RegI &&
781 _register_save_type[i ] == Op_RegI &&
782 is_save_on_entry(i-1) ) {
783 ret_rms [ ret_edge_cnt] = RegMask::Empty;
784 reth_rms [ reth_edge_cnt] = RegMask::Empty;
785 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
786 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
787 halt_rms [ halt_edge_cnt] = RegMask::Empty;
788 mproj = C->top();
789 } else {
790 // Make a projection for it off the Start
791 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
792 }
793
794 ret_edge_cnt ++;
795 reth_edge_cnt ++;
796 tail_call_edge_cnt ++;
797 tail_jump_edge_cnt ++;
798 halt_edge_cnt ++;
799
800 // Add a use of the SOE register to all exit paths
801 for( uint j=1; j < root->req(); j++ )
802 root->in(j)->add_req(mproj);
803 } // End of if a save-on-entry register
804 } // End of for all machine registers
805 }
806
807 //------------------------------init_spill_mask--------------------------------
808 void Matcher::init_spill_mask( Node *ret ) {
809 if( idealreg2regmask[Op_RegI] ) return; // One time only init
810
811 OptoReg::c_frame_pointer = c_frame_pointer();
812 c_frame_ptr_mask = c_frame_pointer();
813 #ifdef _LP64
814 // pointers are twice as big
815 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
816 #endif
817
818 // Start at OptoReg::stack0()
819 STACK_ONLY_mask.Clear();
820 OptoReg::Name init = OptoReg::stack2reg(0);
821 // STACK_ONLY_mask is all stack bits
822 OptoReg::Name i;
823 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
824 STACK_ONLY_mask.Insert(i);
825 // Also set the "infinite stack" bit.
826 STACK_ONLY_mask.set_AllStack();
827
828 // Copy the register names over into the shared world
829 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
830 // SharedInfo::regName[i] = regName[i];
831 // Handy RegMasks per machine register
832 mreg2regmask[i].Insert(i);
833 }
834
835 // Grab the Frame Pointer
836 Node *fp = ret->in(TypeFunc::FramePtr);
837 Node *mem = ret->in(TypeFunc::Memory);
838 const TypePtr* atp = TypePtr::BOTTOM;
839 // Share frame pointer while making spill ops
840 set_shared(fp);
841
842 // Compute generic short-offset Loads
843 #ifdef _LP64
844 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
845 #endif
846 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
847 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
848 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
849 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
850 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
851 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
852 spillD != NULL && spillP != NULL, "");
853 // Get the ADLC notion of the right regmask, for each basic type.
854 #ifdef _LP64
855 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
856 #endif
857 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
858 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
859 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
860 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
861 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
862
863 // Vector regmasks.
864 if (Matcher::vector_size_supported(T_BYTE,4)) {
865 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
866 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
867 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
868 }
869 if (Matcher::vector_size_supported(T_FLOAT,2)) {
870 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
871 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
872 }
873 if (Matcher::vector_size_supported(T_FLOAT,4)) {
874 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
875 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
876 }
877 if (Matcher::vector_size_supported(T_FLOAT,8)) {
878 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
879 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
880 }
881 if (Matcher::vector_size_supported(T_FLOAT,16)) {
882 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
883 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
884 }
885 }
886
887 #ifdef ASSERT
888 static void match_alias_type(Compile* C, Node* n, Node* m) {
889 if (!VerifyAliases) return; // do not go looking for trouble by default
890 const TypePtr* nat = n->adr_type();
891 const TypePtr* mat = m->adr_type();
892 int nidx = C->get_alias_index(nat);
893 int midx = C->get_alias_index(mat);
894 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
895 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
896 for (uint i = 1; i < n->req(); i++) {
897 Node* n1 = n->in(i);
898 const TypePtr* n1at = n1->adr_type();
899 if (n1at != NULL) {
900 nat = n1at;
901 nidx = C->get_alias_index(n1at);
902 }
903 }
904 }
905 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
906 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
907 switch (n->Opcode()) {
908 case Op_PrefetchAllocation:
909 nidx = Compile::AliasIdxRaw;
910 nat = TypeRawPtr::BOTTOM;
911 break;
912 }
913 }
914 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
915 switch (n->Opcode()) {
916 case Op_ClearArray:
917 midx = Compile::AliasIdxRaw;
918 mat = TypeRawPtr::BOTTOM;
919 break;
920 }
921 }
922 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
923 switch (n->Opcode()) {
924 case Op_Return:
925 case Op_Rethrow:
926 case Op_Halt:
927 case Op_TailCall:
928 case Op_TailJump:
929 nidx = Compile::AliasIdxBot;
930 nat = TypePtr::BOTTOM;
931 break;
932 }
933 }
934 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
935 switch (n->Opcode()) {
936 case Op_StrComp:
937 case Op_StrEquals:
938 case Op_StrIndexOf:
939 case Op_AryEq:
940 case Op_MemBarVolatile:
941 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
942 case Op_EncodeISOArray:
943 nidx = Compile::AliasIdxTop;
944 nat = NULL;
945 break;
946 }
947 }
948 if (nidx != midx) {
949 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
950 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
951 n->dump();
952 m->dump();
953 }
954 assert(C->subsume_loads() && C->must_alias(nat, midx),
955 "must not lose alias info when matching");
956 }
957 }
958 #endif
959
960
961 //------------------------------MStack-----------------------------------------
962 // State and MStack class used in xform() and find_shared() iterative methods.
963 enum Node_State { Pre_Visit, // node has to be pre-visited
964 Visit, // visit node
965 Post_Visit, // post-visit node
966 Alt_Post_Visit // alternative post-visit path
967 };
968
969 class MStack: public Node_Stack {
970 public:
971 MStack(int size) : Node_Stack(size) { }
972
973 void push(Node *n, Node_State ns) {
974 Node_Stack::push(n, (uint)ns);
975 }
976 void push(Node *n, Node_State ns, Node *parent, int indx) {
977 ++_inode_top;
978 if ((_inode_top + 1) >= _inode_max) grow();
979 _inode_top->node = parent;
980 _inode_top->indx = (uint)indx;
981 ++_inode_top;
982 _inode_top->node = n;
983 _inode_top->indx = (uint)ns;
984 }
985 Node *parent() {
986 pop();
987 return node();
988 }
989 Node_State state() const {
990 return (Node_State)index();
991 }
992 void set_state(Node_State ns) {
993 set_index((uint)ns);
994 }
995 };
996
997
998 //------------------------------xform------------------------------------------
999 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1000 // Node in new-space. Given a new-space Node, recursively walk his children.
1001 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1002 Node *Matcher::xform( Node *n, int max_stack ) {
1003 // Use one stack to keep both: child's node/state and parent's node/index
1004 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1005 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1006
1007 while (mstack.is_nonempty()) {
1008 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1009 if (C->failing()) return NULL;
1010 n = mstack.node(); // Leave node on stack
1011 Node_State nstate = mstack.state();
1012 if (nstate == Visit) {
1013 mstack.set_state(Post_Visit);
1014 Node *oldn = n;
1015 // Old-space or new-space check
1016 if (!C->node_arena()->contains(n)) {
1017 // Old space!
1018 Node* m;
1019 if (has_new_node(n)) { // Not yet Label/Reduced
1020 m = new_node(n);
1021 } else {
1022 if (!is_dontcare(n)) { // Matcher can match this guy
1023 // Calls match special. They match alone with no children.
1024 // Their children, the incoming arguments, match normally.
1025 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1026 if (C->failing()) return NULL;
1027 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1028 } else { // Nothing the matcher cares about
1029 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections?
1030 // Convert to machine-dependent projection
1031 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1032 #ifdef ASSERT
1033 _new2old_map.map(m->_idx, n);
1034 #endif
1035 if (m->in(0) != NULL) // m might be top
1036 collect_null_checks(m, n);
1037 } else { // Else just a regular 'ol guy
1038 m = n->clone(); // So just clone into new-space
1039 #ifdef ASSERT
1040 _new2old_map.map(m->_idx, n);
1041 #endif
1042 // Def-Use edges will be added incrementally as Uses
1043 // of this node are matched.
1044 assert(m->outcnt() == 0, "no Uses of this clone yet");
1045 }
1046 }
1047
1048 set_new_node(n, m); // Map old to new
1049 if (_old_node_note_array != NULL) {
1050 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1051 n->_idx);
1052 C->set_node_notes_at(m->_idx, nn);
1053 }
1054 debug_only(match_alias_type(C, n, m));
1055 }
1056 n = m; // n is now a new-space node
1057 mstack.set_node(n);
1058 }
1059
1060 // New space!
1061 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1062
1063 int i;
1064 // Put precedence edges on stack first (match them last).
1065 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1066 Node *m = oldn->in(i);
1067 if (m == NULL) break;
1068 // set -1 to call add_prec() instead of set_req() during Step1
1069 mstack.push(m, Visit, n, -1);
1070 }
1071
1072 // Handle precedence edges for interior nodes
1073 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1074 Node *m = n->in(i);
1075 if (m == NULL || C->node_arena()->contains(m)) continue;
1076 n->rm_prec(i);
1077 // set -1 to call add_prec() instead of set_req() during Step1
1078 mstack.push(m, Visit, n, -1);
1079 }
1080
1081 // For constant debug info, I'd rather have unmatched constants.
1082 int cnt = n->req();
1083 JVMState* jvms = n->jvms();
1084 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1085
1086 // Now do only debug info. Clone constants rather than matching.
1087 // Constants are represented directly in the debug info without
1088 // the need for executable machine instructions.
1089 // Monitor boxes are also represented directly.
1090 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1091 Node *m = n->in(i); // Get input
1092 int op = m->Opcode();
1093 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1094 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1095 op == Op_ConF || op == Op_ConD || op == Op_ConL
1096 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1097 ) {
1098 m = m->clone();
1099 #ifdef ASSERT
1100 _new2old_map.map(m->_idx, n);
1101 #endif
1102 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1103 mstack.push(m->in(0), Visit, m, 0);
1104 } else {
1105 mstack.push(m, Visit, n, i);
1106 }
1107 }
1108
1109 // And now walk his children, and convert his inputs to new-space.
1110 for( ; i >= 0; --i ) { // For all normal inputs do
1111 Node *m = n->in(i); // Get input
1112 if(m != NULL)
1113 mstack.push(m, Visit, n, i);
1114 }
1115
1116 }
1117 else if (nstate == Post_Visit) {
1118 // Set xformed input
1119 Node *p = mstack.parent();
1120 if (p != NULL) { // root doesn't have parent
1121 int i = (int)mstack.index();
1122 if (i >= 0)
1123 p->set_req(i, n); // required input
1124 else if (i == -1)
1125 p->add_prec(n); // precedence input
1126 else
1127 ShouldNotReachHere();
1128 }
1129 mstack.pop(); // remove processed node from stack
1130 }
1131 else {
1132 ShouldNotReachHere();
1133 }
1134 } // while (mstack.is_nonempty())
1135 return n; // Return new-space Node
1136 }
1137
1138 //------------------------------warp_outgoing_stk_arg------------------------
1139 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1140 // Convert outgoing argument location to a pre-biased stack offset
1141 if (reg->is_stack()) {
1142 OptoReg::Name warped = reg->reg2stack();
1143 // Adjust the stack slot offset to be the register number used
1144 // by the allocator.
1145 warped = OptoReg::add(begin_out_arg_area, warped);
1146 // Keep track of the largest numbered stack slot used for an arg.
1147 // Largest used slot per call-site indicates the amount of stack
1148 // that is killed by the call.
1149 if( warped >= out_arg_limit_per_call )
1150 out_arg_limit_per_call = OptoReg::add(warped,1);
1151 if (!RegMask::can_represent_arg(warped)) {
1152 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1153 return OptoReg::Bad;
1154 }
1155 return warped;
1156 }
1157 return OptoReg::as_OptoReg(reg);
1158 }
1159
1160
1161 //------------------------------match_sfpt-------------------------------------
1162 // Helper function to match call instructions. Calls match special.
1163 // They match alone with no children. Their children, the incoming
1164 // arguments, match normally.
1165 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1166 MachSafePointNode *msfpt = NULL;
1167 MachCallNode *mcall = NULL;
1168 uint cnt;
1169 // Split out case for SafePoint vs Call
1170 CallNode *call;
1171 const TypeTuple *domain;
1172 ciMethod* method = NULL;
1173 bool is_method_handle_invoke = false; // for special kill effects
1174 if( sfpt->is_Call() ) {
1175 call = sfpt->as_Call();
1176 domain = call->tf()->domain();
1177 cnt = domain->cnt();
1178
1179 // Match just the call, nothing else
1180 MachNode *m = match_tree(call);
1181 if (C->failing()) return NULL;
1182 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1183
1184 // Copy data from the Ideal SafePoint to the machine version
1185 mcall = m->as_MachCall();
1186
1187 mcall->set_tf( call->tf());
1188 mcall->set_entry_point(call->entry_point());
1189 mcall->set_cnt( call->cnt());
1190
1191 if( mcall->is_MachCallJava() ) {
1192 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1193 const CallJavaNode *call_java = call->as_CallJava();
1194 method = call_java->method();
1195 mcall_java->_method = method;
1196 mcall_java->_bci = call_java->_bci;
1197 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1198 is_method_handle_invoke = call_java->is_method_handle_invoke();
1199 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1200 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1201 if (is_method_handle_invoke) {
1202 C->set_has_method_handle_invokes(true);
1203 }
1204 if( mcall_java->is_MachCallStaticJava() )
1205 mcall_java->as_MachCallStaticJava()->_name =
1206 call_java->as_CallStaticJava()->_name;
1207 if( mcall_java->is_MachCallDynamicJava() )
1208 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1209 call_java->as_CallDynamicJava()->_vtable_index;
1210 }
1211 else if( mcall->is_MachCallRuntime() ) {
1212 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1213 }
1214 msfpt = mcall;
1215 }
1216 // This is a non-call safepoint
1217 else {
1218 call = NULL;
1219 domain = NULL;
1220 MachNode *mn = match_tree(sfpt);
1221 if (C->failing()) return NULL;
1222 msfpt = mn->as_MachSafePoint();
1223 cnt = TypeFunc::Parms;
1224 }
1225
1226 // Advertise the correct memory effects (for anti-dependence computation).
1227 msfpt->set_adr_type(sfpt->adr_type());
1228
1229 // Allocate a private array of RegMasks. These RegMasks are not shared.
1230 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1231 // Empty them all.
1232 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1233
1234 // Do all the pre-defined non-Empty register masks
1235 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1236 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1237
1238 // Place first outgoing argument can possibly be put.
1239 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1240 assert( is_even(begin_out_arg_area), "" );
1241 // Compute max outgoing register number per call site.
1242 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1243 // Calls to C may hammer extra stack slots above and beyond any arguments.
1244 // These are usually backing store for register arguments for varargs.
1245 if( call != NULL && call->is_CallRuntime() )
1246 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1247
1248
1249 // Do the normal argument list (parameters) register masks
1250 int argcnt = cnt - TypeFunc::Parms;
1251 if( argcnt > 0 ) { // Skip it all if we have no args
1252 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1253 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1254 int i;
1255 for( i = 0; i < argcnt; i++ ) {
1256 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1257 }
1258 // V-call to pick proper calling convention
1259 call->calling_convention( sig_bt, parm_regs, argcnt );
1260
1261 #ifdef ASSERT
1262 // Sanity check users' calling convention. Really handy during
1263 // the initial porting effort. Fairly expensive otherwise.
1264 { for (int i = 0; i<argcnt; i++) {
1265 if( !parm_regs[i].first()->is_valid() &&
1266 !parm_regs[i].second()->is_valid() ) continue;
1267 VMReg reg1 = parm_regs[i].first();
1268 VMReg reg2 = parm_regs[i].second();
1269 for (int j = 0; j < i; j++) {
1270 if( !parm_regs[j].first()->is_valid() &&
1271 !parm_regs[j].second()->is_valid() ) continue;
1272 VMReg reg3 = parm_regs[j].first();
1273 VMReg reg4 = parm_regs[j].second();
1274 if( !reg1->is_valid() ) {
1275 assert( !reg2->is_valid(), "valid halvsies" );
1276 } else if( !reg3->is_valid() ) {
1277 assert( !reg4->is_valid(), "valid halvsies" );
1278 } else {
1279 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1280 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1281 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1282 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1283 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1284 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1285 }
1286 }
1287 }
1288 }
1289 #endif
1290
1291 // Visit each argument. Compute its outgoing register mask.
1292 // Return results now can have 2 bits returned.
1293 // Compute max over all outgoing arguments both per call-site
1294 // and over the entire method.
1295 for( i = 0; i < argcnt; i++ ) {
1296 // Address of incoming argument mask to fill in
1297 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1298 if( !parm_regs[i].first()->is_valid() &&
1299 !parm_regs[i].second()->is_valid() ) {
1300 continue; // Avoid Halves
1301 }
1302 // Grab first register, adjust stack slots and insert in mask.
1303 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1304 if (OptoReg::is_valid(reg1))
1305 rm->Insert( reg1 );
1306 // Grab second register (if any), adjust stack slots and insert in mask.
1307 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1308 if (OptoReg::is_valid(reg2))
1309 rm->Insert( reg2 );
1310 } // End of for all arguments
1311
1312 // Compute number of stack slots needed to restore stack in case of
1313 // Pascal-style argument popping.
1314 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1315 }
1316
1317 // Compute the max stack slot killed by any call. These will not be
1318 // available for debug info, and will be used to adjust FIRST_STACK_mask
1319 // after all call sites have been visited.
1320 if( _out_arg_limit < out_arg_limit_per_call)
1321 _out_arg_limit = out_arg_limit_per_call;
1322
1323 if (mcall) {
1324 // Kill the outgoing argument area, including any non-argument holes and
1325 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1326 // Since the max-per-method covers the max-per-call-site and debug info
1327 // is excluded on the max-per-method basis, debug info cannot land in
1328 // this killed area.
1329 uint r_cnt = mcall->tf()->range()->cnt();
1330 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1331 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1332 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1333 } else {
1334 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1335 proj->_rout.Insert(OptoReg::Name(i));
1336 }
1337 if (proj->_rout.is_NotEmpty()) {
1338 push_projection(proj);
1339 }
1340 }
1341 // Transfer the safepoint information from the call to the mcall
1342 // Move the JVMState list
1343 msfpt->set_jvms(sfpt->jvms());
1344 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1345 jvms->set_map(sfpt);
1346 }
1347
1348 // Debug inputs begin just after the last incoming parameter
1349 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1350 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1351
1352 // Move the OopMap
1353 msfpt->_oop_map = sfpt->_oop_map;
1354
1355 // Add additional edges.
1356 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1357 // For these calls we can not add MachConstantBase in expand(), as the
1358 // ins are not complete then.
1359 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1360 if (msfpt->jvms() &&
1361 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1362 // We added an edge before jvms, so we must adapt the position of the ins.
1363 msfpt->jvms()->adapt_position(+1);
1364 }
1365 }
1366
1367 // Registers killed by the call are set in the local scheduling pass
1368 // of Global Code Motion.
1369 return msfpt;
1370 }
1371
1372 //---------------------------match_tree----------------------------------------
1373 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1374 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1375 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1376 // a Load's result RegMask for memoization in idealreg2regmask[]
1377 MachNode *Matcher::match_tree( const Node *n ) {
1378 assert( n->Opcode() != Op_Phi, "cannot match" );
1379 assert( !n->is_block_start(), "cannot match" );
1380 // Set the mark for all locally allocated State objects.
1381 // When this call returns, the _states_arena arena will be reset
1382 // freeing all State objects.
1383 ResourceMark rm( &_states_arena );
1384
1385 LabelRootDepth = 0;
1386
1387 // StoreNodes require their Memory input to match any LoadNodes
1388 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1389 #ifdef ASSERT
1390 Node* save_mem_node = _mem_node;
1391 _mem_node = n->is_Store() ? (Node*)n : NULL;
1392 #endif
1393 // State object for root node of match tree
1394 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1395 State *s = new (&_states_arena) State;
1396 s->_kids[0] = NULL;
1397 s->_kids[1] = NULL;
1398 s->_leaf = (Node*)n;
1399 // Label the input tree, allocating labels from top-level arena
1400 Label_Root( n, s, n->in(0), mem );
1401 if (C->failing()) return NULL;
1402
1403 // The minimum cost match for the whole tree is found at the root State
1404 uint mincost = max_juint;
1405 uint cost = max_juint;
1406 uint i;
1407 for( i = 0; i < NUM_OPERANDS; i++ ) {
1408 if( s->valid(i) && // valid entry and
1409 s->_cost[i] < cost && // low cost and
1410 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1411 cost = s->_cost[mincost=i];
1412 }
1413 if (mincost == max_juint) {
1414 #ifndef PRODUCT
1415 tty->print("No matching rule for:");
1416 s->dump();
1417 #endif
1418 Matcher::soft_match_failure();
1419 return NULL;
1420 }
1421 // Reduce input tree based upon the state labels to machine Nodes
1422 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1423 #ifdef ASSERT
1424 _old2new_map.map(n->_idx, m);
1425 _new2old_map.map(m->_idx, (Node*)n);
1426 #endif
1427
1428 // Add any Matcher-ignored edges
1429 uint cnt = n->req();
1430 uint start = 1;
1431 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1432 if( n->is_AddP() ) {
1433 assert( mem == (Node*)1, "" );
1434 start = AddPNode::Base+1;
1435 }
1436 for( i = start; i < cnt; i++ ) {
1437 if( !n->match_edge(i) ) {
1438 if( i < m->req() )
1439 m->ins_req( i, n->in(i) );
1440 else
1441 m->add_req( n->in(i) );
1442 }
1443 }
1444
1445 debug_only( _mem_node = save_mem_node; )
1446 return m;
1447 }
1448
1449
1450 //------------------------------match_into_reg---------------------------------
1451 // Choose to either match this Node in a register or part of the current
1452 // match tree. Return true for requiring a register and false for matching
1453 // as part of the current match tree.
1454 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1455
1456 const Type *t = m->bottom_type();
1457
1458 if (t->singleton()) {
1459 // Never force constants into registers. Allow them to match as
1460 // constants or registers. Copies of the same value will share
1461 // the same register. See find_shared_node.
1462 return false;
1463 } else { // Not a constant
1464 // Stop recursion if they have different Controls.
1465 Node* m_control = m->in(0);
1466 // Control of load's memory can post-dominates load's control.
1467 // So use it since load can't float above its memory.
1468 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1469 if (control && m_control && control != m_control && control != mem_control) {
1470
1471 // Actually, we can live with the most conservative control we
1472 // find, if it post-dominates the others. This allows us to
1473 // pick up load/op/store trees where the load can float a little
1474 // above the store.
1475 Node *x = control;
1476 const uint max_scan = 6; // Arbitrary scan cutoff
1477 uint j;
1478 for (j=0; j<max_scan; j++) {
1479 if (x->is_Region()) // Bail out at merge points
1480 return true;
1481 x = x->in(0);
1482 if (x == m_control) // Does 'control' post-dominate
1483 break; // m->in(0)? If so, we can use it
1484 if (x == mem_control) // Does 'control' post-dominate
1485 break; // mem_control? If so, we can use it
1486 }
1487 if (j == max_scan) // No post-domination before scan end?
1488 return true; // Then break the match tree up
1489 }
1490 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1491 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1492 // These are commonly used in address expressions and can
1493 // efficiently fold into them on X64 in some cases.
1494 return false;
1495 }
1496 }
1497
1498 // Not forceable cloning. If shared, put it into a register.
1499 return shared;
1500 }
1501
1502
1503 //------------------------------Instruction Selection--------------------------
1504 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1505 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1506 // things the Matcher does not match (e.g., Memory), and things with different
1507 // Controls (hence forced into different blocks). We pass in the Control
1508 // selected for this entire State tree.
1509
1510 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1511 // Store and the Load must have identical Memories (as well as identical
1512 // pointers). Since the Matcher does not have anything for Memory (and
1513 // does not handle DAGs), I have to match the Memory input myself. If the
1514 // Tree root is a Store, I require all Loads to have the identical memory.
1515 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1516 // Since Label_Root is a recursive function, its possible that we might run
1517 // out of stack space. See bugs 6272980 & 6227033 for more info.
1518 LabelRootDepth++;
1519 if (LabelRootDepth > MaxLabelRootDepth) {
1520 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1521 return NULL;
1522 }
1523 uint care = 0; // Edges matcher cares about
1524 uint cnt = n->req();
1525 uint i = 0;
1526
1527 // Examine children for memory state
1528 // Can only subsume a child into your match-tree if that child's memory state
1529 // is not modified along the path to another input.
1530 // It is unsafe even if the other inputs are separate roots.
1531 Node *input_mem = NULL;
1532 for( i = 1; i < cnt; i++ ) {
1533 if( !n->match_edge(i) ) continue;
1534 Node *m = n->in(i); // Get ith input
1535 assert( m, "expect non-null children" );
1536 if( m->is_Load() ) {
1537 if( input_mem == NULL ) {
1538 input_mem = m->in(MemNode::Memory);
1539 } else if( input_mem != m->in(MemNode::Memory) ) {
1540 input_mem = NodeSentinel;
1541 }
1542 }
1543 }
1544
1545 for( i = 1; i < cnt; i++ ){// For my children
1546 if( !n->match_edge(i) ) continue;
1547 Node *m = n->in(i); // Get ith input
1548 // Allocate states out of a private arena
1549 State *s = new (&_states_arena) State;
1550 svec->_kids[care++] = s;
1551 assert( care <= 2, "binary only for now" );
1552
1553 // Recursively label the State tree.
1554 s->_kids[0] = NULL;
1555 s->_kids[1] = NULL;
1556 s->_leaf = m;
1557
1558 // Check for leaves of the State Tree; things that cannot be a part of
1559 // the current tree. If it finds any, that value is matched as a
1560 // register operand. If not, then the normal matching is used.
1561 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1562 //
1563 // Stop recursion if this is LoadNode and the root of this tree is a
1564 // StoreNode and the load & store have different memories.
1565 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1566 // Can NOT include the match of a subtree when its memory state
1567 // is used by any of the other subtrees
1568 (input_mem == NodeSentinel) ) {
1569 #ifndef PRODUCT
1570 // Print when we exclude matching due to different memory states at input-loads
1571 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1572 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1573 tty->print_cr("invalid input_mem");
1574 }
1575 #endif
1576 // Switch to a register-only opcode; this value must be in a register
1577 // and cannot be subsumed as part of a larger instruction.
1578 s->DFA( m->ideal_reg(), m );
1579
1580 } else {
1581 // If match tree has no control and we do, adopt it for entire tree
1582 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1583 control = m->in(0); // Pick up control
1584 // Else match as a normal part of the match tree.
1585 control = Label_Root(m,s,control,mem);
1586 if (C->failing()) return NULL;
1587 }
1588 }
1589
1590
1591 // Call DFA to match this node, and return
1592 svec->DFA( n->Opcode(), n );
1593
1594 #ifdef ASSERT
1595 uint x;
1596 for( x = 0; x < _LAST_MACH_OPER; x++ )
1597 if( svec->valid(x) )
1598 break;
1599
1600 if (x >= _LAST_MACH_OPER) {
1601 n->dump();
1602 svec->dump();
1603 assert( false, "bad AD file" );
1604 }
1605 #endif
1606 return control;
1607 }
1608
1609
1610 // Con nodes reduced using the same rule can share their MachNode
1611 // which reduces the number of copies of a constant in the final
1612 // program. The register allocator is free to split uses later to
1613 // split live ranges.
1614 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1615 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1616
1617 // See if this Con has already been reduced using this rule.
1618 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1619 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1620 if (last != NULL && rule == last->rule()) {
1621 // Don't expect control change for DecodeN
1622 if (leaf->is_DecodeNarrowPtr())
1623 return last;
1624 // Get the new space root.
1625 Node* xroot = new_node(C->root());
1626 if (xroot == NULL) {
1627 // This shouldn't happen give the order of matching.
1628 return NULL;
1629 }
1630
1631 // Shared constants need to have their control be root so they
1632 // can be scheduled properly.
1633 Node* control = last->in(0);
1634 if (control != xroot) {
1635 if (control == NULL || control == C->root()) {
1636 last->set_req(0, xroot);
1637 } else {
1638 assert(false, "unexpected control");
1639 return NULL;
1640 }
1641 }
1642 return last;
1643 }
1644 return NULL;
1645 }
1646
1647
1648 //------------------------------ReduceInst-------------------------------------
1649 // Reduce a State tree (with given Control) into a tree of MachNodes.
1650 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1651 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1652 // Each MachNode has a number of complicated MachOper operands; each
1653 // MachOper also covers a further tree of Ideal Nodes.
1654
1655 // The root of the Ideal match tree is always an instruction, so we enter
1656 // the recursion here. After building the MachNode, we need to recurse
1657 // the tree checking for these cases:
1658 // (1) Child is an instruction -
1659 // Build the instruction (recursively), add it as an edge.
1660 // Build a simple operand (register) to hold the result of the instruction.
1661 // (2) Child is an interior part of an instruction -
1662 // Skip over it (do nothing)
1663 // (3) Child is the start of a operand -
1664 // Build the operand, place it inside the instruction
1665 // Call ReduceOper.
1666 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1667 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1668
1669 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1670 if (shared_node != NULL) {
1671 return shared_node;
1672 }
1673
1674 // Build the object to represent this state & prepare for recursive calls
1675 MachNode *mach = s->MachNodeGenerator(rule);
1676 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1677 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1678 Node *leaf = s->_leaf;
1679 // Check for instruction or instruction chain rule
1680 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1681 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1682 "duplicating node that's already been matched");
1683 // Instruction
1684 mach->add_req( leaf->in(0) ); // Set initial control
1685 // Reduce interior of complex instruction
1686 ReduceInst_Interior( s, rule, mem, mach, 1 );
1687 } else {
1688 // Instruction chain rules are data-dependent on their inputs
1689 mach->add_req(0); // Set initial control to none
1690 ReduceInst_Chain_Rule( s, rule, mem, mach );
1691 }
1692
1693 // If a Memory was used, insert a Memory edge
1694 if( mem != (Node*)1 ) {
1695 mach->ins_req(MemNode::Memory,mem);
1696 #ifdef ASSERT
1697 // Verify adr type after matching memory operation
1698 const MachOper* oper = mach->memory_operand();
1699 if (oper != NULL && oper != (MachOper*)-1) {
1700 // It has a unique memory operand. Find corresponding ideal mem node.
1701 Node* m = NULL;
1702 if (leaf->is_Mem()) {
1703 m = leaf;
1704 } else {
1705 m = _mem_node;
1706 assert(m != NULL && m->is_Mem(), "expecting memory node");
1707 }
1708 const Type* mach_at = mach->adr_type();
1709 // DecodeN node consumed by an address may have different type
1710 // then its input. Don't compare types for such case.
1711 if (m->adr_type() != mach_at &&
1712 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1713 m->in(MemNode::Address)->is_AddP() &&
1714 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1715 m->in(MemNode::Address)->is_AddP() &&
1716 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1717 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1718 mach_at = m->adr_type();
1719 }
1720 if (m->adr_type() != mach_at) {
1721 m->dump();
1722 tty->print_cr("mach:");
1723 mach->dump(1);
1724 }
1725 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1726 }
1727 #endif
1728 }
1729
1730 // If the _leaf is an AddP, insert the base edge
1731 if (leaf->is_AddP()) {
1732 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1733 }
1734
1735 uint number_of_projections_prior = number_of_projections();
1736
1737 // Perform any 1-to-many expansions required
1738 MachNode *ex = mach->Expand(s, _projection_list, mem);
1739 if (ex != mach) {
1740 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1741 if( ex->in(1)->is_Con() )
1742 ex->in(1)->set_req(0, C->root());
1743 // Remove old node from the graph
1744 for( uint i=0; i<mach->req(); i++ ) {
1745 mach->set_req(i,NULL);
1746 }
1747 #ifdef ASSERT
1748 _new2old_map.map(ex->_idx, s->_leaf);
1749 #endif
1750 }
1751
1752 // PhaseChaitin::fixup_spills will sometimes generate spill code
1753 // via the matcher. By the time, nodes have been wired into the CFG,
1754 // and any further nodes generated by expand rules will be left hanging
1755 // in space, and will not get emitted as output code. Catch this.
1756 // Also, catch any new register allocation constraints ("projections")
1757 // generated belatedly during spill code generation.
1758 if (_allocation_started) {
1759 guarantee(ex == mach, "no expand rules during spill generation");
1760 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1761 }
1762
1763 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1764 // Record the con for sharing
1765 _shared_nodes.map(leaf->_idx, ex);
1766 }
1767
1768 return ex;
1769 }
1770
1771 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1772 for (uint i = n->req(); i < n->len(); i++) {
1773 if (n->in(i) != NULL) {
1774 mach->add_prec(n->in(i));
1775 }
1776 }
1777 }
1778
1779 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1780 // 'op' is what I am expecting to receive
1781 int op = _leftOp[rule];
1782 // Operand type to catch childs result
1783 // This is what my child will give me.
1784 int opnd_class_instance = s->_rule[op];
1785 // Choose between operand class or not.
1786 // This is what I will receive.
1787 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1788 // New rule for child. Chase operand classes to get the actual rule.
1789 int newrule = s->_rule[catch_op];
1790
1791 if( newrule < NUM_OPERANDS ) {
1792 // Chain from operand or operand class, may be output of shared node
1793 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1794 "Bad AD file: Instruction chain rule must chain from operand");
1795 // Insert operand into array of operands for this instruction
1796 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1797
1798 ReduceOper( s, newrule, mem, mach );
1799 } else {
1800 // Chain from the result of an instruction
1801 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1802 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1803 Node *mem1 = (Node*)1;
1804 debug_only(Node *save_mem_node = _mem_node;)
1805 mach->add_req( ReduceInst(s, newrule, mem1) );
1806 debug_only(_mem_node = save_mem_node;)
1807 }
1808 return;
1809 }
1810
1811
1812 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1813 handle_precedence_edges(s->_leaf, mach);
1814
1815 if( s->_leaf->is_Load() ) {
1816 Node *mem2 = s->_leaf->in(MemNode::Memory);
1817 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1818 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1819 mem = mem2;
1820 }
1821 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1822 if( mach->in(0) == NULL )
1823 mach->set_req(0, s->_leaf->in(0));
1824 }
1825
1826 // Now recursively walk the state tree & add operand list.
1827 for( uint i=0; i<2; i++ ) { // binary tree
1828 State *newstate = s->_kids[i];
1829 if( newstate == NULL ) break; // Might only have 1 child
1830 // 'op' is what I am expecting to receive
1831 int op;
1832 if( i == 0 ) {
1833 op = _leftOp[rule];
1834 } else {
1835 op = _rightOp[rule];
1836 }
1837 // Operand type to catch childs result
1838 // This is what my child will give me.
1839 int opnd_class_instance = newstate->_rule[op];
1840 // Choose between operand class or not.
1841 // This is what I will receive.
1842 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1843 // New rule for child. Chase operand classes to get the actual rule.
1844 int newrule = newstate->_rule[catch_op];
1845
1846 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1847 // Operand/operandClass
1848 // Insert operand into array of operands for this instruction
1849 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1850 ReduceOper( newstate, newrule, mem, mach );
1851
1852 } else { // Child is internal operand or new instruction
1853 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1854 // internal operand --> call ReduceInst_Interior
1855 // Interior of complex instruction. Do nothing but recurse.
1856 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1857 } else {
1858 // instruction --> call build operand( ) to catch result
1859 // --> ReduceInst( newrule )
1860 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1861 Node *mem1 = (Node*)1;
1862 debug_only(Node *save_mem_node = _mem_node;)
1863 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1864 debug_only(_mem_node = save_mem_node;)
1865 }
1866 }
1867 assert( mach->_opnds[num_opnds-1], "" );
1868 }
1869 return num_opnds;
1870 }
1871
1872 // This routine walks the interior of possible complex operands.
1873 // At each point we check our children in the match tree:
1874 // (1) No children -
1875 // We are a leaf; add _leaf field as an input to the MachNode
1876 // (2) Child is an internal operand -
1877 // Skip over it ( do nothing )
1878 // (3) Child is an instruction -
1879 // Call ReduceInst recursively and
1880 // and instruction as an input to the MachNode
1881 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1882 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1883 State *kid = s->_kids[0];
1884 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1885
1886 // Leaf? And not subsumed?
1887 if( kid == NULL && !_swallowed[rule] ) {
1888 mach->add_req( s->_leaf ); // Add leaf pointer
1889 return; // Bail out
1890 }
1891
1892 if( s->_leaf->is_Load() ) {
1893 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1894 mem = s->_leaf->in(MemNode::Memory);
1895 debug_only(_mem_node = s->_leaf;)
1896 }
1897
1898 handle_precedence_edges(s->_leaf, mach);
1899
1900 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1901 if( !mach->in(0) )
1902 mach->set_req(0,s->_leaf->in(0));
1903 else {
1904 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1905 }
1906 }
1907
1908 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1909 int newrule;
1910 if( i == 0)
1911 newrule = kid->_rule[_leftOp[rule]];
1912 else
1913 newrule = kid->_rule[_rightOp[rule]];
1914
1915 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1916 // Internal operand; recurse but do nothing else
1917 ReduceOper( kid, newrule, mem, mach );
1918
1919 } else { // Child is a new instruction
1920 // Reduce the instruction, and add a direct pointer from this
1921 // machine instruction to the newly reduced one.
1922 Node *mem1 = (Node*)1;
1923 debug_only(Node *save_mem_node = _mem_node;)
1924 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1925 debug_only(_mem_node = save_mem_node;)
1926 }
1927 }
1928 }
1929
1930
1931 // -------------------------------------------------------------------------
1932 // Java-Java calling convention
1933 // (what you use when Java calls Java)
1934
1935 //------------------------------find_receiver----------------------------------
1936 // For a given signature, return the OptoReg for parameter 0.
1937 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1938 VMRegPair regs;
1939 BasicType sig_bt = T_OBJECT;
1940 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1941 // Return argument 0 register. In the LP64 build pointers
1942 // take 2 registers, but the VM wants only the 'main' name.
1943 return OptoReg::as_OptoReg(regs.first());
1944 }
1945
1946 // This function identifies sub-graphs in which a 'load' node is
1947 // input to two different nodes, and such that it can be matched
1948 // with BMI instructions like blsi, blsr, etc.
1949 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1950 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1951 // refers to the same node.
1952 #ifdef X86
1953 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1954 // This is a temporary solution until we make DAGs expressible in ADL.
1955 template<typename ConType>
1956 class FusedPatternMatcher {
1957 Node* _op1_node;
1958 Node* _mop_node;
1959 int _con_op;
1960
1961 static int match_next(Node* n, int next_op, int next_op_idx) {
1962 if (n->in(1) == NULL || n->in(2) == NULL) {
1963 return -1;
1964 }
1965
1966 if (next_op_idx == -1) { // n is commutative, try rotations
1967 if (n->in(1)->Opcode() == next_op) {
1968 return 1;
1969 } else if (n->in(2)->Opcode() == next_op) {
1970 return 2;
1971 }
1972 } else {
1973 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1974 if (n->in(next_op_idx)->Opcode() == next_op) {
1975 return next_op_idx;
1976 }
1977 }
1978 return -1;
1979 }
1980 public:
1981 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1982 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1983
1984 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1985 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1986 typename ConType::NativeType con_value) {
1987 if (_op1_node->Opcode() != op1) {
1988 return false;
1989 }
1990 if (_mop_node->outcnt() > 2) {
1991 return false;
1992 }
1993 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1994 if (op1_op2_idx == -1) {
1995 return false;
1996 }
1997 // Memory operation must be the other edge
1998 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1999
2000 // Check that the mop node is really what we want
2001 if (_op1_node->in(op1_mop_idx) == _mop_node) {
2002 Node *op2_node = _op1_node->in(op1_op2_idx);
2003 if (op2_node->outcnt() > 1) {
2004 return false;
2005 }
2006 assert(op2_node->Opcode() == op2, "Should be");
2007 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2008 if (op2_con_idx == -1) {
2009 return false;
2010 }
2011 // Memory operation must be the other edge
2012 int op2_mop_idx = (op2_con_idx & 1) + 1;
2013 // Check that the memory operation is the same node
2014 if (op2_node->in(op2_mop_idx) == _mop_node) {
2015 // Now check the constant
2016 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2017 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2018 return true;
2019 }
2020 }
2021 }
2022 return false;
2023 }
2024 };
2025
2026
2027 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2028 if (n != NULL && m != NULL) {
2029 if (m->Opcode() == Op_LoadI) {
2030 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2031 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2032 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2033 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2034 } else if (m->Opcode() == Op_LoadL) {
2035 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2036 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2037 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2038 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2039 }
2040 }
2041 return false;
2042 }
2043 #endif // X86
2044
2045 // A method-klass-holder may be passed in the inline_cache_reg
2046 // and then expanded into the inline_cache_reg and a method_oop register
2047 // defined in ad_<arch>.cpp
2048
2049 // Check for shift by small constant as well
2050 static bool clone_shift(Node* shift, Matcher* matcher, MStack& mstack, VectorSet& address_visited) {
2051 if (shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2052 shift->in(2)->get_int() <= 3 &&
2053 // Are there other uses besides address expressions?
2054 !matcher->is_visited(shift)) {
2055 address_visited.set(shift->_idx); // Flag as address_visited
2056 mstack.push(shift->in(2), Visit);
2057 Node *conv = shift->in(1);
2058 #ifdef _LP64
2059 // Allow Matcher to match the rule which bypass
2060 // ConvI2L operation for an array index on LP64
2061 // if the index value is positive.
2062 if (conv->Opcode() == Op_ConvI2L &&
2063 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2064 // Are there other uses besides address expressions?
2065 !matcher->is_visited(conv)) {
2066 address_visited.set(conv->_idx); // Flag as address_visited
2067 mstack.push(conv->in(1), Pre_Visit);
2068 } else
2069 #endif
2070 mstack.push(conv, Pre_Visit);
2071 return true;
2072 }
2073 return false;
2074 }
2075
2076
2077 //------------------------------find_shared------------------------------------
2078 // Set bits if Node is shared or otherwise a root
2079 void Matcher::find_shared( Node *n ) {
2080 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2081 MStack mstack(C->live_nodes() * 2);
2082 // Mark nodes as address_visited if they are inputs to an address expression
2083 VectorSet address_visited(Thread::current()->resource_area());
2084 mstack.push(n, Visit); // Don't need to pre-visit root node
2085 while (mstack.is_nonempty()) {
2086 n = mstack.node(); // Leave node on stack
2087 Node_State nstate = mstack.state();
2088 uint nop = n->Opcode();
2089 if (nstate == Pre_Visit) {
2090 if (address_visited.test(n->_idx)) { // Visited in address already?
2091 // Flag as visited and shared now.
2092 set_visited(n);
2093 }
2094 if (is_visited(n)) { // Visited already?
2095 // Node is shared and has no reason to clone. Flag it as shared.
2096 // This causes it to match into a register for the sharing.
2097 set_shared(n); // Flag as shared and
2098 mstack.pop(); // remove node from stack
2099 continue;
2100 }
2101 nstate = Visit; // Not already visited; so visit now
2102 }
2103 if (nstate == Visit) {
2104 mstack.set_state(Post_Visit);
2105 set_visited(n); // Flag as visited now
2106 bool mem_op = false;
2107
2108 switch( nop ) { // Handle some opcodes special
2109 case Op_Phi: // Treat Phis as shared roots
2110 case Op_Parm:
2111 case Op_Proj: // All handled specially during matching
2112 case Op_SafePointScalarObject:
2113 set_shared(n);
2114 set_dontcare(n);
2115 break;
2116 case Op_If:
2117 case Op_CountedLoopEnd:
2118 mstack.set_state(Alt_Post_Visit); // Alternative way
2119 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2120 // with matching cmp/branch in 1 instruction. The Matcher needs the
2121 // Bool and CmpX side-by-side, because it can only get at constants
2122 // that are at the leaves of Match trees, and the Bool's condition acts
2123 // as a constant here.
2124 mstack.push(n->in(1), Visit); // Clone the Bool
2125 mstack.push(n->in(0), Pre_Visit); // Visit control input
2126 continue; // while (mstack.is_nonempty())
2127 case Op_ConvI2D: // These forms efficiently match with a prior
2128 case Op_ConvI2F: // Load but not a following Store
2129 if( n->in(1)->is_Load() && // Prior load
2130 n->outcnt() == 1 && // Not already shared
2131 n->unique_out()->is_Store() ) // Following store
2132 set_shared(n); // Force it to be a root
2133 break;
2134 case Op_ReverseBytesI:
2135 case Op_ReverseBytesL:
2136 if( n->in(1)->is_Load() && // Prior load
2137 n->outcnt() == 1 ) // Not already shared
2138 set_shared(n); // Force it to be a root
2139 break;
2140 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2141 case Op_IfFalse:
2142 case Op_IfTrue:
2143 case Op_MachProj:
2144 case Op_MergeMem:
2145 case Op_Catch:
2146 case Op_CatchProj:
2147 case Op_CProj:
2148 case Op_JumpProj:
2149 case Op_JProj:
2150 case Op_NeverBranch:
2151 set_dontcare(n);
2152 break;
2153 case Op_Jump:
2154 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2155 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2156 continue; // while (mstack.is_nonempty())
2157 case Op_StrComp:
2158 case Op_StrEquals:
2159 case Op_StrIndexOf:
2160 case Op_AryEq:
2161 case Op_EncodeISOArray:
2162 set_shared(n); // Force result into register (it will be anyways)
2163 break;
2164 case Op_ConP: { // Convert pointers above the centerline to NUL
2165 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2166 const TypePtr* tp = tn->type()->is_ptr();
2167 if (tp->_ptr == TypePtr::AnyNull) {
2168 tn->set_type(TypePtr::NULL_PTR);
2169 }
2170 break;
2171 }
2172 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2173 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2174 const TypePtr* tp = tn->type()->make_ptr();
2175 if (tp && tp->_ptr == TypePtr::AnyNull) {
2176 tn->set_type(TypeNarrowOop::NULL_PTR);
2177 }
2178 break;
2179 }
2180 case Op_Binary: // These are introduced in the Post_Visit state.
2181 ShouldNotReachHere();
2182 break;
2183 case Op_ClearArray:
2184 case Op_SafePoint:
2185 mem_op = true;
2186 break;
2187 default:
2188 if( n->is_Store() ) {
2189 // Do match stores, despite no ideal reg
2190 mem_op = true;
2191 break;
2192 }
2193 if( n->is_Mem() ) { // Loads and LoadStores
2194 mem_op = true;
2195 // Loads must be root of match tree due to prior load conflict
2196 if( C->subsume_loads() == false )
2197 set_shared(n);
2198 }
2199 // Fall into default case
2200 if( !n->ideal_reg() )
2201 set_dontcare(n); // Unmatchable Nodes
2202 } // end_switch
2203
2204 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2205 Node *m = n->in(i); // Get ith input
2206 if (m == NULL) continue; // Ignore NULLs
2207 uint mop = m->Opcode();
2208
2209 // Must clone all producers of flags, or we will not match correctly.
2210 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2211 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2212 // are also there, so we may match a float-branch to int-flags and
2213 // expect the allocator to haul the flags from the int-side to the
2214 // fp-side. No can do.
2215 if( _must_clone[mop] ) {
2216 mstack.push(m, Visit);
2217 continue; // for(int i = ...)
2218 }
2219
2220 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2221 // Bases used in addresses must be shared but since
2222 // they are shared through a DecodeN they may appear
2223 // to have a single use so force sharing here.
2224 set_shared(m->in(AddPNode::Base)->in(1));
2225 }
2226
2227 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2228 #ifdef X86
2229 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2230 mstack.push(m, Visit);
2231 continue;
2232 }
2233 #endif
2234
2235 // Clone addressing expressions as they are "free" in memory access instructions
2236 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2237 // When there are other uses besides address expressions
2238 // put it on stack and mark as shared.
2239 !is_visited(m)) {
2240 // Some inputs for address expression are not put on stack
2241 // to avoid marking them as shared and forcing them into register
2242 // if they are used only in address expressions.
2243 // But they should be marked as shared if there are other uses
2244 // besides address expressions.
2245
2246 Node *off = m->in(AddPNode::Offset);
2247 if (off->is_Con()) {
2248 address_visited.test_set(m->_idx); // Flag as address_visited
2249 Node *adr = m->in(AddPNode::Address);
2250
2251 // Intel, ARM and friends can handle 2 adds in addressing mode
2252 if( clone_shift_expressions && adr->is_AddP() &&
2253 // AtomicAdd is not an addressing expression.
2254 // Cheap to find it by looking for screwy base.
2255 !adr->in(AddPNode::Base)->is_top() &&
2256 // Are there other uses besides address expressions?
2257 !is_visited(adr) ) {
2258 address_visited.set(adr->_idx); // Flag as address_visited
2259 Node *shift = adr->in(AddPNode::Offset);
2260 if (!clone_shift(shift, this, mstack, address_visited)) {
2261 mstack.push(shift, Pre_Visit);
2262 }
2263 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2264 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2265 } else { // Sparc, Alpha, PPC and friends
2266 mstack.push(adr, Pre_Visit);
2267 }
2268
2269 // Clone X+offset as it also folds into most addressing expressions
2270 mstack.push(off, Visit);
2271 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2272 continue; // for(int i = ...)
2273 } else if (clone_shift_expressions &&
2274 clone_shift(off, this, mstack, address_visited)) {
2275 address_visited.test_set(m->_idx); // Flag as address_visited
2276 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2277 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2278 continue;
2279 } // if( off->is_Con() )
2280 } // if( mem_op &&
2281 mstack.push(m, Pre_Visit);
2282 } // for(int i = ...)
2283 }
2284 else if (nstate == Alt_Post_Visit) {
2285 mstack.pop(); // Remove node from stack
2286 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2287 // shared and all users of the Bool need to move the Cmp in parallel.
2288 // This leaves both the Bool and the If pointing at the Cmp. To
2289 // prevent the Matcher from trying to Match the Cmp along both paths
2290 // BoolNode::match_edge always returns a zero.
2291
2292 // We reorder the Op_If in a pre-order manner, so we can visit without
2293 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2294 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2295 }
2296 else if (nstate == Post_Visit) {
2297 mstack.pop(); // Remove node from stack
2298
2299 // Now hack a few special opcodes
2300 switch( n->Opcode() ) { // Handle some opcodes special
2301 case Op_StorePConditional:
2302 case Op_StoreIConditional:
2303 case Op_StoreLConditional:
2304 case Op_CompareAndSwapI:
2305 case Op_CompareAndSwapL:
2306 case Op_CompareAndSwapP:
2307 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2308 Node *newval = n->in(MemNode::ValueIn );
2309 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2310 Node *pair = new BinaryNode( oldval, newval );
2311 n->set_req(MemNode::ValueIn,pair);
2312 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2313 break;
2314 }
2315 case Op_CMoveD: // Convert trinary to binary-tree
2316 case Op_CMoveF:
2317 case Op_CMoveI:
2318 case Op_CMoveL:
2319 case Op_CMoveN:
2320 case Op_CMoveP:
2321 case Op_CMoveVD: {
2322 // Restructure into a binary tree for Matching. It's possible that
2323 // we could move this code up next to the graph reshaping for IfNodes
2324 // or vice-versa, but I do not want to debug this for Ladybird.
2325 // 10/2/2000 CNC.
2326 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2327 n->set_req(1,pair1);
2328 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2329 n->set_req(2,pair2);
2330 n->del_req(3);
2331 break;
2332 }
2333 case Op_LoopLimit: {
2334 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2335 n->set_req(1,pair1);
2336 n->set_req(2,n->in(3));
2337 n->del_req(3);
2338 break;
2339 }
2340 case Op_StrEquals: {
2341 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2342 n->set_req(2,pair1);
2343 n->set_req(3,n->in(4));
2344 n->del_req(4);
2345 break;
2346 }
2347 case Op_StrComp:
2348 case Op_StrIndexOf: {
2349 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2350 n->set_req(2,pair1);
2351 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2352 n->set_req(3,pair2);
2353 n->del_req(5);
2354 n->del_req(4);
2355 break;
2356 }
2357 case Op_EncodeISOArray: {
2358 // Restructure into a binary tree for Matching.
2359 Node* pair = new BinaryNode(n->in(3), n->in(4));
2360 n->set_req(3, pair);
2361 n->del_req(4);
2362 break;
2363 }
2364 default:
2365 break;
2366 }
2367 }
2368 else {
2369 ShouldNotReachHere();
2370 }
2371 } // end of while (mstack.is_nonempty())
2372 }
2373
2374 #ifdef ASSERT
2375 // machine-independent root to machine-dependent root
2376 void Matcher::dump_old2new_map() {
2377 _old2new_map.dump();
2378 }
2379 #endif
2380
2381 //---------------------------collect_null_checks-------------------------------
2382 // Find null checks in the ideal graph; write a machine-specific node for
2383 // it. Used by later implicit-null-check handling. Actually collects
2384 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2385 // value being tested.
2386 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2387 Node *iff = proj->in(0);
2388 if( iff->Opcode() == Op_If ) {
2389 // During matching If's have Bool & Cmp side-by-side
2390 BoolNode *b = iff->in(1)->as_Bool();
2391 Node *cmp = iff->in(2);
2392 int opc = cmp->Opcode();
2393 if (opc != Op_CmpP && opc != Op_CmpN) return;
2394
2395 const Type* ct = cmp->in(2)->bottom_type();
2396 if (ct == TypePtr::NULL_PTR ||
2397 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2398
2399 bool push_it = false;
2400 if( proj->Opcode() == Op_IfTrue ) {
2401 extern int all_null_checks_found;
2402 all_null_checks_found++;
2403 if( b->_test._test == BoolTest::ne ) {
2404 push_it = true;
2405 }
2406 } else {
2407 assert( proj->Opcode() == Op_IfFalse, "" );
2408 if( b->_test._test == BoolTest::eq ) {
2409 push_it = true;
2410 }
2411 }
2412 if( push_it ) {
2413 _null_check_tests.push(proj);
2414 Node* val = cmp->in(1);
2415 #ifdef _LP64
2416 if (val->bottom_type()->isa_narrowoop() &&
2417 !Matcher::narrow_oop_use_complex_address()) {
2418 //
2419 // Look for DecodeN node which should be pinned to orig_proj.
2420 // On platforms (Sparc) which can not handle 2 adds
2421 // in addressing mode we have to keep a DecodeN node and
2422 // use it to do implicit NULL check in address.
2423 //
2424 // DecodeN node was pinned to non-null path (orig_proj) during
2425 // CastPP transformation in final_graph_reshaping_impl().
2426 //
2427 uint cnt = orig_proj->outcnt();
2428 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2429 Node* d = orig_proj->raw_out(i);
2430 if (d->is_DecodeN() && d->in(1) == val) {
2431 val = d;
2432 val->set_req(0, NULL); // Unpin now.
2433 // Mark this as special case to distinguish from
2434 // a regular case: CmpP(DecodeN, NULL).
2435 val = (Node*)(((intptr_t)val) | 1);
2436 break;
2437 }
2438 }
2439 }
2440 #endif
2441 _null_check_tests.push(val);
2442 }
2443 }
2444 }
2445 }
2446
2447 //---------------------------validate_null_checks------------------------------
2448 // Its possible that the value being NULL checked is not the root of a match
2449 // tree. If so, I cannot use the value in an implicit null check.
2450 void Matcher::validate_null_checks( ) {
2451 uint cnt = _null_check_tests.size();
2452 for( uint i=0; i < cnt; i+=2 ) {
2453 Node *test = _null_check_tests[i];
2454 Node *val = _null_check_tests[i+1];
2455 bool is_decoden = ((intptr_t)val) & 1;
2456 val = (Node*)(((intptr_t)val) & ~1);
2457 if (has_new_node(val)) {
2458 Node* new_val = new_node(val);
2459 if (is_decoden) {
2460 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2461 // Note: new_val may have a control edge if
2462 // the original ideal node DecodeN was matched before
2463 // it was unpinned in Matcher::collect_null_checks().
2464 // Unpin the mach node and mark it.
2465 new_val->set_req(0, NULL);
2466 new_val = (Node*)(((intptr_t)new_val) | 1);
2467 }
2468 // Is a match-tree root, so replace with the matched value
2469 _null_check_tests.map(i+1, new_val);
2470 } else {
2471 // Yank from candidate list
2472 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2473 _null_check_tests.map(i,_null_check_tests[--cnt]);
2474 _null_check_tests.pop();
2475 _null_check_tests.pop();
2476 i-=2;
2477 }
2478 }
2479 }
2480
2481 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2482 // atomic instruction acting as a store_load barrier without any
2483 // intervening volatile load, and thus we don't need a barrier here.
2484 // We retain the Node to act as a compiler ordering barrier.
2485 bool Matcher::post_store_load_barrier(const Node* vmb) {
2486 Compile* C = Compile::current();
2487 assert(vmb->is_MemBar(), "");
2488 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2489 const MemBarNode* membar = vmb->as_MemBar();
2490
2491 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2492 Node* ctrl = NULL;
2493 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2494 Node* p = membar->fast_out(i);
2495 assert(p->is_Proj(), "only projections here");
2496 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2497 !C->node_arena()->contains(p)) { // Unmatched old-space only
2498 ctrl = p;
2499 break;
2500 }
2501 }
2502 assert((ctrl != NULL), "missing control projection");
2503
2504 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2505 Node *x = ctrl->fast_out(j);
2506 int xop = x->Opcode();
2507
2508 // We don't need current barrier if we see another or a lock
2509 // before seeing volatile load.
2510 //
2511 // Op_Fastunlock previously appeared in the Op_* list below.
2512 // With the advent of 1-0 lock operations we're no longer guaranteed
2513 // that a monitor exit operation contains a serializing instruction.
2514
2515 if (xop == Op_MemBarVolatile ||
2516 xop == Op_CompareAndSwapL ||
2517 xop == Op_CompareAndSwapP ||
2518 xop == Op_CompareAndSwapN ||
2519 xop == Op_CompareAndSwapI) {
2520 return true;
2521 }
2522
2523 // Op_FastLock previously appeared in the Op_* list above.
2524 // With biased locking we're no longer guaranteed that a monitor
2525 // enter operation contains a serializing instruction.
2526 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2527 return true;
2528 }
2529
2530 if (x->is_MemBar()) {
2531 // We must retain this membar if there is an upcoming volatile
2532 // load, which will be followed by acquire membar.
2533 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2534 return false;
2535 } else {
2536 // For other kinds of barriers, check by pretending we
2537 // are them, and seeing if we can be removed.
2538 return post_store_load_barrier(x->as_MemBar());
2539 }
2540 }
2541
2542 // probably not necessary to check for these
2543 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2544 return false;
2545 }
2546 }
2547 return false;
2548 }
2549
2550 // Check whether node n is a branch to an uncommon trap that we could
2551 // optimize as test with very high branch costs in case of going to
2552 // the uncommon trap. The code must be able to be recompiled to use
2553 // a cheaper test.
2554 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2555 // Don't do it for natives, adapters, or runtime stubs
2556 Compile *C = Compile::current();
2557 if (!C->is_method_compilation()) return false;
2558
2559 assert(n->is_If(), "You should only call this on if nodes.");
2560 IfNode *ifn = n->as_If();
2561
2562 Node *ifFalse = NULL;
2563 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2564 if (ifn->fast_out(i)->is_IfFalse()) {
2565 ifFalse = ifn->fast_out(i);
2566 break;
2567 }
2568 }
2569 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2570
2571 Node *reg = ifFalse;
2572 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2573 // Alternatively use visited set? Seems too expensive.
2574 while (reg != NULL && cnt > 0) {
2575 CallNode *call = NULL;
2576 RegionNode *nxt_reg = NULL;
2577 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2578 Node *o = reg->fast_out(i);
2579 if (o->is_Call()) {
2580 call = o->as_Call();
2581 }
2582 if (o->is_Region()) {
2583 nxt_reg = o->as_Region();
2584 }
2585 }
2586
2587 if (call &&
2588 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2589 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2590 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2591 jint tr_con = trtype->is_int()->get_con();
2592 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2593 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2594 assert((int)reason < (int)BitsPerInt, "recode bit map");
2595
2596 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2597 && action != Deoptimization::Action_none) {
2598 // This uncommon trap is sure to recompile, eventually.
2599 // When that happens, C->too_many_traps will prevent
2600 // this transformation from happening again.
2601 return true;
2602 }
2603 }
2604 }
2605
2606 reg = nxt_reg;
2607 cnt--;
2608 }
2609
2610 return false;
2611 }
2612
2613 //=============================================================================
2614 //---------------------------State---------------------------------------------
2615 State::State(void) {
2616 #ifdef ASSERT
2617 _id = 0;
2618 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2619 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2620 //memset(_cost, -1, sizeof(_cost));
2621 //memset(_rule, -1, sizeof(_rule));
2622 #endif
2623 memset(_valid, 0, sizeof(_valid));
2624 }
2625
2626 #ifdef ASSERT
2627 State::~State() {
2628 _id = 99;
2629 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2630 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2631 memset(_cost, -3, sizeof(_cost));
2632 memset(_rule, -3, sizeof(_rule));
2633 }
2634 #endif
2635
2636 #ifndef PRODUCT
2637 //---------------------------dump----------------------------------------------
2638 void State::dump() {
2639 tty->print("\n");
2640 dump(0);
2641 }
2642
2643 void State::dump(int depth) {
2644 for( int j = 0; j < depth; j++ )
2645 tty->print(" ");
2646 tty->print("--N: ");
2647 _leaf->dump();
2648 uint i;
2649 for( i = 0; i < _LAST_MACH_OPER; i++ )
2650 // Check for valid entry
2651 if( valid(i) ) {
2652 for( int j = 0; j < depth; j++ )
2653 tty->print(" ");
2654 assert(_cost[i] != max_juint, "cost must be a valid value");
2655 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2656 tty->print_cr("%s %d %s",
2657 ruleName[i], _cost[i], ruleName[_rule[i]] );
2658 }
2659 tty->cr();
2660
2661 for( i=0; i<2; i++ )
2662 if( _kids[i] )
2663 _kids[i]->dump(depth+1);
2664 }
2665 #endif