1 //
2 // Copyright (c) 2011, 2015, Oracle and/or its affiliates. All rights reserved.
3 // Copyright 2012, 2015 SAP AG. All rights reserved.
4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 //
6 // This code is free software; you can redistribute it and/or modify it
7 // under the terms of the GNU General Public License version 2 only, as
8 // published by the Free Software Foundation.
9 //
10 // This code is distributed in the hope that it will be useful, but WITHOUT
11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 // version 2 for more details (a copy is included in the LICENSE file that
14 // accompanied this code).
15 //
16 // You should have received a copy of the GNU General Public License version
17 // 2 along with this work; if not, write to the Free Software Foundation,
18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 //
20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 // or visit www.oracle.com if you need additional information or have any
22 // questions.
23 //
24 //
25
26 //
27 // PPC64 Architecture Description File
28 //
29
30 //----------REGISTER DEFINITION BLOCK------------------------------------------
31 // This information is used by the matcher and the register allocator to
32 // describe individual registers and classes of registers within the target
33 // architecture.
34 register %{
35 //----------Architecture Description Register Definitions----------------------
36 // General Registers
37 // "reg_def" name (register save type, C convention save type,
38 // ideal register type, encoding);
39 //
40 // Register Save Types:
41 //
42 // NS = No-Save: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method, &
44 // that they do not need to be saved at call sites.
45 //
46 // SOC = Save-On-Call: The register allocator assumes that these registers
47 // can be used without saving upon entry to the method,
48 // but that they must be saved at call sites.
49 // These are called "volatiles" on ppc.
50 //
51 // SOE = Save-On-Entry: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, but they do not need to be saved at call
54 // sites.
55 // These are called "nonvolatiles" on ppc.
56 //
57 // AS = Always-Save: The register allocator assumes that these registers
58 // must be saved before using them upon entry to the
59 // method, & that they must be saved at call sites.
60 //
61 // Ideal Register Type is used to determine how to save & restore a
62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
64 //
65 // The encoding number is the actual bit-pattern placed into the opcodes.
66 //
67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
68 // Supplement Version 1.7 as of 2003-10-29.
69 //
70 // For each 64-bit register we must define two registers: the register
71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
72 // e.g. R3_H, which is needed by the allocator, but is not used
73 // for stores, loads, etc.
74
75 // ----------------------------
76 // Integer/Long Registers
77 // ----------------------------
78
79 // PPC64 has 32 64-bit integer registers.
80
81 // types: v = volatile, nv = non-volatile, s = system
82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs
83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP
85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() );
86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC
87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret
89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2
91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3
93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4
95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5
97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6
99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7
101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8
103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch
105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch
107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id
109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next());
110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv
111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv
113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv
115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv
117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv
119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv
121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv
123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv
125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv
127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv
129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv
131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv
133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv
135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv
137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv
139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv
141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv
143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv
145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
146
147
148 // ----------------------------
149 // Float/Double Registers
150 // ----------------------------
151
152 // Double Registers
153 // The rules of ADL require that double registers be defined in pairs.
154 // Each pair must be two 32-bit values, but not necessarily a pair of
155 // single float registers. In each pair, ADLC-assigned register numbers
156 // must be adjacent, with the lower number even. Finally, when the
157 // CPU stores such a register pair to memory, the word associated with
158 // the lower ADLC-assigned number must be stored to the lower address.
159
160 // PPC64 has 32 64-bit floating-point registers. Each can store a single
161 // or double precision floating-point value.
162
163 // types: v = volatile, nv = non-volatile, s = system
164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch
165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret
167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2
169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3
171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4
173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5
175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6
177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7
179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8
181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9
183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10
185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11
187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12
189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13
191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv
193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv
195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv
197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv
199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv
201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv
203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv
205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv
207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv
209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv
211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv
213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv
215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv
217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv
219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv
221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv
223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv
225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv
227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
228
229 // ----------------------------
230 // Special Registers
231 // ----------------------------
232
233 // Condition Codes Flag Registers
234
235 // PPC64 has 8 condition code "registers" which are all contained
236 // in the CR register.
237
238 // types: v = volatile, nv = non-volatile, s = system
239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v
240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v
241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv
242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv
243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv
244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v
245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v
246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v
247
248 // Special registers of PPC64
249
250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v
251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v
252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v
253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v
254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v
256
257
258 // ----------------------------
259 // Specify priority of register selection within phases of register
260 // allocation. Highest priority is first. A useful heuristic is to
261 // give registers a low priority when they are required by machine
262 // instructions, like EAX and EDX on I486, and choose no-save registers
263 // before save-on-call, & save-on-call before save-on-entry. Registers
264 // which participate in fixed calling sequences should come last.
265 // Registers which are used as pairs must fall on an even boundary.
266
267 // It's worth about 1% on SPEC geomean to get this right.
268
269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
271 // R3_num. Therefore, R3_num may not be (and in reality is not)
272 // the same as R3->encoding()! Furthermore, we cannot make any
273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
274 // Additionally, the function
275 // static enum RC rc_class(OptoReg::Name reg )
276 // maps a given <register>_num value to its chunk type (except for flags)
277 // and its current implementation relies on chunk0 and chunk1 having a
278 // size of 64 each.
279
280 // If you change this allocation class, please have a look at the
281 // default values for the parameters RoundRobinIntegerRegIntervalStart
282 // and RoundRobinFloatRegIntervalStart
283
284 alloc_class chunk0 (
285 // Chunk0 contains *all* 64 integer registers halves.
286
287 // "non-volatile" registers
288 R14, R14_H,
289 R15, R15_H,
290 R17, R17_H,
291 R18, R18_H,
292 R19, R19_H,
293 R20, R20_H,
294 R21, R21_H,
295 R22, R22_H,
296 R23, R23_H,
297 R24, R24_H,
298 R25, R25_H,
299 R26, R26_H,
300 R27, R27_H,
301 R28, R28_H,
302 R29, R29_H,
303 R30, R30_H,
304 R31, R31_H,
305
306 // scratch/special registers
307 R11, R11_H,
308 R12, R12_H,
309
310 // argument registers
311 R10, R10_H,
312 R9, R9_H,
313 R8, R8_H,
314 R7, R7_H,
315 R6, R6_H,
316 R5, R5_H,
317 R4, R4_H,
318 R3, R3_H,
319
320 // special registers, not available for allocation
321 R16, R16_H, // R16_thread
322 R13, R13_H, // system thread id
323 R2, R2_H, // may be used for TOC
324 R1, R1_H, // SP
325 R0, R0_H // R0 (scratch)
326 );
327
328 // If you change this allocation class, please have a look at the
329 // default values for the parameters RoundRobinIntegerRegIntervalStart
330 // and RoundRobinFloatRegIntervalStart
331
332 alloc_class chunk1 (
333 // Chunk1 contains *all* 64 floating-point registers halves.
334
335 // scratch register
336 F0, F0_H,
337
338 // argument registers
339 F13, F13_H,
340 F12, F12_H,
341 F11, F11_H,
342 F10, F10_H,
343 F9, F9_H,
344 F8, F8_H,
345 F7, F7_H,
346 F6, F6_H,
347 F5, F5_H,
348 F4, F4_H,
349 F3, F3_H,
350 F2, F2_H,
351 F1, F1_H,
352
353 // non-volatile registers
354 F14, F14_H,
355 F15, F15_H,
356 F16, F16_H,
357 F17, F17_H,
358 F18, F18_H,
359 F19, F19_H,
360 F20, F20_H,
361 F21, F21_H,
362 F22, F22_H,
363 F23, F23_H,
364 F24, F24_H,
365 F25, F25_H,
366 F26, F26_H,
367 F27, F27_H,
368 F28, F28_H,
369 F29, F29_H,
370 F30, F30_H,
371 F31, F31_H
372 );
373
374 alloc_class chunk2 (
375 // Chunk2 contains *all* 8 condition code registers.
376
377 CCR0,
378 CCR1,
379 CCR2,
380 CCR3,
381 CCR4,
382 CCR5,
383 CCR6,
384 CCR7
385 );
386
387 alloc_class chunk3 (
388 // special registers
389 // These registers are not allocated, but used for nodes generated by postalloc expand.
390 SR_XER,
391 SR_LR,
392 SR_CTR,
393 SR_VRSAVE,
394 SR_SPEFSCR,
395 SR_PPR
396 );
397
398 //-------Architecture Description Register Classes-----------------------
399
400 // Several register classes are automatically defined based upon
401 // information in this architecture description.
402
403 // 1) reg_class inline_cache_reg ( as defined in frame section )
404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section )
405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
407 //
408
409 // ----------------------------
410 // 32 Bit Register Classes
411 // ----------------------------
412
413 // We specify registers twice, once as read/write, and once read-only.
414 // We use the read-only registers for source operands. With this, we
415 // can include preset read only registers in this class, as a hard-coded
416 // '0'-register. (We used to simulate this on ppc.)
417
418 // 32 bit registers that can be read and written i.e. these registers
419 // can be dest (or src) of normal instructions.
420 reg_class bits32_reg_rw(
421 /*R0*/ // R0
422 /*R1*/ // SP
423 R2, // TOC
424 R3,
425 R4,
426 R5,
427 R6,
428 R7,
429 R8,
430 R9,
431 R10,
432 R11,
433 R12,
434 /*R13*/ // system thread id
435 R14,
436 R15,
437 /*R16*/ // R16_thread
438 R17,
439 R18,
440 R19,
441 R20,
442 R21,
443 R22,
444 R23,
445 R24,
446 R25,
447 R26,
448 R27,
449 R28,
450 /*R29,*/ // global TOC
451 R30,
452 R31
453 );
454
455 // 32 bit registers that can only be read i.e. these registers can
456 // only be src of all instructions.
457 reg_class bits32_reg_ro(
458 /*R0*/ // R0
459 /*R1*/ // SP
460 R2 // TOC
461 R3,
462 R4,
463 R5,
464 R6,
465 R7,
466 R8,
467 R9,
468 R10,
469 R11,
470 R12,
471 /*R13*/ // system thread id
472 R14,
473 R15,
474 /*R16*/ // R16_thread
475 R17,
476 R18,
477 R19,
478 R20,
479 R21,
480 R22,
481 R23,
482 R24,
483 R25,
484 R26,
485 R27,
486 R28,
487 /*R29,*/
488 R30,
489 R31
490 );
491
492 reg_class rscratch1_bits32_reg(R11);
493 reg_class rscratch2_bits32_reg(R12);
494 reg_class rarg1_bits32_reg(R3);
495 reg_class rarg2_bits32_reg(R4);
496 reg_class rarg3_bits32_reg(R5);
497 reg_class rarg4_bits32_reg(R6);
498
499 // ----------------------------
500 // 64 Bit Register Classes
501 // ----------------------------
502 // 64-bit build means 64-bit pointers means hi/lo pairs
503
504 reg_class rscratch1_bits64_reg(R11_H, R11);
505 reg_class rscratch2_bits64_reg(R12_H, R12);
506 reg_class rarg1_bits64_reg(R3_H, R3);
507 reg_class rarg2_bits64_reg(R4_H, R4);
508 reg_class rarg3_bits64_reg(R5_H, R5);
509 reg_class rarg4_bits64_reg(R6_H, R6);
510 // Thread register, 'written' by tlsLoadP, see there.
511 reg_class thread_bits64_reg(R16_H, R16);
512
513 reg_class r19_bits64_reg(R19_H, R19);
514
515 // 64 bit registers that can be read and written i.e. these registers
516 // can be dest (or src) of normal instructions.
517 reg_class bits64_reg_rw(
518 /*R0_H, R0*/ // R0
519 /*R1_H, R1*/ // SP
520 R2_H, R2, // TOC
521 R3_H, R3,
522 R4_H, R4,
523 R5_H, R5,
524 R6_H, R6,
525 R7_H, R7,
526 R8_H, R8,
527 R9_H, R9,
528 R10_H, R10,
529 R11_H, R11,
530 R12_H, R12,
531 /*R13_H, R13*/ // system thread id
532 R14_H, R14,
533 R15_H, R15,
534 /*R16_H, R16*/ // R16_thread
535 R17_H, R17,
536 R18_H, R18,
537 R19_H, R19,
538 R20_H, R20,
539 R21_H, R21,
540 R22_H, R22,
541 R23_H, R23,
542 R24_H, R24,
543 R25_H, R25,
544 R26_H, R26,
545 R27_H, R27,
546 R28_H, R28,
547 /*R29_H, R29,*/
548 R30_H, R30,
549 R31_H, R31
550 );
551
552 // 64 bit registers used excluding r2, r11 and r12
553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
554 // r2, r11 and r12 internally.
555 reg_class bits64_reg_leaf_call(
556 /*R0_H, R0*/ // R0
557 /*R1_H, R1*/ // SP
558 /*R2_H, R2*/ // TOC
559 R3_H, R3,
560 R4_H, R4,
561 R5_H, R5,
562 R6_H, R6,
563 R7_H, R7,
564 R8_H, R8,
565 R9_H, R9,
566 R10_H, R10,
567 /*R11_H, R11*/
568 /*R12_H, R12*/
569 /*R13_H, R13*/ // system thread id
570 R14_H, R14,
571 R15_H, R15,
572 /*R16_H, R16*/ // R16_thread
573 R17_H, R17,
574 R18_H, R18,
575 R19_H, R19,
576 R20_H, R20,
577 R21_H, R21,
578 R22_H, R22,
579 R23_H, R23,
580 R24_H, R24,
581 R25_H, R25,
582 R26_H, R26,
583 R27_H, R27,
584 R28_H, R28,
585 /*R29_H, R29,*/
586 R30_H, R30,
587 R31_H, R31
588 );
589
590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
591 // which uses r19 as inline cache internally and expanded LeafCall which uses
592 // r2, r11 and r12 internally.
593 reg_class bits64_constant_table_base(
594 /*R0_H, R0*/ // R0
595 /*R1_H, R1*/ // SP
596 /*R2_H, R2*/ // TOC
597 R3_H, R3,
598 R4_H, R4,
599 R5_H, R5,
600 R6_H, R6,
601 R7_H, R7,
602 R8_H, R8,
603 R9_H, R9,
604 R10_H, R10,
605 /*R11_H, R11*/
606 /*R12_H, R12*/
607 /*R13_H, R13*/ // system thread id
608 R14_H, R14,
609 R15_H, R15,
610 /*R16_H, R16*/ // R16_thread
611 R17_H, R17,
612 R18_H, R18,
613 /*R19_H, R19*/
614 R20_H, R20,
615 R21_H, R21,
616 R22_H, R22,
617 R23_H, R23,
618 R24_H, R24,
619 R25_H, R25,
620 R26_H, R26,
621 R27_H, R27,
622 R28_H, R28,
623 /*R29_H, R29,*/
624 R30_H, R30,
625 R31_H, R31
626 );
627
628 // 64 bit registers that can only be read i.e. these registers can
629 // only be src of all instructions.
630 reg_class bits64_reg_ro(
631 /*R0_H, R0*/ // R0
632 R1_H, R1,
633 R2_H, R2, // TOC
634 R3_H, R3,
635 R4_H, R4,
636 R5_H, R5,
637 R6_H, R6,
638 R7_H, R7,
639 R8_H, R8,
640 R9_H, R9,
641 R10_H, R10,
642 R11_H, R11,
643 R12_H, R12,
644 /*R13_H, R13*/ // system thread id
645 R14_H, R14,
646 R15_H, R15,
647 R16_H, R16, // R16_thread
648 R17_H, R17,
649 R18_H, R18,
650 R19_H, R19,
651 R20_H, R20,
652 R21_H, R21,
653 R22_H, R22,
654 R23_H, R23,
655 R24_H, R24,
656 R25_H, R25,
657 R26_H, R26,
658 R27_H, R27,
659 R28_H, R28,
660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
661 R30_H, R30,
662 R31_H, R31
663 );
664
665
666 // ----------------------------
667 // Special Class for Condition Code Flags Register
668
669 reg_class int_flags(
670 /*CCR0*/ // scratch
671 /*CCR1*/ // scratch
672 /*CCR2*/ // nv!
673 /*CCR3*/ // nv!
674 /*CCR4*/ // nv!
675 CCR5,
676 CCR6,
677 CCR7
678 );
679
680 reg_class int_flags_ro(
681 CCR0,
682 CCR1,
683 CCR2,
684 CCR3,
685 CCR4,
686 CCR5,
687 CCR6,
688 CCR7
689 );
690
691 reg_class int_flags_CR0(CCR0);
692 reg_class int_flags_CR1(CCR1);
693 reg_class int_flags_CR6(CCR6);
694 reg_class ctr_reg(SR_CTR);
695
696 // ----------------------------
697 // Float Register Classes
698 // ----------------------------
699
700 reg_class flt_reg(
701 /*F0*/ // scratch
702 F1,
703 F2,
704 F3,
705 F4,
706 F5,
707 F6,
708 F7,
709 F8,
710 F9,
711 F10,
712 F11,
713 F12,
714 F13,
715 F14, // nv!
716 F15, // nv!
717 F16, // nv!
718 F17, // nv!
719 F18, // nv!
720 F19, // nv!
721 F20, // nv!
722 F21, // nv!
723 F22, // nv!
724 F23, // nv!
725 F24, // nv!
726 F25, // nv!
727 F26, // nv!
728 F27, // nv!
729 F28, // nv!
730 F29, // nv!
731 F30, // nv!
732 F31 // nv!
733 );
734
735 // Double precision float registers have virtual `high halves' that
736 // are needed by the allocator.
737 reg_class dbl_reg(
738 /*F0, F0_H*/ // scratch
739 F1, F1_H,
740 F2, F2_H,
741 F3, F3_H,
742 F4, F4_H,
743 F5, F5_H,
744 F6, F6_H,
745 F7, F7_H,
746 F8, F8_H,
747 F9, F9_H,
748 F10, F10_H,
749 F11, F11_H,
750 F12, F12_H,
751 F13, F13_H,
752 F14, F14_H, // nv!
753 F15, F15_H, // nv!
754 F16, F16_H, // nv!
755 F17, F17_H, // nv!
756 F18, F18_H, // nv!
757 F19, F19_H, // nv!
758 F20, F20_H, // nv!
759 F21, F21_H, // nv!
760 F22, F22_H, // nv!
761 F23, F23_H, // nv!
762 F24, F24_H, // nv!
763 F25, F25_H, // nv!
764 F26, F26_H, // nv!
765 F27, F27_H, // nv!
766 F28, F28_H, // nv!
767 F29, F29_H, // nv!
768 F30, F30_H, // nv!
769 F31, F31_H // nv!
770 );
771
772 %}
773
774 //----------DEFINITION BLOCK---------------------------------------------------
775 // Define name --> value mappings to inform the ADLC of an integer valued name
776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
777 // Format:
778 // int_def <name> ( <int_value>, <expression>);
779 // Generated Code in ad_<arch>.hpp
780 // #define <name> (<expression>)
781 // // value == <int_value>
782 // Generated code in ad_<arch>.cpp adlc_verification()
783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
784 //
785 definitions %{
786 // The default cost (of an ALU instruction).
787 int_def DEFAULT_COST_LOW ( 30, 30);
788 int_def DEFAULT_COST ( 100, 100);
789 int_def HUGE_COST (1000000, 1000000);
790
791 // Memory refs
792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2);
793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3);
794
795 // Branches are even more expensive.
796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9);
797 int_def CALL_COST ( 1300, DEFAULT_COST * 13);
798 %}
799
800
801 //----------SOURCE BLOCK-------------------------------------------------------
802 // This is a block of C++ code which provides values, functions, and
803 // definitions necessary in the rest of the architecture description.
804 source_hpp %{
805 // Header information of the source block.
806 // Method declarations/definitions which are used outside
807 // the ad-scope can conveniently be defined here.
808 //
809 // To keep related declarations/definitions/uses close together,
810 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
811
812 // Returns true if Node n is followed by a MemBar node that
813 // will do an acquire. If so, this node must not do the acquire
814 // operation.
815 bool followed_by_acquire(const Node *n);
816 %}
817
818 source %{
819
820 // Optimize load-acquire.
821 //
822 // Check if acquire is unnecessary due to following operation that does
823 // acquire anyways.
824 // Walk the pattern:
825 //
826 // n: Load.acq
827 // |
828 // MemBarAcquire
829 // | |
830 // Proj(ctrl) Proj(mem)
831 // | |
832 // MemBarRelease/Volatile
833 //
834 bool followed_by_acquire(const Node *load) {
835 assert(load->is_Load(), "So far implemented only for loads.");
836
837 // Find MemBarAcquire.
838 const Node *mba = NULL;
839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
840 const Node *out = load->fast_out(i);
841 if (out->Opcode() == Op_MemBarAcquire) {
842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
843 mba = out;
844 break;
845 }
846 }
847 if (!mba) return false;
848
849 // Find following MemBar node.
850 //
851 // The following node must be reachable by control AND memory
852 // edge to assure no other operations are in between the two nodes.
853 //
854 // So first get the Proj node, mem_proj, to use it to iterate forward.
855 Node *mem_proj = NULL;
856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found
858 assert(mem_proj->is_Proj(), "only projections here");
859 ProjNode *proj = mem_proj->as_Proj();
860 if (proj->_con == TypeFunc::Memory &&
861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
862 break;
863 }
864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
865
866 // Search MemBar behind Proj. If there are other memory operations
867 // behind the Proj we lost.
868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
869 Node *x = mem_proj->fast_out(j);
870 // Proj might have an edge to a store or load node which precedes the membar.
871 if (x->is_Mem()) return false;
872
873 // On PPC64 release and volatile are implemented by an instruction
874 // that also has acquire semantics. I.e. there is no need for an
875 // acquire before these.
876 int xop = x->Opcode();
877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
878 // Make sure we're not missing Call/Phi/MergeMem by checking
879 // control edges. The control edge must directly lead back
880 // to the MemBarAcquire
881 Node *ctrl_proj = x->in(0);
882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
883 return true;
884 }
885 }
886 }
887
888 return false;
889 }
890
891 #define __ _masm.
892
893 // Tertiary op of a LoadP or StoreP encoding.
894 #define REGP_OP true
895
896 // ****************************************************************************
897
898 // REQUIRED FUNCTIONALITY
899
900 // !!!!! Special hack to get all type of calls to specify the byte offset
901 // from the start of the call to the point where the return address
902 // will point.
903
904 // PPC port: Removed use of lazy constant construct.
905
906 int MachCallStaticJavaNode::ret_addr_offset() {
907 // It's only a single branch-and-link instruction.
908 return 4;
909 }
910
911 int MachCallDynamicJavaNode::ret_addr_offset() {
912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
913 // postalloc expanded calls if we use inline caches and do not update method data.
914 if (UseInlineCaches)
915 return 4;
916
917 int vtable_index = this->_vtable_index;
918 if (vtable_index < 0) {
919 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
921 return 12;
922 } else {
923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
924 return 24;
925 }
926 }
927
928 int MachCallRuntimeNode::ret_addr_offset() {
929 #if defined(ABI_ELFv2)
930 return 28;
931 #else
932 return 40;
933 #endif
934 }
935
936 //=============================================================================
937
938 // condition code conversions
939
940 static int cc_to_boint(int cc) {
941 return Assembler::bcondCRbiIs0 | (cc & 8);
942 }
943
944 static int cc_to_inverse_boint(int cc) {
945 return Assembler::bcondCRbiIs0 | (8-(cc & 8));
946 }
947
948 static int cc_to_biint(int cc, int flags_reg) {
949 return (flags_reg << 2) | (cc & 3);
950 }
951
952 //=============================================================================
953
954 // Compute padding required for nodes which need alignment. The padding
955 // is the number of bytes (not instructions) which will be inserted before
956 // the instruction. The padding must match the size of a NOP instruction.
957
958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
959 return (3*4-current_offset)&31;
960 }
961
962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
963 return (2*4-current_offset)&31;
964 }
965
966 int string_indexOf_immNode::compute_padding(int current_offset) const {
967 return (3*4-current_offset)&31;
968 }
969
970 int string_indexOfNode::compute_padding(int current_offset) const {
971 return (1*4-current_offset)&31;
972 }
973
974 int string_compareNode::compute_padding(int current_offset) const {
975 return (4*4-current_offset)&31;
976 }
977
978 int string_equals_immNode::compute_padding(int current_offset) const {
979 if (opnd_array(3)->constant() < 16) return 0; // Don't insert nops for short version (loop completely unrolled).
980 return (2*4-current_offset)&31;
981 }
982
983 int string_equalsNode::compute_padding(int current_offset) const {
984 return (7*4-current_offset)&31;
985 }
986
987 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
988 return (2*4-current_offset)&31;
989 }
990
991 //=============================================================================
992
993 // Indicate if the safepoint node needs the polling page as an input.
994 bool SafePointNode::needs_polling_address_input() {
995 // The address is loaded from thread by a seperate node.
996 return true;
997 }
998
999 //=============================================================================
1000
1001 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1002 void emit_break(CodeBuffer &cbuf) {
1003 MacroAssembler _masm(&cbuf);
1004 __ illtrap();
1005 }
1006
1007 #ifndef PRODUCT
1008 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1009 st->print("BREAKPOINT");
1010 }
1011 #endif
1012
1013 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1014 emit_break(cbuf);
1015 }
1016
1017 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1018 return MachNode::size(ra_);
1019 }
1020
1021 //=============================================================================
1022
1023 void emit_nop(CodeBuffer &cbuf) {
1024 MacroAssembler _masm(&cbuf);
1025 __ nop();
1026 }
1027
1028 static inline void emit_long(CodeBuffer &cbuf, int value) {
1029 *((int*)(cbuf.insts_end())) = value;
1030 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1031 }
1032
1033 //=============================================================================
1034
1035 %} // interrupt source
1036
1037 source_hpp %{ // Header information of the source block.
1038
1039 //--------------------------------------------------------------
1040 //---< Used for optimization in Compile::Shorten_branches >---
1041 //--------------------------------------------------------------
1042
1043 const uint trampoline_stub_size = 6 * BytesPerInstWord;
1044
1045 class CallStubImpl {
1046
1047 public:
1048
1049 // Emit call stub, compiled java to interpreter.
1050 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1051
1052 // Size of call trampoline stub.
1053 // This doesn't need to be accurate to the byte, but it
1054 // must be larger than or equal to the real size of the stub.
1055 static uint size_call_trampoline() {
1056 return trampoline_stub_size;
1057 }
1058
1059 // number of relocations needed by a call trampoline stub
1060 static uint reloc_call_trampoline() {
1061 return 5;
1062 }
1063
1064 };
1065
1066 %} // end source_hpp
1067
1068 source %{
1069
1070 // Emit a trampoline stub for a call to a target which is too far away.
1071 //
1072 // code sequences:
1073 //
1074 // call-site:
1075 // branch-and-link to <destination> or <trampoline stub>
1076 //
1077 // Related trampoline stub for this call-site in the stub section:
1078 // load the call target from the constant pool
1079 // branch via CTR (LR/link still points to the call-site above)
1080
1081 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1082 // Start the stub.
1083 address stub = __ start_a_stub(Compile::MAX_stubs_size/2);
1084 if (stub == NULL) {
1085 ciEnv::current()->record_failure("CodeCache is full");
1086 return;
1087 }
1088
1089 // For java_to_interp stubs we use R11_scratch1 as scratch register
1090 // and in call trampoline stubs we use R12_scratch2. This way we
1091 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1092 Register reg_scratch = R12_scratch2;
1093
1094 // Create a trampoline stub relocation which relates this trampoline stub
1095 // with the call instruction at insts_call_instruction_offset in the
1096 // instructions code-section.
1097 __ relocate(trampoline_stub_Relocation::spec(__ code()->insts()->start() + insts_call_instruction_offset));
1098 const int stub_start_offset = __ offset();
1099
1100 // Now, create the trampoline stub's code:
1101 // - load the TOC
1102 // - load the call target from the constant pool
1103 // - call
1104 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1105 __ ld_largeoffset_unchecked(reg_scratch, destination_toc_offset, reg_scratch, false);
1106 __ mtctr(reg_scratch);
1107 __ bctr();
1108
1109 const address stub_start_addr = __ addr_at(stub_start_offset);
1110
1111 // FIXME: Assert that the trampoline stub can be identified and patched.
1112
1113 // Assert that the encoded destination_toc_offset can be identified and that it is correct.
1114 assert(destination_toc_offset == NativeCallTrampolineStub_at(stub_start_addr)->destination_toc_offset(),
1115 "encoded offset into the constant pool must match");
1116 // Trampoline_stub_size should be good.
1117 assert((uint)(__ offset() - stub_start_offset) <= trampoline_stub_size, "should be good size");
1118 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
1119
1120 // End the stub.
1121 __ end_a_stub();
1122 }
1123
1124 //=============================================================================
1125
1126 // Emit an inline branch-and-link call and a related trampoline stub.
1127 //
1128 // code sequences:
1129 //
1130 // call-site:
1131 // branch-and-link to <destination> or <trampoline stub>
1132 //
1133 // Related trampoline stub for this call-site in the stub section:
1134 // load the call target from the constant pool
1135 // branch via CTR (LR/link still points to the call-site above)
1136 //
1137
1138 typedef struct {
1139 int insts_call_instruction_offset;
1140 int ret_addr_offset;
1141 } EmitCallOffsets;
1142
1143 // Emit a branch-and-link instruction that branches to a trampoline.
1144 // - Remember the offset of the branch-and-link instruction.
1145 // - Add a relocation at the branch-and-link instruction.
1146 // - Emit a branch-and-link.
1147 // - Remember the return pc offset.
1148 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1149 EmitCallOffsets offsets = { -1, -1 };
1150 const int start_offset = __ offset();
1151 offsets.insts_call_instruction_offset = __ offset();
1152
1153 // No entry point given, use the current pc.
1154 if (entry_point == NULL) entry_point = __ pc();
1155
1156 if (!Compile::current()->in_scratch_emit_size()) {
1157 // Put the entry point as a constant into the constant pool.
1158 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
1159 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1160
1161 // Emit the trampoline stub which will be related to the branch-and-link below.
1162 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1163 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1164 __ relocate(rtype);
1165 }
1166
1167 // Note: At this point we do not have the address of the trampoline
1168 // stub, and the entry point might be too far away for bl, so __ pc()
1169 // serves as dummy and the bl will be patched later.
1170 __ bl((address) __ pc());
1171
1172 offsets.ret_addr_offset = __ offset() - start_offset;
1173
1174 return offsets;
1175 }
1176
1177 //=============================================================================
1178
1179 // Factory for creating loadConL* nodes for large/small constant pool.
1180
1181 static inline jlong replicate_immF(float con) {
1182 // Replicate float con 2 times and pack into vector.
1183 int val = *((int*)&con);
1184 jlong lval = val;
1185 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1186 return lval;
1187 }
1188
1189 //=============================================================================
1190
1191 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1192 int Compile::ConstantTable::calculate_table_base_offset() const {
1193 return 0; // absolute addressing, no offset
1194 }
1195
1196 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1197 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1198 iRegPdstOper *op_dst = new iRegPdstOper();
1199 MachNode *m1 = new loadToc_hiNode();
1200 MachNode *m2 = new loadToc_loNode();
1201
1202 m1->add_req(NULL);
1203 m2->add_req(NULL, m1);
1204 m1->_opnds[0] = op_dst;
1205 m2->_opnds[0] = op_dst;
1206 m2->_opnds[1] = op_dst;
1207 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1208 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1209 nodes->push(m1);
1210 nodes->push(m2);
1211 }
1212
1213 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1214 // Is postalloc expanded.
1215 ShouldNotReachHere();
1216 }
1217
1218 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1219 return 0;
1220 }
1221
1222 #ifndef PRODUCT
1223 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1224 st->print("-- \t// MachConstantBaseNode (empty encoding)");
1225 }
1226 #endif
1227
1228 //=============================================================================
1229
1230 #ifndef PRODUCT
1231 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1232 Compile* C = ra_->C;
1233 const long framesize = C->frame_slots() << LogBytesPerInt;
1234
1235 st->print("PROLOG\n\t");
1236 if (C->need_stack_bang(framesize)) {
1237 st->print("stack_overflow_check\n\t");
1238 }
1239
1240 if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1241 st->print("save return pc\n\t");
1242 st->print("push frame %ld\n\t", -framesize);
1243 }
1244 }
1245 #endif
1246
1247 // Macro used instead of the common __ to emulate the pipes of PPC.
1248 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1249 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1250 // still no scheduling of this code is possible, the micro scheduler is aware of the
1251 // code and can update its internal data. The following mechanism is used to achieve this:
1252 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1253 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1254 #if 0 // TODO: PPC port
1255 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1256 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1257 _masm.
1258 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1259 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1260 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \
1261 C->hb_scheduling()->_pdScheduling->advance_offset
1262 #else
1263 #define ___(op) if (UsePower6SchedulerPPC64) \
1264 Unimplemented(); \
1265 _masm.
1266 #define ___stop if (UsePower6SchedulerPPC64) \
1267 Unimplemented()
1268 #define ___advance if (UsePower6SchedulerPPC64) \
1269 Unimplemented()
1270 #endif
1271
1272 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1273 Compile* C = ra_->C;
1274 MacroAssembler _masm(&cbuf);
1275
1276 const long framesize = C->frame_size_in_bytes();
1277 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1278
1279 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1280
1281 const Register return_pc = R20; // Must match return_addr() in frame section.
1282 const Register callers_sp = R21;
1283 const Register push_frame_temp = R22;
1284 const Register toc_temp = R23;
1285 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1286
1287 if (method_is_frameless) {
1288 // Add nop at beginning of all frameless methods to prevent any
1289 // oop instructions from getting overwritten by make_not_entrant
1290 // (patching attempt would fail).
1291 ___(nop) nop();
1292 } else {
1293 // Get return pc.
1294 ___(mflr) mflr(return_pc);
1295 }
1296
1297 // Calls to C2R adapters often do not accept exceptional returns.
1298 // We require that their callers must bang for them. But be
1299 // careful, because some VM calls (such as call site linkage) can
1300 // use several kilobytes of stack. But the stack safety zone should
1301 // account for that. See bugs 4446381, 4468289, 4497237.
1302
1303 int bangsize = C->bang_size_in_bytes();
1304 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1305 if (C->need_stack_bang(bangsize) && UseStackBanging) {
1306 // Unfortunately we cannot use the function provided in
1307 // assembler.cpp as we have to emulate the pipes. So I had to
1308 // insert the code of generate_stack_overflow_check(), see
1309 // assembler.cpp for some illuminative comments.
1310 const int page_size = os::vm_page_size();
1311 int bang_end = StackShadowPages * page_size;
1312
1313 // This is how far the previous frame's stack banging extended.
1314 const int bang_end_safe = bang_end;
1315
1316 if (bangsize > page_size) {
1317 bang_end += bangsize;
1318 }
1319
1320 int bang_offset = bang_end_safe;
1321
1322 while (bang_offset <= bang_end) {
1323 // Need at least one stack bang at end of shadow zone.
1324
1325 // Again I had to copy code, this time from assembler_ppc.cpp,
1326 // bang_stack_with_offset - see there for comments.
1327
1328 // Stack grows down, caller passes positive offset.
1329 assert(bang_offset > 0, "must bang with positive offset");
1330
1331 long stdoffset = -bang_offset;
1332
1333 if (Assembler::is_simm(stdoffset, 16)) {
1334 // Signed 16 bit offset, a simple std is ok.
1335 if (UseLoadInstructionsForStackBangingPPC64) {
1336 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP);
1337 } else {
1338 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1339 }
1340 } else if (Assembler::is_simm(stdoffset, 31)) {
1341 // Use largeoffset calculations for addis & ld/std.
1342 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1343 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1344
1345 Register tmp = R11;
1346 ___(addis) addis(tmp, R1_SP, hi);
1347 if (UseLoadInstructionsForStackBangingPPC64) {
1348 ___(ld) ld(R0, lo, tmp);
1349 } else {
1350 ___(std) std(R0, lo, tmp);
1351 }
1352 } else {
1353 ShouldNotReachHere();
1354 }
1355
1356 bang_offset += page_size;
1357 }
1358 // R11 trashed
1359 } // C->need_stack_bang(framesize) && UseStackBanging
1360
1361 unsigned int bytes = (unsigned int)framesize;
1362 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1363 ciMethod *currMethod = C->method();
1364
1365 // Optimized version for most common case.
1366 if (UsePower6SchedulerPPC64 &&
1367 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1368 !(false /* ConstantsALot TODO: PPC port*/)) {
1369 ___(or) mr(callers_sp, R1_SP);
1370 ___(std) std(return_pc, _abi(lr), R1_SP);
1371 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1372 return;
1373 }
1374
1375 if (!method_is_frameless) {
1376 // Get callers sp.
1377 ___(or) mr(callers_sp, R1_SP);
1378
1379 // Push method's frame, modifies SP.
1380 assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1381 // The ABI is already accounted for in 'framesize' via the
1382 // 'out_preserve' area.
1383 Register tmp = push_frame_temp;
1384 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1385 if (Assembler::is_simm(-offset, 16)) {
1386 ___(stdu) stdu(R1_SP, -offset, R1_SP);
1387 } else {
1388 long x = -offset;
1389 // Had to insert load_const(tmp, -offset).
1390 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1391 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1392 ___(rldicr) sldi(tmp, tmp, 32);
1393 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16);
1394 ___(ori) ori( tmp, tmp, (x & 0x0000ffff));
1395
1396 ___(stdux) stdux(R1_SP, R1_SP, tmp);
1397 }
1398 }
1399 #if 0 // TODO: PPC port
1400 // For testing large constant pools, emit a lot of constants to constant pool.
1401 // "Randomize" const_size.
1402 if (ConstantsALot) {
1403 const int num_consts = const_size();
1404 for (int i = 0; i < num_consts; i++) {
1405 __ long_constant(0xB0B5B00BBABE);
1406 }
1407 }
1408 #endif
1409 if (!method_is_frameless) {
1410 // Save return pc.
1411 ___(std) std(return_pc, _abi(lr), callers_sp);
1412 }
1413 }
1414 #undef ___
1415 #undef ___stop
1416 #undef ___advance
1417
1418 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1419 // Variable size. determine dynamically.
1420 return MachNode::size(ra_);
1421 }
1422
1423 int MachPrologNode::reloc() const {
1424 // Return number of relocatable values contained in this instruction.
1425 return 1; // 1 reloc entry for load_const(toc).
1426 }
1427
1428 //=============================================================================
1429
1430 #ifndef PRODUCT
1431 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1432 Compile* C = ra_->C;
1433
1434 st->print("EPILOG\n\t");
1435 st->print("restore return pc\n\t");
1436 st->print("pop frame\n\t");
1437
1438 if (do_polling() && C->is_method_compilation()) {
1439 st->print("touch polling page\n\t");
1440 }
1441 }
1442 #endif
1443
1444 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1445 Compile* C = ra_->C;
1446 MacroAssembler _masm(&cbuf);
1447
1448 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1449 assert(framesize >= 0, "negative frame-size?");
1450
1451 const bool method_needs_polling = do_polling() && C->is_method_compilation();
1452 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/;
1453 const Register return_pc = R11;
1454 const Register polling_page = R12;
1455
1456 if (!method_is_frameless) {
1457 // Restore return pc relative to callers' sp.
1458 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1459 }
1460
1461 if (method_needs_polling) {
1462 if (LoadPollAddressFromThread) {
1463 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1464 Unimplemented();
1465 } else {
1466 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1467 }
1468 }
1469
1470 if (!method_is_frameless) {
1471 // Move return pc to LR.
1472 __ mtlr(return_pc);
1473 // Pop frame (fixed frame-size).
1474 __ addi(R1_SP, R1_SP, (int)framesize);
1475 }
1476
1477 if (method_needs_polling) {
1478 // We need to mark the code position where the load from the safepoint
1479 // polling page was emitted as relocInfo::poll_return_type here.
1480 __ relocate(relocInfo::poll_return_type);
1481 __ load_from_polling_page(polling_page);
1482 }
1483 }
1484
1485 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1486 // Variable size. Determine dynamically.
1487 return MachNode::size(ra_);
1488 }
1489
1490 int MachEpilogNode::reloc() const {
1491 // Return number of relocatable values contained in this instruction.
1492 return 1; // 1 for load_from_polling_page.
1493 }
1494
1495 const Pipeline * MachEpilogNode::pipeline() const {
1496 return MachNode::pipeline_class();
1497 }
1498
1499 // This method seems to be obsolete. It is declared in machnode.hpp
1500 // and defined in all *.ad files, but it is never called. Should we
1501 // get rid of it?
1502 int MachEpilogNode::safepoint_offset() const {
1503 assert(do_polling(), "no return for this epilog node");
1504 return 0;
1505 }
1506
1507 #if 0 // TODO: PPC port
1508 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1509 MacroAssembler _masm(&cbuf);
1510 if (LoadPollAddressFromThread) {
1511 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1512 } else {
1513 _masm.nop();
1514 }
1515 }
1516
1517 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1518 if (LoadPollAddressFromThread) {
1519 return 4;
1520 } else {
1521 return 4;
1522 }
1523 }
1524
1525 #ifndef PRODUCT
1526 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1527 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1528 }
1529 #endif
1530
1531 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1532 return RSCRATCH1_BITS64_REG_mask();
1533 }
1534 #endif // PPC port
1535
1536 // =============================================================================
1537
1538 // Figure out which register class each belongs in: rc_int, rc_float or
1539 // rc_stack.
1540 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1541
1542 static enum RC rc_class(OptoReg::Name reg) {
1543 // Return the register class for the given register. The given register
1544 // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1545 // enumeration in adGlobals_ppc.hpp.
1546
1547 if (reg == OptoReg::Bad) return rc_bad;
1548
1549 // We have 64 integer register halves, starting at index 0.
1550 if (reg < 64) return rc_int;
1551
1552 // We have 64 floating-point register halves, starting at index 64.
1553 if (reg < 64+64) return rc_float;
1554
1555 // Between float regs & stack are the flags regs.
1556 assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1557
1558 return rc_stack;
1559 }
1560
1561 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1562 bool do_print, Compile* C, outputStream *st) {
1563
1564 assert(opcode == Assembler::LD_OPCODE ||
1565 opcode == Assembler::STD_OPCODE ||
1566 opcode == Assembler::LWZ_OPCODE ||
1567 opcode == Assembler::STW_OPCODE ||
1568 opcode == Assembler::LFD_OPCODE ||
1569 opcode == Assembler::STFD_OPCODE ||
1570 opcode == Assembler::LFS_OPCODE ||
1571 opcode == Assembler::STFS_OPCODE,
1572 "opcode not supported");
1573
1574 if (cbuf) {
1575 int d =
1576 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1577 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1578 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1579 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1580 }
1581 #ifndef PRODUCT
1582 else if (do_print) {
1583 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1584 op_str,
1585 Matcher::regName[reg],
1586 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1587 }
1588 #endif
1589 return 4; // size
1590 }
1591
1592 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1593 Compile* C = ra_->C;
1594
1595 // Get registers to move.
1596 OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1597 OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1598 OptoReg::Name dst_hi = ra_->get_reg_second(this);
1599 OptoReg::Name dst_lo = ra_->get_reg_first(this);
1600
1601 enum RC src_hi_rc = rc_class(src_hi);
1602 enum RC src_lo_rc = rc_class(src_lo);
1603 enum RC dst_hi_rc = rc_class(dst_hi);
1604 enum RC dst_lo_rc = rc_class(dst_lo);
1605
1606 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1607 if (src_hi != OptoReg::Bad)
1608 assert((src_lo&1)==0 && src_lo+1==src_hi &&
1609 (dst_lo&1)==0 && dst_lo+1==dst_hi,
1610 "expected aligned-adjacent pairs");
1611 // Generate spill code!
1612 int size = 0;
1613
1614 if (src_lo == dst_lo && src_hi == dst_hi)
1615 return size; // Self copy, no move.
1616
1617 // --------------------------------------
1618 // Memory->Memory Spill. Use R0 to hold the value.
1619 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1620 int src_offset = ra_->reg2offset(src_lo);
1621 int dst_offset = ra_->reg2offset(dst_lo);
1622 if (src_hi != OptoReg::Bad) {
1623 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1624 "expected same type of move for high parts");
1625 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st);
1626 if (!cbuf && !do_size) st->print("\n\t");
1627 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1628 } else {
1629 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1630 if (!cbuf && !do_size) st->print("\n\t");
1631 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1632 }
1633 return size;
1634 }
1635
1636 // --------------------------------------
1637 // Check for float->int copy; requires a trip through memory.
1638 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1639 Unimplemented();
1640 }
1641
1642 // --------------------------------------
1643 // Check for integer reg-reg copy.
1644 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1645 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1646 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1647 size = (Rsrc != Rdst) ? 4 : 0;
1648
1649 if (cbuf) {
1650 MacroAssembler _masm(cbuf);
1651 if (size) {
1652 __ mr(Rdst, Rsrc);
1653 }
1654 }
1655 #ifndef PRODUCT
1656 else if (!do_size) {
1657 if (size) {
1658 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1659 } else {
1660 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1661 }
1662 }
1663 #endif
1664 return size;
1665 }
1666
1667 // Check for integer store.
1668 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1669 int dst_offset = ra_->reg2offset(dst_lo);
1670 if (src_hi != OptoReg::Bad) {
1671 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1672 "expected same type of move for high parts");
1673 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1674 } else {
1675 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1676 }
1677 return size;
1678 }
1679
1680 // Check for integer load.
1681 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1682 int src_offset = ra_->reg2offset(src_lo);
1683 if (src_hi != OptoReg::Bad) {
1684 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1685 "expected same type of move for high parts");
1686 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1687 } else {
1688 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1689 }
1690 return size;
1691 }
1692
1693 // Check for float reg-reg copy.
1694 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1695 if (cbuf) {
1696 MacroAssembler _masm(cbuf);
1697 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1698 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1699 __ fmr(Rdst, Rsrc);
1700 }
1701 #ifndef PRODUCT
1702 else if (!do_size) {
1703 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1704 }
1705 #endif
1706 return 4;
1707 }
1708
1709 // Check for float store.
1710 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1711 int dst_offset = ra_->reg2offset(dst_lo);
1712 if (src_hi != OptoReg::Bad) {
1713 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1714 "expected same type of move for high parts");
1715 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1716 } else {
1717 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1718 }
1719 return size;
1720 }
1721
1722 // Check for float load.
1723 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1724 int src_offset = ra_->reg2offset(src_lo);
1725 if (src_hi != OptoReg::Bad) {
1726 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1727 "expected same type of move for high parts");
1728 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1729 } else {
1730 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1731 }
1732 return size;
1733 }
1734
1735 // --------------------------------------------------------------------
1736 // Check for hi bits still needing moving. Only happens for misaligned
1737 // arguments to native calls.
1738 if (src_hi == dst_hi)
1739 return size; // Self copy; no move.
1740
1741 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1742 ShouldNotReachHere(); // Unimplemented
1743 return 0;
1744 }
1745
1746 #ifndef PRODUCT
1747 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1748 if (!ra_)
1749 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1750 else
1751 implementation(NULL, ra_, false, st);
1752 }
1753 #endif
1754
1755 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1756 implementation(&cbuf, ra_, false, NULL);
1757 }
1758
1759 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1760 return implementation(NULL, ra_, true, NULL);
1761 }
1762
1763 #if 0 // TODO: PPC port
1764 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1765 #ifndef PRODUCT
1766 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1767 #endif
1768 assert(ra_->node_regs_max_index() != 0, "");
1769
1770 // Get registers to move.
1771 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1772 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1773 OptoReg::Name dst_hi = ra_->get_reg_second(n);
1774 OptoReg::Name dst_lo = ra_->get_reg_first(n);
1775
1776 enum RC src_lo_rc = rc_class(src_lo);
1777 enum RC dst_lo_rc = rc_class(dst_lo);
1778
1779 if (src_lo == dst_lo && src_hi == dst_hi)
1780 return ppc64Opcode_none; // Self copy, no move.
1781
1782 // --------------------------------------
1783 // Memory->Memory Spill. Use R0 to hold the value.
1784 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1785 return ppc64Opcode_compound;
1786 }
1787
1788 // --------------------------------------
1789 // Check for float->int copy; requires a trip through memory.
1790 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1791 Unimplemented();
1792 }
1793
1794 // --------------------------------------
1795 // Check for integer reg-reg copy.
1796 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1797 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1798 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1799 if (Rsrc == Rdst) {
1800 return ppc64Opcode_none;
1801 } else {
1802 return ppc64Opcode_or;
1803 }
1804 }
1805
1806 // Check for integer store.
1807 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1808 if (src_hi != OptoReg::Bad) {
1809 return ppc64Opcode_std;
1810 } else {
1811 return ppc64Opcode_stw;
1812 }
1813 }
1814
1815 // Check for integer load.
1816 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1817 if (src_hi != OptoReg::Bad) {
1818 return ppc64Opcode_ld;
1819 } else {
1820 return ppc64Opcode_lwz;
1821 }
1822 }
1823
1824 // Check for float reg-reg copy.
1825 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1826 return ppc64Opcode_fmr;
1827 }
1828
1829 // Check for float store.
1830 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1831 if (src_hi != OptoReg::Bad) {
1832 return ppc64Opcode_stfd;
1833 } else {
1834 return ppc64Opcode_stfs;
1835 }
1836 }
1837
1838 // Check for float load.
1839 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1840 if (src_hi != OptoReg::Bad) {
1841 return ppc64Opcode_lfd;
1842 } else {
1843 return ppc64Opcode_lfs;
1844 }
1845 }
1846
1847 // --------------------------------------------------------------------
1848 // Check for hi bits still needing moving. Only happens for misaligned
1849 // arguments to native calls.
1850 if (src_hi == dst_hi) {
1851 return ppc64Opcode_none; // Self copy; no move.
1852 }
1853
1854 ShouldNotReachHere();
1855 return ppc64Opcode_undefined;
1856 }
1857 #endif // PPC port
1858
1859 #ifndef PRODUCT
1860 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1861 st->print("NOP \t// %d nops to pad for loops.", _count);
1862 }
1863 #endif
1864
1865 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1866 MacroAssembler _masm(&cbuf);
1867 // _count contains the number of nops needed for padding.
1868 for (int i = 0; i < _count; i++) {
1869 __ nop();
1870 }
1871 }
1872
1873 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1874 return _count * 4;
1875 }
1876
1877 #ifndef PRODUCT
1878 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1879 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1880 char reg_str[128];
1881 ra_->dump_register(this, reg_str);
1882 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset);
1883 }
1884 #endif
1885
1886 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1887 MacroAssembler _masm(&cbuf);
1888
1889 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1890 int reg = ra_->get_encode(this);
1891
1892 if (Assembler::is_simm(offset, 16)) {
1893 __ addi(as_Register(reg), R1, offset);
1894 } else {
1895 ShouldNotReachHere();
1896 }
1897 }
1898
1899 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1900 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1901 return 4;
1902 }
1903
1904 #ifndef PRODUCT
1905 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1906 st->print_cr("---- MachUEPNode ----");
1907 st->print_cr("...");
1908 }
1909 #endif
1910
1911 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1912 // This is the unverified entry point.
1913 MacroAssembler _masm(&cbuf);
1914
1915 // Inline_cache contains a klass.
1916 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
1917 Register receiver_klass = R12_scratch2; // tmp
1918
1919 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1920 assert(R11_scratch1 == R11, "need prologue scratch register");
1921
1922 // Check for NULL argument if we don't have implicit null checks.
1923 if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1924 if (TrapBasedNullChecks) {
1925 __ trap_null_check(R3_ARG1);
1926 } else {
1927 Label valid;
1928 __ cmpdi(CCR0, R3_ARG1, 0);
1929 __ bne_predict_taken(CCR0, valid);
1930 // We have a null argument, branch to ic_miss_stub.
1931 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1932 relocInfo::runtime_call_type);
1933 __ bind(valid);
1934 }
1935 }
1936 // Assume argument is not NULL, load klass from receiver.
1937 __ load_klass(receiver_klass, R3_ARG1);
1938
1939 if (TrapBasedICMissChecks) {
1940 __ trap_ic_miss_check(receiver_klass, ic_klass);
1941 } else {
1942 Label valid;
1943 __ cmpd(CCR0, receiver_klass, ic_klass);
1944 __ beq_predict_taken(CCR0, valid);
1945 // We have an unexpected klass, branch to ic_miss_stub.
1946 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1947 relocInfo::runtime_call_type);
1948 __ bind(valid);
1949 }
1950
1951 // Argument is valid and klass is as expected, continue.
1952 }
1953
1954 #if 0 // TODO: PPC port
1955 // Optimize UEP code on z (save a load_const() call in main path).
1956 int MachUEPNode::ep_offset() {
1957 return 0;
1958 }
1959 #endif
1960
1961 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1962 // Variable size. Determine dynamically.
1963 return MachNode::size(ra_);
1964 }
1965
1966 //=============================================================================
1967
1968 %} // interrupt source
1969
1970 source_hpp %{ // Header information of the source block.
1971
1972 class HandlerImpl {
1973
1974 public:
1975
1976 static int emit_exception_handler(CodeBuffer &cbuf);
1977 static int emit_deopt_handler(CodeBuffer& cbuf);
1978
1979 static uint size_exception_handler() {
1980 // The exception_handler is a b64_patchable.
1981 return MacroAssembler::b64_patchable_size;
1982 }
1983
1984 static uint size_deopt_handler() {
1985 // The deopt_handler is a bl64_patchable.
1986 return MacroAssembler::bl64_patchable_size;
1987 }
1988
1989 };
1990
1991 %} // end source_hpp
1992
1993 source %{
1994
1995 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1996 MacroAssembler _masm(&cbuf);
1997
1998 address base = __ start_a_stub(size_exception_handler());
1999 if (base == NULL) return 0; // CodeBuffer::expand failed
2000
2001 int offset = __ offset();
2002 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
2003 relocInfo::runtime_call_type);
2004 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
2005 __ end_a_stub();
2006
2007 return offset;
2008 }
2009
2010 // The deopt_handler is like the exception handler, but it calls to
2011 // the deoptimization blob instead of jumping to the exception blob.
2012 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
2013 MacroAssembler _masm(&cbuf);
2014
2015 address base = __ start_a_stub(size_deopt_handler());
2016 if (base == NULL) return 0; // CodeBuffer::expand failed
2017
2018 int offset = __ offset();
2019 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2020 relocInfo::runtime_call_type);
2021 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2022 __ end_a_stub();
2023
2024 return offset;
2025 }
2026
2027 //=============================================================================
2028
2029 // Use a frame slots bias for frameless methods if accessing the stack.
2030 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2031 if (as_Register(reg_enc) == R1_SP) {
2032 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2033 }
2034 return 0;
2035 }
2036
2037 const bool Matcher::match_rule_supported(int opcode) {
2038 if (!has_match_rule(opcode))
2039 return false;
2040
2041 switch (opcode) {
2042 case Op_SqrtD:
2043 return VM_Version::has_fsqrt();
2044 case Op_CountLeadingZerosI:
2045 case Op_CountLeadingZerosL:
2046 case Op_CountTrailingZerosI:
2047 case Op_CountTrailingZerosL:
2048 if (!UseCountLeadingZerosInstructionsPPC64)
2049 return false;
2050 break;
2051
2052 case Op_PopCountI:
2053 case Op_PopCountL:
2054 return (UsePopCountInstruction && VM_Version::has_popcntw());
2055
2056 case Op_StrComp:
2057 return SpecialStringCompareTo;
2058 case Op_StrEquals:
2059 return SpecialStringEquals;
2060 case Op_StrIndexOf:
2061 return SpecialStringIndexOf;
2062 }
2063
2064 return true; // Per default match rules are supported.
2065 }
2066
2067 const int Matcher::float_pressure(int default_pressure_threshold) {
2068 return default_pressure_threshold;
2069 }
2070
2071 int Matcher::regnum_to_fpu_offset(int regnum) {
2072 // No user for this method?
2073 Unimplemented();
2074 return 999;
2075 }
2076
2077 const bool Matcher::convL2FSupported(void) {
2078 // fcfids can do the conversion (>= Power7).
2079 // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2080 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2081 }
2082
2083 // Vector width in bytes.
2084 const int Matcher::vector_width_in_bytes(BasicType bt) {
2085 assert(MaxVectorSize == 8, "");
2086 return 8;
2087 }
2088
2089 // Vector ideal reg.
2090 const int Matcher::vector_ideal_reg(int size) {
2091 assert(MaxVectorSize == 8 && size == 8, "");
2092 return Op_RegL;
2093 }
2094
2095 const int Matcher::vector_shift_count_ideal_reg(int size) {
2096 fatal("vector shift is not supported");
2097 return Node::NotAMachineReg;
2098 }
2099
2100 // Limits on vector size (number of elements) loaded into vector.
2101 const int Matcher::max_vector_size(const BasicType bt) {
2102 assert(is_java_primitive(bt), "only primitive type vectors");
2103 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2104 }
2105
2106 const int Matcher::min_vector_size(const BasicType bt) {
2107 return max_vector_size(bt); // Same as max.
2108 }
2109
2110 // PPC doesn't support misaligned vectors store/load.
2111 const bool Matcher::misaligned_vectors_ok() {
2112 return false;
2113 }
2114
2115 // PPC AES support not yet implemented
2116 const bool Matcher::pass_original_key_for_aes() {
2117 return false;
2118 }
2119
2120 // RETURNS: whether this branch offset is short enough that a short
2121 // branch can be used.
2122 //
2123 // If the platform does not provide any short branch variants, then
2124 // this method should return `false' for offset 0.
2125 //
2126 // `Compile::Fill_buffer' will decide on basis of this information
2127 // whether to do the pass `Compile::Shorten_branches' at all.
2128 //
2129 // And `Compile::Shorten_branches' will decide on basis of this
2130 // information whether to replace particular branch sites by short
2131 // ones.
2132 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2133 // Is the offset within the range of a ppc64 pc relative branch?
2134 bool b;
2135
2136 const int safety_zone = 3 * BytesPerInstWord;
2137 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2138 29 - 16 + 1 + 2);
2139 return b;
2140 }
2141
2142 const bool Matcher::isSimpleConstant64(jlong value) {
2143 // Probably always true, even if a temp register is required.
2144 return true;
2145 }
2146 /* TODO: PPC port
2147 // Make a new machine dependent decode node (with its operands).
2148 MachTypeNode *Matcher::make_decode_node() {
2149 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2150 "This method is only implemented for unscaled cOops mode so far");
2151 MachTypeNode *decode = new decodeN_unscaledNode();
2152 decode->set_opnd_array(0, new iRegPdstOper());
2153 decode->set_opnd_array(1, new iRegNsrcOper());
2154 return decode;
2155 }
2156 */
2157 // Threshold size for cleararray.
2158 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2159
2160 // false => size gets scaled to BytesPerLong, ok.
2161 const bool Matcher::init_array_count_is_in_bytes = false;
2162
2163 // Use conditional move (CMOVL) on Power7.
2164 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2165
2166 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2167 // fsel doesn't accept a condition register as input, so this would be slightly different.
2168 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2169
2170 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2171 const bool Matcher::require_postalloc_expand = true;
2172
2173 // Should the Matcher clone shifts on addressing modes, expecting them to
2174 // be subsumed into complex addressing expressions or compute them into
2175 // registers? True for Intel but false for most RISCs.
2176 const bool Matcher::clone_shift_expressions = false;
2177
2178 // Do we need to mask the count passed to shift instructions or does
2179 // the cpu only look at the lower 5/6 bits anyway?
2180 // PowerPC requires masked shift counts.
2181 const bool Matcher::need_masked_shift_count = true;
2182
2183 // This affects two different things:
2184 // - how Decode nodes are matched
2185 // - how ImplicitNullCheck opportunities are recognized
2186 // If true, the matcher will try to remove all Decodes and match them
2187 // (as operands) into nodes. NullChecks are not prepared to deal with
2188 // Decodes by final_graph_reshaping().
2189 // If false, final_graph_reshaping() forces the decode behind the Cmp
2190 // for a NullCheck. The matcher matches the Decode node into a register.
2191 // Implicit_null_check optimization moves the Decode along with the
2192 // memory operation back up before the NullCheck.
2193 bool Matcher::narrow_oop_use_complex_address() {
2194 // TODO: PPC port if (MatchDecodeNodes) return true;
2195 return false;
2196 }
2197
2198 bool Matcher::narrow_klass_use_complex_address() {
2199 NOT_LP64(ShouldNotCallThis());
2200 assert(UseCompressedClassPointers, "only for compressed klass code");
2201 // TODO: PPC port if (MatchDecodeNodes) return true;
2202 return false;
2203 }
2204
2205 // Is it better to copy float constants, or load them directly from memory?
2206 // Intel can load a float constant from a direct address, requiring no
2207 // extra registers. Most RISCs will have to materialize an address into a
2208 // register first, so they would do better to copy the constant from stack.
2209 const bool Matcher::rematerialize_float_constants = false;
2210
2211 // If CPU can load and store mis-aligned doubles directly then no fixup is
2212 // needed. Else we split the double into 2 integer pieces and move it
2213 // piece-by-piece. Only happens when passing doubles into C code as the
2214 // Java calling convention forces doubles to be aligned.
2215 const bool Matcher::misaligned_doubles_ok = true;
2216
2217 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2218 Unimplemented();
2219 }
2220
2221 // Advertise here if the CPU requires explicit rounding operations
2222 // to implement the UseStrictFP mode.
2223 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2224
2225 // Do floats take an entire double register or just half?
2226 //
2227 // A float occupies a ppc64 double register. For the allocator, a
2228 // ppc64 double register appears as a pair of float registers.
2229 bool Matcher::float_in_double() { return true; }
2230
2231 // Do ints take an entire long register or just half?
2232 // The relevant question is how the int is callee-saved:
2233 // the whole long is written but de-opt'ing will have to extract
2234 // the relevant 32 bits.
2235 const bool Matcher::int_in_long = true;
2236
2237 // Constants for c2c and c calling conventions.
2238
2239 const MachRegisterNumbers iarg_reg[8] = {
2240 R3_num, R4_num, R5_num, R6_num,
2241 R7_num, R8_num, R9_num, R10_num
2242 };
2243
2244 const MachRegisterNumbers farg_reg[13] = {
2245 F1_num, F2_num, F3_num, F4_num,
2246 F5_num, F6_num, F7_num, F8_num,
2247 F9_num, F10_num, F11_num, F12_num,
2248 F13_num
2249 };
2250
2251 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2252
2253 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2254
2255 // Return whether or not this register is ever used as an argument. This
2256 // function is used on startup to build the trampoline stubs in generateOptoStub.
2257 // Registers not mentioned will be killed by the VM call in the trampoline, and
2258 // arguments in those registers not be available to the callee.
2259 bool Matcher::can_be_java_arg(int reg) {
2260 // We return true for all registers contained in iarg_reg[] and
2261 // farg_reg[] and their virtual halves.
2262 // We must include the virtual halves in order to get STDs and LDs
2263 // instead of STWs and LWs in the trampoline stubs.
2264
2265 if ( reg == R3_num || reg == R3_H_num
2266 || reg == R4_num || reg == R4_H_num
2267 || reg == R5_num || reg == R5_H_num
2268 || reg == R6_num || reg == R6_H_num
2269 || reg == R7_num || reg == R7_H_num
2270 || reg == R8_num || reg == R8_H_num
2271 || reg == R9_num || reg == R9_H_num
2272 || reg == R10_num || reg == R10_H_num)
2273 return true;
2274
2275 if ( reg == F1_num || reg == F1_H_num
2276 || reg == F2_num || reg == F2_H_num
2277 || reg == F3_num || reg == F3_H_num
2278 || reg == F4_num || reg == F4_H_num
2279 || reg == F5_num || reg == F5_H_num
2280 || reg == F6_num || reg == F6_H_num
2281 || reg == F7_num || reg == F7_H_num
2282 || reg == F8_num || reg == F8_H_num
2283 || reg == F9_num || reg == F9_H_num
2284 || reg == F10_num || reg == F10_H_num
2285 || reg == F11_num || reg == F11_H_num
2286 || reg == F12_num || reg == F12_H_num
2287 || reg == F13_num || reg == F13_H_num)
2288 return true;
2289
2290 return false;
2291 }
2292
2293 bool Matcher::is_spillable_arg(int reg) {
2294 return can_be_java_arg(reg);
2295 }
2296
2297 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2298 return false;
2299 }
2300
2301 // Register for DIVI projection of divmodI.
2302 RegMask Matcher::divI_proj_mask() {
2303 ShouldNotReachHere();
2304 return RegMask();
2305 }
2306
2307 // Register for MODI projection of divmodI.
2308 RegMask Matcher::modI_proj_mask() {
2309 ShouldNotReachHere();
2310 return RegMask();
2311 }
2312
2313 // Register for DIVL projection of divmodL.
2314 RegMask Matcher::divL_proj_mask() {
2315 ShouldNotReachHere();
2316 return RegMask();
2317 }
2318
2319 // Register for MODL projection of divmodL.
2320 RegMask Matcher::modL_proj_mask() {
2321 ShouldNotReachHere();
2322 return RegMask();
2323 }
2324
2325 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2326 return RegMask();
2327 }
2328
2329 %}
2330
2331 //----------ENCODING BLOCK-----------------------------------------------------
2332 // This block specifies the encoding classes used by the compiler to output
2333 // byte streams. Encoding classes are parameterized macros used by
2334 // Machine Instruction Nodes in order to generate the bit encoding of the
2335 // instruction. Operands specify their base encoding interface with the
2336 // interface keyword. There are currently supported four interfaces,
2337 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2338 // operand to generate a function which returns its register number when
2339 // queried. CONST_INTER causes an operand to generate a function which
2340 // returns the value of the constant when queried. MEMORY_INTER causes an
2341 // operand to generate four functions which return the Base Register, the
2342 // Index Register, the Scale Value, and the Offset Value of the operand when
2343 // queried. COND_INTER causes an operand to generate six functions which
2344 // return the encoding code (ie - encoding bits for the instruction)
2345 // associated with each basic boolean condition for a conditional instruction.
2346 //
2347 // Instructions specify two basic values for encoding. Again, a function
2348 // is available to check if the constant displacement is an oop. They use the
2349 // ins_encode keyword to specify their encoding classes (which must be
2350 // a sequence of enc_class names, and their parameters, specified in
2351 // the encoding block), and they use the
2352 // opcode keyword to specify, in order, their primary, secondary, and
2353 // tertiary opcode. Only the opcode sections which a particular instruction
2354 // needs for encoding need to be specified.
2355 encode %{
2356 enc_class enc_unimplemented %{
2357 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2358 MacroAssembler _masm(&cbuf);
2359 __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2360 %}
2361
2362 enc_class enc_untested %{
2363 #ifdef ASSERT
2364 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2365 MacroAssembler _masm(&cbuf);
2366 __ untested("Untested mach node encoding in AD file.");
2367 #else
2368 // TODO: PPC port $archOpcode(ppc64Opcode_none);
2369 #endif
2370 %}
2371
2372 enc_class enc_lbz(iRegIdst dst, memory mem) %{
2373 // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2374 MacroAssembler _masm(&cbuf);
2375 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2376 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2377 %}
2378
2379 // Load acquire.
2380 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2381 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2382 MacroAssembler _masm(&cbuf);
2383 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2384 __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2385 __ twi_0($dst$$Register);
2386 __ isync();
2387 %}
2388
2389 enc_class enc_lhz(iRegIdst dst, memory mem) %{
2390 // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2391
2392 MacroAssembler _masm(&cbuf);
2393 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2394 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2395 %}
2396
2397 // Load acquire.
2398 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2399 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2400
2401 MacroAssembler _masm(&cbuf);
2402 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2403 __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2404 __ twi_0($dst$$Register);
2405 __ isync();
2406 %}
2407
2408 enc_class enc_lwz(iRegIdst dst, memory mem) %{
2409 // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2410
2411 MacroAssembler _masm(&cbuf);
2412 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2413 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2414 %}
2415
2416 // Load acquire.
2417 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2418 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2419
2420 MacroAssembler _masm(&cbuf);
2421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2422 __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2423 __ twi_0($dst$$Register);
2424 __ isync();
2425 %}
2426
2427 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2428 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2429 MacroAssembler _masm(&cbuf);
2430 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2431 // Operand 'ds' requires 4-alignment.
2432 assert((Idisp & 0x3) == 0, "unaligned offset");
2433 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2434 %}
2435
2436 // Load acquire.
2437 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2438 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2439 MacroAssembler _masm(&cbuf);
2440 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2441 // Operand 'ds' requires 4-alignment.
2442 assert((Idisp & 0x3) == 0, "unaligned offset");
2443 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2444 __ twi_0($dst$$Register);
2445 __ isync();
2446 %}
2447
2448 enc_class enc_lfd(RegF dst, memory mem) %{
2449 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2450 MacroAssembler _masm(&cbuf);
2451 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2452 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2453 %}
2454
2455 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2456 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2457
2458 MacroAssembler _masm(&cbuf);
2459 int toc_offset = 0;
2460
2461 if (!ra_->C->in_scratch_emit_size()) {
2462 address const_toc_addr;
2463 // Create a non-oop constant, no relocation needed.
2464 // If it is an IC, it has a virtual_call_Relocation.
2465 const_toc_addr = __ long_constant((jlong)$src$$constant);
2466
2467 // Get the constant's TOC offset.
2468 toc_offset = __ offset_to_method_toc(const_toc_addr);
2469
2470 // Keep the current instruction offset in mind.
2471 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2472 }
2473
2474 __ ld($dst$$Register, toc_offset, $toc$$Register);
2475 %}
2476
2477 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2478 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2479
2480 MacroAssembler _masm(&cbuf);
2481
2482 if (!ra_->C->in_scratch_emit_size()) {
2483 address const_toc_addr;
2484 // Create a non-oop constant, no relocation needed.
2485 // If it is an IC, it has a virtual_call_Relocation.
2486 const_toc_addr = __ long_constant((jlong)$src$$constant);
2487
2488 // Get the constant's TOC offset.
2489 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2490 // Store the toc offset of the constant.
2491 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2492
2493 // Also keep the current instruction offset in mind.
2494 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2495 }
2496
2497 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2498 %}
2499
2500 %} // encode
2501
2502 source %{
2503
2504 typedef struct {
2505 loadConL_hiNode *_large_hi;
2506 loadConL_loNode *_large_lo;
2507 loadConLNode *_small;
2508 MachNode *_last;
2509 } loadConLNodesTuple;
2510
2511 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2512 OptoReg::Name reg_second, OptoReg::Name reg_first) {
2513 loadConLNodesTuple nodes;
2514
2515 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2516 if (large_constant_pool) {
2517 // Create new nodes.
2518 loadConL_hiNode *m1 = new loadConL_hiNode();
2519 loadConL_loNode *m2 = new loadConL_loNode();
2520
2521 // inputs for new nodes
2522 m1->add_req(NULL, toc);
2523 m2->add_req(NULL, m1);
2524
2525 // operands for new nodes
2526 m1->_opnds[0] = new iRegLdstOper(); // dst
2527 m1->_opnds[1] = immSrc; // src
2528 m1->_opnds[2] = new iRegPdstOper(); // toc
2529 m2->_opnds[0] = new iRegLdstOper(); // dst
2530 m2->_opnds[1] = immSrc; // src
2531 m2->_opnds[2] = new iRegLdstOper(); // base
2532
2533 // Initialize ins_attrib TOC fields.
2534 m1->_const_toc_offset = -1;
2535 m2->_const_toc_offset_hi_node = m1;
2536
2537 // Initialize ins_attrib instruction offset.
2538 m1->_cbuf_insts_offset = -1;
2539
2540 // register allocation for new nodes
2541 ra_->set_pair(m1->_idx, reg_second, reg_first);
2542 ra_->set_pair(m2->_idx, reg_second, reg_first);
2543
2544 // Create result.
2545 nodes._large_hi = m1;
2546 nodes._large_lo = m2;
2547 nodes._small = NULL;
2548 nodes._last = nodes._large_lo;
2549 assert(m2->bottom_type()->isa_long(), "must be long");
2550 } else {
2551 loadConLNode *m2 = new loadConLNode();
2552
2553 // inputs for new nodes
2554 m2->add_req(NULL, toc);
2555
2556 // operands for new nodes
2557 m2->_opnds[0] = new iRegLdstOper(); // dst
2558 m2->_opnds[1] = immSrc; // src
2559 m2->_opnds[2] = new iRegPdstOper(); // toc
2560
2561 // Initialize ins_attrib instruction offset.
2562 m2->_cbuf_insts_offset = -1;
2563
2564 // register allocation for new nodes
2565 ra_->set_pair(m2->_idx, reg_second, reg_first);
2566
2567 // Create result.
2568 nodes._large_hi = NULL;
2569 nodes._large_lo = NULL;
2570 nodes._small = m2;
2571 nodes._last = nodes._small;
2572 assert(m2->bottom_type()->isa_long(), "must be long");
2573 }
2574
2575 return nodes;
2576 }
2577
2578 %} // source
2579
2580 encode %{
2581 // Postalloc expand emitter for loading a long constant from the method's TOC.
2582 // Enc_class needed as consttanttablebase is not supported by postalloc
2583 // expand.
2584 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2585 // Create new nodes.
2586 loadConLNodesTuple loadConLNodes =
2587 loadConLNodesTuple_create(ra_, n_toc, op_src,
2588 ra_->get_reg_second(this), ra_->get_reg_first(this));
2589
2590 // Push new nodes.
2591 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2592 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
2593
2594 // some asserts
2595 assert(nodes->length() >= 1, "must have created at least 1 node");
2596 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2597 %}
2598
2599 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2600 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2601
2602 MacroAssembler _masm(&cbuf);
2603 int toc_offset = 0;
2604
2605 if (!ra_->C->in_scratch_emit_size()) {
2606 intptr_t val = $src$$constant;
2607 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2608 address const_toc_addr;
2609 if (constant_reloc == relocInfo::oop_type) {
2610 // Create an oop constant and a corresponding relocation.
2611 AddressLiteral a = __ allocate_oop_address((jobject)val);
2612 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2613 __ relocate(a.rspec());
2614 } else if (constant_reloc == relocInfo::metadata_type) {
2615 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2616 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2617 __ relocate(a.rspec());
2618 } else {
2619 // Create a non-oop constant, no relocation needed.
2620 const_toc_addr = __ long_constant((jlong)$src$$constant);
2621 }
2622
2623 // Get the constant's TOC offset.
2624 toc_offset = __ offset_to_method_toc(const_toc_addr);
2625 }
2626
2627 __ ld($dst$$Register, toc_offset, $toc$$Register);
2628 %}
2629
2630 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2631 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2632
2633 MacroAssembler _masm(&cbuf);
2634 if (!ra_->C->in_scratch_emit_size()) {
2635 intptr_t val = $src$$constant;
2636 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src
2637 address const_toc_addr;
2638 if (constant_reloc == relocInfo::oop_type) {
2639 // Create an oop constant and a corresponding relocation.
2640 AddressLiteral a = __ allocate_oop_address((jobject)val);
2641 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2642 __ relocate(a.rspec());
2643 } else if (constant_reloc == relocInfo::metadata_type) {
2644 AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2645 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2646 __ relocate(a.rspec());
2647 } else { // non-oop pointers, e.g. card mark base, heap top
2648 // Create a non-oop constant, no relocation needed.
2649 const_toc_addr = __ long_constant((jlong)$src$$constant);
2650 }
2651
2652 // Get the constant's TOC offset.
2653 const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2654 // Store the toc offset of the constant.
2655 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2656 }
2657
2658 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2659 %}
2660
2661 // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2662 // Enc_class needed as consttanttablebase is not supported by postalloc
2663 // expand.
2664 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2665 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2666 if (large_constant_pool) {
2667 // Create new nodes.
2668 loadConP_hiNode *m1 = new loadConP_hiNode();
2669 loadConP_loNode *m2 = new loadConP_loNode();
2670
2671 // inputs for new nodes
2672 m1->add_req(NULL, n_toc);
2673 m2->add_req(NULL, m1);
2674
2675 // operands for new nodes
2676 m1->_opnds[0] = new iRegPdstOper(); // dst
2677 m1->_opnds[1] = op_src; // src
2678 m1->_opnds[2] = new iRegPdstOper(); // toc
2679 m2->_opnds[0] = new iRegPdstOper(); // dst
2680 m2->_opnds[1] = op_src; // src
2681 m2->_opnds[2] = new iRegLdstOper(); // base
2682
2683 // Initialize ins_attrib TOC fields.
2684 m1->_const_toc_offset = -1;
2685 m2->_const_toc_offset_hi_node = m1;
2686
2687 // Register allocation for new nodes.
2688 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2689 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2690
2691 nodes->push(m1);
2692 nodes->push(m2);
2693 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2694 } else {
2695 loadConPNode *m2 = new loadConPNode();
2696
2697 // inputs for new nodes
2698 m2->add_req(NULL, n_toc);
2699
2700 // operands for new nodes
2701 m2->_opnds[0] = new iRegPdstOper(); // dst
2702 m2->_opnds[1] = op_src; // src
2703 m2->_opnds[2] = new iRegPdstOper(); // toc
2704
2705 // Register allocation for new nodes.
2706 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2707
2708 nodes->push(m2);
2709 assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2710 }
2711 %}
2712
2713 // Enc_class needed as consttanttablebase is not supported by postalloc
2714 // expand.
2715 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2716 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2717
2718 MachNode *m2;
2719 if (large_constant_pool) {
2720 m2 = new loadConFCompNode();
2721 } else {
2722 m2 = new loadConFNode();
2723 }
2724 // inputs for new nodes
2725 m2->add_req(NULL, n_toc);
2726
2727 // operands for new nodes
2728 m2->_opnds[0] = op_dst;
2729 m2->_opnds[1] = op_src;
2730 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2731
2732 // register allocation for new nodes
2733 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2734 nodes->push(m2);
2735 %}
2736
2737 // Enc_class needed as consttanttablebase is not supported by postalloc
2738 // expand.
2739 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2740 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2741
2742 MachNode *m2;
2743 if (large_constant_pool) {
2744 m2 = new loadConDCompNode();
2745 } else {
2746 m2 = new loadConDNode();
2747 }
2748 // inputs for new nodes
2749 m2->add_req(NULL, n_toc);
2750
2751 // operands for new nodes
2752 m2->_opnds[0] = op_dst;
2753 m2->_opnds[1] = op_src;
2754 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2755
2756 // register allocation for new nodes
2757 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2758 nodes->push(m2);
2759 %}
2760
2761 enc_class enc_stw(iRegIsrc src, memory mem) %{
2762 // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2763 MacroAssembler _masm(&cbuf);
2764 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2765 __ stw($src$$Register, Idisp, $mem$$base$$Register);
2766 %}
2767
2768 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2769 // TODO: PPC port $archOpcode(ppc64Opcode_std);
2770 MacroAssembler _masm(&cbuf);
2771 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2772 // Operand 'ds' requires 4-alignment.
2773 assert((Idisp & 0x3) == 0, "unaligned offset");
2774 __ std($src$$Register, Idisp, $mem$$base$$Register);
2775 %}
2776
2777 enc_class enc_stfs(RegF src, memory mem) %{
2778 // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2779 MacroAssembler _masm(&cbuf);
2780 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2781 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2782 %}
2783
2784 enc_class enc_stfd(RegF src, memory mem) %{
2785 // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2786 MacroAssembler _masm(&cbuf);
2787 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2788 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2789 %}
2790
2791 // Use release_store for card-marking to ensure that previous
2792 // oop-stores are visible before the card-mark change.
2793 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2794 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2795 // FIXME: Implement this as a cmove and use a fixed condition code
2796 // register which is written on every transition to compiled code,
2797 // e.g. in call-stub and when returning from runtime stubs.
2798 //
2799 // Proposed code sequence for the cmove implementation:
2800 //
2801 // Label skip_release;
2802 // __ beq(CCRfixed, skip_release);
2803 // __ release();
2804 // __ bind(skip_release);
2805 // __ stb(card mark);
2806
2807 MacroAssembler _masm(&cbuf);
2808 Label skip_storestore;
2809
2810 #if 0 // TODO: PPC port
2811 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2812 // StoreStore barrier conditionally.
2813 __ lwz(R0, 0, $releaseFieldAddr$$Register);
2814 __ cmpwi($crx$$CondRegister, R0, 0);
2815 __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2816 #endif
2817 __ li(R0, 0);
2818 __ membar(Assembler::StoreStore);
2819 #if 0 // TODO: PPC port
2820 __ bind(skip_storestore);
2821 #endif
2822
2823 // Do the store.
2824 if ($mem$$index == 0) {
2825 __ stb(R0, $mem$$disp, $mem$$base$$Register);
2826 } else {
2827 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2828 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2829 }
2830 %}
2831
2832 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2833
2834 if (VM_Version::has_isel()) {
2835 // use isel instruction with Power 7
2836 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2837 encodeP_subNode *n_sub_base = new encodeP_subNode();
2838 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2839 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2840
2841 n_compare->add_req(n_region, n_src);
2842 n_compare->_opnds[0] = op_crx;
2843 n_compare->_opnds[1] = op_src;
2844 n_compare->_opnds[2] = new immL16Oper(0);
2845
2846 n_sub_base->add_req(n_region, n_src);
2847 n_sub_base->_opnds[0] = op_dst;
2848 n_sub_base->_opnds[1] = op_src;
2849 n_sub_base->_bottom_type = _bottom_type;
2850
2851 n_shift->add_req(n_region, n_sub_base);
2852 n_shift->_opnds[0] = op_dst;
2853 n_shift->_opnds[1] = op_dst;
2854 n_shift->_bottom_type = _bottom_type;
2855
2856 n_cond_set->add_req(n_region, n_compare, n_shift);
2857 n_cond_set->_opnds[0] = op_dst;
2858 n_cond_set->_opnds[1] = op_crx;
2859 n_cond_set->_opnds[2] = op_dst;
2860 n_cond_set->_bottom_type = _bottom_type;
2861
2862 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2863 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2864 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2865 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2866
2867 nodes->push(n_compare);
2868 nodes->push(n_sub_base);
2869 nodes->push(n_shift);
2870 nodes->push(n_cond_set);
2871
2872 } else {
2873 // before Power 7
2874 moveRegNode *n_move = new moveRegNode();
2875 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node();
2876 encodeP_shiftNode *n_shift = new encodeP_shiftNode();
2877 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode();
2878
2879 n_move->add_req(n_region, n_src);
2880 n_move->_opnds[0] = op_dst;
2881 n_move->_opnds[1] = op_src;
2882 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2883
2884 n_compare->add_req(n_region, n_src);
2885 n_compare->add_prec(n_move);
2886
2887 n_compare->_opnds[0] = op_crx;
2888 n_compare->_opnds[1] = op_src;
2889 n_compare->_opnds[2] = new immL16Oper(0);
2890
2891 n_sub_base->add_req(n_region, n_compare, n_src);
2892 n_sub_base->_opnds[0] = op_dst;
2893 n_sub_base->_opnds[1] = op_crx;
2894 n_sub_base->_opnds[2] = op_src;
2895 n_sub_base->_bottom_type = _bottom_type;
2896
2897 n_shift->add_req(n_region, n_sub_base);
2898 n_shift->_opnds[0] = op_dst;
2899 n_shift->_opnds[1] = op_dst;
2900 n_shift->_bottom_type = _bottom_type;
2901
2902 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2903 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2904 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2905 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2906
2907 nodes->push(n_move);
2908 nodes->push(n_compare);
2909 nodes->push(n_sub_base);
2910 nodes->push(n_shift);
2911 }
2912
2913 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2914 %}
2915
2916 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2917
2918 encodeP_subNode *n1 = new encodeP_subNode();
2919 n1->add_req(n_region, n_src);
2920 n1->_opnds[0] = op_dst;
2921 n1->_opnds[1] = op_src;
2922 n1->_bottom_type = _bottom_type;
2923
2924 encodeP_shiftNode *n2 = new encodeP_shiftNode();
2925 n2->add_req(n_region, n1);
2926 n2->_opnds[0] = op_dst;
2927 n2->_opnds[1] = op_dst;
2928 n2->_bottom_type = _bottom_type;
2929 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2930 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2931
2932 nodes->push(n1);
2933 nodes->push(n2);
2934 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2935 %}
2936
2937 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2938 decodeN_shiftNode *n_shift = new decodeN_shiftNode();
2939 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
2940
2941 n_compare->add_req(n_region, n_src);
2942 n_compare->_opnds[0] = op_crx;
2943 n_compare->_opnds[1] = op_src;
2944 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2945
2946 n_shift->add_req(n_region, n_src);
2947 n_shift->_opnds[0] = op_dst;
2948 n_shift->_opnds[1] = op_src;
2949 n_shift->_bottom_type = _bottom_type;
2950
2951 if (VM_Version::has_isel()) {
2952 // use isel instruction with Power 7
2953
2954 decodeN_addNode *n_add_base = new decodeN_addNode();
2955 n_add_base->add_req(n_region, n_shift);
2956 n_add_base->_opnds[0] = op_dst;
2957 n_add_base->_opnds[1] = op_dst;
2958 n_add_base->_bottom_type = _bottom_type;
2959
2960 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2961 n_cond_set->add_req(n_region, n_compare, n_add_base);
2962 n_cond_set->_opnds[0] = op_dst;
2963 n_cond_set->_opnds[1] = op_crx;
2964 n_cond_set->_opnds[2] = op_dst;
2965 n_cond_set->_bottom_type = _bottom_type;
2966
2967 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2968 ra_->set_oop(n_cond_set, true);
2969
2970 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2971 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2972 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2973 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2974
2975 nodes->push(n_compare);
2976 nodes->push(n_shift);
2977 nodes->push(n_add_base);
2978 nodes->push(n_cond_set);
2979
2980 } else {
2981 // before Power 7
2982 cond_add_baseNode *n_add_base = new cond_add_baseNode();
2983
2984 n_add_base->add_req(n_region, n_compare, n_shift);
2985 n_add_base->_opnds[0] = op_dst;
2986 n_add_base->_opnds[1] = op_crx;
2987 n_add_base->_opnds[2] = op_dst;
2988 n_add_base->_bottom_type = _bottom_type;
2989
2990 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2991 ra_->set_oop(n_add_base, true);
2992
2993 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2994 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2995 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2996
2997 nodes->push(n_compare);
2998 nodes->push(n_shift);
2999 nodes->push(n_add_base);
3000 }
3001 %}
3002
3003 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3004 decodeN_shiftNode *n1 = new decodeN_shiftNode();
3005 n1->add_req(n_region, n_src);
3006 n1->_opnds[0] = op_dst;
3007 n1->_opnds[1] = op_src;
3008 n1->_bottom_type = _bottom_type;
3009
3010 decodeN_addNode *n2 = new decodeN_addNode();
3011 n2->add_req(n_region, n1);
3012 n2->_opnds[0] = op_dst;
3013 n2->_opnds[1] = op_dst;
3014 n2->_bottom_type = _bottom_type;
3015 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3016 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3017
3018 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3019 ra_->set_oop(n2, true);
3020
3021 nodes->push(n1);
3022 nodes->push(n2);
3023 %}
3024
3025 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3026 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3027
3028 MacroAssembler _masm(&cbuf);
3029 int cc = $cmp$$cmpcode;
3030 int flags_reg = $crx$$reg;
3031 Label done;
3032 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3033 // Branch if not (cmp crx).
3034 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3035 __ mr($dst$$Register, $src$$Register);
3036 // TODO PPC port __ endgroup_if_needed(_size == 12);
3037 __ bind(done);
3038 %}
3039
3040 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3041 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3042
3043 MacroAssembler _masm(&cbuf);
3044 Label done;
3045 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3046 // Branch if not (cmp crx).
3047 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3048 __ li($dst$$Register, $src$$constant);
3049 // TODO PPC port __ endgroup_if_needed(_size == 12);
3050 __ bind(done);
3051 %}
3052
3053 // New atomics.
3054 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3055 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3056
3057 MacroAssembler _masm(&cbuf);
3058 Register Rtmp = R0;
3059 Register Rres = $res$$Register;
3060 Register Rsrc = $src$$Register;
3061 Register Rptr = $mem_ptr$$Register;
3062 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3063 Register Rold = RegCollision ? Rtmp : Rres;
3064
3065 Label Lretry;
3066 __ bind(Lretry);
3067 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3068 __ add(Rtmp, Rsrc, Rold);
3069 __ stwcx_(Rtmp, Rptr);
3070 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3071 __ bne_predict_not_taken(CCR0, Lretry);
3072 } else {
3073 __ bne( CCR0, Lretry);
3074 }
3075 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3076 __ fence();
3077 %}
3078
3079 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3080 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3081
3082 MacroAssembler _masm(&cbuf);
3083 Register Rtmp = R0;
3084 Register Rres = $res$$Register;
3085 Register Rsrc = $src$$Register;
3086 Register Rptr = $mem_ptr$$Register;
3087 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3088 Register Rold = RegCollision ? Rtmp : Rres;
3089
3090 Label Lretry;
3091 __ bind(Lretry);
3092 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3093 __ add(Rtmp, Rsrc, Rold);
3094 __ stdcx_(Rtmp, Rptr);
3095 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3096 __ bne_predict_not_taken(CCR0, Lretry);
3097 } else {
3098 __ bne( CCR0, Lretry);
3099 }
3100 if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3101 __ fence();
3102 %}
3103
3104 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3105 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3106
3107 MacroAssembler _masm(&cbuf);
3108 Register Rtmp = R0;
3109 Register Rres = $res$$Register;
3110 Register Rsrc = $src$$Register;
3111 Register Rptr = $mem_ptr$$Register;
3112 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3113 Register Rold = RegCollision ? Rtmp : Rres;
3114
3115 Label Lretry;
3116 __ bind(Lretry);
3117 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3118 __ stwcx_(Rsrc, Rptr);
3119 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3120 __ bne_predict_not_taken(CCR0, Lretry);
3121 } else {
3122 __ bne( CCR0, Lretry);
3123 }
3124 if (RegCollision) __ mr(Rres, Rtmp);
3125 __ fence();
3126 %}
3127
3128 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3129 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3130
3131 MacroAssembler _masm(&cbuf);
3132 Register Rtmp = R0;
3133 Register Rres = $res$$Register;
3134 Register Rsrc = $src$$Register;
3135 Register Rptr = $mem_ptr$$Register;
3136 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3137 Register Rold = RegCollision ? Rtmp : Rres;
3138
3139 Label Lretry;
3140 __ bind(Lretry);
3141 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3142 __ stdcx_(Rsrc, Rptr);
3143 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3144 __ bne_predict_not_taken(CCR0, Lretry);
3145 } else {
3146 __ bne( CCR0, Lretry);
3147 }
3148 if (RegCollision) __ mr(Rres, Rtmp);
3149 __ fence();
3150 %}
3151
3152 // This enc_class is needed so that scheduler gets proper
3153 // input mapping for latency computation.
3154 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3155 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3156 MacroAssembler _masm(&cbuf);
3157 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3158 %}
3159
3160 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3161 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3162
3163 MacroAssembler _masm(&cbuf);
3164
3165 Label done;
3166 __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3167 __ li($dst$$Register, $zero$$constant);
3168 __ beq($crx$$CondRegister, done);
3169 __ li($dst$$Register, $notzero$$constant);
3170 __ bind(done);
3171 %}
3172
3173 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3174 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3175
3176 MacroAssembler _masm(&cbuf);
3177
3178 Label done;
3179 __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3180 __ li($dst$$Register, $zero$$constant);
3181 __ beq($crx$$CondRegister, done);
3182 __ li($dst$$Register, $notzero$$constant);
3183 __ bind(done);
3184 %}
3185
3186 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3187 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3188
3189 MacroAssembler _masm(&cbuf);
3190 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3191 Label done;
3192 __ bso($crx$$CondRegister, done);
3193 __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3194 // TODO PPC port __ endgroup_if_needed(_size == 12);
3195 __ bind(done);
3196 %}
3197
3198 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3199 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3200
3201 MacroAssembler _masm(&cbuf);
3202 Label d; // dummy
3203 __ bind(d);
3204 Label* p = ($lbl$$label);
3205 // `p' is `NULL' when this encoding class is used only to
3206 // determine the size of the encoded instruction.
3207 Label& l = (NULL == p)? d : *(p);
3208 int cc = $cmp$$cmpcode;
3209 int flags_reg = $crx$$reg;
3210 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3211 int bhint = Assembler::bhintNoHint;
3212
3213 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3214 if (_prob <= PROB_NEVER) {
3215 bhint = Assembler::bhintIsNotTaken;
3216 } else if (_prob >= PROB_ALWAYS) {
3217 bhint = Assembler::bhintIsTaken;
3218 }
3219 }
3220
3221 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3222 cc_to_biint(cc, flags_reg),
3223 l);
3224 %}
3225
3226 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3227 // The scheduler doesn't know about branch shortening, so we set the opcode
3228 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3229 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3230
3231 MacroAssembler _masm(&cbuf);
3232 Label d; // dummy
3233 __ bind(d);
3234 Label* p = ($lbl$$label);
3235 // `p' is `NULL' when this encoding class is used only to
3236 // determine the size of the encoded instruction.
3237 Label& l = (NULL == p)? d : *(p);
3238 int cc = $cmp$$cmpcode;
3239 int flags_reg = $crx$$reg;
3240 int bhint = Assembler::bhintNoHint;
3241
3242 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3243 if (_prob <= PROB_NEVER) {
3244 bhint = Assembler::bhintIsNotTaken;
3245 } else if (_prob >= PROB_ALWAYS) {
3246 bhint = Assembler::bhintIsTaken;
3247 }
3248 }
3249
3250 // Tell the conditional far branch to optimize itself when being relocated.
3251 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3252 cc_to_biint(cc, flags_reg),
3253 l,
3254 MacroAssembler::bc_far_optimize_on_relocate);
3255 %}
3256
3257 // Branch used with Power6 scheduling (can be shortened without changing the node).
3258 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3259 // The scheduler doesn't know about branch shortening, so we set the opcode
3260 // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3261 // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3262
3263 MacroAssembler _masm(&cbuf);
3264 Label d; // dummy
3265 __ bind(d);
3266 Label* p = ($lbl$$label);
3267 // `p' is `NULL' when this encoding class is used only to
3268 // determine the size of the encoded instruction.
3269 Label& l = (NULL == p)? d : *(p);
3270 int cc = $cmp$$cmpcode;
3271 int flags_reg = $crx$$reg;
3272 int bhint = Assembler::bhintNoHint;
3273
3274 if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3275 if (_prob <= PROB_NEVER) {
3276 bhint = Assembler::bhintIsNotTaken;
3277 } else if (_prob >= PROB_ALWAYS) {
3278 bhint = Assembler::bhintIsTaken;
3279 }
3280 }
3281
3282 #if 0 // TODO: PPC port
3283 if (_size == 8) {
3284 // Tell the conditional far branch to optimize itself when being relocated.
3285 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3286 cc_to_biint(cc, flags_reg),
3287 l,
3288 MacroAssembler::bc_far_optimize_on_relocate);
3289 } else {
3290 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3291 cc_to_biint(cc, flags_reg),
3292 l);
3293 }
3294 #endif
3295 Unimplemented();
3296 %}
3297
3298 // Postalloc expand emitter for loading a replicatef float constant from
3299 // the method's TOC.
3300 // Enc_class needed as consttanttablebase is not supported by postalloc
3301 // expand.
3302 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3303 // Create new nodes.
3304
3305 // Make an operand with the bit pattern to load as float.
3306 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3307
3308 loadConLNodesTuple loadConLNodes =
3309 loadConLNodesTuple_create(ra_, n_toc, op_repl,
3310 ra_->get_reg_second(this), ra_->get_reg_first(this));
3311
3312 // Push new nodes.
3313 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3314 if (loadConLNodes._last) nodes->push(loadConLNodes._last);
3315
3316 assert(nodes->length() >= 1, "must have created at least 1 node");
3317 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3318 %}
3319
3320 // This enc_class is needed so that scheduler gets proper
3321 // input mapping for latency computation.
3322 enc_class enc_poll(immI dst, iRegLdst poll) %{
3323 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3324 // Fake operand dst needed for PPC scheduler.
3325 assert($dst$$constant == 0x0, "dst must be 0x0");
3326
3327 MacroAssembler _masm(&cbuf);
3328 // Mark the code position where the load from the safepoint
3329 // polling page was emitted as relocInfo::poll_type.
3330 __ relocate(relocInfo::poll_type);
3331 __ load_from_polling_page($poll$$Register);
3332 %}
3333
3334 // A Java static call or a runtime call.
3335 //
3336 // Branch-and-link relative to a trampoline.
3337 // The trampoline loads the target address and does a long branch to there.
3338 // In case we call java, the trampoline branches to a interpreter_stub
3339 // which loads the inline cache and the real call target from the constant pool.
3340 //
3341 // This basically looks like this:
3342 //
3343 // >>>> consts -+ -+
3344 // | |- offset1
3345 // [call target1] | <-+
3346 // [IC cache] |- offset2
3347 // [call target2] <--+
3348 //
3349 // <<<< consts
3350 // >>>> insts
3351 //
3352 // bl offset16 -+ -+ ??? // How many bits available?
3353 // | |
3354 // <<<< insts | |
3355 // >>>> stubs | |
3356 // | |- trampoline_stub_Reloc
3357 // trampoline stub: | <-+
3358 // r2 = toc |
3359 // r2 = [r2 + offset1] | // Load call target1 from const section
3360 // mtctr r2 |
3361 // bctr |- static_stub_Reloc
3362 // comp_to_interp_stub: <---+
3363 // r1 = toc
3364 // ICreg = [r1 + IC_offset] // Load IC from const section
3365 // r1 = [r1 + offset2] // Load call target2 from const section
3366 // mtctr r1
3367 // bctr
3368 //
3369 // <<<< stubs
3370 //
3371 // The call instruction in the code either
3372 // - Branches directly to a compiled method if the offset is encodable in instruction.
3373 // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3374 // - Branches to the compiled_to_interp stub if the target is interpreted.
3375 //
3376 // Further there are three relocations from the loads to the constants in
3377 // the constant section.
3378 //
3379 // Usage of r1 and r2 in the stubs allows to distinguish them.
3380 enc_class enc_java_static_call(method meth) %{
3381 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3382
3383 MacroAssembler _masm(&cbuf);
3384 address entry_point = (address)$meth$$method;
3385
3386 if (!_method) {
3387 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3388 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3389 } else {
3390 // Remember the offset not the address.
3391 const int start_offset = __ offset();
3392 // The trampoline stub.
3393 if (!Compile::current()->in_scratch_emit_size()) {
3394 // No entry point given, use the current pc.
3395 // Make sure branch fits into
3396 if (entry_point == 0) entry_point = __ pc();
3397
3398 // Put the entry point as a constant into the constant pool.
3399 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3400 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3401
3402
3403 // Emit the trampoline stub which will be related to the branch-and-link below.
3404 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3405 if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3406 int method_index = resolved_method_index(cbuf);
3407 __ relocate(_optimized_virtual ? opt_virtual_call_Relocate::spec(method_index)
3408 : static_call_Relocate::spec(method_index));
3409 }
3410
3411 // The real call.
3412 // Note: At this point we do not have the address of the trampoline
3413 // stub, and the entry point might be too far away for bl, so __ pc()
3414 // serves as dummy and the bl will be patched later.
3415 cbuf.set_insts_mark();
3416 __ bl(__ pc()); // Emits a relocation.
3417
3418 // The stub for call to interpreter.
3419 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3420 if (stub == NULL) {
3421 ciEnv::current()->record_failure("CodeCache is full");
3422 return;
3423 }
3424 }
3425 %}
3426
3427 // Emit a method handle call.
3428 //
3429 // Method handle calls from compiled to compiled are going thru a
3430 // c2i -> i2c adapter, extending the frame for their arguments. The
3431 // caller however, returns directly to the compiled callee, that has
3432 // to cope with the extended frame. We restore the original frame by
3433 // loading the callers sp and adding the calculated framesize.
3434 enc_class enc_java_handle_call(method meth) %{
3435 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3436
3437 MacroAssembler _masm(&cbuf);
3438 address entry_point = (address)$meth$$method;
3439
3440 // Remember the offset not the address.
3441 const int start_offset = __ offset();
3442 // The trampoline stub.
3443 if (!ra_->C->in_scratch_emit_size()) {
3444 // No entry point given, use the current pc.
3445 // Make sure branch fits into
3446 if (entry_point == 0) entry_point = __ pc();
3447
3448 // Put the entry point as a constant into the constant pool.
3449 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3450 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3451
3452 assert(!_override_symbolic_info, "resolved method overriding not supported");
3453
3454 // Emit the trampoline stub which will be related to the branch-and-link below.
3455 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3456 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3457 assert(_optimized_virtual, "methodHandle call should be a virtual call");
3458 __ relocate(relocInfo::opt_virtual_call_type);
3459 }
3460
3461 // The real call.
3462 // Note: At this point we do not have the address of the trampoline
3463 // stub, and the entry point might be too far away for bl, so __ pc()
3464 // serves as dummy and the bl will be patched later.
3465 cbuf.set_insts_mark();
3466 __ bl(__ pc()); // Emits a relocation.
3467
3468 assert(_method, "execute next statement conditionally");
3469 // The stub for call to interpreter.
3470 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3471 if (stub == NULL) {
3472 ciEnv::current()->record_failure("CodeCache is full");
3473 return;
3474 }
3475
3476 // Restore original sp.
3477 __ ld(R11_scratch1, 0, R1_SP); // Load caller sp.
3478 const long framesize = ra_->C->frame_slots() << LogBytesPerInt;
3479 unsigned int bytes = (unsigned int)framesize;
3480 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
3481 if (Assembler::is_simm(-offset, 16)) {
3482 __ addi(R1_SP, R11_scratch1, -offset);
3483 } else {
3484 __ load_const_optimized(R12_scratch2, -offset);
3485 __ add(R1_SP, R11_scratch1, R12_scratch2);
3486 }
3487 #ifdef ASSERT
3488 __ ld(R12_scratch2, 0, R1_SP); // Load from unextended_sp.
3489 __ cmpd(CCR0, R11_scratch1, R12_scratch2);
3490 __ asm_assert_eq("backlink changed", 0x8000);
3491 #endif
3492 // If fails should store backlink before unextending.
3493
3494 if (ra_->C->env()->failing()) {
3495 return;
3496 }
3497 %}
3498
3499 // Second node of expanded dynamic call - the call.
3500 enc_class enc_java_dynamic_call_sched(method meth) %{
3501 // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3502
3503 MacroAssembler _masm(&cbuf);
3504
3505 if (!ra_->C->in_scratch_emit_size()) {
3506 // Create a call trampoline stub for the given method.
3507 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3508 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3509 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3510 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3511 if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3512
3513 // Build relocation at call site with ic position as data.
3514 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3515 (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3516 "must have one, but can't have both");
3517 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3518 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1),
3519 "must contain instruction offset");
3520 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3521 ? _load_ic_hi_node->_cbuf_insts_offset
3522 : _load_ic_node->_cbuf_insts_offset;
3523 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3524 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3525 "should be load from TOC");
3526 int method_index = resolved_method_index(cbuf);
3527 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3528 }
3529
3530 // At this point I do not have the address of the trampoline stub,
3531 // and the entry point might be too far away for bl. Pc() serves
3532 // as dummy and bl will be patched later.
3533 __ bl((address) __ pc());
3534 %}
3535
3536 // postalloc expand emitter for virtual calls.
3537 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3538
3539 // Create the nodes for loading the IC from the TOC.
3540 loadConLNodesTuple loadConLNodes_IC =
3541 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3542 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3543
3544 // Create the call node.
3545 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3546 call->_method_handle_invoke = _method_handle_invoke;
3547 call->_vtable_index = _vtable_index;
3548 call->_method = _method;
3549 call->_bci = _bci;
3550 call->_optimized_virtual = _optimized_virtual;
3551 call->_tf = _tf;
3552 call->_entry_point = _entry_point;
3553 call->_cnt = _cnt;
3554 call->_argsize = _argsize;
3555 call->_oop_map = _oop_map;
3556 call->_jvms = _jvms;
3557 call->_jvmadj = _jvmadj;
3558 call->_in_rms = _in_rms;
3559 call->_nesting = _nesting;
3560
3561 // New call needs all inputs of old call.
3562 // Req...
3563 for (uint i = 0; i < req(); ++i) {
3564 // The expanded node does not need toc any more.
3565 // Add the inline cache constant here instead. This expresses the
3566 // register of the inline cache must be live at the call.
3567 // Else we would have to adapt JVMState by -1.
3568 if (i == mach_constant_base_node_input()) {
3569 call->add_req(loadConLNodes_IC._last);
3570 } else {
3571 call->add_req(in(i));
3572 }
3573 }
3574 // ...as well as prec
3575 for (uint i = req(); i < len(); ++i) {
3576 call->add_prec(in(i));
3577 }
3578
3579 // Remember nodes loading the inline cache into r19.
3580 call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3581 call->_load_ic_node = loadConLNodes_IC._small;
3582
3583 // Operands for new nodes.
3584 call->_opnds[0] = _opnds[0];
3585 call->_opnds[1] = _opnds[1];
3586
3587 // Only the inline cache is associated with a register.
3588 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3589
3590 // Push new nodes.
3591 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3592 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last);
3593 nodes->push(call);
3594 %}
3595
3596 // Compound version of call dynamic
3597 // Toc is only passed so that it can be used in ins_encode statement.
3598 // In the code we have to use $constanttablebase.
3599 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3600 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3601 MacroAssembler _masm(&cbuf);
3602 int start_offset = __ offset();
3603
3604 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3605 #if 0
3606 int vtable_index = this->_vtable_index;
3607 if (_vtable_index < 0) {
3608 // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3609 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3610 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3611
3612 // Virtual call relocation will point to ic load.
3613 address virtual_call_meta_addr = __ pc();
3614 // Load a clear inline cache.
3615 AddressLiteral empty_ic((address) Universe::non_oop_word());
3616 __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc);
3617 // CALL to fixup routine. Fixup routine uses ScopeDesc info
3618 // to determine who we intended to call.
3619 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3620 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3621 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3622 "Fix constant in ret_addr_offset()");
3623 } else {
3624 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3625 // Go thru the vtable. Get receiver klass. Receiver already
3626 // checked for non-null. If we'll go thru a C2I adapter, the
3627 // interpreter expects method in R19_method.
3628
3629 __ load_klass(R11_scratch1, R3);
3630
3631 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size();
3632 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes();
3633 __ li(R19_method, v_off);
3634 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3635 // NOTE: for vtable dispatches, the vtable entry will never be
3636 // null. However it may very well end up in handle_wrong_method
3637 // if the method is abstract for the particular class.
3638 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3639 // Call target. Either compiled code or C2I adapter.
3640 __ mtctr(R11_scratch1);
3641 __ bctrl();
3642 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3643 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3644 }
3645 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3646 "Fix constant in ret_addr_offset()");
3647 }
3648 #endif
3649 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3650 %}
3651
3652 // a runtime call
3653 enc_class enc_java_to_runtime_call (method meth) %{
3654 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3655
3656 MacroAssembler _masm(&cbuf);
3657 const address start_pc = __ pc();
3658
3659 #if defined(ABI_ELFv2)
3660 address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3661 __ call_c(entry, relocInfo::runtime_call_type);
3662 #else
3663 // The function we're going to call.
3664 FunctionDescriptor fdtemp;
3665 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3666
3667 Register Rtoc = R12_scratch2;
3668 // Calculate the method's TOC.
3669 __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3670 // Put entry, env, toc into the constant pool, this needs up to 3 constant
3671 // pool entries; call_c_using_toc will optimize the call.
3672 __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3673 #endif
3674
3675 // Check the ret_addr_offset.
3676 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc,
3677 "Fix constant in ret_addr_offset()");
3678 %}
3679
3680 // Move to ctr for leaf call.
3681 // This enc_class is needed so that scheduler gets proper
3682 // input mapping for latency computation.
3683 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3684 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3685 MacroAssembler _masm(&cbuf);
3686 __ mtctr($src$$Register);
3687 %}
3688
3689 // Postalloc expand emitter for runtime leaf calls.
3690 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3691 loadConLNodesTuple loadConLNodes_Entry;
3692 #if defined(ABI_ELFv2)
3693 jlong entry_address = (jlong) this->entry_point();
3694 assert(entry_address, "need address here");
3695 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3696 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3697 #else
3698 // Get the struct that describes the function we are about to call.
3699 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3700 assert(fd, "need fd here");
3701 jlong entry_address = (jlong) fd->entry();
3702 // new nodes
3703 loadConLNodesTuple loadConLNodes_Env;
3704 loadConLNodesTuple loadConLNodes_Toc;
3705
3706 // Create nodes and operands for loading the entry point.
3707 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3708 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3709
3710
3711 // Create nodes and operands for loading the env pointer.
3712 if (fd->env() != NULL) {
3713 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3714 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3715 } else {
3716 loadConLNodes_Env._large_hi = NULL;
3717 loadConLNodes_Env._large_lo = NULL;
3718 loadConLNodes_Env._small = NULL;
3719 loadConLNodes_Env._last = new loadConL16Node();
3720 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3721 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3722 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3723 }
3724
3725 // Create nodes and operands for loading the Toc point.
3726 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3727 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3728 #endif // ABI_ELFv2
3729 // mtctr node
3730 MachNode *mtctr = new CallLeafDirect_mtctrNode();
3731
3732 assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3733 mtctr->add_req(0, loadConLNodes_Entry._last);
3734
3735 mtctr->_opnds[0] = new iRegLdstOper();
3736 mtctr->_opnds[1] = new iRegLdstOper();
3737
3738 // call node
3739 MachCallLeafNode *call = new CallLeafDirectNode();
3740
3741 call->_opnds[0] = _opnds[0];
3742 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3743
3744 // Make the new call node look like the old one.
3745 call->_name = _name;
3746 call->_tf = _tf;
3747 call->_entry_point = _entry_point;
3748 call->_cnt = _cnt;
3749 call->_argsize = _argsize;
3750 call->_oop_map = _oop_map;
3751 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3752 call->_jvms = NULL;
3753 call->_jvmadj = _jvmadj;
3754 call->_in_rms = _in_rms;
3755 call->_nesting = _nesting;
3756
3757
3758 // New call needs all inputs of old call.
3759 // Req...
3760 for (uint i = 0; i < req(); ++i) {
3761 if (i != mach_constant_base_node_input()) {
3762 call->add_req(in(i));
3763 }
3764 }
3765
3766 // These must be reqired edges, as the registers are live up to
3767 // the call. Else the constants are handled as kills.
3768 call->add_req(mtctr);
3769 #if !defined(ABI_ELFv2)
3770 call->add_req(loadConLNodes_Env._last);
3771 call->add_req(loadConLNodes_Toc._last);
3772 #endif
3773
3774 // ...as well as prec
3775 for (uint i = req(); i < len(); ++i) {
3776 call->add_prec(in(i));
3777 }
3778
3779 // registers
3780 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3781
3782 // Insert the new nodes.
3783 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3784 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last);
3785 #if !defined(ABI_ELFv2)
3786 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi);
3787 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last);
3788 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi);
3789 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last);
3790 #endif
3791 nodes->push(mtctr);
3792 nodes->push(call);
3793 %}
3794 %}
3795
3796 //----------FRAME--------------------------------------------------------------
3797 // Definition of frame structure and management information.
3798
3799 frame %{
3800 // What direction does stack grow in (assumed to be same for native & Java).
3801 stack_direction(TOWARDS_LOW);
3802
3803 // These two registers define part of the calling convention between
3804 // compiled code and the interpreter.
3805
3806 // Inline Cache Register or method for I2C.
3807 inline_cache_reg(R19); // R19_method
3808
3809 // Method Oop Register when calling interpreter.
3810 interpreter_method_oop_reg(R19); // R19_method
3811
3812 // Optional: name the operand used by cisc-spilling to access
3813 // [stack_pointer + offset].
3814 cisc_spilling_operand_name(indOffset);
3815
3816 // Number of stack slots consumed by a Monitor enter.
3817 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3818
3819 // Compiled code's Frame Pointer.
3820 frame_pointer(R1); // R1_SP
3821
3822 // Interpreter stores its frame pointer in a register which is
3823 // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3824 // interpreted java to compiled java.
3825 //
3826 // R14_state holds pointer to caller's cInterpreter.
3827 interpreter_frame_pointer(R14); // R14_state
3828
3829 stack_alignment(frame::alignment_in_bytes);
3830
3831 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3832
3833 // Number of outgoing stack slots killed above the
3834 // out_preserve_stack_slots for calls to C. Supports the var-args
3835 // backing area for register parms.
3836 //
3837 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3838
3839 // The after-PROLOG location of the return address. Location of
3840 // return address specifies a type (REG or STACK) and a number
3841 // representing the register number (i.e. - use a register name) or
3842 // stack slot.
3843 //
3844 // A: Link register is stored in stack slot ...
3845 // M: ... but it's in the caller's frame according to PPC-64 ABI.
3846 // J: Therefore, we make sure that the link register is also in R11_scratch1
3847 // at the end of the prolog.
3848 // B: We use R20, now.
3849 //return_addr(REG R20);
3850
3851 // G: After reading the comments made by all the luminaries on their
3852 // failure to tell the compiler where the return address really is,
3853 // I hardly dare to try myself. However, I'm convinced it's in slot
3854 // 4 what apparently works and saves us some spills.
3855 return_addr(STACK 4);
3856
3857 // This is the body of the function
3858 //
3859 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3860 // uint length, // length of array
3861 // bool is_outgoing)
3862 //
3863 // The `sig' array is to be updated. sig[j] represents the location
3864 // of the j-th argument, either a register or a stack slot.
3865
3866 // Comment taken from i486.ad:
3867 // Body of function which returns an integer array locating
3868 // arguments either in registers or in stack slots. Passed an array
3869 // of ideal registers called "sig" and a "length" count. Stack-slot
3870 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3871 // arguments for a CALLEE. Incoming stack arguments are
3872 // automatically biased by the preserve_stack_slots field above.
3873 calling_convention %{
3874 // No difference between ingoing/outgoing. Just pass false.
3875 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3876 %}
3877
3878 // Comment taken from i486.ad:
3879 // Body of function which returns an integer array locating
3880 // arguments either in registers or in stack slots. Passed an array
3881 // of ideal registers called "sig" and a "length" count. Stack-slot
3882 // offsets are based on outgoing arguments, i.e. a CALLER setting up
3883 // arguments for a CALLEE. Incoming stack arguments are
3884 // automatically biased by the preserve_stack_slots field above.
3885 c_calling_convention %{
3886 // This is obviously always outgoing.
3887 // C argument in register AND stack slot.
3888 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3889 %}
3890
3891 // Location of native (C/C++) and interpreter return values. This
3892 // is specified to be the same as Java. In the 32-bit VM, long
3893 // values are actually returned from native calls in O0:O1 and
3894 // returned to the interpreter in I0:I1. The copying to and from
3895 // the register pairs is done by the appropriate call and epilog
3896 // opcodes. This simplifies the register allocator.
3897 c_return_value %{
3898 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3899 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3900 "only return normal values");
3901 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3902 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3903 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3904 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3905 %}
3906
3907 // Location of compiled Java return values. Same as C
3908 return_value %{
3909 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3910 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3911 "only return normal values");
3912 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL
3913 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num };
3914 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3915 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3916 %}
3917 %}
3918
3919
3920 //----------ATTRIBUTES---------------------------------------------------------
3921
3922 //----------Operand Attributes-------------------------------------------------
3923 op_attrib op_cost(1); // Required cost attribute.
3924
3925 //----------Instruction Attributes---------------------------------------------
3926
3927 // Cost attribute. required.
3928 ins_attrib ins_cost(DEFAULT_COST);
3929
3930 // Is this instruction a non-matching short branch variant of some
3931 // long branch? Not required.
3932 ins_attrib ins_short_branch(0);
3933
3934 ins_attrib ins_is_TrapBasedCheckNode(true);
3935
3936 // Number of constants.
3937 // This instruction uses the given number of constants
3938 // (optional attribute).
3939 // This is needed to determine in time whether the constant pool will
3940 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3941 // is determined. It's also used to compute the constant pool size
3942 // in Output().
3943 ins_attrib ins_num_consts(0);
3944
3945 // Required alignment attribute (must be a power of 2) specifies the
3946 // alignment that some part of the instruction (not necessarily the
3947 // start) requires. If > 1, a compute_padding() function must be
3948 // provided for the instruction.
3949 ins_attrib ins_alignment(1);
3950
3951 // Enforce/prohibit rematerializations.
3952 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3953 // then rematerialization of that instruction is prohibited and the
3954 // instruction's value will be spilled if necessary.
3955 // Causes that MachNode::rematerialize() returns false.
3956 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3957 // then rematerialization should be enforced and a copy of the instruction
3958 // should be inserted if possible; rematerialization is not guaranteed.
3959 // Note: this may result in rematerializations in front of every use.
3960 // Causes that MachNode::rematerialize() can return true.
3961 // (optional attribute)
3962 ins_attrib ins_cannot_rematerialize(false);
3963 ins_attrib ins_should_rematerialize(false);
3964
3965 // Instruction has variable size depending on alignment.
3966 ins_attrib ins_variable_size_depending_on_alignment(false);
3967
3968 // Instruction is a nop.
3969 ins_attrib ins_is_nop(false);
3970
3971 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3972 ins_attrib ins_use_mach_if_fast_lock_node(false);
3973
3974 // Field for the toc offset of a constant.
3975 //
3976 // This is needed if the toc offset is not encodable as an immediate in
3977 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3978 // added to the toc, and from this a load with immediate is performed.
3979 // With postalloc expand, we get two nodes that require the same offset
3980 // but which don't know about each other. The offset is only known
3981 // when the constant is added to the constant pool during emitting.
3982 // It is generated in the 'hi'-node adding the upper bits, and saved
3983 // in this node. The 'lo'-node has a link to the 'hi'-node and reads
3984 // the offset from there when it gets encoded.
3985 ins_attrib ins_field_const_toc_offset(0);
3986 ins_attrib ins_field_const_toc_offset_hi_node(0);
3987
3988 // A field that can hold the instructions offset in the code buffer.
3989 // Set in the nodes emitter.
3990 ins_attrib ins_field_cbuf_insts_offset(-1);
3991
3992 // Fields for referencing a call's load-IC-node.
3993 // If the toc offset can not be encoded as an immediate in a load, we
3994 // use two nodes.
3995 ins_attrib ins_field_load_ic_hi_node(0);
3996 ins_attrib ins_field_load_ic_node(0);
3997
3998 //----------OPERANDS-----------------------------------------------------------
3999 // Operand definitions must precede instruction definitions for correct
4000 // parsing in the ADLC because operands constitute user defined types
4001 // which are used in instruction definitions.
4002 //
4003 // Formats are generated automatically for constants and base registers.
4004
4005 //----------Simple Operands----------------------------------------------------
4006 // Immediate Operands
4007
4008 // Integer Immediate: 32-bit
4009 operand immI() %{
4010 match(ConI);
4011 op_cost(40);
4012 format %{ %}
4013 interface(CONST_INTER);
4014 %}
4015
4016 operand immI8() %{
4017 predicate(Assembler::is_simm(n->get_int(), 8));
4018 op_cost(0);
4019 match(ConI);
4020 format %{ %}
4021 interface(CONST_INTER);
4022 %}
4023
4024 // Integer Immediate: 16-bit
4025 operand immI16() %{
4026 predicate(Assembler::is_simm(n->get_int(), 16));
4027 op_cost(0);
4028 match(ConI);
4029 format %{ %}
4030 interface(CONST_INTER);
4031 %}
4032
4033 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
4034 operand immIhi16() %{
4035 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
4036 match(ConI);
4037 op_cost(0);
4038 format %{ %}
4039 interface(CONST_INTER);
4040 %}
4041
4042 operand immInegpow2() %{
4043 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4044 match(ConI);
4045 op_cost(0);
4046 format %{ %}
4047 interface(CONST_INTER);
4048 %}
4049
4050 operand immIpow2minus1() %{
4051 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4052 match(ConI);
4053 op_cost(0);
4054 format %{ %}
4055 interface(CONST_INTER);
4056 %}
4057
4058 operand immIpowerOf2() %{
4059 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4060 match(ConI);
4061 op_cost(0);
4062 format %{ %}
4063 interface(CONST_INTER);
4064 %}
4065
4066 // Unsigned Integer Immediate: the values 0-31
4067 operand uimmI5() %{
4068 predicate(Assembler::is_uimm(n->get_int(), 5));
4069 match(ConI);
4070 op_cost(0);
4071 format %{ %}
4072 interface(CONST_INTER);
4073 %}
4074
4075 // Unsigned Integer Immediate: 6-bit
4076 operand uimmI6() %{
4077 predicate(Assembler::is_uimm(n->get_int(), 6));
4078 match(ConI);
4079 op_cost(0);
4080 format %{ %}
4081 interface(CONST_INTER);
4082 %}
4083
4084 // Unsigned Integer Immediate: 6-bit int, greater than 32
4085 operand uimmI6_ge32() %{
4086 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4087 match(ConI);
4088 op_cost(0);
4089 format %{ %}
4090 interface(CONST_INTER);
4091 %}
4092
4093 // Unsigned Integer Immediate: 15-bit
4094 operand uimmI15() %{
4095 predicate(Assembler::is_uimm(n->get_int(), 15));
4096 match(ConI);
4097 op_cost(0);
4098 format %{ %}
4099 interface(CONST_INTER);
4100 %}
4101
4102 // Unsigned Integer Immediate: 16-bit
4103 operand uimmI16() %{
4104 predicate(Assembler::is_uimm(n->get_int(), 16));
4105 match(ConI);
4106 op_cost(0);
4107 format %{ %}
4108 interface(CONST_INTER);
4109 %}
4110
4111 // constant 'int 0'.
4112 operand immI_0() %{
4113 predicate(n->get_int() == 0);
4114 match(ConI);
4115 op_cost(0);
4116 format %{ %}
4117 interface(CONST_INTER);
4118 %}
4119
4120 // constant 'int 1'.
4121 operand immI_1() %{
4122 predicate(n->get_int() == 1);
4123 match(ConI);
4124 op_cost(0);
4125 format %{ %}
4126 interface(CONST_INTER);
4127 %}
4128
4129 // constant 'int -1'.
4130 operand immI_minus1() %{
4131 predicate(n->get_int() == -1);
4132 match(ConI);
4133 op_cost(0);
4134 format %{ %}
4135 interface(CONST_INTER);
4136 %}
4137
4138 // int value 16.
4139 operand immI_16() %{
4140 predicate(n->get_int() == 16);
4141 match(ConI);
4142 op_cost(0);
4143 format %{ %}
4144 interface(CONST_INTER);
4145 %}
4146
4147 // int value 24.
4148 operand immI_24() %{
4149 predicate(n->get_int() == 24);
4150 match(ConI);
4151 op_cost(0);
4152 format %{ %}
4153 interface(CONST_INTER);
4154 %}
4155
4156 // Compressed oops constants
4157 // Pointer Immediate
4158 operand immN() %{
4159 match(ConN);
4160
4161 op_cost(10);
4162 format %{ %}
4163 interface(CONST_INTER);
4164 %}
4165
4166 // NULL Pointer Immediate
4167 operand immN_0() %{
4168 predicate(n->get_narrowcon() == 0);
4169 match(ConN);
4170
4171 op_cost(0);
4172 format %{ %}
4173 interface(CONST_INTER);
4174 %}
4175
4176 // Compressed klass constants
4177 operand immNKlass() %{
4178 match(ConNKlass);
4179
4180 op_cost(0);
4181 format %{ %}
4182 interface(CONST_INTER);
4183 %}
4184
4185 // This operand can be used to avoid matching of an instruct
4186 // with chain rule.
4187 operand immNKlass_NM() %{
4188 match(ConNKlass);
4189 predicate(false);
4190 op_cost(0);
4191 format %{ %}
4192 interface(CONST_INTER);
4193 %}
4194
4195 // Pointer Immediate: 64-bit
4196 operand immP() %{
4197 match(ConP);
4198 op_cost(0);
4199 format %{ %}
4200 interface(CONST_INTER);
4201 %}
4202
4203 // Operand to avoid match of loadConP.
4204 // This operand can be used to avoid matching of an instruct
4205 // with chain rule.
4206 operand immP_NM() %{
4207 match(ConP);
4208 predicate(false);
4209 op_cost(0);
4210 format %{ %}
4211 interface(CONST_INTER);
4212 %}
4213
4214 // costant 'pointer 0'.
4215 operand immP_0() %{
4216 predicate(n->get_ptr() == 0);
4217 match(ConP);
4218 op_cost(0);
4219 format %{ %}
4220 interface(CONST_INTER);
4221 %}
4222
4223 // pointer 0x0 or 0x1
4224 operand immP_0or1() %{
4225 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4226 match(ConP);
4227 op_cost(0);
4228 format %{ %}
4229 interface(CONST_INTER);
4230 %}
4231
4232 operand immL() %{
4233 match(ConL);
4234 op_cost(40);
4235 format %{ %}
4236 interface(CONST_INTER);
4237 %}
4238
4239 // Long Immediate: 16-bit
4240 operand immL16() %{
4241 predicate(Assembler::is_simm(n->get_long(), 16));
4242 match(ConL);
4243 op_cost(0);
4244 format %{ %}
4245 interface(CONST_INTER);
4246 %}
4247
4248 // Long Immediate: 16-bit, 4-aligned
4249 operand immL16Alg4() %{
4250 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4251 match(ConL);
4252 op_cost(0);
4253 format %{ %}
4254 interface(CONST_INTER);
4255 %}
4256
4257 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4258 operand immL32hi16() %{
4259 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4260 match(ConL);
4261 op_cost(0);
4262 format %{ %}
4263 interface(CONST_INTER);
4264 %}
4265
4266 // Long Immediate: 32-bit
4267 operand immL32() %{
4268 predicate(Assembler::is_simm(n->get_long(), 32));
4269 match(ConL);
4270 op_cost(0);
4271 format %{ %}
4272 interface(CONST_INTER);
4273 %}
4274
4275 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4276 operand immLhighest16() %{
4277 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4278 match(ConL);
4279 op_cost(0);
4280 format %{ %}
4281 interface(CONST_INTER);
4282 %}
4283
4284 operand immLnegpow2() %{
4285 predicate(is_power_of_2_long((jlong)-(n->get_long())));
4286 match(ConL);
4287 op_cost(0);
4288 format %{ %}
4289 interface(CONST_INTER);
4290 %}
4291
4292 operand immLpow2minus1() %{
4293 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4294 (n->get_long() != (jlong)0xffffffffffffffffL));
4295 match(ConL);
4296 op_cost(0);
4297 format %{ %}
4298 interface(CONST_INTER);
4299 %}
4300
4301 // constant 'long 0'.
4302 operand immL_0() %{
4303 predicate(n->get_long() == 0L);
4304 match(ConL);
4305 op_cost(0);
4306 format %{ %}
4307 interface(CONST_INTER);
4308 %}
4309
4310 // constat ' long -1'.
4311 operand immL_minus1() %{
4312 predicate(n->get_long() == -1L);
4313 match(ConL);
4314 op_cost(0);
4315 format %{ %}
4316 interface(CONST_INTER);
4317 %}
4318
4319 // Long Immediate: low 32-bit mask
4320 operand immL_32bits() %{
4321 predicate(n->get_long() == 0xFFFFFFFFL);
4322 match(ConL);
4323 op_cost(0);
4324 format %{ %}
4325 interface(CONST_INTER);
4326 %}
4327
4328 // Unsigned Long Immediate: 16-bit
4329 operand uimmL16() %{
4330 predicate(Assembler::is_uimm(n->get_long(), 16));
4331 match(ConL);
4332 op_cost(0);
4333 format %{ %}
4334 interface(CONST_INTER);
4335 %}
4336
4337 // Float Immediate
4338 operand immF() %{
4339 match(ConF);
4340 op_cost(40);
4341 format %{ %}
4342 interface(CONST_INTER);
4343 %}
4344
4345 // Float Immediate: +0.0f.
4346 operand immF_0() %{
4347 predicate(jint_cast(n->getf()) == 0);
4348 match(ConF);
4349
4350 op_cost(0);
4351 format %{ %}
4352 interface(CONST_INTER);
4353 %}
4354
4355 // Double Immediate
4356 operand immD() %{
4357 match(ConD);
4358 op_cost(40);
4359 format %{ %}
4360 interface(CONST_INTER);
4361 %}
4362
4363 // Integer Register Operands
4364 // Integer Destination Register
4365 // See definition of reg_class bits32_reg_rw.
4366 operand iRegIdst() %{
4367 constraint(ALLOC_IN_RC(bits32_reg_rw));
4368 match(RegI);
4369 match(rscratch1RegI);
4370 match(rscratch2RegI);
4371 match(rarg1RegI);
4372 match(rarg2RegI);
4373 match(rarg3RegI);
4374 match(rarg4RegI);
4375 format %{ %}
4376 interface(REG_INTER);
4377 %}
4378
4379 // Integer Source Register
4380 // See definition of reg_class bits32_reg_ro.
4381 operand iRegIsrc() %{
4382 constraint(ALLOC_IN_RC(bits32_reg_ro));
4383 match(RegI);
4384 match(rscratch1RegI);
4385 match(rscratch2RegI);
4386 match(rarg1RegI);
4387 match(rarg2RegI);
4388 match(rarg3RegI);
4389 match(rarg4RegI);
4390 format %{ %}
4391 interface(REG_INTER);
4392 %}
4393
4394 operand rscratch1RegI() %{
4395 constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4396 match(iRegIdst);
4397 format %{ %}
4398 interface(REG_INTER);
4399 %}
4400
4401 operand rscratch2RegI() %{
4402 constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4403 match(iRegIdst);
4404 format %{ %}
4405 interface(REG_INTER);
4406 %}
4407
4408 operand rarg1RegI() %{
4409 constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4410 match(iRegIdst);
4411 format %{ %}
4412 interface(REG_INTER);
4413 %}
4414
4415 operand rarg2RegI() %{
4416 constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4417 match(iRegIdst);
4418 format %{ %}
4419 interface(REG_INTER);
4420 %}
4421
4422 operand rarg3RegI() %{
4423 constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4424 match(iRegIdst);
4425 format %{ %}
4426 interface(REG_INTER);
4427 %}
4428
4429 operand rarg4RegI() %{
4430 constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4431 match(iRegIdst);
4432 format %{ %}
4433 interface(REG_INTER);
4434 %}
4435
4436 operand rarg1RegL() %{
4437 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4438 match(iRegLdst);
4439 format %{ %}
4440 interface(REG_INTER);
4441 %}
4442
4443 operand rarg2RegL() %{
4444 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4445 match(iRegLdst);
4446 format %{ %}
4447 interface(REG_INTER);
4448 %}
4449
4450 operand rarg3RegL() %{
4451 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4452 match(iRegLdst);
4453 format %{ %}
4454 interface(REG_INTER);
4455 %}
4456
4457 operand rarg4RegL() %{
4458 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4459 match(iRegLdst);
4460 format %{ %}
4461 interface(REG_INTER);
4462 %}
4463
4464 // Pointer Destination Register
4465 // See definition of reg_class bits64_reg_rw.
4466 operand iRegPdst() %{
4467 constraint(ALLOC_IN_RC(bits64_reg_rw));
4468 match(RegP);
4469 match(rscratch1RegP);
4470 match(rscratch2RegP);
4471 match(rarg1RegP);
4472 match(rarg2RegP);
4473 match(rarg3RegP);
4474 match(rarg4RegP);
4475 format %{ %}
4476 interface(REG_INTER);
4477 %}
4478
4479 // Pointer Destination Register
4480 // Operand not using r11 and r12 (killed in epilog).
4481 operand iRegPdstNoScratch() %{
4482 constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4483 match(RegP);
4484 match(rarg1RegP);
4485 match(rarg2RegP);
4486 match(rarg3RegP);
4487 match(rarg4RegP);
4488 format %{ %}
4489 interface(REG_INTER);
4490 %}
4491
4492 // Pointer Source Register
4493 // See definition of reg_class bits64_reg_ro.
4494 operand iRegPsrc() %{
4495 constraint(ALLOC_IN_RC(bits64_reg_ro));
4496 match(RegP);
4497 match(iRegPdst);
4498 match(rscratch1RegP);
4499 match(rscratch2RegP);
4500 match(rarg1RegP);
4501 match(rarg2RegP);
4502 match(rarg3RegP);
4503 match(rarg4RegP);
4504 match(threadRegP);
4505 format %{ %}
4506 interface(REG_INTER);
4507 %}
4508
4509 // Thread operand.
4510 operand threadRegP() %{
4511 constraint(ALLOC_IN_RC(thread_bits64_reg));
4512 match(iRegPdst);
4513 format %{ "R16" %}
4514 interface(REG_INTER);
4515 %}
4516
4517 operand rscratch1RegP() %{
4518 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4519 match(iRegPdst);
4520 format %{ "R11" %}
4521 interface(REG_INTER);
4522 %}
4523
4524 operand rscratch2RegP() %{
4525 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4526 match(iRegPdst);
4527 format %{ %}
4528 interface(REG_INTER);
4529 %}
4530
4531 operand rarg1RegP() %{
4532 constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4533 match(iRegPdst);
4534 format %{ %}
4535 interface(REG_INTER);
4536 %}
4537
4538 operand rarg2RegP() %{
4539 constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4540 match(iRegPdst);
4541 format %{ %}
4542 interface(REG_INTER);
4543 %}
4544
4545 operand rarg3RegP() %{
4546 constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4547 match(iRegPdst);
4548 format %{ %}
4549 interface(REG_INTER);
4550 %}
4551
4552 operand rarg4RegP() %{
4553 constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4554 match(iRegPdst);
4555 format %{ %}
4556 interface(REG_INTER);
4557 %}
4558
4559 operand iRegNsrc() %{
4560 constraint(ALLOC_IN_RC(bits32_reg_ro));
4561 match(RegN);
4562 match(iRegNdst);
4563
4564 format %{ %}
4565 interface(REG_INTER);
4566 %}
4567
4568 operand iRegNdst() %{
4569 constraint(ALLOC_IN_RC(bits32_reg_rw));
4570 match(RegN);
4571
4572 format %{ %}
4573 interface(REG_INTER);
4574 %}
4575
4576 // Long Destination Register
4577 // See definition of reg_class bits64_reg_rw.
4578 operand iRegLdst() %{
4579 constraint(ALLOC_IN_RC(bits64_reg_rw));
4580 match(RegL);
4581 match(rscratch1RegL);
4582 match(rscratch2RegL);
4583 format %{ %}
4584 interface(REG_INTER);
4585 %}
4586
4587 // Long Source Register
4588 // See definition of reg_class bits64_reg_ro.
4589 operand iRegLsrc() %{
4590 constraint(ALLOC_IN_RC(bits64_reg_ro));
4591 match(RegL);
4592 match(iRegLdst);
4593 match(rscratch1RegL);
4594 match(rscratch2RegL);
4595 format %{ %}
4596 interface(REG_INTER);
4597 %}
4598
4599 // Special operand for ConvL2I.
4600 operand iRegL2Isrc(iRegLsrc reg) %{
4601 constraint(ALLOC_IN_RC(bits64_reg_ro));
4602 match(ConvL2I reg);
4603 format %{ "ConvL2I($reg)" %}
4604 interface(REG_INTER)
4605 %}
4606
4607 operand rscratch1RegL() %{
4608 constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4609 match(RegL);
4610 format %{ %}
4611 interface(REG_INTER);
4612 %}
4613
4614 operand rscratch2RegL() %{
4615 constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4616 match(RegL);
4617 format %{ %}
4618 interface(REG_INTER);
4619 %}
4620
4621 // Condition Code Flag Registers
4622 operand flagsReg() %{
4623 constraint(ALLOC_IN_RC(int_flags));
4624 match(RegFlags);
4625 format %{ %}
4626 interface(REG_INTER);
4627 %}
4628
4629 operand flagsRegSrc() %{
4630 constraint(ALLOC_IN_RC(int_flags_ro));
4631 match(RegFlags);
4632 match(flagsReg);
4633 match(flagsRegCR0);
4634 format %{ %}
4635 interface(REG_INTER);
4636 %}
4637
4638 // Condition Code Flag Register CR0
4639 operand flagsRegCR0() %{
4640 constraint(ALLOC_IN_RC(int_flags_CR0));
4641 match(RegFlags);
4642 format %{ "CR0" %}
4643 interface(REG_INTER);
4644 %}
4645
4646 operand flagsRegCR1() %{
4647 constraint(ALLOC_IN_RC(int_flags_CR1));
4648 match(RegFlags);
4649 format %{ "CR1" %}
4650 interface(REG_INTER);
4651 %}
4652
4653 operand flagsRegCR6() %{
4654 constraint(ALLOC_IN_RC(int_flags_CR6));
4655 match(RegFlags);
4656 format %{ "CR6" %}
4657 interface(REG_INTER);
4658 %}
4659
4660 operand regCTR() %{
4661 constraint(ALLOC_IN_RC(ctr_reg));
4662 // RegFlags should work. Introducing a RegSpecial type would cause a
4663 // lot of changes.
4664 match(RegFlags);
4665 format %{"SR_CTR" %}
4666 interface(REG_INTER);
4667 %}
4668
4669 operand regD() %{
4670 constraint(ALLOC_IN_RC(dbl_reg));
4671 match(RegD);
4672 format %{ %}
4673 interface(REG_INTER);
4674 %}
4675
4676 operand regF() %{
4677 constraint(ALLOC_IN_RC(flt_reg));
4678 match(RegF);
4679 format %{ %}
4680 interface(REG_INTER);
4681 %}
4682
4683 // Special Registers
4684
4685 // Method Register
4686 operand inline_cache_regP(iRegPdst reg) %{
4687 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4688 match(reg);
4689 format %{ %}
4690 interface(REG_INTER);
4691 %}
4692
4693 operand compiler_method_oop_regP(iRegPdst reg) %{
4694 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4695 match(reg);
4696 format %{ %}
4697 interface(REG_INTER);
4698 %}
4699
4700 operand interpreter_method_oop_regP(iRegPdst reg) %{
4701 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4702 match(reg);
4703 format %{ %}
4704 interface(REG_INTER);
4705 %}
4706
4707 // Operands to remove register moves in unscaled mode.
4708 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4709 operand iRegP2N(iRegPsrc reg) %{
4710 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4711 constraint(ALLOC_IN_RC(bits64_reg_ro));
4712 match(EncodeP reg);
4713 format %{ "$reg" %}
4714 interface(REG_INTER)
4715 %}
4716
4717 operand iRegN2P(iRegNsrc reg) %{
4718 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4719 constraint(ALLOC_IN_RC(bits32_reg_ro));
4720 match(DecodeN reg);
4721 format %{ "$reg" %}
4722 interface(REG_INTER)
4723 %}
4724
4725 operand iRegN2P_klass(iRegNsrc reg) %{
4726 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4727 constraint(ALLOC_IN_RC(bits32_reg_ro));
4728 match(DecodeNKlass reg);
4729 format %{ "$reg" %}
4730 interface(REG_INTER)
4731 %}
4732
4733 //----------Complex Operands---------------------------------------------------
4734 // Indirect Memory Reference
4735 operand indirect(iRegPsrc reg) %{
4736 constraint(ALLOC_IN_RC(bits64_reg_ro));
4737 match(reg);
4738 op_cost(100);
4739 format %{ "[$reg]" %}
4740 interface(MEMORY_INTER) %{
4741 base($reg);
4742 index(0x0);
4743 scale(0x0);
4744 disp(0x0);
4745 %}
4746 %}
4747
4748 // Indirect with Offset
4749 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4750 constraint(ALLOC_IN_RC(bits64_reg_ro));
4751 match(AddP reg offset);
4752 op_cost(100);
4753 format %{ "[$reg + $offset]" %}
4754 interface(MEMORY_INTER) %{
4755 base($reg);
4756 index(0x0);
4757 scale(0x0);
4758 disp($offset);
4759 %}
4760 %}
4761
4762 // Indirect with 4-aligned Offset
4763 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4764 constraint(ALLOC_IN_RC(bits64_reg_ro));
4765 match(AddP reg offset);
4766 op_cost(100);
4767 format %{ "[$reg + $offset]" %}
4768 interface(MEMORY_INTER) %{
4769 base($reg);
4770 index(0x0);
4771 scale(0x0);
4772 disp($offset);
4773 %}
4774 %}
4775
4776 //----------Complex Operands for Compressed OOPs-------------------------------
4777 // Compressed OOPs with narrow_oop_shift == 0.
4778
4779 // Indirect Memory Reference, compressed OOP
4780 operand indirectNarrow(iRegNsrc reg) %{
4781 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4782 constraint(ALLOC_IN_RC(bits64_reg_ro));
4783 match(DecodeN reg);
4784 op_cost(100);
4785 format %{ "[$reg]" %}
4786 interface(MEMORY_INTER) %{
4787 base($reg);
4788 index(0x0);
4789 scale(0x0);
4790 disp(0x0);
4791 %}
4792 %}
4793
4794 operand indirectNarrow_klass(iRegNsrc reg) %{
4795 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4796 constraint(ALLOC_IN_RC(bits64_reg_ro));
4797 match(DecodeNKlass reg);
4798 op_cost(100);
4799 format %{ "[$reg]" %}
4800 interface(MEMORY_INTER) %{
4801 base($reg);
4802 index(0x0);
4803 scale(0x0);
4804 disp(0x0);
4805 %}
4806 %}
4807
4808 // Indirect with Offset, compressed OOP
4809 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4810 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4811 constraint(ALLOC_IN_RC(bits64_reg_ro));
4812 match(AddP (DecodeN reg) offset);
4813 op_cost(100);
4814 format %{ "[$reg + $offset]" %}
4815 interface(MEMORY_INTER) %{
4816 base($reg);
4817 index(0x0);
4818 scale(0x0);
4819 disp($offset);
4820 %}
4821 %}
4822
4823 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4824 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4825 constraint(ALLOC_IN_RC(bits64_reg_ro));
4826 match(AddP (DecodeNKlass reg) offset);
4827 op_cost(100);
4828 format %{ "[$reg + $offset]" %}
4829 interface(MEMORY_INTER) %{
4830 base($reg);
4831 index(0x0);
4832 scale(0x0);
4833 disp($offset);
4834 %}
4835 %}
4836
4837 // Indirect with 4-aligned Offset, compressed OOP
4838 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4839 predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4840 constraint(ALLOC_IN_RC(bits64_reg_ro));
4841 match(AddP (DecodeN reg) offset);
4842 op_cost(100);
4843 format %{ "[$reg + $offset]" %}
4844 interface(MEMORY_INTER) %{
4845 base($reg);
4846 index(0x0);
4847 scale(0x0);
4848 disp($offset);
4849 %}
4850 %}
4851
4852 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4853 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4854 constraint(ALLOC_IN_RC(bits64_reg_ro));
4855 match(AddP (DecodeNKlass reg) offset);
4856 op_cost(100);
4857 format %{ "[$reg + $offset]" %}
4858 interface(MEMORY_INTER) %{
4859 base($reg);
4860 index(0x0);
4861 scale(0x0);
4862 disp($offset);
4863 %}
4864 %}
4865
4866 //----------Special Memory Operands--------------------------------------------
4867 // Stack Slot Operand
4868 //
4869 // This operand is used for loading and storing temporary values on
4870 // the stack where a match requires a value to flow through memory.
4871 operand stackSlotI(sRegI reg) %{
4872 constraint(ALLOC_IN_RC(stack_slots));
4873 op_cost(100);
4874 //match(RegI);
4875 format %{ "[sp+$reg]" %}
4876 interface(MEMORY_INTER) %{
4877 base(0x1); // R1_SP
4878 index(0x0);
4879 scale(0x0);
4880 disp($reg); // Stack Offset
4881 %}
4882 %}
4883
4884 operand stackSlotL(sRegL reg) %{
4885 constraint(ALLOC_IN_RC(stack_slots));
4886 op_cost(100);
4887 //match(RegL);
4888 format %{ "[sp+$reg]" %}
4889 interface(MEMORY_INTER) %{
4890 base(0x1); // R1_SP
4891 index(0x0);
4892 scale(0x0);
4893 disp($reg); // Stack Offset
4894 %}
4895 %}
4896
4897 operand stackSlotP(sRegP reg) %{
4898 constraint(ALLOC_IN_RC(stack_slots));
4899 op_cost(100);
4900 //match(RegP);
4901 format %{ "[sp+$reg]" %}
4902 interface(MEMORY_INTER) %{
4903 base(0x1); // R1_SP
4904 index(0x0);
4905 scale(0x0);
4906 disp($reg); // Stack Offset
4907 %}
4908 %}
4909
4910 operand stackSlotF(sRegF reg) %{
4911 constraint(ALLOC_IN_RC(stack_slots));
4912 op_cost(100);
4913 //match(RegF);
4914 format %{ "[sp+$reg]" %}
4915 interface(MEMORY_INTER) %{
4916 base(0x1); // R1_SP
4917 index(0x0);
4918 scale(0x0);
4919 disp($reg); // Stack Offset
4920 %}
4921 %}
4922
4923 operand stackSlotD(sRegD reg) %{
4924 constraint(ALLOC_IN_RC(stack_slots));
4925 op_cost(100);
4926 //match(RegD);
4927 format %{ "[sp+$reg]" %}
4928 interface(MEMORY_INTER) %{
4929 base(0x1); // R1_SP
4930 index(0x0);
4931 scale(0x0);
4932 disp($reg); // Stack Offset
4933 %}
4934 %}
4935
4936 // Operands for expressing Control Flow
4937 // NOTE: Label is a predefined operand which should not be redefined in
4938 // the AD file. It is generically handled within the ADLC.
4939
4940 //----------Conditional Branch Operands----------------------------------------
4941 // Comparison Op
4942 //
4943 // This is the operation of the comparison, and is limited to the
4944 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4945 // (!=).
4946 //
4947 // Other attributes of the comparison, such as unsignedness, are specified
4948 // by the comparison instruction that sets a condition code flags register.
4949 // That result is represented by a flags operand whose subtype is appropriate
4950 // to the unsignedness (etc.) of the comparison.
4951 //
4952 // Later, the instruction which matches both the Comparison Op (a Bool) and
4953 // the flags (produced by the Cmp) specifies the coding of the comparison op
4954 // by matching a specific subtype of Bool operand below.
4955
4956 // When used for floating point comparisons: unordered same as less.
4957 operand cmpOp() %{
4958 match(Bool);
4959 format %{ "" %}
4960 interface(COND_INTER) %{
4961 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4962 // BO & BI
4963 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal
4964 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal
4965 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less
4966 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less
4967 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater
4968 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater
4969 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow
4970 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow
4971 %}
4972 %}
4973
4974 //----------OPERAND CLASSES----------------------------------------------------
4975 // Operand Classes are groups of operands that are used to simplify
4976 // instruction definitions by not requiring the AD writer to specify
4977 // seperate instructions for every form of operand when the
4978 // instruction accepts multiple operand types with the same basic
4979 // encoding and format. The classic case of this is memory operands.
4980 // Indirect is not included since its use is limited to Compare & Swap.
4981
4982 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4983 // Memory operand where offsets are 4-aligned. Required for ld, std.
4984 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4985 opclass indirectMemory(indirect, indirectNarrow);
4986
4987 // Special opclass for I and ConvL2I.
4988 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4989
4990 // Operand classes to match encode and decode. iRegN_P2N is only used
4991 // for storeN. I have never seen an encode node elsewhere.
4992 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4993 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4994
4995 //----------PIPELINE-----------------------------------------------------------
4996
4997 pipeline %{
4998
4999 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
5000 // J. Res. & Dev., No. 1, Jan. 2002.
5001
5002 //----------ATTRIBUTES---------------------------------------------------------
5003 attributes %{
5004
5005 // Power4 instructions are of fixed length.
5006 fixed_size_instructions;
5007
5008 // TODO: if `bundle' means number of instructions fetched
5009 // per cycle, this is 8. If `bundle' means Power4 `group', that is
5010 // max instructions issued per cycle, this is 5.
5011 max_instructions_per_bundle = 8;
5012
5013 // A Power4 instruction is 4 bytes long.
5014 instruction_unit_size = 4;
5015
5016 // The Power4 processor fetches 64 bytes...
5017 instruction_fetch_unit_size = 64;
5018
5019 // ...in one line
5020 instruction_fetch_units = 1
5021
5022 // Unused, list one so that array generated by adlc is not empty.
5023 // Aix compiler chokes if _nop_count = 0.
5024 nops(fxNop);
5025 %}
5026
5027 //----------RESOURCES----------------------------------------------------------
5028 // Resources are the functional units available to the machine
5029 resources(
5030 PPC_BR, // branch unit
5031 PPC_CR, // condition unit
5032 PPC_FX1, // integer arithmetic unit 1
5033 PPC_FX2, // integer arithmetic unit 2
5034 PPC_LDST1, // load/store unit 1
5035 PPC_LDST2, // load/store unit 2
5036 PPC_FP1, // float arithmetic unit 1
5037 PPC_FP2, // float arithmetic unit 2
5038 PPC_LDST = PPC_LDST1 | PPC_LDST2,
5039 PPC_FX = PPC_FX1 | PPC_FX2,
5040 PPC_FP = PPC_FP1 | PPC_FP2
5041 );
5042
5043 //----------PIPELINE DESCRIPTION-----------------------------------------------
5044 // Pipeline Description specifies the stages in the machine's pipeline
5045 pipe_desc(
5046 // Power4 longest pipeline path
5047 PPC_IF, // instruction fetch
5048 PPC_IC,
5049 //PPC_BP, // branch prediction
5050 PPC_D0, // decode
5051 PPC_D1, // decode
5052 PPC_D2, // decode
5053 PPC_D3, // decode
5054 PPC_Xfer1,
5055 PPC_GD, // group definition
5056 PPC_MP, // map
5057 PPC_ISS, // issue
5058 PPC_RF, // resource fetch
5059 PPC_EX1, // execute (all units)
5060 PPC_EX2, // execute (FP, LDST)
5061 PPC_EX3, // execute (FP, LDST)
5062 PPC_EX4, // execute (FP)
5063 PPC_EX5, // execute (FP)
5064 PPC_EX6, // execute (FP)
5065 PPC_WB, // write back
5066 PPC_Xfer2,
5067 PPC_CP
5068 );
5069
5070 //----------PIPELINE CLASSES---------------------------------------------------
5071 // Pipeline Classes describe the stages in which input and output are
5072 // referenced by the hardware pipeline.
5073
5074 // Simple pipeline classes.
5075
5076 // Default pipeline class.
5077 pipe_class pipe_class_default() %{
5078 single_instruction;
5079 fixed_latency(2);
5080 %}
5081
5082 // Pipeline class for empty instructions.
5083 pipe_class pipe_class_empty() %{
5084 single_instruction;
5085 fixed_latency(0);
5086 %}
5087
5088 // Pipeline class for compares.
5089 pipe_class pipe_class_compare() %{
5090 single_instruction;
5091 fixed_latency(16);
5092 %}
5093
5094 // Pipeline class for traps.
5095 pipe_class pipe_class_trap() %{
5096 single_instruction;
5097 fixed_latency(100);
5098 %}
5099
5100 // Pipeline class for memory operations.
5101 pipe_class pipe_class_memory() %{
5102 single_instruction;
5103 fixed_latency(16);
5104 %}
5105
5106 // Pipeline class for call.
5107 pipe_class pipe_class_call() %{
5108 single_instruction;
5109 fixed_latency(100);
5110 %}
5111
5112 // Define the class for the Nop node.
5113 define %{
5114 MachNop = pipe_class_default;
5115 %}
5116
5117 %}
5118
5119 //----------INSTRUCTIONS-------------------------------------------------------
5120
5121 // Naming of instructions:
5122 // opA_operB / opA_operB_operC:
5123 // Operation 'op' with one or two source operands 'oper'. Result
5124 // type is A, source operand types are B and C.
5125 // Iff A == B == C, B and C are left out.
5126 //
5127 // The instructions are ordered according to the following scheme:
5128 // - loads
5129 // - load constants
5130 // - prefetch
5131 // - store
5132 // - encode/decode
5133 // - membar
5134 // - conditional moves
5135 // - compare & swap
5136 // - arithmetic and logic operations
5137 // * int: Add, Sub, Mul, Div, Mod
5138 // * int: lShift, arShift, urShift, rot
5139 // * float: Add, Sub, Mul, Div
5140 // * and, or, xor ...
5141 // - register moves: float <-> int, reg <-> stack, repl
5142 // - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5143 // - conv (low level type cast requiring bit changes (sign extend etc)
5144 // - compares, range & zero checks.
5145 // - branches
5146 // - complex operations, intrinsics, min, max, replicate
5147 // - lock
5148 // - Calls
5149 //
5150 // If there are similar instructions with different types they are sorted:
5151 // int before float
5152 // small before big
5153 // signed before unsigned
5154 // e.g., loadS before loadUS before loadI before loadF.
5155
5156
5157 //----------Load/Store Instructions--------------------------------------------
5158
5159 //----------Load Instructions--------------------------------------------------
5160
5161 // Converts byte to int.
5162 // As convB2I_reg, but without match rule. The match rule of convB2I_reg
5163 // reuses the 'amount' operand, but adlc expects that operand specification
5164 // and operands in match rule are equivalent.
5165 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5166 effect(DEF dst, USE src);
5167 format %{ "EXTSB $dst, $src \t// byte->int" %}
5168 size(4);
5169 ins_encode %{
5170 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5171 __ extsb($dst$$Register, $src$$Register);
5172 %}
5173 ins_pipe(pipe_class_default);
5174 %}
5175
5176 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5177 // match-rule, false predicate
5178 match(Set dst (LoadB mem));
5179 predicate(false);
5180
5181 format %{ "LBZ $dst, $mem" %}
5182 size(4);
5183 ins_encode( enc_lbz(dst, mem) );
5184 ins_pipe(pipe_class_memory);
5185 %}
5186
5187 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5188 // match-rule, false predicate
5189 match(Set dst (LoadB mem));
5190 predicate(false);
5191
5192 format %{ "LBZ $dst, $mem\n\t"
5193 "TWI $dst\n\t"
5194 "ISYNC" %}
5195 size(12);
5196 ins_encode( enc_lbz_ac(dst, mem) );
5197 ins_pipe(pipe_class_memory);
5198 %}
5199
5200 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5201 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5202 match(Set dst (LoadB mem));
5203 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5204 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5205 expand %{
5206 iRegIdst tmp;
5207 loadUB_indirect(tmp, mem);
5208 convB2I_reg_2(dst, tmp);
5209 %}
5210 %}
5211
5212 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5213 match(Set dst (LoadB mem));
5214 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5215 expand %{
5216 iRegIdst tmp;
5217 loadUB_indirect_ac(tmp, mem);
5218 convB2I_reg_2(dst, tmp);
5219 %}
5220 %}
5221
5222 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5223 // match-rule, false predicate
5224 match(Set dst (LoadB mem));
5225 predicate(false);
5226
5227 format %{ "LBZ $dst, $mem" %}
5228 size(4);
5229 ins_encode( enc_lbz(dst, mem) );
5230 ins_pipe(pipe_class_memory);
5231 %}
5232
5233 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5234 // match-rule, false predicate
5235 match(Set dst (LoadB mem));
5236 predicate(false);
5237
5238 format %{ "LBZ $dst, $mem\n\t"
5239 "TWI $dst\n\t"
5240 "ISYNC" %}
5241 size(12);
5242 ins_encode( enc_lbz_ac(dst, mem) );
5243 ins_pipe(pipe_class_memory);
5244 %}
5245
5246 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5247 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5248 match(Set dst (LoadB mem));
5249 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5250 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5251
5252 expand %{
5253 iRegIdst tmp;
5254 loadUB_indOffset16(tmp, mem);
5255 convB2I_reg_2(dst, tmp);
5256 %}
5257 %}
5258
5259 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5260 match(Set dst (LoadB mem));
5261 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5262
5263 expand %{
5264 iRegIdst tmp;
5265 loadUB_indOffset16_ac(tmp, mem);
5266 convB2I_reg_2(dst, tmp);
5267 %}
5268 %}
5269
5270 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5271 instruct loadUB(iRegIdst dst, memory mem) %{
5272 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5273 match(Set dst (LoadUB mem));
5274 ins_cost(MEMORY_REF_COST);
5275
5276 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %}
5277 size(4);
5278 ins_encode( enc_lbz(dst, mem) );
5279 ins_pipe(pipe_class_memory);
5280 %}
5281
5282 // Load Unsigned Byte (8bit UNsigned) acquire.
5283 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5284 match(Set dst (LoadUB mem));
5285 ins_cost(3*MEMORY_REF_COST);
5286
5287 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5288 "TWI $dst\n\t"
5289 "ISYNC" %}
5290 size(12);
5291 ins_encode( enc_lbz_ac(dst, mem) );
5292 ins_pipe(pipe_class_memory);
5293 %}
5294
5295 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5296 instruct loadUB2L(iRegLdst dst, memory mem) %{
5297 match(Set dst (ConvI2L (LoadUB mem)));
5298 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5299 ins_cost(MEMORY_REF_COST);
5300
5301 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %}
5302 size(4);
5303 ins_encode( enc_lbz(dst, mem) );
5304 ins_pipe(pipe_class_memory);
5305 %}
5306
5307 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5308 match(Set dst (ConvI2L (LoadUB mem)));
5309 ins_cost(3*MEMORY_REF_COST);
5310
5311 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5312 "TWI $dst\n\t"
5313 "ISYNC" %}
5314 size(12);
5315 ins_encode( enc_lbz_ac(dst, mem) );
5316 ins_pipe(pipe_class_memory);
5317 %}
5318
5319 // Load Short (16bit signed)
5320 instruct loadS(iRegIdst dst, memory mem) %{
5321 match(Set dst (LoadS mem));
5322 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5323 ins_cost(MEMORY_REF_COST);
5324
5325 format %{ "LHA $dst, $mem" %}
5326 size(4);
5327 ins_encode %{
5328 // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5329 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5330 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5331 %}
5332 ins_pipe(pipe_class_memory);
5333 %}
5334
5335 // Load Short (16bit signed) acquire.
5336 instruct loadS_ac(iRegIdst dst, memory mem) %{
5337 match(Set dst (LoadS mem));
5338 ins_cost(3*MEMORY_REF_COST);
5339
5340 format %{ "LHA $dst, $mem\t acquire\n\t"
5341 "TWI $dst\n\t"
5342 "ISYNC" %}
5343 size(12);
5344 ins_encode %{
5345 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5346 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5347 __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5348 __ twi_0($dst$$Register);
5349 __ isync();
5350 %}
5351 ins_pipe(pipe_class_memory);
5352 %}
5353
5354 // Load Char (16bit unsigned)
5355 instruct loadUS(iRegIdst dst, memory mem) %{
5356 match(Set dst (LoadUS mem));
5357 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5358 ins_cost(MEMORY_REF_COST);
5359
5360 format %{ "LHZ $dst, $mem" %}
5361 size(4);
5362 ins_encode( enc_lhz(dst, mem) );
5363 ins_pipe(pipe_class_memory);
5364 %}
5365
5366 // Load Char (16bit unsigned) acquire.
5367 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5368 match(Set dst (LoadUS mem));
5369 ins_cost(3*MEMORY_REF_COST);
5370
5371 format %{ "LHZ $dst, $mem \t// acquire\n\t"
5372 "TWI $dst\n\t"
5373 "ISYNC" %}
5374 size(12);
5375 ins_encode( enc_lhz_ac(dst, mem) );
5376 ins_pipe(pipe_class_memory);
5377 %}
5378
5379 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5380 instruct loadUS2L(iRegLdst dst, memory mem) %{
5381 match(Set dst (ConvI2L (LoadUS mem)));
5382 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5383 ins_cost(MEMORY_REF_COST);
5384
5385 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %}
5386 size(4);
5387 ins_encode( enc_lhz(dst, mem) );
5388 ins_pipe(pipe_class_memory);
5389 %}
5390
5391 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5392 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5393 match(Set dst (ConvI2L (LoadUS mem)));
5394 ins_cost(3*MEMORY_REF_COST);
5395
5396 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5397 "TWI $dst\n\t"
5398 "ISYNC" %}
5399 size(12);
5400 ins_encode( enc_lhz_ac(dst, mem) );
5401 ins_pipe(pipe_class_memory);
5402 %}
5403
5404 // Load Integer.
5405 instruct loadI(iRegIdst dst, memory mem) %{
5406 match(Set dst (LoadI mem));
5407 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5408 ins_cost(MEMORY_REF_COST);
5409
5410 format %{ "LWZ $dst, $mem" %}
5411 size(4);
5412 ins_encode( enc_lwz(dst, mem) );
5413 ins_pipe(pipe_class_memory);
5414 %}
5415
5416 // Load Integer acquire.
5417 instruct loadI_ac(iRegIdst dst, memory mem) %{
5418 match(Set dst (LoadI mem));
5419 ins_cost(3*MEMORY_REF_COST);
5420
5421 format %{ "LWZ $dst, $mem \t// load acquire\n\t"
5422 "TWI $dst\n\t"
5423 "ISYNC" %}
5424 size(12);
5425 ins_encode( enc_lwz_ac(dst, mem) );
5426 ins_pipe(pipe_class_memory);
5427 %}
5428
5429 // Match loading integer and casting it to unsigned int in
5430 // long register.
5431 // LoadI + ConvI2L + AndL 0xffffffff.
5432 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5433 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5434 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5435 ins_cost(MEMORY_REF_COST);
5436
5437 format %{ "LWZ $dst, $mem \t// zero-extend to long" %}
5438 size(4);
5439 ins_encode( enc_lwz(dst, mem) );
5440 ins_pipe(pipe_class_memory);
5441 %}
5442
5443 // Match loading integer and casting it to long.
5444 instruct loadI2L(iRegLdst dst, memory mem) %{
5445 match(Set dst (ConvI2L (LoadI mem)));
5446 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5447 ins_cost(MEMORY_REF_COST);
5448
5449 format %{ "LWA $dst, $mem \t// loadI2L" %}
5450 size(4);
5451 ins_encode %{
5452 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5453 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5454 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5455 %}
5456 ins_pipe(pipe_class_memory);
5457 %}
5458
5459 // Match loading integer and casting it to long - acquire.
5460 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5461 match(Set dst (ConvI2L (LoadI mem)));
5462 ins_cost(3*MEMORY_REF_COST);
5463
5464 format %{ "LWA $dst, $mem \t// loadI2L acquire"
5465 "TWI $dst\n\t"
5466 "ISYNC" %}
5467 size(12);
5468 ins_encode %{
5469 // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5470 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5471 __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5472 __ twi_0($dst$$Register);
5473 __ isync();
5474 %}
5475 ins_pipe(pipe_class_memory);
5476 %}
5477
5478 // Load Long - aligned
5479 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5480 match(Set dst (LoadL mem));
5481 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5482 ins_cost(MEMORY_REF_COST);
5483
5484 format %{ "LD $dst, $mem \t// long" %}
5485 size(4);
5486 ins_encode( enc_ld(dst, mem) );
5487 ins_pipe(pipe_class_memory);
5488 %}
5489
5490 // Load Long - aligned acquire.
5491 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5492 match(Set dst (LoadL mem));
5493 ins_cost(3*MEMORY_REF_COST);
5494
5495 format %{ "LD $dst, $mem \t// long acquire\n\t"
5496 "TWI $dst\n\t"
5497 "ISYNC" %}
5498 size(12);
5499 ins_encode( enc_ld_ac(dst, mem) );
5500 ins_pipe(pipe_class_memory);
5501 %}
5502
5503 // Load Long - UNaligned
5504 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5505 match(Set dst (LoadL_unaligned mem));
5506 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5507 ins_cost(MEMORY_REF_COST);
5508
5509 format %{ "LD $dst, $mem \t// unaligned long" %}
5510 size(4);
5511 ins_encode( enc_ld(dst, mem) );
5512 ins_pipe(pipe_class_memory);
5513 %}
5514
5515 // Load nodes for superwords
5516
5517 // Load Aligned Packed Byte
5518 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5519 predicate(n->as_LoadVector()->memory_size() == 8);
5520 match(Set dst (LoadVector mem));
5521 ins_cost(MEMORY_REF_COST);
5522
5523 format %{ "LD $dst, $mem \t// load 8-byte Vector" %}
5524 size(4);
5525 ins_encode( enc_ld(dst, mem) );
5526 ins_pipe(pipe_class_memory);
5527 %}
5528
5529 // Load Range, range = array length (=jint)
5530 instruct loadRange(iRegIdst dst, memory mem) %{
5531 match(Set dst (LoadRange mem));
5532 ins_cost(MEMORY_REF_COST);
5533
5534 format %{ "LWZ $dst, $mem \t// range" %}
5535 size(4);
5536 ins_encode( enc_lwz(dst, mem) );
5537 ins_pipe(pipe_class_memory);
5538 %}
5539
5540 // Load Compressed Pointer
5541 instruct loadN(iRegNdst dst, memory mem) %{
5542 match(Set dst (LoadN mem));
5543 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5544 ins_cost(MEMORY_REF_COST);
5545
5546 format %{ "LWZ $dst, $mem \t// load compressed ptr" %}
5547 size(4);
5548 ins_encode( enc_lwz(dst, mem) );
5549 ins_pipe(pipe_class_memory);
5550 %}
5551
5552 // Load Compressed Pointer acquire.
5553 instruct loadN_ac(iRegNdst dst, memory mem) %{
5554 match(Set dst (LoadN mem));
5555 ins_cost(3*MEMORY_REF_COST);
5556
5557 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t"
5558 "TWI $dst\n\t"
5559 "ISYNC" %}
5560 size(12);
5561 ins_encode( enc_lwz_ac(dst, mem) );
5562 ins_pipe(pipe_class_memory);
5563 %}
5564
5565 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5566 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5567 match(Set dst (DecodeN (LoadN mem)));
5568 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5569 ins_cost(MEMORY_REF_COST);
5570
5571 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5572 size(4);
5573 ins_encode( enc_lwz(dst, mem) );
5574 ins_pipe(pipe_class_memory);
5575 %}
5576
5577 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5578 match(Set dst (DecodeNKlass (LoadNKlass mem)));
5579 // SAPJVM GL 2014-05-21 Differs.
5580 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5581 _kids[0]->_leaf->as_Load()->is_unordered());
5582 ins_cost(MEMORY_REF_COST);
5583
5584 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %}
5585 size(4);
5586 ins_encode( enc_lwz(dst, mem) );
5587 ins_pipe(pipe_class_memory);
5588 %}
5589
5590 // Load Pointer
5591 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5592 match(Set dst (LoadP mem));
5593 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5594 ins_cost(MEMORY_REF_COST);
5595
5596 format %{ "LD $dst, $mem \t// ptr" %}
5597 size(4);
5598 ins_encode( enc_ld(dst, mem) );
5599 ins_pipe(pipe_class_memory);
5600 %}
5601
5602 // Load Pointer acquire.
5603 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5604 match(Set dst (LoadP mem));
5605 ins_cost(3*MEMORY_REF_COST);
5606
5607 format %{ "LD $dst, $mem \t// ptr acquire\n\t"
5608 "TWI $dst\n\t"
5609 "ISYNC" %}
5610 size(12);
5611 ins_encode( enc_ld_ac(dst, mem) );
5612 ins_pipe(pipe_class_memory);
5613 %}
5614
5615 // LoadP + CastP2L
5616 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5617 match(Set dst (CastP2X (LoadP mem)));
5618 predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5619 ins_cost(MEMORY_REF_COST);
5620
5621 format %{ "LD $dst, $mem \t// ptr + p2x" %}
5622 size(4);
5623 ins_encode( enc_ld(dst, mem) );
5624 ins_pipe(pipe_class_memory);
5625 %}
5626
5627 // Load compressed klass pointer.
5628 instruct loadNKlass(iRegNdst dst, memory mem) %{
5629 match(Set dst (LoadNKlass mem));
5630 ins_cost(MEMORY_REF_COST);
5631
5632 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %}
5633 size(4);
5634 ins_encode( enc_lwz(dst, mem) );
5635 ins_pipe(pipe_class_memory);
5636 %}
5637
5638 // Load Klass Pointer
5639 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5640 match(Set dst (LoadKlass mem));
5641 ins_cost(MEMORY_REF_COST);
5642
5643 format %{ "LD $dst, $mem \t// klass ptr" %}
5644 size(4);
5645 ins_encode( enc_ld(dst, mem) );
5646 ins_pipe(pipe_class_memory);
5647 %}
5648
5649 // Load Float
5650 instruct loadF(regF dst, memory mem) %{
5651 match(Set dst (LoadF mem));
5652 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5653 ins_cost(MEMORY_REF_COST);
5654
5655 format %{ "LFS $dst, $mem" %}
5656 size(4);
5657 ins_encode %{
5658 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5659 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5660 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5661 %}
5662 ins_pipe(pipe_class_memory);
5663 %}
5664
5665 // Load Float acquire.
5666 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5667 match(Set dst (LoadF mem));
5668 effect(TEMP cr0);
5669 ins_cost(3*MEMORY_REF_COST);
5670
5671 format %{ "LFS $dst, $mem \t// acquire\n\t"
5672 "FCMPU cr0, $dst, $dst\n\t"
5673 "BNE cr0, next\n"
5674 "next:\n\t"
5675 "ISYNC" %}
5676 size(16);
5677 ins_encode %{
5678 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5679 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5680 Label next;
5681 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5682 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5683 __ bne(CCR0, next);
5684 __ bind(next);
5685 __ isync();
5686 %}
5687 ins_pipe(pipe_class_memory);
5688 %}
5689
5690 // Load Double - aligned
5691 instruct loadD(regD dst, memory mem) %{
5692 match(Set dst (LoadD mem));
5693 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5694 ins_cost(MEMORY_REF_COST);
5695
5696 format %{ "LFD $dst, $mem" %}
5697 size(4);
5698 ins_encode( enc_lfd(dst, mem) );
5699 ins_pipe(pipe_class_memory);
5700 %}
5701
5702 // Load Double - aligned acquire.
5703 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5704 match(Set dst (LoadD mem));
5705 effect(TEMP cr0);
5706 ins_cost(3*MEMORY_REF_COST);
5707
5708 format %{ "LFD $dst, $mem \t// acquire\n\t"
5709 "FCMPU cr0, $dst, $dst\n\t"
5710 "BNE cr0, next\n"
5711 "next:\n\t"
5712 "ISYNC" %}
5713 size(16);
5714 ins_encode %{
5715 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5716 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5717 Label next;
5718 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5719 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5720 __ bne(CCR0, next);
5721 __ bind(next);
5722 __ isync();
5723 %}
5724 ins_pipe(pipe_class_memory);
5725 %}
5726
5727 // Load Double - UNaligned
5728 instruct loadD_unaligned(regD dst, memory mem) %{
5729 match(Set dst (LoadD_unaligned mem));
5730 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5731 ins_cost(MEMORY_REF_COST);
5732
5733 format %{ "LFD $dst, $mem" %}
5734 size(4);
5735 ins_encode( enc_lfd(dst, mem) );
5736 ins_pipe(pipe_class_memory);
5737 %}
5738
5739 //----------Constants--------------------------------------------------------
5740
5741 // Load MachConstantTableBase: add hi offset to global toc.
5742 // TODO: Handle hidden register r29 in bundler!
5743 instruct loadToc_hi(iRegLdst dst) %{
5744 effect(DEF dst);
5745 ins_cost(DEFAULT_COST);
5746
5747 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %}
5748 size(4);
5749 ins_encode %{
5750 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5751 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5752 %}
5753 ins_pipe(pipe_class_default);
5754 %}
5755
5756 // Load MachConstantTableBase: add lo offset to global toc.
5757 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5758 effect(DEF dst, USE src);
5759 ins_cost(DEFAULT_COST);
5760
5761 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %}
5762 size(4);
5763 ins_encode %{
5764 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5765 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5766 %}
5767 ins_pipe(pipe_class_default);
5768 %}
5769
5770 // Load 16-bit integer constant 0xssss????
5771 instruct loadConI16(iRegIdst dst, immI16 src) %{
5772 match(Set dst src);
5773
5774 format %{ "LI $dst, $src" %}
5775 size(4);
5776 ins_encode %{
5777 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5778 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5779 %}
5780 ins_pipe(pipe_class_default);
5781 %}
5782
5783 // Load integer constant 0x????0000
5784 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5785 match(Set dst src);
5786 ins_cost(DEFAULT_COST);
5787
5788 format %{ "LIS $dst, $src.hi" %}
5789 size(4);
5790 ins_encode %{
5791 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5792 // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5793 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5794 %}
5795 ins_pipe(pipe_class_default);
5796 %}
5797
5798 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5799 // and sign extended), this adds the low 16 bits.
5800 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5801 // no match-rule, false predicate
5802 effect(DEF dst, USE src1, USE src2);
5803 predicate(false);
5804
5805 format %{ "ORI $dst, $src1.hi, $src2.lo" %}
5806 size(4);
5807 ins_encode %{
5808 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5809 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5810 %}
5811 ins_pipe(pipe_class_default);
5812 %}
5813
5814 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5815 match(Set dst src);
5816 ins_cost(DEFAULT_COST*2);
5817
5818 expand %{
5819 // Would like to use $src$$constant.
5820 immI16 srcLo %{ _opnds[1]->constant() %}
5821 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5822 immIhi16 srcHi %{ _opnds[1]->constant() %}
5823 iRegIdst tmpI;
5824 loadConIhi16(tmpI, srcHi);
5825 loadConI32_lo16(dst, tmpI, srcLo);
5826 %}
5827 %}
5828
5829 // No constant pool entries required.
5830 instruct loadConL16(iRegLdst dst, immL16 src) %{
5831 match(Set dst src);
5832
5833 format %{ "LI $dst, $src \t// long" %}
5834 size(4);
5835 ins_encode %{
5836 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5837 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5838 %}
5839 ins_pipe(pipe_class_default);
5840 %}
5841
5842 // Load long constant 0xssssssss????0000
5843 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5844 match(Set dst src);
5845 ins_cost(DEFAULT_COST);
5846
5847 format %{ "LIS $dst, $src.hi \t// long" %}
5848 size(4);
5849 ins_encode %{
5850 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5851 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5852 %}
5853 ins_pipe(pipe_class_default);
5854 %}
5855
5856 // To load a 32 bit constant: merge lower 16 bits into already loaded
5857 // high 16 bits.
5858 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5859 // no match-rule, false predicate
5860 effect(DEF dst, USE src1, USE src2);
5861 predicate(false);
5862
5863 format %{ "ORI $dst, $src1, $src2.lo" %}
5864 size(4);
5865 ins_encode %{
5866 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5867 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5868 %}
5869 ins_pipe(pipe_class_default);
5870 %}
5871
5872 // Load 32-bit long constant
5873 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5874 match(Set dst src);
5875 ins_cost(DEFAULT_COST*2);
5876
5877 expand %{
5878 // Would like to use $src$$constant.
5879 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5880 // srcHi can be 0000 if srcLo sign-extends to a negative number.
5881 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5882 iRegLdst tmpL;
5883 loadConL32hi16(tmpL, srcHi);
5884 loadConL32_lo16(dst, tmpL, srcLo);
5885 %}
5886 %}
5887
5888 // Load long constant 0x????000000000000.
5889 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5890 match(Set dst src);
5891 ins_cost(DEFAULT_COST);
5892
5893 expand %{
5894 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5895 immI shift32 %{ 32 %}
5896 iRegLdst tmpL;
5897 loadConL32hi16(tmpL, srcHi);
5898 lshiftL_regL_immI(dst, tmpL, shift32);
5899 %}
5900 %}
5901
5902 // Expand node for constant pool load: small offset.
5903 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5904 effect(DEF dst, USE src, USE toc);
5905 ins_cost(MEMORY_REF_COST);
5906
5907 ins_num_consts(1);
5908 // Needed so that CallDynamicJavaDirect can compute the address of this
5909 // instruction for relocation.
5910 ins_field_cbuf_insts_offset(int);
5911
5912 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %}
5913 size(4);
5914 ins_encode( enc_load_long_constL(dst, src, toc) );
5915 ins_pipe(pipe_class_memory);
5916 %}
5917
5918 // Expand node for constant pool load: large offset.
5919 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5920 effect(DEF dst, USE src, USE toc);
5921 predicate(false);
5922
5923 ins_num_consts(1);
5924 ins_field_const_toc_offset(int);
5925 // Needed so that CallDynamicJavaDirect can compute the address of this
5926 // instruction for relocation.
5927 ins_field_cbuf_insts_offset(int);
5928
5929 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5930 size(4);
5931 ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5932 ins_pipe(pipe_class_default);
5933 %}
5934
5935 // Expand node for constant pool load: large offset.
5936 // No constant pool entries required.
5937 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5938 effect(DEF dst, USE src, USE base);
5939 predicate(false);
5940
5941 ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5942
5943 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %}
5944 size(4);
5945 ins_encode %{
5946 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5947 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5948 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5949 %}
5950 ins_pipe(pipe_class_memory);
5951 %}
5952
5953 // Load long constant from constant table. Expand in case of
5954 // offset > 16 bit is needed.
5955 // Adlc adds toc node MachConstantTableBase.
5956 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5957 match(Set dst src);
5958 ins_cost(MEMORY_REF_COST);
5959
5960 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5961 // We can not inline the enc_class for the expand as that does not support constanttablebase.
5962 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5963 %}
5964
5965 // Load NULL as compressed oop.
5966 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5967 match(Set dst src);
5968 ins_cost(DEFAULT_COST);
5969
5970 format %{ "LI $dst, $src \t// compressed ptr" %}
5971 size(4);
5972 ins_encode %{
5973 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5974 __ li($dst$$Register, 0);
5975 %}
5976 ins_pipe(pipe_class_default);
5977 %}
5978
5979 // Load hi part of compressed oop constant.
5980 instruct loadConN_hi(iRegNdst dst, immN src) %{
5981 effect(DEF dst, USE src);
5982 ins_cost(DEFAULT_COST);
5983
5984 format %{ "LIS $dst, $src \t// narrow oop hi" %}
5985 size(4);
5986 ins_encode %{
5987 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5988 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5989 %}
5990 ins_pipe(pipe_class_default);
5991 %}
5992
5993 // Add lo part of compressed oop constant to already loaded hi part.
5994 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5995 effect(DEF dst, USE src1, USE src2);
5996 ins_cost(DEFAULT_COST);
5997
5998 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %}
5999 size(4);
6000 ins_encode %{
6001 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6002 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6003 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
6004 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6005 __ relocate(rspec, 1);
6006 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
6007 %}
6008 ins_pipe(pipe_class_default);
6009 %}
6010
6011 // Needed to postalloc expand loadConN: ConN is loaded as ConI
6012 // leaving the upper 32 bits with sign-extension bits.
6013 // This clears these bits: dst = src & 0xFFFFFFFF.
6014 // TODO: Eventually call this maskN_regN_FFFFFFFF.
6015 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
6016 effect(DEF dst, USE src);
6017 predicate(false);
6018
6019 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask
6020 size(4);
6021 ins_encode %{
6022 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6023 __ clrldi($dst$$Register, $src$$Register, 0x20);
6024 %}
6025 ins_pipe(pipe_class_default);
6026 %}
6027
6028 // Optimize DecodeN for disjoint base.
6029 // Load base of compressed oops into a register
6030 instruct loadBase(iRegLdst dst) %{
6031 effect(DEF dst);
6032
6033 format %{ "LoadConst $dst, heapbase" %}
6034 ins_encode %{
6035 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6036 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
6037 %}
6038 ins_pipe(pipe_class_default);
6039 %}
6040
6041 // Loading ConN must be postalloc expanded so that edges between
6042 // the nodes are safe. They may not interfere with a safepoint.
6043 // GL TODO: This needs three instructions: better put this into the constant pool.
6044 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6045 match(Set dst src);
6046 ins_cost(DEFAULT_COST*2);
6047
6048 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6049 postalloc_expand %{
6050 MachNode *m1 = new loadConN_hiNode();
6051 MachNode *m2 = new loadConN_loNode();
6052 MachNode *m3 = new clearMs32bNode();
6053 m1->add_req(NULL);
6054 m2->add_req(NULL, m1);
6055 m3->add_req(NULL, m2);
6056 m1->_opnds[0] = op_dst;
6057 m1->_opnds[1] = op_src;
6058 m2->_opnds[0] = op_dst;
6059 m2->_opnds[1] = op_dst;
6060 m2->_opnds[2] = op_src;
6061 m3->_opnds[0] = op_dst;
6062 m3->_opnds[1] = op_dst;
6063 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6064 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6065 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6066 nodes->push(m1);
6067 nodes->push(m2);
6068 nodes->push(m3);
6069 %}
6070 %}
6071
6072 // We have seen a safepoint between the hi and lo parts, and this node was handled
6073 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6074 // not a narrow oop.
6075 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6076 match(Set dst src);
6077 effect(DEF dst, USE src);
6078 ins_cost(DEFAULT_COST);
6079
6080 format %{ "LIS $dst, $src \t// narrow klass hi" %}
6081 size(4);
6082 ins_encode %{
6083 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6084 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6085 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6086 %}
6087 ins_pipe(pipe_class_default);
6088 %}
6089
6090 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6091 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6092 match(Set dst src1);
6093 effect(TEMP src2);
6094 ins_cost(DEFAULT_COST);
6095
6096 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask
6097 size(4);
6098 ins_encode %{
6099 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6100 __ clrldi($dst$$Register, $src2$$Register, 0x20);
6101 %}
6102 ins_pipe(pipe_class_default);
6103 %}
6104
6105 // This needs a match rule so that build_oop_map knows this is
6106 // not a narrow oop.
6107 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6108 match(Set dst src1);
6109 effect(TEMP src2);
6110 ins_cost(DEFAULT_COST);
6111
6112 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %}
6113 size(4);
6114 ins_encode %{
6115 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6116 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6117 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6118 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6119 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6120
6121 __ relocate(rspec, 1);
6122 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6123 %}
6124 ins_pipe(pipe_class_default);
6125 %}
6126
6127 // Loading ConNKlass must be postalloc expanded so that edges between
6128 // the nodes are safe. They may not interfere with a safepoint.
6129 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6130 match(Set dst src);
6131 ins_cost(DEFAULT_COST*2);
6132
6133 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask
6134 postalloc_expand %{
6135 // Load high bits into register. Sign extended.
6136 MachNode *m1 = new loadConNKlass_hiNode();
6137 m1->add_req(NULL);
6138 m1->_opnds[0] = op_dst;
6139 m1->_opnds[1] = op_src;
6140 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6141 nodes->push(m1);
6142
6143 MachNode *m2 = m1;
6144 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6145 // Value might be 1-extended. Mask out these bits.
6146 m2 = new loadConNKlass_maskNode();
6147 m2->add_req(NULL, m1);
6148 m2->_opnds[0] = op_dst;
6149 m2->_opnds[1] = op_src;
6150 m2->_opnds[2] = op_dst;
6151 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6152 nodes->push(m2);
6153 }
6154
6155 MachNode *m3 = new loadConNKlass_loNode();
6156 m3->add_req(NULL, m2);
6157 m3->_opnds[0] = op_dst;
6158 m3->_opnds[1] = op_src;
6159 m3->_opnds[2] = op_dst;
6160 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6161 nodes->push(m3);
6162 %}
6163 %}
6164
6165 // 0x1 is used in object initialization (initial object header).
6166 // No constant pool entries required.
6167 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6168 match(Set dst src);
6169
6170 format %{ "LI $dst, $src \t// ptr" %}
6171 size(4);
6172 ins_encode %{
6173 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6174 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6175 %}
6176 ins_pipe(pipe_class_default);
6177 %}
6178
6179 // Expand node for constant pool load: small offset.
6180 // The match rule is needed to generate the correct bottom_type(),
6181 // however this node should never match. The use of predicate is not
6182 // possible since ADLC forbids predicates for chain rules. The higher
6183 // costs do not prevent matching in this case. For that reason the
6184 // operand immP_NM with predicate(false) is used.
6185 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6186 match(Set dst src);
6187 effect(TEMP toc);
6188
6189 ins_num_consts(1);
6190
6191 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %}
6192 size(4);
6193 ins_encode( enc_load_long_constP(dst, src, toc) );
6194 ins_pipe(pipe_class_memory);
6195 %}
6196
6197 // Expand node for constant pool load: large offset.
6198 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6199 effect(DEF dst, USE src, USE toc);
6200 predicate(false);
6201
6202 ins_num_consts(1);
6203 ins_field_const_toc_offset(int);
6204
6205 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6206 size(4);
6207 ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6208 ins_pipe(pipe_class_default);
6209 %}
6210
6211 // Expand node for constant pool load: large offset.
6212 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6213 match(Set dst src);
6214 effect(TEMP base);
6215
6216 ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6217
6218 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6219 size(4);
6220 ins_encode %{
6221 // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6222 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6223 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6224 %}
6225 ins_pipe(pipe_class_memory);
6226 %}
6227
6228 // Load pointer constant from constant table. Expand in case an
6229 // offset > 16 bit is needed.
6230 // Adlc adds toc node MachConstantTableBase.
6231 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6232 match(Set dst src);
6233 ins_cost(MEMORY_REF_COST);
6234
6235 // This rule does not use "expand" because then
6236 // the result type is not known to be an Oop. An ADLC
6237 // enhancement will be needed to make that work - not worth it!
6238
6239 // If this instruction rematerializes, it prolongs the live range
6240 // of the toc node, causing illegal graphs.
6241 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6242 ins_cannot_rematerialize(true);
6243
6244 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %}
6245 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6246 %}
6247
6248 // Expand node for constant pool load: small offset.
6249 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6250 effect(DEF dst, USE src, USE toc);
6251 ins_cost(MEMORY_REF_COST);
6252
6253 ins_num_consts(1);
6254
6255 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %}
6256 size(4);
6257 ins_encode %{
6258 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6259 address float_address = __ float_constant($src$$constant);
6260 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6261 %}
6262 ins_pipe(pipe_class_memory);
6263 %}
6264
6265 // Expand node for constant pool load: large offset.
6266 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6267 effect(DEF dst, USE src, USE toc);
6268 ins_cost(MEMORY_REF_COST);
6269
6270 ins_num_consts(1);
6271
6272 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6273 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6274 "ADDIS $toc, $toc, -offset_hi"%}
6275 size(12);
6276 ins_encode %{
6277 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6278 FloatRegister Rdst = $dst$$FloatRegister;
6279 Register Rtoc = $toc$$Register;
6280 address float_address = __ float_constant($src$$constant);
6281 int offset = __ offset_to_method_toc(float_address);
6282 int hi = (offset + (1<<15))>>16;
6283 int lo = offset - hi * (1<<16);
6284
6285 __ addis(Rtoc, Rtoc, hi);
6286 __ lfs(Rdst, lo, Rtoc);
6287 __ addis(Rtoc, Rtoc, -hi);
6288 %}
6289 ins_pipe(pipe_class_memory);
6290 %}
6291
6292 // Adlc adds toc node MachConstantTableBase.
6293 instruct loadConF_Ex(regF dst, immF src) %{
6294 match(Set dst src);
6295 ins_cost(MEMORY_REF_COST);
6296
6297 // See loadConP.
6298 ins_cannot_rematerialize(true);
6299
6300 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6301 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6302 %}
6303
6304 // Expand node for constant pool load: small offset.
6305 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6306 effect(DEF dst, USE src, USE toc);
6307 ins_cost(MEMORY_REF_COST);
6308
6309 ins_num_consts(1);
6310
6311 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %}
6312 size(4);
6313 ins_encode %{
6314 // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6315 int offset = __ offset_to_method_toc(__ double_constant($src$$constant));
6316 __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6317 %}
6318 ins_pipe(pipe_class_memory);
6319 %}
6320
6321 // Expand node for constant pool load: large offset.
6322 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6323 effect(DEF dst, USE src, USE toc);
6324 ins_cost(MEMORY_REF_COST);
6325
6326 ins_num_consts(1);
6327
6328 format %{ "ADDIS $toc, $toc, offset_hi\n\t"
6329 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6330 "ADDIS $toc, $toc, -offset_hi" %}
6331 size(12);
6332 ins_encode %{
6333 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6334 FloatRegister Rdst = $dst$$FloatRegister;
6335 Register Rtoc = $toc$$Register;
6336 address float_address = __ double_constant($src$$constant);
6337 int offset = __ offset_to_method_toc(float_address);
6338 int hi = (offset + (1<<15))>>16;
6339 int lo = offset - hi * (1<<16);
6340
6341 __ addis(Rtoc, Rtoc, hi);
6342 __ lfd(Rdst, lo, Rtoc);
6343 __ addis(Rtoc, Rtoc, -hi);
6344 %}
6345 ins_pipe(pipe_class_memory);
6346 %}
6347
6348 // Adlc adds toc node MachConstantTableBase.
6349 instruct loadConD_Ex(regD dst, immD src) %{
6350 match(Set dst src);
6351 ins_cost(MEMORY_REF_COST);
6352
6353 // See loadConP.
6354 ins_cannot_rematerialize(true);
6355
6356 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6357 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6358 %}
6359
6360 // Prefetch instructions.
6361 // Must be safe to execute with invalid address (cannot fault).
6362
6363 // Special prefetch versions which use the dcbz instruction.
6364 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6365 match(PrefetchAllocation (AddP mem src));
6366 predicate(AllocatePrefetchStyle == 3);
6367 ins_cost(MEMORY_REF_COST);
6368
6369 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6370 size(4);
6371 ins_encode %{
6372 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6373 __ dcbz($src$$Register, $mem$$base$$Register);
6374 %}
6375 ins_pipe(pipe_class_memory);
6376 %}
6377
6378 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6379 match(PrefetchAllocation mem);
6380 predicate(AllocatePrefetchStyle == 3);
6381 ins_cost(MEMORY_REF_COST);
6382
6383 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6384 size(4);
6385 ins_encode %{
6386 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6387 __ dcbz($mem$$base$$Register);
6388 %}
6389 ins_pipe(pipe_class_memory);
6390 %}
6391
6392 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6393 match(PrefetchAllocation (AddP mem src));
6394 predicate(AllocatePrefetchStyle != 3);
6395 ins_cost(MEMORY_REF_COST);
6396
6397 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6398 size(4);
6399 ins_encode %{
6400 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6401 __ dcbtst($src$$Register, $mem$$base$$Register);
6402 %}
6403 ins_pipe(pipe_class_memory);
6404 %}
6405
6406 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6407 match(PrefetchAllocation mem);
6408 predicate(AllocatePrefetchStyle != 3);
6409 ins_cost(MEMORY_REF_COST);
6410
6411 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6412 size(4);
6413 ins_encode %{
6414 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6415 __ dcbtst($mem$$base$$Register);
6416 %}
6417 ins_pipe(pipe_class_memory);
6418 %}
6419
6420 //----------Store Instructions-------------------------------------------------
6421
6422 // Store Byte
6423 instruct storeB(memory mem, iRegIsrc src) %{
6424 match(Set mem (StoreB mem src));
6425 ins_cost(MEMORY_REF_COST);
6426
6427 format %{ "STB $src, $mem \t// byte" %}
6428 size(4);
6429 ins_encode %{
6430 // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6431 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6432 __ stb($src$$Register, Idisp, $mem$$base$$Register);
6433 %}
6434 ins_pipe(pipe_class_memory);
6435 %}
6436
6437 // Store Char/Short
6438 instruct storeC(memory mem, iRegIsrc src) %{
6439 match(Set mem (StoreC mem src));
6440 ins_cost(MEMORY_REF_COST);
6441
6442 format %{ "STH $src, $mem \t// short" %}
6443 size(4);
6444 ins_encode %{
6445 // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6446 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6447 __ sth($src$$Register, Idisp, $mem$$base$$Register);
6448 %}
6449 ins_pipe(pipe_class_memory);
6450 %}
6451
6452 // Store Integer
6453 instruct storeI(memory mem, iRegIsrc src) %{
6454 match(Set mem (StoreI mem src));
6455 ins_cost(MEMORY_REF_COST);
6456
6457 format %{ "STW $src, $mem" %}
6458 size(4);
6459 ins_encode( enc_stw(src, mem) );
6460 ins_pipe(pipe_class_memory);
6461 %}
6462
6463 // ConvL2I + StoreI.
6464 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6465 match(Set mem (StoreI mem (ConvL2I src)));
6466 ins_cost(MEMORY_REF_COST);
6467
6468 format %{ "STW l2i($src), $mem" %}
6469 size(4);
6470 ins_encode( enc_stw(src, mem) );
6471 ins_pipe(pipe_class_memory);
6472 %}
6473
6474 // Store Long
6475 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6476 match(Set mem (StoreL mem src));
6477 ins_cost(MEMORY_REF_COST);
6478
6479 format %{ "STD $src, $mem \t// long" %}
6480 size(4);
6481 ins_encode( enc_std(src, mem) );
6482 ins_pipe(pipe_class_memory);
6483 %}
6484
6485 // Store super word nodes.
6486
6487 // Store Aligned Packed Byte long register to memory
6488 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6489 predicate(n->as_StoreVector()->memory_size() == 8);
6490 match(Set mem (StoreVector mem src));
6491 ins_cost(MEMORY_REF_COST);
6492
6493 format %{ "STD $mem, $src \t// packed8B" %}
6494 size(4);
6495 ins_encode( enc_std(src, mem) );
6496 ins_pipe(pipe_class_memory);
6497 %}
6498
6499 // Store Compressed Oop
6500 instruct storeN(memory dst, iRegN_P2N src) %{
6501 match(Set dst (StoreN dst src));
6502 ins_cost(MEMORY_REF_COST);
6503
6504 format %{ "STW $src, $dst \t// compressed oop" %}
6505 size(4);
6506 ins_encode( enc_stw(src, dst) );
6507 ins_pipe(pipe_class_memory);
6508 %}
6509
6510 // Store Compressed KLass
6511 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6512 match(Set dst (StoreNKlass dst src));
6513 ins_cost(MEMORY_REF_COST);
6514
6515 format %{ "STW $src, $dst \t// compressed klass" %}
6516 size(4);
6517 ins_encode( enc_stw(src, dst) );
6518 ins_pipe(pipe_class_memory);
6519 %}
6520
6521 // Store Pointer
6522 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6523 match(Set dst (StoreP dst src));
6524 ins_cost(MEMORY_REF_COST);
6525
6526 format %{ "STD $src, $dst \t// ptr" %}
6527 size(4);
6528 ins_encode( enc_std(src, dst) );
6529 ins_pipe(pipe_class_memory);
6530 %}
6531
6532 // Store Float
6533 instruct storeF(memory mem, regF src) %{
6534 match(Set mem (StoreF mem src));
6535 ins_cost(MEMORY_REF_COST);
6536
6537 format %{ "STFS $src, $mem" %}
6538 size(4);
6539 ins_encode( enc_stfs(src, mem) );
6540 ins_pipe(pipe_class_memory);
6541 %}
6542
6543 // Store Double
6544 instruct storeD(memory mem, regD src) %{
6545 match(Set mem (StoreD mem src));
6546 ins_cost(MEMORY_REF_COST);
6547
6548 format %{ "STFD $src, $mem" %}
6549 size(4);
6550 ins_encode( enc_stfd(src, mem) );
6551 ins_pipe(pipe_class_memory);
6552 %}
6553
6554 //----------Store Instructions With Zeros--------------------------------------
6555
6556 // Card-mark for CMS garbage collection.
6557 // This cardmark does an optimization so that it must not always
6558 // do a releasing store. For this, it gets the address of
6559 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6560 // (Using releaseFieldAddr in the match rule is a hack.)
6561 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6562 match(Set mem (StoreCM mem releaseFieldAddr));
6563 effect(TEMP crx);
6564 predicate(false);
6565 ins_cost(MEMORY_REF_COST);
6566
6567 // See loadConP.
6568 ins_cannot_rematerialize(true);
6569
6570 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6571 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6572 ins_pipe(pipe_class_memory);
6573 %}
6574
6575 // Card-mark for CMS garbage collection.
6576 // This cardmark does an optimization so that it must not always
6577 // do a releasing store. For this, it needs the constant address of
6578 // CMSCollectorCardTableModRefBSExt::_requires_release.
6579 // This constant address is split off here by expand so we can use
6580 // adlc / matcher functionality to load it from the constant section.
6581 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6582 match(Set mem (StoreCM mem zero));
6583 predicate(UseConcMarkSweepGC);
6584
6585 expand %{
6586 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6587 iRegLdst releaseFieldAddress;
6588 flagsReg crx;
6589 loadConL_Ex(releaseFieldAddress, baseImm);
6590 storeCM_CMS(mem, releaseFieldAddress, crx);
6591 %}
6592 %}
6593
6594 instruct storeCM_G1(memory mem, immI_0 zero) %{
6595 match(Set mem (StoreCM mem zero));
6596 predicate(UseG1GC);
6597 ins_cost(MEMORY_REF_COST);
6598
6599 ins_cannot_rematerialize(true);
6600
6601 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %}
6602 size(8);
6603 ins_encode %{
6604 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6605 __ li(R0, 0);
6606 //__ release(); // G1: oops are allowed to get visible after dirty marking
6607 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6608 __ stb(R0, $mem$$disp, $mem$$base$$Register);
6609 %}
6610 ins_pipe(pipe_class_memory);
6611 %}
6612
6613 // Convert oop pointer into compressed form.
6614
6615 // Nodes for postalloc expand.
6616
6617 // Shift node for expand.
6618 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6619 // The match rule is needed to make it a 'MachTypeNode'!
6620 match(Set dst (EncodeP src));
6621 predicate(false);
6622
6623 format %{ "SRDI $dst, $src, 3 \t// encode" %}
6624 size(4);
6625 ins_encode %{
6626 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6627 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6628 %}
6629 ins_pipe(pipe_class_default);
6630 %}
6631
6632 // Add node for expand.
6633 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6634 // The match rule is needed to make it a 'MachTypeNode'!
6635 match(Set dst (EncodeP src));
6636 predicate(false);
6637
6638 format %{ "SUB $dst, $src, oop_base \t// encode" %}
6639 ins_encode %{
6640 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6641 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6642 %}
6643 ins_pipe(pipe_class_default);
6644 %}
6645
6646 // Conditional sub base.
6647 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6648 // The match rule is needed to make it a 'MachTypeNode'!
6649 match(Set dst (EncodeP (Binary crx src1)));
6650 predicate(false);
6651
6652 format %{ "BEQ $crx, done\n\t"
6653 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6654 "done:" %}
6655 ins_encode %{
6656 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6657 Label done;
6658 __ beq($crx$$CondRegister, done);
6659 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6660 __ bind(done);
6661 %}
6662 ins_pipe(pipe_class_default);
6663 %}
6664
6665 // Power 7 can use isel instruction
6666 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6667 // The match rule is needed to make it a 'MachTypeNode'!
6668 match(Set dst (EncodeP (Binary crx src1)));
6669 predicate(false);
6670
6671 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6672 size(4);
6673 ins_encode %{
6674 // This is a Power7 instruction for which no machine description exists.
6675 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6676 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6677 %}
6678 ins_pipe(pipe_class_default);
6679 %}
6680
6681 // Disjoint narrow oop base.
6682 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6683 match(Set dst (EncodeP src));
6684 predicate(Universe::narrow_oop_base_disjoint());
6685
6686 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
6687 size(4);
6688 ins_encode %{
6689 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6690 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6691 %}
6692 ins_pipe(pipe_class_default);
6693 %}
6694
6695 // shift != 0, base != 0
6696 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6697 match(Set dst (EncodeP src));
6698 effect(TEMP crx);
6699 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6700 Universe::narrow_oop_shift() != 0 &&
6701 Universe::narrow_oop_base_overlaps());
6702
6703 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6704 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6705 %}
6706
6707 // shift != 0, base != 0
6708 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6709 match(Set dst (EncodeP src));
6710 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6711 Universe::narrow_oop_shift() != 0 &&
6712 Universe::narrow_oop_base_overlaps());
6713
6714 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6715 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6716 %}
6717
6718 // shift != 0, base == 0
6719 // TODO: This is the same as encodeP_shift. Merge!
6720 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6721 match(Set dst (EncodeP src));
6722 predicate(Universe::narrow_oop_shift() != 0 &&
6723 Universe::narrow_oop_base() ==0);
6724
6725 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %}
6726 size(4);
6727 ins_encode %{
6728 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6729 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6730 %}
6731 ins_pipe(pipe_class_default);
6732 %}
6733
6734 // Compressed OOPs with narrow_oop_shift == 0.
6735 // shift == 0, base == 0
6736 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6737 match(Set dst (EncodeP src));
6738 predicate(Universe::narrow_oop_shift() == 0);
6739
6740 format %{ "MR $dst, $src \t// Ptr->Narrow" %}
6741 // variable size, 0 or 4.
6742 ins_encode %{
6743 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6744 __ mr_if_needed($dst$$Register, $src$$Register);
6745 %}
6746 ins_pipe(pipe_class_default);
6747 %}
6748
6749 // Decode nodes.
6750
6751 // Shift node for expand.
6752 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6753 // The match rule is needed to make it a 'MachTypeNode'!
6754 match(Set dst (DecodeN src));
6755 predicate(false);
6756
6757 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %}
6758 size(4);
6759 ins_encode %{
6760 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6761 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6762 %}
6763 ins_pipe(pipe_class_default);
6764 %}
6765
6766 // Add node for expand.
6767 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6768 // The match rule is needed to make it a 'MachTypeNode'!
6769 match(Set dst (DecodeN src));
6770 predicate(false);
6771
6772 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %}
6773 ins_encode %{
6774 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6775 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6776 %}
6777 ins_pipe(pipe_class_default);
6778 %}
6779
6780 // conditianal add base for expand
6781 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6782 // The match rule is needed to make it a 'MachTypeNode'!
6783 // NOTICE that the rule is nonsense - we just have to make sure that:
6784 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6785 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6786 match(Set dst (DecodeN (Binary crx src)));
6787 predicate(false);
6788
6789 format %{ "BEQ $crx, done\n\t"
6790 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6791 "done:" %}
6792 ins_encode %{
6793 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6794 Label done;
6795 __ beq($crx$$CondRegister, done);
6796 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6797 __ bind(done);
6798 %}
6799 ins_pipe(pipe_class_default);
6800 %}
6801
6802 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6803 // The match rule is needed to make it a 'MachTypeNode'!
6804 // NOTICE that the rule is nonsense - we just have to make sure that:
6805 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6806 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6807 match(Set dst (DecodeN (Binary crx src1)));
6808 predicate(false);
6809
6810 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6811 size(4);
6812 ins_encode %{
6813 // This is a Power7 instruction for which no machine description exists.
6814 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6815 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6816 %}
6817 ins_pipe(pipe_class_default);
6818 %}
6819
6820 // shift != 0, base != 0
6821 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6822 match(Set dst (DecodeN src));
6823 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6824 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6825 Universe::narrow_oop_shift() != 0 &&
6826 Universe::narrow_oop_base() != 0);
6827 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6828 effect(TEMP crx);
6829
6830 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6831 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6832 %}
6833
6834 // shift != 0, base == 0
6835 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6836 match(Set dst (DecodeN src));
6837 predicate(Universe::narrow_oop_shift() != 0 &&
6838 Universe::narrow_oop_base() == 0);
6839
6840 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %}
6841 size(4);
6842 ins_encode %{
6843 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6844 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6845 %}
6846 ins_pipe(pipe_class_default);
6847 %}
6848
6849 // Optimize DecodeN for disjoint base.
6850 // Shift narrow oop and or it into register that already contains the heap base.
6851 // Base == dst must hold, and is assured by construction in postaloc_expand.
6852 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6853 match(Set dst (DecodeN src));
6854 effect(TEMP base);
6855 predicate(false);
6856
6857 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6858 size(4);
6859 ins_encode %{
6860 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6861 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6862 %}
6863 ins_pipe(pipe_class_default);
6864 %}
6865
6866 // Optimize DecodeN for disjoint base.
6867 // This node requires only one cycle on the critical path.
6868 // We must postalloc_expand as we can not express use_def effects where
6869 // the used register is L and the def'ed register P.
6870 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6871 match(Set dst (DecodeN src));
6872 effect(TEMP_DEF dst);
6873 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6874 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6875 Universe::narrow_oop_base_disjoint());
6876 ins_cost(DEFAULT_COST);
6877
6878 format %{ "MOV $dst, heapbase \t\n"
6879 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6880 postalloc_expand %{
6881 loadBaseNode *n1 = new loadBaseNode();
6882 n1->add_req(NULL);
6883 n1->_opnds[0] = op_dst;
6884
6885 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6886 n2->add_req(n_region, n_src, n1);
6887 n2->_opnds[0] = op_dst;
6888 n2->_opnds[1] = op_src;
6889 n2->_opnds[2] = op_dst;
6890 n2->_bottom_type = _bottom_type;
6891
6892 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6893 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6894
6895 nodes->push(n1);
6896 nodes->push(n2);
6897 %}
6898 %}
6899
6900 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6901 match(Set dst (DecodeN src));
6902 effect(TEMP_DEF dst, TEMP crx);
6903 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6904 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6905 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6906 ins_cost(3 * DEFAULT_COST);
6907
6908 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %}
6909 postalloc_expand %{
6910 loadBaseNode *n1 = new loadBaseNode();
6911 n1->add_req(NULL);
6912 n1->_opnds[0] = op_dst;
6913
6914 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node();
6915 n_compare->add_req(n_region, n_src);
6916 n_compare->_opnds[0] = op_crx;
6917 n_compare->_opnds[1] = op_src;
6918 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6919
6920 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6921 n2->add_req(n_region, n_src, n1);
6922 n2->_opnds[0] = op_dst;
6923 n2->_opnds[1] = op_src;
6924 n2->_opnds[2] = op_dst;
6925 n2->_bottom_type = _bottom_type;
6926
6927 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6928 n_cond_set->add_req(n_region, n_compare, n2);
6929 n_cond_set->_opnds[0] = op_dst;
6930 n_cond_set->_opnds[1] = op_crx;
6931 n_cond_set->_opnds[2] = op_dst;
6932 n_cond_set->_bottom_type = _bottom_type;
6933
6934 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6935 ra_->set_oop(n_cond_set, true);
6936
6937 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6938 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6939 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6940 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6941
6942 nodes->push(n1);
6943 nodes->push(n_compare);
6944 nodes->push(n2);
6945 nodes->push(n_cond_set);
6946 %}
6947 %}
6948
6949 // src != 0, shift != 0, base != 0
6950 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6951 match(Set dst (DecodeN src));
6952 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6953 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6954 Universe::narrow_oop_shift() != 0 &&
6955 Universe::narrow_oop_base() != 0);
6956 ins_cost(2 * DEFAULT_COST);
6957
6958 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6959 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6960 %}
6961
6962 // Compressed OOPs with narrow_oop_shift == 0.
6963 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6964 match(Set dst (DecodeN src));
6965 predicate(Universe::narrow_oop_shift() == 0);
6966 ins_cost(DEFAULT_COST);
6967
6968 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %}
6969 // variable size, 0 or 4.
6970 ins_encode %{
6971 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6972 __ mr_if_needed($dst$$Register, $src$$Register);
6973 %}
6974 ins_pipe(pipe_class_default);
6975 %}
6976
6977 // Convert compressed oop into int for vectors alignment masking.
6978 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6979 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6980 predicate(Universe::narrow_oop_shift() == 0);
6981 ins_cost(DEFAULT_COST);
6982
6983 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %}
6984 // variable size, 0 or 4.
6985 ins_encode %{
6986 // TODO: PPC port $archOpcode(ppc64Opcode_or);
6987 __ mr_if_needed($dst$$Register, $src$$Register);
6988 %}
6989 ins_pipe(pipe_class_default);
6990 %}
6991
6992 // Convert klass pointer into compressed form.
6993
6994 // Nodes for postalloc expand.
6995
6996 // Shift node for expand.
6997 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6998 // The match rule is needed to make it a 'MachTypeNode'!
6999 match(Set dst (EncodePKlass src));
7000 predicate(false);
7001
7002 format %{ "SRDI $dst, $src, 3 \t// encode" %}
7003 size(4);
7004 ins_encode %{
7005 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7006 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7007 %}
7008 ins_pipe(pipe_class_default);
7009 %}
7010
7011 // Add node for expand.
7012 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7013 // The match rule is needed to make it a 'MachTypeNode'!
7014 match(Set dst (EncodePKlass (Binary base src)));
7015 predicate(false);
7016
7017 format %{ "SUB $dst, $base, $src \t// encode" %}
7018 size(4);
7019 ins_encode %{
7020 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7021 __ subf($dst$$Register, $base$$Register, $src$$Register);
7022 %}
7023 ins_pipe(pipe_class_default);
7024 %}
7025
7026 // Disjoint narrow oop base.
7027 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7028 match(Set dst (EncodePKlass src));
7029 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7030
7031 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %}
7032 size(4);
7033 ins_encode %{
7034 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7035 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7036 %}
7037 ins_pipe(pipe_class_default);
7038 %}
7039
7040 // shift != 0, base != 0
7041 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7042 match(Set dst (EncodePKlass (Binary base src)));
7043 predicate(false);
7044
7045 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7046 postalloc_expand %{
7047 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7048 n1->add_req(n_region, n_base, n_src);
7049 n1->_opnds[0] = op_dst;
7050 n1->_opnds[1] = op_base;
7051 n1->_opnds[2] = op_src;
7052 n1->_bottom_type = _bottom_type;
7053
7054 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7055 n2->add_req(n_region, n1);
7056 n2->_opnds[0] = op_dst;
7057 n2->_opnds[1] = op_dst;
7058 n2->_bottom_type = _bottom_type;
7059 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7060 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7061
7062 nodes->push(n1);
7063 nodes->push(n2);
7064 %}
7065 %}
7066
7067 // shift != 0, base != 0
7068 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7069 match(Set dst (EncodePKlass src));
7070 //predicate(Universe::narrow_klass_shift() != 0 &&
7071 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7072
7073 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7074 ins_cost(DEFAULT_COST*2); // Don't count constant.
7075 expand %{
7076 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7077 iRegLdst base;
7078 loadConL_Ex(base, baseImm);
7079 encodePKlass_not_null_Ex(dst, base, src);
7080 %}
7081 %}
7082
7083 // Decode nodes.
7084
7085 // Shift node for expand.
7086 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7087 // The match rule is needed to make it a 'MachTypeNode'!
7088 match(Set dst (DecodeNKlass src));
7089 predicate(false);
7090
7091 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %}
7092 size(4);
7093 ins_encode %{
7094 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7095 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7096 %}
7097 ins_pipe(pipe_class_default);
7098 %}
7099
7100 // Add node for expand.
7101
7102 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7103 // The match rule is needed to make it a 'MachTypeNode'!
7104 match(Set dst (DecodeNKlass (Binary base src)));
7105 predicate(false);
7106
7107 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7108 size(4);
7109 ins_encode %{
7110 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7111 __ add($dst$$Register, $base$$Register, $src$$Register);
7112 %}
7113 ins_pipe(pipe_class_default);
7114 %}
7115
7116 // src != 0, shift != 0, base != 0
7117 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7118 match(Set dst (DecodeNKlass (Binary base src)));
7119 //effect(kill src); // We need a register for the immediate result after shifting.
7120 predicate(false);
7121
7122 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7123 postalloc_expand %{
7124 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7125 n1->add_req(n_region, n_base, n_src);
7126 n1->_opnds[0] = op_dst;
7127 n1->_opnds[1] = op_base;
7128 n1->_opnds[2] = op_src;
7129 n1->_bottom_type = _bottom_type;
7130
7131 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7132 n2->add_req(n_region, n1);
7133 n2->_opnds[0] = op_dst;
7134 n2->_opnds[1] = op_dst;
7135 n2->_bottom_type = _bottom_type;
7136
7137 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7138 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7139
7140 nodes->push(n1);
7141 nodes->push(n2);
7142 %}
7143 %}
7144
7145 // src != 0, shift != 0, base != 0
7146 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7147 match(Set dst (DecodeNKlass src));
7148 // predicate(Universe::narrow_klass_shift() != 0 &&
7149 // Universe::narrow_klass_base() != 0);
7150
7151 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7152
7153 ins_cost(DEFAULT_COST*2); // Don't count constant.
7154 expand %{
7155 // We add first, then we shift. Like this, we can get along with one register less.
7156 // But we have to load the base pre-shifted.
7157 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7158 iRegLdst base;
7159 loadConL_Ex(base, baseImm);
7160 decodeNKlass_notNull_addBase_Ex(dst, base, src);
7161 %}
7162 %}
7163
7164 //----------MemBar Instructions-----------------------------------------------
7165 // Memory barrier flavors
7166
7167 instruct membar_acquire() %{
7168 match(LoadFence);
7169 ins_cost(4*MEMORY_REF_COST);
7170
7171 format %{ "MEMBAR-acquire" %}
7172 size(4);
7173 ins_encode %{
7174 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7175 __ acquire();
7176 %}
7177 ins_pipe(pipe_class_default);
7178 %}
7179
7180 instruct unnecessary_membar_acquire() %{
7181 match(MemBarAcquire);
7182 ins_cost(0);
7183
7184 format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7185 size(0);
7186 ins_encode( /*empty*/ );
7187 ins_pipe(pipe_class_default);
7188 %}
7189
7190 instruct membar_acquire_lock() %{
7191 match(MemBarAcquireLock);
7192 ins_cost(0);
7193
7194 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7195 size(0);
7196 ins_encode( /*empty*/ );
7197 ins_pipe(pipe_class_default);
7198 %}
7199
7200 instruct membar_release() %{
7201 match(MemBarRelease);
7202 match(StoreFence);
7203 ins_cost(4*MEMORY_REF_COST);
7204
7205 format %{ "MEMBAR-release" %}
7206 size(4);
7207 ins_encode %{
7208 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7209 __ release();
7210 %}
7211 ins_pipe(pipe_class_default);
7212 %}
7213
7214 instruct membar_storestore() %{
7215 match(MemBarStoreStore);
7216 ins_cost(4*MEMORY_REF_COST);
7217
7218 format %{ "MEMBAR-store-store" %}
7219 size(4);
7220 ins_encode %{
7221 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7222 __ membar(Assembler::StoreStore);
7223 %}
7224 ins_pipe(pipe_class_default);
7225 %}
7226
7227 instruct membar_release_lock() %{
7228 match(MemBarReleaseLock);
7229 ins_cost(0);
7230
7231 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7232 size(0);
7233 ins_encode( /*empty*/ );
7234 ins_pipe(pipe_class_default);
7235 %}
7236
7237 instruct membar_volatile() %{
7238 match(MemBarVolatile);
7239 ins_cost(4*MEMORY_REF_COST);
7240
7241 format %{ "MEMBAR-volatile" %}
7242 size(4);
7243 ins_encode %{
7244 // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7245 __ fence();
7246 %}
7247 ins_pipe(pipe_class_default);
7248 %}
7249
7250 // This optimization is wrong on PPC. The following pattern is not supported:
7251 // MemBarVolatile
7252 // ^ ^
7253 // | |
7254 // CtrlProj MemProj
7255 // ^ ^
7256 // | |
7257 // | Load
7258 // |
7259 // MemBarVolatile
7260 //
7261 // The first MemBarVolatile could get optimized out! According to
7262 // Vladimir, this pattern can not occur on Oracle platforms.
7263 // However, it does occur on PPC64 (because of membars in
7264 // inline_unsafe_load_store).
7265 //
7266 // Add this node again if we found a good solution for inline_unsafe_load_store().
7267 // Don't forget to look at the implementation of post_store_load_barrier again,
7268 // we did other fixes in that method.
7269 //instruct unnecessary_membar_volatile() %{
7270 // match(MemBarVolatile);
7271 // predicate(Matcher::post_store_load_barrier(n));
7272 // ins_cost(0);
7273 //
7274 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7275 // size(0);
7276 // ins_encode( /*empty*/ );
7277 // ins_pipe(pipe_class_default);
7278 //%}
7279
7280 instruct membar_CPUOrder() %{
7281 match(MemBarCPUOrder);
7282 ins_cost(0);
7283
7284 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7285 size(0);
7286 ins_encode( /*empty*/ );
7287 ins_pipe(pipe_class_default);
7288 %}
7289
7290 //----------Conditional Move---------------------------------------------------
7291
7292 // Cmove using isel.
7293 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7294 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7295 predicate(VM_Version::has_isel());
7296 ins_cost(DEFAULT_COST);
7297
7298 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7299 size(4);
7300 ins_encode %{
7301 // This is a Power7 instruction for which no machine description
7302 // exists. Anyways, the scheduler should be off on Power7.
7303 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7304 int cc = $cmp$$cmpcode;
7305 __ isel($dst$$Register, $crx$$CondRegister,
7306 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7307 %}
7308 ins_pipe(pipe_class_default);
7309 %}
7310
7311 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7312 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7313 predicate(!VM_Version::has_isel());
7314 ins_cost(DEFAULT_COST+BRANCH_COST);
7315
7316 ins_variable_size_depending_on_alignment(true);
7317
7318 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7319 // Worst case is branch + move + stop, no stop without scheduler
7320 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7321 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7322 ins_pipe(pipe_class_default);
7323 %}
7324
7325 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7326 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7327 ins_cost(DEFAULT_COST+BRANCH_COST);
7328
7329 ins_variable_size_depending_on_alignment(true);
7330
7331 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7332 // Worst case is branch + move + stop, no stop without scheduler
7333 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7334 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7335 ins_pipe(pipe_class_default);
7336 %}
7337
7338 // Cmove using isel.
7339 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7340 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7341 predicate(VM_Version::has_isel());
7342 ins_cost(DEFAULT_COST);
7343
7344 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7345 size(4);
7346 ins_encode %{
7347 // This is a Power7 instruction for which no machine description
7348 // exists. Anyways, the scheduler should be off on Power7.
7349 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7350 int cc = $cmp$$cmpcode;
7351 __ isel($dst$$Register, $crx$$CondRegister,
7352 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7353 %}
7354 ins_pipe(pipe_class_default);
7355 %}
7356
7357 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7358 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7359 predicate(!VM_Version::has_isel());
7360 ins_cost(DEFAULT_COST+BRANCH_COST);
7361
7362 ins_variable_size_depending_on_alignment(true);
7363
7364 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7365 // Worst case is branch + move + stop, no stop without scheduler.
7366 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7367 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7368 ins_pipe(pipe_class_default);
7369 %}
7370
7371 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7372 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7373 ins_cost(DEFAULT_COST+BRANCH_COST);
7374
7375 ins_variable_size_depending_on_alignment(true);
7376
7377 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7378 // Worst case is branch + move + stop, no stop without scheduler.
7379 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7380 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7381 ins_pipe(pipe_class_default);
7382 %}
7383
7384 // Cmove using isel.
7385 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7386 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7387 predicate(VM_Version::has_isel());
7388 ins_cost(DEFAULT_COST);
7389
7390 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7391 size(4);
7392 ins_encode %{
7393 // This is a Power7 instruction for which no machine description
7394 // exists. Anyways, the scheduler should be off on Power7.
7395 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7396 int cc = $cmp$$cmpcode;
7397 __ isel($dst$$Register, $crx$$CondRegister,
7398 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7399 %}
7400 ins_pipe(pipe_class_default);
7401 %}
7402
7403 // Conditional move for RegN. Only cmov(reg, reg).
7404 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7405 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7406 predicate(!VM_Version::has_isel());
7407 ins_cost(DEFAULT_COST+BRANCH_COST);
7408
7409 ins_variable_size_depending_on_alignment(true);
7410
7411 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7412 // Worst case is branch + move + stop, no stop without scheduler.
7413 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7414 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7415 ins_pipe(pipe_class_default);
7416 %}
7417
7418 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7419 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7420 ins_cost(DEFAULT_COST+BRANCH_COST);
7421
7422 ins_variable_size_depending_on_alignment(true);
7423
7424 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7425 // Worst case is branch + move + stop, no stop without scheduler.
7426 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7427 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7428 ins_pipe(pipe_class_default);
7429 %}
7430
7431 // Cmove using isel.
7432 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7433 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7434 predicate(VM_Version::has_isel());
7435 ins_cost(DEFAULT_COST);
7436
7437 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7438 size(4);
7439 ins_encode %{
7440 // This is a Power7 instruction for which no machine description
7441 // exists. Anyways, the scheduler should be off on Power7.
7442 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7443 int cc = $cmp$$cmpcode;
7444 __ isel($dst$$Register, $crx$$CondRegister,
7445 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7446 %}
7447 ins_pipe(pipe_class_default);
7448 %}
7449
7450 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7451 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7452 predicate(!VM_Version::has_isel());
7453 ins_cost(DEFAULT_COST+BRANCH_COST);
7454
7455 ins_variable_size_depending_on_alignment(true);
7456
7457 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7458 // Worst case is branch + move + stop, no stop without scheduler.
7459 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7460 ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7461 ins_pipe(pipe_class_default);
7462 %}
7463
7464 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7465 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7466 ins_cost(DEFAULT_COST+BRANCH_COST);
7467
7468 ins_variable_size_depending_on_alignment(true);
7469
7470 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %}
7471 // Worst case is branch + move + stop, no stop without scheduler.
7472 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7473 ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7474 ins_pipe(pipe_class_default);
7475 %}
7476
7477 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7478 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7479 ins_cost(DEFAULT_COST+BRANCH_COST);
7480
7481 ins_variable_size_depending_on_alignment(true);
7482
7483 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7484 // Worst case is branch + move + stop, no stop without scheduler.
7485 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7486 ins_encode %{
7487 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7488 Label done;
7489 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7490 // Branch if not (cmp crx).
7491 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7492 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7493 // TODO PPC port __ endgroup_if_needed(_size == 12);
7494 __ bind(done);
7495 %}
7496 ins_pipe(pipe_class_default);
7497 %}
7498
7499 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7500 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7501 ins_cost(DEFAULT_COST+BRANCH_COST);
7502
7503 ins_variable_size_depending_on_alignment(true);
7504
7505 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %}
7506 // Worst case is branch + move + stop, no stop without scheduler.
7507 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7508 ins_encode %{
7509 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7510 Label done;
7511 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7512 // Branch if not (cmp crx).
7513 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7514 __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7515 // TODO PPC port __ endgroup_if_needed(_size == 12);
7516 __ bind(done);
7517 %}
7518 ins_pipe(pipe_class_default);
7519 %}
7520
7521 //----------Conditional_store--------------------------------------------------
7522 // Conditional-store of the updated heap-top.
7523 // Used during allocation of the shared heap.
7524 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7525
7526 // As compareAndSwapL, but return flag register instead of boolean value in
7527 // int register.
7528 // Used by sun/misc/AtomicLongCSImpl.java.
7529 // Mem_ptr must be a memory operand, else this node does not get
7530 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7531 // can be rematerialized which leads to errors.
7532 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7533 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7534 effect(TEMP cr0);
7535 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7536 ins_encode %{
7537 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7538 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7539 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7540 noreg, NULL, true);
7541 %}
7542 ins_pipe(pipe_class_default);
7543 %}
7544
7545 // As compareAndSwapP, but return flag register instead of boolean value in
7546 // int register.
7547 // This instruction is matched if UseTLAB is off.
7548 // Mem_ptr must be a memory operand, else this node does not get
7549 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7550 // can be rematerialized which leads to errors.
7551 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7552 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7553 ins_cost(2*MEMORY_REF_COST);
7554
7555 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7556 ins_encode %{
7557 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7558 __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7559 %}
7560 ins_pipe(pipe_class_memory);
7561 %}
7562
7563 // Implement LoadPLocked. Must be ordered against changes of the memory location
7564 // by storePConditional.
7565 // Don't know whether this is ever used.
7566 instruct loadPLocked(iRegPdst dst, memory mem) %{
7567 match(Set dst (LoadPLocked mem));
7568 ins_cost(2*MEMORY_REF_COST);
7569
7570 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %}
7571 size(4);
7572 ins_encode %{
7573 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7574 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7575 %}
7576 ins_pipe(pipe_class_memory);
7577 %}
7578
7579 //----------Compare-And-Swap---------------------------------------------------
7580
7581 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7582 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be
7583 // matched.
7584
7585 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7586 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7587 effect(TEMP cr0);
7588 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7589 // Variable size: instruction count smaller if regs are disjoint.
7590 ins_encode %{
7591 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7592 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7593 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7594 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7595 $res$$Register, true);
7596 %}
7597 ins_pipe(pipe_class_default);
7598 %}
7599
7600 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7601 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7602 effect(TEMP cr0);
7603 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7604 // Variable size: instruction count smaller if regs are disjoint.
7605 ins_encode %{
7606 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7607 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7608 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7609 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7610 $res$$Register, true);
7611 %}
7612 ins_pipe(pipe_class_default);
7613 %}
7614
7615 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7616 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7617 effect(TEMP cr0);
7618 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7619 // Variable size: instruction count smaller if regs are disjoint.
7620 ins_encode %{
7621 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7622 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7623 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7624 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7625 $res$$Register, NULL, true);
7626 %}
7627 ins_pipe(pipe_class_default);
7628 %}
7629
7630 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7631 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7632 effect(TEMP cr0);
7633 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7634 // Variable size: instruction count smaller if regs are disjoint.
7635 ins_encode %{
7636 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7637 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7638 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7639 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7640 $res$$Register, NULL, true);
7641 %}
7642 ins_pipe(pipe_class_default);
7643 %}
7644
7645 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7646 match(Set res (GetAndAddI mem_ptr src));
7647 effect(TEMP cr0);
7648 format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7649 // Variable size: instruction count smaller if regs are disjoint.
7650 ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7651 ins_pipe(pipe_class_default);
7652 %}
7653
7654 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7655 match(Set res (GetAndAddL mem_ptr src));
7656 effect(TEMP cr0);
7657 format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7658 // Variable size: instruction count smaller if regs are disjoint.
7659 ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7660 ins_pipe(pipe_class_default);
7661 %}
7662
7663 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7664 match(Set res (GetAndSetI mem_ptr src));
7665 effect(TEMP cr0);
7666 format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7667 // Variable size: instruction count smaller if regs are disjoint.
7668 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7669 ins_pipe(pipe_class_default);
7670 %}
7671
7672 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7673 match(Set res (GetAndSetL mem_ptr src));
7674 effect(TEMP cr0);
7675 format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7676 // Variable size: instruction count smaller if regs are disjoint.
7677 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7678 ins_pipe(pipe_class_default);
7679 %}
7680
7681 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7682 match(Set res (GetAndSetP mem_ptr src));
7683 effect(TEMP cr0);
7684 format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7685 // Variable size: instruction count smaller if regs are disjoint.
7686 ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7687 ins_pipe(pipe_class_default);
7688 %}
7689
7690 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7691 match(Set res (GetAndSetN mem_ptr src));
7692 effect(TEMP cr0);
7693 format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7694 // Variable size: instruction count smaller if regs are disjoint.
7695 ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7696 ins_pipe(pipe_class_default);
7697 %}
7698
7699 //----------Arithmetic Instructions--------------------------------------------
7700 // Addition Instructions
7701
7702 // Register Addition
7703 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7704 match(Set dst (AddI src1 src2));
7705 format %{ "ADD $dst, $src1, $src2" %}
7706 size(4);
7707 ins_encode %{
7708 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7709 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7710 %}
7711 ins_pipe(pipe_class_default);
7712 %}
7713
7714 // Expand does not work with above instruct. (??)
7715 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7716 // no match-rule
7717 effect(DEF dst, USE src1, USE src2);
7718 format %{ "ADD $dst, $src1, $src2" %}
7719 size(4);
7720 ins_encode %{
7721 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7722 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7723 %}
7724 ins_pipe(pipe_class_default);
7725 %}
7726
7727 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7728 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7729 ins_cost(DEFAULT_COST*3);
7730
7731 expand %{
7732 // FIXME: we should do this in the ideal world.
7733 iRegIdst tmp1;
7734 iRegIdst tmp2;
7735 addI_reg_reg(tmp1, src1, src2);
7736 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7737 addI_reg_reg(dst, tmp1, tmp2);
7738 %}
7739 %}
7740
7741 // Immediate Addition
7742 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7743 match(Set dst (AddI src1 src2));
7744 format %{ "ADDI $dst, $src1, $src2" %}
7745 size(4);
7746 ins_encode %{
7747 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7748 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7749 %}
7750 ins_pipe(pipe_class_default);
7751 %}
7752
7753 // Immediate Addition with 16-bit shifted operand
7754 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7755 match(Set dst (AddI src1 src2));
7756 format %{ "ADDIS $dst, $src1, $src2" %}
7757 size(4);
7758 ins_encode %{
7759 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7760 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7761 %}
7762 ins_pipe(pipe_class_default);
7763 %}
7764
7765 // Long Addition
7766 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7767 match(Set dst (AddL src1 src2));
7768 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7769 size(4);
7770 ins_encode %{
7771 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7772 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7773 %}
7774 ins_pipe(pipe_class_default);
7775 %}
7776
7777 // Expand does not work with above instruct. (??)
7778 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7779 // no match-rule
7780 effect(DEF dst, USE src1, USE src2);
7781 format %{ "ADD $dst, $src1, $src2 \t// long" %}
7782 size(4);
7783 ins_encode %{
7784 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7785 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7786 %}
7787 ins_pipe(pipe_class_default);
7788 %}
7789
7790 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7791 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7792 ins_cost(DEFAULT_COST*3);
7793
7794 expand %{
7795 // FIXME: we should do this in the ideal world.
7796 iRegLdst tmp1;
7797 iRegLdst tmp2;
7798 addL_reg_reg(tmp1, src1, src2);
7799 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7800 addL_reg_reg(dst, tmp1, tmp2);
7801 %}
7802 %}
7803
7804 // AddL + ConvL2I.
7805 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7806 match(Set dst (ConvL2I (AddL src1 src2)));
7807
7808 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %}
7809 size(4);
7810 ins_encode %{
7811 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7812 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7813 %}
7814 ins_pipe(pipe_class_default);
7815 %}
7816
7817 // No constant pool entries required.
7818 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7819 match(Set dst (AddL src1 src2));
7820
7821 format %{ "ADDI $dst, $src1, $src2" %}
7822 size(4);
7823 ins_encode %{
7824 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7825 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7826 %}
7827 ins_pipe(pipe_class_default);
7828 %}
7829
7830 // Long Immediate Addition with 16-bit shifted operand.
7831 // No constant pool entries required.
7832 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7833 match(Set dst (AddL src1 src2));
7834
7835 format %{ "ADDIS $dst, $src1, $src2" %}
7836 size(4);
7837 ins_encode %{
7838 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7839 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7840 %}
7841 ins_pipe(pipe_class_default);
7842 %}
7843
7844 // Pointer Register Addition
7845 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7846 match(Set dst (AddP src1 src2));
7847 format %{ "ADD $dst, $src1, $src2" %}
7848 size(4);
7849 ins_encode %{
7850 // TODO: PPC port $archOpcode(ppc64Opcode_add);
7851 __ add($dst$$Register, $src1$$Register, $src2$$Register);
7852 %}
7853 ins_pipe(pipe_class_default);
7854 %}
7855
7856 // Pointer Immediate Addition
7857 // No constant pool entries required.
7858 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7859 match(Set dst (AddP src1 src2));
7860
7861 format %{ "ADDI $dst, $src1, $src2" %}
7862 size(4);
7863 ins_encode %{
7864 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7865 __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7866 %}
7867 ins_pipe(pipe_class_default);
7868 %}
7869
7870 // Pointer Immediate Addition with 16-bit shifted operand.
7871 // No constant pool entries required.
7872 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7873 match(Set dst (AddP src1 src2));
7874
7875 format %{ "ADDIS $dst, $src1, $src2" %}
7876 size(4);
7877 ins_encode %{
7878 // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7879 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7880 %}
7881 ins_pipe(pipe_class_default);
7882 %}
7883
7884 //---------------------
7885 // Subtraction Instructions
7886
7887 // Register Subtraction
7888 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7889 match(Set dst (SubI src1 src2));
7890 format %{ "SUBF $dst, $src2, $src1" %}
7891 size(4);
7892 ins_encode %{
7893 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7894 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7895 %}
7896 ins_pipe(pipe_class_default);
7897 %}
7898
7899 // Immediate Subtraction
7900 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7901 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7902
7903 // SubI from constant (using subfic).
7904 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7905 match(Set dst (SubI src1 src2));
7906 format %{ "SUBI $dst, $src1, $src2" %}
7907
7908 size(4);
7909 ins_encode %{
7910 // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7911 __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7912 %}
7913 ins_pipe(pipe_class_default);
7914 %}
7915
7916 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7917 // positive integers and 0xF...F for negative ones.
7918 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7919 // no match-rule, false predicate
7920 effect(DEF dst, USE src);
7921 predicate(false);
7922
7923 format %{ "SRAWI $dst, $src, #31" %}
7924 size(4);
7925 ins_encode %{
7926 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7927 __ srawi($dst$$Register, $src$$Register, 0x1f);
7928 %}
7929 ins_pipe(pipe_class_default);
7930 %}
7931
7932 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7933 match(Set dst (AbsI src));
7934 ins_cost(DEFAULT_COST*3);
7935
7936 expand %{
7937 iRegIdst tmp1;
7938 iRegIdst tmp2;
7939 signmask32I_regI(tmp1, src);
7940 xorI_reg_reg(tmp2, tmp1, src);
7941 subI_reg_reg(dst, tmp2, tmp1);
7942 %}
7943 %}
7944
7945 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7946 match(Set dst (SubI zero src2));
7947 format %{ "NEG $dst, $src2" %}
7948 size(4);
7949 ins_encode %{
7950 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7951 __ neg($dst$$Register, $src2$$Register);
7952 %}
7953 ins_pipe(pipe_class_default);
7954 %}
7955
7956 // Long subtraction
7957 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7958 match(Set dst (SubL src1 src2));
7959 format %{ "SUBF $dst, $src2, $src1 \t// long" %}
7960 size(4);
7961 ins_encode %{
7962 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7963 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7964 %}
7965 ins_pipe(pipe_class_default);
7966 %}
7967
7968 // SubL + convL2I.
7969 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7970 match(Set dst (ConvL2I (SubL src1 src2)));
7971
7972 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %}
7973 size(4);
7974 ins_encode %{
7975 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7976 __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7977 %}
7978 ins_pipe(pipe_class_default);
7979 %}
7980
7981 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7982 // positive longs and 0xF...F for negative ones.
7983 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7984 // no match-rule, false predicate
7985 effect(DEF dst, USE src);
7986 predicate(false);
7987
7988 format %{ "SRADI $dst, $src, #63" %}
7989 size(4);
7990 ins_encode %{
7991 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7992 __ sradi($dst$$Register, $src$$Register, 0x3f);
7993 %}
7994 ins_pipe(pipe_class_default);
7995 %}
7996
7997 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7998 // positive longs and 0xF...F for negative ones.
7999 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8000 // no match-rule, false predicate
8001 effect(DEF dst, USE src);
8002 predicate(false);
8003
8004 format %{ "SRADI $dst, $src, #63" %}
8005 size(4);
8006 ins_encode %{
8007 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8008 __ sradi($dst$$Register, $src$$Register, 0x3f);
8009 %}
8010 ins_pipe(pipe_class_default);
8011 %}
8012
8013 // Long negation
8014 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8015 match(Set dst (SubL zero src2));
8016 format %{ "NEG $dst, $src2 \t// long" %}
8017 size(4);
8018 ins_encode %{
8019 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8020 __ neg($dst$$Register, $src2$$Register);
8021 %}
8022 ins_pipe(pipe_class_default);
8023 %}
8024
8025 // NegL + ConvL2I.
8026 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8027 match(Set dst (ConvL2I (SubL zero src2)));
8028
8029 format %{ "NEG $dst, $src2 \t// long + l2i" %}
8030 size(4);
8031 ins_encode %{
8032 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8033 __ neg($dst$$Register, $src2$$Register);
8034 %}
8035 ins_pipe(pipe_class_default);
8036 %}
8037
8038 // Multiplication Instructions
8039 // Integer Multiplication
8040
8041 // Register Multiplication
8042 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8043 match(Set dst (MulI src1 src2));
8044 ins_cost(DEFAULT_COST);
8045
8046 format %{ "MULLW $dst, $src1, $src2" %}
8047 size(4);
8048 ins_encode %{
8049 // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8050 __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8051 %}
8052 ins_pipe(pipe_class_default);
8053 %}
8054
8055 // Immediate Multiplication
8056 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8057 match(Set dst (MulI src1 src2));
8058 ins_cost(DEFAULT_COST);
8059
8060 format %{ "MULLI $dst, $src1, $src2" %}
8061 size(4);
8062 ins_encode %{
8063 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8064 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8065 %}
8066 ins_pipe(pipe_class_default);
8067 %}
8068
8069 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8070 match(Set dst (MulL src1 src2));
8071 ins_cost(DEFAULT_COST);
8072
8073 format %{ "MULLD $dst $src1, $src2 \t// long" %}
8074 size(4);
8075 ins_encode %{
8076 // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8077 __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8078 %}
8079 ins_pipe(pipe_class_default);
8080 %}
8081
8082 // Multiply high for optimized long division by constant.
8083 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8084 match(Set dst (MulHiL src1 src2));
8085 ins_cost(DEFAULT_COST);
8086
8087 format %{ "MULHD $dst $src1, $src2 \t// long" %}
8088 size(4);
8089 ins_encode %{
8090 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8091 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8092 %}
8093 ins_pipe(pipe_class_default);
8094 %}
8095
8096 // Immediate Multiplication
8097 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8098 match(Set dst (MulL src1 src2));
8099 ins_cost(DEFAULT_COST);
8100
8101 format %{ "MULLI $dst, $src1, $src2" %}
8102 size(4);
8103 ins_encode %{
8104 // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8105 __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8106 %}
8107 ins_pipe(pipe_class_default);
8108 %}
8109
8110 // Integer Division with Immediate -1: Negate.
8111 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8112 match(Set dst (DivI src1 src2));
8113 ins_cost(DEFAULT_COST);
8114
8115 format %{ "NEG $dst, $src1 \t// /-1" %}
8116 size(4);
8117 ins_encode %{
8118 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8119 __ neg($dst$$Register, $src1$$Register);
8120 %}
8121 ins_pipe(pipe_class_default);
8122 %}
8123
8124 // Integer Division with constant, but not -1.
8125 // We should be able to improve this by checking the type of src2.
8126 // It might well be that src2 is known to be positive.
8127 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8128 match(Set dst (DivI src1 src2));
8129 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8130 ins_cost(2*DEFAULT_COST);
8131
8132 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %}
8133 size(4);
8134 ins_encode %{
8135 // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8136 __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8137 %}
8138 ins_pipe(pipe_class_default);
8139 %}
8140
8141 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8142 effect(USE_DEF dst, USE src1, USE crx);
8143 predicate(false);
8144
8145 ins_variable_size_depending_on_alignment(true);
8146
8147 format %{ "CMOVE $dst, neg($src1), $crx" %}
8148 // Worst case is branch + move + stop, no stop without scheduler.
8149 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8150 ins_encode %{
8151 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8152 Label done;
8153 __ bne($crx$$CondRegister, done);
8154 __ neg($dst$$Register, $src1$$Register);
8155 // TODO PPC port __ endgroup_if_needed(_size == 12);
8156 __ bind(done);
8157 %}
8158 ins_pipe(pipe_class_default);
8159 %}
8160
8161 // Integer Division with Registers not containing constants.
8162 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8163 match(Set dst (DivI src1 src2));
8164 ins_cost(10*DEFAULT_COST);
8165
8166 expand %{
8167 immI16 imm %{ (int)-1 %}
8168 flagsReg tmp1;
8169 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8170 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8171 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8172 %}
8173 %}
8174
8175 // Long Division with Immediate -1: Negate.
8176 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8177 match(Set dst (DivL src1 src2));
8178 ins_cost(DEFAULT_COST);
8179
8180 format %{ "NEG $dst, $src1 \t// /-1, long" %}
8181 size(4);
8182 ins_encode %{
8183 // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8184 __ neg($dst$$Register, $src1$$Register);
8185 %}
8186 ins_pipe(pipe_class_default);
8187 %}
8188
8189 // Long Division with constant, but not -1.
8190 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8191 match(Set dst (DivL src1 src2));
8192 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8193 ins_cost(2*DEFAULT_COST);
8194
8195 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %}
8196 size(4);
8197 ins_encode %{
8198 // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8199 __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8200 %}
8201 ins_pipe(pipe_class_default);
8202 %}
8203
8204 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8205 effect(USE_DEF dst, USE src1, USE crx);
8206 predicate(false);
8207
8208 ins_variable_size_depending_on_alignment(true);
8209
8210 format %{ "CMOVE $dst, neg($src1), $crx" %}
8211 // Worst case is branch + move + stop, no stop without scheduler.
8212 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8213 ins_encode %{
8214 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8215 Label done;
8216 __ bne($crx$$CondRegister, done);
8217 __ neg($dst$$Register, $src1$$Register);
8218 // TODO PPC port __ endgroup_if_needed(_size == 12);
8219 __ bind(done);
8220 %}
8221 ins_pipe(pipe_class_default);
8222 %}
8223
8224 // Long Division with Registers not containing constants.
8225 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8226 match(Set dst (DivL src1 src2));
8227 ins_cost(10*DEFAULT_COST);
8228
8229 expand %{
8230 immL16 imm %{ (int)-1 %}
8231 flagsReg tmp1;
8232 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8233 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2
8234 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1
8235 %}
8236 %}
8237
8238 // Integer Remainder with registers.
8239 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8240 match(Set dst (ModI src1 src2));
8241 ins_cost(10*DEFAULT_COST);
8242
8243 expand %{
8244 immI16 imm %{ (int)-1 %}
8245 flagsReg tmp1;
8246 iRegIdst tmp2;
8247 iRegIdst tmp3;
8248 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1
8249 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8250 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8251 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8252 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8253 %}
8254 %}
8255
8256 // Long Remainder with registers
8257 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8258 match(Set dst (ModL src1 src2));
8259 ins_cost(10*DEFAULT_COST);
8260
8261 expand %{
8262 immL16 imm %{ (int)-1 %}
8263 flagsReg tmp1;
8264 iRegLdst tmp2;
8265 iRegLdst tmp3;
8266 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1
8267 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2
8268 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1
8269 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2
8270 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3
8271 %}
8272 %}
8273
8274 // Integer Shift Instructions
8275
8276 // Register Shift Left
8277
8278 // Clear all but the lowest #mask bits.
8279 // Used to normalize shift amounts in registers.
8280 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8281 // no match-rule, false predicate
8282 effect(DEF dst, USE src, USE mask);
8283 predicate(false);
8284
8285 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %}
8286 size(4);
8287 ins_encode %{
8288 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8289 __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8290 %}
8291 ins_pipe(pipe_class_default);
8292 %}
8293
8294 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8295 // no match-rule, false predicate
8296 effect(DEF dst, USE src1, USE src2);
8297 predicate(false);
8298
8299 format %{ "SLW $dst, $src1, $src2" %}
8300 size(4);
8301 ins_encode %{
8302 // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8303 __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8304 %}
8305 ins_pipe(pipe_class_default);
8306 %}
8307
8308 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8309 match(Set dst (LShiftI src1 src2));
8310 ins_cost(DEFAULT_COST*2);
8311 expand %{
8312 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8313 iRegIdst tmpI;
8314 maskI_reg_imm(tmpI, src2, mask);
8315 lShiftI_reg_reg(dst, src1, tmpI);
8316 %}
8317 %}
8318
8319 // Register Shift Left Immediate
8320 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8321 match(Set dst (LShiftI src1 src2));
8322
8323 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %}
8324 size(4);
8325 ins_encode %{
8326 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8327 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8328 %}
8329 ins_pipe(pipe_class_default);
8330 %}
8331
8332 // AndI with negpow2-constant + LShiftI
8333 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8334 match(Set dst (LShiftI (AndI src1 src2) src3));
8335 predicate(UseRotateAndMaskInstructionsPPC64);
8336
8337 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8338 size(4);
8339 ins_encode %{
8340 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8341 long src2 = $src2$$constant;
8342 long src3 = $src3$$constant;
8343 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8344 if (maskbits >= 32) {
8345 __ li($dst$$Register, 0); // addi
8346 } else {
8347 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8348 }
8349 %}
8350 ins_pipe(pipe_class_default);
8351 %}
8352
8353 // RShiftI + AndI with negpow2-constant + LShiftI
8354 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8355 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8356 predicate(UseRotateAndMaskInstructionsPPC64);
8357
8358 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8359 size(4);
8360 ins_encode %{
8361 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8362 long src2 = $src2$$constant;
8363 long src3 = $src3$$constant;
8364 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2);
8365 if (maskbits >= 32) {
8366 __ li($dst$$Register, 0); // addi
8367 } else {
8368 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8369 }
8370 %}
8371 ins_pipe(pipe_class_default);
8372 %}
8373
8374 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8375 // no match-rule, false predicate
8376 effect(DEF dst, USE src1, USE src2);
8377 predicate(false);
8378
8379 format %{ "SLD $dst, $src1, $src2" %}
8380 size(4);
8381 ins_encode %{
8382 // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8383 __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8384 %}
8385 ins_pipe(pipe_class_default);
8386 %}
8387
8388 // Register Shift Left
8389 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8390 match(Set dst (LShiftL src1 src2));
8391 ins_cost(DEFAULT_COST*2);
8392 expand %{
8393 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8394 iRegIdst tmpI;
8395 maskI_reg_imm(tmpI, src2, mask);
8396 lShiftL_regL_regI(dst, src1, tmpI);
8397 %}
8398 %}
8399
8400 // Register Shift Left Immediate
8401 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8402 match(Set dst (LShiftL src1 src2));
8403 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %}
8404 size(4);
8405 ins_encode %{
8406 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8407 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8408 %}
8409 ins_pipe(pipe_class_default);
8410 %}
8411
8412 // If we shift more than 32 bits, we need not convert I2L.
8413 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8414 match(Set dst (LShiftL (ConvI2L src1) src2));
8415 ins_cost(DEFAULT_COST);
8416
8417 size(4);
8418 format %{ "SLDI $dst, i2l($src1), $src2" %}
8419 ins_encode %{
8420 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8421 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8422 %}
8423 ins_pipe(pipe_class_default);
8424 %}
8425
8426 // Shift a postivie int to the left.
8427 // Clrlsldi clears the upper 32 bits and shifts.
8428 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8429 match(Set dst (LShiftL (ConvI2L src1) src2));
8430 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8431
8432 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %}
8433 size(4);
8434 ins_encode %{
8435 // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8436 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8437 %}
8438 ins_pipe(pipe_class_default);
8439 %}
8440
8441 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8442 // no match-rule, false predicate
8443 effect(DEF dst, USE src1, USE src2);
8444 predicate(false);
8445
8446 format %{ "SRAW $dst, $src1, $src2" %}
8447 size(4);
8448 ins_encode %{
8449 // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8450 __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8451 %}
8452 ins_pipe(pipe_class_default);
8453 %}
8454
8455 // Register Arithmetic Shift Right
8456 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8457 match(Set dst (RShiftI src1 src2));
8458 ins_cost(DEFAULT_COST*2);
8459 expand %{
8460 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8461 iRegIdst tmpI;
8462 maskI_reg_imm(tmpI, src2, mask);
8463 arShiftI_reg_reg(dst, src1, tmpI);
8464 %}
8465 %}
8466
8467 // Register Arithmetic Shift Right Immediate
8468 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8469 match(Set dst (RShiftI src1 src2));
8470
8471 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %}
8472 size(4);
8473 ins_encode %{
8474 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8475 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8476 %}
8477 ins_pipe(pipe_class_default);
8478 %}
8479
8480 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8481 // no match-rule, false predicate
8482 effect(DEF dst, USE src1, USE src2);
8483 predicate(false);
8484
8485 format %{ "SRAD $dst, $src1, $src2" %}
8486 size(4);
8487 ins_encode %{
8488 // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8489 __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8490 %}
8491 ins_pipe(pipe_class_default);
8492 %}
8493
8494 // Register Shift Right Arithmetic Long
8495 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8496 match(Set dst (RShiftL src1 src2));
8497 ins_cost(DEFAULT_COST*2);
8498
8499 expand %{
8500 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8501 iRegIdst tmpI;
8502 maskI_reg_imm(tmpI, src2, mask);
8503 arShiftL_regL_regI(dst, src1, tmpI);
8504 %}
8505 %}
8506
8507 // Register Shift Right Immediate
8508 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8509 match(Set dst (RShiftL src1 src2));
8510
8511 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %}
8512 size(4);
8513 ins_encode %{
8514 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8515 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8516 %}
8517 ins_pipe(pipe_class_default);
8518 %}
8519
8520 // RShiftL + ConvL2I
8521 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8522 match(Set dst (ConvL2I (RShiftL src1 src2)));
8523
8524 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8525 size(4);
8526 ins_encode %{
8527 // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8528 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8529 %}
8530 ins_pipe(pipe_class_default);
8531 %}
8532
8533 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8534 // no match-rule, false predicate
8535 effect(DEF dst, USE src1, USE src2);
8536 predicate(false);
8537
8538 format %{ "SRW $dst, $src1, $src2" %}
8539 size(4);
8540 ins_encode %{
8541 // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8542 __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8543 %}
8544 ins_pipe(pipe_class_default);
8545 %}
8546
8547 // Register Shift Right
8548 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8549 match(Set dst (URShiftI src1 src2));
8550 ins_cost(DEFAULT_COST*2);
8551
8552 expand %{
8553 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8554 iRegIdst tmpI;
8555 maskI_reg_imm(tmpI, src2, mask);
8556 urShiftI_reg_reg(dst, src1, tmpI);
8557 %}
8558 %}
8559
8560 // Register Shift Right Immediate
8561 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8562 match(Set dst (URShiftI src1 src2));
8563
8564 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %}
8565 size(4);
8566 ins_encode %{
8567 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8568 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8569 %}
8570 ins_pipe(pipe_class_default);
8571 %}
8572
8573 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8574 // no match-rule, false predicate
8575 effect(DEF dst, USE src1, USE src2);
8576 predicate(false);
8577
8578 format %{ "SRD $dst, $src1, $src2" %}
8579 size(4);
8580 ins_encode %{
8581 // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8582 __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8583 %}
8584 ins_pipe(pipe_class_default);
8585 %}
8586
8587 // Register Shift Right
8588 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8589 match(Set dst (URShiftL src1 src2));
8590 ins_cost(DEFAULT_COST*2);
8591
8592 expand %{
8593 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8594 iRegIdst tmpI;
8595 maskI_reg_imm(tmpI, src2, mask);
8596 urShiftL_regL_regI(dst, src1, tmpI);
8597 %}
8598 %}
8599
8600 // Register Shift Right Immediate
8601 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8602 match(Set dst (URShiftL src1 src2));
8603
8604 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %}
8605 size(4);
8606 ins_encode %{
8607 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8608 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8609 %}
8610 ins_pipe(pipe_class_default);
8611 %}
8612
8613 // URShiftL + ConvL2I.
8614 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8615 match(Set dst (ConvL2I (URShiftL src1 src2)));
8616
8617 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8618 size(4);
8619 ins_encode %{
8620 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8621 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8622 %}
8623 ins_pipe(pipe_class_default);
8624 %}
8625
8626 // Register Shift Right Immediate with a CastP2X
8627 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8628 match(Set dst (URShiftL (CastP2X src1) src2));
8629
8630 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8631 size(4);
8632 ins_encode %{
8633 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8634 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8635 %}
8636 ins_pipe(pipe_class_default);
8637 %}
8638
8639 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8640 match(Set dst (ConvL2I (ConvI2L src)));
8641
8642 format %{ "EXTSW $dst, $src \t// int->int" %}
8643 size(4);
8644 ins_encode %{
8645 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8646 __ extsw($dst$$Register, $src$$Register);
8647 %}
8648 ins_pipe(pipe_class_default);
8649 %}
8650
8651 //----------Rotate Instructions------------------------------------------------
8652
8653 // Rotate Left by 8-bit immediate
8654 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8655 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8656 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8657
8658 format %{ "ROTLWI $dst, $src, $lshift" %}
8659 size(4);
8660 ins_encode %{
8661 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8662 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8663 %}
8664 ins_pipe(pipe_class_default);
8665 %}
8666
8667 // Rotate Right by 8-bit immediate
8668 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8669 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8670 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8671
8672 format %{ "ROTRWI $dst, $rshift" %}
8673 size(4);
8674 ins_encode %{
8675 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8676 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8677 %}
8678 ins_pipe(pipe_class_default);
8679 %}
8680
8681 //----------Floating Point Arithmetic Instructions-----------------------------
8682
8683 // Add float single precision
8684 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8685 match(Set dst (AddF src1 src2));
8686
8687 format %{ "FADDS $dst, $src1, $src2" %}
8688 size(4);
8689 ins_encode %{
8690 // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8691 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8692 %}
8693 ins_pipe(pipe_class_default);
8694 %}
8695
8696 // Add float double precision
8697 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8698 match(Set dst (AddD src1 src2));
8699
8700 format %{ "FADD $dst, $src1, $src2" %}
8701 size(4);
8702 ins_encode %{
8703 // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8704 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8705 %}
8706 ins_pipe(pipe_class_default);
8707 %}
8708
8709 // Sub float single precision
8710 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8711 match(Set dst (SubF src1 src2));
8712
8713 format %{ "FSUBS $dst, $src1, $src2" %}
8714 size(4);
8715 ins_encode %{
8716 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8717 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8718 %}
8719 ins_pipe(pipe_class_default);
8720 %}
8721
8722 // Sub float double precision
8723 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8724 match(Set dst (SubD src1 src2));
8725 format %{ "FSUB $dst, $src1, $src2" %}
8726 size(4);
8727 ins_encode %{
8728 // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8729 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8730 %}
8731 ins_pipe(pipe_class_default);
8732 %}
8733
8734 // Mul float single precision
8735 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8736 match(Set dst (MulF src1 src2));
8737 format %{ "FMULS $dst, $src1, $src2" %}
8738 size(4);
8739 ins_encode %{
8740 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8741 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8742 %}
8743 ins_pipe(pipe_class_default);
8744 %}
8745
8746 // Mul float double precision
8747 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8748 match(Set dst (MulD src1 src2));
8749 format %{ "FMUL $dst, $src1, $src2" %}
8750 size(4);
8751 ins_encode %{
8752 // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8753 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8754 %}
8755 ins_pipe(pipe_class_default);
8756 %}
8757
8758 // Div float single precision
8759 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8760 match(Set dst (DivF src1 src2));
8761 format %{ "FDIVS $dst, $src1, $src2" %}
8762 size(4);
8763 ins_encode %{
8764 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8765 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8766 %}
8767 ins_pipe(pipe_class_default);
8768 %}
8769
8770 // Div float double precision
8771 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8772 match(Set dst (DivD src1 src2));
8773 format %{ "FDIV $dst, $src1, $src2" %}
8774 size(4);
8775 ins_encode %{
8776 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8777 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8778 %}
8779 ins_pipe(pipe_class_default);
8780 %}
8781
8782 // Absolute float single precision
8783 instruct absF_reg(regF dst, regF src) %{
8784 match(Set dst (AbsF src));
8785 format %{ "FABS $dst, $src \t// float" %}
8786 size(4);
8787 ins_encode %{
8788 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8789 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8790 %}
8791 ins_pipe(pipe_class_default);
8792 %}
8793
8794 // Absolute float double precision
8795 instruct absD_reg(regD dst, regD src) %{
8796 match(Set dst (AbsD src));
8797 format %{ "FABS $dst, $src \t// double" %}
8798 size(4);
8799 ins_encode %{
8800 // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8801 __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8802 %}
8803 ins_pipe(pipe_class_default);
8804 %}
8805
8806 instruct negF_reg(regF dst, regF src) %{
8807 match(Set dst (NegF src));
8808 format %{ "FNEG $dst, $src \t// float" %}
8809 size(4);
8810 ins_encode %{
8811 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8812 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8813 %}
8814 ins_pipe(pipe_class_default);
8815 %}
8816
8817 instruct negD_reg(regD dst, regD src) %{
8818 match(Set dst (NegD src));
8819 format %{ "FNEG $dst, $src \t// double" %}
8820 size(4);
8821 ins_encode %{
8822 // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8823 __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8824 %}
8825 ins_pipe(pipe_class_default);
8826 %}
8827
8828 // AbsF + NegF.
8829 instruct negF_absF_reg(regF dst, regF src) %{
8830 match(Set dst (NegF (AbsF src)));
8831 format %{ "FNABS $dst, $src \t// float" %}
8832 size(4);
8833 ins_encode %{
8834 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8835 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8836 %}
8837 ins_pipe(pipe_class_default);
8838 %}
8839
8840 // AbsD + NegD.
8841 instruct negD_absD_reg(regD dst, regD src) %{
8842 match(Set dst (NegD (AbsD src)));
8843 format %{ "FNABS $dst, $src \t// double" %}
8844 size(4);
8845 ins_encode %{
8846 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8847 __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8848 %}
8849 ins_pipe(pipe_class_default);
8850 %}
8851
8852 // VM_Version::has_fsqrt() decides if this node will be used.
8853 // Sqrt float double precision
8854 instruct sqrtD_reg(regD dst, regD src) %{
8855 match(Set dst (SqrtD src));
8856 format %{ "FSQRT $dst, $src" %}
8857 size(4);
8858 ins_encode %{
8859 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8860 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8861 %}
8862 ins_pipe(pipe_class_default);
8863 %}
8864
8865 // Single-precision sqrt.
8866 instruct sqrtF_reg(regF dst, regF src) %{
8867 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8868 predicate(VM_Version::has_fsqrts());
8869 ins_cost(DEFAULT_COST);
8870
8871 format %{ "FSQRTS $dst, $src" %}
8872 size(4);
8873 ins_encode %{
8874 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8875 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8876 %}
8877 ins_pipe(pipe_class_default);
8878 %}
8879
8880 instruct roundDouble_nop(regD dst) %{
8881 match(Set dst (RoundDouble dst));
8882 ins_cost(0);
8883
8884 format %{ " -- \t// RoundDouble not needed - empty" %}
8885 size(0);
8886 // PPC results are already "rounded" (i.e., normal-format IEEE).
8887 ins_encode( /*empty*/ );
8888 ins_pipe(pipe_class_default);
8889 %}
8890
8891 instruct roundFloat_nop(regF dst) %{
8892 match(Set dst (RoundFloat dst));
8893 ins_cost(0);
8894
8895 format %{ " -- \t// RoundFloat not needed - empty" %}
8896 size(0);
8897 // PPC results are already "rounded" (i.e., normal-format IEEE).
8898 ins_encode( /*empty*/ );
8899 ins_pipe(pipe_class_default);
8900 %}
8901
8902 //----------Logical Instructions-----------------------------------------------
8903
8904 // And Instructions
8905
8906 // Register And
8907 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8908 match(Set dst (AndI src1 src2));
8909 format %{ "AND $dst, $src1, $src2" %}
8910 size(4);
8911 ins_encode %{
8912 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8913 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8914 %}
8915 ins_pipe(pipe_class_default);
8916 %}
8917
8918 // Immediate And
8919 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8920 match(Set dst (AndI src1 src2));
8921 effect(KILL cr0);
8922
8923 format %{ "ANDI $dst, $src1, $src2" %}
8924 size(4);
8925 ins_encode %{
8926 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8927 // FIXME: avoid andi_ ?
8928 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8929 %}
8930 ins_pipe(pipe_class_default);
8931 %}
8932
8933 // Immediate And where the immediate is a negative power of 2.
8934 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8935 match(Set dst (AndI src1 src2));
8936 format %{ "ANDWI $dst, $src1, $src2" %}
8937 size(4);
8938 ins_encode %{
8939 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8940 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8941 %}
8942 ins_pipe(pipe_class_default);
8943 %}
8944
8945 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8946 match(Set dst (AndI src1 src2));
8947 format %{ "ANDWI $dst, $src1, $src2" %}
8948 size(4);
8949 ins_encode %{
8950 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8951 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8952 %}
8953 ins_pipe(pipe_class_default);
8954 %}
8955
8956 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8957 match(Set dst (AndI src1 src2));
8958 predicate(UseRotateAndMaskInstructionsPPC64);
8959 format %{ "ANDWI $dst, $src1, $src2" %}
8960 size(4);
8961 ins_encode %{
8962 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8963 __ rlwinm($dst$$Register, $src1$$Register, 0,
8964 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8965 %}
8966 ins_pipe(pipe_class_default);
8967 %}
8968
8969 // Register And Long
8970 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8971 match(Set dst (AndL src1 src2));
8972 ins_cost(DEFAULT_COST);
8973
8974 format %{ "AND $dst, $src1, $src2 \t// long" %}
8975 size(4);
8976 ins_encode %{
8977 // TODO: PPC port $archOpcode(ppc64Opcode_and);
8978 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8979 %}
8980 ins_pipe(pipe_class_default);
8981 %}
8982
8983 // Immediate And long
8984 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8985 match(Set dst (AndL src1 src2));
8986 effect(KILL cr0);
8987
8988 format %{ "ANDI $dst, $src1, $src2 \t// long" %}
8989 size(4);
8990 ins_encode %{
8991 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8992 // FIXME: avoid andi_ ?
8993 __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8994 %}
8995 ins_pipe(pipe_class_default);
8996 %}
8997
8998 // Immediate And Long where the immediate is a negative power of 2.
8999 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9000 match(Set dst (AndL src1 src2));
9001 format %{ "ANDDI $dst, $src1, $src2" %}
9002 size(4);
9003 ins_encode %{
9004 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9005 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9006 %}
9007 ins_pipe(pipe_class_default);
9008 %}
9009
9010 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9011 match(Set dst (AndL src1 src2));
9012 format %{ "ANDDI $dst, $src1, $src2" %}
9013 size(4);
9014 ins_encode %{
9015 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9016 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9017 %}
9018 ins_pipe(pipe_class_default);
9019 %}
9020
9021 // AndL + ConvL2I.
9022 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9023 match(Set dst (ConvL2I (AndL src1 src2)));
9024 ins_cost(DEFAULT_COST);
9025
9026 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %}
9027 size(4);
9028 ins_encode %{
9029 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9030 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9031 %}
9032 ins_pipe(pipe_class_default);
9033 %}
9034
9035 // Or Instructions
9036
9037 // Register Or
9038 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9039 match(Set dst (OrI src1 src2));
9040 format %{ "OR $dst, $src1, $src2" %}
9041 size(4);
9042 ins_encode %{
9043 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9044 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9045 %}
9046 ins_pipe(pipe_class_default);
9047 %}
9048
9049 // Expand does not work with above instruct. (??)
9050 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9051 // no match-rule
9052 effect(DEF dst, USE src1, USE src2);
9053 format %{ "OR $dst, $src1, $src2" %}
9054 size(4);
9055 ins_encode %{
9056 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9057 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9058 %}
9059 ins_pipe(pipe_class_default);
9060 %}
9061
9062 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9063 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9064 ins_cost(DEFAULT_COST*3);
9065
9066 expand %{
9067 // FIXME: we should do this in the ideal world.
9068 iRegIdst tmp1;
9069 iRegIdst tmp2;
9070 orI_reg_reg(tmp1, src1, src2);
9071 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9072 orI_reg_reg(dst, tmp1, tmp2);
9073 %}
9074 %}
9075
9076 // Immediate Or
9077 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9078 match(Set dst (OrI src1 src2));
9079 format %{ "ORI $dst, $src1, $src2" %}
9080 size(4);
9081 ins_encode %{
9082 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9083 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9084 %}
9085 ins_pipe(pipe_class_default);
9086 %}
9087
9088 // Register Or Long
9089 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9090 match(Set dst (OrL src1 src2));
9091 ins_cost(DEFAULT_COST);
9092
9093 size(4);
9094 format %{ "OR $dst, $src1, $src2 \t// long" %}
9095 ins_encode %{
9096 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9097 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9098 %}
9099 ins_pipe(pipe_class_default);
9100 %}
9101
9102 // OrL + ConvL2I.
9103 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9104 match(Set dst (ConvL2I (OrL src1 src2)));
9105 ins_cost(DEFAULT_COST);
9106
9107 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %}
9108 size(4);
9109 ins_encode %{
9110 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9111 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9112 %}
9113 ins_pipe(pipe_class_default);
9114 %}
9115
9116 // Immediate Or long
9117 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9118 match(Set dst (OrL src1 con));
9119 ins_cost(DEFAULT_COST);
9120
9121 format %{ "ORI $dst, $src1, $con \t// long" %}
9122 size(4);
9123 ins_encode %{
9124 // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9125 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9126 %}
9127 ins_pipe(pipe_class_default);
9128 %}
9129
9130 // Xor Instructions
9131
9132 // Register Xor
9133 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9134 match(Set dst (XorI src1 src2));
9135 format %{ "XOR $dst, $src1, $src2" %}
9136 size(4);
9137 ins_encode %{
9138 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9139 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9140 %}
9141 ins_pipe(pipe_class_default);
9142 %}
9143
9144 // Expand does not work with above instruct. (??)
9145 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9146 // no match-rule
9147 effect(DEF dst, USE src1, USE src2);
9148 format %{ "XOR $dst, $src1, $src2" %}
9149 size(4);
9150 ins_encode %{
9151 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9152 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9153 %}
9154 ins_pipe(pipe_class_default);
9155 %}
9156
9157 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9158 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9159 ins_cost(DEFAULT_COST*3);
9160
9161 expand %{
9162 // FIXME: we should do this in the ideal world.
9163 iRegIdst tmp1;
9164 iRegIdst tmp2;
9165 xorI_reg_reg(tmp1, src1, src2);
9166 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9167 xorI_reg_reg(dst, tmp1, tmp2);
9168 %}
9169 %}
9170
9171 // Immediate Xor
9172 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9173 match(Set dst (XorI src1 src2));
9174 format %{ "XORI $dst, $src1, $src2" %}
9175 size(4);
9176 ins_encode %{
9177 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9178 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9179 %}
9180 ins_pipe(pipe_class_default);
9181 %}
9182
9183 // Register Xor Long
9184 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9185 match(Set dst (XorL src1 src2));
9186 ins_cost(DEFAULT_COST);
9187
9188 format %{ "XOR $dst, $src1, $src2 \t// long" %}
9189 size(4);
9190 ins_encode %{
9191 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9192 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9193 %}
9194 ins_pipe(pipe_class_default);
9195 %}
9196
9197 // XorL + ConvL2I.
9198 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9199 match(Set dst (ConvL2I (XorL src1 src2)));
9200 ins_cost(DEFAULT_COST);
9201
9202 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %}
9203 size(4);
9204 ins_encode %{
9205 // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9206 __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9207 %}
9208 ins_pipe(pipe_class_default);
9209 %}
9210
9211 // Immediate Xor Long
9212 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9213 match(Set dst (XorL src1 src2));
9214 ins_cost(DEFAULT_COST);
9215
9216 format %{ "XORI $dst, $src1, $src2 \t// long" %}
9217 size(4);
9218 ins_encode %{
9219 // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9220 __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9221 %}
9222 ins_pipe(pipe_class_default);
9223 %}
9224
9225 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9226 match(Set dst (XorI src1 src2));
9227 ins_cost(DEFAULT_COST);
9228
9229 format %{ "NOT $dst, $src1 ($src2)" %}
9230 size(4);
9231 ins_encode %{
9232 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9233 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9234 %}
9235 ins_pipe(pipe_class_default);
9236 %}
9237
9238 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9239 match(Set dst (XorL src1 src2));
9240 ins_cost(DEFAULT_COST);
9241
9242 format %{ "NOT $dst, $src1 ($src2) \t// long" %}
9243 size(4);
9244 ins_encode %{
9245 // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9246 __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9247 %}
9248 ins_pipe(pipe_class_default);
9249 %}
9250
9251 // And-complement
9252 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9253 match(Set dst (AndI (XorI src1 src2) src3));
9254 ins_cost(DEFAULT_COST);
9255
9256 format %{ "ANDW $dst, xori($src1, $src2), $src3" %}
9257 size(4);
9258 ins_encode( enc_andc(dst, src3, src1) );
9259 ins_pipe(pipe_class_default);
9260 %}
9261
9262 // And-complement
9263 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9264 // no match-rule, false predicate
9265 effect(DEF dst, USE src1, USE src2);
9266 predicate(false);
9267
9268 format %{ "ANDC $dst, $src1, $src2" %}
9269 size(4);
9270 ins_encode %{
9271 // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9272 __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9273 %}
9274 ins_pipe(pipe_class_default);
9275 %}
9276
9277 //----------Moves between int/long and float/double----------------------------
9278 //
9279 // The following rules move values from int/long registers/stack-locations
9280 // to float/double registers/stack-locations and vice versa, without doing any
9281 // conversions. These rules are used to implement the bit-conversion methods
9282 // of java.lang.Float etc., e.g.
9283 // int floatToIntBits(float value)
9284 // float intBitsToFloat(int bits)
9285 //
9286 // Notes on the implementation on ppc64:
9287 // We only provide rules which move between a register and a stack-location,
9288 // because we always have to go through memory when moving between a float
9289 // register and an integer register.
9290
9291 //---------- Chain stack slots between similar types --------
9292
9293 // These are needed so that the rules below can match.
9294
9295 // Load integer from stack slot
9296 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9297 match(Set dst src);
9298 ins_cost(MEMORY_REF_COST);
9299
9300 format %{ "LWZ $dst, $src" %}
9301 size(4);
9302 ins_encode( enc_lwz(dst, src) );
9303 ins_pipe(pipe_class_memory);
9304 %}
9305
9306 // Store integer to stack slot
9307 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9308 match(Set dst src);
9309 ins_cost(MEMORY_REF_COST);
9310
9311 format %{ "STW $src, $dst \t// stk" %}
9312 size(4);
9313 ins_encode( enc_stw(src, dst) ); // rs=rt
9314 ins_pipe(pipe_class_memory);
9315 %}
9316
9317 // Load long from stack slot
9318 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9319 match(Set dst src);
9320 ins_cost(MEMORY_REF_COST);
9321
9322 format %{ "LD $dst, $src \t// long" %}
9323 size(4);
9324 ins_encode( enc_ld(dst, src) );
9325 ins_pipe(pipe_class_memory);
9326 %}
9327
9328 // Store long to stack slot
9329 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9330 match(Set dst src);
9331 ins_cost(MEMORY_REF_COST);
9332
9333 format %{ "STD $src, $dst \t// long" %}
9334 size(4);
9335 ins_encode( enc_std(src, dst) ); // rs=rt
9336 ins_pipe(pipe_class_memory);
9337 %}
9338
9339 //----------Moves between int and float
9340
9341 // Move float value from float stack-location to integer register.
9342 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9343 match(Set dst (MoveF2I src));
9344 ins_cost(MEMORY_REF_COST);
9345
9346 format %{ "LWZ $dst, $src \t// MoveF2I" %}
9347 size(4);
9348 ins_encode( enc_lwz(dst, src) );
9349 ins_pipe(pipe_class_memory);
9350 %}
9351
9352 // Move float value from float register to integer stack-location.
9353 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9354 match(Set dst (MoveF2I src));
9355 ins_cost(MEMORY_REF_COST);
9356
9357 format %{ "STFS $src, $dst \t// MoveF2I" %}
9358 size(4);
9359 ins_encode( enc_stfs(src, dst) );
9360 ins_pipe(pipe_class_memory);
9361 %}
9362
9363 // Move integer value from integer stack-location to float register.
9364 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9365 match(Set dst (MoveI2F src));
9366 ins_cost(MEMORY_REF_COST);
9367
9368 format %{ "LFS $dst, $src \t// MoveI2F" %}
9369 size(4);
9370 ins_encode %{
9371 // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9372 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9373 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9374 %}
9375 ins_pipe(pipe_class_memory);
9376 %}
9377
9378 // Move integer value from integer register to float stack-location.
9379 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9380 match(Set dst (MoveI2F src));
9381 ins_cost(MEMORY_REF_COST);
9382
9383 format %{ "STW $src, $dst \t// MoveI2F" %}
9384 size(4);
9385 ins_encode( enc_stw(src, dst) );
9386 ins_pipe(pipe_class_memory);
9387 %}
9388
9389 //----------Moves between long and float
9390
9391 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9392 // no match-rule, false predicate
9393 effect(DEF dst, USE src);
9394 predicate(false);
9395
9396 format %{ "storeD $src, $dst \t// STACK" %}
9397 size(4);
9398 ins_encode( enc_stfd(src, dst) );
9399 ins_pipe(pipe_class_default);
9400 %}
9401
9402 //----------Moves between long and double
9403
9404 // Move double value from double stack-location to long register.
9405 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9406 match(Set dst (MoveD2L src));
9407 ins_cost(MEMORY_REF_COST);
9408 size(4);
9409 format %{ "LD $dst, $src \t// MoveD2L" %}
9410 ins_encode( enc_ld(dst, src) );
9411 ins_pipe(pipe_class_memory);
9412 %}
9413
9414 // Move double value from double register to long stack-location.
9415 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9416 match(Set dst (MoveD2L src));
9417 effect(DEF dst, USE src);
9418 ins_cost(MEMORY_REF_COST);
9419
9420 format %{ "STFD $src, $dst \t// MoveD2L" %}
9421 size(4);
9422 ins_encode( enc_stfd(src, dst) );
9423 ins_pipe(pipe_class_memory);
9424 %}
9425
9426 // Move long value from long stack-location to double register.
9427 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9428 match(Set dst (MoveL2D src));
9429 ins_cost(MEMORY_REF_COST);
9430
9431 format %{ "LFD $dst, $src \t// MoveL2D" %}
9432 size(4);
9433 ins_encode( enc_lfd(dst, src) );
9434 ins_pipe(pipe_class_memory);
9435 %}
9436
9437 // Move long value from long register to double stack-location.
9438 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9439 match(Set dst (MoveL2D src));
9440 ins_cost(MEMORY_REF_COST);
9441
9442 format %{ "STD $src, $dst \t// MoveL2D" %}
9443 size(4);
9444 ins_encode( enc_std(src, dst) );
9445 ins_pipe(pipe_class_memory);
9446 %}
9447
9448 //----------Register Move Instructions-----------------------------------------
9449
9450 // Replicate for Superword
9451
9452 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9453 predicate(false);
9454 effect(DEF dst, USE src);
9455
9456 format %{ "MR $dst, $src \t// replicate " %}
9457 // variable size, 0 or 4.
9458 ins_encode %{
9459 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9460 __ mr_if_needed($dst$$Register, $src$$Register);
9461 %}
9462 ins_pipe(pipe_class_default);
9463 %}
9464
9465 //----------Cast instructions (Java-level type cast)---------------------------
9466
9467 // Cast Long to Pointer for unsafe natives.
9468 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9469 match(Set dst (CastX2P src));
9470
9471 format %{ "MR $dst, $src \t// Long->Ptr" %}
9472 // variable size, 0 or 4.
9473 ins_encode %{
9474 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9475 __ mr_if_needed($dst$$Register, $src$$Register);
9476 %}
9477 ins_pipe(pipe_class_default);
9478 %}
9479
9480 // Cast Pointer to Long for unsafe natives.
9481 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9482 match(Set dst (CastP2X src));
9483
9484 format %{ "MR $dst, $src \t// Ptr->Long" %}
9485 // variable size, 0 or 4.
9486 ins_encode %{
9487 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9488 __ mr_if_needed($dst$$Register, $src$$Register);
9489 %}
9490 ins_pipe(pipe_class_default);
9491 %}
9492
9493 instruct castPP(iRegPdst dst) %{
9494 match(Set dst (CastPP dst));
9495 format %{ " -- \t// castPP of $dst" %}
9496 size(0);
9497 ins_encode( /*empty*/ );
9498 ins_pipe(pipe_class_default);
9499 %}
9500
9501 instruct castII(iRegIdst dst) %{
9502 match(Set dst (CastII dst));
9503 format %{ " -- \t// castII of $dst" %}
9504 size(0);
9505 ins_encode( /*empty*/ );
9506 ins_pipe(pipe_class_default);
9507 %}
9508
9509 instruct checkCastPP(iRegPdst dst) %{
9510 match(Set dst (CheckCastPP dst));
9511 format %{ " -- \t// checkcastPP of $dst" %}
9512 size(0);
9513 ins_encode( /*empty*/ );
9514 ins_pipe(pipe_class_default);
9515 %}
9516
9517 //----------Convert instructions-----------------------------------------------
9518
9519 // Convert to boolean.
9520
9521 // int_to_bool(src) : { 1 if src != 0
9522 // { 0 else
9523 //
9524 // strategy:
9525 // 1) Count leading zeros of 32 bit-value src,
9526 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9527 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9528 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9529
9530 // convI2Bool
9531 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9532 match(Set dst (Conv2B src));
9533 predicate(UseCountLeadingZerosInstructionsPPC64);
9534 ins_cost(DEFAULT_COST);
9535
9536 expand %{
9537 immI shiftAmount %{ 0x5 %}
9538 uimmI16 mask %{ 0x1 %}
9539 iRegIdst tmp1;
9540 iRegIdst tmp2;
9541 countLeadingZerosI(tmp1, src);
9542 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9543 xorI_reg_uimm16(dst, tmp2, mask);
9544 %}
9545 %}
9546
9547 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9548 match(Set dst (Conv2B src));
9549 effect(TEMP crx);
9550 predicate(!UseCountLeadingZerosInstructionsPPC64);
9551 ins_cost(DEFAULT_COST);
9552
9553 format %{ "CMPWI $crx, $src, #0 \t// convI2B"
9554 "LI $dst, #0\n\t"
9555 "BEQ $crx, done\n\t"
9556 "LI $dst, #1\n"
9557 "done:" %}
9558 size(16);
9559 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9560 ins_pipe(pipe_class_compare);
9561 %}
9562
9563 // ConvI2B + XorI
9564 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9565 match(Set dst (XorI (Conv2B src) mask));
9566 predicate(UseCountLeadingZerosInstructionsPPC64);
9567 ins_cost(DEFAULT_COST);
9568
9569 expand %{
9570 immI shiftAmount %{ 0x5 %}
9571 iRegIdst tmp1;
9572 countLeadingZerosI(tmp1, src);
9573 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9574 %}
9575 %}
9576
9577 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9578 match(Set dst (XorI (Conv2B src) mask));
9579 effect(TEMP crx);
9580 predicate(!UseCountLeadingZerosInstructionsPPC64);
9581 ins_cost(DEFAULT_COST);
9582
9583 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9584 "LI $dst, #1\n\t"
9585 "BEQ $crx, done\n\t"
9586 "LI $dst, #0\n"
9587 "done:" %}
9588 size(16);
9589 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9590 ins_pipe(pipe_class_compare);
9591 %}
9592
9593 // AndI 0b0..010..0 + ConvI2B
9594 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9595 match(Set dst (Conv2B (AndI src mask)));
9596 predicate(UseRotateAndMaskInstructionsPPC64);
9597 ins_cost(DEFAULT_COST);
9598
9599 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9600 size(4);
9601 ins_encode %{
9602 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9603 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9604 %}
9605 ins_pipe(pipe_class_default);
9606 %}
9607
9608 // Convert pointer to boolean.
9609 //
9610 // ptr_to_bool(src) : { 1 if src != 0
9611 // { 0 else
9612 //
9613 // strategy:
9614 // 1) Count leading zeros of 64 bit-value src,
9615 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9616 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9617 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9618
9619 // ConvP2B
9620 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9621 match(Set dst (Conv2B src));
9622 predicate(UseCountLeadingZerosInstructionsPPC64);
9623 ins_cost(DEFAULT_COST);
9624
9625 expand %{
9626 immI shiftAmount %{ 0x6 %}
9627 uimmI16 mask %{ 0x1 %}
9628 iRegIdst tmp1;
9629 iRegIdst tmp2;
9630 countLeadingZerosP(tmp1, src);
9631 urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9632 xorI_reg_uimm16(dst, tmp2, mask);
9633 %}
9634 %}
9635
9636 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9637 match(Set dst (Conv2B src));
9638 effect(TEMP crx);
9639 predicate(!UseCountLeadingZerosInstructionsPPC64);
9640 ins_cost(DEFAULT_COST);
9641
9642 format %{ "CMPDI $crx, $src, #0 \t// convP2B"
9643 "LI $dst, #0\n\t"
9644 "BEQ $crx, done\n\t"
9645 "LI $dst, #1\n"
9646 "done:" %}
9647 size(16);
9648 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9649 ins_pipe(pipe_class_compare);
9650 %}
9651
9652 // ConvP2B + XorI
9653 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9654 match(Set dst (XorI (Conv2B src) mask));
9655 predicate(UseCountLeadingZerosInstructionsPPC64);
9656 ins_cost(DEFAULT_COST);
9657
9658 expand %{
9659 immI shiftAmount %{ 0x6 %}
9660 iRegIdst tmp1;
9661 countLeadingZerosP(tmp1, src);
9662 urShiftI_reg_imm(dst, tmp1, shiftAmount);
9663 %}
9664 %}
9665
9666 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9667 match(Set dst (XorI (Conv2B src) mask));
9668 effect(TEMP crx);
9669 predicate(!UseCountLeadingZerosInstructionsPPC64);
9670 ins_cost(DEFAULT_COST);
9671
9672 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9673 "LI $dst, #1\n\t"
9674 "BEQ $crx, done\n\t"
9675 "LI $dst, #0\n"
9676 "done:" %}
9677 size(16);
9678 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9679 ins_pipe(pipe_class_compare);
9680 %}
9681
9682 // if src1 < src2, return -1 else return 0
9683 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9684 match(Set dst (CmpLTMask src1 src2));
9685 ins_cost(DEFAULT_COST*4);
9686
9687 expand %{
9688 iRegLdst src1s;
9689 iRegLdst src2s;
9690 iRegLdst diff;
9691 convI2L_reg(src1s, src1); // Ensure proper sign extension.
9692 convI2L_reg(src2s, src2); // Ensure proper sign extension.
9693 subL_reg_reg(diff, src1s, src2s);
9694 // Need to consider >=33 bit result, therefore we need signmaskL.
9695 signmask64I_regL(dst, diff);
9696 %}
9697 %}
9698
9699 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9700 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9701 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %}
9702 size(4);
9703 ins_encode %{
9704 // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9705 __ srawi($dst$$Register, $src1$$Register, 0x1f);
9706 %}
9707 ins_pipe(pipe_class_default);
9708 %}
9709
9710 //----------Arithmetic Conversion Instructions---------------------------------
9711
9712 // Convert to Byte -- nop
9713 // Convert to Short -- nop
9714
9715 // Convert to Int
9716
9717 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9718 match(Set dst (RShiftI (LShiftI src amount) amount));
9719 format %{ "EXTSB $dst, $src \t// byte->int" %}
9720 size(4);
9721 ins_encode %{
9722 // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9723 __ extsb($dst$$Register, $src$$Register);
9724 %}
9725 ins_pipe(pipe_class_default);
9726 %}
9727
9728 // LShiftI 16 + RShiftI 16 converts short to int.
9729 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9730 match(Set dst (RShiftI (LShiftI src amount) amount));
9731 format %{ "EXTSH $dst, $src \t// short->int" %}
9732 size(4);
9733 ins_encode %{
9734 // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9735 __ extsh($dst$$Register, $src$$Register);
9736 %}
9737 ins_pipe(pipe_class_default);
9738 %}
9739
9740 // ConvL2I + ConvI2L: Sign extend int in long register.
9741 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9742 match(Set dst (ConvI2L (ConvL2I src)));
9743
9744 format %{ "EXTSW $dst, $src \t// long->long" %}
9745 size(4);
9746 ins_encode %{
9747 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9748 __ extsw($dst$$Register, $src$$Register);
9749 %}
9750 ins_pipe(pipe_class_default);
9751 %}
9752
9753 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9754 match(Set dst (ConvL2I src));
9755 format %{ "MR $dst, $src \t// long->int" %}
9756 // variable size, 0 or 4
9757 ins_encode %{
9758 // TODO: PPC port $archOpcode(ppc64Opcode_or);
9759 __ mr_if_needed($dst$$Register, $src$$Register);
9760 %}
9761 ins_pipe(pipe_class_default);
9762 %}
9763
9764 instruct convD2IRaw_regD(regD dst, regD src) %{
9765 // no match-rule, false predicate
9766 effect(DEF dst, USE src);
9767 predicate(false);
9768
9769 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9770 size(4);
9771 ins_encode %{
9772 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9773 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9774 %}
9775 ins_pipe(pipe_class_default);
9776 %}
9777
9778 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9779 // no match-rule, false predicate
9780 effect(DEF dst, USE crx, USE src);
9781 predicate(false);
9782
9783 ins_variable_size_depending_on_alignment(true);
9784
9785 format %{ "cmovI $crx, $dst, $src" %}
9786 // Worst case is branch + move + stop, no stop without scheduler.
9787 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9788 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9789 ins_pipe(pipe_class_default);
9790 %}
9791
9792 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9793 // no match-rule, false predicate
9794 effect(DEF dst, USE crx, USE mem);
9795 predicate(false);
9796
9797 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %}
9798 postalloc_expand %{
9799 //
9800 // replaces
9801 //
9802 // region dst crx mem
9803 // \ | | /
9804 // dst=cmovI_bso_stackSlotL_conLvalue0
9805 //
9806 // with
9807 //
9808 // region dst
9809 // \ /
9810 // dst=loadConI16(0)
9811 // |
9812 // ^ region dst crx mem
9813 // | \ | | /
9814 // dst=cmovI_bso_stackSlotL
9815 //
9816
9817 // Create new nodes.
9818 MachNode *m1 = new loadConI16Node();
9819 MachNode *m2 = new cmovI_bso_stackSlotLNode();
9820
9821 // inputs for new nodes
9822 m1->add_req(n_region);
9823 m2->add_req(n_region, n_crx, n_mem);
9824
9825 // precedences for new nodes
9826 m2->add_prec(m1);
9827
9828 // operands for new nodes
9829 m1->_opnds[0] = op_dst;
9830 m1->_opnds[1] = new immI16Oper(0);
9831
9832 m2->_opnds[0] = op_dst;
9833 m2->_opnds[1] = op_crx;
9834 m2->_opnds[2] = op_mem;
9835
9836 // registers for new nodes
9837 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9838 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9839
9840 // Insert new nodes.
9841 nodes->push(m1);
9842 nodes->push(m2);
9843 %}
9844 %}
9845
9846 // Double to Int conversion, NaN is mapped to 0.
9847 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9848 match(Set dst (ConvD2I src));
9849 ins_cost(DEFAULT_COST);
9850
9851 expand %{
9852 regD tmpD;
9853 stackSlotL tmpS;
9854 flagsReg crx;
9855 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9856 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated).
9857 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
9858 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9859 %}
9860 %}
9861
9862 instruct convF2IRaw_regF(regF dst, regF src) %{
9863 // no match-rule, false predicate
9864 effect(DEF dst, USE src);
9865 predicate(false);
9866
9867 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9868 size(4);
9869 ins_encode %{
9870 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9871 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9872 %}
9873 ins_pipe(pipe_class_default);
9874 %}
9875
9876 // Float to Int conversion, NaN is mapped to 0.
9877 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9878 match(Set dst (ConvF2I src));
9879 ins_cost(DEFAULT_COST);
9880
9881 expand %{
9882 regF tmpF;
9883 stackSlotL tmpS;
9884 flagsReg crx;
9885 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
9886 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated).
9887 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
9888 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9889 %}
9890 %}
9891
9892 // Convert to Long
9893
9894 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9895 match(Set dst (ConvI2L src));
9896 format %{ "EXTSW $dst, $src \t// int->long" %}
9897 size(4);
9898 ins_encode %{
9899 // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9900 __ extsw($dst$$Register, $src$$Register);
9901 %}
9902 ins_pipe(pipe_class_default);
9903 %}
9904
9905 // Zero-extend: convert unsigned int to long (convUI2L).
9906 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9907 match(Set dst (AndL (ConvI2L src) mask));
9908 ins_cost(DEFAULT_COST);
9909
9910 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9911 size(4);
9912 ins_encode %{
9913 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9914 __ clrldi($dst$$Register, $src$$Register, 32);
9915 %}
9916 ins_pipe(pipe_class_default);
9917 %}
9918
9919 // Zero-extend: convert unsigned int to long in long register.
9920 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9921 match(Set dst (AndL src mask));
9922 ins_cost(DEFAULT_COST);
9923
9924 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %}
9925 size(4);
9926 ins_encode %{
9927 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9928 __ clrldi($dst$$Register, $src$$Register, 32);
9929 %}
9930 ins_pipe(pipe_class_default);
9931 %}
9932
9933 instruct convF2LRaw_regF(regF dst, regF src) %{
9934 // no match-rule, false predicate
9935 effect(DEF dst, USE src);
9936 predicate(false);
9937
9938 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9939 size(4);
9940 ins_encode %{
9941 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9942 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9943 %}
9944 ins_pipe(pipe_class_default);
9945 %}
9946
9947 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9948 // no match-rule, false predicate
9949 effect(DEF dst, USE crx, USE src);
9950 predicate(false);
9951
9952 ins_variable_size_depending_on_alignment(true);
9953
9954 format %{ "cmovL $crx, $dst, $src" %}
9955 // Worst case is branch + move + stop, no stop without scheduler.
9956 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9957 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9958 ins_pipe(pipe_class_default);
9959 %}
9960
9961 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9962 // no match-rule, false predicate
9963 effect(DEF dst, USE crx, USE mem);
9964 predicate(false);
9965
9966 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %}
9967 postalloc_expand %{
9968 //
9969 // replaces
9970 //
9971 // region dst crx mem
9972 // \ | | /
9973 // dst=cmovL_bso_stackSlotL_conLvalue0
9974 //
9975 // with
9976 //
9977 // region dst
9978 // \ /
9979 // dst=loadConL16(0)
9980 // |
9981 // ^ region dst crx mem
9982 // | \ | | /
9983 // dst=cmovL_bso_stackSlotL
9984 //
9985
9986 // Create new nodes.
9987 MachNode *m1 = new loadConL16Node();
9988 MachNode *m2 = new cmovL_bso_stackSlotLNode();
9989
9990 // inputs for new nodes
9991 m1->add_req(n_region);
9992 m2->add_req(n_region, n_crx, n_mem);
9993 m2->add_prec(m1);
9994
9995 // operands for new nodes
9996 m1->_opnds[0] = op_dst;
9997 m1->_opnds[1] = new immL16Oper(0);
9998 m2->_opnds[0] = op_dst;
9999 m2->_opnds[1] = op_crx;
10000 m2->_opnds[2] = op_mem;
10001
10002 // registers for new nodes
10003 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10004 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10005
10006 // Insert new nodes.
10007 nodes->push(m1);
10008 nodes->push(m2);
10009 %}
10010 %}
10011
10012 // Float to Long conversion, NaN is mapped to 0.
10013 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10014 match(Set dst (ConvF2L src));
10015 ins_cost(DEFAULT_COST);
10016
10017 expand %{
10018 regF tmpF;
10019 stackSlotL tmpS;
10020 flagsReg crx;
10021 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10022 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated).
10023 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated).
10024 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10025 %}
10026 %}
10027
10028 instruct convD2LRaw_regD(regD dst, regD src) %{
10029 // no match-rule, false predicate
10030 effect(DEF dst, USE src);
10031 predicate(false);
10032
10033 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10034 size(4);
10035 ins_encode %{
10036 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10037 __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10038 %}
10039 ins_pipe(pipe_class_default);
10040 %}
10041
10042 // Double to Long conversion, NaN is mapped to 0.
10043 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10044 match(Set dst (ConvD2L src));
10045 ins_cost(DEFAULT_COST);
10046
10047 expand %{
10048 regD tmpD;
10049 stackSlotL tmpS;
10050 flagsReg crx;
10051 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN.
10052 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated).
10053 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated).
10054 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10055 %}
10056 %}
10057
10058 // Convert to Float
10059
10060 // Placed here as needed in expand.
10061 instruct convL2DRaw_regD(regD dst, regD src) %{
10062 // no match-rule, false predicate
10063 effect(DEF dst, USE src);
10064 predicate(false);
10065
10066 format %{ "FCFID $dst, $src \t// convL2D" %}
10067 size(4);
10068 ins_encode %{
10069 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10070 __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10071 %}
10072 ins_pipe(pipe_class_default);
10073 %}
10074
10075 // Placed here as needed in expand.
10076 instruct convD2F_reg(regF dst, regD src) %{
10077 match(Set dst (ConvD2F src));
10078 format %{ "FRSP $dst, $src \t// convD2F" %}
10079 size(4);
10080 ins_encode %{
10081 // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10082 __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10083 %}
10084 ins_pipe(pipe_class_default);
10085 %}
10086
10087 // Integer to Float conversion.
10088 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10089 match(Set dst (ConvI2F src));
10090 predicate(!VM_Version::has_fcfids());
10091 ins_cost(DEFAULT_COST);
10092
10093 expand %{
10094 iRegLdst tmpL;
10095 stackSlotL tmpS;
10096 regD tmpD;
10097 regD tmpD2;
10098 convI2L_reg(tmpL, src); // Sign-extension int to long.
10099 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10100 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10101 convL2DRaw_regD(tmpD2, tmpD); // Convert to double.
10102 convD2F_reg(dst, tmpD2); // Convert double to float.
10103 %}
10104 %}
10105
10106 instruct convL2FRaw_regF(regF dst, regD src) %{
10107 // no match-rule, false predicate
10108 effect(DEF dst, USE src);
10109 predicate(false);
10110
10111 format %{ "FCFIDS $dst, $src \t// convL2F" %}
10112 size(4);
10113 ins_encode %{
10114 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10115 __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10116 %}
10117 ins_pipe(pipe_class_default);
10118 %}
10119
10120 // Integer to Float conversion. Special version for Power7.
10121 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10122 match(Set dst (ConvI2F src));
10123 predicate(VM_Version::has_fcfids());
10124 ins_cost(DEFAULT_COST);
10125
10126 expand %{
10127 iRegLdst tmpL;
10128 stackSlotL tmpS;
10129 regD tmpD;
10130 convI2L_reg(tmpL, src); // Sign-extension int to long.
10131 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10132 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10133 convL2FRaw_regF(dst, tmpD); // Convert to float.
10134 %}
10135 %}
10136
10137 // L2F to avoid runtime call.
10138 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10139 match(Set dst (ConvL2F src));
10140 predicate(VM_Version::has_fcfids());
10141 ins_cost(DEFAULT_COST);
10142
10143 expand %{
10144 stackSlotL tmpS;
10145 regD tmpD;
10146 regL_to_stkL(tmpS, src); // Store long to stack.
10147 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10148 convL2FRaw_regF(dst, tmpD); // Convert to float.
10149 %}
10150 %}
10151
10152 // Moved up as used in expand.
10153 //instruct convD2F_reg(regF dst, regD src) %{%}
10154
10155 // Convert to Double
10156
10157 // Integer to Double conversion.
10158 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10159 match(Set dst (ConvI2D src));
10160 ins_cost(DEFAULT_COST);
10161
10162 expand %{
10163 iRegLdst tmpL;
10164 stackSlotL tmpS;
10165 regD tmpD;
10166 convI2L_reg(tmpL, src); // Sign-extension int to long.
10167 regL_to_stkL(tmpS, tmpL); // Store long to stack.
10168 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register.
10169 convL2DRaw_regD(dst, tmpD); // Convert to double.
10170 %}
10171 %}
10172
10173 // Long to Double conversion
10174 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10175 match(Set dst (ConvL2D src));
10176 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10177
10178 expand %{
10179 regD tmpD;
10180 moveL2D_stack_reg(tmpD, src);
10181 convL2DRaw_regD(dst, tmpD);
10182 %}
10183 %}
10184
10185 instruct convF2D_reg(regD dst, regF src) %{
10186 match(Set dst (ConvF2D src));
10187 format %{ "FMR $dst, $src \t// float->double" %}
10188 // variable size, 0 or 4
10189 ins_encode %{
10190 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10191 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10192 %}
10193 ins_pipe(pipe_class_default);
10194 %}
10195
10196 //----------Control Flow Instructions------------------------------------------
10197 // Compare Instructions
10198
10199 // Compare Integers
10200 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10201 match(Set crx (CmpI src1 src2));
10202 size(4);
10203 format %{ "CMPW $crx, $src1, $src2" %}
10204 ins_encode %{
10205 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10206 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10207 %}
10208 ins_pipe(pipe_class_compare);
10209 %}
10210
10211 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10212 match(Set crx (CmpI src1 src2));
10213 format %{ "CMPWI $crx, $src1, $src2" %}
10214 size(4);
10215 ins_encode %{
10216 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10217 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10218 %}
10219 ins_pipe(pipe_class_compare);
10220 %}
10221
10222 // (src1 & src2) == 0?
10223 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10224 match(Set cr0 (CmpI (AndI src1 src2) zero));
10225 // r0 is killed
10226 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %}
10227 size(4);
10228 ins_encode %{
10229 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10230 __ andi_(R0, $src1$$Register, $src2$$constant);
10231 %}
10232 ins_pipe(pipe_class_compare);
10233 %}
10234
10235 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10236 match(Set crx (CmpL src1 src2));
10237 format %{ "CMPD $crx, $src1, $src2" %}
10238 size(4);
10239 ins_encode %{
10240 // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10241 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10242 %}
10243 ins_pipe(pipe_class_compare);
10244 %}
10245
10246 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10247 match(Set crx (CmpL src1 src2));
10248 format %{ "CMPDI $crx, $src1, $src2" %}
10249 size(4);
10250 ins_encode %{
10251 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10252 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10253 %}
10254 ins_pipe(pipe_class_compare);
10255 %}
10256
10257 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10258 match(Set cr0 (CmpL (AndL src1 src2) zero));
10259 // r0 is killed
10260 format %{ "AND R0, $src1, $src2 \t// BTST long" %}
10261 size(4);
10262 ins_encode %{
10263 // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10264 __ and_(R0, $src1$$Register, $src2$$Register);
10265 %}
10266 ins_pipe(pipe_class_compare);
10267 %}
10268
10269 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10270 match(Set cr0 (CmpL (AndL src1 src2) zero));
10271 // r0 is killed
10272 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %}
10273 size(4);
10274 ins_encode %{
10275 // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10276 __ andi_(R0, $src1$$Register, $src2$$constant);
10277 %}
10278 ins_pipe(pipe_class_compare);
10279 %}
10280
10281 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10282 // no match-rule, false predicate
10283 effect(DEF dst, USE crx);
10284 predicate(false);
10285
10286 ins_variable_size_depending_on_alignment(true);
10287
10288 format %{ "cmovI $crx, $dst, -1, 0, +1" %}
10289 // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10290 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10291 ins_encode %{
10292 // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10293 Label done;
10294 // li(Rdst, 0); // equal -> 0
10295 __ beq($crx$$CondRegister, done);
10296 __ li($dst$$Register, 1); // greater -> +1
10297 __ bgt($crx$$CondRegister, done);
10298 __ li($dst$$Register, -1); // unordered or less -> -1
10299 // TODO: PPC port__ endgroup_if_needed(_size == 20);
10300 __ bind(done);
10301 %}
10302 ins_pipe(pipe_class_compare);
10303 %}
10304
10305 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10306 // no match-rule, false predicate
10307 effect(DEF dst, USE crx);
10308 predicate(false);
10309
10310 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10311 postalloc_expand %{
10312 //
10313 // replaces
10314 //
10315 // region crx
10316 // \ |
10317 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10318 //
10319 // with
10320 //
10321 // region
10322 // \
10323 // dst=loadConI16(0)
10324 // |
10325 // ^ region crx
10326 // | \ |
10327 // dst=cmovI_conIvalueMinus1_conIvalue1
10328 //
10329
10330 // Create new nodes.
10331 MachNode *m1 = new loadConI16Node();
10332 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10333
10334 // inputs for new nodes
10335 m1->add_req(n_region);
10336 m2->add_req(n_region, n_crx);
10337 m2->add_prec(m1);
10338
10339 // operands for new nodes
10340 m1->_opnds[0] = op_dst;
10341 m1->_opnds[1] = new immI16Oper(0);
10342 m2->_opnds[0] = op_dst;
10343 m2->_opnds[1] = op_crx;
10344
10345 // registers for new nodes
10346 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10347 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10348
10349 // Insert new nodes.
10350 nodes->push(m1);
10351 nodes->push(m2);
10352 %}
10353 %}
10354
10355 // Manifest a CmpL3 result in an integer register. Very painful.
10356 // This is the test to avoid.
10357 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10358 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10359 match(Set dst (CmpL3 src1 src2));
10360 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10361
10362 expand %{
10363 flagsReg tmp1;
10364 cmpL_reg_reg(tmp1, src1, src2);
10365 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10366 %}
10367 %}
10368
10369 // Implicit range checks.
10370 // A range check in the ideal world has one of the following shapes:
10371 // - (If le (CmpU length index)), (IfTrue throw exception)
10372 // - (If lt (CmpU index length)), (IfFalse throw exception)
10373 //
10374 // Match range check 'If le (CmpU length index)'.
10375 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10376 match(If cmp (CmpU src_length index));
10377 effect(USE labl);
10378 predicate(TrapBasedRangeChecks &&
10379 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10380 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10381 (Matcher::branches_to_uncommon_trap(_leaf)));
10382
10383 ins_is_TrapBasedCheckNode(true);
10384
10385 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10386 size(4);
10387 ins_encode %{
10388 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10389 if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10390 __ trap_range_check_le($src_length$$Register, $index$$constant);
10391 } else {
10392 // Both successors are uncommon traps, probability is 0.
10393 // Node got flipped during fixup flow.
10394 assert($cmp$$cmpcode == 0x9, "must be greater");
10395 __ trap_range_check_g($src_length$$Register, $index$$constant);
10396 }
10397 %}
10398 ins_pipe(pipe_class_trap);
10399 %}
10400
10401 // Match range check 'If lt (CmpU index length)'.
10402 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10403 match(If cmp (CmpU src_index src_length));
10404 effect(USE labl);
10405 predicate(TrapBasedRangeChecks &&
10406 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10407 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10408 (Matcher::branches_to_uncommon_trap(_leaf)));
10409
10410 ins_is_TrapBasedCheckNode(true);
10411
10412 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10413 size(4);
10414 ins_encode %{
10415 // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10416 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10417 __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10418 } else {
10419 // Both successors are uncommon traps, probability is 0.
10420 // Node got flipped during fixup flow.
10421 assert($cmp$$cmpcode == 0x8, "must be less");
10422 __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10423 }
10424 %}
10425 ins_pipe(pipe_class_trap);
10426 %}
10427
10428 // Match range check 'If lt (CmpU index length)'.
10429 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10430 match(If cmp (CmpU src_index length));
10431 effect(USE labl);
10432 predicate(TrapBasedRangeChecks &&
10433 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10434 _leaf->as_If()->_prob >= PROB_ALWAYS &&
10435 (Matcher::branches_to_uncommon_trap(_leaf)));
10436
10437 ins_is_TrapBasedCheckNode(true);
10438
10439 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10440 size(4);
10441 ins_encode %{
10442 // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10443 if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10444 __ trap_range_check_ge($src_index$$Register, $length$$constant);
10445 } else {
10446 // Both successors are uncommon traps, probability is 0.
10447 // Node got flipped during fixup flow.
10448 assert($cmp$$cmpcode == 0x8, "must be less");
10449 __ trap_range_check_l($src_index$$Register, $length$$constant);
10450 }
10451 %}
10452 ins_pipe(pipe_class_trap);
10453 %}
10454
10455 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10456 match(Set crx (CmpU src1 src2));
10457 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %}
10458 size(4);
10459 ins_encode %{
10460 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10461 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10462 %}
10463 ins_pipe(pipe_class_compare);
10464 %}
10465
10466 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10467 match(Set crx (CmpU src1 src2));
10468 size(4);
10469 format %{ "CMPLWI $crx, $src1, $src2" %}
10470 ins_encode %{
10471 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10472 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10473 %}
10474 ins_pipe(pipe_class_compare);
10475 %}
10476
10477 // Implicit zero checks (more implicit null checks).
10478 // No constant pool entries required.
10479 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10480 match(If cmp (CmpN value zero));
10481 effect(USE labl);
10482 predicate(TrapBasedNullChecks &&
10483 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10484 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10485 Matcher::branches_to_uncommon_trap(_leaf));
10486 ins_cost(1);
10487
10488 ins_is_TrapBasedCheckNode(true);
10489
10490 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10491 size(4);
10492 ins_encode %{
10493 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10494 if ($cmp$$cmpcode == 0xA) {
10495 __ trap_null_check($value$$Register);
10496 } else {
10497 // Both successors are uncommon traps, probability is 0.
10498 // Node got flipped during fixup flow.
10499 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10500 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10501 }
10502 %}
10503 ins_pipe(pipe_class_trap);
10504 %}
10505
10506 // Compare narrow oops.
10507 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10508 match(Set crx (CmpN src1 src2));
10509
10510 size(4);
10511 ins_cost(2);
10512 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %}
10513 ins_encode %{
10514 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10515 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10516 %}
10517 ins_pipe(pipe_class_compare);
10518 %}
10519
10520 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10521 match(Set crx (CmpN src1 src2));
10522 // Make this more expensive than zeroCheckN_iReg_imm0.
10523 ins_cost(2);
10524
10525 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %}
10526 size(4);
10527 ins_encode %{
10528 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10529 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10530 %}
10531 ins_pipe(pipe_class_compare);
10532 %}
10533
10534 // Implicit zero checks (more implicit null checks).
10535 // No constant pool entries required.
10536 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10537 match(If cmp (CmpP value zero));
10538 effect(USE labl);
10539 predicate(TrapBasedNullChecks &&
10540 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10541 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10542 Matcher::branches_to_uncommon_trap(_leaf));
10543 ins_cost(1); // Should not be cheaper than zeroCheckN.
10544
10545 ins_is_TrapBasedCheckNode(true);
10546
10547 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10548 size(4);
10549 ins_encode %{
10550 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10551 if ($cmp$$cmpcode == 0xA) {
10552 __ trap_null_check($value$$Register);
10553 } else {
10554 // Both successors are uncommon traps, probability is 0.
10555 // Node got flipped during fixup flow.
10556 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10557 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10558 }
10559 %}
10560 ins_pipe(pipe_class_trap);
10561 %}
10562
10563 // Compare Pointers
10564 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10565 match(Set crx (CmpP src1 src2));
10566 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %}
10567 size(4);
10568 ins_encode %{
10569 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10570 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10571 %}
10572 ins_pipe(pipe_class_compare);
10573 %}
10574
10575 // Used in postalloc expand.
10576 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10577 // This match rule prevents reordering of node before a safepoint.
10578 // This only makes sense if this instructions is used exclusively
10579 // for the expansion of EncodeP!
10580 match(Set crx (CmpP src1 src2));
10581 predicate(false);
10582
10583 format %{ "CMPDI $crx, $src1, $src2" %}
10584 size(4);
10585 ins_encode %{
10586 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10587 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10588 %}
10589 ins_pipe(pipe_class_compare);
10590 %}
10591
10592 //----------Float Compares----------------------------------------------------
10593
10594 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10595 // Needs matchrule, see cmpDUnordered.
10596 match(Set crx (CmpF src1 src2));
10597 // no match-rule, false predicate
10598 predicate(false);
10599
10600 format %{ "cmpFUrd $crx, $src1, $src2" %}
10601 size(4);
10602 ins_encode %{
10603 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10604 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10605 %}
10606 ins_pipe(pipe_class_default);
10607 %}
10608
10609 instruct cmov_bns_less(flagsReg crx) %{
10610 // no match-rule, false predicate
10611 effect(DEF crx);
10612 predicate(false);
10613
10614 ins_variable_size_depending_on_alignment(true);
10615
10616 format %{ "cmov $crx" %}
10617 // Worst case is branch + move + stop, no stop without scheduler.
10618 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10619 ins_encode %{
10620 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10621 Label done;
10622 __ bns($crx$$CondRegister, done); // not unordered -> keep crx
10623 __ li(R0, 0);
10624 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less'
10625 // TODO PPC port __ endgroup_if_needed(_size == 16);
10626 __ bind(done);
10627 %}
10628 ins_pipe(pipe_class_default);
10629 %}
10630
10631 // Compare floating, generate condition code.
10632 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10633 // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10634 //
10635 // The following code sequence occurs a lot in mpegaudio:
10636 //
10637 // block BXX:
10638 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10639 // cmpFUrd CCR6, F11, F9
10640 // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10641 // cmov CCR6
10642 // 8: instruct branchConSched:
10643 // B_FARle CCR6, B56 P=0.500000 C=-1.000000
10644 match(Set crx (CmpF src1 src2));
10645 ins_cost(DEFAULT_COST+BRANCH_COST);
10646
10647 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %}
10648 postalloc_expand %{
10649 //
10650 // replaces
10651 //
10652 // region src1 src2
10653 // \ | |
10654 // crx=cmpF_reg_reg
10655 //
10656 // with
10657 //
10658 // region src1 src2
10659 // \ | |
10660 // crx=cmpFUnordered_reg_reg
10661 // |
10662 // ^ region
10663 // | \
10664 // crx=cmov_bns_less
10665 //
10666
10667 // Create new nodes.
10668 MachNode *m1 = new cmpFUnordered_reg_regNode();
10669 MachNode *m2 = new cmov_bns_lessNode();
10670
10671 // inputs for new nodes
10672 m1->add_req(n_region, n_src1, n_src2);
10673 m2->add_req(n_region);
10674 m2->add_prec(m1);
10675
10676 // operands for new nodes
10677 m1->_opnds[0] = op_crx;
10678 m1->_opnds[1] = op_src1;
10679 m1->_opnds[2] = op_src2;
10680 m2->_opnds[0] = op_crx;
10681
10682 // registers for new nodes
10683 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10684 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10685
10686 // Insert new nodes.
10687 nodes->push(m1);
10688 nodes->push(m2);
10689 %}
10690 %}
10691
10692 // Compare float, generate -1,0,1
10693 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10694 match(Set dst (CmpF3 src1 src2));
10695 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10696
10697 expand %{
10698 flagsReg tmp1;
10699 cmpFUnordered_reg_reg(tmp1, src1, src2);
10700 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10701 %}
10702 %}
10703
10704 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10705 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10706 // node right before the conditional move using it.
10707 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10708 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10709 // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10710 // conditional move was supposed to be spilled.
10711 match(Set crx (CmpD src1 src2));
10712 // False predicate, shall not be matched.
10713 predicate(false);
10714
10715 format %{ "cmpFUrd $crx, $src1, $src2" %}
10716 size(4);
10717 ins_encode %{
10718 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10719 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10720 %}
10721 ins_pipe(pipe_class_default);
10722 %}
10723
10724 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10725 match(Set crx (CmpD src1 src2));
10726 ins_cost(DEFAULT_COST+BRANCH_COST);
10727
10728 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %}
10729 postalloc_expand %{
10730 //
10731 // replaces
10732 //
10733 // region src1 src2
10734 // \ | |
10735 // crx=cmpD_reg_reg
10736 //
10737 // with
10738 //
10739 // region src1 src2
10740 // \ | |
10741 // crx=cmpDUnordered_reg_reg
10742 // |
10743 // ^ region
10744 // | \
10745 // crx=cmov_bns_less
10746 //
10747
10748 // create new nodes
10749 MachNode *m1 = new cmpDUnordered_reg_regNode();
10750 MachNode *m2 = new cmov_bns_lessNode();
10751
10752 // inputs for new nodes
10753 m1->add_req(n_region, n_src1, n_src2);
10754 m2->add_req(n_region);
10755 m2->add_prec(m1);
10756
10757 // operands for new nodes
10758 m1->_opnds[0] = op_crx;
10759 m1->_opnds[1] = op_src1;
10760 m1->_opnds[2] = op_src2;
10761 m2->_opnds[0] = op_crx;
10762
10763 // registers for new nodes
10764 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10765 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10766
10767 // Insert new nodes.
10768 nodes->push(m1);
10769 nodes->push(m2);
10770 %}
10771 %}
10772
10773 // Compare double, generate -1,0,1
10774 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10775 match(Set dst (CmpD3 src1 src2));
10776 ins_cost(DEFAULT_COST*5+BRANCH_COST);
10777
10778 expand %{
10779 flagsReg tmp1;
10780 cmpDUnordered_reg_reg(tmp1, src1, src2);
10781 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10782 %}
10783 %}
10784
10785 //----------Branches---------------------------------------------------------
10786 // Jump
10787
10788 // Direct Branch.
10789 instruct branch(label labl) %{
10790 match(Goto);
10791 effect(USE labl);
10792 ins_cost(BRANCH_COST);
10793
10794 format %{ "B $labl" %}
10795 size(4);
10796 ins_encode %{
10797 // TODO: PPC port $archOpcode(ppc64Opcode_b);
10798 Label d; // dummy
10799 __ bind(d);
10800 Label* p = $labl$$label;
10801 // `p' is `NULL' when this encoding class is used only to
10802 // determine the size of the encoded instruction.
10803 Label& l = (NULL == p)? d : *(p);
10804 __ b(l);
10805 %}
10806 ins_pipe(pipe_class_default);
10807 %}
10808
10809 // Conditional Near Branch
10810 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10811 // Same match rule as `branchConFar'.
10812 match(If cmp crx);
10813 effect(USE lbl);
10814 ins_cost(BRANCH_COST);
10815
10816 // If set to 1 this indicates that the current instruction is a
10817 // short variant of a long branch. This avoids using this
10818 // instruction in first-pass matching. It will then only be used in
10819 // the `Shorten_branches' pass.
10820 ins_short_branch(1);
10821
10822 format %{ "B$cmp $crx, $lbl" %}
10823 size(4);
10824 ins_encode( enc_bc(crx, cmp, lbl) );
10825 ins_pipe(pipe_class_default);
10826 %}
10827
10828 // This is for cases when the ppc64 `bc' instruction does not
10829 // reach far enough. So we emit a far branch here, which is more
10830 // expensive.
10831 //
10832 // Conditional Far Branch
10833 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10834 // Same match rule as `branchCon'.
10835 match(If cmp crx);
10836 effect(USE crx, USE lbl);
10837 predicate(!false /* TODO: PPC port HB_Schedule*/);
10838 // Higher cost than `branchCon'.
10839 ins_cost(5*BRANCH_COST);
10840
10841 // This is not a short variant of a branch, but the long variant.
10842 ins_short_branch(0);
10843
10844 format %{ "B_FAR$cmp $crx, $lbl" %}
10845 size(8);
10846 ins_encode( enc_bc_far(crx, cmp, lbl) );
10847 ins_pipe(pipe_class_default);
10848 %}
10849
10850 // Conditional Branch used with Power6 scheduler (can be far or short).
10851 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10852 // Same match rule as `branchCon'.
10853 match(If cmp crx);
10854 effect(USE crx, USE lbl);
10855 predicate(false /* TODO: PPC port HB_Schedule*/);
10856 // Higher cost than `branchCon'.
10857 ins_cost(5*BRANCH_COST);
10858
10859 // Actually size doesn't depend on alignment but on shortening.
10860 ins_variable_size_depending_on_alignment(true);
10861 // long variant.
10862 ins_short_branch(0);
10863
10864 format %{ "B_FAR$cmp $crx, $lbl" %}
10865 size(8); // worst case
10866 ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10867 ins_pipe(pipe_class_default);
10868 %}
10869
10870 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10871 match(CountedLoopEnd cmp crx);
10872 effect(USE labl);
10873 ins_cost(BRANCH_COST);
10874
10875 // short variant.
10876 ins_short_branch(1);
10877
10878 format %{ "B$cmp $crx, $labl \t// counted loop end" %}
10879 size(4);
10880 ins_encode( enc_bc(crx, cmp, labl) );
10881 ins_pipe(pipe_class_default);
10882 %}
10883
10884 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10885 match(CountedLoopEnd cmp crx);
10886 effect(USE labl);
10887 predicate(!false /* TODO: PPC port HB_Schedule */);
10888 ins_cost(BRANCH_COST);
10889
10890 // Long variant.
10891 ins_short_branch(0);
10892
10893 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10894 size(8);
10895 ins_encode( enc_bc_far(crx, cmp, labl) );
10896 ins_pipe(pipe_class_default);
10897 %}
10898
10899 // Conditional Branch used with Power6 scheduler (can be far or short).
10900 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10901 match(CountedLoopEnd cmp crx);
10902 effect(USE labl);
10903 predicate(false /* TODO: PPC port HB_Schedule */);
10904 // Higher cost than `branchCon'.
10905 ins_cost(5*BRANCH_COST);
10906
10907 // Actually size doesn't depend on alignment but on shortening.
10908 ins_variable_size_depending_on_alignment(true);
10909 // Long variant.
10910 ins_short_branch(0);
10911
10912 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10913 size(8); // worst case
10914 ins_encode( enc_bc_short_far(crx, cmp, labl) );
10915 ins_pipe(pipe_class_default);
10916 %}
10917
10918 // ============================================================================
10919 // Java runtime operations, intrinsics and other complex operations.
10920
10921 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10922 // array for an instance of the superklass. Set a hidden internal cache on a
10923 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10924 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10925 //
10926 // GL TODO: Improve this.
10927 // - result should not be a TEMP
10928 // - Add match rule as on sparc avoiding additional Cmp.
10929 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10930 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10931 match(Set result (PartialSubtypeCheck subklass superklass));
10932 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10933 ins_cost(DEFAULT_COST*10);
10934
10935 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10936 ins_encode %{
10937 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10938 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10939 $tmp_klass$$Register, NULL, $result$$Register);
10940 %}
10941 ins_pipe(pipe_class_default);
10942 %}
10943
10944 // inlined locking and unlocking
10945
10946 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10947 match(Set crx (FastLock oop box));
10948 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10949 predicate(!Compile::current()->use_rtm());
10950
10951 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3" %}
10952 ins_encode %{
10953 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10954 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10955 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10956 UseBiasedLocking && !UseOptoBiasInlining); // SAPJVM MD 2014-11-06 UseOptoBiasInlining
10957 // If locking was successfull, crx should indicate 'EQ'.
10958 // The compiler generates a branch to the runtime call to
10959 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10960 %}
10961 ins_pipe(pipe_class_compare);
10962 %}
10963
10964 // Separate version for TM. Use bound register for box to enable USE_KILL.
10965 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10966 match(Set crx (FastLock oop box));
10967 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10968 predicate(Compile::current()->use_rtm());
10969
10970 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10971 ins_encode %{
10972 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10973 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10974 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10975 /*Biased Locking*/ false,
10976 _rtm_counters, _stack_rtm_counters,
10977 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10978 /*TM*/ true, ra_->C->profile_rtm());
10979 // If locking was successfull, crx should indicate 'EQ'.
10980 // The compiler generates a branch to the runtime call to
10981 // _complete_monitor_locking_Java for the case where crx is 'NE'.
10982 %}
10983 ins_pipe(pipe_class_compare);
10984 %}
10985
10986 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10987 match(Set crx (FastUnlock oop box));
10988 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10989 predicate(!Compile::current()->use_rtm());
10990
10991 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %}
10992 ins_encode %{
10993 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10994 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10995 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
10996 UseBiasedLocking && !UseOptoBiasInlining,
10997 false);
10998 // If unlocking was successfull, crx should indicate 'EQ'.
10999 // The compiler generates a branch to the runtime call to
11000 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11001 %}
11002 ins_pipe(pipe_class_compare);
11003 %}
11004
11005 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
11006 match(Set crx (FastUnlock oop box));
11007 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
11008 predicate(Compile::current()->use_rtm());
11009
11010 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %}
11011 ins_encode %{
11012 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11013 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
11014 $tmp3$$Register, $tmp1$$Register, $tmp2$$Register,
11015 /*Biased Locking*/ false, /*TM*/ true);
11016 // If unlocking was successfull, crx should indicate 'EQ'.
11017 // The compiler generates a branch to the runtime call to
11018 // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
11019 %}
11020 ins_pipe(pipe_class_compare);
11021 %}
11022
11023 // Align address.
11024 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11025 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11026
11027 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %}
11028 size(4);
11029 ins_encode %{
11030 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11031 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11032 %}
11033 ins_pipe(pipe_class_default);
11034 %}
11035
11036 // Array size computation.
11037 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11038 match(Set dst (SubL (CastP2X end) (CastP2X start)));
11039
11040 format %{ "SUB $dst, $end, $start \t// array size in bytes" %}
11041 size(4);
11042 ins_encode %{
11043 // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11044 __ subf($dst$$Register, $start$$Register, $end$$Register);
11045 %}
11046 ins_pipe(pipe_class_default);
11047 %}
11048
11049 // Clear-array with dynamic array-size.
11050 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11051 match(Set dummy (ClearArray cnt base));
11052 effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11053 ins_cost(MEMORY_REF_COST);
11054
11055 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11056
11057 format %{ "ClearArray $cnt, $base" %}
11058 ins_encode %{
11059 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11060 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11061 %}
11062 ins_pipe(pipe_class_default);
11063 %}
11064
11065 // String_IndexOf for needle of length 1.
11066 //
11067 // Match needle into immediate operands: no loadConP node needed. Saves one
11068 // register and two instructions over string_indexOf_imm1Node.
11069 //
11070 // Assumes register result differs from all input registers.
11071 //
11072 // Preserves registers haystack, haycnt
11073 // Kills registers tmp1, tmp2
11074 // Defines registers result
11075 //
11076 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11077 //
11078 // Unfortunately this does not match too often. In many situations the AddP is used
11079 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11080 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11081 immP needleImm, immL offsetImm, immI_1 needlecntImm,
11082 iRegIdst tmp1, iRegIdst tmp2,
11083 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11084 predicate(SpecialStringIndexOf); // type check implicit by parameter type, See Matcher::match_rule_supported
11085 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11086
11087 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1);
11088
11089 ins_cost(150);
11090 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11091 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11092
11093 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11094 ins_encode %{
11095 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11096 immPOper *needleOper = (immPOper *)$needleImm;
11097 const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11098 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char *
11099
11100 __ string_indexof_1($result$$Register,
11101 $haystack$$Register, $haycnt$$Register,
11102 R0, needle_values->char_at(0),
11103 $tmp1$$Register, $tmp2$$Register);
11104 %}
11105 ins_pipe(pipe_class_compare);
11106 %}
11107
11108 // String_IndexOf for needle of length 1.
11109 //
11110 // Special case requires less registers and emits less instructions.
11111 //
11112 // Assumes register result differs from all input registers.
11113 //
11114 // Preserves registers haystack, haycnt
11115 // Kills registers tmp1, tmp2, needle
11116 // Defines registers result
11117 //
11118 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11119 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11120 rscratch2RegP needle, immI_1 needlecntImm,
11121 iRegIdst tmp1, iRegIdst tmp2,
11122 flagsRegCR0 cr0, flagsRegCR1 cr1) %{
11123 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11124 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11125 TEMP tmp1, TEMP tmp2);
11126 // Required for EA: check if it is still a type_array.
11127 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11128 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11129 ins_cost(180);
11130
11131 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11132
11133 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11134 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11135 ins_encode %{
11136 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11137 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11138 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11139 guarantee(needle_values, "sanity");
11140 if (needle_values != NULL) {
11141 __ string_indexof_1($result$$Register,
11142 $haystack$$Register, $haycnt$$Register,
11143 R0, needle_values->char_at(0),
11144 $tmp1$$Register, $tmp2$$Register);
11145 } else {
11146 __ string_indexof_1($result$$Register,
11147 $haystack$$Register, $haycnt$$Register,
11148 $needle$$Register, 0,
11149 $tmp1$$Register, $tmp2$$Register);
11150 }
11151 %}
11152 ins_pipe(pipe_class_compare);
11153 %}
11154
11155 // String_IndexOf.
11156 //
11157 // Length of needle as immediate. This saves instruction loading constant needle
11158 // length.
11159 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11160 // completely or do it in vector instruction. This should save registers for
11161 // needlecnt and needle.
11162 //
11163 // Assumes register result differs from all input registers.
11164 // Overwrites haycnt, needlecnt.
11165 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11166 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11167 iRegPsrc needle, uimmI15 needlecntImm,
11168 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11169 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11170 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11171 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11172 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6);
11173 // Required for EA: check if it is still a type_array.
11174 predicate(SpecialStringIndexOf && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11175 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11176 ins_cost(250);
11177
11178 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11179
11180 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11181 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11182 ins_encode %{
11183 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11184 Node *ndl = in(operand_index($needle)); // The node that defines needle.
11185 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11186
11187 __ string_indexof($result$$Register,
11188 $haystack$$Register, $haycnt$$Register,
11189 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11190 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11191 %}
11192 ins_pipe(pipe_class_compare);
11193 %}
11194
11195 // StrIndexOf node.
11196 //
11197 // Assumes register result differs from all input registers.
11198 // Overwrites haycnt, needlecnt.
11199 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11200 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11201 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11202 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6) %{
11203 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11204 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11205 TEMP_DEF result,
11206 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6);
11207 predicate(SpecialStringIndexOf); // See Matcher::match_rule_supported.
11208 ins_cost(300);
11209
11210 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11211
11212 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11213 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11214 ins_encode %{
11215 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11216 __ string_indexof($result$$Register,
11217 $haystack$$Register, $haycnt$$Register,
11218 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant.
11219 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11220 %}
11221 ins_pipe(pipe_class_compare);
11222 %}
11223
11224 // String equals with immediate.
11225 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11226 iRegPdst tmp1, iRegPdst tmp2,
11227 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11228 match(Set result (StrEquals (Binary str1 str2) cntImm));
11229 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11230 KILL cr0, KILL cr6, KILL ctr);
11231 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11232 ins_cost(250);
11233
11234 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11235
11236 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11237 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11238 ins_encode %{
11239 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11240 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11241 $result$$Register, $tmp1$$Register, $tmp2$$Register);
11242 %}
11243 ins_pipe(pipe_class_compare);
11244 %}
11245
11246 // String equals.
11247 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11248 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11249 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11250 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11251 match(Set result (StrEquals (Binary str1 str2) cnt));
11252 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11253 KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11254 predicate(SpecialStringEquals); // See Matcher::match_rule_supported.
11255 ins_cost(300);
11256
11257 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11258
11259 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11260 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11261 ins_encode %{
11262 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11263 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11264 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11265 %}
11266 ins_pipe(pipe_class_compare);
11267 %}
11268
11269 // String compare.
11270 // Char[] pointers are passed in.
11271 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11272 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11273 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11274 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11275 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11276 ins_cost(300);
11277
11278 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11279
11280 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11281 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11282 ins_encode %{
11283 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11284 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11285 $result$$Register, $tmp$$Register);
11286 %}
11287 ins_pipe(pipe_class_compare);
11288 %}
11289
11290 //---------- Min/Max Instructions ---------------------------------------------
11291
11292 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11293 match(Set dst (MinI src1 src2));
11294 ins_cost(DEFAULT_COST*6);
11295
11296 expand %{
11297 iRegLdst src1s;
11298 iRegLdst src2s;
11299 iRegLdst diff;
11300 iRegLdst sm;
11301 iRegLdst doz; // difference or zero
11302 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11303 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11304 subL_reg_reg(diff, src2s, src1s);
11305 // Need to consider >=33 bit result, therefore we need signmaskL.
11306 signmask64L_regL(sm, diff);
11307 andL_reg_reg(doz, diff, sm); // <=0
11308 addI_regL_regL(dst, doz, src1s);
11309 %}
11310 %}
11311
11312 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11313 match(Set dst (MaxI src1 src2));
11314 ins_cost(DEFAULT_COST*6);
11315
11316 expand %{
11317 iRegLdst src1s;
11318 iRegLdst src2s;
11319 iRegLdst diff;
11320 iRegLdst sm;
11321 iRegLdst doz; // difference or zero
11322 convI2L_reg(src1s, src1); // Ensure proper sign extension.
11323 convI2L_reg(src2s, src2); // Ensure proper sign extension.
11324 subL_reg_reg(diff, src2s, src1s);
11325 // Need to consider >=33 bit result, therefore we need signmaskL.
11326 signmask64L_regL(sm, diff);
11327 andcL_reg_reg(doz, diff, sm); // >=0
11328 addI_regL_regL(dst, doz, src1s);
11329 %}
11330 %}
11331
11332 //---------- Population Count Instructions ------------------------------------
11333
11334 // Popcnt for Power7.
11335 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11336 match(Set dst (PopCountI src));
11337 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11338 ins_cost(DEFAULT_COST);
11339
11340 format %{ "POPCNTW $dst, $src" %}
11341 size(4);
11342 ins_encode %{
11343 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11344 __ popcntw($dst$$Register, $src$$Register);
11345 %}
11346 ins_pipe(pipe_class_default);
11347 %}
11348
11349 // Popcnt for Power7.
11350 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11351 predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11352 match(Set dst (PopCountL src));
11353 ins_cost(DEFAULT_COST);
11354
11355 format %{ "POPCNTD $dst, $src" %}
11356 size(4);
11357 ins_encode %{
11358 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11359 __ popcntd($dst$$Register, $src$$Register);
11360 %}
11361 ins_pipe(pipe_class_default);
11362 %}
11363
11364 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11365 match(Set dst (CountLeadingZerosI src));
11366 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11367 ins_cost(DEFAULT_COST);
11368
11369 format %{ "CNTLZW $dst, $src" %}
11370 size(4);
11371 ins_encode %{
11372 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
11373 __ cntlzw($dst$$Register, $src$$Register);
11374 %}
11375 ins_pipe(pipe_class_default);
11376 %}
11377
11378 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
11379 match(Set dst (CountLeadingZerosL src));
11380 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported.
11381 ins_cost(DEFAULT_COST);
11382
11383 format %{ "CNTLZD $dst, $src" %}
11384 size(4);
11385 ins_encode %{
11386 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11387 __ cntlzd($dst$$Register, $src$$Register);
11388 %}
11389 ins_pipe(pipe_class_default);
11390 %}
11391
11392 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
11393 // no match-rule, false predicate
11394 effect(DEF dst, USE src);
11395 predicate(false);
11396
11397 format %{ "CNTLZD $dst, $src" %}
11398 size(4);
11399 ins_encode %{
11400 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
11401 __ cntlzd($dst$$Register, $src$$Register);
11402 %}
11403 ins_pipe(pipe_class_default);
11404 %}
11405
11406 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
11407 match(Set dst (CountTrailingZerosI src));
11408 predicate(UseCountLeadingZerosInstructionsPPC64);
11409 ins_cost(DEFAULT_COST);
11410
11411 expand %{
11412 immI16 imm1 %{ (int)-1 %}
11413 immI16 imm2 %{ (int)32 %}
11414 immI_minus1 m1 %{ -1 %}
11415 iRegIdst tmpI1;
11416 iRegIdst tmpI2;
11417 iRegIdst tmpI3;
11418 addI_reg_imm16(tmpI1, src, imm1);
11419 andcI_reg_reg(tmpI2, src, m1, tmpI1);
11420 countLeadingZerosI(tmpI3, tmpI2);
11421 subI_imm16_reg(dst, imm2, tmpI3);
11422 %}
11423 %}
11424
11425 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
11426 match(Set dst (CountTrailingZerosL src));
11427 predicate(UseCountLeadingZerosInstructionsPPC64);
11428 ins_cost(DEFAULT_COST);
11429
11430 expand %{
11431 immL16 imm1 %{ (long)-1 %}
11432 immI16 imm2 %{ (int)64 %}
11433 iRegLdst tmpL1;
11434 iRegLdst tmpL2;
11435 iRegIdst tmpL3;
11436 addL_reg_imm16(tmpL1, src, imm1);
11437 andcL_reg_reg(tmpL2, tmpL1, src);
11438 countLeadingZerosL(tmpL3, tmpL2);
11439 subI_imm16_reg(dst, imm2, tmpL3);
11440 %}
11441 %}
11442
11443 // Expand nodes for byte_reverse_int.
11444 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11445 effect(DEF dst, USE src, USE pos, USE shift);
11446 predicate(false);
11447
11448 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11449 size(4);
11450 ins_encode %{
11451 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11452 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11453 %}
11454 ins_pipe(pipe_class_default);
11455 %}
11456
11457 // As insrwi_a, but with USE_DEF.
11458 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
11459 effect(USE_DEF dst, USE src, USE pos, USE shift);
11460 predicate(false);
11461
11462 format %{ "INSRWI $dst, $src, $pos, $shift" %}
11463 size(4);
11464 ins_encode %{
11465 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
11466 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
11467 %}
11468 ins_pipe(pipe_class_default);
11469 %}
11470
11471 // Just slightly faster than java implementation.
11472 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
11473 match(Set dst (ReverseBytesI src));
11474 predicate(UseCountLeadingZerosInstructionsPPC64);
11475 ins_cost(DEFAULT_COST);
11476
11477 expand %{
11478 immI16 imm24 %{ (int) 24 %}
11479 immI16 imm16 %{ (int) 16 %}
11480 immI16 imm8 %{ (int) 8 %}
11481 immI16 imm4 %{ (int) 4 %}
11482 immI16 imm0 %{ (int) 0 %}
11483 iRegLdst tmpI1;
11484 iRegLdst tmpI2;
11485 iRegLdst tmpI3;
11486
11487 urShiftI_reg_imm(tmpI1, src, imm24);
11488 insrwi_a(dst, tmpI1, imm24, imm8);
11489 urShiftI_reg_imm(tmpI2, src, imm16);
11490 insrwi(dst, tmpI2, imm8, imm16);
11491 urShiftI_reg_imm(tmpI3, src, imm8);
11492 insrwi(dst, tmpI3, imm8, imm8);
11493 insrwi(dst, src, imm0, imm8);
11494 %}
11495 %}
11496
11497 //---------- Replicate Vector Instructions ------------------------------------
11498
11499 // Insrdi does replicate if src == dst.
11500 instruct repl32(iRegLdst dst) %{
11501 predicate(false);
11502 effect(USE_DEF dst);
11503
11504 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %}
11505 size(4);
11506 ins_encode %{
11507 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11508 __ insrdi($dst$$Register, $dst$$Register, 32, 0);
11509 %}
11510 ins_pipe(pipe_class_default);
11511 %}
11512
11513 // Insrdi does replicate if src == dst.
11514 instruct repl48(iRegLdst dst) %{
11515 predicate(false);
11516 effect(USE_DEF dst);
11517
11518 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %}
11519 size(4);
11520 ins_encode %{
11521 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11522 __ insrdi($dst$$Register, $dst$$Register, 48, 0);
11523 %}
11524 ins_pipe(pipe_class_default);
11525 %}
11526
11527 // Insrdi does replicate if src == dst.
11528 instruct repl56(iRegLdst dst) %{
11529 predicate(false);
11530 effect(USE_DEF dst);
11531
11532 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %}
11533 size(4);
11534 ins_encode %{
11535 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
11536 __ insrdi($dst$$Register, $dst$$Register, 56, 0);
11537 %}
11538 ins_pipe(pipe_class_default);
11539 %}
11540
11541 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11542 match(Set dst (ReplicateB src));
11543 predicate(n->as_Vector()->length() == 8);
11544 expand %{
11545 moveReg(dst, src);
11546 repl56(dst);
11547 repl48(dst);
11548 repl32(dst);
11549 %}
11550 %}
11551
11552 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
11553 match(Set dst (ReplicateB zero));
11554 predicate(n->as_Vector()->length() == 8);
11555 format %{ "LI $dst, #0 \t// replicate8B" %}
11556 size(4);
11557 ins_encode %{
11558 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11559 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11560 %}
11561 ins_pipe(pipe_class_default);
11562 %}
11563
11564 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
11565 match(Set dst (ReplicateB src));
11566 predicate(n->as_Vector()->length() == 8);
11567 format %{ "LI $dst, #-1 \t// replicate8B" %}
11568 size(4);
11569 ins_encode %{
11570 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11571 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11572 %}
11573 ins_pipe(pipe_class_default);
11574 %}
11575
11576 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11577 match(Set dst (ReplicateS src));
11578 predicate(n->as_Vector()->length() == 4);
11579 expand %{
11580 moveReg(dst, src);
11581 repl48(dst);
11582 repl32(dst);
11583 %}
11584 %}
11585
11586 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
11587 match(Set dst (ReplicateS zero));
11588 predicate(n->as_Vector()->length() == 4);
11589 format %{ "LI $dst, #0 \t// replicate4C" %}
11590 size(4);
11591 ins_encode %{
11592 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11593 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11594 %}
11595 ins_pipe(pipe_class_default);
11596 %}
11597
11598 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
11599 match(Set dst (ReplicateS src));
11600 predicate(n->as_Vector()->length() == 4);
11601 format %{ "LI $dst, -1 \t// replicate4C" %}
11602 size(4);
11603 ins_encode %{
11604 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11605 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11606 %}
11607 ins_pipe(pipe_class_default);
11608 %}
11609
11610 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
11611 match(Set dst (ReplicateI src));
11612 predicate(n->as_Vector()->length() == 2);
11613 ins_cost(2 * DEFAULT_COST);
11614 expand %{
11615 moveReg(dst, src);
11616 repl32(dst);
11617 %}
11618 %}
11619
11620 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
11621 match(Set dst (ReplicateI zero));
11622 predicate(n->as_Vector()->length() == 2);
11623 format %{ "LI $dst, #0 \t// replicate4C" %}
11624 size(4);
11625 ins_encode %{
11626 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11627 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
11628 %}
11629 ins_pipe(pipe_class_default);
11630 %}
11631
11632 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
11633 match(Set dst (ReplicateI src));
11634 predicate(n->as_Vector()->length() == 2);
11635 format %{ "LI $dst, -1 \t// replicate4C" %}
11636 size(4);
11637 ins_encode %{
11638 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11639 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
11640 %}
11641 ins_pipe(pipe_class_default);
11642 %}
11643
11644 // Move float to int register via stack, replicate.
11645 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
11646 match(Set dst (ReplicateF src));
11647 predicate(n->as_Vector()->length() == 2);
11648 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
11649 expand %{
11650 stackSlotL tmpS;
11651 iRegIdst tmpI;
11652 moveF2I_reg_stack(tmpS, src); // Move float to stack.
11653 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg.
11654 moveReg(dst, tmpI); // Move int to long reg.
11655 repl32(dst); // Replicate bitpattern.
11656 %}
11657 %}
11658
11659 // Replicate scalar constant to packed float values in Double register
11660 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
11661 match(Set dst (ReplicateF src));
11662 predicate(n->as_Vector()->length() == 2);
11663 ins_cost(5 * DEFAULT_COST);
11664
11665 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
11666 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
11667 %}
11668
11669 // Replicate scalar zero constant to packed float values in Double register
11670 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
11671 match(Set dst (ReplicateF zero));
11672 predicate(n->as_Vector()->length() == 2);
11673
11674 format %{ "LI $dst, #0 \t// replicate2F" %}
11675 ins_encode %{
11676 // TODO: PPC port $archOpcode(ppc64Opcode_addi);
11677 __ li($dst$$Register, 0x0);
11678 %}
11679 ins_pipe(pipe_class_default);
11680 %}
11681
11682
11683 //----------Overflow Math Instructions-----------------------------------------
11684
11685 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
11686 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
11687 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
11688
11689 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11690 match(Set cr0 (OverflowAddL op1 op2));
11691
11692 format %{ "add_ $op1, $op2\t# overflow check long" %}
11693 ins_encode %{
11694 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11695 __ li(R0, 0);
11696 __ mtxer(R0); // clear XER.SO
11697 __ addo_(R0, $op1$$Register, $op2$$Register);
11698 %}
11699 ins_pipe(pipe_class_default);
11700 %}
11701
11702 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11703 match(Set cr0 (OverflowSubL op1 op2));
11704
11705 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %}
11706 ins_encode %{
11707 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11708 __ li(R0, 0);
11709 __ mtxer(R0); // clear XER.SO
11710 __ subfo_(R0, $op2$$Register, $op1$$Register);
11711 %}
11712 ins_pipe(pipe_class_default);
11713 %}
11714
11715 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
11716 match(Set cr0 (OverflowSubL zero op2));
11717
11718 format %{ "nego_ R0, $op2\t# overflow check long" %}
11719 ins_encode %{
11720 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11721 __ li(R0, 0);
11722 __ mtxer(R0); // clear XER.SO
11723 __ nego_(R0, $op2$$Register);
11724 %}
11725 ins_pipe(pipe_class_default);
11726 %}
11727
11728 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
11729 match(Set cr0 (OverflowMulL op1 op2));
11730
11731 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
11732 ins_encode %{
11733 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11734 __ li(R0, 0);
11735 __ mtxer(R0); // clear XER.SO
11736 __ mulldo_(R0, $op1$$Register, $op2$$Register);
11737 %}
11738 ins_pipe(pipe_class_default);
11739 %}
11740
11741
11742 // ============================================================================
11743 // Safepoint Instruction
11744
11745 instruct safePoint_poll(iRegPdst poll) %{
11746 match(SafePoint poll);
11747 predicate(LoadPollAddressFromThread);
11748
11749 // It caused problems to add the effect that r0 is killed, but this
11750 // effect no longer needs to be mentioned, since r0 is not contained
11751 // in a reg_class.
11752
11753 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %}
11754 size(4);
11755 ins_encode( enc_poll(0x0, poll) );
11756 ins_pipe(pipe_class_default);
11757 %}
11758
11759 // Safepoint without per-thread support. Load address of page to poll
11760 // as constant.
11761 // Rscratch2RegP is R12.
11762 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
11763 // a seperate node so that the oop map is at the right location.
11764 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
11765 match(SafePoint poll);
11766 predicate(!LoadPollAddressFromThread);
11767
11768 // It caused problems to add the effect that r0 is killed, but this
11769 // effect no longer needs to be mentioned, since r0 is not contained
11770 // in a reg_class.
11771
11772 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %}
11773 ins_encode( enc_poll(0x0, poll) );
11774 ins_pipe(pipe_class_default);
11775 %}
11776
11777 // ============================================================================
11778 // Call Instructions
11779
11780 // Call Java Static Instruction
11781
11782 // Schedulable version of call static node.
11783 instruct CallStaticJavaDirect(method meth) %{
11784 match(CallStaticJava);
11785 effect(USE meth);
11786 predicate(!((CallStaticJavaNode*)n)->is_method_handle_invoke());
11787 ins_cost(CALL_COST);
11788
11789 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11790
11791 format %{ "CALL,static $meth \t// ==> " %}
11792 size(4);
11793 ins_encode( enc_java_static_call(meth) );
11794 ins_pipe(pipe_class_call);
11795 %}
11796
11797 // Schedulable version of call static node.
11798 instruct CallStaticJavaDirectHandle(method meth) %{
11799 match(CallStaticJava);
11800 effect(USE meth);
11801 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
11802 ins_cost(CALL_COST);
11803
11804 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
11805
11806 format %{ "CALL,static $meth \t// ==> " %}
11807 ins_encode( enc_java_handle_call(meth) );
11808 ins_pipe(pipe_class_call);
11809 %}
11810
11811 // Call Java Dynamic Instruction
11812
11813 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
11814 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
11815 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
11816 // The call destination must still be placed in the constant pool.
11817 instruct CallDynamicJavaDirectSched(method meth) %{
11818 match(CallDynamicJava); // To get all the data fields we need ...
11819 effect(USE meth);
11820 predicate(false); // ... but never match.
11821
11822 ins_field_load_ic_hi_node(loadConL_hiNode*);
11823 ins_field_load_ic_node(loadConLNode*);
11824 ins_num_consts(1 /* 1 patchable constant: call destination */);
11825
11826 format %{ "BL \t// dynamic $meth ==> " %}
11827 size(4);
11828 ins_encode( enc_java_dynamic_call_sched(meth) );
11829 ins_pipe(pipe_class_call);
11830 %}
11831
11832 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
11833 // We use postalloc expanded calls if we use inline caches
11834 // and do not update method data.
11835 //
11836 // This instruction has two constants: inline cache (IC) and call destination.
11837 // Loading the inline cache will be postalloc expanded, thus leaving a call with
11838 // one constant.
11839 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
11840 match(CallDynamicJava);
11841 effect(USE meth);
11842 predicate(UseInlineCaches);
11843 ins_cost(CALL_COST);
11844
11845 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
11846
11847 format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
11848 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
11849 %}
11850
11851 // Compound version of call dynamic java
11852 // We use postalloc expanded calls if we use inline caches
11853 // and do not update method data.
11854 instruct CallDynamicJavaDirect(method meth) %{
11855 match(CallDynamicJava);
11856 effect(USE meth);
11857 predicate(!UseInlineCaches);
11858 ins_cost(CALL_COST);
11859
11860 // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
11861 ins_num_consts(4);
11862
11863 format %{ "CALL,dynamic $meth \t// ==> " %}
11864 ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
11865 ins_pipe(pipe_class_call);
11866 %}
11867
11868 // Call Runtime Instruction
11869
11870 instruct CallRuntimeDirect(method meth) %{
11871 match(CallRuntime);
11872 effect(USE meth);
11873 ins_cost(CALL_COST);
11874
11875 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11876 // env for callee, C-toc.
11877 ins_num_consts(3);
11878
11879 format %{ "CALL,runtime" %}
11880 ins_encode( enc_java_to_runtime_call(meth) );
11881 ins_pipe(pipe_class_call);
11882 %}
11883
11884 // Call Leaf
11885
11886 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
11887 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
11888 effect(DEF dst, USE src);
11889
11890 ins_num_consts(1);
11891
11892 format %{ "MTCTR $src" %}
11893 size(4);
11894 ins_encode( enc_leaf_call_mtctr(src) );
11895 ins_pipe(pipe_class_default);
11896 %}
11897
11898 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
11899 instruct CallLeafDirect(method meth) %{
11900 match(CallLeaf); // To get the data all the data fields we need ...
11901 effect(USE meth);
11902 predicate(false); // but never match.
11903
11904 format %{ "BCTRL \t// leaf call $meth ==> " %}
11905 size(4);
11906 ins_encode %{
11907 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
11908 __ bctrl();
11909 %}
11910 ins_pipe(pipe_class_call);
11911 %}
11912
11913 // postalloc expand of CallLeafDirect.
11914 // Load adress to call from TOC, then bl to it.
11915 instruct CallLeafDirect_Ex(method meth) %{
11916 match(CallLeaf);
11917 effect(USE meth);
11918 ins_cost(CALL_COST);
11919
11920 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
11921 // env for callee, C-toc.
11922 ins_num_consts(3);
11923
11924 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
11925 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11926 %}
11927
11928 // Call runtime without safepoint - same as CallLeaf.
11929 // postalloc expand of CallLeafNoFPDirect.
11930 // Load adress to call from TOC, then bl to it.
11931 instruct CallLeafNoFPDirect_Ex(method meth) %{
11932 match(CallLeafNoFP);
11933 effect(USE meth);
11934 ins_cost(CALL_COST);
11935
11936 // Enc_java_to_runtime_call needs up to 3 constants: call target,
11937 // env for callee, C-toc.
11938 ins_num_consts(3);
11939
11940 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
11941 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
11942 %}
11943
11944 // Tail Call; Jump from runtime stub to Java code.
11945 // Also known as an 'interprocedural jump'.
11946 // Target of jump will eventually return to caller.
11947 // TailJump below removes the return address.
11948 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
11949 match(TailCall jump_target method_oop);
11950 ins_cost(CALL_COST);
11951
11952 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t"
11953 "BCTR \t// tail call" %}
11954 size(8);
11955 ins_encode %{
11956 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11957 __ mtctr($jump_target$$Register);
11958 __ bctr();
11959 %}
11960 ins_pipe(pipe_class_call);
11961 %}
11962
11963 // Return Instruction
11964 instruct Ret() %{
11965 match(Return);
11966 format %{ "BLR \t// branch to link register" %}
11967 size(4);
11968 ins_encode %{
11969 // TODO: PPC port $archOpcode(ppc64Opcode_blr);
11970 // LR is restored in MachEpilogNode. Just do the RET here.
11971 __ blr();
11972 %}
11973 ins_pipe(pipe_class_default);
11974 %}
11975
11976 // Tail Jump; remove the return address; jump to target.
11977 // TailCall above leaves the return address around.
11978 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
11979 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
11980 // "restore" before this instruction (in Epilogue), we need to materialize it
11981 // in %i0.
11982 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
11983 match(TailJump jump_target ex_oop);
11984 ins_cost(CALL_COST);
11985
11986 format %{ "LD R4_ARG2 = LR\n\t"
11987 "MTCTR $jump_target\n\t"
11988 "BCTR \t// TailJump, exception oop: $ex_oop" %}
11989 size(12);
11990 ins_encode %{
11991 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11992 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
11993 __ mtctr($jump_target$$Register);
11994 __ bctr();
11995 %}
11996 ins_pipe(pipe_class_call);
11997 %}
11998
11999 // Create exception oop: created by stack-crawling runtime code.
12000 // Created exception is now available to this handler, and is setup
12001 // just prior to jumping to this handler. No code emitted.
12002 instruct CreateException(rarg1RegP ex_oop) %{
12003 match(Set ex_oop (CreateEx));
12004 ins_cost(0);
12005
12006 format %{ " -- \t// exception oop; no code emitted" %}
12007 size(0);
12008 ins_encode( /*empty*/ );
12009 ins_pipe(pipe_class_default);
12010 %}
12011
12012 // Rethrow exception: The exception oop will come in the first
12013 // argument position. Then JUMP (not call) to the rethrow stub code.
12014 instruct RethrowException() %{
12015 match(Rethrow);
12016 ins_cost(CALL_COST);
12017
12018 format %{ "Jmp rethrow_stub" %}
12019 ins_encode %{
12020 // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12021 cbuf.set_insts_mark();
12022 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12023 %}
12024 ins_pipe(pipe_class_call);
12025 %}
12026
12027 // Die now.
12028 instruct ShouldNotReachHere() %{
12029 match(Halt);
12030 ins_cost(CALL_COST);
12031
12032 format %{ "ShouldNotReachHere" %}
12033 size(4);
12034 ins_encode %{
12035 // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12036 __ trap_should_not_reach_here();
12037 %}
12038 ins_pipe(pipe_class_default);
12039 %}
12040
12041 // This name is KNOWN by the ADLC and cannot be changed. The ADLC
12042 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12043 // Get a DEF on threadRegP, no costs, no encoding, use
12044 // 'ins_should_rematerialize(true)' to avoid spilling.
12045 instruct tlsLoadP(threadRegP dst) %{
12046 match(Set dst (ThreadLocal));
12047 ins_cost(0);
12048
12049 ins_should_rematerialize(true);
12050
12051 format %{ " -- \t// $dst=Thread::current(), empty" %}
12052 size(0);
12053 ins_encode( /*empty*/ );
12054 ins_pipe(pipe_class_empty);
12055 %}
12056
12057 //---Some PPC specific nodes---------------------------------------------------
12058
12059 // Stop a group.
12060 instruct endGroup() %{
12061 ins_cost(0);
12062
12063 ins_is_nop(true);
12064
12065 format %{ "End Bundle (ori r1, r1, 0)" %}
12066 size(4);
12067 ins_encode %{
12068 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12069 __ endgroup();
12070 %}
12071 ins_pipe(pipe_class_default);
12072 %}
12073
12074 // Nop instructions
12075
12076 instruct fxNop() %{
12077 ins_cost(0);
12078
12079 ins_is_nop(true);
12080
12081 format %{ "fxNop" %}
12082 size(4);
12083 ins_encode %{
12084 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12085 __ nop();
12086 %}
12087 ins_pipe(pipe_class_default);
12088 %}
12089
12090 instruct fpNop0() %{
12091 ins_cost(0);
12092
12093 ins_is_nop(true);
12094
12095 format %{ "fpNop0" %}
12096 size(4);
12097 ins_encode %{
12098 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12099 __ fpnop0();
12100 %}
12101 ins_pipe(pipe_class_default);
12102 %}
12103
12104 instruct fpNop1() %{
12105 ins_cost(0);
12106
12107 ins_is_nop(true);
12108
12109 format %{ "fpNop1" %}
12110 size(4);
12111 ins_encode %{
12112 // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12113 __ fpnop1();
12114 %}
12115 ins_pipe(pipe_class_default);
12116 %}
12117
12118 instruct brNop0() %{
12119 ins_cost(0);
12120 size(4);
12121 format %{ "brNop0" %}
12122 ins_encode %{
12123 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12124 __ brnop0();
12125 %}
12126 ins_is_nop(true);
12127 ins_pipe(pipe_class_default);
12128 %}
12129
12130 instruct brNop1() %{
12131 ins_cost(0);
12132
12133 ins_is_nop(true);
12134
12135 format %{ "brNop1" %}
12136 size(4);
12137 ins_encode %{
12138 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12139 __ brnop1();
12140 %}
12141 ins_pipe(pipe_class_default);
12142 %}
12143
12144 instruct brNop2() %{
12145 ins_cost(0);
12146
12147 ins_is_nop(true);
12148
12149 format %{ "brNop2" %}
12150 size(4);
12151 ins_encode %{
12152 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12153 __ brnop2();
12154 %}
12155 ins_pipe(pipe_class_default);
12156 %}
12157
12158 //----------PEEPHOLE RULES-----------------------------------------------------
12159 // These must follow all instruction definitions as they use the names
12160 // defined in the instructions definitions.
12161 //
12162 // peepmatch ( root_instr_name [preceeding_instruction]* );
12163 //
12164 // peepconstraint %{
12165 // (instruction_number.operand_name relational_op instruction_number.operand_name
12166 // [, ...] );
12167 // // instruction numbers are zero-based using left to right order in peepmatch
12168 //
12169 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12170 // // provide an instruction_number.operand_name for each operand that appears
12171 // // in the replacement instruction's match rule
12172 //
12173 // ---------VM FLAGS---------------------------------------------------------
12174 //
12175 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12176 //
12177 // Each peephole rule is given an identifying number starting with zero and
12178 // increasing by one in the order seen by the parser. An individual peephole
12179 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12180 // on the command-line.
12181 //
12182 // ---------CURRENT LIMITATIONS----------------------------------------------
12183 //
12184 // Only match adjacent instructions in same basic block
12185 // Only equality constraints
12186 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12187 // Only one replacement instruction
12188 //
12189 // ---------EXAMPLE----------------------------------------------------------
12190 //
12191 // // pertinent parts of existing instructions in architecture description
12192 // instruct movI(eRegI dst, eRegI src) %{
12193 // match(Set dst (CopyI src));
12194 // %}
12195 //
12196 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12197 // match(Set dst (AddI dst src));
12198 // effect(KILL cr);
12199 // %}
12200 //
12201 // // Change (inc mov) to lea
12202 // peephole %{
12203 // // increment preceeded by register-register move
12204 // peepmatch ( incI_eReg movI );
12205 // // require that the destination register of the increment
12206 // // match the destination register of the move
12207 // peepconstraint ( 0.dst == 1.dst );
12208 // // construct a replacement instruction that sets
12209 // // the destination to ( move's source register + one )
12210 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12211 // %}
12212 //
12213 // Implementation no longer uses movX instructions since
12214 // machine-independent system no longer uses CopyX nodes.
12215 //
12216 // peephole %{
12217 // peepmatch ( incI_eReg movI );
12218 // peepconstraint ( 0.dst == 1.dst );
12219 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12220 // %}
12221 //
12222 // peephole %{
12223 // peepmatch ( decI_eReg movI );
12224 // peepconstraint ( 0.dst == 1.dst );
12225 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12226 // %}
12227 //
12228 // peephole %{
12229 // peepmatch ( addI_eReg_imm movI );
12230 // peepconstraint ( 0.dst == 1.dst );
12231 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12232 // %}
12233 //
12234 // peephole %{
12235 // peepmatch ( addP_eReg_imm movP );
12236 // peepconstraint ( 0.dst == 1.dst );
12237 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12238 // %}
12239
12240 // // Change load of spilled value to only a spill
12241 // instruct storeI(memory mem, eRegI src) %{
12242 // match(Set mem (StoreI mem src));
12243 // %}
12244 //
12245 // instruct loadI(eRegI dst, memory mem) %{
12246 // match(Set dst (LoadI mem));
12247 // %}
12248 //
12249 peephole %{
12250 peepmatch ( loadI storeI );
12251 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12252 peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12253 %}
12254
12255 peephole %{
12256 peepmatch ( loadL storeL );
12257 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12258 peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12259 %}
12260
12261 peephole %{
12262 peepmatch ( loadP storeP );
12263 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12264 peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12265 %}
12266
12267 //----------SMARTSPILL RULES---------------------------------------------------
12268 // These must follow all instruction definitions as they use the names
12269 // defined in the instructions definitions.