1 /* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP 26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP 27 28 #include "asm/assembler.hpp" 29 #include "utilities/macros.hpp" 30 #include "runtime/rtmLocking.hpp" 31 32 33 // MacroAssembler extends Assembler by frequently used macros. 34 // 35 // Instructions for which a 'better' code sequence exists depending 36 // on arguments should also go in here. 37 38 class MacroAssembler: public Assembler { 39 friend class LIR_Assembler; 40 friend class Runtime1; // as_Address() 41 42 protected: 43 44 Address as_Address(AddressLiteral adr); 45 Address as_Address(ArrayAddress adr); 46 47 // Support for VM calls 48 // 49 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 50 // may customize this version by overriding it for its purposes (e.g., to save/restore 51 // additional registers when doing a VM call). 52 #ifdef CC_INTERP 53 // c++ interpreter never wants to use interp_masm version of call_VM 54 #define VIRTUAL 55 #else 56 #define VIRTUAL virtual 57 #endif 58 59 #define COMMA , 60 61 VIRTUAL void call_VM_leaf_base( 62 address entry_point, // the entry point 63 int number_of_arguments // the number of arguments to pop after the call 64 ); 65 66 // This is the base routine called by the different versions of call_VM. The interpreter 67 // may customize this version by overriding it for its purposes (e.g., to save/restore 68 // additional registers when doing a VM call). 69 // 70 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 71 // returns the register which contains the thread upon return. If a thread register has been 72 // specified, the return value will correspond to that register. If no last_java_sp is specified 73 // (noreg) than rsp will be used instead. 74 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 75 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 76 Register java_thread, // the thread if computed before ; use noreg otherwise 77 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 78 address entry_point, // the entry point 79 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 80 bool check_exceptions // whether to check for pending exceptions after return 81 ); 82 83 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 84 // The implementation is only non-empty for the InterpreterMacroAssembler, 85 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 86 virtual void check_and_handle_popframe(Register java_thread); 87 virtual void check_and_handle_earlyret(Register java_thread); 88 89 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 90 91 // helpers for FPU flag access 92 // tmp is a temporary register, if none is available use noreg 93 void save_rax (Register tmp); 94 void restore_rax(Register tmp); 95 96 public: 97 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 98 99 // Support for NULL-checks 100 // 101 // Generates code that causes a NULL OS exception if the content of reg is NULL. 102 // If the accessed location is M[reg + offset] and the offset is known, provide the 103 // offset. No explicit code generation is needed if the offset is within a certain 104 // range (0 <= offset <= page_size). 105 106 void null_check(Register reg, int offset = -1); 107 static bool needs_explicit_null_check(intptr_t offset); 108 109 // Required platform-specific helpers for Label::patch_instructions. 110 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 111 void pd_patch_instruction(address branch, address target) { 112 unsigned char op = branch[0]; 113 assert(op == 0xE8 /* call */ || 114 op == 0xE9 /* jmp */ || 115 op == 0xEB /* short jmp */ || 116 (op & 0xF0) == 0x70 /* short jcc */ || 117 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ || 118 op == 0xC7 && branch[1] == 0xF8 /* xbegin */, 119 "Invalid opcode at patch point"); 120 121 if (op == 0xEB || (op & 0xF0) == 0x70) { 122 // short offset operators (jmp and jcc) 123 char* disp = (char*) &branch[1]; 124 int imm8 = target - (address) &disp[1]; 125 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); 126 *disp = imm8; 127 } else { 128 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1]; 129 int imm32 = target - (address) &disp[1]; 130 *disp = imm32; 131 } 132 } 133 134 // The following 4 methods return the offset of the appropriate move instruction 135 136 // Support for fast byte/short loading with zero extension (depending on particular CPU) 137 int load_unsigned_byte(Register dst, Address src); 138 int load_unsigned_short(Register dst, Address src); 139 140 // Support for fast byte/short loading with sign extension (depending on particular CPU) 141 int load_signed_byte(Register dst, Address src); 142 int load_signed_short(Register dst, Address src); 143 144 // Support for sign-extension (hi:lo = extend_sign(lo)) 145 void extend_sign(Register hi, Register lo); 146 147 // Load and store values by size and signed-ness 148 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 149 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 150 151 // Support for inc/dec with optimal instruction selection depending on value 152 153 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 154 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 155 156 void decrementl(Address dst, int value = 1); 157 void decrementl(Register reg, int value = 1); 158 159 void decrementq(Register reg, int value = 1); 160 void decrementq(Address dst, int value = 1); 161 162 void incrementl(Address dst, int value = 1); 163 void incrementl(Register reg, int value = 1); 164 165 void incrementq(Register reg, int value = 1); 166 void incrementq(Address dst, int value = 1); 167 168 // Support optimal SSE move instructions. 169 void movflt(XMMRegister dst, XMMRegister src) { 170 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 171 else { movss (dst, src); return; } 172 } 173 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 174 void movflt(XMMRegister dst, AddressLiteral src); 175 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 176 177 void movdbl(XMMRegister dst, XMMRegister src) { 178 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 179 else { movsd (dst, src); return; } 180 } 181 182 void movdbl(XMMRegister dst, AddressLiteral src); 183 184 void movdbl(XMMRegister dst, Address src) { 185 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 186 else { movlpd(dst, src); return; } 187 } 188 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 189 190 void incrementl(AddressLiteral dst); 191 void incrementl(ArrayAddress dst); 192 193 void incrementq(AddressLiteral dst); 194 195 // Alignment 196 void align(int modulus); 197 void align(int modulus, int target); 198 199 // A 5 byte nop that is safe for patching (see patch_verified_entry) 200 void fat_nop(); 201 202 // Stack frame creation/removal 203 void enter(); 204 void leave(); 205 206 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 207 // The pointer will be loaded into the thread register. 208 void get_thread(Register thread); 209 210 211 // Support for VM calls 212 // 213 // It is imperative that all calls into the VM are handled via the call_VM macros. 214 // They make sure that the stack linkage is setup correctly. call_VM's correspond 215 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 216 217 218 void call_VM(Register oop_result, 219 address entry_point, 220 bool check_exceptions = true); 221 void call_VM(Register oop_result, 222 address entry_point, 223 Register arg_1, 224 bool check_exceptions = true); 225 void call_VM(Register oop_result, 226 address entry_point, 227 Register arg_1, Register arg_2, 228 bool check_exceptions = true); 229 void call_VM(Register oop_result, 230 address entry_point, 231 Register arg_1, Register arg_2, Register arg_3, 232 bool check_exceptions = true); 233 234 // Overloadings with last_Java_sp 235 void call_VM(Register oop_result, 236 Register last_java_sp, 237 address entry_point, 238 int number_of_arguments = 0, 239 bool check_exceptions = true); 240 void call_VM(Register oop_result, 241 Register last_java_sp, 242 address entry_point, 243 Register arg_1, bool 244 check_exceptions = true); 245 void call_VM(Register oop_result, 246 Register last_java_sp, 247 address entry_point, 248 Register arg_1, Register arg_2, 249 bool check_exceptions = true); 250 void call_VM(Register oop_result, 251 Register last_java_sp, 252 address entry_point, 253 Register arg_1, Register arg_2, Register arg_3, 254 bool check_exceptions = true); 255 256 void get_vm_result (Register oop_result, Register thread); 257 void get_vm_result_2(Register metadata_result, Register thread); 258 259 // These always tightly bind to MacroAssembler::call_VM_base 260 // bypassing the virtual implementation 261 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 262 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 263 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 264 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 265 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 266 267 void call_VM_leaf(address entry_point, 268 int number_of_arguments = 0); 269 void call_VM_leaf(address entry_point, 270 Register arg_1); 271 void call_VM_leaf(address entry_point, 272 Register arg_1, Register arg_2); 273 void call_VM_leaf(address entry_point, 274 Register arg_1, Register arg_2, Register arg_3); 275 276 // These always tightly bind to MacroAssembler::call_VM_leaf_base 277 // bypassing the virtual implementation 278 void super_call_VM_leaf(address entry_point); 279 void super_call_VM_leaf(address entry_point, Register arg_1); 280 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 281 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 282 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 283 284 // last Java Frame (fills frame anchor) 285 void set_last_Java_frame(Register thread, 286 Register last_java_sp, 287 Register last_java_fp, 288 address last_java_pc); 289 290 // thread in the default location (r15_thread on 64bit) 291 void set_last_Java_frame(Register last_java_sp, 292 Register last_java_fp, 293 address last_java_pc); 294 295 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); 296 297 // thread in the default location (r15_thread on 64bit) 298 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 299 300 // Stores 301 void store_check(Register obj); // store check for obj - register is destroyed afterwards 302 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 303 304 #if INCLUDE_ALL_GCS 305 306 void g1_write_barrier_pre(Register obj, 307 Register pre_val, 308 Register thread, 309 Register tmp, 310 bool tosca_live, 311 bool expand_call); 312 313 void g1_write_barrier_post(Register store_addr, 314 Register new_val, 315 Register thread, 316 Register tmp, 317 Register tmp2); 318 319 #endif // INCLUDE_ALL_GCS 320 321 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 322 void c2bool(Register x); 323 324 // C++ bool manipulation 325 326 void movbool(Register dst, Address src); 327 void movbool(Address dst, bool boolconst); 328 void movbool(Address dst, Register src); 329 void testbool(Register dst); 330 331 // oop manipulations 332 void load_klass(Register dst, Register src); 333 void store_klass(Register dst, Register src); 334 335 void load_heap_oop(Register dst, Address src); 336 void load_heap_oop_not_null(Register dst, Address src); 337 void store_heap_oop(Address dst, Register src); 338 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); 339 340 // Used for storing NULL. All other oop constants should be 341 // stored using routines that take a jobject. 342 void store_heap_oop_null(Address dst); 343 344 void load_prototype_header(Register dst, Register src); 345 346 #ifdef _LP64 347 void store_klass_gap(Register dst, Register src); 348 349 // This dummy is to prevent a call to store_heap_oop from 350 // converting a zero (like NULL) into a Register by giving 351 // the compiler two choices it can't resolve 352 353 void store_heap_oop(Address dst, void* dummy); 354 355 void encode_heap_oop(Register r); 356 void decode_heap_oop(Register r); 357 void encode_heap_oop_not_null(Register r); 358 void decode_heap_oop_not_null(Register r); 359 void encode_heap_oop_not_null(Register dst, Register src); 360 void decode_heap_oop_not_null(Register dst, Register src); 361 362 void set_narrow_oop(Register dst, jobject obj); 363 void set_narrow_oop(Address dst, jobject obj); 364 void cmp_narrow_oop(Register dst, jobject obj); 365 void cmp_narrow_oop(Address dst, jobject obj); 366 367 void encode_klass_not_null(Register r); 368 void decode_klass_not_null(Register r); 369 void encode_klass_not_null(Register dst, Register src); 370 void decode_klass_not_null(Register dst, Register src); 371 void set_narrow_klass(Register dst, Klass* k); 372 void set_narrow_klass(Address dst, Klass* k); 373 void cmp_narrow_klass(Register dst, Klass* k); 374 void cmp_narrow_klass(Address dst, Klass* k); 375 376 // Returns the byte size of the instructions generated by decode_klass_not_null() 377 // when compressed klass pointers are being used. 378 static int instr_size_for_decode_klass_not_null(); 379 380 // if heap base register is used - reinit it with the correct value 381 void reinit_heapbase(); 382 383 DEBUG_ONLY(void verify_heapbase(const char* msg);) 384 385 #endif // _LP64 386 387 // Int division/remainder for Java 388 // (as idivl, but checks for special case as described in JVM spec.) 389 // returns idivl instruction offset for implicit exception handling 390 int corrected_idivl(Register reg); 391 392 // Long division/remainder for Java 393 // (as idivq, but checks for special case as described in JVM spec.) 394 // returns idivq instruction offset for implicit exception handling 395 int corrected_idivq(Register reg); 396 397 void int3(); 398 399 // Long operation macros for a 32bit cpu 400 // Long negation for Java 401 void lneg(Register hi, Register lo); 402 403 // Long multiplication for Java 404 // (destroys contents of eax, ebx, ecx and edx) 405 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 406 407 // Long shifts for Java 408 // (semantics as described in JVM spec.) 409 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 410 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 411 412 // Long compare for Java 413 // (semantics as described in JVM spec.) 414 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 415 416 417 // misc 418 419 // Sign extension 420 void sign_extend_short(Register reg); 421 void sign_extend_byte(Register reg); 422 423 // Division by power of 2, rounding towards 0 424 void division_with_shift(Register reg, int shift_value); 425 426 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 427 // 428 // CF (corresponds to C0) if x < y 429 // PF (corresponds to C2) if unordered 430 // ZF (corresponds to C3) if x = y 431 // 432 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 433 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 434 void fcmp(Register tmp); 435 // Variant of the above which allows y to be further down the stack 436 // and which only pops x and y if specified. If pop_right is 437 // specified then pop_left must also be specified. 438 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 439 440 // Floating-point comparison for Java 441 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 442 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 443 // (semantics as described in JVM spec.) 444 void fcmp2int(Register dst, bool unordered_is_less); 445 // Variant of the above which allows y to be further down the stack 446 // and which only pops x and y if specified. If pop_right is 447 // specified then pop_left must also be specified. 448 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 449 450 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 451 // tmp is a temporary register, if none is available use noreg 452 void fremr(Register tmp); 453 454 455 // same as fcmp2int, but using SSE2 456 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 457 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 458 459 // Inlined sin/cos generator for Java; must not use CPU instruction 460 // directly on Intel as it does not have high enough precision 461 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 462 // number of FPU stack slots in use; all but the topmost will 463 // require saving if a slow case is necessary. Assumes argument is 464 // on FP TOS; result is on FP TOS. No cpu registers are changed by 465 // this code. 466 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 467 468 // branch to L if FPU flag C2 is set/not set 469 // tmp is a temporary register, if none is available use noreg 470 void jC2 (Register tmp, Label& L); 471 void jnC2(Register tmp, Label& L); 472 473 // Pop ST (ffree & fincstp combined) 474 void fpop(); 475 476 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into 477 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 478 void load_float(Address src); 479 480 // Store float value to 'address'. If UseSSE >= 1, the value is stored 481 // from register xmm0. Otherwise, the value is stored from the FPU stack. 482 void store_float(Address dst); 483 484 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into 485 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 486 void load_double(Address src); 487 488 // Store double value to 'address'. If UseSSE >= 2, the value is stored 489 // from register xmm0. Otherwise, the value is stored from the FPU stack. 490 void store_double(Address dst); 491 492 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 493 void push_fTOS(); 494 495 // pops double TOS element from CPU stack and pushes on FPU stack 496 void pop_fTOS(); 497 498 void empty_FPU_stack(); 499 500 void push_IU_state(); 501 void pop_IU_state(); 502 503 void push_FPU_state(); 504 void pop_FPU_state(); 505 506 void push_CPU_state(); 507 void pop_CPU_state(); 508 509 // Round up to a power of two 510 void round_to(Register reg, int modulus); 511 512 // Callee saved registers handling 513 void push_callee_saved_registers(); 514 void pop_callee_saved_registers(); 515 516 // allocation 517 void eden_allocate( 518 Register obj, // result: pointer to object after successful allocation 519 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 520 int con_size_in_bytes, // object size in bytes if known at compile time 521 Register t1, // temp register 522 Label& slow_case // continuation point if fast allocation fails 523 ); 524 void tlab_allocate( 525 Register obj, // result: pointer to object after successful allocation 526 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 527 int con_size_in_bytes, // object size in bytes if known at compile time 528 Register t1, // temp register 529 Register t2, // temp register 530 Label& slow_case // continuation point if fast allocation fails 531 ); 532 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 533 void incr_allocated_bytes(Register thread, 534 Register var_size_in_bytes, int con_size_in_bytes, 535 Register t1 = noreg); 536 537 // interface method calling 538 void lookup_interface_method(Register recv_klass, 539 Register intf_klass, 540 RegisterOrConstant itable_index, 541 Register method_result, 542 Register scan_temp, 543 Label& no_such_interface); 544 545 // virtual method calling 546 void lookup_virtual_method(Register recv_klass, 547 RegisterOrConstant vtable_index, 548 Register method_result); 549 550 // Test sub_klass against super_klass, with fast and slow paths. 551 552 // The fast path produces a tri-state answer: yes / no / maybe-slow. 553 // One of the three labels can be NULL, meaning take the fall-through. 554 // If super_check_offset is -1, the value is loaded up from super_klass. 555 // No registers are killed, except temp_reg. 556 void check_klass_subtype_fast_path(Register sub_klass, 557 Register super_klass, 558 Register temp_reg, 559 Label* L_success, 560 Label* L_failure, 561 Label* L_slow_path, 562 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 563 564 // The rest of the type check; must be wired to a corresponding fast path. 565 // It does not repeat the fast path logic, so don't use it standalone. 566 // The temp_reg and temp2_reg can be noreg, if no temps are available. 567 // Updates the sub's secondary super cache as necessary. 568 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 569 void check_klass_subtype_slow_path(Register sub_klass, 570 Register super_klass, 571 Register temp_reg, 572 Register temp2_reg, 573 Label* L_success, 574 Label* L_failure, 575 bool set_cond_codes = false); 576 577 // Simplified, combined version, good for typical uses. 578 // Falls through on failure. 579 void check_klass_subtype(Register sub_klass, 580 Register super_klass, 581 Register temp_reg, 582 Label& L_success); 583 584 // method handles (JSR 292) 585 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 586 587 //---- 588 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 589 590 // Debugging 591 592 // only if +VerifyOops 593 // TODO: Make these macros with file and line like sparc version! 594 void verify_oop(Register reg, const char* s = "broken oop"); 595 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 596 597 // TODO: verify method and klass metadata (compare against vptr?) 598 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 599 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 600 601 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 602 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 603 604 // only if +VerifyFPU 605 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 606 607 // Verify or restore cpu control state after JNI call 608 void restore_cpu_control_state_after_jni(); 609 610 // prints msg, dumps registers and stops execution 611 void stop(const char* msg); 612 613 // prints msg and continues 614 void warn(const char* msg); 615 616 // dumps registers and other state 617 void print_state(); 618 619 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 620 static void debug64(char* msg, int64_t pc, int64_t regs[]); 621 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); 622 static void print_state64(int64_t pc, int64_t regs[]); 623 624 void os_breakpoint(); 625 626 void untested() { stop("untested"); } 627 628 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 629 630 void should_not_reach_here() { stop("should not reach here"); } 631 632 void print_CPU_state(); 633 634 // Stack overflow checking 635 void bang_stack_with_offset(int offset) { 636 // stack grows down, caller passes positive offset 637 assert(offset > 0, "must bang with negative offset"); 638 movl(Address(rsp, (-offset)), rax); 639 } 640 641 // Writes to stack successive pages until offset reached to check for 642 // stack overflow + shadow pages. Also, clobbers tmp 643 void bang_stack_size(Register size, Register tmp); 644 645 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 646 Register tmp, 647 int offset); 648 649 // Support for serializing memory accesses between threads 650 void serialize_memory(Register thread, Register tmp); 651 652 void verify_tlab(); 653 654 // Biased locking support 655 // lock_reg and obj_reg must be loaded up with the appropriate values. 656 // swap_reg must be rax, and is killed. 657 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 658 // be killed; if not supplied, push/pop will be used internally to 659 // allocate a temporary (inefficient, avoid if possible). 660 // Optional slow case is for implementations (interpreter and C1) which branch to 661 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 662 // Returns offset of first potentially-faulting instruction for null 663 // check info (currently consumed only by C1). If 664 // swap_reg_contains_mark is true then returns -1 as it is assumed 665 // the calling code has already passed any potential faults. 666 int biased_locking_enter(Register lock_reg, Register obj_reg, 667 Register swap_reg, Register tmp_reg, 668 bool swap_reg_contains_mark, 669 Label& done, Label* slow_case = NULL, 670 BiasedLockingCounters* counters = NULL); 671 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 672 #ifdef COMPILER2 673 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. 674 // See full desription in macroAssembler_x86.cpp. 675 void fast_lock(Register obj, Register box, Register tmp, 676 Register scr, Register cx1, Register cx2, 677 BiasedLockingCounters* counters, 678 RTMLockingCounters* rtm_counters, 679 RTMLockingCounters* stack_rtm_counters, 680 Metadata* method_data, 681 bool use_rtm, bool profile_rtm); 682 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm); 683 #if INCLUDE_RTM_OPT 684 void rtm_counters_update(Register abort_status, Register rtm_counters); 685 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel); 686 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg, 687 RTMLockingCounters* rtm_counters, 688 Metadata* method_data); 689 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg, 690 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); 691 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel); 692 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel); 693 void rtm_stack_locking(Register obj, Register tmp, Register scr, 694 Register retry_on_abort_count, 695 RTMLockingCounters* stack_rtm_counters, 696 Metadata* method_data, bool profile_rtm, 697 Label& DONE_LABEL, Label& IsInflated); 698 void rtm_inflated_locking(Register obj, Register box, Register tmp, 699 Register scr, Register retry_on_busy_count, 700 Register retry_on_abort_count, 701 RTMLockingCounters* rtm_counters, 702 Metadata* method_data, bool profile_rtm, 703 Label& DONE_LABEL); 704 #endif 705 #endif 706 707 Condition negate_condition(Condition cond); 708 709 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 710 // operands. In general the names are modified to avoid hiding the instruction in Assembler 711 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 712 // here in MacroAssembler. The major exception to this rule is call 713 714 // Arithmetics 715 716 717 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 718 void addptr(Address dst, Register src); 719 720 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 721 void addptr(Register dst, int32_t src); 722 void addptr(Register dst, Register src); 723 void addptr(Register dst, RegisterOrConstant src) { 724 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 725 else addptr(dst, src.as_register()); 726 } 727 728 void andptr(Register dst, int32_t src); 729 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 730 731 void cmp8(AddressLiteral src1, int imm); 732 733 // renamed to drag out the casting of address to int32_t/intptr_t 734 void cmp32(Register src1, int32_t imm); 735 736 void cmp32(AddressLiteral src1, int32_t imm); 737 // compare reg - mem, or reg - &mem 738 void cmp32(Register src1, AddressLiteral src2); 739 740 void cmp32(Register src1, Address src2); 741 742 #ifndef _LP64 743 void cmpklass(Address dst, Metadata* obj); 744 void cmpklass(Register dst, Metadata* obj); 745 void cmpoop(Address dst, jobject obj); 746 void cmpoop(Register dst, jobject obj); 747 #endif // _LP64 748 749 // NOTE src2 must be the lval. This is NOT an mem-mem compare 750 void cmpptr(Address src1, AddressLiteral src2); 751 752 void cmpptr(Register src1, AddressLiteral src2); 753 754 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 755 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 756 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 757 758 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 759 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 760 761 // cmp64 to avoild hiding cmpq 762 void cmp64(Register src1, AddressLiteral src); 763 764 void cmpxchgptr(Register reg, Address adr); 765 766 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 767 768 769 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 770 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); } 771 772 773 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 774 775 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 776 777 void shlptr(Register dst, int32_t shift); 778 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 779 780 void shrptr(Register dst, int32_t shift); 781 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 782 783 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 784 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 785 786 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 787 788 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 789 void subptr(Register dst, int32_t src); 790 // Force generation of a 4 byte immediate value even if it fits into 8bit 791 void subptr_imm32(Register dst, int32_t src); 792 void subptr(Register dst, Register src); 793 void subptr(Register dst, RegisterOrConstant src) { 794 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 795 else subptr(dst, src.as_register()); 796 } 797 798 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 799 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 800 801 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 802 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 803 804 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 805 806 807 808 // Helper functions for statistics gathering. 809 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 810 void cond_inc32(Condition cond, AddressLiteral counter_addr); 811 // Unconditional atomic increment. 812 void atomic_incl(Address counter_addr); 813 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1); 814 #ifdef _LP64 815 void atomic_incq(Address counter_addr); 816 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1); 817 #endif 818 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; } 819 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; } 820 821 void lea(Register dst, AddressLiteral adr); 822 void lea(Address dst, AddressLiteral adr); 823 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 824 825 void leal32(Register dst, Address src) { leal(dst, src); } 826 827 // Import other testl() methods from the parent class or else 828 // they will be hidden by the following overriding declaration. 829 using Assembler::testl; 830 void testl(Register dst, AddressLiteral src); 831 832 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 833 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 834 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 835 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); } 836 837 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 838 void testptr(Register src1, Register src2); 839 840 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 841 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 842 843 // Calls 844 845 void call(Label& L, relocInfo::relocType rtype); 846 void call(Register entry); 847 848 // NOTE: this call tranfers to the effective address of entry NOT 849 // the address contained by entry. This is because this is more natural 850 // for jumps/calls. 851 void call(AddressLiteral entry); 852 853 // Emit the CompiledIC call idiom 854 void ic_call(address entry); 855 856 // Jumps 857 858 // NOTE: these jumps tranfer to the effective address of dst NOT 859 // the address contained by dst. This is because this is more natural 860 // for jumps/calls. 861 void jump(AddressLiteral dst); 862 void jump_cc(Condition cc, AddressLiteral dst); 863 864 // 32bit can do a case table jump in one instruction but we no longer allow the base 865 // to be installed in the Address class. This jump will tranfers to the address 866 // contained in the location described by entry (not the address of entry) 867 void jump(ArrayAddress entry); 868 869 // Floating 870 871 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 872 void andpd(XMMRegister dst, AddressLiteral src); 873 874 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } 875 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 876 void andps(XMMRegister dst, AddressLiteral src); 877 878 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } 879 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 880 void comiss(XMMRegister dst, AddressLiteral src); 881 882 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } 883 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 884 void comisd(XMMRegister dst, AddressLiteral src); 885 886 void fadd_s(Address src) { Assembler::fadd_s(src); } 887 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 888 889 void fldcw(Address src) { Assembler::fldcw(src); } 890 void fldcw(AddressLiteral src); 891 892 void fld_s(int index) { Assembler::fld_s(index); } 893 void fld_s(Address src) { Assembler::fld_s(src); } 894 void fld_s(AddressLiteral src); 895 896 void fld_d(Address src) { Assembler::fld_d(src); } 897 void fld_d(AddressLiteral src); 898 899 void fld_x(Address src) { Assembler::fld_x(src); } 900 void fld_x(AddressLiteral src); 901 902 void fmul_s(Address src) { Assembler::fmul_s(src); } 903 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 904 905 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 906 void ldmxcsr(AddressLiteral src); 907 908 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover 909 // all corner cases and may result in NaN and require fallback to a 910 // runtime call. 911 void fast_pow(); 912 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 913 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 914 Register rax, Register rcx, Register rdx, Register tmp); 915 916 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 917 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 918 Register rax, Register rcx, Register rdx, Register tmp1 LP64_ONLY(COMMA Register tmp2)); 919 920 void increase_precision(); 921 void restore_precision(); 922 923 // computes pow(x,y). Fallback to runtime call included. 924 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(num_fpu_regs_in_use); } 925 926 private: 927 928 // call runtime as a fallback for trig functions and pow/exp. 929 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); 930 931 // computes 2^(Ylog2X); Ylog2X in ST(0) 932 void pow_exp_core_encoding(); 933 934 // computes pow(x,y) or exp(x). Fallback to runtime call included. 935 void pow_or_exp(int num_fpu_regs_in_use); 936 937 // these are private because users should be doing movflt/movdbl 938 939 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 940 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 941 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 942 void movss(XMMRegister dst, AddressLiteral src); 943 944 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 945 void movlpd(XMMRegister dst, AddressLiteral src); 946 947 public: 948 949 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 950 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 951 void addsd(XMMRegister dst, AddressLiteral src); 952 953 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 954 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 955 void addss(XMMRegister dst, AddressLiteral src); 956 957 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 958 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 959 void divsd(XMMRegister dst, AddressLiteral src); 960 961 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 962 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 963 void divss(XMMRegister dst, AddressLiteral src); 964 965 // Move Unaligned Double Quadword 966 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); } 967 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); } 968 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); } 969 void movdqu(XMMRegister dst, AddressLiteral src); 970 971 // Move Aligned Double Quadword 972 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); } 973 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); } 974 void movdqa(XMMRegister dst, AddressLiteral src); 975 976 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 977 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 978 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 979 void movsd(XMMRegister dst, AddressLiteral src); 980 981 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); } 982 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); } 983 void mulpd(XMMRegister dst, AddressLiteral src); 984 985 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 986 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 987 void mulsd(XMMRegister dst, AddressLiteral src); 988 989 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 990 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 991 void mulss(XMMRegister dst, AddressLiteral src); 992 993 // Carry-Less Multiplication Quadword 994 void pclmulldq(XMMRegister dst, XMMRegister src) { 995 // 0x00 - multiply lower 64 bits [0:63] 996 Assembler::pclmulqdq(dst, src, 0x00); 997 } 998 void pclmulhdq(XMMRegister dst, XMMRegister src) { 999 // 0x11 - multiply upper 64 bits [64:127] 1000 Assembler::pclmulqdq(dst, src, 0x11); 1001 } 1002 1003 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 1004 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 1005 void sqrtsd(XMMRegister dst, AddressLiteral src); 1006 1007 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 1008 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 1009 void sqrtss(XMMRegister dst, AddressLiteral src); 1010 1011 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 1012 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 1013 void subsd(XMMRegister dst, AddressLiteral src); 1014 1015 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 1016 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 1017 void subss(XMMRegister dst, AddressLiteral src); 1018 1019 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 1020 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 1021 void ucomiss(XMMRegister dst, AddressLiteral src); 1022 1023 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 1024 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 1025 void ucomisd(XMMRegister dst, AddressLiteral src); 1026 1027 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1028 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } 1029 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 1030 void xorpd(XMMRegister dst, AddressLiteral src); 1031 1032 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1033 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } 1034 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 1035 void xorps(XMMRegister dst, AddressLiteral src); 1036 1037 // Shuffle Bytes 1038 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } 1039 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } 1040 void pshufb(XMMRegister dst, AddressLiteral src); 1041 // AVX 3-operands instructions 1042 1043 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } 1044 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 1045 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1046 1047 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 1048 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 1049 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1050 1051 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1052 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1053 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1054 1055 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1056 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1057 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1058 1059 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 1060 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 1061 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1062 1063 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } 1064 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 1065 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1066 1067 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } 1068 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 1069 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1070 1071 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } 1072 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 1073 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1074 1075 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } 1076 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 1077 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1078 1079 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } 1080 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 1081 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1082 1083 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1084 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1085 1086 // AVX Vector instructions 1087 1088 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1089 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1090 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1091 1092 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1093 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1094 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1095 1096 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1097 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1098 Assembler::vpxor(dst, nds, src, vector_len); 1099 else 1100 Assembler::vxorpd(dst, nds, src, vector_len); 1101 } 1102 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 1103 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1104 Assembler::vpxor(dst, nds, src, vector_len); 1105 else 1106 Assembler::vxorpd(dst, nds, src, vector_len); 1107 } 1108 1109 // Simple version for AVX2 256bit vectors 1110 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } 1111 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } 1112 1113 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. 1114 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1115 if (UseAVX > 1) // vinserti128h is available only in AVX2 1116 Assembler::vinserti128h(dst, nds, src); 1117 else 1118 Assembler::vinsertf128h(dst, nds, src); 1119 } 1120 1121 // Carry-Less Multiplication Quadword 1122 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1123 // 0x00 - multiply lower 64 bits [0:63] 1124 Assembler::vpclmulqdq(dst, nds, src, 0x00); 1125 } 1126 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1127 // 0x11 - multiply upper 64 bits [64:127] 1128 Assembler::vpclmulqdq(dst, nds, src, 0x11); 1129 } 1130 1131 // Data 1132 1133 void cmov32( Condition cc, Register dst, Address src); 1134 void cmov32( Condition cc, Register dst, Register src); 1135 1136 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 1137 1138 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1139 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1140 1141 void movoop(Register dst, jobject obj); 1142 void movoop(Address dst, jobject obj); 1143 1144 void mov_metadata(Register dst, Metadata* obj); 1145 void mov_metadata(Address dst, Metadata* obj); 1146 1147 void movptr(ArrayAddress dst, Register src); 1148 // can this do an lea? 1149 void movptr(Register dst, ArrayAddress src); 1150 1151 void movptr(Register dst, Address src); 1152 1153 #ifdef _LP64 1154 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1); 1155 #else 1156 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit 1157 #endif 1158 1159 void movptr(Register dst, intptr_t src); 1160 void movptr(Register dst, Register src); 1161 void movptr(Address dst, intptr_t src); 1162 1163 void movptr(Address dst, Register src); 1164 1165 void movptr(Register dst, RegisterOrConstant src) { 1166 if (src.is_constant()) movptr(dst, src.as_constant()); 1167 else movptr(dst, src.as_register()); 1168 } 1169 1170 #ifdef _LP64 1171 // Generally the next two are only used for moving NULL 1172 // Although there are situations in initializing the mark word where 1173 // they could be used. They are dangerous. 1174 1175 // They only exist on LP64 so that int32_t and intptr_t are not the same 1176 // and we have ambiguous declarations. 1177 1178 void movptr(Address dst, int32_t imm32); 1179 void movptr(Register dst, int32_t imm32); 1180 #endif // _LP64 1181 1182 // to avoid hiding movl 1183 void mov32(AddressLiteral dst, Register src); 1184 void mov32(Register dst, AddressLiteral src); 1185 1186 // to avoid hiding movb 1187 void movbyte(ArrayAddress dst, int src); 1188 1189 // Import other mov() methods from the parent class or else 1190 // they will be hidden by the following overriding declaration. 1191 using Assembler::movdl; 1192 using Assembler::movq; 1193 void movdl(XMMRegister dst, AddressLiteral src); 1194 void movq(XMMRegister dst, AddressLiteral src); 1195 1196 // Can push value or effective address 1197 void pushptr(AddressLiteral src); 1198 1199 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 1200 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 1201 1202 void pushoop(jobject obj); 1203 void pushklass(Metadata* obj); 1204 1205 // sign extend as need a l to ptr sized element 1206 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 1207 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 1208 1209 // C2 compiled method's prolog code. 1210 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); 1211 1212 // clear memory of size 'cnt' qwords, starting at 'base'. 1213 void clear_mem(Register base, Register cnt, Register rtmp); 1214 1215 // IndexOf strings. 1216 // Small strings are loaded through stack if they cross page boundary. 1217 void string_indexof(Register str1, Register str2, 1218 Register cnt1, Register cnt2, 1219 int int_cnt2, Register result, 1220 XMMRegister vec, Register tmp); 1221 1222 // IndexOf for constant substrings with size >= 8 elements 1223 // which don't need to be loaded through stack. 1224 void string_indexofC8(Register str1, Register str2, 1225 Register cnt1, Register cnt2, 1226 int int_cnt2, Register result, 1227 XMMRegister vec, Register tmp); 1228 1229 // Smallest code: we don't need to load through stack, 1230 // check string tail. 1231 1232 // Compare strings. 1233 void string_compare(Register str1, Register str2, 1234 Register cnt1, Register cnt2, Register result, 1235 XMMRegister vec1); 1236 1237 // Compare char[] arrays. 1238 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 1239 Register limit, Register result, Register chr, 1240 XMMRegister vec1, XMMRegister vec2); 1241 1242 // Fill primitive arrays 1243 void generate_fill(BasicType t, bool aligned, 1244 Register to, Register value, Register count, 1245 Register rtmp, XMMRegister xtmp); 1246 1247 void encode_iso_array(Register src, Register dst, Register len, 1248 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1249 XMMRegister tmp4, Register tmp5, Register result); 1250 1251 #ifdef _LP64 1252 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); 1253 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1254 Register y, Register y_idx, Register z, 1255 Register carry, Register product, 1256 Register idx, Register kdx); 1257 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 1258 Register yz_idx, Register idx, 1259 Register carry, Register product, int offset); 1260 void multiply_128_x_128_bmi2_loop(Register y, Register z, 1261 Register carry, Register carry2, 1262 Register idx, Register jdx, 1263 Register yz_idx1, Register yz_idx2, 1264 Register tmp, Register tmp3, Register tmp4); 1265 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 1266 Register yz_idx, Register idx, Register jdx, 1267 Register carry, Register product, 1268 Register carry2); 1269 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 1270 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5); 1271 1272 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3, 1273 Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1274 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, 1275 Register tmp2); 1276 void multiply_add_64(Register sum, Register op1, Register op2, Register carry, 1277 Register rdxReg, Register raxReg); 1278 void add_one_64(Register z, Register zlen, Register carry, Register tmp1); 1279 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1280 Register tmp3, Register tmp4); 1281 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1282 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1283 1284 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1, 1285 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1286 Register raxReg); 1287 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1, 1288 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1289 Register raxReg); 1290 #endif 1291 1292 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1293 void update_byte_crc32(Register crc, Register val, Register table); 1294 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); 1295 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic 1296 // Note on a naming convention: 1297 // Prefix w = register only used on a Westmere+ architecture 1298 // Prefix n = register only used on a Nehalem architecture 1299 #ifdef _LP64 1300 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1301 Register tmp1, Register tmp2, Register tmp3); 1302 #else 1303 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1304 Register tmp1, Register tmp2, Register tmp3, 1305 XMMRegister xtmp1, XMMRegister xtmp2); 1306 #endif 1307 void crc32c_pclmulqdq(XMMRegister w_xtmp1, 1308 Register in_out, 1309 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 1310 XMMRegister w_xtmp2, 1311 Register tmp1, 1312 Register n_tmp2, Register n_tmp3); 1313 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 1314 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1315 Register tmp1, Register tmp2, 1316 Register n_tmp3); 1317 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 1318 Register in_out1, Register in_out2, Register in_out3, 1319 Register tmp1, Register tmp2, Register tmp3, 1320 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1321 Register tmp4, Register tmp5, 1322 Register n_tmp6); 1323 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 1324 Register tmp1, Register tmp2, Register tmp3, 1325 Register tmp4, Register tmp5, Register tmp6, 1326 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1327 bool is_pclmulqdq_supported); 1328 // Fold 128-bit data chunk 1329 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); 1330 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); 1331 // Fold 8-bit data 1332 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1333 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); 1334 1335 #undef VIRTUAL 1336 1337 }; 1338 1339 /** 1340 * class SkipIfEqual: 1341 * 1342 * Instantiating this class will result in assembly code being output that will 1343 * jump around any code emitted between the creation of the instance and it's 1344 * automatic destruction at the end of a scope block, depending on the value of 1345 * the flag passed to the constructor, which will be checked at run-time. 1346 */ 1347 class SkipIfEqual { 1348 private: 1349 MacroAssembler* _masm; 1350 Label _label; 1351 1352 public: 1353 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1354 ~SkipIfEqual(); 1355 }; 1356 1357 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP