1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 #ifdef CC_INTERP
51 // c++ interpreter never wants to use interp_masm version of call_VM
52 #define VIRTUAL
53 #else
54 #define VIRTUAL virtual
55 #endif
56
57 VIRTUAL void call_VM_leaf_base(
58 address entry_point, // the entry point
59 int number_of_arguments, // the number of arguments to pop after the call
60 Label *retaddr = NULL
61 );
62
63 VIRTUAL void call_VM_leaf_base(
64 address entry_point, // the entry point
65 int number_of_arguments, // the number of arguments to pop after the call
66 Label &retaddr) {
67 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
68 }
69
70 // This is the base routine called by the different versions of call_VM. The interpreter
71 // may customize this version by overriding it for its purposes (e.g., to save/restore
72 // additional registers when doing a VM call).
73 //
74 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
75 // returns the register which contains the thread upon return. If a thread register has been
76 // specified, the return value will correspond to that register. If no last_java_sp is specified
77 // (noreg) than rsp will be used instead.
78 VIRTUAL void call_VM_base( // returns the register containing the thread upon return
79 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
80 Register java_thread, // the thread if computed before ; use noreg otherwise
81 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
82 address entry_point, // the entry point
83 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
84 bool check_exceptions // whether to check for pending exceptions after return
85 );
86
87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
88 // The implementation is only non-empty for the InterpreterMacroAssembler,
89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
90 virtual void check_and_handle_popframe(Register java_thread);
91 virtual void check_and_handle_earlyret(Register java_thread);
92
93 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
94
95 // Maximum size of class area in Metaspace when compressed
96 uint64_t use_XOR_for_compressed_class_base;
97
98 public:
99 MacroAssembler(CodeBuffer* code) : Assembler(code) {
100 use_XOR_for_compressed_class_base
101 = (operand_valid_for_logical_immediate(false /*is32*/,
102 (uint64_t)Universe::narrow_klass_base())
103 && ((uint64_t)Universe::narrow_klass_base()
104 > (1u << log2_intptr(CompressedClassSpaceSize))));
105 }
106
107 // Biased locking support
108 // lock_reg and obj_reg must be loaded up with the appropriate values.
109 // swap_reg is killed.
110 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
111 // Optional slow case is for implementations (interpreter and C1) which branch to
112 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
113 // Returns offset of first potentially-faulting instruction for null
114 // check info (currently consumed only by C1). If
115 // swap_reg_contains_mark is true then returns -1 as it is assumed
116 // the calling code has already passed any potential faults.
117 int biased_locking_enter(Register lock_reg, Register obj_reg,
118 Register swap_reg, Register tmp_reg,
119 bool swap_reg_contains_mark,
120 Label& done, Label* slow_case = NULL,
121 BiasedLockingCounters* counters = NULL);
122 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
123
124
125 // Helper functions for statistics gathering.
126 // Unconditional atomic increment.
127 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
128 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
129 lea(tmp1, counter_addr);
130 atomic_incw(tmp1, tmp2, tmp3);
131 }
132 // Load Effective Address
133 void lea(Register r, const Address &a) {
134 InstructionMark im(this);
135 code_section()->relocate(inst_mark(), a.rspec());
136 a.lea(this, r);
137 }
138
139 void addmw(Address a, Register incr, Register scratch) {
140 ldrw(scratch, a);
141 addw(scratch, scratch, incr);
142 strw(scratch, a);
143 }
144
145 // Add constant to memory word
146 void addmw(Address a, int imm, Register scratch) {
147 ldrw(scratch, a);
148 if (imm > 0)
149 addw(scratch, scratch, (unsigned)imm);
150 else
151 subw(scratch, scratch, (unsigned)-imm);
152 strw(scratch, a);
153 }
154
155 void bind(Label& L) {
156 Assembler::bind(L);
157 code()->clear_last_membar();
158 }
159
160 void membar(Membar_mask_bits order_constraint);
161
162 // Frame creation and destruction shared between JITs.
163 void build_frame(int framesize);
164 void remove_frame(int framesize);
165
166 virtual void _call_Unimplemented(address call_site) {
167 mov(rscratch2, call_site);
168 haltsim();
169 }
170
171 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
172
173 virtual void notify(int type);
174
175 // aliases defined in AARCH64 spec
176
177 template<class T>
178 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
179 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
180
181 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
182 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
183
184 void cset(Register Rd, Assembler::Condition cond) {
185 csinc(Rd, zr, zr, ~cond);
186 }
187 void csetw(Register Rd, Assembler::Condition cond) {
188 csincw(Rd, zr, zr, ~cond);
189 }
190
191 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
192 csneg(Rd, Rn, Rn, ~cond);
193 }
194 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
195 csnegw(Rd, Rn, Rn, ~cond);
196 }
197
198 inline void movw(Register Rd, Register Rn) {
199 if (Rd == sp || Rn == sp) {
200 addw(Rd, Rn, 0U);
201 } else {
202 orrw(Rd, zr, Rn);
203 }
204 }
205 inline void mov(Register Rd, Register Rn) {
206 assert(Rd != r31_sp && Rn != r31_sp, "should be");
207 if (Rd == Rn) {
208 } else if (Rd == sp || Rn == sp) {
209 add(Rd, Rn, 0U);
210 } else {
211 orr(Rd, zr, Rn);
212 }
213 }
214
215 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
216 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
217
218 inline void tstw(Register Rd, unsigned imm) { andsw(zr, Rd, imm); }
219 inline void tst(Register Rd, unsigned imm) { ands(zr, Rd, imm); }
220
221 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
222 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
223 }
224 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
226 }
227
228 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
229 bfmw(Rd, Rn, lsb, (lsb + width - 1));
230 }
231 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 bfm(Rd, Rn, lsb , (lsb + width - 1));
233 }
234
235 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
236 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
237 }
238 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
240 }
241
242 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
243 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
244 }
245 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 sbfm(Rd, Rn, lsb , (lsb + width - 1));
247 }
248
249 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
250 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
251 }
252 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
254 }
255
256 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
257 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
258 }
259 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
260 ubfm(Rd, Rn, lsb , (lsb + width - 1));
261 }
262
263 inline void asrw(Register Rd, Register Rn, unsigned imm) {
264 sbfmw(Rd, Rn, imm, 31);
265 }
266
267 inline void asr(Register Rd, Register Rn, unsigned imm) {
268 sbfm(Rd, Rn, imm, 63);
269 }
270
271 inline void lslw(Register Rd, Register Rn, unsigned imm) {
272 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
273 }
274
275 inline void lsl(Register Rd, Register Rn, unsigned imm) {
276 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
277 }
278
279 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
280 ubfmw(Rd, Rn, imm, 31);
281 }
282
283 inline void lsr(Register Rd, Register Rn, unsigned imm) {
284 ubfm(Rd, Rn, imm, 63);
285 }
286
287 inline void rorw(Register Rd, Register Rn, unsigned imm) {
288 extrw(Rd, Rn, Rn, imm);
289 }
290
291 inline void ror(Register Rd, Register Rn, unsigned imm) {
292 extr(Rd, Rn, Rn, imm);
293 }
294
295 inline void sxtbw(Register Rd, Register Rn) {
296 sbfmw(Rd, Rn, 0, 7);
297 }
298 inline void sxthw(Register Rd, Register Rn) {
299 sbfmw(Rd, Rn, 0, 15);
300 }
301 inline void sxtb(Register Rd, Register Rn) {
302 sbfm(Rd, Rn, 0, 7);
303 }
304 inline void sxth(Register Rd, Register Rn) {
305 sbfm(Rd, Rn, 0, 15);
306 }
307 inline void sxtw(Register Rd, Register Rn) {
308 sbfm(Rd, Rn, 0, 31);
309 }
310
311 inline void uxtbw(Register Rd, Register Rn) {
312 ubfmw(Rd, Rn, 0, 7);
313 }
314 inline void uxthw(Register Rd, Register Rn) {
315 ubfmw(Rd, Rn, 0, 15);
316 }
317 inline void uxtb(Register Rd, Register Rn) {
318 ubfm(Rd, Rn, 0, 7);
319 }
320 inline void uxth(Register Rd, Register Rn) {
321 ubfm(Rd, Rn, 0, 15);
322 }
323 inline void uxtw(Register Rd, Register Rn) {
324 ubfm(Rd, Rn, 0, 31);
325 }
326
327 inline void cmnw(Register Rn, Register Rm) {
328 addsw(zr, Rn, Rm);
329 }
330 inline void cmn(Register Rn, Register Rm) {
331 adds(zr, Rn, Rm);
332 }
333
334 inline void cmpw(Register Rn, Register Rm) {
335 subsw(zr, Rn, Rm);
336 }
337 inline void cmp(Register Rn, Register Rm) {
338 subs(zr, Rn, Rm);
339 }
340
341 inline void negw(Register Rd, Register Rn) {
342 subw(Rd, zr, Rn);
343 }
344
345 inline void neg(Register Rd, Register Rn) {
346 sub(Rd, zr, Rn);
347 }
348
349 inline void negsw(Register Rd, Register Rn) {
350 subsw(Rd, zr, Rn);
351 }
352
353 inline void negs(Register Rd, Register Rn) {
354 subs(Rd, zr, Rn);
355 }
356
357 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
358 addsw(zr, Rn, Rm, kind, shift);
359 }
360 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 adds(zr, Rn, Rm, kind, shift);
362 }
363
364 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
365 subsw(zr, Rn, Rm, kind, shift);
366 }
367 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
368 subs(zr, Rn, Rm, kind, shift);
369 }
370
371 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
372 subw(Rd, zr, Rn, kind, shift);
373 }
374
375 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
376 sub(Rd, zr, Rn, kind, shift);
377 }
378
379 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
380 subsw(Rd, zr, Rn, kind, shift);
381 }
382
383 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
384 subs(Rd, zr, Rn, kind, shift);
385 }
386
387 inline void mnegw(Register Rd, Register Rn, Register Rm) {
388 msubw(Rd, Rn, Rm, zr);
389 }
390 inline void mneg(Register Rd, Register Rn, Register Rm) {
391 msub(Rd, Rn, Rm, zr);
392 }
393
394 inline void mulw(Register Rd, Register Rn, Register Rm) {
395 maddw(Rd, Rn, Rm, zr);
396 }
397 inline void mul(Register Rd, Register Rn, Register Rm) {
398 madd(Rd, Rn, Rm, zr);
399 }
400
401 inline void smnegl(Register Rd, Register Rn, Register Rm) {
402 smsubl(Rd, Rn, Rm, zr);
403 }
404 inline void smull(Register Rd, Register Rn, Register Rm) {
405 smaddl(Rd, Rn, Rm, zr);
406 }
407
408 inline void umnegl(Register Rd, Register Rn, Register Rm) {
409 umsubl(Rd, Rn, Rm, zr);
410 }
411 inline void umull(Register Rd, Register Rn, Register Rm) {
412 umaddl(Rd, Rn, Rm, zr);
413 }
414
415 #define WRAP(INSN) \
416 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
417 if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
418 nop(); \
419 Assembler::INSN(Rd, Rn, Rm, Ra); \
420 }
421
422 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
423 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
424 #undef WRAP
425
426
427 // macro assembly operations needed for aarch64
428
429 // first two private routines for loading 32 bit or 64 bit constants
430 private:
431
432 void mov_immediate64(Register dst, u_int64_t imm64);
433 void mov_immediate32(Register dst, u_int32_t imm32);
434
435 int push(unsigned int bitset, Register stack);
436 int pop(unsigned int bitset, Register stack);
437
438 void mov(Register dst, Address a);
439
440 public:
441 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
442 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
443
444 // now mov instructions for loading absolute addresses and 32 or
445 // 64 bit integers
446
447 inline void mov(Register dst, address addr)
448 {
449 mov_immediate64(dst, (u_int64_t)addr);
450 }
451
452 inline void mov(Register dst, u_int64_t imm64)
453 {
454 mov_immediate64(dst, imm64);
455 }
456
457 inline void movw(Register dst, u_int32_t imm32)
458 {
459 mov_immediate32(dst, imm32);
460 }
461
462 inline void mov(Register dst, long l)
463 {
464 mov(dst, (u_int64_t)l);
465 }
466
467 inline void mov(Register dst, int i)
468 {
469 mov(dst, (long)i);
470 }
471
472 void mov(Register dst, RegisterOrConstant src) {
473 if (src.is_register())
474 mov(dst, src.as_register());
475 else
476 mov(dst, src.as_constant());
477 }
478
479 void movptr(Register r, uintptr_t imm64);
480
481 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
482
483 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
484 orr(Vd, T, Vn, Vn);
485 }
486
487 // macro instructions for accessing and updating floating point
488 // status register
489 //
490 // FPSR : op1 == 011
491 // CRn == 0100
492 // CRm == 0100
493 // op2 == 001
494
495 inline void get_fpsr(Register reg)
496 {
497 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
498 }
499
500 inline void set_fpsr(Register reg)
501 {
502 msr(0b011, 0b0100, 0b0100, 0b001, reg);
503 }
504
505 inline void clear_fpsr()
506 {
507 msr(0b011, 0b0100, 0b0100, 0b001, zr);
508 }
509
510 // idiv variant which deals with MINLONG as dividend and -1 as divisor
511 int corrected_idivl(Register result, Register ra, Register rb,
512 bool want_remainder, Register tmp = rscratch1);
513 int corrected_idivq(Register result, Register ra, Register rb,
514 bool want_remainder, Register tmp = rscratch1);
515
516 // Support for NULL-checks
517 //
518 // Generates code that causes a NULL OS exception if the content of reg is NULL.
519 // If the accessed location is M[reg + offset] and the offset is known, provide the
520 // offset. No explicit code generation is needed if the offset is within a certain
521 // range (0 <= offset <= page_size).
522
523 virtual void null_check(Register reg, int offset = -1);
524 static bool needs_explicit_null_check(intptr_t offset);
525
526 static address target_addr_for_insn(address insn_addr, unsigned insn);
527 static address target_addr_for_insn(address insn_addr) {
528 unsigned insn = *(unsigned*)insn_addr;
529 return target_addr_for_insn(insn_addr, insn);
530 }
531
532 // Required platform-specific helpers for Label::patch_instructions.
533 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
534 static int pd_patch_instruction_size(address branch, address target);
535 static void pd_patch_instruction(address branch, address target) {
536 pd_patch_instruction_size(branch, target);
537 }
538 static address pd_call_destination(address branch) {
539 return target_addr_for_insn(branch);
540 }
541 #ifndef PRODUCT
542 static void pd_print_patched_instruction(address branch);
543 #endif
544
545 static int patch_oop(address insn_addr, address o);
546
547 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
548
549 // The following 4 methods return the offset of the appropriate move instruction
550
551 // Support for fast byte/short loading with zero extension (depending on particular CPU)
552 int load_unsigned_byte(Register dst, Address src);
553 int load_unsigned_short(Register dst, Address src);
554
555 // Support for fast byte/short loading with sign extension (depending on particular CPU)
556 int load_signed_byte(Register dst, Address src);
557 int load_signed_short(Register dst, Address src);
558
559 int load_signed_byte32(Register dst, Address src);
560 int load_signed_short32(Register dst, Address src);
561
562 // Support for sign-extension (hi:lo = extend_sign(lo))
563 void extend_sign(Register hi, Register lo);
564
565 // Load and store values by size and signed-ness
566 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
567 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
568
569 // Support for inc/dec with optimal instruction selection depending on value
570
571 // x86_64 aliases an unqualified register/address increment and
572 // decrement to call incrementq and decrementq but also supports
573 // explicitly sized calls to incrementq/decrementq or
574 // incrementl/decrementl
575
576 // for aarch64 the proper convention would be to use
577 // increment/decrement for 64 bit operatons and
578 // incrementw/decrementw for 32 bit operations. so when porting
579 // x86_64 code we can leave calls to increment/decrement as is,
580 // replace incrementq/decrementq with increment/decrement and
581 // replace incrementl/decrementl with incrementw/decrementw.
582
583 // n.b. increment/decrement calls with an Address destination will
584 // need to use a scratch register to load the value to be
585 // incremented. increment/decrement calls which add or subtract a
586 // constant value greater than 2^12 will need to use a 2nd scratch
587 // register to hold the constant. so, a register increment/decrement
588 // may trash rscratch2 and an address increment/decrement trash
589 // rscratch and rscratch2
590
591 void decrementw(Address dst, int value = 1);
592 void decrementw(Register reg, int value = 1);
593
594 void decrement(Register reg, int value = 1);
595 void decrement(Address dst, int value = 1);
596
597 void incrementw(Address dst, int value = 1);
598 void incrementw(Register reg, int value = 1);
599
600 void increment(Register reg, int value = 1);
601 void increment(Address dst, int value = 1);
602
603
604 // Alignment
605 void align(int modulus);
606
607 // Stack frame creation/removal
608 void enter()
609 {
610 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
611 mov(rfp, sp);
612 }
613 void leave()
614 {
615 mov(sp, rfp);
616 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
617 }
618
619 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
620 // The pointer will be loaded into the thread register.
621 void get_thread(Register thread);
622
623
624 // Support for VM calls
625 //
626 // It is imperative that all calls into the VM are handled via the call_VM macros.
627 // They make sure that the stack linkage is setup correctly. call_VM's correspond
628 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
629
630
631 void call_VM(Register oop_result,
632 address entry_point,
633 bool check_exceptions = true);
634 void call_VM(Register oop_result,
635 address entry_point,
636 Register arg_1,
637 bool check_exceptions = true);
638 void call_VM(Register oop_result,
639 address entry_point,
640 Register arg_1, Register arg_2,
641 bool check_exceptions = true);
642 void call_VM(Register oop_result,
643 address entry_point,
644 Register arg_1, Register arg_2, Register arg_3,
645 bool check_exceptions = true);
646
647 // Overloadings with last_Java_sp
648 void call_VM(Register oop_result,
649 Register last_java_sp,
650 address entry_point,
651 int number_of_arguments = 0,
652 bool check_exceptions = true);
653 void call_VM(Register oop_result,
654 Register last_java_sp,
655 address entry_point,
656 Register arg_1, bool
657 check_exceptions = true);
658 void call_VM(Register oop_result,
659 Register last_java_sp,
660 address entry_point,
661 Register arg_1, Register arg_2,
662 bool check_exceptions = true);
663 void call_VM(Register oop_result,
664 Register last_java_sp,
665 address entry_point,
666 Register arg_1, Register arg_2, Register arg_3,
667 bool check_exceptions = true);
668
669 void get_vm_result (Register oop_result, Register thread);
670 void get_vm_result_2(Register metadata_result, Register thread);
671
672 // These always tightly bind to MacroAssembler::call_VM_base
673 // bypassing the virtual implementation
674 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
675 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
676 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
677 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
678 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
679
680 void call_VM_leaf(address entry_point,
681 int number_of_arguments = 0);
682 void call_VM_leaf(address entry_point,
683 Register arg_1);
684 void call_VM_leaf(address entry_point,
685 Register arg_1, Register arg_2);
686 void call_VM_leaf(address entry_point,
687 Register arg_1, Register arg_2, Register arg_3);
688
689 // These always tightly bind to MacroAssembler::call_VM_leaf_base
690 // bypassing the virtual implementation
691 void super_call_VM_leaf(address entry_point);
692 void super_call_VM_leaf(address entry_point, Register arg_1);
693 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
694 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
695 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
696
697 // last Java Frame (fills frame anchor)
698 void set_last_Java_frame(Register last_java_sp,
699 Register last_java_fp,
700 address last_java_pc,
701 Register scratch);
702
703 void set_last_Java_frame(Register last_java_sp,
704 Register last_java_fp,
705 Label &last_java_pc,
706 Register scratch);
707
708 void set_last_Java_frame(Register last_java_sp,
709 Register last_java_fp,
710 Register last_java_pc,
711 Register scratch);
712
713 void reset_last_Java_frame(Register thread, bool clearfp, bool clear_pc);
714
715 // thread in the default location (r15_thread on 64bit)
716 void reset_last_Java_frame(bool clear_fp, bool clear_pc);
717
718 // Stores
719 void store_check(Register obj); // store check for obj - register is destroyed afterwards
720 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
721
722 #if INCLUDE_ALL_GCS
723
724 void g1_write_barrier_pre(Register obj,
725 Register pre_val,
726 Register thread,
727 Register tmp,
728 bool tosca_live,
729 bool expand_call);
730
731 void g1_write_barrier_post(Register store_addr,
732 Register new_val,
733 Register thread,
734 Register tmp,
735 Register tmp2);
736
737 #endif // INCLUDE_ALL_GCS
738
739 // oop manipulations
740 void load_klass(Register dst, Register src);
741 void store_klass(Register dst, Register src);
742 void cmp_klass(Register oop, Register trial_klass, Register tmp);
743
744 void load_heap_oop(Register dst, Address src);
745
746 void load_heap_oop_not_null(Register dst, Address src);
747 void store_heap_oop(Address dst, Register src);
748
749 // currently unimplemented
750 // Used for storing NULL. All other oop constants should be
751 // stored using routines that take a jobject.
752 void store_heap_oop_null(Address dst);
753
754 void load_prototype_header(Register dst, Register src);
755
756 void store_klass_gap(Register dst, Register src);
757
758 // This dummy is to prevent a call to store_heap_oop from
759 // converting a zero (like NULL) into a Register by giving
760 // the compiler two choices it can't resolve
761
762 void store_heap_oop(Address dst, void* dummy);
763
764 void encode_heap_oop(Register d, Register s);
765 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
766 void decode_heap_oop(Register d, Register s);
767 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
768 void encode_heap_oop_not_null(Register r);
769 void decode_heap_oop_not_null(Register r);
770 void encode_heap_oop_not_null(Register dst, Register src);
771 void decode_heap_oop_not_null(Register dst, Register src);
772
773 void set_narrow_oop(Register dst, jobject obj);
774
775 void encode_klass_not_null(Register r);
776 void decode_klass_not_null(Register r);
777 void encode_klass_not_null(Register dst, Register src);
778 void decode_klass_not_null(Register dst, Register src);
779
780 void set_narrow_klass(Register dst, Klass* k);
781
782 // if heap base register is used - reinit it with the correct value
783 void reinit_heapbase();
784
785 DEBUG_ONLY(void verify_heapbase(const char* msg);)
786
787 void push_CPU_state(bool save_vectors = false);
788 void pop_CPU_state(bool restore_vectors = false) ;
789
790 // Round up to a power of two
791 void round_to(Register reg, int modulus);
792
793 // allocation
794 void eden_allocate(
795 Register obj, // result: pointer to object after successful allocation
796 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
797 int con_size_in_bytes, // object size in bytes if known at compile time
798 Register t1, // temp register
799 Label& slow_case // continuation point if fast allocation fails
800 );
801 void tlab_allocate(
802 Register obj, // result: pointer to object after successful allocation
803 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
804 int con_size_in_bytes, // object size in bytes if known at compile time
805 Register t1, // temp register
806 Register t2, // temp register
807 Label& slow_case // continuation point if fast allocation fails
808 );
809 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
810 void verify_tlab();
811
812 void incr_allocated_bytes(Register thread,
813 Register var_size_in_bytes, int con_size_in_bytes,
814 Register t1 = noreg);
815
816 // interface method calling
817 void lookup_interface_method(Register recv_klass,
818 Register intf_klass,
819 RegisterOrConstant itable_index,
820 Register method_result,
821 Register scan_temp,
822 Label& no_such_interface);
823
824 // virtual method calling
825 // n.b. x86 allows RegisterOrConstant for vtable_index
826 void lookup_virtual_method(Register recv_klass,
827 RegisterOrConstant vtable_index,
828 Register method_result);
829
830 // Test sub_klass against super_klass, with fast and slow paths.
831
832 // The fast path produces a tri-state answer: yes / no / maybe-slow.
833 // One of the three labels can be NULL, meaning take the fall-through.
834 // If super_check_offset is -1, the value is loaded up from super_klass.
835 // No registers are killed, except temp_reg.
836 void check_klass_subtype_fast_path(Register sub_klass,
837 Register super_klass,
838 Register temp_reg,
839 Label* L_success,
840 Label* L_failure,
841 Label* L_slow_path,
842 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
843
844 // The rest of the type check; must be wired to a corresponding fast path.
845 // It does not repeat the fast path logic, so don't use it standalone.
846 // The temp_reg and temp2_reg can be noreg, if no temps are available.
847 // Updates the sub's secondary super cache as necessary.
848 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
849 void check_klass_subtype_slow_path(Register sub_klass,
850 Register super_klass,
851 Register temp_reg,
852 Register temp2_reg,
853 Label* L_success,
854 Label* L_failure,
855 bool set_cond_codes = false);
856
857 // Simplified, combined version, good for typical uses.
858 // Falls through on failure.
859 void check_klass_subtype(Register sub_klass,
860 Register super_klass,
861 Register temp_reg,
862 Label& L_success);
863
864 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
865
866
867 // Debugging
868
869 // only if +VerifyOops
870 void verify_oop(Register reg, const char* s = "broken oop");
871 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
872
873 // TODO: verify method and klass metadata (compare against vptr?)
874 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
875 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
876
877 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
878 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
879
880 // only if +VerifyFPU
881 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
882
883 // prints msg, dumps registers and stops execution
884 void stop(const char* msg);
885
886 // prints msg and continues
887 void warn(const char* msg);
888
889 static void debug64(char* msg, int64_t pc, int64_t regs[]);
890
891 void untested() { stop("untested"); }
892
893 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
894
895 void should_not_reach_here() { stop("should not reach here"); }
896
897 // Stack overflow checking
898 void bang_stack_with_offset(int offset) {
899 // stack grows down, caller passes positive offset
900 assert(offset > 0, "must bang with negative offset");
901 mov(rscratch2, -offset);
902 str(zr, Address(sp, rscratch2));
903 }
904
905 // Writes to stack successive pages until offset reached to check for
906 // stack overflow + shadow pages. Also, clobbers tmp
907 void bang_stack_size(Register size, Register tmp);
908
909 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
910 Register tmp,
911 int offset);
912
913 // Support for serializing memory accesses between threads
914 void serialize_memory(Register thread, Register tmp);
915
916 // Arithmetics
917
918 void addptr(const Address &dst, int32_t src);
919 void cmpptr(Register src1, Address src2);
920
921 // Various forms of CAS
922
923 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
924 Label &suceed, Label *fail);
925
926 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
927 Label &suceed, Label *fail);
928
929 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
930 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
931
932 void atomic_xchg(Register prev, Register newv, Register addr);
933 void atomic_xchgw(Register prev, Register newv, Register addr);
934
935 void orptr(Address adr, RegisterOrConstant src) {
936 ldr(rscratch2, adr);
937 if (src.is_register())
938 orr(rscratch2, rscratch2, src.as_register());
939 else
940 orr(rscratch2, rscratch2, src.as_constant());
941 str(rscratch2, adr);
942 }
943
944 // A generic CAS; success or failure is in the EQ flag.
945 template <typename T1, typename T2>
946 void cmpxchg(Register addr, Register expected, Register new_val,
947 T1 load_insn,
948 void (MacroAssembler::*cmp_insn)(Register, Register),
949 T2 store_insn,
950 Register tmp = rscratch1) {
951 Label retry_load, done;
952 bind(retry_load);
953 (this->*load_insn)(tmp, addr);
954 (this->*cmp_insn)(tmp, expected);
955 br(Assembler::NE, done);
956 (this->*store_insn)(tmp, new_val, addr);
957 cbnzw(tmp, retry_load);
958 bind(done);
959 }
960
961 // Calls
962
963 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
964
965 static bool far_branches() {
966 return ReservedCodeCacheSize > branch_range;
967 }
968
969 // Jumps that can reach anywhere in the code cache.
970 // Trashes tmp.
971 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
972 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
973
974 static int far_branch_size() {
975 if (far_branches()) {
976 return 3 * 4; // adrp, add, br
977 } else {
978 return 4;
979 }
980 }
981
982 // Emit the CompiledIC call idiom
983 address ic_call(address entry, jint method_index = 0);
984
985 public:
986
987 // Data
988
989 void mov_metadata(Register dst, Metadata* obj);
990 Address allocate_metadata_address(Metadata* obj);
991 Address constant_oop_address(jobject obj);
992
993 void movoop(Register dst, jobject obj, bool immediate = false);
994
995 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
996 void kernel_crc32(Register crc, Register buf, Register len,
997 Register table0, Register table1, Register table2, Register table3,
998 Register tmp, Register tmp2, Register tmp3);
999 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1000 void kernel_crc32c(Register crc, Register buf, Register len,
1001 Register table0, Register table1, Register table2, Register table3,
1002 Register tmp, Register tmp2, Register tmp3);
1003
1004 #undef VIRTUAL
1005
1006 // Stack push and pop individual 64 bit registers
1007 void push(Register src);
1008 void pop(Register dst);
1009
1010 // push all registers onto the stack
1011 void pusha();
1012 void popa();
1013
1014 void repne_scan(Register addr, Register value, Register count,
1015 Register scratch);
1016 void repne_scanw(Register addr, Register value, Register count,
1017 Register scratch);
1018
1019 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1020 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1021
1022 // If a constant does not fit in an immediate field, generate some
1023 // number of MOV instructions and then perform the operation
1024 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1025 add_sub_imm_insn insn1,
1026 add_sub_reg_insn insn2);
1027 // Seperate vsn which sets the flags
1028 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1029 add_sub_imm_insn insn1,
1030 add_sub_reg_insn insn2);
1031
1032 #define WRAP(INSN) \
1033 void INSN(Register Rd, Register Rn, unsigned imm) { \
1034 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1035 } \
1036 \
1037 void INSN(Register Rd, Register Rn, Register Rm, \
1038 enum shift_kind kind, unsigned shift = 0) { \
1039 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1040 } \
1041 \
1042 void INSN(Register Rd, Register Rn, Register Rm) { \
1043 Assembler::INSN(Rd, Rn, Rm); \
1044 } \
1045 \
1046 void INSN(Register Rd, Register Rn, Register Rm, \
1047 ext::operation option, int amount = 0) { \
1048 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1049 }
1050
1051 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1052
1053 #undef WRAP
1054 #define WRAP(INSN) \
1055 void INSN(Register Rd, Register Rn, unsigned imm) { \
1056 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1057 } \
1058 \
1059 void INSN(Register Rd, Register Rn, Register Rm, \
1060 enum shift_kind kind, unsigned shift = 0) { \
1061 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1062 } \
1063 \
1064 void INSN(Register Rd, Register Rn, Register Rm) { \
1065 Assembler::INSN(Rd, Rn, Rm); \
1066 } \
1067 \
1068 void INSN(Register Rd, Register Rn, Register Rm, \
1069 ext::operation option, int amount = 0) { \
1070 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1071 }
1072
1073 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1074
1075 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1076 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1077 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1078 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1079
1080 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1081
1082 void tableswitch(Register index, jint lowbound, jint highbound,
1083 Label &jumptable, Label &jumptable_end, int stride = 1) {
1084 adr(rscratch1, jumptable);
1085 subsw(rscratch2, index, lowbound);
1086 subsw(zr, rscratch2, highbound - lowbound);
1087 br(Assembler::HS, jumptable_end);
1088 add(rscratch1, rscratch1, rscratch2,
1089 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1090 br(rscratch1);
1091 }
1092
1093 // Form an address from base + offset in Rd. Rd may or may not
1094 // actually be used: you must use the Address that is returned. It
1095 // is up to you to ensure that the shift provided matches the size
1096 // of your data.
1097 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1098
1099 // Prolog generator routines to support switch between x86 code and
1100 // generated ARM code
1101
1102 // routine to generate an x86 prolog for a stub function which
1103 // bootstraps into the generated ARM code which directly follows the
1104 // stub
1105 //
1106
1107 public:
1108 // enum used for aarch64--x86 linkage to define return type of x86 function
1109 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1110
1111 #ifdef BUILTIN_SIM
1112 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1113 #else
1114 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1115 #endif
1116
1117 // special version of call_VM_leaf_base needed for aarch64 simulator
1118 // where we need to specify both the gp and fp arg counts and the
1119 // return type so that the linkage routine from aarch64 to x86 and
1120 // back knows which aarch64 registers to copy to x86 registers and
1121 // which x86 result register to copy back to an aarch64 register
1122
1123 void call_VM_leaf_base1(
1124 address entry_point, // the entry point
1125 int number_of_gp_arguments, // the number of gp reg arguments to pass
1126 int number_of_fp_arguments, // the number of fp reg arguments to pass
1127 ret_type type, // the return type for the call
1128 Label* retaddr = NULL
1129 );
1130
1131 void ldr_constant(Register dest, const Address &const_addr) {
1132 if (NearCpool) {
1133 ldr(dest, const_addr);
1134 } else {
1135 unsigned long offset;
1136 adrp(dest, InternalAddress(const_addr.target()), offset);
1137 ldr(dest, Address(dest, offset));
1138 }
1139 }
1140
1141 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1142 address read_polling_page(Register r, relocInfo::relocType rtype);
1143
1144 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1145 void update_byte_crc32(Register crc, Register val, Register table);
1146 void update_word_crc32(Register crc, Register v, Register tmp,
1147 Register table0, Register table1, Register table2, Register table3,
1148 bool upper = false);
1149
1150 void string_compare(Register str1, Register str2,
1151 Register cnt1, Register cnt2, Register result,
1152 Register tmp1);
1153 void string_equals(Register str1, Register str2,
1154 Register cnt, Register result,
1155 Register tmp1);
1156 void char_arrays_equals(Register ary1, Register ary2,
1157 Register result, Register tmp1);
1158 void encode_iso_array(Register src, Register dst,
1159 Register len, Register result,
1160 FloatRegister Vtmp1, FloatRegister Vtmp2,
1161 FloatRegister Vtmp3, FloatRegister Vtmp4);
1162 void string_indexof(Register str1, Register str2,
1163 Register cnt1, Register cnt2,
1164 Register tmp1, Register tmp2,
1165 Register tmp3, Register tmp4,
1166 int int_cnt1, Register result);
1167 private:
1168 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1169 Register src1, Register src2);
1170 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1171 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1172 }
1173 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1174 Register y, Register y_idx, Register z,
1175 Register carry, Register product,
1176 Register idx, Register kdx);
1177 void multiply_128_x_128_loop(Register y, Register z,
1178 Register carry, Register carry2,
1179 Register idx, Register jdx,
1180 Register yz_idx1, Register yz_idx2,
1181 Register tmp, Register tmp3, Register tmp4,
1182 Register tmp7, Register product_hi);
1183 public:
1184 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1185 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1186 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1187 // ISB may be needed because of a safepoint
1188 void maybe_isb() { isb(); }
1189
1190 private:
1191 // Return the effective address r + (r1 << ext) + offset.
1192 // Uses rscratch2.
1193 Address offsetted_address(Register r, Register r1, Address::extend ext,
1194 int offset, int size);
1195
1196 private:
1197 // Returns an address on the stack which is reachable with a ldr/str of size
1198 // Uses rscratch2 if the address is not directly reachable
1199 Address spill_address(int size, int offset, Register tmp=rscratch2);
1200
1201 public:
1202 void spill(Register Rx, bool is64, int offset) {
1203 if (is64) {
1204 str(Rx, spill_address(8, offset));
1205 } else {
1206 strw(Rx, spill_address(4, offset));
1207 }
1208 }
1209 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1210 str(Vx, T, spill_address(1 << (int)T, offset));
1211 }
1212 void unspill(Register Rx, bool is64, int offset) {
1213 if (is64) {
1214 ldr(Rx, spill_address(8, offset));
1215 } else {
1216 ldrw(Rx, spill_address(4, offset));
1217 }
1218 }
1219 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1220 ldr(Vx, T, spill_address(1 << (int)T, offset));
1221 }
1222 void spill_copy128(int src_offset, int dst_offset,
1223 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1224 if (src_offset < 512 && (src_offset & 7) == 0 &&
1225 dst_offset < 512 && (dst_offset & 7) == 0) {
1226 ldp(tmp1, tmp2, Address(sp, src_offset));
1227 stp(tmp1, tmp2, Address(sp, dst_offset));
1228 } else {
1229 unspill(tmp1, true, src_offset);
1230 spill(tmp1, true, dst_offset);
1231 unspill(tmp1, true, src_offset+8);
1232 spill(tmp1, true, dst_offset+8);
1233 }
1234 }
1235 };
1236
1237 #ifdef ASSERT
1238 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1239 #endif
1240
1241 /**
1242 * class SkipIfEqual:
1243 *
1244 * Instantiating this class will result in assembly code being output that will
1245 * jump around any code emitted between the creation of the instance and it's
1246 * automatic destruction at the end of a scope block, depending on the value of
1247 * the flag passed to the constructor, which will be checked at run-time.
1248 */
1249 class SkipIfEqual {
1250 private:
1251 MacroAssembler* _masm;
1252 Label _label;
1253
1254 public:
1255 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1256 ~SkipIfEqual();
1257 };
1258
1259 struct tableswitch {
1260 Register _reg;
1261 int _insn_index; jint _first_key; jint _last_key;
1262 Label _after;
1263 Label _branches;
1264 };
1265
1266 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP