1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 26 #define CPU_SPARC_VM_ASSEMBLER_SPARC_HPP 27 28 #include "asm/register.hpp" 29 30 // The SPARC Assembler: Pure assembler doing NO optimizations on the instruction 31 // level; i.e., what you write 32 // is what you get. The Assembler is generating code into a CodeBuffer. 33 34 class Assembler : public AbstractAssembler { 35 friend class AbstractAssembler; 36 friend class AddressLiteral; 37 38 // code patchers need various routines like inv_wdisp() 39 friend class NativeInstruction; 40 friend class NativeGeneralJump; 41 friend class Relocation; 42 friend class Label; 43 44 public: 45 // op carries format info; see page 62 & 267 46 47 enum ops { 48 call_op = 1, // fmt 1 49 branch_op = 0, // also sethi (fmt2) 50 arith_op = 2, // fmt 3, arith & misc 51 ldst_op = 3 // fmt 3, load/store 52 }; 53 54 enum op2s { 55 bpr_op2 = 3, 56 fb_op2 = 6, 57 fbp_op2 = 5, 58 br_op2 = 2, 59 bp_op2 = 1, 60 sethi_op2 = 4 61 }; 62 63 enum op3s { 64 // selected op3s 65 add_op3 = 0x00, 66 and_op3 = 0x01, 67 or_op3 = 0x02, 68 xor_op3 = 0x03, 69 sub_op3 = 0x04, 70 andn_op3 = 0x05, 71 orn_op3 = 0x06, 72 xnor_op3 = 0x07, 73 addc_op3 = 0x08, 74 mulx_op3 = 0x09, 75 umul_op3 = 0x0a, 76 smul_op3 = 0x0b, 77 subc_op3 = 0x0c, 78 udivx_op3 = 0x0d, 79 udiv_op3 = 0x0e, 80 sdiv_op3 = 0x0f, 81 82 addcc_op3 = 0x10, 83 andcc_op3 = 0x11, 84 orcc_op3 = 0x12, 85 xorcc_op3 = 0x13, 86 subcc_op3 = 0x14, 87 andncc_op3 = 0x15, 88 orncc_op3 = 0x16, 89 xnorcc_op3 = 0x17, 90 addccc_op3 = 0x18, 91 aes4_op3 = 0x19, 92 umulcc_op3 = 0x1a, 93 smulcc_op3 = 0x1b, 94 subccc_op3 = 0x1c, 95 udivcc_op3 = 0x1e, 96 sdivcc_op3 = 0x1f, 97 98 taddcc_op3 = 0x20, 99 tsubcc_op3 = 0x21, 100 taddcctv_op3 = 0x22, 101 tsubcctv_op3 = 0x23, 102 mulscc_op3 = 0x24, 103 sll_op3 = 0x25, 104 sllx_op3 = 0x25, 105 srl_op3 = 0x26, 106 srlx_op3 = 0x26, 107 sra_op3 = 0x27, 108 srax_op3 = 0x27, 109 rdreg_op3 = 0x28, 110 membar_op3 = 0x28, 111 112 flushw_op3 = 0x2b, 113 movcc_op3 = 0x2c, 114 sdivx_op3 = 0x2d, 115 popc_op3 = 0x2e, 116 movr_op3 = 0x2f, 117 118 sir_op3 = 0x30, 119 wrreg_op3 = 0x30, 120 saved_op3 = 0x31, 121 122 fpop1_op3 = 0x34, 123 fpop2_op3 = 0x35, 124 impdep1_op3 = 0x36, 125 aes3_op3 = 0x36, 126 sha_op3 = 0x36, 127 bmask_op3 = 0x36, 128 bshuffle_op3 = 0x36, 129 alignaddr_op3 = 0x36, 130 faligndata_op3 = 0x36, 131 flog3_op3 = 0x36, 132 edge_op3 = 0x36, 133 fzero_op3 = 0x36, 134 fsrc_op3 = 0x36, 135 fnot_op3 = 0x36, 136 xmulx_op3 = 0x36, 137 crc32c_op3 = 0x36, 138 impdep2_op3 = 0x37, 139 stpartialf_op3 = 0x37, 140 jmpl_op3 = 0x38, 141 rett_op3 = 0x39, 142 trap_op3 = 0x3a, 143 flush_op3 = 0x3b, 144 save_op3 = 0x3c, 145 restore_op3 = 0x3d, 146 done_op3 = 0x3e, 147 retry_op3 = 0x3e, 148 149 lduw_op3 = 0x00, 150 ldub_op3 = 0x01, 151 lduh_op3 = 0x02, 152 ldd_op3 = 0x03, 153 stw_op3 = 0x04, 154 stb_op3 = 0x05, 155 sth_op3 = 0x06, 156 std_op3 = 0x07, 157 ldsw_op3 = 0x08, 158 ldsb_op3 = 0x09, 159 ldsh_op3 = 0x0a, 160 ldx_op3 = 0x0b, 161 162 stx_op3 = 0x0e, 163 swap_op3 = 0x0f, 164 165 stwa_op3 = 0x14, 166 stxa_op3 = 0x1e, 167 168 ldf_op3 = 0x20, 169 ldfsr_op3 = 0x21, 170 ldqf_op3 = 0x22, 171 lddf_op3 = 0x23, 172 stf_op3 = 0x24, 173 stfsr_op3 = 0x25, 174 stqf_op3 = 0x26, 175 stdf_op3 = 0x27, 176 177 prefetch_op3 = 0x2d, 178 179 casa_op3 = 0x3c, 180 casxa_op3 = 0x3e, 181 182 mftoi_op3 = 0x36, 183 184 alt_bit_op3 = 0x10, 185 cc_bit_op3 = 0x10 186 }; 187 188 enum opfs { 189 // selected opfs 190 edge8n_opf = 0x01, 191 192 fmovs_opf = 0x01, 193 fmovd_opf = 0x02, 194 195 fnegs_opf = 0x05, 196 fnegd_opf = 0x06, 197 198 alignaddr_opf = 0x18, 199 bmask_opf = 0x19, 200 201 fadds_opf = 0x41, 202 faddd_opf = 0x42, 203 fsubs_opf = 0x45, 204 fsubd_opf = 0x46, 205 206 faligndata_opf = 0x48, 207 208 fmuls_opf = 0x49, 209 fmuld_opf = 0x4a, 210 bshuffle_opf = 0x4c, 211 fdivs_opf = 0x4d, 212 fdivd_opf = 0x4e, 213 214 fcmps_opf = 0x51, 215 fcmpd_opf = 0x52, 216 217 fstox_opf = 0x81, 218 fdtox_opf = 0x82, 219 fxtos_opf = 0x84, 220 fxtod_opf = 0x88, 221 fitos_opf = 0xc4, 222 fdtos_opf = 0xc6, 223 fitod_opf = 0xc8, 224 fstod_opf = 0xc9, 225 fstoi_opf = 0xd1, 226 fdtoi_opf = 0xd2, 227 228 mdtox_opf = 0x110, 229 mstouw_opf = 0x111, 230 mstosw_opf = 0x113, 231 xmulx_opf = 0x115, 232 xmulxhi_opf = 0x116, 233 mxtod_opf = 0x118, 234 mwtos_opf = 0x119, 235 236 aes_kexpand0_opf = 0x130, 237 aes_kexpand2_opf = 0x131, 238 239 sha1_opf = 0x141, 240 sha256_opf = 0x142, 241 sha512_opf = 0x143, 242 243 crc32c_opf = 0x147 244 }; 245 246 enum op5s { 247 aes_eround01_op5 = 0x00, 248 aes_eround23_op5 = 0x01, 249 aes_dround01_op5 = 0x02, 250 aes_dround23_op5 = 0x03, 251 aes_eround01_l_op5 = 0x04, 252 aes_eround23_l_op5 = 0x05, 253 aes_dround01_l_op5 = 0x06, 254 aes_dround23_l_op5 = 0x07, 255 aes_kexpand1_op5 = 0x08 256 }; 257 258 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7, rc_last = rc_gez }; 259 260 enum Condition { 261 // for FBfcc & FBPfcc instruction 262 f_never = 0, 263 f_notEqual = 1, 264 f_notZero = 1, 265 f_lessOrGreater = 2, 266 f_unorderedOrLess = 3, 267 f_less = 4, 268 f_unorderedOrGreater = 5, 269 f_greater = 6, 270 f_unordered = 7, 271 f_always = 8, 272 f_equal = 9, 273 f_zero = 9, 274 f_unorderedOrEqual = 10, 275 f_greaterOrEqual = 11, 276 f_unorderedOrGreaterOrEqual = 12, 277 f_lessOrEqual = 13, 278 f_unorderedOrLessOrEqual = 14, 279 f_ordered = 15, 280 281 // V8 coproc, pp 123 v8 manual 282 283 cp_always = 8, 284 cp_never = 0, 285 cp_3 = 7, 286 cp_2 = 6, 287 cp_2or3 = 5, 288 cp_1 = 4, 289 cp_1or3 = 3, 290 cp_1or2 = 2, 291 cp_1or2or3 = 1, 292 cp_0 = 9, 293 cp_0or3 = 10, 294 cp_0or2 = 11, 295 cp_0or2or3 = 12, 296 cp_0or1 = 13, 297 cp_0or1or3 = 14, 298 cp_0or1or2 = 15, 299 300 301 // for integers 302 303 never = 0, 304 equal = 1, 305 zero = 1, 306 lessEqual = 2, 307 less = 3, 308 lessEqualUnsigned = 4, 309 lessUnsigned = 5, 310 carrySet = 5, 311 negative = 6, 312 overflowSet = 7, 313 always = 8, 314 notEqual = 9, 315 notZero = 9, 316 greater = 10, 317 greaterEqual = 11, 318 greaterUnsigned = 12, 319 greaterEqualUnsigned = 13, 320 carryClear = 13, 321 positive = 14, 322 overflowClear = 15 323 }; 324 325 enum CC { 326 icc = 0, xcc = 2, 327 // ptr_cc is the correct condition code for a pointer or intptr_t: 328 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), 329 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 330 }; 331 332 enum PrefetchFcn { 333 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 334 }; 335 336 public: 337 // Helper functions for groups of instructions 338 339 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 340 341 enum Membar_mask_bits { // page 184, v9 342 StoreStore = 1 << 3, 343 LoadStore = 1 << 2, 344 StoreLoad = 1 << 1, 345 LoadLoad = 1 << 0, 346 347 Sync = 1 << 6, 348 MemIssue = 1 << 5, 349 Lookaside = 1 << 4 350 }; 351 352 static bool is_in_wdisp_range(address a, address b, int nbits) { 353 intptr_t d = intptr_t(b) - intptr_t(a); 354 return is_simm(d, nbits + 2); 355 } 356 357 address target_distance(Label& L) { 358 // Assembler::target(L) should be called only when 359 // a branch instruction is emitted since non-bound 360 // labels record current pc() as a branch address. 361 if (L.is_bound()) return target(L); 362 // Return current address for non-bound labels. 363 return pc(); 364 } 365 366 // test if label is in simm16 range in words (wdisp16). 367 bool is_in_wdisp16_range(Label& L) { 368 return is_in_wdisp_range(target_distance(L), pc(), 16); 369 } 370 // test if the distance between two addresses fits in simm30 range in words 371 static bool is_in_wdisp30_range(address a, address b) { 372 return is_in_wdisp_range(a, b, 30); 373 } 374 375 enum ASIs { // page 72, v9 376 ASI_PRIMARY = 0x80, 377 ASI_PRIMARY_NOFAULT = 0x82, 378 ASI_PRIMARY_LITTLE = 0x88, 379 // 8x8-bit partial store 380 ASI_PST8_PRIMARY = 0xC0, 381 // Block initializing store 382 ASI_ST_BLKINIT_PRIMARY = 0xE2, 383 // Most-Recently-Used (MRU) BIS variant 384 ASI_ST_BLKINIT_MRU_PRIMARY = 0xF2 385 // add more from book as needed 386 }; 387 388 protected: 389 // helpers 390 391 // x is supposed to fit in a field "nbits" wide 392 // and be sign-extended. Check the range. 393 394 static void assert_signed_range(intptr_t x, int nbits) { 395 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < ( 1 << nbits-1)), 396 "value out of range: x=" INTPTR_FORMAT ", nbits=%d", x, nbits); 397 } 398 399 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 400 assert( (x & 3) == 0, "not word aligned"); 401 assert_signed_range(x, nbits + 2); 402 } 403 404 static void assert_unsigned_const(int x, int nbits) { 405 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); 406 } 407 408 // fields: note bits numbered from LSB = 0, 409 // fields known by inclusive bit range 410 411 static int fmask(juint hi_bit, juint lo_bit) { 412 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); 413 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 414 } 415 416 // inverse of u_field 417 418 static int inv_u_field(int x, int hi_bit, int lo_bit) { 419 juint r = juint(x) >> lo_bit; 420 r &= fmask( hi_bit, lo_bit); 421 return int(r); 422 } 423 424 425 // signed version: extract from field and sign-extend 426 427 static int inv_s_field(int x, int hi_bit, int lo_bit) { 428 int sign_shift = 31 - hi_bit; 429 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); 430 } 431 432 // given a field that ranges from hi_bit to lo_bit (inclusive, 433 // LSB = 0), and an unsigned value for the field, 434 // shift it into the field 435 436 #ifdef ASSERT 437 static int u_field(int x, int hi_bit, int lo_bit) { 438 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, 439 "value out of range"); 440 int r = x << lo_bit; 441 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 442 return r; 443 } 444 #else 445 // make sure this is inlined as it will reduce code size significantly 446 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) 447 #endif 448 449 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } 450 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } 451 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } 452 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } 453 454 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } 455 456 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } 457 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } 458 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } 459 460 static int op( int x) { return u_field(x, 31, 30); } 461 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } 462 static int fcn( int x) { return u_field(x, 29, 25); } 463 static int op3( int x) { return u_field(x, 24, 19); } 464 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } 465 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } 466 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } 467 static int cond( int x) { return u_field(x, 28, 25); } 468 static int cond_mov( int x) { return u_field(x, 17, 14); } 469 static int rcond( RCondition x) { return u_field(x, 12, 10); } 470 static int op2( int x) { return u_field(x, 24, 22); } 471 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } 472 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } 473 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } 474 static int imm_asi( int x) { return u_field(x, 12, 5); } 475 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } 476 static int opf_low6( int w) { return u_field(w, 10, 5); } 477 static int opf_low5( int w) { return u_field(w, 9, 5); } 478 static int op5( int x) { return u_field(x, 8, 5); } 479 static int trapcc( CC cc) { return u_field(cc, 12, 11); } 480 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 481 static int opf( int x) { return u_field(x, 13, 5); } 482 483 static bool is_cbcond( int x ) { 484 return (VM_Version::has_cbcond() && (inv_cond(x) > rc_last) && 485 inv_op(x) == branch_op && inv_op2(x) == bpr_op2); 486 } 487 static bool is_cxb( int x ) { 488 assert(is_cbcond(x), "wrong instruction"); 489 return (x & (1<<21)) != 0; 490 } 491 static int cond_cbcond( int x) { return u_field((((x & 8)<<1) + 8 + (x & 7)), 29, 25); } 492 static int inv_cond_cbcond(int x) { 493 assert(is_cbcond(x), "wrong instruction"); 494 return inv_u_field(x, 27, 25) | (inv_u_field(x, 29, 29)<<3); 495 } 496 497 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } 498 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 499 500 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 501 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 502 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 503 static int fs3(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 13, 9); }; 504 505 // some float instructions use this encoding on the op3 field 506 static int alt_op3(int op, FloatRegisterImpl::Width w) { 507 int r; 508 switch(w) { 509 case FloatRegisterImpl::S: r = op + 0; break; 510 case FloatRegisterImpl::D: r = op + 3; break; 511 case FloatRegisterImpl::Q: r = op + 2; break; 512 default: ShouldNotReachHere(); break; 513 } 514 return op3(r); 515 } 516 517 518 // compute inverse of simm 519 static int inv_simm(int x, int nbits) { 520 return (int)(x << (32 - nbits)) >> (32 - nbits); 521 } 522 523 static int inv_simm13( int x ) { return inv_simm(x, 13); } 524 525 // signed immediate, in low bits, nbits long 526 static int simm(int x, int nbits) { 527 assert_signed_range(x, nbits); 528 return x & (( 1 << nbits ) - 1); 529 } 530 531 // compute inverse of wdisp16 532 static intptr_t inv_wdisp16(int x, intptr_t pos) { 533 int lo = x & (( 1 << 14 ) - 1); 534 int hi = (x >> 20) & 3; 535 if (hi >= 2) hi |= ~1; 536 return (((hi << 14) | lo) << 2) + pos; 537 } 538 539 // word offset, 14 bits at LSend, 2 bits at B21, B20 540 static int wdisp16(intptr_t x, intptr_t off) { 541 intptr_t xx = x - off; 542 assert_signed_word_disp_range(xx, 16); 543 int r = (xx >> 2) & ((1 << 14) - 1) 544 | ( ( (xx>>(2+14)) & 3 ) << 20 ); 545 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); 546 return r; 547 } 548 549 // compute inverse of wdisp10 550 static intptr_t inv_wdisp10(int x, intptr_t pos) { 551 assert(is_cbcond(x), "wrong instruction"); 552 int lo = inv_u_field(x, 12, 5); 553 int hi = (x >> 19) & 3; 554 if (hi >= 2) hi |= ~1; 555 return (((hi << 8) | lo) << 2) + pos; 556 } 557 558 // word offset for cbcond, 8 bits at [B12,B5], 2 bits at [B20,B19] 559 static int wdisp10(intptr_t x, intptr_t off) { 560 assert(VM_Version::has_cbcond(), "This CPU does not have CBCOND instruction"); 561 intptr_t xx = x - off; 562 assert_signed_word_disp_range(xx, 10); 563 int r = ( ( (xx >> 2 ) & ((1 << 8) - 1) ) << 5 ) 564 | ( ( (xx >> (2+8)) & 3 ) << 19 ); 565 // Have to fake cbcond instruction to pass assert in inv_wdisp10() 566 assert(inv_wdisp10((r | op(branch_op) | cond_cbcond(rc_last+1) | op2(bpr_op2)), off) == x, "inverse is not inverse"); 567 return r; 568 } 569 570 // word displacement in low-order nbits bits 571 572 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { 573 int pre_sign_extend = x & (( 1 << nbits ) - 1); 574 int r = pre_sign_extend >= ( 1 << (nbits-1) ) 575 ? pre_sign_extend | ~(( 1 << nbits ) - 1) 576 : pre_sign_extend; 577 return (r << 2) + pos; 578 } 579 580 static int wdisp( intptr_t x, intptr_t off, int nbits ) { 581 intptr_t xx = x - off; 582 assert_signed_word_disp_range(xx, nbits); 583 int r = (xx >> 2) & (( 1 << nbits ) - 1); 584 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); 585 return r; 586 } 587 588 589 // Extract the top 32 bits in a 64 bit word 590 static int32_t hi32( int64_t x ) { 591 int32_t r = int32_t( (uint64_t)x >> 32 ); 592 return r; 593 } 594 595 // given a sethi instruction, extract the constant, left-justified 596 static int inv_hi22( int x ) { 597 return x << 10; 598 } 599 600 // create an imm22 field, given a 32-bit left-justified constant 601 static int hi22( int x ) { 602 int r = int( juint(x) >> 10 ); 603 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); 604 return r; 605 } 606 607 // create a low10 __value__ (not a field) for a given a 32-bit constant 608 static int low10( int x ) { 609 return x & ((1 << 10) - 1); 610 } 611 612 // create a low12 __value__ (not a field) for a given a 32-bit constant 613 static int low12( int x ) { 614 return x & ((1 << 12) - 1); 615 } 616 617 // AES crypto instructions supported only on certain processors 618 static void aes_only() { assert( VM_Version::has_aes(), "This instruction only works on SPARC with AES instructions support"); } 619 620 // SHA crypto instructions supported only on certain processors 621 static void sha1_only() { assert( VM_Version::has_sha1(), "This instruction only works on SPARC with SHA1"); } 622 static void sha256_only() { assert( VM_Version::has_sha256(), "This instruction only works on SPARC with SHA256"); } 623 static void sha512_only() { assert( VM_Version::has_sha512(), "This instruction only works on SPARC with SHA512"); } 624 625 // CRC32C instruction supported only on certain processors 626 static void crc32c_only() { assert( VM_Version::has_crc32c(), "This instruction only works on SPARC with CRC32C"); } 627 628 // instruction only in VIS1 629 static void vis1_only() { assert( VM_Version::has_vis1(), "This instruction only works on SPARC with VIS1"); } 630 631 // instruction only in VIS2 632 static void vis2_only() { assert( VM_Version::has_vis2(), "This instruction only works on SPARC with VIS2"); } 633 634 // instruction only in VIS3 635 static void vis3_only() { assert( VM_Version::has_vis3(), "This instruction only works on SPARC with VIS3"); } 636 637 // instruction only in v9 638 static void v9_only() { } // do nothing 639 640 // instruction deprecated in v9 641 static void v9_dep() { } // do nothing for now 642 643 // v8 has no CC field 644 static void v8_no_cc(CC cc) { if (cc) v9_only(); } 645 646 protected: 647 // Simple delay-slot scheme: 648 // In order to check the programmer, the assembler keeps track of deley slots. 649 // It forbids CTIs in delay slots (conservative, but should be OK). 650 // Also, when putting an instruction into a delay slot, you must say 651 // asm->delayed()->add(...), in order to check that you don't omit 652 // delay-slot instructions. 653 // To implement this, we use a simple FSA 654 655 #ifdef ASSERT 656 #define CHECK_DELAY 657 #endif 658 #ifdef CHECK_DELAY 659 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; 660 #endif 661 662 public: 663 // Tells assembler next instruction must NOT be in delay slot. 664 // Use at start of multinstruction macros. 665 void assert_not_delayed() { 666 // This is a separate overloading to avoid creation of string constants 667 // in non-asserted code--with some compilers this pollutes the object code. 668 #ifdef CHECK_DELAY 669 assert_not_delayed("next instruction should not be a delay slot"); 670 #endif 671 } 672 void assert_not_delayed(const char* msg) { 673 #ifdef CHECK_DELAY 674 assert(delay_state == no_delay, msg); 675 #endif 676 } 677 678 protected: 679 // Insert a nop if the previous is cbcond 680 void insert_nop_after_cbcond() { 681 if (UseCBCond && cbcond_before()) { 682 nop(); 683 } 684 } 685 // Delay slot helpers 686 // cti is called when emitting control-transfer instruction, 687 // BEFORE doing the emitting. 688 // Only effective when assertion-checking is enabled. 689 void cti() { 690 // A cbcond instruction immediately followed by a CTI 691 // instruction introduces pipeline stalls, we need to avoid that. 692 no_cbcond_before(); 693 #ifdef CHECK_DELAY 694 assert_not_delayed("cti should not be in delay slot"); 695 #endif 696 } 697 698 // called when emitting cti with a delay slot, AFTER emitting 699 void has_delay_slot() { 700 #ifdef CHECK_DELAY 701 assert_not_delayed("just checking"); 702 delay_state = at_delay_slot; 703 #endif 704 } 705 706 // cbcond instruction should not be generated one after an other 707 bool cbcond_before() { 708 if (offset() == 0) return false; // it is first instruction 709 int x = *(int*)(intptr_t(pc()) - 4); // previous instruction 710 return is_cbcond(x); 711 } 712 713 void no_cbcond_before() { 714 assert(offset() == 0 || !cbcond_before(), "cbcond should not follow an other cbcond"); 715 } 716 public: 717 718 bool use_cbcond(Label& L) { 719 if (!UseCBCond || cbcond_before()) return false; 720 intptr_t x = intptr_t(target_distance(L)) - intptr_t(pc()); 721 assert( (x & 3) == 0, "not word aligned"); 722 return is_simm12(x); 723 } 724 725 // Tells assembler you know that next instruction is delayed 726 Assembler* delayed() { 727 #ifdef CHECK_DELAY 728 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); 729 delay_state = filling_delay_slot; 730 #endif 731 return this; 732 } 733 734 void flush() { 735 #ifdef CHECK_DELAY 736 assert ( delay_state == no_delay, "ending code with a delay slot"); 737 #endif 738 AbstractAssembler::flush(); 739 } 740 741 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 742 inline void emit_data(int x) { emit_int32(x); } 743 inline void emit_data(int, RelocationHolder const&); 744 inline void emit_data(int, relocInfo::relocType rtype); 745 // helper for above fcns 746 inline void check_delay(); 747 748 749 public: 750 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 751 752 // pp 135 (addc was addx in v8) 753 754 inline void add(Register s1, Register s2, Register d ); 755 inline void add(Register s1, int simm13a, Register d ); 756 757 void addcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 758 void addcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 759 void addc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } 760 void addc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 761 void addccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 762 void addccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 763 764 765 // 4-operand AES instructions 766 767 void aes_eround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_op5) | fs2(s2, FloatRegisterImpl::D) ); } 768 void aes_eround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_op5) | fs2(s2, FloatRegisterImpl::D) ); } 769 void aes_dround01( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_op5) | fs2(s2, FloatRegisterImpl::D) ); } 770 void aes_dround23( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_op5) | fs2(s2, FloatRegisterImpl::D) ); } 771 void aes_eround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 772 void aes_eround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_eround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 773 void aes_dround01_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround01_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 774 void aes_dround23_l( FloatRegister s1, FloatRegister s2, FloatRegister s3, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | fs3(s3, FloatRegisterImpl::D) | op5(aes_dround23_l_op5) | fs2(s2, FloatRegisterImpl::D) ); } 775 void aes_kexpand1( FloatRegister s1, FloatRegister s2, int imm5a, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes4_op3) | fs1(s1, FloatRegisterImpl::D) | u_field(imm5a, 13, 9) | op5(aes_kexpand1_op5) | fs2(s2, FloatRegisterImpl::D) ); } 776 777 778 // 3-operand AES instructions 779 780 void aes_kexpand0( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand0_opf) | fs2(s2, FloatRegisterImpl::D) ); } 781 void aes_kexpand2( FloatRegister s1, FloatRegister s2, FloatRegister d ) { aes_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(aes3_op3) | fs1(s1, FloatRegisterImpl::D) | opf(aes_kexpand2_opf) | fs2(s2, FloatRegisterImpl::D) ); } 782 783 // pp 136 784 785 inline void bpr(RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none); 786 inline void bpr(RCondition c, bool a, Predict p, Register s1, Label& L); 787 788 // compare and branch 789 inline void cbcond(Condition c, CC cc, Register s1, Register s2, Label& L); 790 inline void cbcond(Condition c, CC cc, Register s1, int simm5, Label& L); 791 792 protected: // use MacroAssembler::br instead 793 794 // pp 138 795 796 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 797 inline void fb( Condition c, bool a, Label& L ); 798 799 // pp 141 800 801 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 802 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); 803 804 // pp 144 805 806 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 807 inline void br( Condition c, bool a, Label& L ); 808 809 // pp 146 810 811 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 812 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); 813 814 // pp 149 815 816 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); 817 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); 818 819 inline void call( address d, RelocationHolder const& rspec ); 820 821 public: 822 823 // pp 150 824 825 // These instructions compare the contents of s2 with the contents of 826 // memory at address in s1. If the values are equal, the contents of memory 827 // at address s1 is swapped with the data in d. If the values are not equal, 828 // the the contents of memory at s1 is loaded into d, without the swap. 829 830 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 831 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 832 833 // pp 152 834 835 void udiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } 836 void udiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 837 void sdiv( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } 838 void sdiv( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 839 void udivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 840 void udivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 841 void sdivcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 842 void sdivcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 843 844 // pp 155 845 846 void done() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(0) | op3(done_op3) ); } 847 void retry() { v9_only(); cti(); emit_int32( op(arith_op) | fcn(1) | op3(retry_op3) ); } 848 849 // pp 156 850 851 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } 852 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } 853 854 // pp 157 855 856 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } 857 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { emit_int32( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } 858 859 // pp 159 860 861 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } 862 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } 863 864 // pp 160 865 866 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } 867 868 // pp 161 869 870 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, FloatRegisterImpl::D)); } 871 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, FloatRegisterImpl::S)); } 872 873 // pp 162 874 875 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } 876 877 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } 878 879 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } 880 881 // pp 163 882 883 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } 884 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } 885 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } 886 887 // FXORs/FXORd instructions 888 889 void fxor( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(flog3_op3) | fs1(s1, w) | opf(0x6E - w) | fs2(s2, w)); } 890 891 // pp 164 892 893 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_int32( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } 894 895 // pp 165 896 897 inline void flush( Register s1, Register s2 ); 898 inline void flush( Register s1, int simm13a); 899 900 // pp 167 901 902 void flushw() { v9_only(); emit_int32( op(arith_op) | op3(flushw_op3) ); } 903 904 // pp 168 905 906 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_int32( op(branch_op) | u_field(const22a, 21, 0) ); } 907 // v8 unimp == illtrap(0) 908 909 // pp 169 910 911 void impdep1( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } 912 void impdep2( int id1, int const19a ) { v9_only(); emit_int32( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } 913 914 // pp 170 915 916 void jmpl( Register s1, Register s2, Register d ); 917 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 918 919 // 171 920 921 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); 922 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); 923 924 925 inline void ldfsr( Register s1, Register s2 ); 926 inline void ldfsr( Register s1, int simm13a); 927 inline void ldxfsr( Register s1, Register s2 ); 928 inline void ldxfsr( Register s1, int simm13a); 929 930 // 173 931 932 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 933 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 934 935 // pp 175, lduw is ld on v8 936 937 inline void ldsb( Register s1, Register s2, Register d ); 938 inline void ldsb( Register s1, int simm13a, Register d); 939 inline void ldsh( Register s1, Register s2, Register d ); 940 inline void ldsh( Register s1, int simm13a, Register d); 941 inline void ldsw( Register s1, Register s2, Register d ); 942 inline void ldsw( Register s1, int simm13a, Register d); 943 inline void ldub( Register s1, Register s2, Register d ); 944 inline void ldub( Register s1, int simm13a, Register d); 945 inline void lduh( Register s1, Register s2, Register d ); 946 inline void lduh( Register s1, int simm13a, Register d); 947 inline void lduw( Register s1, Register s2, Register d ); 948 inline void lduw( Register s1, int simm13a, Register d); 949 inline void ldx( Register s1, Register s2, Register d ); 950 inline void ldx( Register s1, int simm13a, Register d); 951 inline void ldd( Register s1, Register s2, Register d ); 952 inline void ldd( Register s1, int simm13a, Register d); 953 954 // pp 177 955 956 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 957 void ldsba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 958 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 959 void ldsha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 960 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 961 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 962 void lduba( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 963 void lduba( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 964 void lduha( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 965 void lduha( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 966 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 967 void lduwa( Register s1, int simm13a, Register d ) { emit_int32( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 968 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 969 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 970 971 // pp 181 972 973 void and3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } 974 void and3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 975 void andcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 976 void andcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 977 void andn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } 978 void andn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 979 void andncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 980 void andncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 981 void or3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } 982 void or3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 983 void orcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 984 void orcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 985 void orn( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } 986 void orn( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 987 void orncc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 988 void orncc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 989 void xor3( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } 990 void xor3( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 991 void xorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 992 void xorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 993 void xnor( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } 994 void xnor( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 995 void xnorcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 996 void xnorcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 997 998 // pp 183 999 1000 void membar( Membar_mask_bits const7a ) { v9_only(); emit_int32( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } 1001 1002 // pp 185 1003 1004 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } 1005 1006 // pp 189 1007 1008 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } 1009 1010 // pp 191 1011 1012 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } 1013 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } 1014 1015 // pp 195 1016 1017 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } 1018 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } 1019 1020 // pp 196 1021 1022 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } 1023 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1024 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } 1025 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1026 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } 1027 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1028 1029 // pp 197 1030 1031 void umul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } 1032 void umul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1033 void smul( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } 1034 void smul( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1035 void umulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1036 void umulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1037 void smulcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1038 void smulcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1039 1040 // pp 201 1041 1042 void nop() { emit_int32( op(branch_op) | op2(sethi_op2) ); } 1043 1044 void sw_count() { emit_int32( op(branch_op) | op2(sethi_op2) | 0x3f0 ); } 1045 1046 // pp 202 1047 1048 void popc( Register s, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } 1049 void popc( int simm13a, Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } 1050 1051 // pp 203 1052 1053 void prefetch( Register s1, Register s2, PrefetchFcn f) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | rs2(s2) ); } 1054 void prefetch( Register s1, int simm13a, PrefetchFcn f) { v9_only(); emit_data( op(ldst_op) | fcn(f) | op3(prefetch_op3) | rs1(s1) | immed(true) | simm(simm13a, 13)); } 1055 1056 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1057 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_int32( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1058 1059 // pp 208 1060 1061 // not implementing read privileged register 1062 1063 inline void rdy( Register d) { v9_dep(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } 1064 inline void rdccr( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } 1065 inline void rdasi( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } 1066 inline void rdtick( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! 1067 inline void rdpc( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } 1068 inline void rdfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } 1069 1070 // pp 213 1071 1072 inline void rett( Register s1, Register s2); 1073 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); 1074 1075 // pp 214 1076 1077 void save( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } 1078 void save( Register s1, int simm13a, Register d ) { 1079 // make sure frame is at least large enough for the register save area 1080 assert(-simm13a >= 16 * wordSize, "frame too small"); 1081 emit_int32( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); 1082 } 1083 1084 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } 1085 void restore( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1086 1087 // pp 216 1088 1089 void saved() { v9_only(); emit_int32( op(arith_op) | fcn(0) | op3(saved_op3)); } 1090 void restored() { v9_only(); emit_int32( op(arith_op) | fcn(1) | op3(saved_op3)); } 1091 1092 // pp 217 1093 1094 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 1095 // pp 218 1096 1097 void sll( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1098 void sll( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1099 void srl( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1100 void srl( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1101 void sra( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1102 void sra( Register s1, int imm5a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1103 1104 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1105 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1106 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1107 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1108 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1109 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_int32( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1110 1111 // pp 220 1112 1113 void sir( int simm13a ) { emit_int32( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } 1114 1115 // pp 221 1116 1117 void stbar() { emit_int32( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } 1118 1119 // pp 222 1120 1121 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); 1122 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); 1123 1124 inline void stfsr( Register s1, Register s2 ); 1125 inline void stfsr( Register s1, int simm13a); 1126 inline void stxfsr( Register s1, Register s2 ); 1127 inline void stxfsr( Register s1, int simm13a); 1128 1129 // pp 224 1130 1131 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1132 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1133 1134 // p 226 1135 1136 inline void stb( Register d, Register s1, Register s2 ); 1137 inline void stb( Register d, Register s1, int simm13a); 1138 inline void sth( Register d, Register s1, Register s2 ); 1139 inline void sth( Register d, Register s1, int simm13a); 1140 inline void stw( Register d, Register s1, Register s2 ); 1141 inline void stw( Register d, Register s1, int simm13a); 1142 inline void stx( Register d, Register s1, Register s2 ); 1143 inline void stx( Register d, Register s1, int simm13a); 1144 inline void std( Register d, Register s1, Register s2 ); 1145 inline void std( Register d, Register s1, int simm13a); 1146 1147 // pp 177 1148 1149 void stba( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1150 void stba( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1151 void stha( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1152 void stha( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1153 void stwa( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1154 void stwa( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1155 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1156 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_int32( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1157 void stda( Register d, Register s1, Register s2, int ia ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1158 void stda( Register d, Register s1, int simm13a ) { emit_int32( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1159 1160 // pp 230 1161 1162 void sub( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } 1163 void sub( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1164 1165 void subcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } 1166 void subcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1167 void subc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } 1168 void subc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1169 void subccc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1170 void subccc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1171 1172 // pp 231 1173 1174 inline void swap( Register s1, Register s2, Register d ); 1175 inline void swap( Register s1, int simm13a, Register d); 1176 1177 // pp 232 1178 1179 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1180 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_int32( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1181 1182 // pp 234, note op in book is wrong, see pp 268 1183 1184 void taddcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } 1185 void taddcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1186 1187 // pp 235 1188 1189 void tsubcc( Register s1, Register s2, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } 1190 void tsubcc( Register s1, int simm13a, Register d ) { emit_int32( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1191 1192 // pp 237 1193 1194 void trap( Condition c, CC cc, Register s1, Register s2 ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } 1195 void trap( Condition c, CC cc, Register s1, int trapa ) { emit_int32( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } 1196 // simple uncond. trap 1197 void trap( int trapa ) { trap( always, icc, G0, trapa ); } 1198 1199 // pp 239 omit write priv register for now 1200 1201 inline void wry( Register d) { v9_dep(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } 1202 inline void wrccr(Register s) { v9_only(); emit_int32( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } 1203 inline void wrccr(Register s, int simm13a) { v9_only(); emit_int32( op(arith_op) | 1204 rs1(s) | 1205 op3(wrreg_op3) | 1206 u_field(2, 29, 25) | 1207 immed(true) | 1208 simm(simm13a, 13)); } 1209 inline void wrasi(Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } 1210 // wrasi(d, imm) stores (d xor imm) to asi 1211 inline void wrasi(Register d, int simm13a) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | 1212 u_field(3, 29, 25) | immed(true) | simm(simm13a, 13)); } 1213 inline void wrfprs( Register d) { v9_only(); emit_int32( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } 1214 1215 // VIS1 instructions 1216 1217 void alignaddr( Register s1, Register s2, Register d ) { vis1_only(); emit_int32( op(arith_op) | rd(d) | op3(alignaddr_op3) | rs1(s1) | opf(alignaddr_opf) | rs2(s2)); } 1218 1219 void faligndata( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(faligndata_op3) | fs1(s1, FloatRegisterImpl::D) | opf(faligndata_opf) | fs2(s2, FloatRegisterImpl::D)); } 1220 1221 void fzero( FloatRegisterImpl::Width w, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fzero_op3) | opf(0x62 - w)); } 1222 1223 void fsrc2( FloatRegisterImpl::Width w, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fsrc_op3) | opf(0x7A - w) | fs2(s2, w)); } 1224 1225 void fnot1( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, w) | op3(fnot_op3) | fs1(s1, w) | opf(0x6C - w)); } 1226 1227 void fpmerge( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis1_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(0x36) | fs1(s1, FloatRegisterImpl::S) | opf(0x4b) | fs2(s2, FloatRegisterImpl::S)); } 1228 1229 void stpartialf( Register s1, Register s2, FloatRegister d, int ia = -1 ) { vis1_only(); emit_int32( op(ldst_op) | fd(d, FloatRegisterImpl::D) | op3(stpartialf_op3) | rs1(s1) | imm_asi(ia) | rs2(s2)); } 1230 1231 // VIS2 instructions 1232 1233 void edge8n( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(edge_op3) | rs1(s1) | opf(edge8n_opf) | rs2(s2)); } 1234 1235 void bmask( Register s1, Register s2, Register d ) { vis2_only(); emit_int32( op(arith_op) | rd(d) | op3(bmask_op3) | rs1(s1) | opf(bmask_opf) | rs2(s2)); } 1236 void bshuffle( FloatRegister s1, FloatRegister s2, FloatRegister d ) { vis2_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(bshuffle_op3) | fs1(s1, FloatRegisterImpl::D) | opf(bshuffle_opf) | fs2(s2, FloatRegisterImpl::D)); } 1237 1238 // VIS3 instructions 1239 1240 void movstosw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstosw_opf) | fs2(s, FloatRegisterImpl::S)); } 1241 void movstouw( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mstouw_opf) | fs2(s, FloatRegisterImpl::S)); } 1242 void movdtox( FloatRegister s, Register d ) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(mftoi_op3) | opf(mdtox_opf) | fs2(s, FloatRegisterImpl::D)); } 1243 1244 void movwtos( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::S) | op3(mftoi_op3) | opf(mwtos_opf) | rs2(s)); } 1245 void movxtod( Register s, FloatRegister d ) { vis3_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(mftoi_op3) | opf(mxtod_opf) | rs2(s)); } 1246 1247 void xmulx(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulx_opf) | rs2(s2)); } 1248 void xmulxhi(Register s1, Register s2, Register d) { vis3_only(); emit_int32( op(arith_op) | rd(d) | op3(xmulx_op3) | rs1(s1) | opf(xmulxhi_opf) | rs2(s2)); } 1249 1250 // Crypto SHA instructions 1251 1252 void sha1() { sha1_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha1_opf)); } 1253 void sha256() { sha256_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha256_opf)); } 1254 void sha512() { sha512_only(); emit_int32( op(arith_op) | op3(sha_op3) | opf(sha512_opf)); } 1255 1256 // CRC32C instruction 1257 1258 void crc32c( FloatRegister s1, FloatRegister s2, FloatRegister d ) { crc32c_only(); emit_int32( op(arith_op) | fd(d, FloatRegisterImpl::D) | op3(crc32c_op3) | fs1(s1, FloatRegisterImpl::D) | opf(crc32c_opf) | fs2(s2, FloatRegisterImpl::D)); } 1259 1260 // Creation 1261 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 1262 #ifdef CHECK_DELAY 1263 delay_state = no_delay; 1264 #endif 1265 } 1266 }; 1267 1268 #endif // CPU_SPARC_VM_ASSEMBLER_SPARC_HPP