1 /* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef SHARE_VM_OPTO_MACHNODE_HPP 26 #define SHARE_VM_OPTO_MACHNODE_HPP 27 28 #include "opto/callnode.hpp" 29 #include "opto/matcher.hpp" 30 #include "opto/multnode.hpp" 31 #include "opto/node.hpp" 32 #include "opto/regmask.hpp" 33 34 class BiasedLockingCounters; 35 class BufferBlob; 36 class CodeBuffer; 37 class JVMState; 38 class MachCallDynamicJavaNode; 39 class MachCallJavaNode; 40 class MachCallLeafNode; 41 class MachCallNode; 42 class MachCallRuntimeNode; 43 class MachCallStaticJavaNode; 44 class MachEpilogNode; 45 class MachIfNode; 46 class MachNullCheckNode; 47 class MachOper; 48 class MachProjNode; 49 class MachPrologNode; 50 class MachReturnNode; 51 class MachSafePointNode; 52 class MachSpillCopyNode; 53 class Matcher; 54 class PhaseRegAlloc; 55 class RegMask; 56 class RTMLockingCounters; 57 class State; 58 59 //---------------------------MachOper------------------------------------------ 60 class MachOper : public ResourceObj { 61 public: 62 // Allocate right next to the MachNodes in the same arena 63 void *operator new(size_t x) throw() { 64 Compile* C = Compile::current(); 65 return C->node_arena()->Amalloc_D(x); 66 } 67 68 // Opcode 69 virtual uint opcode() const = 0; 70 71 // Number of input edges. 72 // Generally at least 1 73 virtual uint num_edges() const { return 1; } 74 // Array of Register masks 75 virtual const RegMask *in_RegMask(int index) const; 76 77 // Methods to output the encoding of the operand 78 79 // Negate conditional branches. Error for non-branch Nodes 80 virtual void negate(); 81 82 // Return the value requested 83 // result register lookup, corresponding to int_format 84 virtual int reg(PhaseRegAlloc *ra_, const Node *node) const; 85 // input register lookup, corresponding to ext_format 86 virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const; 87 88 // helpers for MacroAssembler generation from ADLC 89 Register as_Register(PhaseRegAlloc *ra_, const Node *node) const { 90 return ::as_Register(reg(ra_, node)); 91 } 92 Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const { 93 return ::as_Register(reg(ra_, node, idx)); 94 } 95 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const { 96 return ::as_FloatRegister(reg(ra_, node)); 97 } 98 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 99 return ::as_FloatRegister(reg(ra_, node, idx)); 100 } 101 102 #if defined(IA32) || defined(AMD64) 103 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const { 104 return ::as_XMMRegister(reg(ra_, node)); 105 } 106 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 107 return ::as_XMMRegister(reg(ra_, node, idx)); 108 } 109 #endif 110 // CondRegister reg converter 111 #if defined(PPC64) 112 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const { 113 return ::as_ConditionRegister(reg(ra_, node)); 114 } 115 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const { 116 return ::as_ConditionRegister(reg(ra_, node, idx)); 117 } 118 #endif 119 120 virtual intptr_t constant() const; 121 virtual relocInfo::relocType constant_reloc() const; 122 virtual jdouble constantD() const; 123 virtual jfloat constantF() const; 124 virtual jlong constantL() const; 125 virtual TypeOopPtr *oop() const; 126 virtual int ccode() const; 127 // A zero, default, indicates this value is not needed. 128 // May need to lookup the base register, as done in int_ and ext_format 129 virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const; 130 virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const; 131 virtual int scale() const; 132 // Parameters needed to support MEMORY_INTERFACE access to stackSlot 133 virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const; 134 // Check for PC-Relative displacement 135 virtual relocInfo::relocType disp_reloc() const; 136 virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot 137 virtual int base_position() const; // base edge position, or -1 138 virtual int index_position() const; // index edge position, or -1 139 140 // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP 141 // Only returns non-null value for i486.ad's indOffset32X 142 virtual const TypePtr *disp_as_type() const { return NULL; } 143 144 // Return the label 145 virtual Label *label() const; 146 147 // Return the method's address 148 virtual intptr_t method() const; 149 150 // Hash and compare over operands are currently identical 151 virtual uint hash() const; 152 virtual uint cmp( const MachOper &oper ) const; 153 154 // Virtual clone, since I do not know how big the MachOper is. 155 virtual MachOper *clone() const = 0; 156 157 // Return ideal Type from simple operands. Fail for complex operands. 158 virtual const Type *type() const; 159 160 // Set an integer offset if we have one, or error otherwise 161 virtual void set_con( jint c0 ) { ShouldNotReachHere(); } 162 163 #ifndef PRODUCT 164 // Return name of operand 165 virtual const char *Name() const { return "???";} 166 167 // Methods to output the text version of the operand 168 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0; 169 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0; 170 171 virtual void dump_spec(outputStream *st) const; // Print per-operand info 172 173 // Check whether o is a valid oper. 174 static bool notAnOper(const MachOper *o) { 175 if (o == NULL) return true; 176 if (((intptr_t)o & 1) != 0) return true; 177 if (*(address*)o == badAddress) return true; // kill by Node::destruct 178 return false; 179 } 180 #endif // !PRODUCT 181 }; 182 183 //------------------------------MachNode--------------------------------------- 184 // Base type for all machine specific nodes. All node classes generated by the 185 // ADLC inherit from this class. 186 class MachNode : public Node { 187 public: 188 MachNode() : Node((uint)0), _num_opnds(0), _opnds(NULL) { 189 init_class_id(Class_Mach); 190 } 191 // Required boilerplate 192 virtual uint size_of() const { return sizeof(MachNode); } 193 virtual int Opcode() const; // Always equal to MachNode 194 virtual uint rule() const = 0; // Machine-specific opcode 195 // Number of inputs which come before the first operand. 196 // Generally at least 1, to skip the Control input 197 virtual uint oper_input_base() const { return 1; } 198 // Position of constant base node in node's inputs. -1 if 199 // no constant base node input. 200 virtual uint mach_constant_base_node_input() const { return (uint)-1; } 201 202 // Copy inputs and operands to new node of instruction. 203 // Called from cisc_version() and short_branch_version(). 204 // !!!! The method's body is defined in ad_<arch>.cpp file. 205 void fill_new_machnode(MachNode *n) const; 206 207 // Return an equivalent instruction using memory for cisc_operand position 208 virtual MachNode *cisc_version(int offset); 209 // Modify this instruction's register mask to use stack version for cisc_operand 210 virtual void use_cisc_RegMask(); 211 212 // Support for short branches 213 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; } 214 215 // Avoid back to back some instructions on some CPUs. 216 enum AvoidBackToBackFlag { AVOID_NONE = 0, 217 AVOID_BEFORE = Flag_avoid_back_to_back_before, 218 AVOID_AFTER = Flag_avoid_back_to_back_after, 219 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER }; 220 221 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const { 222 return (flags() & flag_value) == flag_value; 223 } 224 225 // instruction implemented with a call 226 bool has_call() const { return (flags() & Flag_has_call) != 0; } 227 228 // First index in _in[] corresponding to operand, or -1 if there is none 229 int operand_index(uint operand) const; 230 int operand_index(const MachOper *oper) const; 231 232 // Register class input is expected in 233 virtual const RegMask &in_RegMask(uint) const; 234 235 // cisc-spillable instructions redefine for use by in_RegMask 236 virtual const RegMask *cisc_RegMask() const { return NULL; } 237 238 // If this instruction is a 2-address instruction, then return the 239 // index of the input which must match the output. Not nessecary 240 // for instructions which bind the input and output register to the 241 // same singleton regiser (e.g., Intel IDIV which binds AX to be 242 // both an input and an output). It is nessecary when the input and 243 // output have choices - but they must use the same choice. 244 virtual uint two_adr( ) const { return 0; } 245 246 // Array of complex operand pointers. Each corresponds to zero or 247 // more leafs. Must be set by MachNode constructor to point to an 248 // internal array of MachOpers. The MachOper array is sized by 249 // specific MachNodes described in the ADL. 250 uint _num_opnds; 251 MachOper **_opnds; 252 uint num_opnds() const { return _num_opnds; } 253 254 // Emit bytes into cbuf 255 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 256 // Expand node after register allocation. 257 // Node is replaced by several nodes in the postalloc expand phase. 258 // Corresponding methods are generated for nodes if they specify 259 // postalloc_expand. See block.cpp for more documentation. 260 virtual bool requires_postalloc_expand() const { return false; } 261 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_); 262 // Size of instruction in bytes 263 virtual uint size(PhaseRegAlloc *ra_) const; 264 // Helper function that computes size by emitting code 265 virtual uint emit_size(PhaseRegAlloc *ra_) const; 266 267 // Return the alignment required (in units of relocInfo::addr_unit()) 268 // for this instruction (must be a power of 2) 269 virtual int alignment_required() const { return 1; } 270 271 // Return the padding (in bytes) to be emitted before this 272 // instruction to properly align it. 273 virtual int compute_padding(int current_offset) const { return 0; } 274 275 // Return number of relocatable values contained in this instruction 276 virtual int reloc() const { return 0; } 277 278 // Return number of words used for double constants in this instruction 279 virtual int ins_num_consts() const { return 0; } 280 281 // Hash and compare over operands. Used to do GVN on machine Nodes. 282 virtual uint hash() const; 283 virtual uint cmp( const Node &n ) const; 284 285 // Expand method for MachNode, replaces nodes representing pseudo 286 // instructions with a set of nodes which represent real machine 287 // instructions and compute the same value. 288 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; } 289 290 // Bottom_type call; value comes from operand0 291 virtual const class Type *bottom_type() const { return _opnds[0]->type(); } 292 virtual uint ideal_reg() const { const Type *t = _opnds[0]->type(); return t == TypeInt::CC ? Op_RegFlags : t->ideal_reg(); } 293 294 // If this is a memory op, return the base pointer and fixed offset. 295 // If there are no such, return NULL. If there are multiple addresses 296 // or the address is indeterminate (rare cases) then return (Node*)-1, 297 // which serves as node bottom. 298 // If the offset is not statically determined, set it to Type::OffsetBot. 299 // This method is free to ignore stack slots if that helps. 300 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1) 301 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible 302 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const; 303 304 // Helper for get_base_and_disp: find the base and index input nodes. 305 // Returns the MachOper as determined by memory_operand(), for use, if 306 // needed by the caller. If (MachOper *)-1 is returned, base and index 307 // are set to NodeSentinel. If (MachOper *) NULL is returned, base and 308 // index are set to NULL. 309 const MachOper* memory_inputs(Node* &base, Node* &index) const; 310 311 // Helper for memory_inputs: Which operand carries the necessary info? 312 // By default, returns NULL, which means there is no such operand. 313 // If it returns (MachOper*)-1, this means there are multiple memories. 314 virtual const MachOper* memory_operand() const { return NULL; } 315 316 // Call "get_base_and_disp" to decide which category of memory is used here. 317 virtual const class TypePtr *adr_type() const; 318 319 // Apply peephole rule(s) to this instruction 320 virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted); 321 322 // Top-level ideal Opcode matched 323 virtual int ideal_Opcode() const { return Op_Node; } 324 325 // Adds the label for the case 326 virtual void add_case_label( int switch_val, Label* blockLabel); 327 328 // Set the absolute address for methods 329 virtual void method_set( intptr_t addr ); 330 331 // Should we clone rather than spill this instruction? 332 bool rematerialize() const; 333 334 // Get the pipeline info 335 static const Pipeline *pipeline_class(); 336 virtual const Pipeline *pipeline() const; 337 338 // Returns true if this node is a check that can be implemented with a trap. 339 virtual bool is_TrapBasedCheckNode() const { return false; } 340 341 #ifndef PRODUCT 342 virtual const char *Name() const = 0; // Machine-specific name 343 virtual void dump_spec(outputStream *st) const; // Print per-node info 344 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual 345 #endif 346 }; 347 348 //------------------------------MachIdealNode---------------------------- 349 // Machine specific versions of nodes that must be defined by user. 350 // These are not converted by matcher from ideal nodes to machine nodes 351 // but are inserted into the code by the compiler. 352 class MachIdealNode : public MachNode { 353 public: 354 MachIdealNode( ) {} 355 356 // Define the following defaults for non-matched machine nodes 357 virtual uint oper_input_base() const { return 0; } 358 virtual uint rule() const { return 9999999; } 359 virtual const class Type *bottom_type() const { return _opnds == NULL ? Type::CONTROL : MachNode::bottom_type(); } 360 }; 361 362 //------------------------------MachTypeNode---------------------------- 363 // Machine Nodes that need to retain a known Type. 364 class MachTypeNode : public MachNode { 365 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 366 public: 367 MachTypeNode( ) {} 368 const Type *_bottom_type; 369 370 virtual const class Type *bottom_type() const { return _bottom_type; } 371 #ifndef PRODUCT 372 virtual void dump_spec(outputStream *st) const; 373 #endif 374 }; 375 376 //------------------------------MachBreakpointNode---------------------------- 377 // Machine breakpoint or interrupt Node 378 class MachBreakpointNode : public MachIdealNode { 379 public: 380 MachBreakpointNode( ) {} 381 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 382 virtual uint size(PhaseRegAlloc *ra_) const; 383 384 #ifndef PRODUCT 385 virtual const char *Name() const { return "Breakpoint"; } 386 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 387 #endif 388 }; 389 390 //------------------------------MachConstantBaseNode-------------------------- 391 // Machine node that represents the base address of the constant table. 392 class MachConstantBaseNode : public MachIdealNode { 393 public: 394 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask(). 395 396 public: 397 MachConstantBaseNode() : MachIdealNode() { 398 init_class_id(Class_MachConstantBase); 399 } 400 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; } 401 virtual uint ideal_reg() const { return Op_RegP; } 402 virtual uint oper_input_base() const { return 1; } 403 404 virtual bool requires_postalloc_expand() const; 405 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_); 406 407 virtual void emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const; 408 virtual uint size(PhaseRegAlloc* ra_) const; 409 virtual bool pinned() const { return UseRDPCForConstantTableBase; } 410 411 static const RegMask& static_out_RegMask() { return _out_RegMask; } 412 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); } 413 414 #ifndef PRODUCT 415 virtual const char* Name() const { return "MachConstantBaseNode"; } 416 virtual void format(PhaseRegAlloc*, outputStream* st) const; 417 #endif 418 }; 419 420 //------------------------------MachConstantNode------------------------------- 421 // Machine node that holds a constant which is stored in the constant table. 422 class MachConstantNode : public MachTypeNode { 423 protected: 424 Compile::Constant _constant; // This node's constant. 425 426 public: 427 MachConstantNode() : MachTypeNode() { 428 init_class_id(Class_MachConstant); 429 } 430 431 virtual void eval_constant(Compile* C) { 432 #ifdef ASSERT 433 tty->print("missing MachConstantNode eval_constant function: "); 434 dump(); 435 #endif 436 ShouldNotCallThis(); 437 } 438 439 virtual const RegMask &in_RegMask(uint idx) const { 440 if (idx == mach_constant_base_node_input()) 441 return MachConstantBaseNode::static_out_RegMask(); 442 return MachNode::in_RegMask(idx); 443 } 444 445 // Input edge of MachConstantBaseNode. 446 virtual uint mach_constant_base_node_input() const { return req() - 1; } 447 448 int constant_offset(); 449 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); } 450 // Unchecked version to avoid assertions in debug output. 451 int constant_offset_unchecked() const; 452 }; 453 454 //------------------------------MachUEPNode----------------------------------- 455 // Machine Unvalidated Entry Point Node 456 class MachUEPNode : public MachIdealNode { 457 public: 458 MachUEPNode( ) {} 459 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 460 virtual uint size(PhaseRegAlloc *ra_) const; 461 462 #ifndef PRODUCT 463 virtual const char *Name() const { return "Unvalidated-Entry-Point"; } 464 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 465 #endif 466 }; 467 468 //------------------------------MachPrologNode-------------------------------- 469 // Machine function Prolog Node 470 class MachPrologNode : public MachIdealNode { 471 public: 472 MachPrologNode( ) {} 473 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 474 virtual uint size(PhaseRegAlloc *ra_) const; 475 virtual int reloc() const; 476 477 #ifndef PRODUCT 478 virtual const char *Name() const { return "Prolog"; } 479 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 480 #endif 481 }; 482 483 //------------------------------MachEpilogNode-------------------------------- 484 // Machine function Epilog Node 485 class MachEpilogNode : public MachIdealNode { 486 public: 487 MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {} 488 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 489 virtual uint size(PhaseRegAlloc *ra_) const; 490 virtual int reloc() const; 491 virtual const Pipeline *pipeline() const; 492 493 private: 494 bool _do_polling; 495 496 public: 497 bool do_polling() const { return _do_polling; } 498 499 // Offset of safepoint from the beginning of the node 500 int safepoint_offset() const; 501 502 #ifndef PRODUCT 503 virtual const char *Name() const { return "Epilog"; } 504 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 505 #endif 506 }; 507 508 //------------------------------MachNopNode----------------------------------- 509 // Machine function Nop Node 510 class MachNopNode : public MachIdealNode { 511 private: 512 int _count; 513 public: 514 MachNopNode( ) : _count(1) {} 515 MachNopNode( int count ) : _count(count) {} 516 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 517 virtual uint size(PhaseRegAlloc *ra_) const; 518 519 virtual const class Type *bottom_type() const { return Type::CONTROL; } 520 521 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp 522 virtual const Pipeline *pipeline() const; 523 #ifndef PRODUCT 524 virtual const char *Name() const { return "Nop"; } 525 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 526 virtual void dump_spec(outputStream *st) const { } // No per-operand info 527 #endif 528 }; 529 530 //------------------------------MachSpillCopyNode------------------------------ 531 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any 532 // location (stack or register). 533 class MachSpillCopyNode : public MachIdealNode { 534 public: 535 enum SpillType { 536 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails 537 PhiInput, // Inserted when coalescing of a phi node and its input fails 538 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks 539 LoopPhiInput, // Pre-split compares of loop-phis 540 Definition, // An lrg marked as spilled will be spilled to memory right after its definition, 541 // if in high pressure region or the lrg is bound 542 RegToReg, // A register to register move 543 RegToMem, // A register to memory move 544 MemToReg, // A memory to register move 545 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if 546 // the phi and its input resides at different locations (i.e. reg or mem) 547 BasePointerToMem, // Spill base pointer to memory at safepoint 548 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be 549 // stretched beyond a new definition point, therefore we split out new copies instead 550 CallUse, // Spill use at a call 551 Bound // An lrg marked as spill that is bound and needs to be spilled at a use 552 }; 553 private: 554 const RegMask *_in; // RegMask for input 555 const RegMask *_out; // RegMask for output 556 const Type *_type; 557 const SpillType _spill_type; 558 public: 559 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) : 560 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) { 561 init_class_id(Class_MachSpillCopy); 562 init_flags(Flag_is_Copy); 563 add_req(NULL); 564 add_req(n); 565 } 566 virtual uint size_of() const { return sizeof(*this); } 567 void set_out_RegMask(const RegMask &out) { _out = &out; } 568 void set_in_RegMask(const RegMask &in) { _in = ∈ } 569 virtual const RegMask &out_RegMask() const { return *_out; } 570 virtual const RegMask &in_RegMask(uint) const { return *_in; } 571 virtual const class Type *bottom_type() const { return _type; } 572 virtual uint ideal_reg() const { return _type->ideal_reg(); } 573 virtual uint oper_input_base() const { return 1; } 574 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const; 575 576 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 577 virtual uint size(PhaseRegAlloc *ra_) const; 578 579 580 #ifndef PRODUCT 581 static const char *spill_type(SpillType st) { 582 switch (st) { 583 case TwoAddress: 584 return "TwoAddressSpillCopy"; 585 case PhiInput: 586 return "PhiInputSpillCopy"; 587 case DebugUse: 588 return "DebugUseSpillCopy"; 589 case LoopPhiInput: 590 return "LoopPhiInputSpillCopy"; 591 case Definition: 592 return "DefinitionSpillCopy"; 593 case RegToReg: 594 return "RegToRegSpillCopy"; 595 case RegToMem: 596 return "RegToMemSpillCopy"; 597 case MemToReg: 598 return "MemToRegSpillCopy"; 599 case PhiLocationDifferToInputLocation: 600 return "PhiLocationDifferToInputLocationSpillCopy"; 601 case BasePointerToMem: 602 return "BasePointerToMemSpillCopy"; 603 case InputToRematerialization: 604 return "InputToRematerializationSpillCopy"; 605 case CallUse: 606 return "CallUseSpillCopy"; 607 case Bound: 608 return "BoundSpillCopy"; 609 default: 610 assert(false, "Must have valid spill type"); 611 return "MachSpillCopy"; 612 } 613 } 614 615 virtual const char *Name() const { 616 return spill_type(_spill_type); 617 } 618 619 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 620 #endif 621 }; 622 623 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values, 624 // however it doesn't have a control input and is more like a MergeMem. 625 // It is inserted after the register allocation is done to ensure that nodes use single 626 // definition of a multidef lrg in a block. 627 class MachMergeNode : public MachIdealNode { 628 public: 629 MachMergeNode(Node *n1) { 630 init_class_id(Class_MachMerge); 631 add_req(NULL); 632 add_req(n1); 633 } 634 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); } 635 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); } 636 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); } 637 virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); } 638 virtual uint oper_input_base() const { return 1; } 639 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { } 640 virtual uint size(PhaseRegAlloc *ra_) const { return 0; } 641 #ifndef PRODUCT 642 virtual const char *Name() const { return "MachMerge"; } 643 #endif 644 }; 645 646 //------------------------------MachBranchNode-------------------------------- 647 // Abstract machine branch Node 648 class MachBranchNode : public MachIdealNode { 649 public: 650 MachBranchNode() : MachIdealNode() { 651 init_class_id(Class_MachBranch); 652 } 653 virtual void label_set(Label* label, uint block_num) = 0; 654 virtual void save_label(Label** label, uint* block_num) = 0; 655 656 // Support for short branches 657 virtual MachNode *short_branch_version() { return NULL; } 658 659 virtual bool pinned() const { return true; }; 660 }; 661 662 //------------------------------MachNullChkNode-------------------------------- 663 // Machine-dependent null-pointer-check Node. Points a real MachNode that is 664 // also some kind of memory op. Turns the indicated MachNode into a 665 // conditional branch with good latency on the ptr-not-null path and awful 666 // latency on the pointer-is-null path. 667 668 class MachNullCheckNode : public MachBranchNode { 669 public: 670 const uint _vidx; // Index of memop being tested 671 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) { 672 init_class_id(Class_MachNullCheck); 673 add_req(ctrl); 674 add_req(memop); 675 } 676 virtual uint size_of() const { return sizeof(*this); } 677 678 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const; 679 virtual void label_set(Label* label, uint block_num); 680 virtual void save_label(Label** label, uint* block_num); 681 virtual void negate() { } 682 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; } 683 virtual uint ideal_reg() const { return NotAMachineReg; } 684 virtual const RegMask &in_RegMask(uint) const; 685 virtual const RegMask &out_RegMask() const { return RegMask::Empty; } 686 #ifndef PRODUCT 687 virtual const char *Name() const { return "NullCheck"; } 688 virtual void format( PhaseRegAlloc *, outputStream *st ) const; 689 #endif 690 }; 691 692 //------------------------------MachProjNode---------------------------------- 693 // Machine-dependent Ideal projections (how is that for an oxymoron). Really 694 // just MachNodes made by the Ideal world that replicate simple projections 695 // but with machine-dependent input & output register masks. Generally 696 // produced as part of calling conventions. Normally I make MachNodes as part 697 // of the Matcher process, but the Matcher is ill suited to issues involving 698 // frame handling, so frame handling is all done in the Ideal world with 699 // occasional callbacks to the machine model for important info. 700 class MachProjNode : public ProjNode { 701 public: 702 MachProjNode( Node *multi, uint con, const RegMask &out, uint ideal_reg ) : ProjNode(multi,con), _rout(out), _ideal_reg(ideal_reg) { 703 init_class_id(Class_MachProj); 704 } 705 RegMask _rout; 706 const uint _ideal_reg; 707 enum projType { 708 unmatched_proj = 0, // Projs for Control, I/O, memory not matched 709 fat_proj = 999 // Projs killing many regs, defined by _rout 710 }; 711 virtual int Opcode() const; 712 virtual const Type *bottom_type() const; 713 virtual const TypePtr *adr_type() const; 714 virtual const RegMask &in_RegMask(uint) const { return RegMask::Empty; } 715 virtual const RegMask &out_RegMask() const { return _rout; } 716 virtual uint ideal_reg() const { return _ideal_reg; } 717 // Need size_of() for virtual ProjNode::clone() 718 virtual uint size_of() const { return sizeof(MachProjNode); } 719 #ifndef PRODUCT 720 virtual void dump_spec(outputStream *st) const; 721 #endif 722 }; 723 724 //------------------------------MachIfNode------------------------------------- 725 // Machine-specific versions of IfNodes 726 class MachIfNode : public MachBranchNode { 727 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 728 public: 729 float _prob; // Probability branch goes either way 730 float _fcnt; // Frequency counter 731 MachIfNode() : MachBranchNode() { 732 init_class_id(Class_MachIf); 733 } 734 // Negate conditional branches. 735 virtual void negate() = 0; 736 #ifndef PRODUCT 737 virtual void dump_spec(outputStream *st) const; 738 #endif 739 }; 740 741 //------------------------------MachGotoNode----------------------------------- 742 // Machine-specific versions of GotoNodes 743 class MachGotoNode : public MachBranchNode { 744 public: 745 MachGotoNode() : MachBranchNode() { 746 init_class_id(Class_MachGoto); 747 } 748 }; 749 750 //------------------------------MachFastLockNode------------------------------------- 751 // Machine-specific versions of FastLockNodes 752 class MachFastLockNode : public MachNode { 753 virtual uint size_of() const { return sizeof(*this); } // Size is bigger 754 public: 755 BiasedLockingCounters* _counters; 756 RTMLockingCounters* _rtm_counters; // RTM lock counters for inflated locks 757 RTMLockingCounters* _stack_rtm_counters; // RTM lock counters for stack locks 758 MachFastLockNode() : MachNode() {} 759 }; 760 761 //------------------------------MachReturnNode-------------------------------- 762 // Machine-specific versions of subroutine returns 763 class MachReturnNode : public MachNode { 764 virtual uint size_of() const; // Size is bigger 765 public: 766 RegMask *_in_rms; // Input register masks, set during allocation 767 ReallocMark _nesting; // assertion check for reallocations 768 const TypePtr* _adr_type; // memory effects of call or return 769 MachReturnNode() : MachNode() { 770 init_class_id(Class_MachReturn); 771 _adr_type = TypePtr::BOTTOM; // the default: all of memory 772 } 773 774 void set_adr_type(const TypePtr* atp) { _adr_type = atp; } 775 776 virtual const RegMask &in_RegMask(uint) const; 777 virtual bool pinned() const { return true; }; 778 virtual const TypePtr *adr_type() const; 779 }; 780 781 //------------------------------MachSafePointNode----------------------------- 782 // Machine-specific versions of safepoints 783 class MachSafePointNode : public MachReturnNode { 784 public: 785 OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC 786 JVMState* _jvms; // Pointer to list of JVM State Objects 787 uint _jvmadj; // Extra delta to jvms indexes (mach. args) 788 OopMap* oop_map() const { return _oop_map; } 789 void set_oop_map(OopMap* om) { _oop_map = om; } 790 791 MachSafePointNode() : MachReturnNode(), _oop_map(NULL), _jvms(NULL), _jvmadj(0) { 792 init_class_id(Class_MachSafePoint); 793 } 794 795 virtual JVMState* jvms() const { return _jvms; } 796 void set_jvms(JVMState* s) { 797 _jvms = s; 798 } 799 virtual const Type *bottom_type() const; 800 801 virtual const RegMask &in_RegMask(uint) const; 802 803 // Functionality from old debug nodes 804 Node *returnadr() const { return in(TypeFunc::ReturnAdr); } 805 Node *frameptr () const { return in(TypeFunc::FramePtr); } 806 807 Node *local(const JVMState* jvms, uint idx) const { 808 assert(verify_jvms(jvms), "jvms must match"); 809 return in(_jvmadj + jvms->locoff() + idx); 810 } 811 Node *stack(const JVMState* jvms, uint idx) const { 812 assert(verify_jvms(jvms), "jvms must match"); 813 return in(_jvmadj + jvms->stkoff() + idx); 814 } 815 Node *monitor_obj(const JVMState* jvms, uint idx) const { 816 assert(verify_jvms(jvms), "jvms must match"); 817 return in(_jvmadj + jvms->monitor_obj_offset(idx)); 818 } 819 Node *monitor_box(const JVMState* jvms, uint idx) const { 820 assert(verify_jvms(jvms), "jvms must match"); 821 return in(_jvmadj + jvms->monitor_box_offset(idx)); 822 } 823 void set_local(const JVMState* jvms, uint idx, Node *c) { 824 assert(verify_jvms(jvms), "jvms must match"); 825 set_req(_jvmadj + jvms->locoff() + idx, c); 826 } 827 void set_stack(const JVMState* jvms, uint idx, Node *c) { 828 assert(verify_jvms(jvms), "jvms must match"); 829 set_req(_jvmadj + jvms->stkoff() + idx, c); 830 } 831 void set_monitor(const JVMState* jvms, uint idx, Node *c) { 832 assert(verify_jvms(jvms), "jvms must match"); 833 set_req(_jvmadj + jvms->monoff() + idx, c); 834 } 835 }; 836 837 //------------------------------MachCallNode---------------------------------- 838 // Machine-specific versions of subroutine calls 839 class MachCallNode : public MachSafePointNode { 840 protected: 841 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash 842 virtual uint cmp( const Node &n ) const; 843 virtual uint size_of() const = 0; // Size is bigger 844 public: 845 const TypeFunc *_tf; // Function type 846 address _entry_point; // Address of the method being called 847 float _cnt; // Estimate of number of times called 848 uint _argsize; // Size of argument block on stack 849 850 const TypeFunc* tf() const { return _tf; } 851 const address entry_point() const { return _entry_point; } 852 const float cnt() const { return _cnt; } 853 uint argsize() const { return _argsize; } 854 855 void set_tf(const TypeFunc* tf) { _tf = tf; } 856 void set_entry_point(address p) { _entry_point = p; } 857 void set_cnt(float c) { _cnt = c; } 858 void set_argsize(int s) { _argsize = s; } 859 860 MachCallNode() : MachSafePointNode() { 861 init_class_id(Class_MachCall); 862 } 863 864 virtual const Type *bottom_type() const; 865 virtual bool pinned() const { return false; } 866 virtual const Type *Value( PhaseTransform *phase ) const; 867 virtual const RegMask &in_RegMask(uint) const; 868 virtual int ret_addr_offset() { return 0; } 869 870 bool returns_long() const { return tf()->return_type() == T_LONG; } 871 bool return_value_is_used() const; 872 873 // Similar to cousin class CallNode::returns_pointer 874 bool returns_pointer() const; 875 876 #ifndef PRODUCT 877 virtual void dump_spec(outputStream *st) const; 878 #endif 879 }; 880 881 //------------------------------MachCallJavaNode------------------------------ 882 // "Base" class for machine-specific versions of subroutine calls 883 class MachCallJavaNode : public MachCallNode { 884 protected: 885 virtual uint cmp( const Node &n ) const; 886 virtual uint size_of() const; // Size is bigger 887 public: 888 ciMethod* _method; // Method being direct called 889 int _bci; // Byte Code index of call byte code 890 bool _optimized_virtual; // Tells if node is a static call or an optimized virtual 891 bool _method_handle_invoke; // Tells if the call has to preserve SP 892 MachCallJavaNode() : MachCallNode() { 893 init_class_id(Class_MachCallJava); 894 } 895 896 virtual const RegMask &in_RegMask(uint) const; 897 898 #ifndef PRODUCT 899 virtual void dump_spec(outputStream *st) const; 900 #endif 901 }; 902 903 //------------------------------MachCallStaticJavaNode------------------------ 904 // Machine-specific versions of monomorphic subroutine calls 905 class MachCallStaticJavaNode : public MachCallJavaNode { 906 virtual uint cmp( const Node &n ) const; 907 virtual uint size_of() const; // Size is bigger 908 public: 909 const char *_name; // Runtime wrapper name 910 MachCallStaticJavaNode() : MachCallJavaNode() { 911 init_class_id(Class_MachCallStaticJava); 912 } 913 914 // If this is an uncommon trap, return the request code, else zero. 915 int uncommon_trap_request() const; 916 917 virtual int ret_addr_offset(); 918 #ifndef PRODUCT 919 virtual void dump_spec(outputStream *st) const; 920 void dump_trap_args(outputStream *st) const; 921 #endif 922 }; 923 924 //------------------------------MachCallDynamicJavaNode------------------------ 925 // Machine-specific versions of possibly megamorphic subroutine calls 926 class MachCallDynamicJavaNode : public MachCallJavaNode { 927 public: 928 int _vtable_index; 929 MachCallDynamicJavaNode() : MachCallJavaNode() { 930 init_class_id(Class_MachCallDynamicJava); 931 DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized 932 } 933 virtual int ret_addr_offset(); 934 #ifndef PRODUCT 935 virtual void dump_spec(outputStream *st) const; 936 #endif 937 }; 938 939 //------------------------------MachCallRuntimeNode---------------------------- 940 // Machine-specific versions of subroutine calls 941 class MachCallRuntimeNode : public MachCallNode { 942 virtual uint cmp( const Node &n ) const; 943 virtual uint size_of() const; // Size is bigger 944 public: 945 const char *_name; // Printable name, if _method is NULL 946 MachCallRuntimeNode() : MachCallNode() { 947 init_class_id(Class_MachCallRuntime); 948 } 949 virtual int ret_addr_offset(); 950 #ifndef PRODUCT 951 virtual void dump_spec(outputStream *st) const; 952 #endif 953 }; 954 955 class MachCallLeafNode: public MachCallRuntimeNode { 956 public: 957 MachCallLeafNode() : MachCallRuntimeNode() { 958 init_class_id(Class_MachCallLeaf); 959 } 960 }; 961 962 //------------------------------MachHaltNode----------------------------------- 963 // Machine-specific versions of halt nodes 964 class MachHaltNode : public MachReturnNode { 965 public: 966 virtual JVMState* jvms() const; 967 }; 968 969 970 //------------------------------MachTempNode----------------------------------- 971 // Node used by the adlc to construct inputs to represent temporary registers 972 class MachTempNode : public MachNode { 973 private: 974 MachOper *_opnd_array[1]; 975 976 public: 977 virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); } 978 virtual uint rule() const { return 9999999; } 979 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {} 980 981 MachTempNode(MachOper* oper) { 982 init_class_id(Class_MachTemp); 983 _num_opnds = 1; 984 _opnds = _opnd_array; 985 add_req(NULL); 986 _opnds[0] = oper; 987 } 988 virtual uint size_of() const { return sizeof(MachTempNode); } 989 990 #ifndef PRODUCT 991 virtual void format(PhaseRegAlloc *, outputStream *st ) const {} 992 virtual const char *Name() const { return "MachTemp";} 993 #endif 994 }; 995 996 997 998 //------------------------------labelOper-------------------------------------- 999 // Machine-independent version of label operand 1000 class labelOper : public MachOper { 1001 private: 1002 virtual uint num_edges() const { return 0; } 1003 public: 1004 // Supported for fixed size branches 1005 Label* _label; // Label for branch(es) 1006 1007 uint _block_num; 1008 1009 labelOper() : _block_num(0), _label(0) {} 1010 1011 labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {} 1012 1013 labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {} 1014 1015 virtual MachOper *clone() const; 1016 1017 virtual Label *label() const { assert(_label != NULL, "need Label"); return _label; } 1018 1019 virtual uint opcode() const; 1020 1021 virtual uint hash() const; 1022 virtual uint cmp( const MachOper &oper ) const; 1023 #ifndef PRODUCT 1024 virtual const char *Name() const { return "Label";} 1025 1026 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; 1027 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); } 1028 #endif 1029 }; 1030 1031 1032 //------------------------------methodOper-------------------------------------- 1033 // Machine-independent version of method operand 1034 class methodOper : public MachOper { 1035 private: 1036 virtual uint num_edges() const { return 0; } 1037 public: 1038 intptr_t _method; // Address of method 1039 methodOper() : _method(0) {} 1040 methodOper(intptr_t method) : _method(method) {} 1041 1042 virtual MachOper *clone() const; 1043 1044 virtual intptr_t method() const { return _method; } 1045 1046 virtual uint opcode() const; 1047 1048 virtual uint hash() const; 1049 virtual uint cmp( const MachOper &oper ) const; 1050 #ifndef PRODUCT 1051 virtual const char *Name() const { return "Method";} 1052 1053 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const; 1054 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); } 1055 #endif 1056 }; 1057 1058 #endif // SHARE_VM_OPTO_MACHNODE_HPP