1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/barrierSet.hpp"
  39 #include "gc/shared/cardTableBarrierSet.hpp"
  40 #include "gc/shared/collectedHeap.hpp"
  41 #include "nativeInst_aarch64.hpp"
  42 #include "oops/objArrayKlass.hpp"
  43 #include "runtime/frame.inline.hpp"
  44 #include "runtime/sharedRuntime.hpp"
  45 #include "vmreg_aarch64.inline.hpp"
  46 
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::set_24bit_FPU() { Unimplemented(); }
 144 
 145 void LIR_Assembler::reset_FPU() { Unimplemented(); }
 146 
 147 void LIR_Assembler::fpop() { Unimplemented(); }
 148 
 149 void LIR_Assembler::fxch(int i) { Unimplemented(); }
 150 
 151 void LIR_Assembler::fld(int i) { Unimplemented(); }
 152 
 153 void LIR_Assembler::ffree(int i) { Unimplemented(); }
 154 
 155 void LIR_Assembler::breakpoint() { Unimplemented(); }
 156 
 157 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 158 
 159 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 160 
 161 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 162 //-------------------------------------------
 163 
 164 static Register as_reg(LIR_Opr op) {
 165   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 166 }
 167 
 168 static jlong as_long(LIR_Opr data) {
 169   jlong result;
 170   switch (data->type()) {
 171   case T_INT:
 172     result = (data->as_jint());
 173     break;
 174   case T_LONG:
 175     result = (data->as_jlong());
 176     break;
 177   default:
 178     ShouldNotReachHere();
 179     result = 0;  // unreachable
 180   }
 181   return result;
 182 }
 183 
 184 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 185   Register base = addr->base()->as_pointer_register();
 186   LIR_Opr opr = addr->index();
 187   if (opr->is_cpu_register()) {
 188     Register index;
 189     if (opr->is_single_cpu())
 190       index = opr->as_register();
 191     else
 192       index = opr->as_register_lo();
 193     assert(addr->disp() == 0, "must be");
 194     switch(opr->type()) {
 195       case T_INT:
 196         return Address(base, index, Address::sxtw(addr->scale()));
 197       case T_LONG:
 198         return Address(base, index, Address::lsl(addr->scale()));
 199       default:
 200         ShouldNotReachHere();
 201       }
 202   } else  {
 203     intptr_t addr_offset = intptr_t(addr->disp());
 204     if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
 205       return Address(base, addr_offset, Address::lsl(addr->scale()));
 206     else {
 207       __ mov(tmp, addr_offset);
 208       return Address(base, tmp, Address::lsl(addr->scale()));
 209     }
 210   }
 211   return Address();
 212 }
 213 
 214 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 215   ShouldNotReachHere();
 216   return Address();
 217 }
 218 
 219 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 220   return as_Address(addr, rscratch1);
 221 }
 222 
 223 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 224   return as_Address(addr, rscratch1);  // Ouch
 225   // FIXME: This needs to be much more clever.  See x86.
 226 }
 227 
 228 
 229 void LIR_Assembler::osr_entry() {
 230   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 231   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 232   ValueStack* entry_state = osr_entry->state();
 233   int number_of_locks = entry_state->locks_size();
 234 
 235   // we jump here if osr happens with the interpreter
 236   // state set up to continue at the beginning of the
 237   // loop that triggered osr - in particular, we have
 238   // the following registers setup:
 239   //
 240   // r2: osr buffer
 241   //
 242 
 243   // build frame
 244   ciMethod* m = compilation()->method();
 245   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 246 
 247   // OSR buffer is
 248   //
 249   // locals[nlocals-1..0]
 250   // monitors[0..number_of_locks]
 251   //
 252   // locals is a direct copy of the interpreter frame so in the osr buffer
 253   // so first slot in the local array is the last local from the interpreter
 254   // and last slot is local[0] (receiver) from the interpreter
 255   //
 256   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 257   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 258   // in the interpreter frame (the method lock if a sync method)
 259 
 260   // Initialize monitors in the compiled activation.
 261   //   r2: pointer to osr buffer
 262   //
 263   // All other registers are dead at this point and the locals will be
 264   // copied into place by code emitted in the IR.
 265 
 266   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 267   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 268     int monitor_offset = BytesPerWord * method()->max_locals() +
 269       (2 * BytesPerWord) * (number_of_locks - 1);
 270     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 271     // the OSR buffer using 2 word entries: first the lock and then
 272     // the oop.
 273     for (int i = 0; i < number_of_locks; i++) {
 274       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 275 #ifdef ASSERT
 276       // verify the interpreter's monitor has a non-null object
 277       {
 278         Label L;
 279         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 280         __ cbnz(rscratch1, L);
 281         __ stop("locked object is NULL");
 282         __ bind(L);
 283       }
 284 #endif
 285       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 286       __ str(r19, frame_map()->address_for_monitor_lock(i));
 287       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 288       __ str(r19, frame_map()->address_for_monitor_object(i));
 289     }
 290   }
 291 }
 292 
 293 
 294 // inline cache check; done before the frame is built.
 295 int LIR_Assembler::check_icache() {
 296   Register receiver = FrameMap::receiver_opr->as_register();
 297   Register ic_klass = IC_Klass;
 298   int start_offset = __ offset();
 299   __ inline_cache_check(receiver, ic_klass);
 300 
 301   // if icache check fails, then jump to runtime routine
 302   // Note: RECEIVER must still contain the receiver!
 303   Label dont;
 304   __ br(Assembler::EQ, dont);
 305   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 306 
 307   // We align the verified entry point unless the method body
 308   // (including its inline cache check) will fit in a single 64-byte
 309   // icache line.
 310   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 311     // force alignment after the cache check.
 312     __ align(CodeEntryAlignment);
 313   }
 314 
 315   __ bind(dont);
 316   return start_offset;
 317 }
 318 
 319 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 320   ShouldNotReachHere(); // not implemented
 321 }
 322 
 323 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 324   if (o == NULL) {
 325     __ mov(reg, zr);
 326   } else {
 327     __ movoop(reg, o, /*immediate*/true);
 328   }
 329 }
 330 
 331 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 332   address target = NULL;
 333   relocInfo::relocType reloc_type = relocInfo::none;
 334 
 335   switch (patching_id(info)) {
 336   case PatchingStub::access_field_id:
 337     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 338     reloc_type = relocInfo::section_word_type;
 339     break;
 340   case PatchingStub::load_klass_id:
 341     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 342     reloc_type = relocInfo::metadata_type;
 343     break;
 344   case PatchingStub::load_mirror_id:
 345     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 346     reloc_type = relocInfo::oop_type;
 347     break;
 348   case PatchingStub::load_appendix_id:
 349     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 350     reloc_type = relocInfo::oop_type;
 351     break;
 352   default: ShouldNotReachHere();
 353   }
 354 
 355   __ far_call(RuntimeAddress(target));
 356   add_call_info_here(info);
 357 }
 358 
 359 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 360   deoptimize_trap(info);
 361 }
 362 
 363 
 364 // This specifies the rsp decrement needed to build the frame
 365 int LIR_Assembler::initial_frame_size_in_bytes() const {
 366   // if rounding, must let FrameMap know!
 367 
 368   // The frame_map records size in slots (32bit word)
 369 
 370   // subtract two words to account for return address and link
 371   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 372 }
 373 
 374 
 375 int LIR_Assembler::emit_exception_handler() {
 376   // if the last instruction is a call (typically to do a throw which
 377   // is coming at the end after block reordering) the return address
 378   // must still point into the code area in order to avoid assertion
 379   // failures when searching for the corresponding bci => add a nop
 380   // (was bug 5/14/1999 - gri)
 381   __ nop();
 382 
 383   // generate code for exception handler
 384   address handler_base = __ start_a_stub(exception_handler_size());
 385   if (handler_base == NULL) {
 386     // not enough space left for the handler
 387     bailout("exception handler overflow");
 388     return -1;
 389   }
 390 
 391   int offset = code_offset();
 392 
 393   // the exception oop and pc are in r0, and r3
 394   // no other registers need to be preserved, so invalidate them
 395   __ invalidate_registers(false, true, true, false, true, true);
 396 
 397   // check that there is really an exception
 398   __ verify_not_null_oop(r0);
 399 
 400   // search an exception handler (r0: exception oop, r3: throwing pc)
 401   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 402   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 403   __ end_a_stub();
 404 
 405   return offset;
 406 }
 407 
 408 
 409 // Emit the code to remove the frame from the stack in the exception
 410 // unwind path.
 411 int LIR_Assembler::emit_unwind_handler() {
 412 #ifndef PRODUCT
 413   if (CommentedAssembly) {
 414     _masm->block_comment("Unwind handler");
 415   }
 416 #endif
 417 
 418   int offset = code_offset();
 419 
 420   // Fetch the exception from TLS and clear out exception related thread state
 421   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 422   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 423   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 424 
 425   __ bind(_unwind_handler_entry);
 426   __ verify_not_null_oop(r0);
 427   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 428     __ mov(r19, r0);  // Preserve the exception
 429   }
 430 
 431   // Preform needed unlocking
 432   MonitorExitStub* stub = NULL;
 433   if (method()->is_synchronized()) {
 434     monitor_address(0, FrameMap::r0_opr);
 435     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 436     __ unlock_object(r5, r4, r0, *stub->entry());
 437     __ bind(*stub->continuation());
 438   }
 439 
 440   if (compilation()->env()->dtrace_method_probes()) {
 441     __ call_Unimplemented();
 442 #if 0
 443     __ movptr(Address(rsp, 0), rax);
 444     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 445     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 446 #endif
 447   }
 448 
 449   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 450     __ mov(r0, r19);  // Restore the exception
 451   }
 452 
 453   // remove the activation and dispatch to the unwind handler
 454   __ block_comment("remove_frame and dispatch to the unwind handler");
 455   __ remove_frame(initial_frame_size_in_bytes());
 456   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 457 
 458   // Emit the slow path assembly
 459   if (stub != NULL) {
 460     stub->emit_code(this);
 461   }
 462 
 463   return offset;
 464 }
 465 
 466 
 467 int LIR_Assembler::emit_deopt_handler() {
 468   // if the last instruction is a call (typically to do a throw which
 469   // is coming at the end after block reordering) the return address
 470   // must still point into the code area in order to avoid assertion
 471   // failures when searching for the corresponding bci => add a nop
 472   // (was bug 5/14/1999 - gri)
 473   __ nop();
 474 
 475   // generate code for exception handler
 476   address handler_base = __ start_a_stub(deopt_handler_size());
 477   if (handler_base == NULL) {
 478     // not enough space left for the handler
 479     bailout("deopt handler overflow");
 480     return -1;
 481   }
 482 
 483   int offset = code_offset();
 484 
 485   __ adr(lr, pc());
 486   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 487   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 488   __ end_a_stub();
 489 
 490   return offset;
 491 }
 492 
 493 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 494   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 495   int pc_offset = code_offset();
 496   flush_debug_info(pc_offset);
 497   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 498   if (info->exception_handlers() != NULL) {
 499     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 500   }
 501 }
 502 
 503 void LIR_Assembler::return_op(LIR_Opr result) {
 504   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 505 
 506   // Pop the stack before the safepoint code
 507   __ remove_frame(initial_frame_size_in_bytes());
 508 
 509   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 510     __ reserved_stack_check();
 511   }
 512 
 513   address polling_page(os::get_polling_page());
 514   __ read_polling_page(rscratch1, polling_page, relocInfo::poll_return_type);
 515   __ ret(lr);
 516 }
 517 
 518 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 519   address polling_page(os::get_polling_page());
 520   guarantee(info != NULL, "Shouldn't be NULL");
 521   assert(os::is_poll_address(polling_page), "should be");
 522   __ get_polling_page(rscratch1, polling_page, relocInfo::poll_type);
 523   add_debug_info_for_branch(info);  // This isn't just debug info:
 524                                     // it's the oop map
 525   __ read_polling_page(rscratch1, relocInfo::poll_type);
 526   return __ offset();
 527 }
 528 
 529 
 530 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 531   if (from_reg == r31_sp)
 532     from_reg = sp;
 533   if (to_reg == r31_sp)
 534     to_reg = sp;
 535   __ mov(to_reg, from_reg);
 536 }
 537 
 538 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 539 
 540 
 541 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 542   assert(src->is_constant(), "should not call otherwise");
 543   assert(dest->is_register(), "should not call otherwise");
 544   LIR_Const* c = src->as_constant_ptr();
 545 
 546   switch (c->type()) {
 547     case T_INT: {
 548       assert(patch_code == lir_patch_none, "no patching handled here");
 549       __ movw(dest->as_register(), c->as_jint());
 550       break;
 551     }
 552 
 553     case T_ADDRESS: {
 554       assert(patch_code == lir_patch_none, "no patching handled here");
 555       __ mov(dest->as_register(), c->as_jint());
 556       break;
 557     }
 558 
 559     case T_LONG: {
 560       assert(patch_code == lir_patch_none, "no patching handled here");
 561       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 562       break;
 563     }
 564 
 565     case T_OBJECT: {
 566         if (patch_code == lir_patch_none) {
 567           jobject2reg(c->as_jobject(), dest->as_register());
 568         } else {
 569           jobject2reg_with_patching(dest->as_register(), info);
 570         }
 571       break;
 572     }
 573 
 574     case T_METADATA: {
 575       if (patch_code != lir_patch_none) {
 576         klass2reg_with_patching(dest->as_register(), info);
 577       } else {
 578         __ mov_metadata(dest->as_register(), c->as_metadata());
 579       }
 580       break;
 581     }
 582 
 583     case T_FLOAT: {
 584       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 585         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 586       } else {
 587         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 588         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 589       }
 590       break;
 591     }
 592 
 593     case T_DOUBLE: {
 594       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 595         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 596       } else {
 597         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 598         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 599       }
 600       break;
 601     }
 602 
 603     default:
 604       ShouldNotReachHere();
 605   }
 606 }
 607 
 608 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 609   LIR_Const* c = src->as_constant_ptr();
 610   switch (c->type()) {
 611   case T_OBJECT:
 612     {
 613       if (! c->as_jobject())
 614         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 615       else {
 616         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 617         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 618       }
 619     }
 620     break;
 621   case T_ADDRESS:
 622     {
 623       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 624       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 625     }
 626   case T_INT:
 627   case T_FLOAT:
 628     {
 629       Register reg = zr;
 630       if (c->as_jint_bits() == 0)
 631         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 632       else {
 633         __ movw(rscratch1, c->as_jint_bits());
 634         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 635       }
 636     }
 637     break;
 638   case T_LONG:
 639   case T_DOUBLE:
 640     {
 641       Register reg = zr;
 642       if (c->as_jlong_bits() == 0)
 643         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 644                                                  lo_word_offset_in_bytes));
 645       else {
 646         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 647         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 648                                                         lo_word_offset_in_bytes));
 649       }
 650     }
 651     break;
 652   default:
 653     ShouldNotReachHere();
 654   }
 655 }
 656 
 657 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 658   assert(src->is_constant(), "should not call otherwise");
 659   LIR_Const* c = src->as_constant_ptr();
 660   LIR_Address* to_addr = dest->as_address_ptr();
 661 
 662   void (Assembler::* insn)(Register Rt, const Address &adr);
 663 
 664   switch (type) {
 665   case T_ADDRESS:
 666     assert(c->as_jint() == 0, "should be");
 667     insn = &Assembler::str;
 668     break;
 669   case T_LONG:
 670     assert(c->as_jlong() == 0, "should be");
 671     insn = &Assembler::str;
 672     break;
 673   case T_INT:
 674     assert(c->as_jint() == 0, "should be");
 675     insn = &Assembler::strw;
 676     break;
 677   case T_OBJECT:
 678   case T_ARRAY:
 679     assert(c->as_jobject() == 0, "should be");
 680     if (UseCompressedOops && !wide) {
 681       insn = &Assembler::strw;
 682     } else {
 683       insn = &Assembler::str;
 684     }
 685     break;
 686   case T_CHAR:
 687   case T_SHORT:
 688     assert(c->as_jint() == 0, "should be");
 689     insn = &Assembler::strh;
 690     break;
 691   case T_BOOLEAN:
 692   case T_BYTE:
 693     assert(c->as_jint() == 0, "should be");
 694     insn = &Assembler::strb;
 695     break;
 696   default:
 697     ShouldNotReachHere();
 698     insn = &Assembler::str;  // unreachable
 699   }
 700 
 701   if (info) add_debug_info_for_null_check_here(info);
 702   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 703 }
 704 
 705 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 706   assert(src->is_register(), "should not call otherwise");
 707   assert(dest->is_register(), "should not call otherwise");
 708 
 709   // move between cpu-registers
 710   if (dest->is_single_cpu()) {
 711     if (src->type() == T_LONG) {
 712       // Can do LONG -> OBJECT
 713       move_regs(src->as_register_lo(), dest->as_register());
 714       return;
 715     }
 716     assert(src->is_single_cpu(), "must match");
 717     if (src->type() == T_OBJECT) {
 718       __ verify_oop(src->as_register());
 719     }
 720     move_regs(src->as_register(), dest->as_register());
 721 
 722   } else if (dest->is_double_cpu()) {
 723     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 724       // Surprising to me but we can see move of a long to t_object
 725       __ verify_oop(src->as_register());
 726       move_regs(src->as_register(), dest->as_register_lo());
 727       return;
 728     }
 729     assert(src->is_double_cpu(), "must match");
 730     Register f_lo = src->as_register_lo();
 731     Register f_hi = src->as_register_hi();
 732     Register t_lo = dest->as_register_lo();
 733     Register t_hi = dest->as_register_hi();
 734     assert(f_hi == f_lo, "must be same");
 735     assert(t_hi == t_lo, "must be same");
 736     move_regs(f_lo, t_lo);
 737 
 738   } else if (dest->is_single_fpu()) {
 739     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 740 
 741   } else if (dest->is_double_fpu()) {
 742     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 743 
 744   } else {
 745     ShouldNotReachHere();
 746   }
 747 }
 748 
 749 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 750   if (src->is_single_cpu()) {
 751     if (type == T_ARRAY || type == T_OBJECT) {
 752       __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 753       __ verify_oop(src->as_register());
 754     } else if (type == T_METADATA || type == T_DOUBLE) {
 755       __ str(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 756     } else {
 757       __ strw(src->as_register(), frame_map()->address_for_slot(dest->single_stack_ix()));
 758     }
 759 
 760   } else if (src->is_double_cpu()) {
 761     Address dest_addr_LO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 762     __ str(src->as_register_lo(), dest_addr_LO);
 763 
 764   } else if (src->is_single_fpu()) {
 765     Address dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 766     __ strs(src->as_float_reg(), dest_addr);
 767 
 768   } else if (src->is_double_fpu()) {
 769     Address dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 770     __ strd(src->as_double_reg(), dest_addr);
 771 
 772   } else {
 773     ShouldNotReachHere();
 774   }
 775 
 776 }
 777 
 778 
 779 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 780   LIR_Address* to_addr = dest->as_address_ptr();
 781   PatchingStub* patch = NULL;
 782   Register compressed_src = rscratch1;
 783 
 784   if (patch_code != lir_patch_none) {
 785     deoptimize_trap(info);
 786     return;
 787   }
 788 
 789   if (type == T_ARRAY || type == T_OBJECT) {
 790     __ verify_oop(src->as_register());
 791 
 792     if (UseCompressedOops && !wide) {
 793       __ encode_heap_oop(compressed_src, src->as_register());
 794     } else {
 795       compressed_src = src->as_register();
 796     }
 797   }
 798 
 799   int null_check_here = code_offset();
 800   switch (type) {
 801     case T_FLOAT: {
 802       __ strs(src->as_float_reg(), as_Address(to_addr));
 803       break;
 804     }
 805 
 806     case T_DOUBLE: {
 807       __ strd(src->as_double_reg(), as_Address(to_addr));
 808       break;
 809     }
 810 
 811     case T_ARRAY:   // fall through
 812     case T_OBJECT:  // fall through
 813       if (UseCompressedOops && !wide) {
 814         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 815       } else {
 816          __ str(compressed_src, as_Address(to_addr));
 817       }
 818       break;
 819     case T_METADATA:
 820       // We get here to store a method pointer to the stack to pass to
 821       // a dtrace runtime call. This can't work on 64 bit with
 822       // compressed klass ptrs: T_METADATA can be a compressed klass
 823       // ptr or a 64 bit method pointer.
 824       ShouldNotReachHere();
 825       __ str(src->as_register(), as_Address(to_addr));
 826       break;
 827     case T_ADDRESS:
 828       __ str(src->as_register(), as_Address(to_addr));
 829       break;
 830     case T_INT:
 831       __ strw(src->as_register(), as_Address(to_addr));
 832       break;
 833 
 834     case T_LONG: {
 835       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 836       break;
 837     }
 838 
 839     case T_BYTE:    // fall through
 840     case T_BOOLEAN: {
 841       __ strb(src->as_register(), as_Address(to_addr));
 842       break;
 843     }
 844 
 845     case T_CHAR:    // fall through
 846     case T_SHORT:
 847       __ strh(src->as_register(), as_Address(to_addr));
 848       break;
 849 
 850     default:
 851       ShouldNotReachHere();
 852   }
 853   if (info != NULL) {
 854     add_debug_info_for_null_check(null_check_here, info);
 855   }
 856 }
 857 
 858 
 859 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 860   assert(src->is_stack(), "should not call otherwise");
 861   assert(dest->is_register(), "should not call otherwise");
 862 
 863   if (dest->is_single_cpu()) {
 864     if (type == T_ARRAY || type == T_OBJECT) {
 865       __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 866       __ verify_oop(dest->as_register());
 867     } else if (type == T_METADATA) {
 868       __ ldr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 869     } else {
 870       __ ldrw(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
 871     }
 872 
 873   } else if (dest->is_double_cpu()) {
 874     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
 875     __ ldr(dest->as_register_lo(), src_addr_LO);
 876 
 877   } else if (dest->is_single_fpu()) {
 878     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
 879     __ ldrs(dest->as_float_reg(), src_addr);
 880 
 881   } else if (dest->is_double_fpu()) {
 882     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
 883     __ ldrd(dest->as_double_reg(), src_addr);
 884 
 885   } else {
 886     ShouldNotReachHere();
 887   }
 888 }
 889 
 890 
 891 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 892   address target = NULL;
 893   relocInfo::relocType reloc_type = relocInfo::none;
 894 
 895   switch (patching_id(info)) {
 896   case PatchingStub::access_field_id:
 897     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 898     reloc_type = relocInfo::section_word_type;
 899     break;
 900   case PatchingStub::load_klass_id:
 901     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 902     reloc_type = relocInfo::metadata_type;
 903     break;
 904   case PatchingStub::load_mirror_id:
 905     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 906     reloc_type = relocInfo::oop_type;
 907     break;
 908   case PatchingStub::load_appendix_id:
 909     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 910     reloc_type = relocInfo::oop_type;
 911     break;
 912   default: ShouldNotReachHere();
 913   }
 914 
 915   __ far_call(RuntimeAddress(target));
 916   add_call_info_here(info);
 917 }
 918 
 919 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 920 
 921   LIR_Opr temp;
 922   if (type == T_LONG || type == T_DOUBLE)
 923     temp = FrameMap::rscratch1_long_opr;
 924   else
 925     temp = FrameMap::rscratch1_opr;
 926 
 927   stack2reg(src, temp, src->type());
 928   reg2stack(temp, dest, dest->type(), false);
 929 }
 930 
 931 
 932 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
 933   LIR_Address* addr = src->as_address_ptr();
 934   LIR_Address* from_addr = src->as_address_ptr();
 935 
 936   if (addr->base()->type() == T_OBJECT) {
 937     __ verify_oop(addr->base()->as_pointer_register());
 938   }
 939 
 940   if (patch_code != lir_patch_none) {
 941     deoptimize_trap(info);
 942     return;
 943   }
 944 
 945   if (info != NULL) {
 946     add_debug_info_for_null_check_here(info);
 947   }
 948   int null_check_here = code_offset();
 949   switch (type) {
 950     case T_FLOAT: {
 951       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 952       break;
 953     }
 954 
 955     case T_DOUBLE: {
 956       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 957       break;
 958     }
 959 
 960     case T_ARRAY:   // fall through
 961     case T_OBJECT:  // fall through
 962       if (UseCompressedOops && !wide) {
 963         __ ldrw(dest->as_register(), as_Address(from_addr));
 964       } else {
 965          __ ldr(dest->as_register(), as_Address(from_addr));
 966       }
 967       break;
 968     case T_METADATA:
 969       // We get here to store a method pointer to the stack to pass to
 970       // a dtrace runtime call. This can't work on 64 bit with
 971       // compressed klass ptrs: T_METADATA can be a compressed klass
 972       // ptr or a 64 bit method pointer.
 973       ShouldNotReachHere();
 974       __ ldr(dest->as_register(), as_Address(from_addr));
 975       break;
 976     case T_ADDRESS:
 977       // FIXME: OMG this is a horrible kludge.  Any offset from an
 978       // address that matches klass_offset_in_bytes() will be loaded
 979       // as a word, not a long.
 980       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 981         __ ldrw(dest->as_register(), as_Address(from_addr));
 982       } else {
 983         __ ldr(dest->as_register(), as_Address(from_addr));
 984       }
 985       break;
 986     case T_INT:
 987       __ ldrw(dest->as_register(), as_Address(from_addr));
 988       break;
 989 
 990     case T_LONG: {
 991       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
 992       break;
 993     }
 994 
 995     case T_BYTE:
 996       __ ldrsb(dest->as_register(), as_Address(from_addr));
 997       break;
 998     case T_BOOLEAN: {
 999       __ ldrb(dest->as_register(), as_Address(from_addr));
1000       break;
1001     }
1002 
1003     case T_CHAR:
1004       __ ldrh(dest->as_register(), as_Address(from_addr));
1005       break;
1006     case T_SHORT:
1007       __ ldrsh(dest->as_register(), as_Address(from_addr));
1008       break;
1009 
1010     default:
1011       ShouldNotReachHere();
1012   }
1013 
1014   if (type == T_ARRAY || type == T_OBJECT) {
1015     if (UseCompressedOops && !wide) {
1016       __ decode_heap_oop(dest->as_register());
1017     }
1018     __ verify_oop(dest->as_register());
1019   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1020     if (UseCompressedClassPointers) {
1021       __ decode_klass_not_null(dest->as_register());
1022     }
1023   }
1024 }
1025 
1026 
1027 int LIR_Assembler::array_element_size(BasicType type) const {
1028   int elem_size = type2aelembytes(type);
1029   return exact_log2(elem_size);
1030 }
1031 
1032 
1033 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1034   switch (op->code()) {
1035   case lir_idiv:
1036   case lir_irem:
1037     arithmetic_idiv(op->code(),
1038                     op->in_opr1(),
1039                     op->in_opr2(),
1040                     op->in_opr3(),
1041                     op->result_opr(),
1042                     op->info());
1043     break;
1044   case lir_fmad:
1045     __ fmaddd(op->result_opr()->as_double_reg(),
1046               op->in_opr1()->as_double_reg(),
1047               op->in_opr2()->as_double_reg(),
1048               op->in_opr3()->as_double_reg());
1049     break;
1050   case lir_fmaf:
1051     __ fmadds(op->result_opr()->as_float_reg(),
1052               op->in_opr1()->as_float_reg(),
1053               op->in_opr2()->as_float_reg(),
1054               op->in_opr3()->as_float_reg());
1055     break;
1056   default:      ShouldNotReachHere(); break;
1057   }
1058 }
1059 
1060 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1061 #ifdef ASSERT
1062   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1063   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1064   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1065 #endif
1066 
1067   if (op->cond() == lir_cond_always) {
1068     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1069     __ b(*(op->label()));
1070   } else {
1071     Assembler::Condition acond;
1072     if (op->code() == lir_cond_float_branch) {
1073       bool is_unordered = (op->ublock() == op->block());
1074       // Assembler::EQ does not permit unordered branches, so we add
1075       // another branch here.  Likewise, Assembler::NE does not permit
1076       // ordered branches.
1077       if (is_unordered && op->cond() == lir_cond_equal
1078           || !is_unordered && op->cond() == lir_cond_notEqual)
1079         __ br(Assembler::VS, *(op->ublock()->label()));
1080       switch(op->cond()) {
1081       case lir_cond_equal:        acond = Assembler::EQ; break;
1082       case lir_cond_notEqual:     acond = Assembler::NE; break;
1083       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1084       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1085       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1086       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1087       default:                    ShouldNotReachHere();
1088         acond = Assembler::EQ;  // unreachable
1089       }
1090     } else {
1091       switch (op->cond()) {
1092         case lir_cond_equal:        acond = Assembler::EQ; break;
1093         case lir_cond_notEqual:     acond = Assembler::NE; break;
1094         case lir_cond_less:         acond = Assembler::LT; break;
1095         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1096         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1097         case lir_cond_greater:      acond = Assembler::GT; break;
1098         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1099         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1100         default:                    ShouldNotReachHere();
1101           acond = Assembler::EQ;  // unreachable
1102       }
1103     }
1104     __ br(acond,*(op->label()));
1105   }
1106 }
1107 
1108 
1109 
1110 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1111   LIR_Opr src  = op->in_opr();
1112   LIR_Opr dest = op->result_opr();
1113 
1114   switch (op->bytecode()) {
1115     case Bytecodes::_i2f:
1116       {
1117         __ scvtfws(dest->as_float_reg(), src->as_register());
1118         break;
1119       }
1120     case Bytecodes::_i2d:
1121       {
1122         __ scvtfwd(dest->as_double_reg(), src->as_register());
1123         break;
1124       }
1125     case Bytecodes::_l2d:
1126       {
1127         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1128         break;
1129       }
1130     case Bytecodes::_l2f:
1131       {
1132         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1133         break;
1134       }
1135     case Bytecodes::_f2d:
1136       {
1137         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1138         break;
1139       }
1140     case Bytecodes::_d2f:
1141       {
1142         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1143         break;
1144       }
1145     case Bytecodes::_i2c:
1146       {
1147         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1148         break;
1149       }
1150     case Bytecodes::_i2l:
1151       {
1152         __ sxtw(dest->as_register_lo(), src->as_register());
1153         break;
1154       }
1155     case Bytecodes::_i2s:
1156       {
1157         __ sxth(dest->as_register(), src->as_register());
1158         break;
1159       }
1160     case Bytecodes::_i2b:
1161       {
1162         __ sxtb(dest->as_register(), src->as_register());
1163         break;
1164       }
1165     case Bytecodes::_l2i:
1166       {
1167         _masm->block_comment("FIXME: This could be a no-op");
1168         __ uxtw(dest->as_register(), src->as_register_lo());
1169         break;
1170       }
1171     case Bytecodes::_d2l:
1172       {
1173         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1174         break;
1175       }
1176     case Bytecodes::_f2i:
1177       {
1178         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1179         break;
1180       }
1181     case Bytecodes::_f2l:
1182       {
1183         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1184         break;
1185       }
1186     case Bytecodes::_d2i:
1187       {
1188         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1189         break;
1190       }
1191     default: ShouldNotReachHere();
1192   }
1193 }
1194 
1195 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1196   if (op->init_check()) {
1197     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1198                                InstanceKlass::init_state_offset()));
1199     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1200     add_debug_info_for_null_check_here(op->stub()->info());
1201     __ br(Assembler::NE, *op->stub()->entry());
1202   }
1203   __ allocate_object(op->obj()->as_register(),
1204                      op->tmp1()->as_register(),
1205                      op->tmp2()->as_register(),
1206                      op->header_size(),
1207                      op->object_size(),
1208                      op->klass()->as_register(),
1209                      *op->stub()->entry());
1210   __ bind(*op->stub()->continuation());
1211 }
1212 
1213 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1214   Register len =  op->len()->as_register();
1215   __ uxtw(len, len);
1216 
1217   if (UseSlowPath ||
1218       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1219       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1220     __ b(*op->stub()->entry());
1221   } else {
1222     Register tmp1 = op->tmp1()->as_register();
1223     Register tmp2 = op->tmp2()->as_register();
1224     Register tmp3 = op->tmp3()->as_register();
1225     if (len == tmp1) {
1226       tmp1 = tmp3;
1227     } else if (len == tmp2) {
1228       tmp2 = tmp3;
1229     } else if (len == tmp3) {
1230       // everything is ok
1231     } else {
1232       __ mov(tmp3, len);
1233     }
1234     __ allocate_array(op->obj()->as_register(),
1235                       len,
1236                       tmp1,
1237                       tmp2,
1238                       arrayOopDesc::header_size(op->type()),
1239                       array_element_size(op->type()),
1240                       op->klass()->as_register(),
1241                       *op->stub()->entry());
1242   }
1243   __ bind(*op->stub()->continuation());
1244 }
1245 
1246 void LIR_Assembler::type_profile_helper(Register mdo,
1247                                         ciMethodData *md, ciProfileData *data,
1248                                         Register recv, Label* update_done) {
1249   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1250     Label next_test;
1251     // See if the receiver is receiver[n].
1252     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1253     __ ldr(rscratch1, Address(rscratch2));
1254     __ cmp(recv, rscratch1);
1255     __ br(Assembler::NE, next_test);
1256     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1257     __ addptr(data_addr, DataLayout::counter_increment);
1258     __ b(*update_done);
1259     __ bind(next_test);
1260   }
1261 
1262   // Didn't find receiver; find next empty slot and fill it in
1263   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1264     Label next_test;
1265     __ lea(rscratch2,
1266            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1267     Address recv_addr(rscratch2);
1268     __ ldr(rscratch1, recv_addr);
1269     __ cbnz(rscratch1, next_test);
1270     __ str(recv, recv_addr);
1271     __ mov(rscratch1, DataLayout::counter_increment);
1272     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1273     __ str(rscratch1, Address(rscratch2));
1274     __ b(*update_done);
1275     __ bind(next_test);
1276   }
1277 }
1278 
1279 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1280   // we always need a stub for the failure case.
1281   CodeStub* stub = op->stub();
1282   Register obj = op->object()->as_register();
1283   Register k_RInfo = op->tmp1()->as_register();
1284   Register klass_RInfo = op->tmp2()->as_register();
1285   Register dst = op->result_opr()->as_register();
1286   ciKlass* k = op->klass();
1287   Register Rtmp1 = noreg;
1288 
1289   // check if it needs to be profiled
1290   ciMethodData* md;
1291   ciProfileData* data;
1292 
1293   const bool should_profile = op->should_profile();
1294 
1295   if (should_profile) {
1296     ciMethod* method = op->profiled_method();
1297     assert(method != NULL, "Should have method");
1298     int bci = op->profiled_bci();
1299     md = method->method_data_or_null();
1300     assert(md != NULL, "Sanity");
1301     data = md->bci_to_data(bci);
1302     assert(data != NULL,                "need data for type check");
1303     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1304   }
1305   Label profile_cast_success, profile_cast_failure;
1306   Label *success_target = should_profile ? &profile_cast_success : success;
1307   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1308 
1309   if (obj == k_RInfo) {
1310     k_RInfo = dst;
1311   } else if (obj == klass_RInfo) {
1312     klass_RInfo = dst;
1313   }
1314   if (k->is_loaded() && !UseCompressedClassPointers) {
1315     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1316   } else {
1317     Rtmp1 = op->tmp3()->as_register();
1318     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1319   }
1320 
1321   assert_different_registers(obj, k_RInfo, klass_RInfo);
1322 
1323     if (should_profile) {
1324       Label not_null;
1325       __ cbnz(obj, not_null);
1326       // Object is null; update MDO and exit
1327       Register mdo  = klass_RInfo;
1328       __ mov_metadata(mdo, md->constant_encoding());
1329       Address data_addr
1330         = __ form_address(rscratch2, mdo,
1331                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1332                           0);
1333       __ ldrb(rscratch1, data_addr);
1334       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1335       __ strb(rscratch1, data_addr);
1336       __ b(*obj_is_null);
1337       __ bind(not_null);
1338     } else {
1339       __ cbz(obj, *obj_is_null);
1340     }
1341 
1342   if (!k->is_loaded()) {
1343     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1344   } else {
1345     __ mov_metadata(k_RInfo, k->constant_encoding());
1346   }
1347   __ verify_oop(obj);
1348 
1349   if (op->fast_check()) {
1350     // get object class
1351     // not a safepoint as obj null check happens earlier
1352     __ load_klass(rscratch1, obj);
1353     __ cmp( rscratch1, k_RInfo);
1354 
1355     __ br(Assembler::NE, *failure_target);
1356     // successful cast, fall through to profile or jump
1357   } else {
1358     // get object class
1359     // not a safepoint as obj null check happens earlier
1360     __ load_klass(klass_RInfo, obj);
1361     if (k->is_loaded()) {
1362       // See if we get an immediate positive hit
1363       __ ldr(rscratch1, Address(klass_RInfo, long(k->super_check_offset())));
1364       __ cmp(k_RInfo, rscratch1);
1365       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1366         __ br(Assembler::NE, *failure_target);
1367         // successful cast, fall through to profile or jump
1368       } else {
1369         // See if we get an immediate positive hit
1370         __ br(Assembler::EQ, *success_target);
1371         // check for self
1372         __ cmp(klass_RInfo, k_RInfo);
1373         __ br(Assembler::EQ, *success_target);
1374 
1375         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1376         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1377         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1378         // result is a boolean
1379         __ cbzw(klass_RInfo, *failure_target);
1380         // successful cast, fall through to profile or jump
1381       }
1382     } else {
1383       // perform the fast part of the checking logic
1384       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1385       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1386       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1387       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1388       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1389       // result is a boolean
1390       __ cbz(k_RInfo, *failure_target);
1391       // successful cast, fall through to profile or jump
1392     }
1393   }
1394   if (should_profile) {
1395     Register mdo  = klass_RInfo, recv = k_RInfo;
1396     __ bind(profile_cast_success);
1397     __ mov_metadata(mdo, md->constant_encoding());
1398     __ load_klass(recv, obj);
1399     Label update_done;
1400     type_profile_helper(mdo, md, data, recv, success);
1401     __ b(*success);
1402 
1403     __ bind(profile_cast_failure);
1404     __ mov_metadata(mdo, md->constant_encoding());
1405     Address counter_addr
1406       = __ form_address(rscratch2, mdo,
1407                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1408                         0);
1409     __ ldr(rscratch1, counter_addr);
1410     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1411     __ str(rscratch1, counter_addr);
1412     __ b(*failure);
1413   }
1414   __ b(*success);
1415 }
1416 
1417 
1418 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1419   const bool should_profile = op->should_profile();
1420 
1421   LIR_Code code = op->code();
1422   if (code == lir_store_check) {
1423     Register value = op->object()->as_register();
1424     Register array = op->array()->as_register();
1425     Register k_RInfo = op->tmp1()->as_register();
1426     Register klass_RInfo = op->tmp2()->as_register();
1427     Register Rtmp1 = op->tmp3()->as_register();
1428 
1429     CodeStub* stub = op->stub();
1430 
1431     // check if it needs to be profiled
1432     ciMethodData* md;
1433     ciProfileData* data;
1434 
1435     if (should_profile) {
1436       ciMethod* method = op->profiled_method();
1437       assert(method != NULL, "Should have method");
1438       int bci = op->profiled_bci();
1439       md = method->method_data_or_null();
1440       assert(md != NULL, "Sanity");
1441       data = md->bci_to_data(bci);
1442       assert(data != NULL,                "need data for type check");
1443       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1444     }
1445     Label profile_cast_success, profile_cast_failure, done;
1446     Label *success_target = should_profile ? &profile_cast_success : &done;
1447     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1448 
1449     if (should_profile) {
1450       Label not_null;
1451       __ cbnz(value, not_null);
1452       // Object is null; update MDO and exit
1453       Register mdo  = klass_RInfo;
1454       __ mov_metadata(mdo, md->constant_encoding());
1455       Address data_addr
1456         = __ form_address(rscratch2, mdo,
1457                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1458                           0);
1459       __ ldrb(rscratch1, data_addr);
1460       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1461       __ strb(rscratch1, data_addr);
1462       __ b(done);
1463       __ bind(not_null);
1464     } else {
1465       __ cbz(value, done);
1466     }
1467 
1468     add_debug_info_for_null_check_here(op->info_for_exception());
1469     __ load_klass(k_RInfo, array);
1470     __ load_klass(klass_RInfo, value);
1471 
1472     // get instance klass (it's already uncompressed)
1473     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1474     // perform the fast part of the checking logic
1475     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1476     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1477     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1478     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1479     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1480     // result is a boolean
1481     __ cbzw(k_RInfo, *failure_target);
1482     // fall through to the success case
1483 
1484     if (should_profile) {
1485       Register mdo  = klass_RInfo, recv = k_RInfo;
1486       __ bind(profile_cast_success);
1487       __ mov_metadata(mdo, md->constant_encoding());
1488       __ load_klass(recv, value);
1489       Label update_done;
1490       type_profile_helper(mdo, md, data, recv, &done);
1491       __ b(done);
1492 
1493       __ bind(profile_cast_failure);
1494       __ mov_metadata(mdo, md->constant_encoding());
1495       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1496       __ lea(rscratch2, counter_addr);
1497       __ ldr(rscratch1, Address(rscratch2));
1498       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1499       __ str(rscratch1, Address(rscratch2));
1500       __ b(*stub->entry());
1501     }
1502 
1503     __ bind(done);
1504   } else if (code == lir_checkcast) {
1505     Register obj = op->object()->as_register();
1506     Register dst = op->result_opr()->as_register();
1507     Label success;
1508     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1509     __ bind(success);
1510     if (dst != obj) {
1511       __ mov(dst, obj);
1512     }
1513   } else if (code == lir_instanceof) {
1514     Register obj = op->object()->as_register();
1515     Register dst = op->result_opr()->as_register();
1516     Label success, failure, done;
1517     emit_typecheck_helper(op, &success, &failure, &failure);
1518     __ bind(failure);
1519     __ mov(dst, zr);
1520     __ b(done);
1521     __ bind(success);
1522     __ mov(dst, 1);
1523     __ bind(done);
1524   } else {
1525     ShouldNotReachHere();
1526   }
1527 }
1528 
1529 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1530   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1531   __ cset(rscratch1, Assembler::NE);
1532   __ membar(__ AnyAny);
1533 }
1534 
1535 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1536   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1537   __ cset(rscratch1, Assembler::NE);
1538   __ membar(__ AnyAny);
1539 }
1540 
1541 
1542 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1543   assert(VM_Version::supports_cx8(), "wrong machine");
1544   Register addr;
1545   if (op->addr()->is_register()) {
1546     addr = as_reg(op->addr());
1547   } else {
1548     assert(op->addr()->is_address(), "what else?");
1549     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1550     assert(addr_ptr->disp() == 0, "need 0 disp");
1551     assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1552     addr = as_reg(addr_ptr->base());
1553   }
1554   Register newval = as_reg(op->new_value());
1555   Register cmpval = as_reg(op->cmp_value());
1556 
1557   if (op->code() == lir_cas_obj) {
1558     if (UseCompressedOops) {
1559       Register t1 = op->tmp1()->as_register();
1560       assert(op->tmp1()->is_valid(), "must be");
1561       __ encode_heap_oop(t1, cmpval);
1562       cmpval = t1;
1563       __ encode_heap_oop(rscratch2, newval);
1564       newval = rscratch2;
1565       casw(addr, newval, cmpval);
1566     } else {
1567       casl(addr, newval, cmpval);
1568     }
1569   } else if (op->code() == lir_cas_int) {
1570     casw(addr, newval, cmpval);
1571   } else {
1572     casl(addr, newval, cmpval);
1573   }
1574 }
1575 
1576 
1577 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1578 
1579   Assembler::Condition acond, ncond;
1580   switch (condition) {
1581   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1582   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1583   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1584   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1585   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1586   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1587   case lir_cond_belowEqual:
1588   case lir_cond_aboveEqual:
1589   default:                    ShouldNotReachHere();
1590     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1591   }
1592 
1593   assert(result->is_single_cpu() || result->is_double_cpu(),
1594          "expect single register for result");
1595   if (opr1->is_constant() && opr2->is_constant()
1596       && opr1->type() == T_INT && opr2->type() == T_INT) {
1597     jint val1 = opr1->as_jint();
1598     jint val2 = opr2->as_jint();
1599     if (val1 == 0 && val2 == 1) {
1600       __ cset(result->as_register(), ncond);
1601       return;
1602     } else if (val1 == 1 && val2 == 0) {
1603       __ cset(result->as_register(), acond);
1604       return;
1605     }
1606   }
1607 
1608   if (opr1->is_constant() && opr2->is_constant()
1609       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1610     jlong val1 = opr1->as_jlong();
1611     jlong val2 = opr2->as_jlong();
1612     if (val1 == 0 && val2 == 1) {
1613       __ cset(result->as_register_lo(), ncond);
1614       return;
1615     } else if (val1 == 1 && val2 == 0) {
1616       __ cset(result->as_register_lo(), acond);
1617       return;
1618     }
1619   }
1620 
1621   if (opr1->is_stack()) {
1622     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1623     opr1 = FrameMap::rscratch1_opr;
1624   } else if (opr1->is_constant()) {
1625     LIR_Opr tmp
1626       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1627     const2reg(opr1, tmp, lir_patch_none, NULL);
1628     opr1 = tmp;
1629   }
1630 
1631   if (opr2->is_stack()) {
1632     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1633     opr2 = FrameMap::rscratch2_opr;
1634   } else if (opr2->is_constant()) {
1635     LIR_Opr tmp
1636       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1637     const2reg(opr2, tmp, lir_patch_none, NULL);
1638     opr2 = tmp;
1639   }
1640 
1641   if (result->type() == T_LONG)
1642     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1643   else
1644     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1645 }
1646 
1647 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1648   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1649 
1650   if (left->is_single_cpu()) {
1651     Register lreg = left->as_register();
1652     Register dreg = as_reg(dest);
1653 
1654     if (right->is_single_cpu()) {
1655       // cpu register - cpu register
1656 
1657       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1658              "should be");
1659       Register rreg = right->as_register();
1660       switch (code) {
1661       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1662       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1663       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1664       default:      ShouldNotReachHere();
1665       }
1666 
1667     } else if (right->is_double_cpu()) {
1668       Register rreg = right->as_register_lo();
1669       // single_cpu + double_cpu: can happen with obj+long
1670       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1671       switch (code) {
1672       case lir_add: __ add(dreg, lreg, rreg); break;
1673       case lir_sub: __ sub(dreg, lreg, rreg); break;
1674       default: ShouldNotReachHere();
1675       }
1676     } else if (right->is_constant()) {
1677       // cpu register - constant
1678       jlong c;
1679 
1680       // FIXME.  This is fugly: we really need to factor all this logic.
1681       switch(right->type()) {
1682       case T_LONG:
1683         c = right->as_constant_ptr()->as_jlong();
1684         break;
1685       case T_INT:
1686       case T_ADDRESS:
1687         c = right->as_constant_ptr()->as_jint();
1688         break;
1689       default:
1690         ShouldNotReachHere();
1691         c = 0;  // unreachable
1692         break;
1693       }
1694 
1695       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1696       if (c == 0 && dreg == lreg) {
1697         COMMENT("effective nop elided");
1698         return;
1699       }
1700       switch(left->type()) {
1701       case T_INT:
1702         switch (code) {
1703         case lir_add: __ addw(dreg, lreg, c); break;
1704         case lir_sub: __ subw(dreg, lreg, c); break;
1705         default: ShouldNotReachHere();
1706         }
1707         break;
1708       case T_OBJECT:
1709       case T_ADDRESS:
1710         switch (code) {
1711         case lir_add: __ add(dreg, lreg, c); break;
1712         case lir_sub: __ sub(dreg, lreg, c); break;
1713         default: ShouldNotReachHere();
1714         }
1715         break;
1716       default:
1717         ShouldNotReachHere();
1718       }
1719     } else {
1720       ShouldNotReachHere();
1721     }
1722 
1723   } else if (left->is_double_cpu()) {
1724     Register lreg_lo = left->as_register_lo();
1725 
1726     if (right->is_double_cpu()) {
1727       // cpu register - cpu register
1728       Register rreg_lo = right->as_register_lo();
1729       switch (code) {
1730       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1731       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1732       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1733       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1734       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1735       default:
1736         ShouldNotReachHere();
1737       }
1738 
1739     } else if (right->is_constant()) {
1740       jlong c = right->as_constant_ptr()->as_jlong();
1741       Register dreg = as_reg(dest);
1742       switch (code) {
1743         case lir_add:
1744         case lir_sub:
1745           if (c == 0 && dreg == lreg_lo) {
1746             COMMENT("effective nop elided");
1747             return;
1748           }
1749           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1750           break;
1751         case lir_div:
1752           assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1753           if (c == 1) {
1754             // move lreg_lo to dreg if divisor is 1
1755             __ mov(dreg, lreg_lo);
1756           } else {
1757             unsigned int shift = exact_log2_long(c);
1758             // use rscratch1 as intermediate result register
1759             __ asr(rscratch1, lreg_lo, 63);
1760             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1761             __ asr(dreg, rscratch1, shift);
1762           }
1763           break;
1764         case lir_rem:
1765           assert(c > 0 && is_power_of_2_long(c), "divisor must be power-of-2 constant");
1766           if (c == 1) {
1767             // move 0 to dreg if divisor is 1
1768             __ mov(dreg, zr);
1769           } else {
1770             // use rscratch1 as intermediate result register
1771             __ negs(rscratch1, lreg_lo);
1772             __ andr(dreg, lreg_lo, c - 1);
1773             __ andr(rscratch1, rscratch1, c - 1);
1774             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1775           }
1776           break;
1777         default:
1778           ShouldNotReachHere();
1779       }
1780     } else {
1781       ShouldNotReachHere();
1782     }
1783   } else if (left->is_single_fpu()) {
1784     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1785     switch (code) {
1786     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1787     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1788     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1789     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1790     default:
1791       ShouldNotReachHere();
1792     }
1793   } else if (left->is_double_fpu()) {
1794     if (right->is_double_fpu()) {
1795       // cpu register - cpu register
1796       switch (code) {
1797       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1798       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1799       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1800       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1801       default:
1802         ShouldNotReachHere();
1803       }
1804     } else {
1805       if (right->is_constant()) {
1806         ShouldNotReachHere();
1807       }
1808       ShouldNotReachHere();
1809     }
1810   } else if (left->is_single_stack() || left->is_address()) {
1811     assert(left == dest, "left and dest must be equal");
1812     ShouldNotReachHere();
1813   } else {
1814     ShouldNotReachHere();
1815   }
1816 }
1817 
1818 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1819 
1820 
1821 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1822   switch(code) {
1823   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1824   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1825   default      : ShouldNotReachHere();
1826   }
1827 }
1828 
1829 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1830 
1831   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1832   Register Rleft = left->is_single_cpu() ? left->as_register() :
1833                                            left->as_register_lo();
1834    if (dst->is_single_cpu()) {
1835      Register Rdst = dst->as_register();
1836      if (right->is_constant()) {
1837        switch (code) {
1838          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1839          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1840          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1841          default: ShouldNotReachHere(); break;
1842        }
1843      } else {
1844        Register Rright = right->is_single_cpu() ? right->as_register() :
1845                                                   right->as_register_lo();
1846        switch (code) {
1847          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1848          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1849          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1850          default: ShouldNotReachHere(); break;
1851        }
1852      }
1853    } else {
1854      Register Rdst = dst->as_register_lo();
1855      if (right->is_constant()) {
1856        switch (code) {
1857          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1858          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1859          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1860          default: ShouldNotReachHere(); break;
1861        }
1862      } else {
1863        Register Rright = right->is_single_cpu() ? right->as_register() :
1864                                                   right->as_register_lo();
1865        switch (code) {
1866          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1867          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1868          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1869          default: ShouldNotReachHere(); break;
1870        }
1871      }
1872    }
1873 }
1874 
1875 
1876 
1877 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1878 
1879   // opcode check
1880   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1881   bool is_irem = (code == lir_irem);
1882 
1883   // operand check
1884   assert(left->is_single_cpu(),   "left must be register");
1885   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1886   assert(result->is_single_cpu(), "result must be register");
1887   Register lreg = left->as_register();
1888   Register dreg = result->as_register();
1889 
1890   // power-of-2 constant check and codegen
1891   if (right->is_constant()) {
1892     int c = right->as_constant_ptr()->as_jint();
1893     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1894     if (is_irem) {
1895       if (c == 1) {
1896         // move 0 to dreg if divisor is 1
1897         __ movw(dreg, zr);
1898       } else {
1899         // use rscratch1 as intermediate result register
1900         __ negsw(rscratch1, lreg);
1901         __ andw(dreg, lreg, c - 1);
1902         __ andw(rscratch1, rscratch1, c - 1);
1903         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1904       }
1905     } else {
1906       if (c == 1) {
1907         // move lreg to dreg if divisor is 1
1908         __ movw(dreg, lreg);
1909       } else {
1910         unsigned int shift = exact_log2(c);
1911         // use rscratch1 as intermediate result register
1912         __ asrw(rscratch1, lreg, 31);
1913         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1914         __ asrw(dreg, rscratch1, shift);
1915       }
1916     }
1917   } else {
1918     Register rreg = right->as_register();
1919     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1920   }
1921 }
1922 
1923 
1924 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1925   if (opr1->is_constant() && opr2->is_single_cpu()) {
1926     // tableswitch
1927     Register reg = as_reg(opr2);
1928     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1929     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1930   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1931     Register reg1 = as_reg(opr1);
1932     if (opr2->is_single_cpu()) {
1933       // cpu register - cpu register
1934       Register reg2 = opr2->as_register();
1935       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1936         __ cmpoop(reg1, reg2);
1937       } else {
1938         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1939         __ cmpw(reg1, reg2);
1940       }
1941       return;
1942     }
1943     if (opr2->is_double_cpu()) {
1944       // cpu register - cpu register
1945       Register reg2 = opr2->as_register_lo();
1946       __ cmp(reg1, reg2);
1947       return;
1948     }
1949 
1950     if (opr2->is_constant()) {
1951       bool is_32bit = false; // width of register operand
1952       jlong imm;
1953 
1954       switch(opr2->type()) {
1955       case T_INT:
1956         imm = opr2->as_constant_ptr()->as_jint();
1957         is_32bit = true;
1958         break;
1959       case T_LONG:
1960         imm = opr2->as_constant_ptr()->as_jlong();
1961         break;
1962       case T_ADDRESS:
1963         imm = opr2->as_constant_ptr()->as_jint();
1964         break;
1965       case T_OBJECT:
1966       case T_ARRAY:
1967         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1968         __ cmpoop(reg1, rscratch1);
1969         return;
1970       default:
1971         ShouldNotReachHere();
1972         imm = 0;  // unreachable
1973         break;
1974       }
1975 
1976       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1977         if (is_32bit)
1978           __ cmpw(reg1, imm);
1979         else
1980           __ subs(zr, reg1, imm);
1981         return;
1982       } else {
1983         __ mov(rscratch1, imm);
1984         if (is_32bit)
1985           __ cmpw(reg1, rscratch1);
1986         else
1987           __ cmp(reg1, rscratch1);
1988         return;
1989       }
1990     } else
1991       ShouldNotReachHere();
1992   } else if (opr1->is_single_fpu()) {
1993     FloatRegister reg1 = opr1->as_float_reg();
1994     assert(opr2->is_single_fpu(), "expect single float register");
1995     FloatRegister reg2 = opr2->as_float_reg();
1996     __ fcmps(reg1, reg2);
1997   } else if (opr1->is_double_fpu()) {
1998     FloatRegister reg1 = opr1->as_double_reg();
1999     assert(opr2->is_double_fpu(), "expect double float register");
2000     FloatRegister reg2 = opr2->as_double_reg();
2001     __ fcmpd(reg1, reg2);
2002   } else {
2003     ShouldNotReachHere();
2004   }
2005 }
2006 
2007 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2008   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2009     bool is_unordered_less = (code == lir_ucmp_fd2i);
2010     if (left->is_single_fpu()) {
2011       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2012     } else if (left->is_double_fpu()) {
2013       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2014     } else {
2015       ShouldNotReachHere();
2016     }
2017   } else if (code == lir_cmp_l2i) {
2018     Label done;
2019     __ cmp(left->as_register_lo(), right->as_register_lo());
2020     __ mov(dst->as_register(), (u_int64_t)-1L);
2021     __ br(Assembler::LT, done);
2022     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2023     __ bind(done);
2024   } else {
2025     ShouldNotReachHere();
2026   }
2027 }
2028 
2029 
2030 void LIR_Assembler::align_call(LIR_Code code) {  }
2031 
2032 
2033 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2034   address call = __ trampoline_call(Address(op->addr(), rtype));
2035   if (call == NULL) {
2036     bailout("trampoline stub overflow");
2037     return;
2038   }
2039   add_call_info(code_offset(), op->info());
2040 }
2041 
2042 
2043 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2044   address call = __ ic_call(op->addr());
2045   if (call == NULL) {
2046     bailout("trampoline stub overflow");
2047     return;
2048   }
2049   add_call_info(code_offset(), op->info());
2050 }
2051 
2052 
2053 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2054 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2055   ShouldNotReachHere();
2056 }
2057 
2058 
2059 void LIR_Assembler::emit_static_call_stub() {
2060   address call_pc = __ pc();
2061   address stub = __ start_a_stub(call_stub_size());
2062   if (stub == NULL) {
2063     bailout("static call stub overflow");
2064     return;
2065   }
2066 
2067   int start = __ offset();
2068 
2069   __ relocate(static_stub_Relocation::spec(call_pc));
2070   __ emit_static_call_stub();
2071 
2072   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2073         <= call_stub_size(), "stub too big");
2074   __ end_a_stub();
2075 }
2076 
2077 
2078 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2079   assert(exceptionOop->as_register() == r0, "must match");
2080   assert(exceptionPC->as_register() == r3, "must match");
2081 
2082   // exception object is not added to oop map by LinearScan
2083   // (LinearScan assumes that no oops are in fixed registers)
2084   info->add_register_oop(exceptionOop);
2085   Runtime1::StubID unwind_id;
2086 
2087   // get current pc information
2088   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2089   int pc_for_athrow_offset = __ offset();
2090   InternalAddress pc_for_athrow(__ pc());
2091   __ adr(exceptionPC->as_register(), pc_for_athrow);
2092   add_call_info(pc_for_athrow_offset, info); // for exception handler
2093 
2094   __ verify_not_null_oop(r0);
2095   // search an exception handler (r0: exception oop, r3: throwing pc)
2096   if (compilation()->has_fpu_code()) {
2097     unwind_id = Runtime1::handle_exception_id;
2098   } else {
2099     unwind_id = Runtime1::handle_exception_nofpu_id;
2100   }
2101   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2102 
2103   // FIXME: enough room for two byte trap   ????
2104   __ nop();
2105 }
2106 
2107 
2108 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2109   assert(exceptionOop->as_register() == r0, "must match");
2110 
2111   __ b(_unwind_handler_entry);
2112 }
2113 
2114 
2115 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2116   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2117   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2118 
2119   switch (left->type()) {
2120     case T_INT: {
2121       switch (code) {
2122       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2123       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2124       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2125       default:
2126         ShouldNotReachHere();
2127         break;
2128       }
2129       break;
2130     case T_LONG:
2131     case T_ADDRESS:
2132     case T_OBJECT:
2133       switch (code) {
2134       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2135       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2136       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2137       default:
2138         ShouldNotReachHere();
2139         break;
2140       }
2141       break;
2142     default:
2143       ShouldNotReachHere();
2144       break;
2145     }
2146   }
2147 }
2148 
2149 
2150 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2151   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2152   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2153 
2154   switch (left->type()) {
2155     case T_INT: {
2156       switch (code) {
2157       case lir_shl:  __ lslw (dreg, lreg, count); break;
2158       case lir_shr:  __ asrw (dreg, lreg, count); break;
2159       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2160       default:
2161         ShouldNotReachHere();
2162         break;
2163       }
2164       break;
2165     case T_LONG:
2166     case T_ADDRESS:
2167     case T_OBJECT:
2168       switch (code) {
2169       case lir_shl:  __ lsl (dreg, lreg, count); break;
2170       case lir_shr:  __ asr (dreg, lreg, count); break;
2171       case lir_ushr: __ lsr (dreg, lreg, count); break;
2172       default:
2173         ShouldNotReachHere();
2174         break;
2175       }
2176       break;
2177     default:
2178       ShouldNotReachHere();
2179       break;
2180     }
2181   }
2182 }
2183 
2184 
2185 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2186   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2187   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2188   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2189   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2190 }
2191 
2192 
2193 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2194   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2195   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2196   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2197   __ mov (rscratch1, c);
2198   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2199 }
2200 
2201 
2202 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2203   ShouldNotReachHere();
2204   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2205   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2206   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2207   __ lea(rscratch1, __ constant_oop_address(o));
2208   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2209 }
2210 
2211 
2212 // This code replaces a call to arraycopy; no exception may
2213 // be thrown in this code, they must be thrown in the System.arraycopy
2214 // activation frame; we could save some checks if this would not be the case
2215 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2216   ciArrayKlass* default_type = op->expected_type();
2217   Register src = op->src()->as_register();
2218   Register dst = op->dst()->as_register();
2219   Register src_pos = op->src_pos()->as_register();
2220   Register dst_pos = op->dst_pos()->as_register();
2221   Register length  = op->length()->as_register();
2222   Register tmp = op->tmp()->as_register();
2223 
2224   __ resolve(ACCESS_READ, src);
2225   __ resolve(ACCESS_WRITE, dst);
2226 
2227   CodeStub* stub = op->stub();
2228   int flags = op->flags();
2229   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2230   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2231 
2232   // if we don't know anything, just go through the generic arraycopy
2233   if (default_type == NULL // || basic_type == T_OBJECT
2234       ) {
2235     Label done;
2236     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2237 
2238     // Save the arguments in case the generic arraycopy fails and we
2239     // have to fall back to the JNI stub
2240     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2241     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2242     __ str(src,              Address(sp, 4*BytesPerWord));
2243 
2244     address copyfunc_addr = StubRoutines::generic_arraycopy();
2245     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2246 
2247     // The arguments are in java calling convention so we shift them
2248     // to C convention
2249     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2250     __ mov(c_rarg0, j_rarg0);
2251     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2252     __ mov(c_rarg1, j_rarg1);
2253     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2254     __ mov(c_rarg2, j_rarg2);
2255     assert_different_registers(c_rarg3, j_rarg4);
2256     __ mov(c_rarg3, j_rarg3);
2257     __ mov(c_rarg4, j_rarg4);
2258 #ifndef PRODUCT
2259     if (PrintC1Statistics) {
2260       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2261     }
2262 #endif
2263     __ far_call(RuntimeAddress(copyfunc_addr));
2264 
2265     __ cbz(r0, *stub->continuation());
2266 
2267     // Reload values from the stack so they are where the stub
2268     // expects them.
2269     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2270     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2271     __ ldr(src,              Address(sp, 4*BytesPerWord));
2272 
2273     // r0 is -1^K where K == partial copied count
2274     __ eonw(rscratch1, r0, 0);
2275     // adjust length down and src/end pos up by partial copied count
2276     __ subw(length, length, rscratch1);
2277     __ addw(src_pos, src_pos, rscratch1);
2278     __ addw(dst_pos, dst_pos, rscratch1);
2279     __ b(*stub->entry());
2280 
2281     __ bind(*stub->continuation());
2282     return;
2283   }
2284 
2285   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2286 
2287   int elem_size = type2aelembytes(basic_type);
2288   int shift_amount;
2289   int scale = exact_log2(elem_size);
2290 
2291   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2292   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2293   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2294   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2295 
2296   // test for NULL
2297   if (flags & LIR_OpArrayCopy::src_null_check) {
2298     __ cbz(src, *stub->entry());
2299   }
2300   if (flags & LIR_OpArrayCopy::dst_null_check) {
2301     __ cbz(dst, *stub->entry());
2302   }
2303 
2304   // If the compiler was not able to prove that exact type of the source or the destination
2305   // of the arraycopy is an array type, check at runtime if the source or the destination is
2306   // an instance type.
2307   if (flags & LIR_OpArrayCopy::type_check) {
2308     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2309       __ load_klass(tmp, dst);
2310       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2311       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2312       __ br(Assembler::GE, *stub->entry());
2313     }
2314 
2315     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2316       __ load_klass(tmp, src);
2317       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2318       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2319       __ br(Assembler::GE, *stub->entry());
2320     }
2321   }
2322 
2323   // check if negative
2324   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2325     __ cmpw(src_pos, 0);
2326     __ br(Assembler::LT, *stub->entry());
2327   }
2328   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2329     __ cmpw(dst_pos, 0);
2330     __ br(Assembler::LT, *stub->entry());
2331   }
2332 
2333   if (flags & LIR_OpArrayCopy::length_positive_check) {
2334     __ cmpw(length, 0);
2335     __ br(Assembler::LT, *stub->entry());
2336   }
2337 
2338   if (flags & LIR_OpArrayCopy::src_range_check) {
2339     __ addw(tmp, src_pos, length);
2340     __ ldrw(rscratch1, src_length_addr);
2341     __ cmpw(tmp, rscratch1);
2342     __ br(Assembler::HI, *stub->entry());
2343   }
2344   if (flags & LIR_OpArrayCopy::dst_range_check) {
2345     __ addw(tmp, dst_pos, length);
2346     __ ldrw(rscratch1, dst_length_addr);
2347     __ cmpw(tmp, rscratch1);
2348     __ br(Assembler::HI, *stub->entry());
2349   }
2350 
2351   if (flags & LIR_OpArrayCopy::type_check) {
2352     // We don't know the array types are compatible
2353     if (basic_type != T_OBJECT) {
2354       // Simple test for basic type arrays
2355       if (UseCompressedClassPointers) {
2356         __ ldrw(tmp, src_klass_addr);
2357         __ ldrw(rscratch1, dst_klass_addr);
2358         __ cmpw(tmp, rscratch1);
2359       } else {
2360         __ ldr(tmp, src_klass_addr);
2361         __ ldr(rscratch1, dst_klass_addr);
2362         __ cmp(tmp, rscratch1);
2363       }
2364       __ br(Assembler::NE, *stub->entry());
2365     } else {
2366       // For object arrays, if src is a sub class of dst then we can
2367       // safely do the copy.
2368       Label cont, slow;
2369 
2370 #define PUSH(r1, r2)                                    \
2371       stp(r1, r2, __ pre(sp, -2 * wordSize));
2372 
2373 #define POP(r1, r2)                                     \
2374       ldp(r1, r2, __ post(sp, 2 * wordSize));
2375 
2376       __ PUSH(src, dst);
2377 
2378       __ load_klass(src, src);
2379       __ load_klass(dst, dst);
2380 
2381       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2382 
2383       __ PUSH(src, dst);
2384       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2385       __ POP(src, dst);
2386 
2387       __ cbnz(src, cont);
2388 
2389       __ bind(slow);
2390       __ POP(src, dst);
2391 
2392       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2393       if (copyfunc_addr != NULL) { // use stub if available
2394         // src is not a sub class of dst so we have to do a
2395         // per-element check.
2396 
2397         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2398         if ((flags & mask) != mask) {
2399           // Check that at least both of them object arrays.
2400           assert(flags & mask, "one of the two should be known to be an object array");
2401 
2402           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2403             __ load_klass(tmp, src);
2404           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2405             __ load_klass(tmp, dst);
2406           }
2407           int lh_offset = in_bytes(Klass::layout_helper_offset());
2408           Address klass_lh_addr(tmp, lh_offset);
2409           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2410           __ ldrw(rscratch1, klass_lh_addr);
2411           __ mov(rscratch2, objArray_lh);
2412           __ eorw(rscratch1, rscratch1, rscratch2);
2413           __ cbnzw(rscratch1, *stub->entry());
2414         }
2415 
2416        // Spill because stubs can use any register they like and it's
2417        // easier to restore just those that we care about.
2418         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2419         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2420         __ str(src,              Address(sp, 4*BytesPerWord));
2421 
2422         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2423         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2424         assert_different_registers(c_rarg0, dst, dst_pos, length);
2425         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2426         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2427         assert_different_registers(c_rarg1, dst, length);
2428         __ uxtw(c_rarg2, length);
2429         assert_different_registers(c_rarg2, dst);
2430 
2431         __ load_klass(c_rarg4, dst);
2432         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2433         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2434         __ far_call(RuntimeAddress(copyfunc_addr));
2435 
2436 #ifndef PRODUCT
2437         if (PrintC1Statistics) {
2438           Label failed;
2439           __ cbnz(r0, failed);
2440           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2441           __ bind(failed);
2442         }
2443 #endif
2444 
2445         __ cbz(r0, *stub->continuation());
2446 
2447 #ifndef PRODUCT
2448         if (PrintC1Statistics) {
2449           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2450         }
2451 #endif
2452         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2453 
2454         // Restore previously spilled arguments
2455         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2456         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2457         __ ldr(src,              Address(sp, 4*BytesPerWord));
2458 
2459         // return value is -1^K where K is partial copied count
2460         __ eonw(rscratch1, r0, zr);
2461         // adjust length down and src/end pos up by partial copied count
2462         __ subw(length, length, rscratch1);
2463         __ addw(src_pos, src_pos, rscratch1);
2464         __ addw(dst_pos, dst_pos, rscratch1);
2465       }
2466 
2467       __ b(*stub->entry());
2468 
2469       __ bind(cont);
2470       __ POP(src, dst);
2471     }
2472   }
2473 
2474 #ifdef ASSERT
2475   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2476     // Sanity check the known type with the incoming class.  For the
2477     // primitive case the types must match exactly with src.klass and
2478     // dst.klass each exactly matching the default type.  For the
2479     // object array case, if no type check is needed then either the
2480     // dst type is exactly the expected type and the src type is a
2481     // subtype which we can't check or src is the same array as dst
2482     // but not necessarily exactly of type default_type.
2483     Label known_ok, halt;
2484     __ mov_metadata(tmp, default_type->constant_encoding());
2485     if (UseCompressedClassPointers) {
2486       __ encode_klass_not_null(tmp);
2487     }
2488 
2489     if (basic_type != T_OBJECT) {
2490 
2491       if (UseCompressedClassPointers) {
2492         __ ldrw(rscratch1, dst_klass_addr);
2493         __ cmpw(tmp, rscratch1);
2494       } else {
2495         __ ldr(rscratch1, dst_klass_addr);
2496         __ cmp(tmp, rscratch1);
2497       }
2498       __ br(Assembler::NE, halt);
2499       if (UseCompressedClassPointers) {
2500         __ ldrw(rscratch1, src_klass_addr);
2501         __ cmpw(tmp, rscratch1);
2502       } else {
2503         __ ldr(rscratch1, src_klass_addr);
2504         __ cmp(tmp, rscratch1);
2505       }
2506       __ br(Assembler::EQ, known_ok);
2507     } else {
2508       if (UseCompressedClassPointers) {
2509         __ ldrw(rscratch1, dst_klass_addr);
2510         __ cmpw(tmp, rscratch1);
2511       } else {
2512         __ ldr(rscratch1, dst_klass_addr);
2513         __ cmp(tmp, rscratch1);
2514       }
2515       __ br(Assembler::EQ, known_ok);
2516       __ cmp(src, dst);
2517       __ br(Assembler::EQ, known_ok);
2518     }
2519     __ bind(halt);
2520     __ stop("incorrect type information in arraycopy");
2521     __ bind(known_ok);
2522   }
2523 #endif
2524 
2525 #ifndef PRODUCT
2526   if (PrintC1Statistics) {
2527     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2528   }
2529 #endif
2530 
2531   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2532   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2533   assert_different_registers(c_rarg0, dst, dst_pos, length);
2534   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2535   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2536   assert_different_registers(c_rarg1, dst, length);
2537   __ uxtw(c_rarg2, length);
2538   assert_different_registers(c_rarg2, dst);
2539 
2540   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2541   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2542   const char *name;
2543   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2544 
2545  CodeBlob *cb = CodeCache::find_blob(entry);
2546  if (cb) {
2547    __ far_call(RuntimeAddress(entry));
2548  } else {
2549    __ call_VM_leaf(entry, 3);
2550  }
2551 
2552   __ bind(*stub->continuation());
2553 }
2554 
2555 
2556 
2557 
2558 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2559   Register obj = op->obj_opr()->as_register();  // may not be an oop
2560   Register hdr = op->hdr_opr()->as_register();
2561   Register lock = op->lock_opr()->as_register();
2562   if (!UseFastLocking) {
2563     __ b(*op->stub()->entry());
2564   } else if (op->code() == lir_lock) {
2565     Register scratch = noreg;
2566     if (UseBiasedLocking) {
2567       scratch = op->scratch_opr()->as_register();
2568     }
2569     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2570     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2571     // add debug info for NullPointerException only if one is possible
2572     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
2573     if (op->info() != NULL) {
2574       add_debug_info_for_null_check(null_check_offset, op->info());
2575     }
2576     // done
2577   } else if (op->code() == lir_unlock) {
2578     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2579     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2580   } else {
2581     Unimplemented();
2582   }
2583   __ bind(*op->stub()->continuation());
2584 }
2585 
2586 
2587 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2588   ciMethod* method = op->profiled_method();
2589   int bci          = op->profiled_bci();
2590   ciMethod* callee = op->profiled_callee();
2591 
2592   // Update counter for all call types
2593   ciMethodData* md = method->method_data_or_null();
2594   assert(md != NULL, "Sanity");
2595   ciProfileData* data = md->bci_to_data(bci);
2596   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2597   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2598   Register mdo  = op->mdo()->as_register();
2599   __ mov_metadata(mdo, md->constant_encoding());
2600   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2601   // Perform additional virtual call profiling for invokevirtual and
2602   // invokeinterface bytecodes
2603   if (op->should_profile_receiver_type()) {
2604     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2605     Register recv = op->recv()->as_register();
2606     assert_different_registers(mdo, recv);
2607     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2608     ciKlass* known_klass = op->known_holder();
2609     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2610       // We know the type that will be seen at this call site; we can
2611       // statically update the MethodData* rather than needing to do
2612       // dynamic tests on the receiver type
2613 
2614       // NOTE: we should probably put a lock around this search to
2615       // avoid collisions by concurrent compilations
2616       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2617       uint i;
2618       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2619         ciKlass* receiver = vc_data->receiver(i);
2620         if (known_klass->equals(receiver)) {
2621           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2622           __ addptr(data_addr, DataLayout::counter_increment);
2623           return;
2624         }
2625       }
2626 
2627       // Receiver type not found in profile data; select an empty slot
2628 
2629       // Note that this is less efficient than it should be because it
2630       // always does a write to the receiver part of the
2631       // VirtualCallData rather than just the first time
2632       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2633         ciKlass* receiver = vc_data->receiver(i);
2634         if (receiver == NULL) {
2635           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2636           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2637           __ lea(rscratch2, recv_addr);
2638           __ str(rscratch1, Address(rscratch2));
2639           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2640           __ addptr(data_addr, DataLayout::counter_increment);
2641           return;
2642         }
2643       }
2644     } else {
2645       __ load_klass(recv, recv);
2646       Label update_done;
2647       type_profile_helper(mdo, md, data, recv, &update_done);
2648       // Receiver did not match any saved receiver and there is no empty row for it.
2649       // Increment total counter to indicate polymorphic case.
2650       __ addptr(counter_addr, DataLayout::counter_increment);
2651 
2652       __ bind(update_done);
2653     }
2654   } else {
2655     // Static call
2656     __ addptr(counter_addr, DataLayout::counter_increment);
2657   }
2658 }
2659 
2660 
2661 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2662   Unimplemented();
2663 }
2664 
2665 
2666 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2667   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2668 }
2669 
2670 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2671   assert(op->crc()->is_single_cpu(),  "crc must be register");
2672   assert(op->val()->is_single_cpu(),  "byte value must be register");
2673   assert(op->result_opr()->is_single_cpu(), "result must be register");
2674   Register crc = op->crc()->as_register();
2675   Register val = op->val()->as_register();
2676   Register res = op->result_opr()->as_register();
2677 
2678   assert_different_registers(val, crc, res);
2679   unsigned long offset;
2680   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2681   if (offset) __ add(res, res, offset);
2682 
2683   __ mvnw(crc, crc); // ~crc
2684   __ update_byte_crc32(crc, val, res);
2685   __ mvnw(res, crc); // ~crc
2686 }
2687 
2688 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2689   COMMENT("emit_profile_type {");
2690   Register obj = op->obj()->as_register();
2691   Register tmp = op->tmp()->as_pointer_register();
2692   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2693   ciKlass* exact_klass = op->exact_klass();
2694   intptr_t current_klass = op->current_klass();
2695   bool not_null = op->not_null();
2696   bool no_conflict = op->no_conflict();
2697 
2698   Label update, next, none;
2699 
2700   bool do_null = !not_null;
2701   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2702   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2703 
2704   assert(do_null || do_update, "why are we here?");
2705   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2706   assert(mdo_addr.base() != rscratch1, "wrong register");
2707 
2708   __ verify_oop(obj);
2709 
2710   if (tmp != obj) {
2711     __ mov(tmp, obj);
2712   }
2713   if (do_null) {
2714     __ cbnz(tmp, update);
2715     if (!TypeEntries::was_null_seen(current_klass)) {
2716       __ ldr(rscratch2, mdo_addr);
2717       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2718       __ str(rscratch2, mdo_addr);
2719     }
2720     if (do_update) {
2721 #ifndef ASSERT
2722       __ b(next);
2723     }
2724 #else
2725       __ b(next);
2726     }
2727   } else {
2728     __ cbnz(tmp, update);
2729     __ stop("unexpected null obj");
2730 #endif
2731   }
2732 
2733   __ bind(update);
2734 
2735   if (do_update) {
2736 #ifdef ASSERT
2737     if (exact_klass != NULL) {
2738       Label ok;
2739       __ load_klass(tmp, tmp);
2740       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2741       __ eor(rscratch1, tmp, rscratch1);
2742       __ cbz(rscratch1, ok);
2743       __ stop("exact klass and actual klass differ");
2744       __ bind(ok);
2745     }
2746 #endif
2747     if (!no_conflict) {
2748       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2749         if (exact_klass != NULL) {
2750           __ mov_metadata(tmp, exact_klass->constant_encoding());
2751         } else {
2752           __ load_klass(tmp, tmp);
2753         }
2754 
2755         __ ldr(rscratch2, mdo_addr);
2756         __ eor(tmp, tmp, rscratch2);
2757         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2758         // klass seen before, nothing to do. The unknown bit may have been
2759         // set already but no need to check.
2760         __ cbz(rscratch1, next);
2761 
2762         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2763 
2764         if (TypeEntries::is_type_none(current_klass)) {
2765           __ cbz(rscratch2, none);
2766           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2767           __ br(Assembler::EQ, none);
2768           // There is a chance that the checks above (re-reading profiling
2769           // data from memory) fail if another thread has just set the
2770           // profiling to this obj's klass
2771           __ dmb(Assembler::ISHLD);
2772           __ ldr(rscratch2, mdo_addr);
2773           __ eor(tmp, tmp, rscratch2);
2774           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2775           __ cbz(rscratch1, next);
2776         }
2777       } else {
2778         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2779                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2780 
2781         __ ldr(tmp, mdo_addr);
2782         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2783       }
2784 
2785       // different than before. Cannot keep accurate profile.
2786       __ ldr(rscratch2, mdo_addr);
2787       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2788       __ str(rscratch2, mdo_addr);
2789 
2790       if (TypeEntries::is_type_none(current_klass)) {
2791         __ b(next);
2792 
2793         __ bind(none);
2794         // first time here. Set profile type.
2795         __ str(tmp, mdo_addr);
2796       }
2797     } else {
2798       // There's a single possible klass at this profile point
2799       assert(exact_klass != NULL, "should be");
2800       if (TypeEntries::is_type_none(current_klass)) {
2801         __ mov_metadata(tmp, exact_klass->constant_encoding());
2802         __ ldr(rscratch2, mdo_addr);
2803         __ eor(tmp, tmp, rscratch2);
2804         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2805         __ cbz(rscratch1, next);
2806 #ifdef ASSERT
2807         {
2808           Label ok;
2809           __ ldr(rscratch1, mdo_addr);
2810           __ cbz(rscratch1, ok);
2811           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2812           __ br(Assembler::EQ, ok);
2813           // may have been set by another thread
2814           __ dmb(Assembler::ISHLD);
2815           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2816           __ ldr(rscratch2, mdo_addr);
2817           __ eor(rscratch2, rscratch1, rscratch2);
2818           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2819           __ cbz(rscratch2, ok);
2820 
2821           __ stop("unexpected profiling mismatch");
2822           __ bind(ok);
2823         }
2824 #endif
2825         // first time here. Set profile type.
2826         __ ldr(tmp, mdo_addr);
2827       } else {
2828         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2829                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2830 
2831         __ ldr(tmp, mdo_addr);
2832         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2833 
2834         __ orr(tmp, tmp, TypeEntries::type_unknown);
2835         __ str(tmp, mdo_addr);
2836         // FIXME: Write barrier needed here?
2837       }
2838     }
2839 
2840     __ bind(next);
2841   }
2842   COMMENT("} emit_profile_type");
2843 }
2844 
2845 
2846 void LIR_Assembler::align_backward_branch_target() {
2847 }
2848 
2849 
2850 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2851   // tmp must be unused
2852   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2853 
2854   if (left->is_single_cpu()) {
2855     assert(dest->is_single_cpu(), "expect single result reg");
2856     __ negw(dest->as_register(), left->as_register());
2857   } else if (left->is_double_cpu()) {
2858     assert(dest->is_double_cpu(), "expect double result reg");
2859     __ neg(dest->as_register_lo(), left->as_register_lo());
2860   } else if (left->is_single_fpu()) {
2861     assert(dest->is_single_fpu(), "expect single float result reg");
2862     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2863   } else {
2864     assert(left->is_double_fpu(), "expect double float operand reg");
2865     assert(dest->is_double_fpu(), "expect double float result reg");
2866     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2867   }
2868 }
2869 
2870 
2871 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2872   assert(patch_code == lir_patch_none, "Patch code not supported");
2873   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2874 }
2875 
2876 
2877 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2878   assert(!tmp->is_valid(), "don't need temporary");
2879 
2880   CodeBlob *cb = CodeCache::find_blob(dest);
2881   if (cb) {
2882     __ far_call(RuntimeAddress(dest));
2883   } else {
2884     __ mov(rscratch1, RuntimeAddress(dest));
2885     int len = args->length();
2886     int type = 0;
2887     if (! result->is_illegal()) {
2888       switch (result->type()) {
2889       case T_VOID:
2890         type = 0;
2891         break;
2892       case T_INT:
2893       case T_LONG:
2894       case T_OBJECT:
2895         type = 1;
2896         break;
2897       case T_FLOAT:
2898         type = 2;
2899         break;
2900       case T_DOUBLE:
2901         type = 3;
2902         break;
2903       default:
2904         ShouldNotReachHere();
2905         break;
2906       }
2907     }
2908     int num_gpargs = 0;
2909     int num_fpargs = 0;
2910     for (int i = 0; i < args->length(); i++) {
2911       LIR_Opr arg = args->at(i);
2912       if (arg->type() == T_FLOAT || arg->type() == T_DOUBLE) {
2913         num_fpargs++;
2914       } else {
2915         num_gpargs++;
2916       }
2917     }
2918     __ blrt(rscratch1, num_gpargs, num_fpargs, type);
2919   }
2920 
2921   if (info != NULL) {
2922     add_call_info_here(info);
2923   }
2924   __ maybe_isb();
2925 }
2926 
2927 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2928   if (dest->is_address() || src->is_address()) {
2929     move_op(src, dest, type, lir_patch_none, info,
2930             /*pop_fpu_stack*/false, /*unaligned*/false, /*wide*/false);
2931   } else {
2932     ShouldNotReachHere();
2933   }
2934 }
2935 
2936 #ifdef ASSERT
2937 // emit run-time assertion
2938 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2939   assert(op->code() == lir_assert, "must be");
2940 
2941   if (op->in_opr1()->is_valid()) {
2942     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2943     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2944   } else {
2945     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2946     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2947   }
2948 
2949   Label ok;
2950   if (op->condition() != lir_cond_always) {
2951     Assembler::Condition acond = Assembler::AL;
2952     switch (op->condition()) {
2953       case lir_cond_equal:        acond = Assembler::EQ;  break;
2954       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2955       case lir_cond_less:         acond = Assembler::LT;  break;
2956       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2957       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2958       case lir_cond_greater:      acond = Assembler::GT;  break;
2959       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2960       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2961       default:                    ShouldNotReachHere();
2962     }
2963     __ br(acond, ok);
2964   }
2965   if (op->halt()) {
2966     const char* str = __ code_string(op->msg());
2967     __ stop(str);
2968   } else {
2969     breakpoint();
2970   }
2971   __ bind(ok);
2972 }
2973 #endif
2974 
2975 #ifndef PRODUCT
2976 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2977 #else
2978 #define COMMENT(x)
2979 #endif
2980 
2981 void LIR_Assembler::membar() {
2982   COMMENT("membar");
2983   __ membar(MacroAssembler::AnyAny);
2984 }
2985 
2986 void LIR_Assembler::membar_acquire() {
2987   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2988 }
2989 
2990 void LIR_Assembler::membar_release() {
2991   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2992 }
2993 
2994 void LIR_Assembler::membar_loadload() {
2995   __ membar(Assembler::LoadLoad);
2996 }
2997 
2998 void LIR_Assembler::membar_storestore() {
2999   __ membar(MacroAssembler::StoreStore);
3000 }
3001 
3002 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3003 
3004 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3005 
3006 void LIR_Assembler::on_spin_wait() {
3007   Unimplemented();
3008 }
3009 
3010 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3011   __ mov(result_reg->as_register(), rthread);
3012 }
3013 
3014 
3015 void LIR_Assembler::peephole(LIR_List *lir) {
3016 #if 0
3017   if (tableswitch_count >= max_tableswitches)
3018     return;
3019 
3020   /*
3021     This finite-state automaton recognizes sequences of compare-and-
3022     branch instructions.  We will turn them into a tableswitch.  You
3023     could argue that C1 really shouldn't be doing this sort of
3024     optimization, but without it the code is really horrible.
3025   */
3026 
3027   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3028   int first_key, last_key = -2147483648;
3029   int next_key = 0;
3030   int start_insn = -1;
3031   int last_insn = -1;
3032   Register reg = noreg;
3033   LIR_Opr reg_opr;
3034   state = start_s;
3035 
3036   LIR_OpList* inst = lir->instructions_list();
3037   for (int i = 0; i < inst->length(); i++) {
3038     LIR_Op* op = inst->at(i);
3039     switch (state) {
3040     case start_s:
3041       first_key = -1;
3042       start_insn = i;
3043       switch (op->code()) {
3044       case lir_cmp:
3045         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3046         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3047         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3048             && opr2->is_constant()
3049             && opr2->type() == T_INT) {
3050           reg_opr = opr1;
3051           reg = opr1->as_register();
3052           first_key = opr2->as_constant_ptr()->as_jint();
3053           next_key = first_key + 1;
3054           state = cmp_s;
3055           goto next_state;
3056         }
3057         break;
3058       }
3059       break;
3060     case cmp_s:
3061       switch (op->code()) {
3062       case lir_branch:
3063         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3064           state = beq_s;
3065           last_insn = i;
3066           goto next_state;
3067         }
3068       }
3069       state = start_s;
3070       break;
3071     case beq_s:
3072       switch (op->code()) {
3073       case lir_cmp: {
3074         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3075         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3076         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3077             && opr1->as_register() == reg
3078             && opr2->is_constant()
3079             && opr2->type() == T_INT
3080             && opr2->as_constant_ptr()->as_jint() == next_key) {
3081           last_key = next_key;
3082           next_key++;
3083           state = cmp_s;
3084           goto next_state;
3085         }
3086       }
3087       }
3088       last_key = next_key;
3089       state = start_s;
3090       break;
3091     default:
3092       assert(false, "impossible state");
3093     }
3094     if (state == start_s) {
3095       if (first_key < last_key - 5L && reg != noreg) {
3096         {
3097           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3098           //        reg->encoding(),
3099           //        start_insn, first_key, last_key);
3100           //   for (int i = 0; i < inst->length(); i++) {
3101           //     inst->at(i)->print();
3102           //     tty->print("\n");
3103           //   }
3104           //   tty->print("\n");
3105         }
3106 
3107         struct tableswitch *sw = &switches[tableswitch_count];
3108         sw->_insn_index = start_insn, sw->_first_key = first_key,
3109           sw->_last_key = last_key, sw->_reg = reg;
3110         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3111         {
3112           // Insert the new table of branches
3113           int offset = last_insn;
3114           for (int n = first_key; n < last_key; n++) {
3115             inst->insert_before
3116               (last_insn + 1,
3117                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3118                                 inst->at(offset)->as_OpBranch()->label()));
3119             offset -= 2, i++;
3120           }
3121         }
3122         // Delete all the old compare-and-branch instructions
3123         for (int n = first_key; n < last_key; n++) {
3124           inst->remove_at(start_insn);
3125           inst->remove_at(start_insn);
3126         }
3127         // Insert the tableswitch instruction
3128         inst->insert_before(start_insn,
3129                             new LIR_Op2(lir_cmp, lir_cond_always,
3130                                         LIR_OprFact::intConst(tableswitch_count),
3131                                         reg_opr));
3132         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3133         tableswitch_count++;
3134       }
3135       reg = noreg;
3136       last_key = -2147483648;
3137     }
3138   next_state:
3139     ;
3140   }
3141 #endif
3142 }
3143 
3144 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3145   Address addr = as_Address(src->as_address_ptr());
3146   BasicType type = src->type();
3147   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3148 
3149   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3150   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3151 
3152   switch(type) {
3153   case T_INT:
3154     xchg = &MacroAssembler::atomic_xchgalw;
3155     add = &MacroAssembler::atomic_addalw;
3156     break;
3157   case T_LONG:
3158     xchg = &MacroAssembler::atomic_xchgal;
3159     add = &MacroAssembler::atomic_addal;
3160     break;
3161   case T_OBJECT:
3162   case T_ARRAY:
3163     if (UseCompressedOops) {
3164       xchg = &MacroAssembler::atomic_xchgalw;
3165       add = &MacroAssembler::atomic_addalw;
3166     } else {
3167       xchg = &MacroAssembler::atomic_xchgal;
3168       add = &MacroAssembler::atomic_addal;
3169     }
3170     break;
3171   default:
3172     ShouldNotReachHere();
3173     xchg = &MacroAssembler::atomic_xchgal;
3174     add = &MacroAssembler::atomic_addal; // unreachable
3175   }
3176 
3177   switch (code) {
3178   case lir_xadd:
3179     {
3180       RegisterOrConstant inc;
3181       Register tmp = as_reg(tmp_op);
3182       Register dst = as_reg(dest);
3183       if (data->is_constant()) {
3184         inc = RegisterOrConstant(as_long(data));
3185         assert_different_registers(dst, addr.base(), tmp,
3186                                    rscratch1, rscratch2);
3187       } else {
3188         inc = RegisterOrConstant(as_reg(data));
3189         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3190                                    rscratch1, rscratch2);
3191       }
3192       __ lea(tmp, addr);
3193       (_masm->*add)(dst, inc, tmp);
3194       break;
3195     }
3196   case lir_xchg:
3197     {
3198       Register tmp = tmp_op->as_register();
3199       Register obj = as_reg(data);
3200       Register dst = as_reg(dest);
3201       if (is_oop && UseCompressedOops) {
3202         __ encode_heap_oop(rscratch2, obj);
3203         obj = rscratch2;
3204       }
3205       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3206       __ lea(tmp, addr);
3207       (_masm->*xchg)(dst, obj, tmp);
3208       if (is_oop && UseCompressedOops) {
3209         __ decode_heap_oop(dst);
3210       }
3211     }
3212     break;
3213   default:
3214     ShouldNotReachHere();
3215   }
3216   __ membar(__ AnyAny);
3217 }
3218 
3219 #undef __
--- EOF ---