1 /*
   2  * Copyright (c) 2008, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.inline.hpp"
  27 #include "c1/c1_Compilation.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "c1/c1_ValueStack.hpp"
  32 #include "ci/ciArrayKlass.hpp"
  33 #include "ci/ciInstance.hpp"
  34 #include "gc/shared/barrierSet.hpp"
  35 #include "gc/shared/cardTableBarrierSet.hpp"
  36 #include "gc/shared/collectedHeap.hpp"
  37 #include "nativeInst_arm.hpp"
  38 #include "oops/objArrayKlass.hpp"
  39 #include "runtime/frame.inline.hpp"
  40 #include "runtime/sharedRuntime.hpp"
  41 #include "vmreg_arm.inline.hpp"
  42 
  43 #define __ _masm->
  44 
  45 // Note: Rtemp usage is this file should not impact C2 and should be
  46 // correct as long as it is not implicitly used in lower layers (the
  47 // arm [macro]assembler) and used with care in the other C1 specific
  48 // files.
  49 
  50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  51   ShouldNotCallThis(); // Not used on ARM
  52   return false;
  53 }
  54 
  55 
  56 LIR_Opr LIR_Assembler::receiverOpr() {
  57   // The first register in Java calling conventions
  58   return FrameMap::R0_oop_opr;
  59 }
  60 
  61 LIR_Opr LIR_Assembler::osrBufferPointer() {
  62   return FrameMap::as_pointer_opr(R0);
  63 }
  64 
  65 #ifndef PRODUCT
  66 void LIR_Assembler::verify_reserved_argument_area_size(int args_count) {
  67   assert(args_count * wordSize <= frame_map()->reserved_argument_area_size(), "not enough space for arguments");
  68 }
  69 #endif // !PRODUCT
  70 
  71 void LIR_Assembler::store_parameter(jint c, int offset_from_sp_in_words) {
  72   assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
  73   int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
  74   assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
  75   __ mov_slow(Rtemp, c);
  76   __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
  77 }
  78 
  79 void LIR_Assembler::store_parameter(Metadata* m, int offset_from_sp_in_words) {
  80   assert(offset_from_sp_in_words >= 0, "invalid offset from sp");
  81   int offset_from_sp_in_bytes = offset_from_sp_in_words * BytesPerWord;
  82   assert(offset_from_sp_in_bytes < frame_map()->reserved_argument_area_size(), "not enough space");
  83   __ mov_metadata(Rtemp, m);
  84   __ str(Rtemp, Address(SP, offset_from_sp_in_bytes));
  85 }
  86 
  87 //--------------fpu register translations-----------------------
  88 
  89 
  90 void LIR_Assembler::set_24bit_FPU() {
  91   ShouldNotReachHere();
  92 }
  93 
  94 void LIR_Assembler::reset_FPU() {
  95   ShouldNotReachHere();
  96 }
  97 
  98 void LIR_Assembler::fpop() {
  99   Unimplemented();
 100 }
 101 
 102 void LIR_Assembler::fxch(int i) {
 103   Unimplemented();
 104 }
 105 
 106 void LIR_Assembler::fld(int i) {
 107   Unimplemented();
 108 }
 109 
 110 void LIR_Assembler::ffree(int i) {
 111   Unimplemented();
 112 }
 113 
 114 void LIR_Assembler::breakpoint() {
 115   __ breakpoint();
 116 }
 117 
 118 void LIR_Assembler::push(LIR_Opr opr) {
 119   Unimplemented();
 120 }
 121 
 122 void LIR_Assembler::pop(LIR_Opr opr) {
 123   Unimplemented();
 124 }
 125 
 126 //-------------------------------------------
 127 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 128   Register base = addr->base()->as_pointer_register();
 129 
 130 
 131   if (addr->index()->is_illegal() || addr->index()->is_constant()) {
 132     int offset = addr->disp();
 133     if (addr->index()->is_constant()) {
 134       offset += addr->index()->as_constant_ptr()->as_jint() << addr->scale();
 135     }
 136 
 137     if ((offset <= -4096) || (offset >= 4096)) {
 138       BAILOUT_("offset not in range", Address(base));
 139     }
 140 
 141     return Address(base, offset);
 142 
 143   } else {
 144     assert(addr->disp() == 0, "can't have both");
 145     int scale = addr->scale();
 146 
 147     assert(addr->index()->is_single_cpu(), "should be");
 148     return scale >= 0 ? Address(base, addr->index()->as_register(), lsl, scale) :
 149                         Address(base, addr->index()->as_register(), lsr, -scale);
 150   }
 151 }
 152 
 153 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 154   Address base = as_Address(addr);
 155   assert(base.index() == noreg, "must be");
 156   if (base.disp() + BytesPerWord >= 4096) { BAILOUT_("offset not in range", Address(base.base(),0)); }
 157   return Address(base.base(), base.disp() + BytesPerWord);
 158 }
 159 
 160 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 161   return as_Address(addr);
 162 }
 163 
 164 
 165 void LIR_Assembler::osr_entry() {
 166   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 167   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 168   ValueStack* entry_state = osr_entry->end()->state();
 169   int number_of_locks = entry_state->locks_size();
 170 
 171   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 172   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 173 
 174   assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 175   int monitor_offset = (method()->max_locals() + 2 * (number_of_locks - 1)) * BytesPerWord;
 176   for (int i = 0; i < number_of_locks; i++) {
 177     int slot_offset = monitor_offset - (i * 2 * BytesPerWord);
 178     __ ldr(R1, Address(OSR_buf, slot_offset + 0*BytesPerWord));
 179     __ ldr(R2, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 180     __ str(R1, frame_map()->address_for_monitor_lock(i));
 181     __ str(R2, frame_map()->address_for_monitor_object(i));
 182   }
 183 }
 184 
 185 
 186 int LIR_Assembler::check_icache() {
 187   Register receiver = LIR_Assembler::receiverOpr()->as_register();
 188   int offset = __ offset();
 189   __ inline_cache_check(receiver, Ricklass);
 190   return offset;
 191 }
 192 
 193 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 194   ShouldNotReachHere(); // not implemented
 195 }
 196 
 197 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 198   jobject o = (jobject)Universe::non_oop_word();
 199   int index = __ oop_recorder()->allocate_oop_index(o);
 200 
 201   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), index);
 202 
 203   __ patchable_mov_oop(reg, o, index);
 204   patching_epilog(patch, lir_patch_normal, reg, info);
 205 }
 206 
 207 
 208 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 209   Metadata* o = (Metadata*)Universe::non_oop_word();
 210   int index = __ oop_recorder()->allocate_metadata_index(o);
 211   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 212 
 213   __ patchable_mov_metadata(reg, o, index);
 214   patching_epilog(patch, lir_patch_normal, reg, info);
 215 }
 216 
 217 
 218 int LIR_Assembler::initial_frame_size_in_bytes() const {
 219   // Subtracts two words to account for return address and link
 220   return frame_map()->framesize()*VMRegImpl::stack_slot_size - 2*wordSize;
 221 }
 222 
 223 
 224 int LIR_Assembler::emit_exception_handler() {
 225   // TODO: ARM
 226   __ nop(); // See comments in other ports
 227 
 228   address handler_base = __ start_a_stub(exception_handler_size());
 229   if (handler_base == NULL) {
 230     bailout("exception handler overflow");
 231     return -1;
 232   }
 233 
 234   int offset = code_offset();
 235 
 236   // check that there is really an exception
 237   __ verify_not_null_oop(Rexception_obj);
 238 
 239   __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type);
 240   __ should_not_reach_here();
 241 
 242   assert(code_offset() - offset <= exception_handler_size(), "overflow");
 243   __ end_a_stub();
 244 
 245   return offset;
 246 }
 247 
 248 // Emit the code to remove the frame from the stack in the exception
 249 // unwind path.
 250 int LIR_Assembler::emit_unwind_handler() {
 251 #ifndef PRODUCT
 252   if (CommentedAssembly) {
 253     _masm->block_comment("Unwind handler");
 254   }
 255 #endif
 256 
 257   int offset = code_offset();
 258 
 259   // Fetch the exception from TLS and clear out exception related thread state
 260   Register zero = __ zero_register(Rtemp);
 261   __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
 262   __ str(zero, Address(Rthread, JavaThread::exception_oop_offset()));
 263   __ str(zero, Address(Rthread, JavaThread::exception_pc_offset()));
 264 
 265   __ bind(_unwind_handler_entry);
 266   __ verify_not_null_oop(Rexception_obj);
 267 
 268   // Preform needed unlocking
 269   MonitorExitStub* stub = NULL;
 270   if (method()->is_synchronized()) {
 271     monitor_address(0, FrameMap::R0_opr);
 272     stub = new MonitorExitStub(FrameMap::R0_opr, true, 0);
 273     __ unlock_object(R2, R1, R0, Rtemp, *stub->entry());
 274     __ bind(*stub->continuation());
 275   }
 276 
 277   // remove the activation and dispatch to the unwind handler
 278   __ remove_frame(initial_frame_size_in_bytes()); // restores FP and LR
 279   __ jump(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type, Rtemp);
 280 
 281   // Emit the slow path assembly
 282   if (stub != NULL) {
 283     stub->emit_code(this);
 284   }
 285 
 286   return offset;
 287 }
 288 
 289 
 290 int LIR_Assembler::emit_deopt_handler() {
 291   address handler_base = __ start_a_stub(deopt_handler_size());
 292   if (handler_base == NULL) {
 293     bailout("deopt handler overflow");
 294     return -1;
 295   }
 296 
 297   int offset = code_offset();
 298 
 299   __ mov_relative_address(LR, __ pc());
 300   __ push(LR); // stub expects LR to be saved
 301   __ jump(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type, noreg);
 302 
 303   assert(code_offset() - offset <= deopt_handler_size(), "overflow");
 304   __ end_a_stub();
 305 
 306   return offset;
 307 }
 308 
 309 
 310 void LIR_Assembler::return_op(LIR_Opr result) {
 311   // Pop the frame before safepoint polling
 312   __ remove_frame(initial_frame_size_in_bytes());
 313 
 314   // mov_slow here is usually one or two instruction
 315   __ mov_address(Rtemp, os::get_polling_page());
 316   __ relocate(relocInfo::poll_return_type);
 317   __ ldr(Rtemp, Address(Rtemp));
 318   __ ret();
 319 }
 320 
 321 
 322 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 323   __ mov_address(Rtemp, os::get_polling_page());
 324   if (info != NULL) {
 325     add_debug_info_for_branch(info);
 326   }
 327   int offset = __ offset();
 328   __ relocate(relocInfo::poll_type);
 329   __ ldr(Rtemp, Address(Rtemp));
 330   return offset;
 331 }
 332 
 333 
 334 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 335   if (from_reg != to_reg) {
 336     __ mov(to_reg, from_reg);
 337   }
 338 }
 339 
 340 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 341   assert(src->is_constant() && dest->is_register(), "must be");
 342   LIR_Const* c = src->as_constant_ptr();
 343 
 344   switch (c->type()) {
 345     case T_ADDRESS:
 346     case T_INT:
 347       assert(patch_code == lir_patch_none, "no patching handled here");
 348       __ mov_slow(dest->as_register(), c->as_jint());
 349       break;
 350 
 351     case T_LONG:
 352       assert(patch_code == lir_patch_none, "no patching handled here");
 353       __ mov_slow(dest->as_register_lo(), c->as_jint_lo());
 354       __ mov_slow(dest->as_register_hi(), c->as_jint_hi());
 355       break;
 356 
 357     case T_OBJECT:
 358       if (patch_code == lir_patch_none) {
 359         __ mov_oop(dest->as_register(), c->as_jobject());
 360       } else {
 361         jobject2reg_with_patching(dest->as_register(), info);
 362       }
 363       break;
 364 
 365     case T_METADATA:
 366       if (patch_code == lir_patch_none) {
 367         __ mov_metadata(dest->as_register(), c->as_metadata());
 368       } else {
 369         klass2reg_with_patching(dest->as_register(), info);
 370       }
 371       break;
 372 
 373     case T_FLOAT:
 374       if (dest->is_single_fpu()) {
 375         __ mov_float(dest->as_float_reg(), c->as_jfloat());
 376       } else {
 377         // Simple getters can return float constant directly into r0
 378         __ mov_slow(dest->as_register(), c->as_jint_bits());
 379       }
 380       break;
 381 
 382     case T_DOUBLE:
 383       if (dest->is_double_fpu()) {
 384         __ mov_double(dest->as_double_reg(), c->as_jdouble());
 385       } else {
 386         // Simple getters can return double constant directly into r1r0
 387         __ mov_slow(dest->as_register_lo(), c->as_jint_lo_bits());
 388         __ mov_slow(dest->as_register_hi(), c->as_jint_hi_bits());
 389       }
 390       break;
 391 
 392     default:
 393       ShouldNotReachHere();
 394   }
 395 }
 396 
 397 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 398   assert(src->is_constant(), "must be");
 399   assert(dest->is_stack(), "must be");
 400   LIR_Const* c = src->as_constant_ptr();
 401 
 402   switch (c->type()) {
 403     case T_INT:  // fall through
 404     case T_FLOAT:
 405       __ mov_slow(Rtemp, c->as_jint_bits());
 406       __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 407       break;
 408 
 409     case T_ADDRESS:
 410       __ mov_slow(Rtemp, c->as_jint());
 411       __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 412       break;
 413 
 414     case T_OBJECT:
 415       __ mov_oop(Rtemp, c->as_jobject());
 416       __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 417       break;
 418 
 419     case T_LONG:  // fall through
 420     case T_DOUBLE:
 421       __ mov_slow(Rtemp, c->as_jint_lo_bits());
 422       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
 423       if (c->as_jint_hi_bits() != c->as_jint_lo_bits()) {
 424         __ mov_slow(Rtemp, c->as_jint_hi_bits());
 425       }
 426       __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 427       break;
 428 
 429     default:
 430       ShouldNotReachHere();
 431   }
 432 }
 433 
 434 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
 435                               CodeEmitInfo* info, bool wide) {
 436   assert((src->as_constant_ptr()->type() == T_OBJECT && src->as_constant_ptr()->as_jobject() == NULL),"cannot handle otherwise");
 437   __ mov(Rtemp, 0);
 438 
 439   int null_check_offset = code_offset();
 440   __ str(Rtemp, as_Address(dest->as_address_ptr()));
 441 
 442   if (info != NULL) {
 443     assert(false, "arm32 didn't support this before, investigate if bug");
 444     add_debug_info_for_null_check(null_check_offset, info);
 445   }
 446 }
 447 
 448 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 449   assert(src->is_register() && dest->is_register(), "must be");
 450 
 451   if (src->is_single_cpu()) {
 452     if (dest->is_single_cpu()) {
 453       move_regs(src->as_register(), dest->as_register());
 454     } else if (dest->is_single_fpu()) {
 455       __ fmsr(dest->as_float_reg(), src->as_register());
 456     } else {
 457       ShouldNotReachHere();
 458     }
 459   } else if (src->is_double_cpu()) {
 460     if (dest->is_double_cpu()) {
 461       __ long_move(dest->as_register_lo(), dest->as_register_hi(), src->as_register_lo(), src->as_register_hi());
 462     } else {
 463       __ fmdrr(dest->as_double_reg(), src->as_register_lo(), src->as_register_hi());
 464     }
 465   } else if (src->is_single_fpu()) {
 466     if (dest->is_single_fpu()) {
 467       __ mov_float(dest->as_float_reg(), src->as_float_reg());
 468     } else if (dest->is_single_cpu()) {
 469       __ mov_fpr2gpr_float(dest->as_register(), src->as_float_reg());
 470     } else {
 471       ShouldNotReachHere();
 472     }
 473   } else if (src->is_double_fpu()) {
 474     if (dest->is_double_fpu()) {
 475       __ mov_double(dest->as_double_reg(), src->as_double_reg());
 476     } else if (dest->is_double_cpu()) {
 477       __ fmrrd(dest->as_register_lo(), dest->as_register_hi(), src->as_double_reg());
 478     } else {
 479       ShouldNotReachHere();
 480     }
 481   } else {
 482     ShouldNotReachHere();
 483   }
 484 }
 485 
 486 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 487   assert(src->is_register(), "should not call otherwise");
 488   assert(dest->is_stack(), "should not call otherwise");
 489 
 490   Address addr = dest->is_single_word() ?
 491     frame_map()->address_for_slot(dest->single_stack_ix()) :
 492     frame_map()->address_for_slot(dest->double_stack_ix());
 493 
 494   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
 495   if (src->is_single_fpu() || src->is_double_fpu()) {
 496     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
 497   }
 498 
 499   if (src->is_single_cpu()) {
 500     switch (type) {
 501       case T_OBJECT:
 502       case T_ARRAY:    __ verify_oop(src->as_register());   // fall through
 503       case T_ADDRESS:
 504       case T_METADATA: __ str(src->as_register(), addr);    break;
 505       case T_FLOAT:    // used in intBitsToFloat intrinsic implementation, fall through
 506       case T_INT:      __ str_32(src->as_register(), addr); break;
 507       default:
 508         ShouldNotReachHere();
 509     }
 510   } else if (src->is_double_cpu()) {
 511     __ str(src->as_register_lo(), addr);
 512     __ str(src->as_register_hi(), frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 513   } else if (src->is_single_fpu()) {
 514     __ str_float(src->as_float_reg(), addr);
 515   } else if (src->is_double_fpu()) {
 516     __ str_double(src->as_double_reg(), addr);
 517   } else {
 518     ShouldNotReachHere();
 519   }
 520 }
 521 
 522 
 523 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
 524                             LIR_PatchCode patch_code, CodeEmitInfo* info,
 525                             bool pop_fpu_stack, bool wide,
 526                             bool unaligned) {
 527   LIR_Address* to_addr = dest->as_address_ptr();
 528   Register base_reg = to_addr->base()->as_pointer_register();
 529   const bool needs_patching = (patch_code != lir_patch_none);
 530 
 531   PatchingStub* patch = NULL;
 532   if (needs_patching) {
 533     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 534   }
 535 
 536   int null_check_offset = code_offset();
 537 
 538   switch (type) {
 539     case T_ARRAY:
 540     case T_OBJECT:
 541       if (UseCompressedOops && !wide) {
 542         ShouldNotReachHere();
 543       } else {
 544         __ str(src->as_register(), as_Address(to_addr));
 545       }
 546       break;
 547 
 548     case T_ADDRESS:
 549       __ str(src->as_pointer_register(), as_Address(to_addr));
 550       break;
 551 
 552     case T_BYTE:
 553     case T_BOOLEAN:
 554       __ strb(src->as_register(), as_Address(to_addr));
 555       break;
 556 
 557     case T_CHAR:
 558     case T_SHORT:
 559       __ strh(src->as_register(), as_Address(to_addr));
 560       break;
 561 
 562     case T_INT:
 563 #ifdef __SOFTFP__
 564     case T_FLOAT:
 565 #endif // __SOFTFP__
 566       __ str_32(src->as_register(), as_Address(to_addr));
 567       break;
 568 
 569 
 570 #ifdef __SOFTFP__
 571     case T_DOUBLE:
 572 #endif // __SOFTFP__
 573     case T_LONG: {
 574       Register from_lo = src->as_register_lo();
 575       Register from_hi = src->as_register_hi();
 576       if (to_addr->index()->is_register()) {
 577         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 578         assert(to_addr->disp() == 0, "Not yet supporting both");
 579         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 580         base_reg = Rtemp;
 581         __ str(from_lo, Address(Rtemp));
 582         if (patch != NULL) {
 583           patching_epilog(patch, lir_patch_low, base_reg, info);
 584           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 585           patch_code = lir_patch_high;
 586         }
 587         __ str(from_hi, Address(Rtemp, BytesPerWord));
 588       } else if (base_reg == from_lo) {
 589         __ str(from_hi, as_Address_hi(to_addr));
 590         if (patch != NULL) {
 591           patching_epilog(patch, lir_patch_high, base_reg, info);
 592           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 593           patch_code = lir_patch_low;
 594         }
 595         __ str(from_lo, as_Address_lo(to_addr));
 596       } else {
 597         __ str(from_lo, as_Address_lo(to_addr));
 598         if (patch != NULL) {
 599           patching_epilog(patch, lir_patch_low, base_reg, info);
 600           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 601           patch_code = lir_patch_high;
 602         }
 603         __ str(from_hi, as_Address_hi(to_addr));
 604       }
 605       break;
 606     }
 607 
 608 #ifndef __SOFTFP__
 609     case T_FLOAT:
 610       if (to_addr->index()->is_register()) {
 611         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 612         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 613         if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 614         __ fsts(src->as_float_reg(), Address(Rtemp, to_addr->disp()));
 615       } else {
 616         __ fsts(src->as_float_reg(), as_Address(to_addr));
 617       }
 618       break;
 619 
 620     case T_DOUBLE:
 621       if (to_addr->index()->is_register()) {
 622         assert(to_addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 623         __ add(Rtemp, base_reg, to_addr->index()->as_register());
 624         if ((to_addr->disp() <= -4096) || (to_addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 625         __ fstd(src->as_double_reg(), Address(Rtemp, to_addr->disp()));
 626       } else {
 627         __ fstd(src->as_double_reg(), as_Address(to_addr));
 628       }
 629       break;
 630 #endif // __SOFTFP__
 631 
 632 
 633     default:
 634       ShouldNotReachHere();
 635   }
 636 
 637   if (info != NULL) {
 638     add_debug_info_for_null_check(null_check_offset, info);
 639   }
 640 
 641   if (patch != NULL) {
 642     // Offset embeedded into LDR/STR instruction may appear not enough
 643     // to address a field. So, provide a space for one more instruction
 644     // that will deal with larger offsets.
 645     __ nop();
 646     patching_epilog(patch, patch_code, base_reg, info);
 647   }
 648 }
 649 
 650 
 651 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 652   assert(src->is_stack(), "should not call otherwise");
 653   assert(dest->is_register(), "should not call otherwise");
 654 
 655   Address addr = src->is_single_word() ?
 656     frame_map()->address_for_slot(src->single_stack_ix()) :
 657     frame_map()->address_for_slot(src->double_stack_ix());
 658 
 659   assert(lo_word_offset_in_bytes == 0 && hi_word_offset_in_bytes == 4, "little ending");
 660   if (dest->is_single_fpu() || dest->is_double_fpu()) {
 661     if (addr.disp() >= 1024) { BAILOUT("Too exotic case to handle here"); }
 662   }
 663 
 664   if (dest->is_single_cpu()) {
 665     switch (type) {
 666       case T_OBJECT:
 667       case T_ARRAY:
 668       case T_ADDRESS:
 669       case T_METADATA: __ ldr(dest->as_register(), addr); break;
 670       case T_FLOAT:    // used in floatToRawIntBits intrinsic implemenation
 671       case T_INT:      __ ldr_u32(dest->as_register(), addr); break;
 672       default:
 673         ShouldNotReachHere();
 674     }
 675     if ((type == T_OBJECT) || (type == T_ARRAY)) {
 676       __ verify_oop(dest->as_register());
 677     }
 678   } else if (dest->is_double_cpu()) {
 679     __ ldr(dest->as_register_lo(), addr);
 680     __ ldr(dest->as_register_hi(), frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
 681   } else if (dest->is_single_fpu()) {
 682     __ ldr_float(dest->as_float_reg(), addr);
 683   } else if (dest->is_double_fpu()) {
 684     __ ldr_double(dest->as_double_reg(), addr);
 685   } else {
 686     ShouldNotReachHere();
 687   }
 688 }
 689 
 690 
 691 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 692   if (src->is_single_stack()) {
 693     switch (src->type()) {
 694       case T_OBJECT:
 695       case T_ARRAY:
 696       case T_ADDRESS:
 697       case T_METADATA:
 698         __ ldr(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
 699         __ str(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 700         break;
 701 
 702       case T_INT:
 703       case T_FLOAT:
 704         __ ldr_u32(Rtemp, frame_map()->address_for_slot(src->single_stack_ix()));
 705         __ str_32(Rtemp, frame_map()->address_for_slot(dest->single_stack_ix()));
 706         break;
 707 
 708       default:
 709         ShouldNotReachHere();
 710     }
 711   } else {
 712     assert(src->is_double_stack(), "must be");
 713     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes));
 714     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes));
 715     __ ldr(Rtemp, frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes));
 716     __ str(Rtemp, frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes));
 717   }
 718 }
 719 
 720 
 721 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type,
 722                             LIR_PatchCode patch_code, CodeEmitInfo* info,
 723                             bool wide, bool unaligned) {
 724   assert(src->is_address(), "should not call otherwise");
 725   assert(dest->is_register(), "should not call otherwise");
 726   LIR_Address* addr = src->as_address_ptr();
 727 
 728   Register base_reg = addr->base()->as_pointer_register();
 729 
 730   PatchingStub* patch = NULL;
 731   if (patch_code != lir_patch_none) {
 732     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 733   }
 734   if (info != NULL) {
 735     add_debug_info_for_null_check_here(info);
 736   }
 737 
 738   switch (type) {
 739     case T_OBJECT:  // fall through
 740     case T_ARRAY:
 741       if (UseCompressedOops && !wide) {
 742         __ ldr_u32(dest->as_register(), as_Address(addr));
 743       } else {
 744         __ ldr(dest->as_register(), as_Address(addr));
 745       }
 746       break;
 747 
 748     case T_ADDRESS:
 749       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 750         __ ldr_u32(dest->as_pointer_register(), as_Address(addr));
 751       } else {
 752         __ ldr(dest->as_pointer_register(), as_Address(addr));
 753       }
 754       break;
 755 
 756     case T_INT:
 757 #ifdef __SOFTFP__
 758     case T_FLOAT:
 759 #endif // __SOFTFP__
 760       __ ldr(dest->as_pointer_register(), as_Address(addr));
 761       break;
 762 
 763     case T_BOOLEAN:
 764       __ ldrb(dest->as_register(), as_Address(addr));
 765       break;
 766 
 767     case T_BYTE:
 768       __ ldrsb(dest->as_register(), as_Address(addr));
 769       break;
 770 
 771     case T_CHAR:
 772       __ ldrh(dest->as_register(), as_Address(addr));
 773       break;
 774 
 775     case T_SHORT:
 776       __ ldrsh(dest->as_register(), as_Address(addr));
 777       break;
 778 
 779 
 780 #ifdef __SOFTFP__
 781     case T_DOUBLE:
 782 #endif // __SOFTFP__
 783     case T_LONG: {
 784       Register to_lo = dest->as_register_lo();
 785       Register to_hi = dest->as_register_hi();
 786       if (addr->index()->is_register()) {
 787         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 788         assert(addr->disp() == 0, "Not yet supporting both");
 789         __ add(Rtemp, base_reg, addr->index()->as_register());
 790         base_reg = Rtemp;
 791         __ ldr(to_lo, Address(Rtemp));
 792         if (patch != NULL) {
 793           patching_epilog(patch, lir_patch_low, base_reg, info);
 794           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 795           patch_code = lir_patch_high;
 796         }
 797         __ ldr(to_hi, Address(Rtemp, BytesPerWord));
 798       } else if (base_reg == to_lo) {
 799         __ ldr(to_hi, as_Address_hi(addr));
 800         if (patch != NULL) {
 801           patching_epilog(patch, lir_patch_high, base_reg, info);
 802           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 803           patch_code = lir_patch_low;
 804         }
 805         __ ldr(to_lo, as_Address_lo(addr));
 806       } else {
 807         __ ldr(to_lo, as_Address_lo(addr));
 808         if (patch != NULL) {
 809           patching_epilog(patch, lir_patch_low, base_reg, info);
 810           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 811           patch_code = lir_patch_high;
 812         }
 813         __ ldr(to_hi, as_Address_hi(addr));
 814       }
 815       break;
 816     }
 817 
 818 #ifndef __SOFTFP__
 819     case T_FLOAT:
 820       if (addr->index()->is_register()) {
 821         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 822         __ add(Rtemp, base_reg, addr->index()->as_register());
 823         if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 824         __ flds(dest->as_float_reg(), Address(Rtemp, addr->disp()));
 825       } else {
 826         __ flds(dest->as_float_reg(), as_Address(addr));
 827       }
 828       break;
 829 
 830     case T_DOUBLE:
 831       if (addr->index()->is_register()) {
 832         assert(addr->scale() == LIR_Address::times_1,"Unexpected scaled register");
 833         __ add(Rtemp, base_reg, addr->index()->as_register());
 834         if ((addr->disp() <= -4096) || (addr->disp() >= 4096)) { BAILOUT("offset not in range"); }
 835         __ fldd(dest->as_double_reg(), Address(Rtemp, addr->disp()));
 836       } else {
 837         __ fldd(dest->as_double_reg(), as_Address(addr));
 838       }
 839       break;
 840 #endif // __SOFTFP__
 841 
 842 
 843     default:
 844       ShouldNotReachHere();
 845   }
 846 
 847   if (patch != NULL) {
 848     // Offset embeedded into LDR/STR instruction may appear not enough
 849     // to address a field. So, provide a space for one more instruction
 850     // that will deal with larger offsets.
 851     __ nop();
 852     patching_epilog(patch, patch_code, base_reg, info);
 853   }
 854 
 855 }
 856 
 857 
 858 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 859   bool is_32 = op->result_opr()->is_single_cpu();
 860 
 861   if (op->code() == lir_idiv && op->in_opr2()->is_constant() && is_32) {
 862     int c = op->in_opr2()->as_constant_ptr()->as_jint();
 863     assert(is_power_of_2(c), "non power-of-2 constant should be put in a register");
 864 
 865     Register left = op->in_opr1()->as_register();
 866     Register dest = op->result_opr()->as_register();
 867     if (c == 1) {
 868       __ mov(dest, left);
 869     } else if (c == 2) {
 870       __ add_32(dest, left, AsmOperand(left, lsr, 31));
 871       __ asr_32(dest, dest, 1);
 872     } else if (c != (int) 0x80000000) {
 873       int power = log2_intptr(c);
 874       __ asr_32(Rtemp, left, 31);
 875       __ add_32(dest, left, AsmOperand(Rtemp, lsr, 32-power)); // dest = left + (left < 0 ? 2^power - 1 : 0);
 876       __ asr_32(dest, dest, power);                            // dest = dest >>> power;
 877     } else {
 878       // x/0x80000000 is a special case, since dividend is a power of two, but is negative.
 879       // The only possible result values are 0 and 1, with 1 only for dividend == divisor == 0x80000000.
 880       __ cmp_32(left, c);
 881       __ mov(dest, 0, ne);
 882       __ mov(dest, 1, eq);
 883     }
 884   } else {
 885     assert(op->code() == lir_idiv || op->code() == lir_irem, "unexpected op3");
 886     __ call(StubRoutines::Arm::idiv_irem_entry(), relocInfo::runtime_call_type);
 887     add_debug_info_for_div0_here(op->info());
 888   }
 889 }
 890 
 891 
 892 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 893 #ifdef ASSERT
 894   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 895   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 896   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 897   assert(op->info() == NULL, "CodeEmitInfo?");
 898 #endif // ASSERT
 899 
 900 #ifdef __SOFTFP__
 901   assert (op->code() != lir_cond_float_branch, "this should be impossible");
 902 #else
 903   if (op->code() == lir_cond_float_branch) {
 904     __ fmstat();
 905     __ b(*(op->ublock()->label()), vs);
 906   }
 907 #endif // __SOFTFP__
 908 
 909   AsmCondition acond = al;
 910   switch (op->cond()) {
 911     case lir_cond_equal:        acond = eq; break;
 912     case lir_cond_notEqual:     acond = ne; break;
 913     case lir_cond_less:         acond = lt; break;
 914     case lir_cond_lessEqual:    acond = le; break;
 915     case lir_cond_greaterEqual: acond = ge; break;
 916     case lir_cond_greater:      acond = gt; break;
 917     case lir_cond_aboveEqual:   acond = hs; break;
 918     case lir_cond_belowEqual:   acond = ls; break;
 919     default: assert(op->cond() == lir_cond_always, "must be");
 920   }
 921   __ b(*(op->label()), acond);
 922 }
 923 
 924 
 925 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 926   LIR_Opr src  = op->in_opr();
 927   LIR_Opr dest = op->result_opr();
 928 
 929   switch (op->bytecode()) {
 930     case Bytecodes::_i2l:
 931       move_regs(src->as_register(), dest->as_register_lo());
 932       __ mov(dest->as_register_hi(), AsmOperand(src->as_register(), asr, 31));
 933       break;
 934     case Bytecodes::_l2i:
 935       move_regs(src->as_register_lo(), dest->as_register());
 936       break;
 937     case Bytecodes::_i2b:
 938       __ sign_extend(dest->as_register(), src->as_register(), 8);
 939       break;
 940     case Bytecodes::_i2s:
 941       __ sign_extend(dest->as_register(), src->as_register(), 16);
 942       break;
 943     case Bytecodes::_i2c:
 944       __ zero_extend(dest->as_register(), src->as_register(), 16);
 945       break;
 946     case Bytecodes::_f2d:
 947       __ convert_f2d(dest->as_double_reg(), src->as_float_reg());
 948       break;
 949     case Bytecodes::_d2f:
 950       __ convert_d2f(dest->as_float_reg(), src->as_double_reg());
 951       break;
 952     case Bytecodes::_i2f:
 953       __ fmsr(Stemp, src->as_register());
 954       __ fsitos(dest->as_float_reg(), Stemp);
 955       break;
 956     case Bytecodes::_i2d:
 957       __ fmsr(Stemp, src->as_register());
 958       __ fsitod(dest->as_double_reg(), Stemp);
 959       break;
 960     case Bytecodes::_f2i:
 961       __ ftosizs(Stemp, src->as_float_reg());
 962       __ fmrs(dest->as_register(), Stemp);
 963       break;
 964     case Bytecodes::_d2i:
 965       __ ftosizd(Stemp, src->as_double_reg());
 966       __ fmrs(dest->as_register(), Stemp);
 967       break;
 968     default:
 969       ShouldNotReachHere();
 970   }
 971 }
 972 
 973 
 974 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
 975   if (op->init_check()) {
 976     Register tmp = op->tmp1()->as_register();
 977     __ ldrb(tmp, Address(op->klass()->as_register(), InstanceKlass::init_state_offset()));
 978     add_debug_info_for_null_check_here(op->stub()->info());
 979     __ cmp(tmp, InstanceKlass::fully_initialized);
 980     __ b(*op->stub()->entry(), ne);
 981   }
 982   __ allocate_object(op->obj()->as_register(),
 983                      op->tmp1()->as_register(),
 984                      op->tmp2()->as_register(),
 985                      op->tmp3()->as_register(),
 986                      op->header_size(),
 987                      op->object_size(),
 988                      op->klass()->as_register(),
 989                      *op->stub()->entry());
 990   __ bind(*op->stub()->continuation());
 991 }
 992 
 993 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
 994   if (UseSlowPath ||
 995       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
 996       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
 997     __ b(*op->stub()->entry());
 998   } else {
 999     __ allocate_array(op->obj()->as_register(),
1000                       op->len()->as_register(),
1001                       op->tmp1()->as_register(),
1002                       op->tmp2()->as_register(),
1003                       op->tmp3()->as_register(),
1004                       arrayOopDesc::header_size(op->type()),
1005                       type2aelembytes(op->type()),
1006                       op->klass()->as_register(),
1007                       *op->stub()->entry());
1008   }
1009   __ bind(*op->stub()->continuation());
1010 }
1011 
1012 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
1013                                         ciMethodData *md, ciProfileData *data,
1014                                         Register recv, Register tmp1, Label* update_done) {
1015   assert_different_registers(mdo, recv, tmp1);
1016   uint i;
1017   for (i = 0; i < VirtualCallData::row_limit(); i++) {
1018     Label next_test;
1019     // See if the receiver is receiver[n].
1020     Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1021                           mdo_offset_bias);
1022     __ ldr(tmp1, receiver_addr);
1023     __ verify_klass_ptr(tmp1);
1024     __ cmp(recv, tmp1);
1025     __ b(next_test, ne);
1026     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1027                       mdo_offset_bias);
1028     __ ldr(tmp1, data_addr);
1029     __ add(tmp1, tmp1, DataLayout::counter_increment);
1030     __ str(tmp1, data_addr);
1031     __ b(*update_done);
1032     __ bind(next_test);
1033   }
1034 
1035   // Didn't find receiver; find next empty slot and fill it in
1036   for (i = 0; i < VirtualCallData::row_limit(); i++) {
1037     Label next_test;
1038     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) -
1039                       mdo_offset_bias);
1040     __ ldr(tmp1, recv_addr);
1041     __ cbnz(tmp1, next_test);
1042     __ str(recv, recv_addr);
1043     __ mov(tmp1, DataLayout::counter_increment);
1044     __ str(tmp1, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) -
1045                          mdo_offset_bias));
1046     __ b(*update_done);
1047     __ bind(next_test);
1048   }
1049 }
1050 
1051 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
1052                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
1053   md = method->method_data_or_null();
1054   assert(md != NULL, "Sanity");
1055   data = md->bci_to_data(bci);
1056   assert(data != NULL,       "need data for checkcast");
1057   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1058   if (md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes() >= 4096) {
1059     // The offset is large so bias the mdo by the base of the slot so
1060     // that the ldr can use an immediate offset to reference the slots of the data
1061     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
1062   }
1063 }
1064 
1065 // On 32-bit ARM, code before this helper should test obj for null (ZF should be set if obj is null).
1066 void LIR_Assembler::typecheck_profile_helper1(ciMethod* method, int bci,
1067                                               ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias,
1068                                               Register obj, Register mdo, Register data_val, Label* obj_is_null) {
1069   assert(method != NULL, "Should have method");
1070   assert_different_registers(obj, mdo, data_val);
1071   setup_md_access(method, bci, md, data, mdo_offset_bias);
1072   Label not_null;
1073   __ b(not_null, ne);
1074   __ mov_metadata(mdo, md->constant_encoding());
1075   if (mdo_offset_bias > 0) {
1076     __ mov_slow(data_val, mdo_offset_bias);
1077     __ add(mdo, mdo, data_val);
1078   }
1079   Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias);
1080   __ ldrb(data_val, flags_addr);
1081   __ orr(data_val, data_val, (uint)BitData::null_seen_byte_constant());
1082   __ strb(data_val, flags_addr);
1083   __ b(*obj_is_null);
1084   __ bind(not_null);
1085 }
1086 
1087 void LIR_Assembler::typecheck_profile_helper2(ciMethodData* md, ciProfileData* data, int mdo_offset_bias,
1088                                               Register mdo, Register recv, Register value, Register tmp1,
1089                                               Label* profile_cast_success, Label* profile_cast_failure,
1090                                               Label* success, Label* failure) {
1091   assert_different_registers(mdo, value, tmp1);
1092   __ bind(*profile_cast_success);
1093   __ mov_metadata(mdo, md->constant_encoding());
1094   if (mdo_offset_bias > 0) {
1095     __ mov_slow(tmp1, mdo_offset_bias);
1096     __ add(mdo, mdo, tmp1);
1097   }
1098   __ load_klass(recv, value);
1099   type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success);
1100   __ b(*success);
1101   // Cast failure case
1102   __ bind(*profile_cast_failure);
1103   __ mov_metadata(mdo, md->constant_encoding());
1104   if (mdo_offset_bias > 0) {
1105     __ mov_slow(tmp1, mdo_offset_bias);
1106     __ add(mdo, mdo, tmp1);
1107   }
1108   Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
1109   __ ldr(tmp1, data_addr);
1110   __ sub(tmp1, tmp1, DataLayout::counter_increment);
1111   __ str(tmp1, data_addr);
1112   __ b(*failure);
1113 }
1114 
1115 // Sets `res` to true, if `cond` holds.
1116 static void set_instanceof_result(MacroAssembler* _masm, Register res, AsmCondition cond) {
1117   __ mov(res, 1, cond);
1118 }
1119 
1120 
1121 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1122   // TODO: ARM - can be more effective with one more register
1123   switch (op->code()) {
1124     case lir_store_check: {
1125       CodeStub* stub = op->stub();
1126       Register value = op->object()->as_register();
1127       Register array = op->array()->as_register();
1128       Register klass_RInfo = op->tmp1()->as_register();
1129       Register k_RInfo = op->tmp2()->as_register();
1130       assert_different_registers(klass_RInfo, k_RInfo, Rtemp);
1131       if (op->should_profile()) {
1132         assert_different_registers(value, klass_RInfo, k_RInfo, Rtemp);
1133       }
1134 
1135       // check if it needs to be profiled
1136       ciMethodData* md;
1137       ciProfileData* data;
1138       int mdo_offset_bias = 0;
1139       Label profile_cast_success, profile_cast_failure, done;
1140       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1141       Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1142 
1143       if (op->should_profile()) {
1144         __ cmp(value, 0);
1145         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, value, k_RInfo, Rtemp, &done);
1146       } else {
1147         __ cbz(value, done);
1148       }
1149       assert_different_registers(k_RInfo, value);
1150       add_debug_info_for_null_check_here(op->info_for_exception());
1151       __ load_klass(k_RInfo, array);
1152       __ load_klass(klass_RInfo, value);
1153       __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1154       __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1155       // check for immediate positive hit
1156       __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1157       __ cmp(klass_RInfo, k_RInfo);
1158       __ cond_cmp(Rtemp, k_RInfo, ne);
1159       __ b(*success_target, eq);
1160       // check for immediate negative hit
1161       __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1162       __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1163       __ b(*failure_target, ne);
1164       // slow case
1165       assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1166       __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1167       __ cbz(R0, *failure_target);
1168       if (op->should_profile()) {
1169         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1170         if (mdo == value) {
1171           mdo = k_RInfo;
1172           recv = klass_RInfo;
1173         }
1174         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, value, tmp1,
1175                                   &profile_cast_success, &profile_cast_failure,
1176                                   &done, stub->entry());
1177       }
1178       __ bind(done);
1179       break;
1180     }
1181 
1182     case lir_checkcast: {
1183       CodeStub* stub = op->stub();
1184       Register obj = op->object()->as_register();
1185       Register res = op->result_opr()->as_register();
1186       Register klass_RInfo = op->tmp1()->as_register();
1187       Register k_RInfo = op->tmp2()->as_register();
1188       ciKlass* k = op->klass();
1189       assert_different_registers(res, k_RInfo, klass_RInfo, Rtemp);
1190 
1191       if (stub->is_simple_exception_stub()) {
1192       // TODO: ARM - Late binding is used to prevent confusion of register allocator
1193       assert(stub->is_exception_throw_stub(), "must be");
1194       ((SimpleExceptionStub*)stub)->set_obj(op->result_opr());
1195       }
1196       ciMethodData* md;
1197       ciProfileData* data;
1198       int mdo_offset_bias = 0;
1199 
1200       Label done;
1201 
1202       Label profile_cast_failure, profile_cast_success;
1203       Label *failure_target = op->should_profile() ? &profile_cast_failure : op->stub()->entry();
1204       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1205 
1206 
1207       __ movs(res, obj);
1208       if (op->should_profile()) {
1209         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1210       } else {
1211         __ b(done, eq);
1212       }
1213       if (k->is_loaded()) {
1214         __ mov_metadata(k_RInfo, k->constant_encoding());
1215       } else if (k_RInfo != obj) {
1216         klass2reg_with_patching(k_RInfo, op->info_for_patch());
1217         __ movs(res, obj);
1218       } else {
1219         // Patching doesn't update "res" register after GC, so do patching first
1220         klass2reg_with_patching(Rtemp, op->info_for_patch());
1221         __ movs(res, obj);
1222         __ mov(k_RInfo, Rtemp);
1223       }
1224       __ load_klass(klass_RInfo, res, ne);
1225 
1226       if (op->fast_check()) {
1227         __ cmp(klass_RInfo, k_RInfo, ne);
1228         __ b(*failure_target, ne);
1229       } else if (k->is_loaded()) {
1230         __ b(*success_target, eq);
1231         __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1232         if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1233           __ cmp(Rtemp, k_RInfo);
1234           __ b(*failure_target, ne);
1235         } else {
1236           __ cmp(klass_RInfo, k_RInfo);
1237           __ cmp(Rtemp, k_RInfo, ne);
1238           __ b(*success_target, eq);
1239           assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1240           __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1241           __ cbz(R0, *failure_target);
1242         }
1243       } else {
1244         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1245         __ b(*success_target, eq);
1246         // check for immediate positive hit
1247         __ ldr(Rtemp, Address(klass_RInfo, Rtemp));
1248         __ cmp(klass_RInfo, k_RInfo);
1249         __ cmp(Rtemp, k_RInfo, ne);
1250         __ b(*success_target, eq);
1251         // check for immediate negative hit
1252         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1253         __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1254         __ b(*failure_target, ne);
1255         // slow case
1256         assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1257         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1258         __ cbz(R0, *failure_target);
1259       }
1260 
1261       if (op->should_profile()) {
1262         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1263         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1264                                   &profile_cast_success, &profile_cast_failure,
1265                                   &done, stub->entry());
1266       }
1267       __ bind(done);
1268       break;
1269     }
1270 
1271     case lir_instanceof: {
1272       Register obj = op->object()->as_register();
1273       Register res = op->result_opr()->as_register();
1274       Register klass_RInfo = op->tmp1()->as_register();
1275       Register k_RInfo = op->tmp2()->as_register();
1276       ciKlass* k = op->klass();
1277       assert_different_registers(res, klass_RInfo, k_RInfo, Rtemp);
1278 
1279       ciMethodData* md;
1280       ciProfileData* data;
1281       int mdo_offset_bias = 0;
1282 
1283       Label done;
1284 
1285       Label profile_cast_failure, profile_cast_success;
1286       Label *failure_target = op->should_profile() ? &profile_cast_failure : &done;
1287       Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1288 
1289       __ movs(res, obj);
1290 
1291       if (op->should_profile()) {
1292         typecheck_profile_helper1(op->profiled_method(), op->profiled_bci(), md, data, mdo_offset_bias, res, klass_RInfo, Rtemp, &done);
1293       } else {
1294         __ b(done, eq);
1295       }
1296 
1297       if (k->is_loaded()) {
1298         __ mov_metadata(k_RInfo, k->constant_encoding());
1299       } else {
1300         op->info_for_patch()->add_register_oop(FrameMap::as_oop_opr(res));
1301         klass2reg_with_patching(k_RInfo, op->info_for_patch());
1302       }
1303       __ load_klass(klass_RInfo, res);
1304 
1305       if (!op->should_profile()) {
1306         __ mov(res, 0);
1307       }
1308 
1309       if (op->fast_check()) {
1310         __ cmp(klass_RInfo, k_RInfo);
1311         if (!op->should_profile()) {
1312           set_instanceof_result(_masm, res, eq);
1313         } else {
1314           __ b(profile_cast_failure, ne);
1315         }
1316       } else if (k->is_loaded()) {
1317         __ ldr(Rtemp, Address(klass_RInfo, k->super_check_offset()));
1318         if (in_bytes(Klass::secondary_super_cache_offset()) != (int) k->super_check_offset()) {
1319           __ cmp(Rtemp, k_RInfo);
1320           if (!op->should_profile()) {
1321             set_instanceof_result(_masm, res, eq);
1322           } else {
1323             __ b(profile_cast_failure, ne);
1324           }
1325         } else {
1326           __ cmp(klass_RInfo, k_RInfo);
1327           __ cond_cmp(Rtemp, k_RInfo, ne);
1328           if (!op->should_profile()) {
1329             set_instanceof_result(_masm, res, eq);
1330           }
1331           __ b(*success_target, eq);
1332           assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1333           __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1334           if (!op->should_profile()) {
1335             move_regs(R0, res);
1336           } else {
1337             __ cbz(R0, *failure_target);
1338           }
1339         }
1340       } else {
1341         __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1342         // check for immediate positive hit
1343         __ cmp(klass_RInfo, k_RInfo);
1344         if (!op->should_profile()) {
1345           __ ldr(res, Address(klass_RInfo, Rtemp), ne);
1346           __ cond_cmp(res, k_RInfo, ne);
1347           set_instanceof_result(_masm, res, eq);
1348         } else {
1349           __ ldr(Rtemp, Address(klass_RInfo, Rtemp), ne);
1350           __ cond_cmp(Rtemp, k_RInfo, ne);
1351         }
1352         __ b(*success_target, eq);
1353         // check for immediate negative hit
1354         if (op->should_profile()) {
1355           __ ldr_u32(Rtemp, Address(k_RInfo, Klass::super_check_offset_offset()));
1356         }
1357         __ cmp(Rtemp, in_bytes(Klass::secondary_super_cache_offset()));
1358         if (!op->should_profile()) {
1359           __ mov(res, 0, ne);
1360         }
1361         __ b(*failure_target, ne);
1362         // slow case
1363         assert(klass_RInfo == R0 && k_RInfo == R1, "runtime call setup");
1364         __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type);
1365         if (!op->should_profile()) {
1366           move_regs(R0, res);
1367         }
1368         if (op->should_profile()) {
1369           __ cbz(R0, *failure_target);
1370         }
1371       }
1372 
1373       if (op->should_profile()) {
1374         Label done_ok, done_failure;
1375         Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtemp;
1376         typecheck_profile_helper2(md, data, mdo_offset_bias, mdo, recv, res, tmp1,
1377                                   &profile_cast_success, &profile_cast_failure,
1378                                   &done_ok, &done_failure);
1379         __ bind(done_failure);
1380         __ mov(res, 0);
1381         __ b(done);
1382         __ bind(done_ok);
1383         __ mov(res, 1);
1384       }
1385       __ bind(done);
1386       break;
1387     }
1388     default:
1389       ShouldNotReachHere();
1390   }
1391 }
1392 
1393 
1394 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1395   //   if (*addr == cmpval) {
1396   //     *addr = newval;
1397   //     dest = 1;
1398   //   } else {
1399   //     dest = 0;
1400   //   }
1401   // FIXME: membar_release
1402   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
1403   Register addr = op->addr()->is_register() ?
1404     op->addr()->as_pointer_register() :
1405     op->addr()->as_address_ptr()->base()->as_pointer_register();
1406   assert(op->addr()->is_register() || op->addr()->as_address_ptr()->disp() == 0, "unexpected disp");
1407   assert(op->addr()->is_register() || op->addr()->as_address_ptr()->index() == LIR_OprDesc::illegalOpr(), "unexpected index");
1408   if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
1409     Register cmpval = op->cmp_value()->as_register();
1410     Register newval = op->new_value()->as_register();
1411     Register dest = op->result_opr()->as_register();
1412     assert_different_registers(dest, addr, cmpval, newval, Rtemp);
1413 
1414     __ atomic_cas_bool(cmpval, newval, addr, 0, Rtemp); // Rtemp free by default at C1 LIR layer
1415     __ mov(dest, 1, eq);
1416     __ mov(dest, 0, ne);
1417   } else if (op->code() == lir_cas_long) {
1418     assert(VM_Version::supports_cx8(), "wrong machine");
1419     Register cmp_value_lo = op->cmp_value()->as_register_lo();
1420     Register cmp_value_hi = op->cmp_value()->as_register_hi();
1421     Register new_value_lo = op->new_value()->as_register_lo();
1422     Register new_value_hi = op->new_value()->as_register_hi();
1423     Register dest = op->result_opr()->as_register();
1424     Register tmp_lo = op->tmp1()->as_register_lo();
1425     Register tmp_hi = op->tmp1()->as_register_hi();
1426 
1427     assert_different_registers(tmp_lo, tmp_hi, cmp_value_lo, cmp_value_hi, dest, new_value_lo, new_value_hi, addr);
1428     assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
1429     assert(new_value_hi->encoding() == new_value_lo->encoding() + 1, "non aligned register pair");
1430     assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
1431     assert((new_value_lo->encoding() & 0x1) == 0, "misaligned register pair");
1432     __ atomic_cas64(tmp_lo, tmp_hi, dest, cmp_value_lo, cmp_value_hi,
1433                     new_value_lo, new_value_hi, addr, 0);
1434   } else {
1435     Unimplemented();
1436   }
1437   // FIXME: is full membar really needed instead of just membar_acquire?
1438   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1439 }
1440 
1441 
1442 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1443   AsmCondition acond = al;
1444   AsmCondition ncond = nv;
1445   if (opr1 != opr2) {
1446     switch (condition) {
1447       case lir_cond_equal:        acond = eq; ncond = ne; break;
1448       case lir_cond_notEqual:     acond = ne; ncond = eq; break;
1449       case lir_cond_less:         acond = lt; ncond = ge; break;
1450       case lir_cond_lessEqual:    acond = le; ncond = gt; break;
1451       case lir_cond_greaterEqual: acond = ge; ncond = lt; break;
1452       case lir_cond_greater:      acond = gt; ncond = le; break;
1453       case lir_cond_aboveEqual:   acond = hs; ncond = lo; break;
1454       case lir_cond_belowEqual:   acond = ls; ncond = hi; break;
1455       default: ShouldNotReachHere();
1456     }
1457   }
1458 
1459   for (;;) {                         // two iterations only
1460     if (opr1 == result) {
1461       // do nothing
1462     } else if (opr1->is_single_cpu()) {
1463       __ mov(result->as_register(), opr1->as_register(), acond);
1464     } else if (opr1->is_double_cpu()) {
1465       __ long_move(result->as_register_lo(), result->as_register_hi(),
1466                    opr1->as_register_lo(), opr1->as_register_hi(), acond);
1467     } else if (opr1->is_single_stack()) {
1468       __ ldr(result->as_register(), frame_map()->address_for_slot(opr1->single_stack_ix()), acond);
1469     } else if (opr1->is_double_stack()) {
1470       __ ldr(result->as_register_lo(),
1471              frame_map()->address_for_slot(opr1->double_stack_ix(), lo_word_offset_in_bytes), acond);
1472       __ ldr(result->as_register_hi(),
1473              frame_map()->address_for_slot(opr1->double_stack_ix(), hi_word_offset_in_bytes), acond);
1474     } else if (opr1->is_illegal()) {
1475       // do nothing: this part of the cmove has been optimized away in the peephole optimizer
1476     } else {
1477       assert(opr1->is_constant(), "must be");
1478       LIR_Const* c = opr1->as_constant_ptr();
1479 
1480       switch (c->type()) {
1481         case T_INT:
1482           __ mov_slow(result->as_register(), c->as_jint(), acond);
1483           break;
1484         case T_LONG:
1485           __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1486           __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1487           break;
1488         case T_OBJECT:
1489           __ mov_oop(result->as_register(), c->as_jobject(), 0, acond);
1490           break;
1491         case T_FLOAT:
1492 #ifdef __SOFTFP__
1493           // not generated now.
1494           __ mov_slow(result->as_register(), c->as_jint(), acond);
1495 #else
1496           __ mov_float(result->as_float_reg(), c->as_jfloat(), acond);
1497 #endif // __SOFTFP__
1498           break;
1499         case T_DOUBLE:
1500 #ifdef __SOFTFP__
1501           // not generated now.
1502           __ mov_slow(result->as_register_lo(), c->as_jint_lo(), acond);
1503           __ mov_slow(result->as_register_hi(), c->as_jint_hi(), acond);
1504 #else
1505           __ mov_double(result->as_double_reg(), c->as_jdouble(), acond);
1506 #endif // __SOFTFP__
1507           break;
1508         default:
1509           ShouldNotReachHere();
1510       }
1511     }
1512 
1513     // Negate the condition and repeat the algorithm with the second operand
1514     if (opr1 == opr2) { break; }
1515     opr1 = opr2;
1516     acond = ncond;
1517   }
1518 }
1519 
1520 #ifdef ASSERT
1521 static int reg_size(LIR_Opr op) {
1522   switch (op->type()) {
1523   case T_FLOAT:
1524   case T_INT:      return BytesPerInt;
1525   case T_LONG:
1526   case T_DOUBLE:   return BytesPerLong;
1527   case T_OBJECT:
1528   case T_ARRAY:
1529   case T_METADATA: return BytesPerWord;
1530   case T_ADDRESS:
1531   case T_ILLEGAL:  // fall through
1532   default: ShouldNotReachHere(); return -1;
1533   }
1534 }
1535 #endif
1536 
1537 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1538   assert(info == NULL, "unused on this code path");
1539   assert(dest->is_register(), "wrong items state");
1540 
1541   if (right->is_address()) {
1542     // special case for adding shifted/extended register
1543     const Register res = dest->as_pointer_register();
1544     const Register lreg = left->as_pointer_register();
1545     const LIR_Address* addr = right->as_address_ptr();
1546 
1547     assert(addr->base()->as_pointer_register() == lreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1548 
1549     int scale = addr->scale();
1550     AsmShift shift = lsl;
1551 
1552 
1553     assert(reg_size(addr->base()) == reg_size(addr->index()), "should be");
1554     assert(reg_size(addr->base()) == reg_size(dest), "should be");
1555     assert(reg_size(dest) == wordSize, "should be");
1556 
1557     AsmOperand operand(addr->index()->as_pointer_register(), shift, scale);
1558     switch (code) {
1559       case lir_add: __ add(res, lreg, operand); break;
1560       case lir_sub: __ sub(res, lreg, operand); break;
1561       default: ShouldNotReachHere();
1562     }
1563 
1564   } else if (left->is_address()) {
1565     assert(code == lir_sub && right->is_single_cpu(), "special case used by strength_reduce_multiply()");
1566     const LIR_Address* addr = left->as_address_ptr();
1567     const Register res = dest->as_register();
1568     const Register rreg = right->as_register();
1569     assert(addr->base()->as_register() == rreg && addr->index()->is_register() && addr->disp() == 0, "must be");
1570     __ rsb(res, rreg, AsmOperand(addr->index()->as_register(), lsl, addr->scale()));
1571 
1572   } else if (dest->is_single_cpu()) {
1573     assert(left->is_single_cpu(), "unexpected left operand");
1574 
1575     const Register res = dest->as_register();
1576     const Register lreg = left->as_register();
1577 
1578     if (right->is_single_cpu()) {
1579       const Register rreg = right->as_register();
1580       switch (code) {
1581         case lir_add: __ add_32(res, lreg, rreg); break;
1582         case lir_sub: __ sub_32(res, lreg, rreg); break;
1583         case lir_mul: __ mul_32(res, lreg, rreg); break;
1584         default: ShouldNotReachHere();
1585       }
1586     } else {
1587       assert(right->is_constant(), "must be");
1588       const jint c = right->as_constant_ptr()->as_jint();
1589       if (!Assembler::is_arith_imm_in_range(c)) {
1590         BAILOUT("illegal arithmetic operand");
1591       }
1592       switch (code) {
1593         case lir_add: __ add_32(res, lreg, c); break;
1594         case lir_sub: __ sub_32(res, lreg, c); break;
1595         default: ShouldNotReachHere();
1596       }
1597     }
1598 
1599   } else if (dest->is_double_cpu()) {
1600     Register res_lo = dest->as_register_lo();
1601     Register res_hi = dest->as_register_hi();
1602     Register lreg_lo = left->as_register_lo();
1603     Register lreg_hi = left->as_register_hi();
1604     if (right->is_double_cpu()) {
1605       Register rreg_lo = right->as_register_lo();
1606       Register rreg_hi = right->as_register_hi();
1607       if (res_lo == lreg_hi || res_lo == rreg_hi) {
1608         res_lo = Rtemp;
1609       }
1610       switch (code) {
1611         case lir_add:
1612           __ adds(res_lo, lreg_lo, rreg_lo);
1613           __ adc(res_hi, lreg_hi, rreg_hi);
1614           break;
1615         case lir_sub:
1616           __ subs(res_lo, lreg_lo, rreg_lo);
1617           __ sbc(res_hi, lreg_hi, rreg_hi);
1618           break;
1619         default:
1620           ShouldNotReachHere();
1621       }
1622     } else {
1623       assert(right->is_constant(), "must be");
1624       assert((right->as_constant_ptr()->as_jlong() >> 32) == 0, "out of range");
1625       const jint c = (jint) right->as_constant_ptr()->as_jlong();
1626       if (res_lo == lreg_hi) {
1627         res_lo = Rtemp;
1628       }
1629       switch (code) {
1630         case lir_add:
1631           __ adds(res_lo, lreg_lo, c);
1632           __ adc(res_hi, lreg_hi, 0);
1633           break;
1634         case lir_sub:
1635           __ subs(res_lo, lreg_lo, c);
1636           __ sbc(res_hi, lreg_hi, 0);
1637           break;
1638         default:
1639           ShouldNotReachHere();
1640       }
1641     }
1642     move_regs(res_lo, dest->as_register_lo());
1643 
1644   } else if (dest->is_single_fpu()) {
1645     assert(left->is_single_fpu(), "must be");
1646     assert(right->is_single_fpu(), "must be");
1647     const FloatRegister res = dest->as_float_reg();
1648     const FloatRegister lreg = left->as_float_reg();
1649     const FloatRegister rreg = right->as_float_reg();
1650     switch (code) {
1651       case lir_add: __ add_float(res, lreg, rreg); break;
1652       case lir_sub: __ sub_float(res, lreg, rreg); break;
1653       case lir_mul_strictfp: // fall through
1654       case lir_mul: __ mul_float(res, lreg, rreg); break;
1655       case lir_div_strictfp: // fall through
1656       case lir_div: __ div_float(res, lreg, rreg); break;
1657       default: ShouldNotReachHere();
1658     }
1659   } else if (dest->is_double_fpu()) {
1660     assert(left->is_double_fpu(), "must be");
1661     assert(right->is_double_fpu(), "must be");
1662     const FloatRegister res = dest->as_double_reg();
1663     const FloatRegister lreg = left->as_double_reg();
1664     const FloatRegister rreg = right->as_double_reg();
1665     switch (code) {
1666       case lir_add: __ add_double(res, lreg, rreg); break;
1667       case lir_sub: __ sub_double(res, lreg, rreg); break;
1668       case lir_mul_strictfp: // fall through
1669       case lir_mul: __ mul_double(res, lreg, rreg); break;
1670       case lir_div_strictfp: // fall through
1671       case lir_div: __ div_double(res, lreg, rreg); break;
1672       default: ShouldNotReachHere();
1673     }
1674   } else {
1675     ShouldNotReachHere();
1676   }
1677 }
1678 
1679 
1680 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1681   switch (code) {
1682     case lir_abs:
1683       __ abs_double(dest->as_double_reg(), value->as_double_reg());
1684       break;
1685     case lir_sqrt:
1686       __ sqrt_double(dest->as_double_reg(), value->as_double_reg());
1687       break;
1688     default:
1689       ShouldNotReachHere();
1690   }
1691 }
1692 
1693 
1694 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1695   assert(dest->is_register(), "wrong items state");
1696   assert(left->is_register(), "wrong items state");
1697 
1698   if (dest->is_single_cpu()) {
1699 
1700     const Register res = dest->as_register();
1701     const Register lreg = left->as_register();
1702 
1703     if (right->is_single_cpu()) {
1704       const Register rreg = right->as_register();
1705       switch (code) {
1706         case lir_logic_and: __ and_32(res, lreg, rreg); break;
1707         case lir_logic_or:  __ orr_32(res, lreg, rreg); break;
1708         case lir_logic_xor: __ eor_32(res, lreg, rreg); break;
1709         default: ShouldNotReachHere();
1710       }
1711     } else {
1712       assert(right->is_constant(), "must be");
1713       const uint c = (uint)right->as_constant_ptr()->as_jint();
1714       switch (code) {
1715         case lir_logic_and: __ and_32(res, lreg, c); break;
1716         case lir_logic_or:  __ orr_32(res, lreg, c); break;
1717         case lir_logic_xor: __ eor_32(res, lreg, c); break;
1718         default: ShouldNotReachHere();
1719       }
1720     }
1721   } else {
1722     assert(dest->is_double_cpu(), "should be");
1723     Register res_lo = dest->as_register_lo();
1724 
1725     assert (dest->type() == T_LONG, "unexpected result type");
1726     assert (left->type() == T_LONG, "unexpected left type");
1727     assert (right->type() == T_LONG, "unexpected right type");
1728 
1729     const Register res_hi = dest->as_register_hi();
1730     const Register lreg_lo = left->as_register_lo();
1731     const Register lreg_hi = left->as_register_hi();
1732 
1733     if (right->is_register()) {
1734       const Register rreg_lo = right->as_register_lo();
1735       const Register rreg_hi = right->as_register_hi();
1736       if (res_lo == lreg_hi || res_lo == rreg_hi) {
1737         res_lo = Rtemp; // Temp register helps to avoid overlap between result and input
1738       }
1739       switch (code) {
1740         case lir_logic_and:
1741           __ andr(res_lo, lreg_lo, rreg_lo);
1742           __ andr(res_hi, lreg_hi, rreg_hi);
1743           break;
1744         case lir_logic_or:
1745           __ orr(res_lo, lreg_lo, rreg_lo);
1746           __ orr(res_hi, lreg_hi, rreg_hi);
1747           break;
1748         case lir_logic_xor:
1749           __ eor(res_lo, lreg_lo, rreg_lo);
1750           __ eor(res_hi, lreg_hi, rreg_hi);
1751           break;
1752         default:
1753           ShouldNotReachHere();
1754       }
1755       move_regs(res_lo, dest->as_register_lo());
1756     } else {
1757       assert(right->is_constant(), "must be");
1758       const jint c_lo = (jint) right->as_constant_ptr()->as_jlong();
1759       const jint c_hi = (jint) (right->as_constant_ptr()->as_jlong() >> 32);
1760       // Case for logic_or from do_ClassIDIntrinsic()
1761       if (c_hi == 0 && AsmOperand::is_rotated_imm(c_lo)) {
1762         switch (code) {
1763           case lir_logic_and:
1764             __ andr(res_lo, lreg_lo, c_lo);
1765             __ mov(res_hi, 0);
1766             break;
1767           case lir_logic_or:
1768             __ orr(res_lo, lreg_lo, c_lo);
1769             break;
1770           case lir_logic_xor:
1771             __ eor(res_lo, lreg_lo, c_lo);
1772             break;
1773         default:
1774           ShouldNotReachHere();
1775         }
1776       } else if (code == lir_logic_and &&
1777                  c_hi == -1 &&
1778                  (AsmOperand::is_rotated_imm(c_lo) ||
1779                   AsmOperand::is_rotated_imm(~c_lo))) {
1780         // Another case which handles logic_and from do_ClassIDIntrinsic()
1781         if (AsmOperand::is_rotated_imm(c_lo)) {
1782           __ andr(res_lo, lreg_lo, c_lo);
1783         } else {
1784           __ bic(res_lo, lreg_lo, ~c_lo);
1785         }
1786         if (res_hi != lreg_hi) {
1787           __ mov(res_hi, lreg_hi);
1788         }
1789       } else {
1790         BAILOUT("64 bit constant cannot be inlined");
1791       }
1792     }
1793   }
1794 }
1795 
1796 
1797 
1798 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1799   if (opr1->is_single_cpu()) {
1800     if (opr2->is_constant()) {
1801       switch (opr2->as_constant_ptr()->type()) {
1802         case T_INT: {
1803           const jint c = opr2->as_constant_ptr()->as_jint();
1804           if (Assembler::is_arith_imm_in_range(c)) {
1805             __ cmp_32(opr1->as_register(), c);
1806           } else if (Assembler::is_arith_imm_in_range(-c)) {
1807             __ cmn_32(opr1->as_register(), -c);
1808           } else {
1809             // This can happen when compiling lookupswitch
1810             __ mov_slow(Rtemp, c);
1811             __ cmp_32(opr1->as_register(), Rtemp);
1812           }
1813           break;
1814         }
1815         case T_OBJECT:
1816           assert(opr2->as_constant_ptr()->as_jobject() == NULL, "cannot handle otherwise");
1817           __ cmp(opr1->as_register(), 0);
1818           break;
1819         default:
1820           ShouldNotReachHere();
1821       }
1822     } else if (opr2->is_single_cpu()) {
1823       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1824         assert(opr2->type() == T_OBJECT || opr2->type() == T_ARRAY, "incompatibe type");
1825         __ cmpoop(opr1->as_register(), opr2->as_register());
1826       } else if (opr1->type() == T_METADATA || opr1->type() == T_ADDRESS) {
1827         assert(opr2->type() == T_METADATA || opr2->type() == T_ADDRESS, "incompatibe type");
1828         __ cmp(opr1->as_register(), opr2->as_register());
1829       } else {
1830         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY && opr2->type() != T_METADATA && opr2->type() != T_ADDRESS, "incompatibe type");
1831         __ cmp_32(opr1->as_register(), opr2->as_register());
1832       }
1833     } else {
1834       ShouldNotReachHere();
1835     }
1836   } else if (opr1->is_double_cpu()) {
1837     Register xlo = opr1->as_register_lo();
1838     Register xhi = opr1->as_register_hi();
1839     if (opr2->is_constant() && opr2->as_jlong() == 0) {
1840       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "cannot handle otherwise");
1841       __ orrs(Rtemp, xlo, xhi);
1842     } else if (opr2->is_register()) {
1843       Register ylo = opr2->as_register_lo();
1844       Register yhi = opr2->as_register_hi();
1845       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
1846         __ teq(xhi, yhi);
1847         __ teq(xlo, ylo, eq);
1848       } else {
1849         __ subs(xlo, xlo, ylo);
1850         __ sbcs(xhi, xhi, yhi);
1851       }
1852     } else {
1853       ShouldNotReachHere();
1854     }
1855   } else if (opr1->is_single_fpu()) {
1856     if (opr2->is_constant()) {
1857       assert(opr2->as_jfloat() == 0.0f, "cannot handle otherwise");
1858       __ cmp_zero_float(opr1->as_float_reg());
1859     } else {
1860       __ cmp_float(opr1->as_float_reg(), opr2->as_float_reg());
1861     }
1862   } else if (opr1->is_double_fpu()) {
1863     if (opr2->is_constant()) {
1864       assert(opr2->as_jdouble() == 0.0, "cannot handle otherwise");
1865       __ cmp_zero_double(opr1->as_double_reg());
1866     } else {
1867       __ cmp_double(opr1->as_double_reg(), opr2->as_double_reg());
1868     }
1869   } else {
1870     ShouldNotReachHere();
1871   }
1872 }
1873 
1874 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1875   const Register res = dst->as_register();
1876   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1877     comp_op(lir_cond_unknown, left, right, op);
1878     __ fmstat();
1879     if (code == lir_ucmp_fd2i) {  // unordered is less
1880       __ mvn(res, 0, lt);
1881       __ mov(res, 1, ge);
1882     } else {                      // unordered is greater
1883       __ mov(res, 1, cs);
1884       __ mvn(res, 0, cc);
1885     }
1886     __ mov(res, 0, eq);
1887 
1888   } else {
1889     assert(code == lir_cmp_l2i, "must be");
1890 
1891     Label done;
1892     const Register xlo = left->as_register_lo();
1893     const Register xhi = left->as_register_hi();
1894     const Register ylo = right->as_register_lo();
1895     const Register yhi = right->as_register_hi();
1896     __ cmp(xhi, yhi);
1897     __ mov(res, 1, gt);
1898     __ mvn(res, 0, lt);
1899     __ b(done, ne);
1900     __ subs(res, xlo, ylo);
1901     __ mov(res, 1, hi);
1902     __ mvn(res, 0, lo);
1903     __ bind(done);
1904   }
1905 }
1906 
1907 
1908 void LIR_Assembler::align_call(LIR_Code code) {
1909   // Not needed
1910 }
1911 
1912 
1913 void LIR_Assembler::call(LIR_OpJavaCall *op, relocInfo::relocType rtype) {
1914   int ret_addr_offset = __ patchable_call(op->addr(), rtype);
1915   assert(ret_addr_offset == __ offset(), "embedded return address not allowed");
1916   add_call_info_here(op->info());
1917 }
1918 
1919 
1920 void LIR_Assembler::ic_call(LIR_OpJavaCall *op) {
1921   bool near_range = __ cache_fully_reachable();
1922   address oop_address = pc();
1923 
1924   bool use_movw = VM_Version::supports_movw();
1925 
1926   // Ricklass may contain something that is not a metadata pointer so
1927   // mov_metadata can't be used
1928   InlinedAddress value((address)Universe::non_oop_word());
1929   InlinedAddress addr(op->addr());
1930   if (use_movw) {
1931     __ movw(Ricklass, ((unsigned int)Universe::non_oop_word()) & 0xffff);
1932     __ movt(Ricklass, ((unsigned int)Universe::non_oop_word()) >> 16);
1933   } else {
1934     // No movw/movt, must be load a pc relative value but no
1935     // relocation so no metadata table to load from.
1936     // Use a b instruction rather than a bl, inline constant after the
1937     // branch, use a PC relative ldr to load the constant, arrange for
1938     // the call to return after the constant(s).
1939     __ ldr_literal(Ricklass, value);
1940   }
1941   __ relocate(virtual_call_Relocation::spec(oop_address));
1942   if (near_range && use_movw) {
1943     __ bl(op->addr());
1944   } else {
1945     Label call_return;
1946     __ adr(LR, call_return);
1947     if (near_range) {
1948       __ b(op->addr());
1949     } else {
1950       __ indirect_jump(addr, Rtemp);
1951       __ bind_literal(addr);
1952     }
1953     if (!use_movw) {
1954       __ bind_literal(value);
1955     }
1956     __ bind(call_return);
1957   }
1958   add_call_info(code_offset(), op->info());
1959 }
1960 
1961 
1962 /* Currently, vtable-dispatch is only enabled for sparc platforms */
1963 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
1964   ShouldNotReachHere();
1965 }
1966 
1967 void LIR_Assembler::emit_static_call_stub() {
1968   address call_pc = __ pc();
1969   address stub = __ start_a_stub(call_stub_size());
1970   if (stub == NULL) {
1971     BAILOUT("static call stub overflow");
1972   }
1973 
1974   DEBUG_ONLY(int offset = code_offset();)
1975 
1976   InlinedMetadata metadata_literal(NULL);
1977   __ relocate(static_stub_Relocation::spec(call_pc));
1978   // If not a single instruction, NativeMovConstReg::next_instruction_address()
1979   // must jump over the whole following ldr_literal.
1980   // (See CompiledStaticCall::set_to_interpreted())
1981 #ifdef ASSERT
1982   address ldr_site = __ pc();
1983 #endif
1984   __ ldr_literal(Rmethod, metadata_literal);
1985   assert(nativeMovConstReg_at(ldr_site)->next_instruction_address() == __ pc(), "Fix ldr_literal or its parsing");
1986   bool near_range = __ cache_fully_reachable();
1987   InlinedAddress dest((address)-1);
1988   if (near_range) {
1989     address branch_site = __ pc();
1990     __ b(branch_site); // b to self maps to special NativeJump -1 destination
1991   } else {
1992     __ indirect_jump(dest, Rtemp);
1993   }
1994   __ bind_literal(metadata_literal); // includes spec_for_immediate reloc
1995   if (!near_range) {
1996     __ bind_literal(dest); // special NativeJump -1 destination
1997   }
1998 
1999   assert(code_offset() - offset <= call_stub_size(), "overflow");
2000   __ end_a_stub();
2001 }
2002 
2003 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2004   assert(exceptionOop->as_register() == Rexception_obj, "must match");
2005   assert(exceptionPC->as_register()  == Rexception_pc, "must match");
2006   info->add_register_oop(exceptionOop);
2007 
2008   Runtime1::StubID handle_id = compilation()->has_fpu_code() ?
2009                                Runtime1::handle_exception_id :
2010                                Runtime1::handle_exception_nofpu_id;
2011   Label return_address;
2012   __ adr(Rexception_pc, return_address);
2013   __ call(Runtime1::entry_for(handle_id), relocInfo::runtime_call_type);
2014   __ bind(return_address);
2015   add_call_info_here(info);  // for exception handler
2016 }
2017 
2018 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2019   assert(exceptionOop->as_register() == Rexception_obj, "must match");
2020   __ b(_unwind_handler_entry);
2021 }
2022 
2023 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2024   AsmShift shift = lsl;
2025   switch (code) {
2026     case lir_shl:  shift = lsl; break;
2027     case lir_shr:  shift = asr; break;
2028     case lir_ushr: shift = lsr; break;
2029     default: ShouldNotReachHere();
2030   }
2031 
2032   if (dest->is_single_cpu()) {
2033     __ andr(Rtemp, count->as_register(), 31);
2034     __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, Rtemp));
2035   } else if (dest->is_double_cpu()) {
2036     Register dest_lo = dest->as_register_lo();
2037     Register dest_hi = dest->as_register_hi();
2038     Register src_lo  = left->as_register_lo();
2039     Register src_hi  = left->as_register_hi();
2040     Register Rcount  = count->as_register();
2041     // Resolve possible register conflicts
2042     if (shift == lsl && dest_hi == src_lo) {
2043       dest_hi = Rtemp;
2044     } else if (shift != lsl && dest_lo == src_hi) {
2045       dest_lo = Rtemp;
2046     } else if (dest_lo == src_lo && dest_hi == src_hi) {
2047       dest_lo = Rtemp;
2048     } else if (dest_lo == Rcount || dest_hi == Rcount) {
2049       Rcount = Rtemp;
2050     }
2051     __ andr(Rcount, count->as_register(), 63);
2052     __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, Rcount);
2053     move_regs(dest_lo, dest->as_register_lo());
2054     move_regs(dest_hi, dest->as_register_hi());
2055   } else {
2056     ShouldNotReachHere();
2057   }
2058 }
2059 
2060 
2061 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2062   AsmShift shift = lsl;
2063   switch (code) {
2064     case lir_shl:  shift = lsl; break;
2065     case lir_shr:  shift = asr; break;
2066     case lir_ushr: shift = lsr; break;
2067     default: ShouldNotReachHere();
2068   }
2069 
2070   if (dest->is_single_cpu()) {
2071     count &= 31;
2072     if (count != 0) {
2073       __ mov(dest->as_register(), AsmOperand(left->as_register(), shift, count));
2074     } else {
2075       move_regs(left->as_register(), dest->as_register());
2076     }
2077   } else if (dest->is_double_cpu()) {
2078     count &= 63;
2079     if (count != 0) {
2080       Register dest_lo = dest->as_register_lo();
2081       Register dest_hi = dest->as_register_hi();
2082       Register src_lo  = left->as_register_lo();
2083       Register src_hi  = left->as_register_hi();
2084       // Resolve possible register conflicts
2085       if (shift == lsl && dest_hi == src_lo) {
2086         dest_hi = Rtemp;
2087       } else if (shift != lsl && dest_lo == src_hi) {
2088         dest_lo = Rtemp;
2089       }
2090       __ long_shift(dest_lo, dest_hi, src_lo, src_hi, shift, count);
2091       move_regs(dest_lo, dest->as_register_lo());
2092       move_regs(dest_hi, dest->as_register_hi());
2093     } else {
2094       __ long_move(dest->as_register_lo(), dest->as_register_hi(),
2095                    left->as_register_lo(), left->as_register_hi());
2096     }
2097   } else {
2098     ShouldNotReachHere();
2099   }
2100 }
2101 
2102 
2103 // Saves 4 given registers in reserved argument area.
2104 void LIR_Assembler::save_in_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2105   verify_reserved_argument_area_size(4);
2106   __ stmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4));
2107 }
2108 
2109 // Restores 4 given registers from reserved argument area.
2110 void LIR_Assembler::restore_from_reserved_area(Register r1, Register r2, Register r3, Register r4) {
2111   __ ldmia(SP, RegisterSet(r1) | RegisterSet(r2) | RegisterSet(r3) | RegisterSet(r4), no_writeback);
2112 }
2113 
2114 
2115 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2116   ciArrayKlass* default_type = op->expected_type();
2117   Register src = op->src()->as_register();
2118   Register src_pos = op->src_pos()->as_register();
2119   Register dst = op->dst()->as_register();
2120   Register dst_pos = op->dst_pos()->as_register();
2121   Register length  = op->length()->as_register();
2122   Register tmp = op->tmp()->as_register();
2123   Register tmp2 = Rtemp;
2124 
2125   assert(src == R0 && src_pos == R1 && dst == R2 && dst_pos == R3, "code assumption");
2126 
2127   __ resolve(ACCESS_READ, src);
2128   __ resolve(ACCESS_WRITE, dst);
2129 
2130   CodeStub* stub = op->stub();
2131 
2132   int flags = op->flags();
2133   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2134   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
2135 
2136   // If we don't know anything or it's an object array, just go through the generic arraycopy
2137   if (default_type == NULL) {
2138 
2139     // save arguments, because they will be killed by a runtime call
2140     save_in_reserved_area(R0, R1, R2, R3);
2141 
2142     // pass length argument on SP[0]
2143     __ str(length, Address(SP, -2*wordSize, pre_indexed));  // 2 words for a proper stack alignment
2144 
2145     address copyfunc_addr = StubRoutines::generic_arraycopy();
2146     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2147 #ifndef PRODUCT
2148     if (PrintC1Statistics) {
2149       __ inc_counter((address)&Runtime1::_generic_arraycopystub_cnt, tmp, tmp2);
2150     }
2151 #endif // !PRODUCT
2152     // the stub is in the code cache so close enough
2153     __ call(copyfunc_addr, relocInfo::runtime_call_type);
2154 
2155     __ add(SP, SP, 2*wordSize);
2156 
2157     __ cbz_32(R0, *stub->continuation());
2158 
2159     __ mvn_32(tmp, R0);
2160     restore_from_reserved_area(R0, R1, R2, R3);  // load saved arguments in slow case only
2161     __ sub_32(length, length, tmp);
2162     __ add_32(src_pos, src_pos, tmp);
2163     __ add_32(dst_pos, dst_pos, tmp);
2164 
2165     __ b(*stub->entry());
2166 
2167     __ bind(*stub->continuation());
2168     return;
2169   }
2170 
2171   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(),
2172          "must be true at this point");
2173   int elem_size = type2aelembytes(basic_type);
2174   int shift = exact_log2(elem_size);
2175 
2176   // Check for NULL
2177   if (flags & LIR_OpArrayCopy::src_null_check) {
2178     if (flags & LIR_OpArrayCopy::dst_null_check) {
2179       __ cmp(src, 0);
2180       __ cond_cmp(dst, 0, ne);  // make one instruction shorter if both checks are needed
2181       __ b(*stub->entry(), eq);
2182     } else {
2183       __ cbz(src, *stub->entry());
2184     }
2185   } else if (flags & LIR_OpArrayCopy::dst_null_check) {
2186     __ cbz(dst, *stub->entry());
2187   }
2188 
2189   // If the compiler was not able to prove that exact type of the source or the destination
2190   // of the arraycopy is an array type, check at runtime if the source or the destination is
2191   // an instance type.
2192   if (flags & LIR_OpArrayCopy::type_check) {
2193     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2194       __ load_klass(tmp, dst);
2195       __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2196       __ mov_slow(tmp, Klass::_lh_neutral_value);
2197       __ cmp_32(tmp2, tmp);
2198       __ b(*stub->entry(), ge);
2199     }
2200 
2201     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2202       __ load_klass(tmp, src);
2203       __ ldr_u32(tmp2, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2204       __ mov_slow(tmp, Klass::_lh_neutral_value);
2205       __ cmp_32(tmp2, tmp);
2206       __ b(*stub->entry(), ge);
2207     }
2208   }
2209 
2210   // Check if negative
2211   const int all_positive_checks = LIR_OpArrayCopy::src_pos_positive_check |
2212                                   LIR_OpArrayCopy::dst_pos_positive_check |
2213                                   LIR_OpArrayCopy::length_positive_check;
2214   switch (flags & all_positive_checks) {
2215     case LIR_OpArrayCopy::src_pos_positive_check:
2216       __ branch_if_negative_32(src_pos, *stub->entry());
2217       break;
2218     case LIR_OpArrayCopy::dst_pos_positive_check:
2219       __ branch_if_negative_32(dst_pos, *stub->entry());
2220       break;
2221     case LIR_OpArrayCopy::length_positive_check:
2222       __ branch_if_negative_32(length, *stub->entry());
2223       break;
2224     case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::dst_pos_positive_check:
2225       __ branch_if_any_negative_32(src_pos, dst_pos, tmp, *stub->entry());
2226       break;
2227     case LIR_OpArrayCopy::src_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2228       __ branch_if_any_negative_32(src_pos, length, tmp, *stub->entry());
2229       break;
2230     case LIR_OpArrayCopy::dst_pos_positive_check | LIR_OpArrayCopy::length_positive_check:
2231       __ branch_if_any_negative_32(dst_pos, length, tmp, *stub->entry());
2232       break;
2233     case all_positive_checks:
2234       __ branch_if_any_negative_32(src_pos, dst_pos, length, tmp, *stub->entry());
2235       break;
2236     default:
2237       assert((flags & all_positive_checks) == 0, "the last option");
2238   }
2239 
2240   // Range checks
2241   if (flags & LIR_OpArrayCopy::src_range_check) {
2242     __ ldr_s32(tmp2, Address(src, arrayOopDesc::length_offset_in_bytes()));
2243     __ add_32(tmp, src_pos, length);
2244     __ cmp_32(tmp, tmp2);
2245     __ b(*stub->entry(), hi);
2246   }
2247   if (flags & LIR_OpArrayCopy::dst_range_check) {
2248     __ ldr_s32(tmp2, Address(dst, arrayOopDesc::length_offset_in_bytes()));
2249     __ add_32(tmp, dst_pos, length);
2250     __ cmp_32(tmp, tmp2);
2251     __ b(*stub->entry(), hi);
2252   }
2253 
2254   // Check if src and dst are of the same type
2255   if (flags & LIR_OpArrayCopy::type_check) {
2256     // We don't know the array types are compatible
2257     if (basic_type != T_OBJECT) {
2258       // Simple test for basic type arrays
2259       if (UseCompressedClassPointers) {
2260         // We don't need decode because we just need to compare
2261         __ ldr_u32(tmp, Address(src, oopDesc::klass_offset_in_bytes()));
2262         __ ldr_u32(tmp2, Address(dst, oopDesc::klass_offset_in_bytes()));
2263         __ cmp_32(tmp, tmp2);
2264       } else {
2265         __ load_klass(tmp, src);
2266         __ load_klass(tmp2, dst);
2267         __ cmp(tmp, tmp2);
2268       }
2269       __ b(*stub->entry(), ne);
2270     } else {
2271       // For object arrays, if src is a sub class of dst then we can
2272       // safely do the copy.
2273       Label cont, slow;
2274 
2275       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2276 
2277       __ load_klass(tmp, src);
2278       __ load_klass(tmp2, dst);
2279 
2280       // We are at a call so all live registers are saved before we
2281       // get here
2282       assert_different_registers(tmp, tmp2, R6, altFP_7_11);
2283 
2284       __ check_klass_subtype_fast_path(tmp, tmp2, R6, altFP_7_11, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL);
2285 
2286       __ mov(R6, R0);
2287       __ mov(altFP_7_11, R1);
2288       __ mov(R0, tmp);
2289       __ mov(R1, tmp2);
2290       __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); // does not blow any registers except R0, LR and Rtemp
2291       __ cmp_32(R0, 0);
2292       __ mov(R0, R6);
2293       __ mov(R1, altFP_7_11);
2294 
2295       if (copyfunc_addr != NULL) { // use stub if available
2296         // src is not a sub class of dst so we have to do a
2297         // per-element check.
2298 
2299         __ b(cont, ne);
2300 
2301         __ bind(slow);
2302 
2303         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2304         if ((flags & mask) != mask) {
2305           // Check that at least both of them object arrays.
2306           assert(flags & mask, "one of the two should be known to be an object array");
2307 
2308           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2309             __ load_klass(tmp, src);
2310           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2311             __ load_klass(tmp, dst);
2312           }
2313           int lh_offset = in_bytes(Klass::layout_helper_offset());
2314 
2315           __ ldr_u32(tmp2, Address(tmp, lh_offset));
2316 
2317           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2318           __ mov_slow(tmp, objArray_lh);
2319           __ cmp_32(tmp, tmp2);
2320           __ b(*stub->entry(), ne);
2321         }
2322 
2323         save_in_reserved_area(R0, R1, R2, R3);
2324 
2325         Register src_ptr = R0;
2326         Register dst_ptr = R1;
2327         Register len     = R2;
2328         Register chk_off = R3;
2329         Register super_k = tmp;
2330 
2331         __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2332         __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2333 
2334         __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2335         __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2336         __ load_klass(tmp, dst);
2337 
2338         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2339         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2340 
2341         __ ldr(super_k, Address(tmp, ek_offset));
2342 
2343         __ mov(len, length);
2344         __ ldr_u32(chk_off, Address(super_k, sco_offset));
2345         __ push(super_k);
2346 
2347         __ call(copyfunc_addr, relocInfo::runtime_call_type);
2348 
2349 #ifndef PRODUCT
2350         if (PrintC1Statistics) {
2351           Label failed;
2352           __ cbnz_32(R0, failed);
2353           __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, tmp, tmp2);
2354           __ bind(failed);
2355         }
2356 #endif // PRODUCT
2357 
2358         __ add(SP, SP, wordSize);  // Drop super_k argument
2359 
2360         __ cbz_32(R0, *stub->continuation());
2361         __ mvn_32(tmp, R0);
2362 
2363         // load saved arguments in slow case only
2364         restore_from_reserved_area(R0, R1, R2, R3);
2365 
2366         __ sub_32(length, length, tmp);
2367         __ add_32(src_pos, src_pos, tmp);
2368         __ add_32(dst_pos, dst_pos, tmp);
2369 
2370 #ifndef PRODUCT
2371         if (PrintC1Statistics) {
2372           __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, tmp, tmp2);
2373         }
2374 #endif
2375 
2376         __ b(*stub->entry());
2377 
2378         __ bind(cont);
2379       } else {
2380         __ b(*stub->entry(), eq);
2381         __ bind(cont);
2382       }
2383     }
2384   }
2385 
2386 #ifndef PRODUCT
2387   if (PrintC1Statistics) {
2388     address counter = Runtime1::arraycopy_count_address(basic_type);
2389     __ inc_counter(counter, tmp, tmp2);
2390   }
2391 #endif // !PRODUCT
2392 
2393   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2394   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2395   const char *name;
2396   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2397 
2398   Register src_ptr = R0;
2399   Register dst_ptr = R1;
2400   Register len     = R2;
2401 
2402   __ add(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2403   __ add_ptr_scaled_int32(src_ptr, src_ptr, src_pos, shift);
2404 
2405   __ add(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2406   __ add_ptr_scaled_int32(dst_ptr, dst_ptr, dst_pos, shift);
2407 
2408   __ mov(len, length);
2409 
2410   __ call(entry, relocInfo::runtime_call_type);
2411 
2412   __ bind(*stub->continuation());
2413 }
2414 
2415 #ifdef ASSERT
2416  // emit run-time assertion
2417 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2418   assert(op->code() == lir_assert, "must be");
2419 
2420   if (op->in_opr1()->is_valid()) {
2421     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2422     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2423   } else {
2424     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2425     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2426   }
2427 
2428   Label ok;
2429   if (op->condition() != lir_cond_always) {
2430     AsmCondition acond = al;
2431     switch (op->condition()) {
2432       case lir_cond_equal:        acond = eq; break;
2433       case lir_cond_notEqual:     acond = ne; break;
2434       case lir_cond_less:         acond = lt; break;
2435       case lir_cond_lessEqual:    acond = le; break;
2436       case lir_cond_greaterEqual: acond = ge; break;
2437       case lir_cond_greater:      acond = gt; break;
2438       case lir_cond_aboveEqual:   acond = hs; break;
2439       case lir_cond_belowEqual:   acond = ls; break;
2440       default:                    ShouldNotReachHere();
2441     }
2442     __ b(ok, acond);
2443   }
2444   if (op->halt()) {
2445     const char* str = __ code_string(op->msg());
2446     __ stop(str);
2447   } else {
2448     breakpoint();
2449   }
2450   __ bind(ok);
2451 }
2452 #endif // ASSERT
2453 
2454 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2455   fatal("CRC32 intrinsic is not implemented on this platform");
2456 }
2457 
2458 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2459   Register obj = op->obj_opr()->as_pointer_register();
2460   Register hdr = op->hdr_opr()->as_pointer_register();
2461   Register lock = op->lock_opr()->as_pointer_register();
2462   Register tmp = op->scratch_opr()->is_illegal() ? noreg :
2463                  op->scratch_opr()->as_pointer_register();
2464 
2465   if (!UseFastLocking) {
2466     __ b(*op->stub()->entry());
2467   } else if (op->code() == lir_lock) {
2468     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2469     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
2470     int null_check_offset = __ lock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2471     if (op->info() != NULL) {
2472       add_debug_info_for_null_check(null_check_offset, op->info());
2473     }
2474   } else if (op->code() == lir_unlock) {
2475     __ unlock_object(hdr, obj, lock, tmp, *op->stub()->entry());
2476   } else {
2477     ShouldNotReachHere();
2478   }
2479   __ bind(*op->stub()->continuation());
2480 }
2481 
2482 
2483 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2484   ciMethod* method = op->profiled_method();
2485   int bci          = op->profiled_bci();
2486   ciMethod* callee = op->profiled_callee();
2487 
2488   // Update counter for all call types
2489   ciMethodData* md = method->method_data_or_null();
2490   assert(md != NULL, "Sanity");
2491   ciProfileData* data = md->bci_to_data(bci);
2492   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2493   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2494   Register mdo  = op->mdo()->as_register();
2495   assert(op->tmp1()->is_register(), "tmp1 must be allocated");
2496   Register tmp1 = op->tmp1()->as_pointer_register();
2497   assert_different_registers(mdo, tmp1);
2498   __ mov_metadata(mdo, md->constant_encoding());
2499   int mdo_offset_bias = 0;
2500   int max_offset = 4096;
2501   if (md->byte_offset_of_slot(data, CounterData::count_offset()) + data->size_in_bytes() >= max_offset) {
2502     // The offset is large so bias the mdo by the base of the slot so
2503     // that the ldr can use an immediate offset to reference the slots of the data
2504     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2505     __ mov_slow(tmp1, mdo_offset_bias);
2506     __ add(mdo, mdo, tmp1);
2507   }
2508 
2509   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2510   // Perform additional virtual call profiling for invokevirtual and
2511   // invokeinterface bytecodes
2512   if (op->should_profile_receiver_type()) {
2513     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2514     Register recv = op->recv()->as_register();
2515     assert_different_registers(mdo, tmp1, recv);
2516     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2517     ciKlass* known_klass = op->known_holder();
2518     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2519       // We know the type that will be seen at this call site; we can
2520       // statically update the MethodData* rather than needing to do
2521       // dynamic tests on the receiver type
2522 
2523       // NOTE: we should probably put a lock around this search to
2524       // avoid collisions by concurrent compilations
2525       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2526       uint i;
2527       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2528         ciKlass* receiver = vc_data->receiver(i);
2529         if (known_klass->equals(receiver)) {
2530           Address data_addr(mdo, md->byte_offset_of_slot(data,
2531                                                          VirtualCallData::receiver_count_offset(i)) -
2532                             mdo_offset_bias);
2533           __ ldr(tmp1, data_addr);
2534           __ add(tmp1, tmp1, DataLayout::counter_increment);
2535           __ str(tmp1, data_addr);
2536           return;
2537         }
2538       }
2539 
2540       // Receiver type not found in profile data; select an empty slot
2541 
2542       // Note that this is less efficient than it should be because it
2543       // always does a write to the receiver part of the
2544       // VirtualCallData rather than just the first time
2545       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2546         ciKlass* receiver = vc_data->receiver(i);
2547         if (receiver == NULL) {
2548           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) -
2549                             mdo_offset_bias);
2550           __ mov_metadata(tmp1, known_klass->constant_encoding());
2551           __ str(tmp1, recv_addr);
2552           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) -
2553                             mdo_offset_bias);
2554           __ ldr(tmp1, data_addr);
2555           __ add(tmp1, tmp1, DataLayout::counter_increment);
2556           __ str(tmp1, data_addr);
2557           return;
2558         }
2559       }
2560     } else {
2561       __ load_klass(recv, recv);
2562       Label update_done;
2563       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2564       // Receiver did not match any saved receiver and there is no empty row for it.
2565       // Increment total counter to indicate polymorphic case.
2566       __ ldr(tmp1, counter_addr);
2567       __ add(tmp1, tmp1, DataLayout::counter_increment);
2568       __ str(tmp1, counter_addr);
2569 
2570       __ bind(update_done);
2571     }
2572   } else {
2573     // Static call
2574     __ ldr(tmp1, counter_addr);
2575     __ add(tmp1, tmp1, DataLayout::counter_increment);
2576     __ str(tmp1, counter_addr);
2577   }
2578 }
2579 
2580 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2581   fatal("Type profiling not implemented on this platform");
2582 }
2583 
2584 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2585   Unimplemented();
2586 }
2587 
2588 
2589 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2590   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2591   __ add_slow(dst->as_pointer_register(), mon_addr.base(), mon_addr.disp());
2592 }
2593 
2594 
2595 void LIR_Assembler::align_backward_branch_target() {
2596   // Some ARM processors do better with 8-byte branch target alignment
2597   __ align(8);
2598 }
2599 
2600 
2601 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2602   // tmp must be unused
2603   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2604 
2605   if (left->is_single_cpu()) {
2606     assert (dest->type() == T_INT, "unexpected result type");
2607     assert (left->type() == T_INT, "unexpected left type");
2608     __ neg_32(dest->as_register(), left->as_register());
2609   } else if (left->is_double_cpu()) {
2610     Register dest_lo = dest->as_register_lo();
2611     Register dest_hi = dest->as_register_hi();
2612     Register src_lo = left->as_register_lo();
2613     Register src_hi = left->as_register_hi();
2614     if (dest_lo == src_hi) {
2615       dest_lo = Rtemp;
2616     }
2617     __ rsbs(dest_lo, src_lo, 0);
2618     __ rsc(dest_hi, src_hi, 0);
2619     move_regs(dest_lo, dest->as_register_lo());
2620   } else if (left->is_single_fpu()) {
2621     __ neg_float(dest->as_float_reg(), left->as_float_reg());
2622   } else if (left->is_double_fpu()) {
2623     __ neg_double(dest->as_double_reg(), left->as_double_reg());
2624   } else {
2625     ShouldNotReachHere();
2626   }
2627 }
2628 
2629 
2630 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2631   assert(patch_code == lir_patch_none, "Patch code not supported");
2632   LIR_Address* addr = addr_opr->as_address_ptr();
2633   if (addr->index()->is_illegal()) {
2634     jint c = addr->disp();
2635     if (!Assembler::is_arith_imm_in_range(c)) {
2636       BAILOUT("illegal arithmetic operand");
2637     }
2638     __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(), c);
2639   } else {
2640     assert(addr->disp() == 0, "cannot handle otherwise");
2641     __ add(dest->as_pointer_register(), addr->base()->as_pointer_register(),
2642            AsmOperand(addr->index()->as_pointer_register(), lsl, addr->scale()));
2643   }
2644 }
2645 
2646 
2647 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2648   assert(!tmp->is_valid(), "don't need temporary");
2649   __ call(dest);
2650   if (info != NULL) {
2651     add_call_info_here(info);
2652   }
2653 }
2654 
2655 
2656 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2657   assert(src->is_double_cpu() && dest->is_address() ||
2658          src->is_address() && dest->is_double_cpu(),
2659          "Simple move_op is called for all other cases");
2660 
2661   int null_check_offset;
2662   if (dest->is_address()) {
2663     // Store
2664     const LIR_Address* addr = dest->as_address_ptr();
2665     const Register src_lo = src->as_register_lo();
2666     const Register src_hi = src->as_register_hi();
2667     assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2668 
2669     if (src_lo < src_hi) {
2670       null_check_offset = __ offset();
2671       __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(src_hi));
2672     } else {
2673       assert(src_lo < Rtemp, "Rtemp is higher than any allocatable register");
2674       __ mov(Rtemp, src_hi);
2675       null_check_offset = __ offset();
2676       __ stmia(addr->base()->as_register(), RegisterSet(src_lo) | RegisterSet(Rtemp));
2677     }
2678   } else {
2679     // Load
2680     const LIR_Address* addr = src->as_address_ptr();
2681     const Register dest_lo = dest->as_register_lo();
2682     const Register dest_hi = dest->as_register_hi();
2683     assert(addr->index()->is_illegal() && addr->disp() == 0, "The address is simple already");
2684 
2685     null_check_offset = __ offset();
2686     if (dest_lo < dest_hi) {
2687       __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(dest_hi));
2688     } else {
2689       assert(dest_lo < Rtemp, "Rtemp is higher than any allocatable register");
2690       __ ldmia(addr->base()->as_register(), RegisterSet(dest_lo) | RegisterSet(Rtemp));
2691       __ mov(dest_hi, Rtemp);
2692     }
2693   }
2694 
2695   if (info != NULL) {
2696     add_debug_info_for_null_check(null_check_offset, info);
2697   }
2698 }
2699 
2700 
2701 void LIR_Assembler::membar() {
2702   __ membar(MacroAssembler::StoreLoad, Rtemp);
2703 }
2704 
2705 void LIR_Assembler::membar_acquire() {
2706   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::LoadLoad | MacroAssembler::LoadStore), Rtemp);
2707 }
2708 
2709 void LIR_Assembler::membar_release() {
2710   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2711 }
2712 
2713 void LIR_Assembler::membar_loadload() {
2714   __ membar(MacroAssembler::LoadLoad, Rtemp);
2715 }
2716 
2717 void LIR_Assembler::membar_storestore() {
2718   __ membar(MacroAssembler::StoreStore, Rtemp);
2719 }
2720 
2721 void LIR_Assembler::membar_loadstore() {
2722   __ membar(MacroAssembler::LoadStore, Rtemp);
2723 }
2724 
2725 void LIR_Assembler::membar_storeload() {
2726   __ membar(MacroAssembler::StoreLoad, Rtemp);
2727 }
2728 
2729 void LIR_Assembler::on_spin_wait() {
2730   Unimplemented();
2731 }
2732 
2733 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2734   // Not used on ARM
2735   Unimplemented();
2736 }
2737 
2738 void LIR_Assembler::peephole(LIR_List* lir) {
2739   LIR_OpList* inst = lir->instructions_list();
2740   const int inst_length = inst->length();
2741   for (int i = 0; i < inst_length; i++) {
2742     LIR_Op* op = inst->at(i);
2743     switch (op->code()) {
2744       case lir_cmp: {
2745         // Replace:
2746         //   cmp rX, y
2747         //   cmove [EQ] y, z, rX
2748         // with
2749         //   cmp rX, y
2750         //   cmove [EQ] illegalOpr, z, rX
2751         //
2752         // or
2753         //   cmp rX, y
2754         //   cmove [NE] z, y, rX
2755         // with
2756         //   cmp rX, y
2757         //   cmove [NE] z, illegalOpr, rX
2758         //
2759         // moves from illegalOpr should be removed when converting LIR to native assembly
2760 
2761         LIR_Op2* cmp = op->as_Op2();
2762         assert(cmp != NULL, "cmp LIR instruction is not an op2");
2763 
2764         if (i + 1 < inst_length) {
2765           LIR_Op2* cmove = inst->at(i + 1)->as_Op2();
2766           if (cmove != NULL && cmove->code() == lir_cmove) {
2767             LIR_Opr cmove_res = cmove->result_opr();
2768             bool res_is_op1 = cmove_res == cmp->in_opr1();
2769             bool res_is_op2 = cmove_res == cmp->in_opr2();
2770             LIR_Opr cmp_res, cmp_arg;
2771             if (res_is_op1) {
2772               cmp_res = cmp->in_opr1();
2773               cmp_arg = cmp->in_opr2();
2774             } else if (res_is_op2) {
2775               cmp_res = cmp->in_opr2();
2776               cmp_arg = cmp->in_opr1();
2777             } else {
2778               cmp_res = LIR_OprFact::illegalOpr;
2779               cmp_arg = LIR_OprFact::illegalOpr;
2780             }
2781 
2782             if (cmp_res != LIR_OprFact::illegalOpr) {
2783               LIR_Condition cond = cmove->condition();
2784               if (cond == lir_cond_equal && cmove->in_opr1() == cmp_arg) {
2785                 cmove->set_in_opr1(LIR_OprFact::illegalOpr);
2786               } else if (cond == lir_cond_notEqual && cmove->in_opr2() == cmp_arg) {
2787                 cmove->set_in_opr2(LIR_OprFact::illegalOpr);
2788               }
2789             }
2790           }
2791         }
2792         break;
2793       }
2794 
2795       default:
2796         break;
2797     }
2798   }
2799 }
2800 
2801 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2802   assert(src->is_address(), "sanity");
2803   Address addr = as_Address(src->as_address_ptr());
2804 
2805   if (code == lir_xchg) {
2806   } else {
2807     assert (!data->is_oop(), "xadd for oops");
2808   }
2809 
2810   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore | MacroAssembler::LoadStore), Rtemp);
2811 
2812   Label retry;
2813   __ bind(retry);
2814 
2815   if (data->type() == T_INT || data->is_oop()) {
2816     Register dst = dest->as_register();
2817     Register new_val = noreg;
2818     __ ldrex(dst, addr);
2819     if (code == lir_xadd) {
2820       Register tmp_reg = tmp->as_register();
2821       if (data->is_constant()) {
2822         assert_different_registers(dst, tmp_reg);
2823         __ add_32(tmp_reg, dst, data->as_constant_ptr()->as_jint());
2824       } else {
2825         assert_different_registers(dst, tmp_reg, data->as_register());
2826         __ add_32(tmp_reg, dst, data->as_register());
2827       }
2828       new_val = tmp_reg;
2829     } else {
2830       if (UseCompressedOops && data->is_oop()) {
2831         new_val = tmp->as_pointer_register();
2832       } else {
2833         new_val = data->as_register();
2834       }
2835       assert_different_registers(dst, new_val);
2836     }
2837     __ strex(Rtemp, new_val, addr);
2838 
2839   } else if (data->type() == T_LONG) {
2840     Register dst_lo = dest->as_register_lo();
2841     Register new_val_lo = noreg;
2842     Register dst_hi = dest->as_register_hi();
2843 
2844     assert(dst_hi->encoding() == dst_lo->encoding() + 1, "non aligned register pair");
2845     assert((dst_lo->encoding() & 0x1) == 0, "misaligned register pair");
2846 
2847     __ bind(retry);
2848     __ ldrexd(dst_lo, addr);
2849     if (code == lir_xadd) {
2850       Register tmp_lo = tmp->as_register_lo();
2851       Register tmp_hi = tmp->as_register_hi();
2852 
2853       assert(tmp_hi->encoding() == tmp_lo->encoding() + 1, "non aligned register pair");
2854       assert((tmp_lo->encoding() & 0x1) == 0, "misaligned register pair");
2855 
2856       if (data->is_constant()) {
2857         jlong c = data->as_constant_ptr()->as_jlong();
2858         assert((jlong)((jint)c) == c, "overflow");
2859         assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi);
2860         __ adds(tmp_lo, dst_lo, (jint)c);
2861         __ adc(tmp_hi, dst_hi, 0);
2862       } else {
2863         Register new_val_lo = data->as_register_lo();
2864         Register new_val_hi = data->as_register_hi();
2865         __ adds(tmp_lo, dst_lo, new_val_lo);
2866         __ adc(tmp_hi, dst_hi, new_val_hi);
2867         assert_different_registers(dst_lo, dst_hi, tmp_lo, tmp_hi, new_val_lo, new_val_hi);
2868       }
2869       new_val_lo = tmp_lo;
2870     } else {
2871       new_val_lo = data->as_register_lo();
2872       Register new_val_hi = data->as_register_hi();
2873 
2874       assert_different_registers(dst_lo, dst_hi, new_val_lo, new_val_hi);
2875       assert(new_val_hi->encoding() == new_val_lo->encoding() + 1, "non aligned register pair");
2876       assert((new_val_lo->encoding() & 0x1) == 0, "misaligned register pair");
2877     }
2878     __ strexd(Rtemp, new_val_lo, addr);
2879   } else {
2880     ShouldNotReachHere();
2881   }
2882 
2883   __ cbnz_32(Rtemp, retry);
2884   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
2885 
2886 }
2887 
2888 #undef __