1 /*
   2  * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2019, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "gc/shared/barrierSet.hpp"
  37 #include "gc/shared/cardTableBarrierSet.hpp"
  38 #include "nativeInst_ppc.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.inline.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 
  44 #define __ _masm->
  45 
  46 
  47 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
  48 
  49 
  50 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  51   Unimplemented(); return false; // Currently not used on this platform.
  52 }
  53 
  54 
  55 LIR_Opr LIR_Assembler::receiverOpr() {
  56   return FrameMap::R3_oop_opr;
  57 }
  58 
  59 
  60 LIR_Opr LIR_Assembler::osrBufferPointer() {
  61   return FrameMap::R3_opr;
  62 }
  63 
  64 
  65 // This specifies the stack pointer decrement needed to build the frame.
  66 int LIR_Assembler::initial_frame_size_in_bytes() const {
  67   return in_bytes(frame_map()->framesize_in_bytes());
  68 }
  69 
  70 
  71 // Inline cache check: the inline cached class is in inline_cache_reg;
  72 // we fetch the class of the receiver and compare it with the cached class.
  73 // If they do not match we jump to slow case.
  74 int LIR_Assembler::check_icache() {
  75   int offset = __ offset();
  76   __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
  77   return offset;
  78 }
  79 



  80 
  81 void LIR_Assembler::osr_entry() {
  82   // On-stack-replacement entry sequence:
  83   //
  84   //   1. Create a new compiled activation.
  85   //   2. Initialize local variables in the compiled activation. The expression
  86   //      stack must be empty at the osr_bci; it is not initialized.
  87   //   3. Jump to the continuation address in compiled code to resume execution.
  88 
  89   // OSR entry point
  90   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
  91   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
  92   ValueStack* entry_state = osr_entry->end()->state();
  93   int number_of_locks = entry_state->locks_size();
  94 
  95   // Create a frame for the compiled activation.
  96   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
  97 
  98   // OSR buffer is
  99   //
 100   // locals[nlocals-1..0]
 101   // monitors[number_of_locks-1..0]
 102   //
 103   // Locals is a direct copy of the interpreter frame so in the osr buffer
 104   // the first slot in the local array is the last local from the interpreter
 105   // and the last slot is local[0] (receiver) from the interpreter.
 106   //
 107   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 108   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 109   // in the interpreter frame (the method lock if a sync method).
 110 
 111   // Initialize monitors in the compiled activation.
 112   //   R3: pointer to osr buffer
 113   //
 114   // All other registers are dead at this point and the locals will be
 115   // copied into place by code emitted in the IR.
 116 
 117   Register OSR_buf = osrBufferPointer()->as_register();
 118   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 119     int monitor_offset = BytesPerWord * method()->max_locals() +
 120       (2 * BytesPerWord) * (number_of_locks - 1);
 121     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 122     // the OSR buffer using 2 word entries: first the lock and then
 123     // the oop.
 124     for (int i = 0; i < number_of_locks; i++) {
 125       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 126 #ifdef ASSERT
 127       // Verify the interpreter's monitor has a non-null object.
 128       {
 129         Label L;
 130         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 131         __ cmpdi(CCR0, R0, 0);
 132         __ bne(CCR0, L);
 133         __ stop("locked object is NULL");
 134         __ bind(L);
 135       }
 136 #endif // ASSERT
 137       // Copy the lock field into the compiled activation.
 138       Address ml = frame_map()->address_for_monitor_lock(i),
 139               mo = frame_map()->address_for_monitor_object(i);
 140       assert(ml.index() == noreg && mo.index() == noreg, "sanity");
 141       __ ld(R0, slot_offset + 0, OSR_buf);
 142       __ std(R0, ml.disp(), ml.base());
 143       __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 144       __ std(R0, mo.disp(), mo.base());
 145     }
 146   }
 147 }
 148 
 149 
 150 int LIR_Assembler::emit_exception_handler() {
 151   // If the last instruction is a call (typically to do a throw which
 152   // is coming at the end after block reordering) the return address
 153   // must still point into the code area in order to avoid assertion
 154   // failures when searching for the corresponding bci => add a nop
 155   // (was bug 5/14/1999 - gri).
 156   __ nop();
 157 
 158   // Generate code for the exception handler.
 159   address handler_base = __ start_a_stub(exception_handler_size());
 160 
 161   if (handler_base == NULL) {
 162     // Not enough space left for the handler.
 163     bailout("exception handler overflow");
 164     return -1;
 165   }
 166 
 167   int offset = code_offset();
 168   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
 169   //__ load_const_optimized(R0, entry_point);
 170   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 171   __ mtctr(R0);
 172   __ bctr();
 173 
 174   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 175   __ end_a_stub();
 176 
 177   return offset;
 178 }
 179 
 180 
 181 // Emit the code to remove the frame from the stack in the exception
 182 // unwind path.
 183 int LIR_Assembler::emit_unwind_handler() {
 184   _masm->block_comment("Unwind handler");
 185 
 186   int offset = code_offset();
 187   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 188   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 189 
 190   // Fetch the exception from TLS and clear out exception related thread state.
 191   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 192   __ li(R0, 0);
 193   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 194   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 195 
 196   __ bind(_unwind_handler_entry);
 197   __ verify_not_null_oop(Rexception);
 198   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 199 
 200   // Perform needed unlocking
 201   MonitorExitStub* stub = NULL;
 202   if (method()->is_synchronized()) {
 203     monitor_address(0, FrameMap::R4_opr);
 204     stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
 205     __ unlock_object(R5, R6, R4, *stub->entry());
 206     __ bind(*stub->continuation());
 207   }
 208 
 209   if (compilation()->env()->dtrace_method_probes()) {
 210     Unimplemented();
 211   }
 212 
 213   // Dispatch to the unwind logic.
 214   address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
 215   //__ load_const_optimized(R0, unwind_stub);
 216   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 217   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 218   __ mtctr(R0);
 219   __ bctr();
 220 
 221   // Emit the slow path assembly.
 222   if (stub != NULL) {
 223     stub->emit_code(this);
 224   }
 225 
 226   return offset;
 227 }
 228 
 229 
 230 int LIR_Assembler::emit_deopt_handler() {
 231   // If the last instruction is a call (typically to do a throw which
 232   // is coming at the end after block reordering) the return address
 233   // must still point into the code area in order to avoid assertion
 234   // failures when searching for the corresponding bci => add a nop
 235   // (was bug 5/14/1999 - gri).
 236   __ nop();
 237 
 238   // Generate code for deopt handler.
 239   address handler_base = __ start_a_stub(deopt_handler_size());
 240 
 241   if (handler_base == NULL) {
 242     // Not enough space left for the handler.
 243     bailout("deopt handler overflow");
 244     return -1;
 245   }
 246 
 247   int offset = code_offset();
 248   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 249 
 250   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 251   __ end_a_stub();
 252 
 253   return offset;
 254 }
 255 
 256 
 257 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 258   if (o == NULL) {
 259     __ li(reg, 0);
 260   } else {
 261     AddressLiteral addrlit = __ constant_oop_address(o);
 262     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 263   }
 264 }
 265 
 266 
 267 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 268   // Allocate a new index in table to hold the object once it's been patched.
 269   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 270   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 271 
 272   AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
 273   __ load_const(reg, addrlit, R0);
 274 
 275   patching_epilog(patch, lir_patch_normal, reg, info);
 276 }
 277 
 278 
 279 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 280   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 281   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 282 }
 283 
 284 
 285 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 286   // Allocate a new index in table to hold the klass once it's been patched.
 287   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 288   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 289 
 290   AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
 291   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 292   __ load_const(reg, addrlit, R0);
 293 
 294   patching_epilog(patch, lir_patch_normal, reg, info);
 295 }
 296 
 297 
 298 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 299   const bool is_int = result->is_single_cpu();
 300   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 301   Register Rdivisor  = noreg;
 302   Register Rscratch  = temp->as_register();
 303   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 304   long divisor = -1;
 305 
 306   if (right->is_register()) {
 307     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 308   } else {
 309     divisor = is_int ? right->as_constant_ptr()->as_jint()
 310                      : right->as_constant_ptr()->as_jlong();
 311   }
 312 
 313   assert(Rdividend != Rscratch, "");
 314   assert(Rdivisor  != Rscratch, "");
 315   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 316 
 317   if (Rdivisor == noreg) {
 318     if (divisor == 1) { // stupid, but can happen
 319       if (code == lir_idiv) {
 320         __ mr_if_needed(Rresult, Rdividend);
 321       } else {
 322         __ li(Rresult, 0);
 323       }
 324 
 325     } else if (is_power_of_2(divisor)) {
 326       // Convert division by a power of two into some shifts and logical operations.
 327       int log2 = log2_intptr(divisor);
 328 
 329       // Round towards 0.
 330       if (divisor == 2) {
 331         if (is_int) {
 332           __ srwi(Rscratch, Rdividend, 31);
 333         } else {
 334           __ srdi(Rscratch, Rdividend, 63);
 335         }
 336       } else {
 337         if (is_int) {
 338           __ srawi(Rscratch, Rdividend, 31);
 339         } else {
 340           __ sradi(Rscratch, Rdividend, 63);
 341         }
 342         __ clrldi(Rscratch, Rscratch, 64-log2);
 343       }
 344       __ add(Rscratch, Rdividend, Rscratch);
 345 
 346       if (code == lir_idiv) {
 347         if (is_int) {
 348           __ srawi(Rresult, Rscratch, log2);
 349         } else {
 350           __ sradi(Rresult, Rscratch, log2);
 351         }
 352       } else { // lir_irem
 353         __ clrrdi(Rscratch, Rscratch, log2);
 354         __ sub(Rresult, Rdividend, Rscratch);
 355       }
 356 
 357     } else if (divisor == -1) {
 358       if (code == lir_idiv) {
 359         __ neg(Rresult, Rdividend);
 360       } else {
 361         __ li(Rresult, 0);
 362       }
 363 
 364     } else {
 365       __ load_const_optimized(Rscratch, divisor);
 366       if (code == lir_idiv) {
 367         if (is_int) {
 368           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 369         } else {
 370           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 371         }
 372       } else {
 373         assert(Rscratch != R0, "need both");
 374         if (is_int) {
 375           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 376           __ mullw(Rscratch, R0, Rscratch);
 377         } else {
 378           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 379           __ mulld(Rscratch, R0, Rscratch);
 380         }
 381         __ sub(Rresult, Rdividend, Rscratch);
 382       }
 383 
 384     }
 385     return;
 386   }
 387 
 388   Label regular, done;
 389   if (is_int) {
 390     __ cmpwi(CCR0, Rdivisor, -1);
 391   } else {
 392     __ cmpdi(CCR0, Rdivisor, -1);
 393   }
 394   __ bne(CCR0, regular);
 395   if (code == lir_idiv) {
 396     __ neg(Rresult, Rdividend);
 397     __ b(done);
 398     __ bind(regular);
 399     if (is_int) {
 400       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 401     } else {
 402       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 403     }
 404   } else { // lir_irem
 405     __ li(Rresult, 0);
 406     __ b(done);
 407     __ bind(regular);
 408     if (is_int) {
 409       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 410       __ mullw(Rscratch, Rscratch, Rdivisor);
 411     } else {
 412       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 413       __ mulld(Rscratch, Rscratch, Rdivisor);
 414     }
 415     __ sub(Rresult, Rdividend, Rscratch);
 416   }
 417   __ bind(done);
 418 }
 419 
 420 
 421 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 422   switch (op->code()) {
 423   case lir_idiv:
 424   case lir_irem:
 425     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 426                     op->result_opr(), op->info());
 427     break;
 428   case lir_fmad:
 429     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 430              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 431     break;
 432   case lir_fmaf:
 433     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 434               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 435     break;
 436   default: ShouldNotReachHere(); break;
 437   }
 438 }
 439 
 440 
 441 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 442 #ifdef ASSERT
 443   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 444   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 445   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 446   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 447 #endif
 448 
 449   Label *L = op->label();
 450   if (op->cond() == lir_cond_always) {
 451     __ b(*L);
 452   } else {
 453     Label done;
 454     bool is_unordered = false;
 455     if (op->code() == lir_cond_float_branch) {
 456       assert(op->ublock() != NULL, "must have unordered successor");
 457       is_unordered = true;
 458     } else {
 459       assert(op->code() == lir_branch, "just checking");
 460     }
 461 
 462     bool positive = false;
 463     Assembler::Condition cond = Assembler::equal;
 464     switch (op->cond()) {
 465       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 466       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 467       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 468       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 469       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 470       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 471       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 472       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 473       default:                    ShouldNotReachHere();
 474     }
 475     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 476     int bi = Assembler::bi0(BOOL_RESULT, cond);
 477     if (is_unordered) {
 478       if (positive) {
 479         if (op->ublock() == op->block()) {
 480           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 481         }
 482       } else {
 483         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 484       }
 485     }
 486     __ bc_far_optimized(bo, bi, *L);
 487     __ bind(done);
 488   }
 489 }
 490 
 491 
 492 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 493   Bytecodes::Code code = op->bytecode();
 494   LIR_Opr src = op->in_opr(),
 495           dst = op->result_opr();
 496 
 497   switch(code) {
 498     case Bytecodes::_i2l: {
 499       __ extsw(dst->as_register_lo(), src->as_register());
 500       break;
 501     }
 502     case Bytecodes::_l2i: {
 503       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 504       break;
 505     }
 506     case Bytecodes::_i2b: {
 507       __ extsb(dst->as_register(), src->as_register());
 508       break;
 509     }
 510     case Bytecodes::_i2c: {
 511       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 512       break;
 513     }
 514     case Bytecodes::_i2s: {
 515       __ extsh(dst->as_register(), src->as_register());
 516       break;
 517     }
 518     case Bytecodes::_i2d:
 519     case Bytecodes::_l2d: {
 520       bool src_in_memory = !VM_Version::has_mtfprd();
 521       FloatRegister rdst = dst->as_double_reg();
 522       FloatRegister rsrc;
 523       if (src_in_memory) {
 524         rsrc = src->as_double_reg(); // via mem
 525       } else {
 526         // move src to dst register
 527         if (code == Bytecodes::_i2d) {
 528           __ mtfprwa(rdst, src->as_register());
 529         } else {
 530           __ mtfprd(rdst, src->as_register_lo());
 531         }
 532         rsrc = rdst;
 533       }
 534       __ fcfid(rdst, rsrc);
 535       break;
 536     }
 537     case Bytecodes::_i2f:
 538     case Bytecodes::_l2f: {
 539       bool src_in_memory = !VM_Version::has_mtfprd();
 540       FloatRegister rdst = dst->as_float_reg();
 541       FloatRegister rsrc;
 542       if (src_in_memory) {
 543         rsrc = src->as_double_reg(); // via mem
 544       } else {
 545         // move src to dst register
 546         if (code == Bytecodes::_i2f) {
 547           __ mtfprwa(rdst, src->as_register());
 548         } else {
 549           __ mtfprd(rdst, src->as_register_lo());
 550         }
 551         rsrc = rdst;
 552       }
 553       if (VM_Version::has_fcfids()) {
 554         __ fcfids(rdst, rsrc);
 555       } else {
 556         assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
 557         __ fcfid(rdst, rsrc);
 558         __ frsp(rdst, rdst);
 559       }
 560       break;
 561     }
 562     case Bytecodes::_f2d: {
 563       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 564       break;
 565     }
 566     case Bytecodes::_d2f: {
 567       __ frsp(dst->as_float_reg(), src->as_double_reg());
 568       break;
 569     }
 570     case Bytecodes::_d2i:
 571     case Bytecodes::_f2i: {
 572       bool dst_in_memory = !VM_Version::has_mtfprd();
 573       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 574       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 575       Label L;
 576       // Result must be 0 if value is NaN; test by comparing value to itself.
 577       __ fcmpu(CCR0, rsrc, rsrc);
 578       if (dst_in_memory) {
 579         __ li(R0, 0); // 0 in case of NAN
 580         __ std(R0, addr.disp(), addr.base());
 581       } else {
 582         __ li(dst->as_register(), 0);
 583       }
 584       __ bso(CCR0, L);
 585       __ fctiwz(rsrc, rsrc); // USE_KILL
 586       if (dst_in_memory) {
 587         __ stfd(rsrc, addr.disp(), addr.base());
 588       } else {
 589         __ mffprd(dst->as_register(), rsrc);
 590       }
 591       __ bind(L);
 592       break;
 593     }
 594     case Bytecodes::_d2l:
 595     case Bytecodes::_f2l: {
 596       bool dst_in_memory = !VM_Version::has_mtfprd();
 597       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 598       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 599       Label L;
 600       // Result must be 0 if value is NaN; test by comparing value to itself.
 601       __ fcmpu(CCR0, rsrc, rsrc);
 602       if (dst_in_memory) {
 603         __ li(R0, 0); // 0 in case of NAN
 604         __ std(R0, addr.disp(), addr.base());
 605       } else {
 606         __ li(dst->as_register_lo(), 0);
 607       }
 608       __ bso(CCR0, L);
 609       __ fctidz(rsrc, rsrc); // USE_KILL
 610       if (dst_in_memory) {
 611         __ stfd(rsrc, addr.disp(), addr.base());
 612       } else {
 613         __ mffprd(dst->as_register_lo(), rsrc);
 614       }
 615       __ bind(L);
 616       break;
 617     }
 618 
 619     default: ShouldNotReachHere();
 620   }
 621 }
 622 
 623 
 624 void LIR_Assembler::align_call(LIR_Code) {
 625   // do nothing since all instructions are word aligned on ppc
 626 }
 627 
 628 
 629 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 630   int start_offset = __ offset();
 631   // Put the entry point as a constant into the constant pool.
 632   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 633   if (entry_point_toc_addr == NULL) {
 634     bailout("const section overflow");
 635     return false;
 636   }
 637   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 638 
 639   // Emit the trampoline stub which will be related to the branch-and-link below.
 640   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 641   if (!stub) {
 642     bailout("no space for trampoline stub");
 643     return false;
 644   }
 645   return true;
 646 }
 647 
 648 
 649 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 650   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 651 
 652   bool success = emit_trampoline_stub_for_call(op->addr());
 653   if (!success) { return; }
 654 
 655   __ relocate(rtype);
 656   // Note: At this point we do not have the address of the trampoline
 657   // stub, and the entry point might be too far away for bl, so __ pc()
 658   // serves as dummy and the bl will be patched later.
 659   __ code()->set_insts_mark();
 660   __ bl(__ pc());
 661   add_call_info(code_offset(), op->info());
 662 }
 663 
 664 
 665 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 666   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 667 
 668   // Virtual call relocation will point to ic load.
 669   address virtual_call_meta_addr = __ pc();
 670   // Load a clear inline cache.
 671   AddressLiteral empty_ic((address) Universe::non_oop_word());
 672   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 673   if (!success) {
 674     bailout("const section overflow");
 675     return;
 676   }
 677   // Call to fixup routine. Fixup routine uses ScopeDesc info
 678   // to determine who we intended to call.
 679   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 680 
 681   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 682   if (!success) { return; }
 683 
 684   // Note: At this point we do not have the address of the trampoline
 685   // stub, and the entry point might be too far away for bl, so __ pc()
 686   // serves as dummy and the bl will be patched later.
 687   __ bl(__ pc());
 688   add_call_info(code_offset(), op->info());
 689 }
 690 
 691 
 692 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 693   ShouldNotReachHere(); // ic_call is used instead.
 694 }
 695 
 696 
 697 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 698   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 699   __ null_check(addr, stub->entry());
 700   append_code_stub(stub);
 701 }
 702 
 703 
 704 // Attention: caller must encode oop if needed
 705 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
 706   int store_offset;
 707   if (!Assembler::is_simm16(offset)) {
 708     // For offsets larger than a simm16 we setup the offset.
 709     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 710     __ load_const_optimized(R0, offset);
 711     store_offset = store(from_reg, base, R0, type, wide);
 712   } else {
 713     store_offset = code_offset();
 714     switch (type) {
 715       case T_BOOLEAN: // fall through
 716       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 717       case T_CHAR  :
 718       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 719       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 720       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 721       case T_ADDRESS:
 722       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 723       case T_ARRAY : // fall through
 724       case T_OBJECT:
 725         {
 726           if (UseCompressedOops && !wide) {
 727             // Encoding done in caller
 728             __ stw(from_reg->as_register(), offset, base);
 729           } else {
 730             __ std(from_reg->as_register(), offset, base);
 731           }
 732           __ verify_oop(from_reg->as_register());
 733           break;
 734         }
 735       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 736       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 737       default      : ShouldNotReachHere();
 738     }
 739   }
 740   return store_offset;
 741 }
 742 
 743 
 744 // Attention: caller must encode oop if needed
 745 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 746   int store_offset = code_offset();
 747   switch (type) {
 748     case T_BOOLEAN: // fall through
 749     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 750     case T_CHAR  :
 751     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 752     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 753     case T_LONG  :
 754 #ifdef _LP64
 755       __ stdx(from_reg->as_register_lo(), base, disp);
 756 #else
 757       Unimplemented();
 758 #endif
 759       break;
 760     case T_ADDRESS:
 761       __ stdx(from_reg->as_register(), base, disp);
 762       break;
 763     case T_ARRAY : // fall through
 764     case T_OBJECT:
 765       {
 766         if (UseCompressedOops && !wide) {
 767           // Encoding done in caller.
 768           __ stwx(from_reg->as_register(), base, disp);
 769         } else {
 770           __ stdx(from_reg->as_register(), base, disp);
 771         }
 772         __ verify_oop(from_reg->as_register()); // kills R0
 773         break;
 774       }
 775     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 776     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 777     default      : ShouldNotReachHere();
 778   }
 779   return store_offset;
 780 }
 781 
 782 
 783 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
 784   int load_offset;
 785   if (!Assembler::is_simm16(offset)) {
 786     // For offsets larger than a simm16 we setup the offset.
 787     __ load_const_optimized(R0, offset);
 788     load_offset = load(base, R0, to_reg, type, wide);
 789   } else {
 790     load_offset = code_offset();
 791     switch(type) {
 792       case T_BOOLEAN: // fall through
 793       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 794                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 795       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 796       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 797       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 798       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 799       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 800       case T_ADDRESS:
 801         if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
 802           __ lwz(to_reg->as_register(), offset, base);
 803           __ decode_klass_not_null(to_reg->as_register());
 804         } else {
 805           __ ld(to_reg->as_register(), offset, base);
 806         }
 807         break;
 808       case T_ARRAY : // fall through
 809       case T_OBJECT:
 810         {
 811           if (UseCompressedOops && !wide) {
 812             __ lwz(to_reg->as_register(), offset, base);
 813             __ decode_heap_oop(to_reg->as_register());
 814           } else {
 815             __ ld(to_reg->as_register(), offset, base);
 816           }
 817           __ verify_oop(to_reg->as_register());
 818           break;
 819         }
 820       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 821       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 822       default      : ShouldNotReachHere();
 823     }
 824   }
 825   return load_offset;
 826 }
 827 
 828 
 829 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 830   int load_offset = code_offset();
 831   switch(type) {
 832     case T_BOOLEAN: // fall through
 833     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 834                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 835     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 836     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 837     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 838     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 839     case T_ARRAY : // fall through
 840     case T_OBJECT:
 841       {
 842         if (UseCompressedOops && !wide) {
 843           __ lwzx(to_reg->as_register(), base, disp);
 844           __ decode_heap_oop(to_reg->as_register());
 845         } else {
 846           __ ldx(to_reg->as_register(), base, disp);
 847         }
 848         __ verify_oop(to_reg->as_register());
 849         break;
 850       }
 851     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 852     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 853     case T_LONG  :
 854 #ifdef _LP64
 855       __ ldx(to_reg->as_register_lo(), base, disp);
 856 #else
 857       Unimplemented();
 858 #endif
 859       break;
 860     default      : ShouldNotReachHere();
 861   }
 862   return load_offset;
 863 }
 864 
 865 
 866 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 867   LIR_Const* c = src->as_constant_ptr();
 868   Register src_reg = R0;
 869   switch (c->type()) {
 870     case T_INT:
 871     case T_FLOAT: {
 872       int value = c->as_jint_bits();
 873       __ load_const_optimized(src_reg, value);
 874       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 875       __ stw(src_reg, addr.disp(), addr.base());
 876       break;
 877     }
 878     case T_ADDRESS: {
 879       int value = c->as_jint_bits();
 880       __ load_const_optimized(src_reg, value);
 881       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 882       __ std(src_reg, addr.disp(), addr.base());
 883       break;
 884     }
 885     case T_OBJECT: {
 886       jobject2reg(c->as_jobject(), src_reg);
 887       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 888       __ std(src_reg, addr.disp(), addr.base());
 889       break;
 890     }
 891     case T_LONG:
 892     case T_DOUBLE: {
 893       int value = c->as_jlong_bits();
 894       __ load_const_optimized(src_reg, value);
 895       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 896       __ std(src_reg, addr.disp(), addr.base());
 897       break;
 898     }
 899     default:
 900       Unimplemented();
 901   }
 902 }
 903 
 904 
 905 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 906   LIR_Const* c = src->as_constant_ptr();
 907   LIR_Address* addr = dest->as_address_ptr();
 908   Register base = addr->base()->as_pointer_register();
 909   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 910   int offset = -1;
 911   // Null check for large offsets in LIRGenerator::do_StoreField.
 912   bool needs_explicit_null_check = !ImplicitNullChecks;
 913 
 914   if (info != NULL && needs_explicit_null_check) {
 915     explicit_null_check(base, info);
 916   }
 917 
 918   switch (c->type()) {
 919     case T_FLOAT: type = T_INT;
 920     case T_INT:
 921     case T_ADDRESS: {
 922       tmp = FrameMap::R0_opr;
 923       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 924       break;
 925     }
 926     case T_DOUBLE: type = T_LONG;
 927     case T_LONG: {
 928       tmp = FrameMap::R0_long_opr;
 929       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 930       break;
 931     }
 932     case T_OBJECT: {
 933       tmp = FrameMap::R0_opr;
 934       if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
 935         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 936         __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
 937         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 938         __ ori(R0, R0, oop_addr.value() & 0xffff);
 939       } else {
 940         jobject2reg(c->as_jobject(), R0);
 941       }
 942       break;
 943     }
 944     default:
 945       Unimplemented();
 946   }
 947 
 948   // Handle either reg+reg or reg+disp address.
 949   if (addr->index()->is_valid()) {
 950     assert(addr->disp() == 0, "must be zero");
 951     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 952   } else {
 953     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 954     offset = store(tmp, base, addr->disp(), type, wide, false);
 955   }
 956 
 957   if (info != NULL) {
 958     assert(offset != -1, "offset should've been set");
 959     if (!needs_explicit_null_check) {
 960       add_debug_info_for_null_check(offset, info);
 961     }
 962   }
 963 }
 964 
 965 
 966 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 967   LIR_Const* c = src->as_constant_ptr();
 968   LIR_Opr to_reg = dest;
 969 
 970   switch (c->type()) {
 971     case T_INT: {
 972       assert(patch_code == lir_patch_none, "no patching handled here");
 973       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 974       break;
 975     }
 976     case T_ADDRESS: {
 977       assert(patch_code == lir_patch_none, "no patching handled here");
 978       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 979       break;
 980     }
 981     case T_LONG: {
 982       assert(patch_code == lir_patch_none, "no patching handled here");
 983       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 984       break;
 985     }
 986 
 987     case T_OBJECT: {
 988       if (patch_code == lir_patch_none) {
 989         jobject2reg(c->as_jobject(), to_reg->as_register());
 990       } else {
 991         jobject2reg_with_patching(to_reg->as_register(), info);
 992       }
 993       break;
 994     }
 995 
 996     case T_METADATA:
 997       {
 998         if (patch_code == lir_patch_none) {
 999           metadata2reg(c->as_metadata(), to_reg->as_register());
1000         } else {
1001           klass2reg_with_patching(to_reg->as_register(), info);
1002         }
1003       }
1004       break;
1005 
1006     case T_FLOAT:
1007       {
1008         if (to_reg->is_single_fpu()) {
1009           address const_addr = __ float_constant(c->as_jfloat());
1010           if (const_addr == NULL) {
1011             bailout("const section overflow");
1012             break;
1013           }
1014           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1015           __ relocate(rspec);
1016           __ load_const(R0, const_addr);
1017           __ lfsx(to_reg->as_float_reg(), R0);
1018         } else {
1019           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1020           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1021         }
1022       }
1023       break;
1024 
1025     case T_DOUBLE:
1026       {
1027         if (to_reg->is_double_fpu()) {
1028           address const_addr = __ double_constant(c->as_jdouble());
1029           if (const_addr == NULL) {
1030             bailout("const section overflow");
1031             break;
1032           }
1033           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1034           __ relocate(rspec);
1035           __ load_const(R0, const_addr);
1036           __ lfdx(to_reg->as_double_reg(), R0);
1037         } else {
1038           assert(to_reg->is_double_cpu(), "Must be a long register.");
1039           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1040         }
1041       }
1042       break;
1043 
1044     default:
1045       ShouldNotReachHere();
1046   }
1047 }
1048 
1049 
1050 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1051   Unimplemented(); return Address();
1052 }
1053 
1054 
1055 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1056   if (addr->index()->is_illegal()) {
1057     return (RegisterOrConstant)(addr->disp());
1058   } else {
1059     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1060   }
1061 }
1062 
1063 
1064 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1065   const Register tmp = R0;
1066   switch (type) {
1067     case T_INT:
1068     case T_FLOAT: {
1069       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1070       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1071       __ lwz(tmp, from.disp(), from.base());
1072       __ stw(tmp, to.disp(), to.base());
1073       break;
1074     }
1075     case T_ADDRESS:
1076     case T_OBJECT: {
1077       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1078       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1079       __ ld(tmp, from.disp(), from.base());
1080       __ std(tmp, to.disp(), to.base());
1081       break;
1082     }
1083     case T_LONG:
1084     case T_DOUBLE: {
1085       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1086       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1087       __ ld(tmp, from.disp(), from.base());
1088       __ std(tmp, to.disp(), to.base());
1089       break;
1090     }
1091 
1092     default:
1093       ShouldNotReachHere();
1094   }
1095 }
1096 
1097 
1098 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1099   Unimplemented(); return Address();
1100 }
1101 
1102 
1103 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1104   Unimplemented(); return Address();
1105 }
1106 
1107 
1108 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1109                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1110 
1111   assert(type != T_METADATA, "load of metadata ptr not supported");
1112   LIR_Address* addr = src_opr->as_address_ptr();
1113   LIR_Opr to_reg = dest;
1114 
1115   Register src = addr->base()->as_pointer_register();
1116   Register disp_reg = noreg;
1117   int disp_value = addr->disp();
1118   bool needs_patching = (patch_code != lir_patch_none);
1119   // null check for large offsets in LIRGenerator::do_LoadField
1120   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1121 
1122   if (info != NULL && needs_explicit_null_check) {
1123     explicit_null_check(src, info);
1124   }
1125 
1126   if (addr->base()->type() == T_OBJECT) {
1127     __ verify_oop(src);
1128   }
1129 
1130   PatchingStub* patch = NULL;
1131   if (needs_patching) {
1132     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1133     assert(!to_reg->is_double_cpu() ||
1134            patch_code == lir_patch_none ||
1135            patch_code == lir_patch_normal, "patching doesn't match register");
1136   }
1137 
1138   if (addr->index()->is_illegal()) {
1139     if (!Assembler::is_simm16(disp_value)) {
1140       if (needs_patching) {
1141         __ load_const32(R0, 0); // patchable int
1142       } else {
1143         __ load_const_optimized(R0, disp_value);
1144       }
1145       disp_reg = R0;
1146     }
1147   } else {
1148     disp_reg = addr->index()->as_pointer_register();
1149     assert(disp_value == 0, "can't handle 3 operand addresses");
1150   }
1151 
1152   // Remember the offset of the load. The patching_epilog must be done
1153   // before the call to add_debug_info, otherwise the PcDescs don't get
1154   // entered in increasing order.
1155   int offset;
1156 
1157   if (disp_reg == noreg) {
1158     assert(Assembler::is_simm16(disp_value), "should have set this up");
1159     offset = load(src, disp_value, to_reg, type, wide, unaligned);
1160   } else {
1161     assert(!unaligned, "unexpected");
1162     offset = load(src, disp_reg, to_reg, type, wide);
1163   }
1164 
1165   if (patch != NULL) {
1166     patching_epilog(patch, patch_code, src, info);
1167   }
1168   if (info != NULL && !needs_explicit_null_check) {
1169     add_debug_info_for_null_check(offset, info);
1170   }
1171 }
1172 
1173 
1174 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1175   Address addr;
1176   if (src->is_single_word()) {
1177     addr = frame_map()->address_for_slot(src->single_stack_ix());
1178   } else if (src->is_double_word())  {
1179     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1180   }
1181 
1182   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1183   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1184 }
1185 
1186 
1187 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1188   Address addr;
1189   if (dest->is_single_word()) {
1190     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1191   } else if (dest->is_double_word())  {
1192     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1193   }
1194   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1195   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1196 }
1197 
1198 
1199 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1200   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1201     if (from_reg->is_double_fpu()) {
1202       // double to double moves
1203       assert(to_reg->is_double_fpu(), "should match");
1204       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1205     } else {
1206       // float to float moves
1207       assert(to_reg->is_single_fpu(), "should match");
1208       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1209     }
1210   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1211     if (from_reg->is_double_cpu()) {
1212       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1213     } else if (to_reg->is_double_cpu()) {
1214       // int to int moves
1215       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1216     } else {
1217       // int to int moves
1218       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1219     }
1220   } else {
1221     ShouldNotReachHere();
1222   }
1223   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1224     __ verify_oop(to_reg->as_register());
1225   }
1226 }
1227 
1228 
1229 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1230                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1231                             bool wide, bool unaligned) {
1232   assert(type != T_METADATA, "store of metadata ptr not supported");
1233   LIR_Address* addr = dest->as_address_ptr();
1234 
1235   Register src = addr->base()->as_pointer_register();
1236   Register disp_reg = noreg;
1237   int disp_value = addr->disp();
1238   bool needs_patching = (patch_code != lir_patch_none);
1239   bool compress_oop = (type == T_ARRAY || type == T_OBJECT) && UseCompressedOops && !wide &&
1240                       Universe::narrow_oop_mode() != Universe::UnscaledNarrowOop;
1241   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1242   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1243   // Null check for large offsets in LIRGenerator::do_StoreField.
1244   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1245 
1246   if (info != NULL && needs_explicit_null_check) {
1247     explicit_null_check(src, info);
1248   }
1249 
1250   if (addr->base()->is_oop_register()) {
1251     __ verify_oop(src);
1252   }
1253 
1254   PatchingStub* patch = NULL;
1255   if (needs_patching) {
1256     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1257     assert(!from_reg->is_double_cpu() ||
1258            patch_code == lir_patch_none ||
1259            patch_code == lir_patch_normal, "patching doesn't match register");
1260   }
1261 
1262   if (addr->index()->is_illegal()) {
1263     if (load_disp) {
1264       disp_reg = use_R29 ? R29_TOC : R0;
1265       if (needs_patching) {
1266         __ load_const32(disp_reg, 0); // patchable int
1267       } else {
1268         __ load_const_optimized(disp_reg, disp_value);
1269       }
1270     }
1271   } else {
1272     disp_reg = addr->index()->as_pointer_register();
1273     assert(disp_value == 0, "can't handle 3 operand addresses");
1274   }
1275 
1276   // remember the offset of the store. The patching_epilog must be done
1277   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1278   // entered in increasing order.
1279   int offset;
1280 
1281   if (compress_oop) {
1282     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1283     from_reg = FrameMap::as_opr(co);
1284   }
1285 
1286   if (disp_reg == noreg) {
1287     assert(Assembler::is_simm16(disp_value), "should have set this up");
1288     offset = store(from_reg, src, disp_value, type, wide, unaligned);
1289   } else {
1290     assert(!unaligned, "unexpected");
1291     offset = store(from_reg, src, disp_reg, type, wide);
1292   }
1293 
1294   if (use_R29) {
1295     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1296   }
1297 
1298   if (patch != NULL) {
1299     patching_epilog(patch, patch_code, src, info);
1300   }
1301 
1302   if (info != NULL && !needs_explicit_null_check) {
1303     add_debug_info_for_null_check(offset, info);
1304   }
1305 }
1306 
1307 
1308 void LIR_Assembler::return_op(LIR_Opr result) {
1309   const Register return_pc        = R31;  // Must survive C-call to enable_stack_reserved_zone().
1310   const Register polling_page     = R12;
1311 
1312   // Pop the stack before the safepoint code.
1313   int frame_size = initial_frame_size_in_bytes();
1314   if (Assembler::is_simm(frame_size, 16)) {
1315     __ addi(R1_SP, R1_SP, frame_size);
1316   } else {
1317     __ pop_frame();
1318   }
1319 
1320   if (SafepointMechanism::uses_thread_local_poll()) {
1321     __ ld(polling_page, in_bytes(Thread::polling_page_offset()), R16_thread);
1322   } else {
1323     __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0);
1324   }
1325 
1326   // Restore return pc relative to callers' sp.
1327   __ ld(return_pc, _abi(lr), R1_SP);
1328   // Move return pc to LR.
1329   __ mtlr(return_pc);
1330 
1331   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1332     __ reserved_stack_check(return_pc);
1333   }
1334 
1335   // We need to mark the code position where the load from the safepoint
1336   // polling page was emitted as relocInfo::poll_return_type here.
1337   __ relocate(relocInfo::poll_return_type);
1338   __ load_from_polling_page(polling_page);
1339 
1340   // Return.
1341   __ blr();
1342 }
1343 
1344 
1345 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1346   const Register poll_addr = tmp->as_register();
1347   if (SafepointMechanism::uses_thread_local_poll()) {
1348     __ ld(poll_addr, in_bytes(Thread::polling_page_offset()), R16_thread);
1349   } else {
1350     __ load_const_optimized(poll_addr, (intptr_t)os::get_polling_page(), R0);
1351   }
1352   if (info != NULL) {
1353     add_debug_info_for_branch(info);
1354   }
1355   int offset = __ offset();
1356   __ relocate(relocInfo::poll_type);
1357   __ load_from_polling_page(poll_addr);
1358 
1359   return offset;
1360 }
1361 
1362 
1363 void LIR_Assembler::emit_static_call_stub() {
1364   address call_pc = __ pc();
1365   address stub = __ start_a_stub(static_call_stub_size());
1366   if (stub == NULL) {
1367     bailout("static call stub overflow");
1368     return;
1369   }
1370 
1371   // For java_to_interp stubs we use R11_scratch1 as scratch register
1372   // and in call trampoline stubs we use R12_scratch2. This way we
1373   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1374   const Register reg_scratch = R11_scratch1;
1375 
1376   // Create a static stub relocation which relates this stub
1377   // with the call instruction at insts_call_instruction_offset in the
1378   // instructions code-section.
1379   int start = __ offset();
1380   __ relocate(static_stub_Relocation::spec(call_pc));
1381 
1382   // Now, create the stub's code:
1383   // - load the TOC
1384   // - load the inline cache oop from the constant pool
1385   // - load the call target from the constant pool
1386   // - call
1387   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1388   AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1389   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1390 
1391   if (ReoptimizeCallSequences) {
1392     __ b64_patchable((address)-1, relocInfo::none);
1393   } else {
1394     AddressLiteral a((address)-1);
1395     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1396     __ mtctr(reg_scratch);
1397     __ bctr();
1398   }
1399   if (!success) {
1400     bailout("const section overflow");
1401     return;
1402   }
1403 
1404   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1405   __ end_a_stub();
1406 }
1407 
1408 
1409 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1410   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1411   if (opr1->is_single_fpu()) {
1412     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1413   } else if (opr1->is_double_fpu()) {
1414     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1415   } else if (opr1->is_single_cpu()) {
1416     if (opr2->is_constant()) {
1417       switch (opr2->as_constant_ptr()->type()) {
1418         case T_INT:
1419           {
1420             jint con = opr2->as_constant_ptr()->as_jint();
1421             if (unsigned_comp) {
1422               if (Assembler::is_uimm(con, 16)) {
1423                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1424               } else {
1425                 __ load_const_optimized(R0, con);
1426                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1427               }
1428             } else {
1429               if (Assembler::is_simm(con, 16)) {
1430                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1431               } else {
1432                 __ load_const_optimized(R0, con);
1433                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1434               }
1435             }
1436           }
1437           break;
1438 
1439         case T_OBJECT:
1440           // There are only equal/notequal comparisons on objects.
1441           {
1442             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1443             jobject con = opr2->as_constant_ptr()->as_jobject();
1444             if (con == NULL) {
1445               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1446             } else {
1447               jobject2reg(con, R0);
1448               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1449             }
1450           }
1451           break;
1452 
1453         default:
1454           ShouldNotReachHere();
1455           break;
1456       }
1457     } else {
1458       assert(opr1->type() != T_ADDRESS && opr2->type() != T_ADDRESS, "currently unsupported");
1459       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1460         // There are only equal/notequal comparisons on objects.
1461         assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1462         __ cmpd(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1463       } else {
1464         if (unsigned_comp) {
1465           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1466         } else {
1467           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1468         }
1469       }
1470     }
1471   } else if (opr1->is_double_cpu()) {
1472     if (opr2->is_constant()) {
1473       jlong con = opr2->as_constant_ptr()->as_jlong();
1474       if (unsigned_comp) {
1475         if (Assembler::is_uimm(con, 16)) {
1476           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1477         } else {
1478           __ load_const_optimized(R0, con);
1479           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1480         }
1481       } else {
1482         if (Assembler::is_simm(con, 16)) {
1483           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1484         } else {
1485           __ load_const_optimized(R0, con);
1486           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1487         }
1488       }
1489     } else if (opr2->is_register()) {
1490       if (unsigned_comp) {
1491         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1492       } else {
1493         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1494       }
1495     } else {
1496       ShouldNotReachHere();
1497     }
1498   } else {
1499     ShouldNotReachHere();
1500   }
1501 }
1502 
1503 
1504 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1505   const Register Rdst = dst->as_register();
1506   Label done;
1507   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1508     bool is_unordered_less = (code == lir_ucmp_fd2i);
1509     if (left->is_single_fpu()) {
1510       __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1511     } else if (left->is_double_fpu()) {
1512       __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1513     } else {
1514       ShouldNotReachHere();
1515     }
1516     __ li(Rdst, is_unordered_less ? -1 : 1);
1517     __ bso(CCR0, done);
1518   } else if (code == lir_cmp_l2i) {
1519     __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1520   } else {
1521     ShouldNotReachHere();
1522   }
1523   __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01
1524   __ srwi(Rdst, R0, 30);
1525   __ srawi(R0, R0, 31);
1526   __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1
1527   __ bind(done);
1528 }
1529 
1530 
1531 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1532   if (src->is_constant()) {
1533     lasm->const2reg(src, dst, lir_patch_none, NULL);
1534   } else if (src->is_register()) {
1535     lasm->reg2reg(src, dst);
1536   } else if (src->is_stack()) {
1537     lasm->stack2reg(src, dst, dst->type());
1538   } else {
1539     ShouldNotReachHere();
1540   }
1541 }
1542 
1543 
1544 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1545   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1546     load_to_reg(this, opr1, result); // Condition doesn't matter.
1547     return;
1548   }
1549 
1550   bool positive = false;
1551   Assembler::Condition cond = Assembler::equal;
1552   switch (condition) {
1553     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1554     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1555     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1556     case lir_cond_belowEqual:
1557     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1558     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1559     case lir_cond_aboveEqual:
1560     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1561     default:                    ShouldNotReachHere();
1562   }
1563 
1564   // Try to use isel on >=Power7.
1565   if (VM_Version::has_isel() && result->is_cpu_register()) {
1566     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1567     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1568 
1569     // We can use result_reg to load one operand if not already in register.
1570     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1571              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1572 
1573     if (first != second) {
1574       if (!o1_is_reg) {
1575         load_to_reg(this, opr1, result);
1576       }
1577 
1578       if (!o2_is_reg) {
1579         load_to_reg(this, opr2, result);
1580       }
1581 
1582       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1583       return;
1584     }
1585   } // isel
1586 
1587   load_to_reg(this, opr1, result);
1588 
1589   Label skip;
1590   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1591   int bi = Assembler::bi0(BOOL_RESULT, cond);
1592   __ bc(bo, bi, skip);
1593 
1594   load_to_reg(this, opr2, result);
1595   __ bind(skip);
1596 }
1597 
1598 
1599 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1600                              CodeEmitInfo* info, bool pop_fpu_stack) {
1601   assert(info == NULL, "unused on this code path");
1602   assert(left->is_register(), "wrong items state");
1603   assert(dest->is_register(), "wrong items state");
1604 
1605   if (right->is_register()) {
1606     if (dest->is_float_kind()) {
1607 
1608       FloatRegister lreg, rreg, res;
1609       if (right->is_single_fpu()) {
1610         lreg = left->as_float_reg();
1611         rreg = right->as_float_reg();
1612         res  = dest->as_float_reg();
1613         switch (code) {
1614           case lir_add: __ fadds(res, lreg, rreg); break;
1615           case lir_sub: __ fsubs(res, lreg, rreg); break;
1616           case lir_mul: // fall through
1617           case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break;
1618           case lir_div: // fall through
1619           case lir_div_strictfp: __ fdivs(res, lreg, rreg); break;
1620           default: ShouldNotReachHere();
1621         }
1622       } else {
1623         lreg = left->as_double_reg();
1624         rreg = right->as_double_reg();
1625         res  = dest->as_double_reg();
1626         switch (code) {
1627           case lir_add: __ fadd(res, lreg, rreg); break;
1628           case lir_sub: __ fsub(res, lreg, rreg); break;
1629           case lir_mul: // fall through
1630           case lir_mul_strictfp: __ fmul(res, lreg, rreg); break;
1631           case lir_div: // fall through
1632           case lir_div_strictfp: __ fdiv(res, lreg, rreg); break;
1633           default: ShouldNotReachHere();
1634         }
1635       }
1636 
1637     } else if (dest->is_double_cpu()) {
1638 
1639       Register dst_lo = dest->as_register_lo();
1640       Register op1_lo = left->as_pointer_register();
1641       Register op2_lo = right->as_pointer_register();
1642 
1643       switch (code) {
1644         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1645         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1646         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1647         default: ShouldNotReachHere();
1648       }
1649     } else {
1650       assert (right->is_single_cpu(), "Just Checking");
1651 
1652       Register lreg = left->as_register();
1653       Register res  = dest->as_register();
1654       Register rreg = right->as_register();
1655       switch (code) {
1656         case lir_add:  __ add  (res, lreg, rreg); break;
1657         case lir_sub:  __ sub  (res, lreg, rreg); break;
1658         case lir_mul:  __ mullw(res, lreg, rreg); break;
1659         default: ShouldNotReachHere();
1660       }
1661     }
1662   } else {
1663     assert (right->is_constant(), "must be constant");
1664 
1665     if (dest->is_single_cpu()) {
1666       Register lreg = left->as_register();
1667       Register res  = dest->as_register();
1668       int    simm16 = right->as_constant_ptr()->as_jint();
1669 
1670       switch (code) {
1671         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1672                        simm16 = -simm16;
1673         case lir_add:  if (res == lreg && simm16 == 0) break;
1674                        __ addi(res, lreg, simm16); break;
1675         case lir_mul:  if (res == lreg && simm16 == 1) break;
1676                        __ mulli(res, lreg, simm16); break;
1677         default: ShouldNotReachHere();
1678       }
1679     } else {
1680       Register lreg = left->as_pointer_register();
1681       Register res  = dest->as_register_lo();
1682       long con = right->as_constant_ptr()->as_jlong();
1683       assert(Assembler::is_simm16(con), "must be simm16");
1684 
1685       switch (code) {
1686         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1687                        con = -con;
1688         case lir_add:  if (res == lreg && con == 0) break;
1689                        __ addi(res, lreg, (int)con); break;
1690         case lir_mul:  if (res == lreg && con == 1) break;
1691                        __ mulli(res, lreg, (int)con); break;
1692         default: ShouldNotReachHere();
1693       }
1694     }
1695   }
1696 }
1697 
1698 
1699 void LIR_Assembler::fpop() {
1700   Unimplemented();
1701   // do nothing
1702 }
1703 
1704 
1705 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1706   switch (code) {
1707     case lir_sqrt: {
1708       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1709       break;
1710     }
1711     case lir_abs: {
1712       __ fabs(dest->as_double_reg(), value->as_double_reg());
1713       break;
1714     }
1715     default: {
1716       ShouldNotReachHere();
1717       break;
1718     }
1719   }
1720 }
1721 
1722 
1723 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1724   if (right->is_constant()) { // see do_LogicOp
1725     long uimm;
1726     Register d, l;
1727     if (dest->is_single_cpu()) {
1728       uimm = right->as_constant_ptr()->as_jint();
1729       d = dest->as_register();
1730       l = left->as_register();
1731     } else {
1732       uimm = right->as_constant_ptr()->as_jlong();
1733       d = dest->as_register_lo();
1734       l = left->as_register_lo();
1735     }
1736     long uimms  = (unsigned long)uimm >> 16,
1737          uimmss = (unsigned long)uimm >> 32;
1738 
1739     switch (code) {
1740       case lir_logic_and:
1741         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) {
1742           __ andi(d, l, uimm); // special cases
1743         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1744         else { __ andi_(d, l, uimm); }
1745         break;
1746 
1747       case lir_logic_or:
1748         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1749         else { __ ori(d, l, uimm); }
1750         break;
1751 
1752       case lir_logic_xor:
1753         if (uimm == -1) { __ nand(d, l, l); } // special case
1754         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1755         else { __ xori(d, l, uimm); }
1756         break;
1757 
1758       default: ShouldNotReachHere();
1759     }
1760   } else {
1761     assert(right->is_register(), "right should be in register");
1762 
1763     if (dest->is_single_cpu()) {
1764       switch (code) {
1765         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1766         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1767         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1768         default: ShouldNotReachHere();
1769       }
1770     } else {
1771       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1772                                                                         left->as_register_lo();
1773       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1774                                                                           right->as_register_lo();
1775 
1776       switch (code) {
1777         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1778         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1779         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1780         default: ShouldNotReachHere();
1781       }
1782     }
1783   }
1784 }
1785 
1786 
1787 int LIR_Assembler::shift_amount(BasicType t) {
1788   int elem_size = type2aelembytes(t);
1789   switch (elem_size) {
1790     case 1 : return 0;
1791     case 2 : return 1;
1792     case 4 : return 2;
1793     case 8 : return 3;
1794   }
1795   ShouldNotReachHere();
1796   return -1;
1797 }
1798 
1799 
1800 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1801   info->add_register_oop(exceptionOop);
1802 
1803   // Reuse the debug info from the safepoint poll for the throw op itself.
1804   address pc_for_athrow = __ pc();
1805   int pc_for_athrow_offset = __ offset();
1806   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1807   //__ relocate(rspec);
1808   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1809   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1810   add_call_info(pc_for_athrow_offset, info); // for exception handler
1811 
1812   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1813                                                                    : Runtime1::handle_exception_nofpu_id);
1814   //__ load_const_optimized(R0, stub);
1815   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1816   __ mtctr(R0);
1817   __ bctr();
1818 }
1819 
1820 
1821 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1822   // Note: Not used with EnableDebuggingOnDemand.
1823   assert(exceptionOop->as_register() == R3, "should match");
1824   __ b(_unwind_handler_entry);
1825 }
1826 
1827 
1828 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1829   Register src = op->src()->as_register();
1830   Register dst = op->dst()->as_register();
1831   Register src_pos = op->src_pos()->as_register();
1832   Register dst_pos = op->dst_pos()->as_register();
1833   Register length  = op->length()->as_register();
1834   Register tmp = op->tmp()->as_register();
1835   Register tmp2 = R0;
1836 
1837   int flags = op->flags();
1838   ciArrayKlass* default_type = op->expected_type();
1839   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1840   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1841 
1842   // Set up the arraycopy stub information.
1843   ArrayCopyStub* stub = op->stub();
1844   const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1845 
1846   // Always do stub if no type information is available. It's ok if
1847   // the known type isn't loaded since the code sanity checks
1848   // in debug mode and the type isn't required when we know the exact type
1849   // also check that the type is an array type.
1850   if (op->expected_type() == NULL) {
1851     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1852            length->is_nonvolatile(), "must preserve");
1853     address copyfunc_addr = StubRoutines::generic_arraycopy();
1854     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
1855 
1856     // 3 parms are int. Convert to long.
1857     __ mr(R3_ARG1, src);
1858     __ extsw(R4_ARG2, src_pos);
1859     __ mr(R5_ARG3, dst);
1860     __ extsw(R6_ARG4, dst_pos);
1861     __ extsw(R7_ARG5, length);
1862 
1863 #ifndef PRODUCT
1864     if (PrintC1Statistics) {
1865       address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1866       int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1867       __ lwz(R11_scratch1, simm16_offs, tmp);
1868       __ addi(R11_scratch1, R11_scratch1, 1);
1869       __ stw(R11_scratch1, simm16_offs, tmp);
1870     }
1871 #endif
1872     __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1873 
1874     __ nand(tmp, R3_RET, R3_RET);
1875     __ subf(length, tmp, length);
1876     __ add(src_pos, tmp, src_pos);
1877     __ add(dst_pos, tmp, dst_pos);
1878 
1879     __ cmpwi(CCR0, R3_RET, 0);
1880     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1881     __ bind(*stub->continuation());
1882     return;
1883   }
1884 
1885   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1886   Label cont, slow, copyfunc;
1887 
1888   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1889                                         LIR_OpArrayCopy::dst_null_check |
1890                                         LIR_OpArrayCopy::src_pos_positive_check |
1891                                         LIR_OpArrayCopy::dst_pos_positive_check |
1892                                         LIR_OpArrayCopy::length_positive_check);
1893 
1894   // Use only one conditional branch for simple checks.
1895   if (simple_check_flag_set) {
1896     ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1897 
1898     // Make sure src and dst are non-null.
1899     if (flags & LIR_OpArrayCopy::src_null_check) {
1900       __ cmpdi(combined_check, src, 0);
1901       tmp_check = CCR0;
1902     }
1903 
1904     if (flags & LIR_OpArrayCopy::dst_null_check) {
1905       __ cmpdi(tmp_check, dst, 0);
1906       if (tmp_check != combined_check) {
1907         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1908       }
1909       tmp_check = CCR0;
1910     }
1911 
1912     // Clear combined_check.eq if not already used.
1913     if (tmp_check == combined_check) {
1914       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1915       tmp_check = CCR0;
1916     }
1917 
1918     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1919       // Test src_pos register.
1920       __ cmpwi(tmp_check, src_pos, 0);
1921       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1922     }
1923 
1924     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1925       // Test dst_pos register.
1926       __ cmpwi(tmp_check, dst_pos, 0);
1927       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1928     }
1929 
1930     if (flags & LIR_OpArrayCopy::length_positive_check) {
1931       // Make sure length isn't negative.
1932       __ cmpwi(tmp_check, length, 0);
1933       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1934     }
1935 
1936     __ beq(combined_check, slow);
1937   }
1938 
1939   // If the compiler was not able to prove that exact type of the source or the destination
1940   // of the arraycopy is an array type, check at runtime if the source or the destination is
1941   // an instance type.
1942   if (flags & LIR_OpArrayCopy::type_check) {
1943     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1944       __ load_klass(tmp, dst);
1945       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1946       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1947       __ bge(CCR0, slow);
1948     }
1949 
1950     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1951       __ load_klass(tmp, src);
1952       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1953       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1954       __ bge(CCR0, slow);
1955     }
1956   }
1957 
1958   // Higher 32bits must be null.
1959   __ extsw(length, length);
1960 
1961   __ extsw(src_pos, src_pos);
1962   if (flags & LIR_OpArrayCopy::src_range_check) {
1963     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1964     __ add(tmp, length, src_pos);
1965     __ cmpld(CCR0, tmp2, tmp);
1966     __ ble(CCR0, slow);
1967   }
1968 
1969   __ extsw(dst_pos, dst_pos);
1970   if (flags & LIR_OpArrayCopy::dst_range_check) {
1971     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1972     __ add(tmp, length, dst_pos);
1973     __ cmpld(CCR0, tmp2, tmp);
1974     __ ble(CCR0, slow);
1975   }
1976 
1977   int shift = shift_amount(basic_type);
1978 
1979   if (!(flags & LIR_OpArrayCopy::type_check)) {
1980     __ b(cont);
1981   } else {
1982     // We don't know the array types are compatible.
1983     if (basic_type != T_OBJECT) {
1984       // Simple test for basic type arrays.
1985       if (UseCompressedClassPointers) {
1986         // We don't need decode because we just need to compare.
1987         __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1988         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1989         __ cmpw(CCR0, tmp, tmp2);
1990       } else {
1991         __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1992         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1993         __ cmpd(CCR0, tmp, tmp2);
1994       }
1995       __ beq(CCR0, cont);
1996     } else {
1997       // For object arrays, if src is a sub class of dst then we can
1998       // safely do the copy.
1999       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2000 
2001       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2002       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2003 
2004       __ load_klass(sub_klass, src);
2005       __ load_klass(super_klass, dst);
2006 
2007       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2008                                        &cont, copyfunc_addr != NULL ? &copyfunc : &slow, NULL);
2009 
2010       address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2011       //__ load_const_optimized(tmp, slow_stc, tmp2);
2012       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2013       __ mtctr(tmp);
2014       __ bctrl(); // sets CR0
2015       __ beq(CCR0, cont);
2016 
2017       if (copyfunc_addr != NULL) { // Use stub if available.
2018         __ bind(copyfunc);
2019         // Src is not a sub class of dst so we have to do a
2020         // per-element check.
2021         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2022         if ((flags & mask) != mask) {
2023           assert(flags & mask, "one of the two should be known to be an object array");
2024 
2025           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2026             __ load_klass(tmp, src);
2027           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2028             __ load_klass(tmp, dst);
2029           }
2030 
2031           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2032 
2033           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2034           __ load_const_optimized(tmp, objArray_lh);
2035           __ cmpw(CCR0, tmp, tmp2);
2036           __ bne(CCR0, slow);
2037         }
2038 
2039         Register src_ptr = R3_ARG1;
2040         Register dst_ptr = R4_ARG2;
2041         Register len     = R5_ARG3;
2042         Register chk_off = R6_ARG4;
2043         Register super_k = R7_ARG5;
2044 
2045         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2046         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2047         if (shift == 0) {
2048           __ add(src_ptr, src_pos, src_ptr);
2049           __ add(dst_ptr, dst_pos, dst_ptr);
2050         } else {
2051           __ sldi(tmp, src_pos, shift);
2052           __ sldi(tmp2, dst_pos, shift);
2053           __ add(src_ptr, tmp, src_ptr);
2054           __ add(dst_ptr, tmp2, dst_ptr);
2055         }
2056 
2057         __ load_klass(tmp, dst);
2058         __ mr(len, length);
2059 
2060         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2061         __ ld(super_k, ek_offset, tmp);
2062 
2063         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2064         __ lwz(chk_off, sco_offset, super_k);
2065 
2066         __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2067 
2068 #ifndef PRODUCT
2069         if (PrintC1Statistics) {
2070           Label failed;
2071           __ cmpwi(CCR0, R3_RET, 0);
2072           __ bne(CCR0, failed);
2073           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2074           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2075           __ lwz(R11_scratch1, simm16_offs, tmp);
2076           __ addi(R11_scratch1, R11_scratch1, 1);
2077           __ stw(R11_scratch1, simm16_offs, tmp);
2078           __ bind(failed);
2079         }
2080 #endif
2081 
2082         __ nand(tmp, R3_RET, R3_RET);
2083         __ cmpwi(CCR0, R3_RET, 0);
2084         __ beq(CCR0, *stub->continuation());
2085 
2086 #ifndef PRODUCT
2087         if (PrintC1Statistics) {
2088           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2089           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2090           __ lwz(R11_scratch1, simm16_offs, tmp);
2091           __ addi(R11_scratch1, R11_scratch1, 1);
2092           __ stw(R11_scratch1, simm16_offs, tmp);
2093         }
2094 #endif
2095 
2096         __ subf(length, tmp, length);
2097         __ add(src_pos, tmp, src_pos);
2098         __ add(dst_pos, tmp, dst_pos);
2099       }
2100     }
2101   }
2102   __ bind(slow);
2103   __ b(*stub->entry());
2104   __ bind(cont);
2105 
2106 #ifdef ASSERT
2107   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2108     // Sanity check the known type with the incoming class. For the
2109     // primitive case the types must match exactly with src.klass and
2110     // dst.klass each exactly matching the default type. For the
2111     // object array case, if no type check is needed then either the
2112     // dst type is exactly the expected type and the src type is a
2113     // subtype which we can't check or src is the same array as dst
2114     // but not necessarily exactly of type default_type.
2115     Label known_ok, halt;
2116     metadata2reg(op->expected_type()->constant_encoding(), tmp);
2117     if (UseCompressedClassPointers) {
2118       // Tmp holds the default type. It currently comes uncompressed after the
2119       // load of a constant, so encode it.
2120       __ encode_klass_not_null(tmp);
2121       // Load the raw value of the dst klass, since we will be comparing
2122       // uncompressed values directly.
2123       __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2124       __ cmpw(CCR0, tmp, tmp2);
2125       if (basic_type != T_OBJECT) {
2126         __ bne(CCR0, halt);
2127         // Load the raw value of the src klass.
2128         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2129         __ cmpw(CCR0, tmp, tmp2);
2130         __ beq(CCR0, known_ok);
2131       } else {
2132         __ beq(CCR0, known_ok);
2133         __ cmpw(CCR0, src, dst);
2134         __ beq(CCR0, known_ok);
2135       }
2136     } else {
2137       __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2138       __ cmpd(CCR0, tmp, tmp2);
2139       if (basic_type != T_OBJECT) {
2140         __ bne(CCR0, halt);
2141         // Load the raw value of the src klass.
2142         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2143         __ cmpd(CCR0, tmp, tmp2);
2144         __ beq(CCR0, known_ok);
2145       } else {
2146         __ beq(CCR0, known_ok);
2147         __ cmpd(CCR0, src, dst);
2148         __ beq(CCR0, known_ok);
2149       }
2150     }
2151     __ bind(halt);
2152     __ stop("incorrect type information in arraycopy");
2153     __ bind(known_ok);
2154   }
2155 #endif
2156 
2157 #ifndef PRODUCT
2158   if (PrintC1Statistics) {
2159     address counter = Runtime1::arraycopy_count_address(basic_type);
2160     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2161     __ lwz(R11_scratch1, simm16_offs, tmp);
2162     __ addi(R11_scratch1, R11_scratch1, 1);
2163     __ stw(R11_scratch1, simm16_offs, tmp);
2164   }
2165 #endif
2166 
2167   Register src_ptr = R3_ARG1;
2168   Register dst_ptr = R4_ARG2;
2169   Register len     = R5_ARG3;
2170 
2171   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2172   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2173   if (shift == 0) {
2174     __ add(src_ptr, src_pos, src_ptr);
2175     __ add(dst_ptr, dst_pos, dst_ptr);
2176   } else {
2177     __ sldi(tmp, src_pos, shift);
2178     __ sldi(tmp2, dst_pos, shift);
2179     __ add(src_ptr, tmp, src_ptr);
2180     __ add(dst_ptr, tmp2, dst_ptr);
2181   }
2182 
2183   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2184   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2185   const char *name;
2186   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2187 
2188   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2189   __ mr(len, length);
2190   __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2191 
2192   __ bind(*stub->continuation());
2193 }
2194 
2195 
2196 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2197   if (dest->is_single_cpu()) {
2198     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2199 #ifdef _LP64
2200     if (left->type() == T_OBJECT) {
2201       switch (code) {
2202         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2203         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2204         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2205         default: ShouldNotReachHere();
2206       }
2207     } else
2208 #endif
2209       switch (code) {
2210         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2211         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2212         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2213         default: ShouldNotReachHere();
2214       }
2215   } else {
2216     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2217     switch (code) {
2218       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2219       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2220       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2221       default: ShouldNotReachHere();
2222     }
2223   }
2224 }
2225 
2226 
2227 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2228 #ifdef _LP64
2229   if (left->type() == T_OBJECT) {
2230     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2231     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2232     else {
2233       switch (code) {
2234         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2235         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2236         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2237         default: ShouldNotReachHere();
2238       }
2239     }
2240     return;
2241   }
2242 #endif
2243 
2244   if (dest->is_single_cpu()) {
2245     count = count & 0x1F; // Java spec
2246     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2247     else {
2248       switch (code) {
2249         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2250         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2251         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2252         default: ShouldNotReachHere();
2253       }
2254     }
2255   } else if (dest->is_double_cpu()) {
2256     count = count & 63; // Java spec
2257     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2258     else {
2259       switch (code) {
2260         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2261         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2262         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2263         default: ShouldNotReachHere();
2264       }
2265     }
2266   } else {
2267     ShouldNotReachHere();
2268   }
2269 }
2270 
2271 
2272 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2273   if (op->init_check()) {
2274     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2275       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2276     } else {
2277       add_debug_info_for_null_check_here(op->stub()->info());
2278     }
2279     __ lbz(op->tmp1()->as_register(),
2280            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2281     __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2282     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2283   }
2284   __ allocate_object(op->obj()->as_register(),
2285                      op->tmp1()->as_register(),
2286                      op->tmp2()->as_register(),
2287                      op->tmp3()->as_register(),
2288                      op->header_size(),
2289                      op->object_size(),
2290                      op->klass()->as_register(),
2291                      *op->stub()->entry());
2292 
2293   __ bind(*op->stub()->continuation());
2294   __ verify_oop(op->obj()->as_register());
2295 }
2296 
2297 
2298 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2299   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2300   if (UseSlowPath ||
2301       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2302       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2303     __ b(*op->stub()->entry());
2304   } else {
2305     __ allocate_array(op->obj()->as_register(),
2306                       op->len()->as_register(),
2307                       op->tmp1()->as_register(),
2308                       op->tmp2()->as_register(),
2309                       op->tmp3()->as_register(),
2310                       arrayOopDesc::header_size(op->type()),
2311                       type2aelembytes(op->type()),
2312                       op->klass()->as_register(),
2313                       *op->stub()->entry());
2314   }
2315   __ bind(*op->stub()->continuation());
2316 }
2317 
2318 
2319 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2320                                         ciMethodData *md, ciProfileData *data,
2321                                         Register recv, Register tmp1, Label* update_done) {
2322   uint i;
2323   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2324     Label next_test;
2325     // See if the receiver is receiver[n].
2326     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2327     __ verify_klass_ptr(tmp1);
2328     __ cmpd(CCR0, recv, tmp1);
2329     __ bne(CCR0, next_test);
2330 
2331     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2332     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2333     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2334     __ b(*update_done);
2335 
2336     __ bind(next_test);
2337   }
2338 
2339   // Didn't find receiver; find next empty slot and fill it in.
2340   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2341     Label next_test;
2342     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2343     __ cmpdi(CCR0, tmp1, 0);
2344     __ bne(CCR0, next_test);
2345     __ li(tmp1, DataLayout::counter_increment);
2346     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2347     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2348     __ b(*update_done);
2349 
2350     __ bind(next_test);
2351   }
2352 }
2353 
2354 
2355 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2356                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2357   md = method->method_data_or_null();
2358   assert(md != NULL, "Sanity");
2359   data = md->bci_to_data(bci);
2360   assert(data != NULL,       "need data for checkcast");
2361   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2362   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2363     // The offset is large so bias the mdo by the base of the slot so
2364     // that the ld can use simm16s to reference the slots of the data.
2365     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2366   }
2367 }
2368 
2369 
2370 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2371   const Register obj = op->object()->as_register(); // Needs to live in this register at safepoint (patching stub).
2372   Register k_RInfo = op->tmp1()->as_register();
2373   Register klass_RInfo = op->tmp2()->as_register();
2374   Register Rtmp1 = op->tmp3()->as_register();
2375   Register dst = op->result_opr()->as_register();
2376   ciKlass* k = op->klass();
2377   bool should_profile = op->should_profile();
2378   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2379   bool reg_conflict = false;
2380   if (obj == k_RInfo) {
2381     k_RInfo = dst;
2382     reg_conflict = true;
2383   } else if (obj == klass_RInfo) {
2384     klass_RInfo = dst;
2385     reg_conflict = true;
2386   } else if (obj == Rtmp1) {
2387     Rtmp1 = dst;
2388     reg_conflict = true;
2389   }
2390   assert_different_registers(obj, k_RInfo, klass_RInfo, Rtmp1);
2391 
2392   __ cmpdi(CCR0, obj, 0);
2393 
2394   ciMethodData* md = NULL;
2395   ciProfileData* data = NULL;
2396   int mdo_offset_bias = 0;
2397   if (should_profile) {
2398     ciMethod* method = op->profiled_method();
2399     assert(method != NULL, "Should have method");
2400     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2401 
2402     Register mdo      = k_RInfo;
2403     Register data_val = Rtmp1;
2404     Label not_null;
2405     __ bne(CCR0, not_null);
2406     metadata2reg(md->constant_encoding(), mdo);
2407     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2408     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2409     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2410     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2411     __ b(*obj_is_null);
2412     __ bind(not_null);
2413   } else {
2414     __ beq(CCR0, *obj_is_null);
2415   }
2416 
2417   // get object class
2418   __ load_klass(klass_RInfo, obj);
2419 
2420   if (k->is_loaded()) {
2421     metadata2reg(k->constant_encoding(), k_RInfo);
2422   } else {
2423     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2424   }
2425 
2426   Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2427   Label *failure_target = should_profile ? &profile_cast_failure : failure;
2428   Label *success_target = should_profile ? &profile_cast_success : success;
2429 
2430   if (op->fast_check()) {
2431     assert_different_registers(klass_RInfo, k_RInfo);
2432     __ cmpd(CCR0, k_RInfo, klass_RInfo);
2433     if (should_profile) {
2434       __ bne(CCR0, *failure_target);
2435       // Fall through to success case.
2436     } else {
2437       __ beq(CCR0, *success);
2438       // Fall through to failure case.
2439     }
2440   } else {
2441     bool need_slow_path = true;
2442     if (k->is_loaded()) {
2443       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2444         need_slow_path = false;
2445       }
2446       // Perform the fast part of the checking logic.
2447       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2448                                        failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2449     } else {
2450       // Perform the fast part of the checking logic.
2451       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2452     }
2453     if (!need_slow_path) {
2454       if (!should_profile) { __ b(*success); }
2455     } else {
2456       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2457       address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2458       // Stub needs fixed registers (tmp1-3).
2459       Register original_k_RInfo = op->tmp1()->as_register();
2460       Register original_klass_RInfo = op->tmp2()->as_register();
2461       Register original_Rtmp1 = op->tmp3()->as_register();
2462       bool keep_obj_alive = reg_conflict && (op->code() == lir_checkcast);
2463       bool keep_klass_RInfo_alive = (obj == original_klass_RInfo) && should_profile;
2464       if (keep_obj_alive && (obj != original_Rtmp1)) { __ mr(R0, obj); }
2465       __ mr_if_needed(original_k_RInfo, k_RInfo);
2466       __ mr_if_needed(original_klass_RInfo, klass_RInfo);
2467       if (keep_obj_alive) { __ mr(dst, (obj == original_Rtmp1) ? obj : R0); }
2468       //__ load_const_optimized(original_Rtmp1, entry, R0);
2469       __ calculate_address_from_global_toc(original_Rtmp1, entry, true, true, false);
2470       __ mtctr(original_Rtmp1);
2471       __ bctrl(); // sets CR0
2472       if (keep_obj_alive) {
2473         if (keep_klass_RInfo_alive) { __ mr(R0, obj); }
2474         __ mr(obj, dst);
2475       }
2476       if (should_profile) {
2477         __ bne(CCR0, *failure_target);
2478         if (keep_klass_RInfo_alive) { __ mr(klass_RInfo, keep_obj_alive ? R0 : obj); }
2479         // Fall through to success case.
2480       } else {
2481         __ beq(CCR0, *success);
2482         // Fall through to failure case.
2483       }
2484     }
2485   }
2486 
2487   if (should_profile) {
2488     Register mdo = k_RInfo, recv = klass_RInfo;
2489     assert_different_registers(mdo, recv, Rtmp1);
2490     __ bind(profile_cast_success);
2491     metadata2reg(md->constant_encoding(), mdo);
2492     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2493     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2494     __ b(*success);
2495 
2496     // Cast failure case.
2497     __ bind(profile_cast_failure);
2498     metadata2reg(md->constant_encoding(), mdo);
2499     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2500     __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2501     __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2502     __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2503   }
2504 
2505   __ bind(*failure);
2506 }
2507 
2508 
2509 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2510   LIR_Code code = op->code();
2511   if (code == lir_store_check) {
2512     Register value = op->object()->as_register();
2513     Register array = op->array()->as_register();
2514     Register k_RInfo = op->tmp1()->as_register();
2515     Register klass_RInfo = op->tmp2()->as_register();
2516     Register Rtmp1 = op->tmp3()->as_register();
2517     bool should_profile = op->should_profile();
2518 
2519     __ verify_oop(value);
2520     CodeStub* stub = op->stub();
2521     // Check if it needs to be profiled.
2522     ciMethodData* md = NULL;
2523     ciProfileData* data = NULL;
2524     int mdo_offset_bias = 0;
2525     if (should_profile) {
2526       ciMethod* method = op->profiled_method();
2527       assert(method != NULL, "Should have method");
2528       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2529     }
2530     Label profile_cast_success, failure, done;
2531     Label *success_target = should_profile ? &profile_cast_success : &done;
2532 
2533     __ cmpdi(CCR0, value, 0);
2534     if (should_profile) {
2535       Label not_null;
2536       __ bne(CCR0, not_null);
2537       Register mdo      = k_RInfo;
2538       Register data_val = Rtmp1;
2539       metadata2reg(md->constant_encoding(), mdo);
2540       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2541       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2542       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2543       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2544       __ b(done);
2545       __ bind(not_null);
2546     } else {
2547       __ beq(CCR0, done);
2548     }
2549     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2550       explicit_null_check(array, op->info_for_exception());
2551     } else {
2552       add_debug_info_for_null_check_here(op->info_for_exception());
2553     }
2554     __ load_klass(k_RInfo, array);
2555     __ load_klass(klass_RInfo, value);
2556 
2557     // Get instance klass.
2558     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2559     // Perform the fast part of the checking logic.
2560     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2561 
2562     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2563     const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2564     //__ load_const_optimized(R0, slow_path);
2565     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2566     __ mtctr(R0);
2567     __ bctrl(); // sets CR0
2568     if (!should_profile) {
2569       __ beq(CCR0, done);
2570       __ bind(failure);
2571     } else {
2572       __ bne(CCR0, failure);
2573       // Fall through to the success case.
2574 
2575       Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2576       assert_different_registers(value, mdo, recv, tmp1);
2577       __ bind(profile_cast_success);
2578       metadata2reg(md->constant_encoding(), mdo);
2579       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2580       __ load_klass(recv, value);
2581       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2582       __ b(done);
2583 
2584       // Cast failure case.
2585       __ bind(failure);
2586       metadata2reg(md->constant_encoding(), mdo);
2587       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2588       Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2589       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2590       __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2591       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2592     }
2593     __ b(*stub->entry());
2594     __ bind(done);
2595 
2596   } else if (code == lir_checkcast) {
2597     Label success, failure;
2598     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success);
2599     __ b(*op->stub()->entry());
2600     __ align(32, 12);
2601     __ bind(success);
2602     __ mr_if_needed(op->result_opr()->as_register(), op->object()->as_register());
2603   } else if (code == lir_instanceof) {
2604     Register dst = op->result_opr()->as_register();
2605     Label success, failure, done;
2606     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2607     __ li(dst, 0);
2608     __ b(done);
2609     __ align(32, 12);
2610     __ bind(success);
2611     __ li(dst, 1);
2612     __ bind(done);
2613   } else {
2614     ShouldNotReachHere();
2615   }
2616 }
2617 
2618 
2619 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2620   Register addr = op->addr()->as_pointer_register();
2621   Register cmp_value = noreg, new_value = noreg;
2622   bool is_64bit = false;
2623 
2624   if (op->code() == lir_cas_long) {
2625     cmp_value = op->cmp_value()->as_register_lo();
2626     new_value = op->new_value()->as_register_lo();
2627     is_64bit = true;
2628   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2629     cmp_value = op->cmp_value()->as_register();
2630     new_value = op->new_value()->as_register();
2631     if (op->code() == lir_cas_obj) {
2632       if (UseCompressedOops) {
2633         Register t1 = op->tmp1()->as_register();
2634         Register t2 = op->tmp2()->as_register();
2635         cmp_value = __ encode_heap_oop(t1, cmp_value);
2636         new_value = __ encode_heap_oop(t2, new_value);
2637       } else {
2638         is_64bit = true;
2639       }
2640     }
2641   } else {
2642     Unimplemented();
2643   }
2644 
2645   if (is_64bit) {
2646     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2647                 MacroAssembler::MemBarNone,
2648                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2649                 noreg, NULL, /*check without ldarx first*/true);
2650   } else {
2651     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2652                 MacroAssembler::MemBarNone,
2653                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2654                 noreg, /*check without ldarx first*/true);
2655   }
2656 
2657   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2658     __ isync();
2659   } else {
2660     __ sync();
2661   }
2662 }
2663 
2664 
2665 void LIR_Assembler::set_24bit_FPU() {
2666   Unimplemented();
2667 }
2668 
2669 void LIR_Assembler::reset_FPU() {
2670   Unimplemented();
2671 }
2672 
2673 
2674 void LIR_Assembler::breakpoint() {
2675   __ illtrap();
2676 }
2677 
2678 
2679 void LIR_Assembler::push(LIR_Opr opr) {
2680   Unimplemented();
2681 }
2682 
2683 void LIR_Assembler::pop(LIR_Opr opr) {
2684   Unimplemented();
2685 }
2686 
2687 
2688 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2689   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2690   Register dst = dst_opr->as_register();
2691   Register reg = mon_addr.base();
2692   int offset = mon_addr.disp();
2693   // Compute pointer to BasicLock.
2694   __ add_const_optimized(dst, reg, offset);
2695 }
2696 
2697 
2698 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2699   Register obj = op->obj_opr()->as_register();
2700   Register hdr = op->hdr_opr()->as_register();
2701   Register lock = op->lock_opr()->as_register();
2702 
2703   // Obj may not be an oop.
2704   if (op->code() == lir_lock) {
2705     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2706     if (UseFastLocking) {
2707       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2708       // Add debug info for NullPointerException only if one is possible.
2709       if (op->info() != NULL) {
2710         if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2711           explicit_null_check(obj, op->info());
2712         } else {
2713           add_debug_info_for_null_check_here(op->info());
2714         }
2715       }
2716       __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2717     } else {
2718       // always do slow locking
2719       // note: The slow locking code could be inlined here, however if we use
2720       //       slow locking, speed doesn't matter anyway and this solution is
2721       //       simpler and requires less duplicated code - additionally, the
2722       //       slow locking code is the same in either case which simplifies
2723       //       debugging.
2724       __ b(*op->stub()->entry());
2725     }
2726   } else {
2727     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2728     if (UseFastLocking) {
2729       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2730       __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2731     } else {
2732       // always do slow unlocking
2733       // note: The slow unlocking code could be inlined here, however if we use
2734       //       slow unlocking, speed doesn't matter anyway and this solution is
2735       //       simpler and requires less duplicated code - additionally, the
2736       //       slow unlocking code is the same in either case which simplifies
2737       //       debugging.
2738       __ b(*op->stub()->entry());
2739     }
2740   }
2741   __ bind(*op->stub()->continuation());
2742 }
2743 
2744 
2745 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2746   ciMethod* method = op->profiled_method();
2747   int bci          = op->profiled_bci();
2748   ciMethod* callee = op->profiled_callee();
2749 
2750   // Update counter for all call types.
2751   ciMethodData* md = method->method_data_or_null();
2752   assert(md != NULL, "Sanity");
2753   ciProfileData* data = md->bci_to_data(bci);
2754   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2755   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2756   Register mdo = op->mdo()->as_register();
2757 #ifdef _LP64
2758   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2759   Register tmp1 = op->tmp1()->as_register_lo();
2760 #else
2761   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2762   Register tmp1 = op->tmp1()->as_register();
2763 #endif
2764   metadata2reg(md->constant_encoding(), mdo);
2765   int mdo_offset_bias = 0;
2766   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2767                             data->size_in_bytes())) {
2768     // The offset is large so bias the mdo by the base of the slot so
2769     // that the ld can use simm16s to reference the slots of the data.
2770     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2771     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2772   }
2773 
2774   // Perform additional virtual call profiling for invokevirtual and
2775   // invokeinterface bytecodes
2776   if (op->should_profile_receiver_type()) {
2777     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2778     Register recv = op->recv()->as_register();
2779     assert_different_registers(mdo, tmp1, recv);
2780     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2781     ciKlass* known_klass = op->known_holder();
2782     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2783       // We know the type that will be seen at this call site; we can
2784       // statically update the MethodData* rather than needing to do
2785       // dynamic tests on the receiver type.
2786 
2787       // NOTE: we should probably put a lock around this search to
2788       // avoid collisions by concurrent compilations.
2789       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2790       uint i;
2791       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2792         ciKlass* receiver = vc_data->receiver(i);
2793         if (known_klass->equals(receiver)) {
2794           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2795           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2796           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2797           return;
2798         }
2799       }
2800 
2801       // Receiver type not found in profile data; select an empty slot.
2802 
2803       // Note that this is less efficient than it should be because it
2804       // always does a write to the receiver part of the
2805       // VirtualCallData rather than just the first time.
2806       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2807         ciKlass* receiver = vc_data->receiver(i);
2808         if (receiver == NULL) {
2809           metadata2reg(known_klass->constant_encoding(), tmp1);
2810           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2811 
2812           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2813           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2814           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2815           return;
2816         }
2817       }
2818     } else {
2819       __ load_klass(recv, recv);
2820       Label update_done;
2821       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2822       // Receiver did not match any saved receiver and there is no empty row for it.
2823       // Increment total counter to indicate polymorphic case.
2824       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2825       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2826       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2827 
2828       __ bind(update_done);
2829     }
2830   } else {
2831     // Static call
2832     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2833     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2834     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2835   }
2836 }
2837 
2838 
2839 void LIR_Assembler::align_backward_branch_target() {
2840   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2841 }
2842 
2843 
2844 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2845   Unimplemented();
2846 }
2847 
2848 
2849 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2850   // tmp must be unused
2851   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2852   assert(left->is_register(), "can only handle registers");
2853 
2854   if (left->is_single_cpu()) {
2855     __ neg(dest->as_register(), left->as_register());
2856   } else if (left->is_single_fpu()) {
2857     __ fneg(dest->as_float_reg(), left->as_float_reg());
2858   } else if (left->is_double_fpu()) {
2859     __ fneg(dest->as_double_reg(), left->as_double_reg());
2860   } else {
2861     assert (left->is_double_cpu(), "Must be a long");
2862     __ neg(dest->as_register_lo(), left->as_register_lo());
2863   }
2864 }
2865 
2866 
2867 void LIR_Assembler::fxch(int i) {
2868   Unimplemented();
2869 }
2870 
2871 void LIR_Assembler::fld(int i) {
2872   Unimplemented();
2873 }
2874 
2875 void LIR_Assembler::ffree(int i) {
2876   Unimplemented();
2877 }
2878 
2879 
2880 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2881                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2882   // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2883   if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2884       dest == Runtime1::entry_for(Runtime1::new_multi_array_id   )) {
2885     //__ load_const_optimized(R0, dest);
2886     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2887     __ mtctr(R0);
2888     __ bctrl();
2889     assert(info != NULL, "sanity");
2890     add_call_info_here(info);
2891     return;
2892   }
2893 
2894   __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2895   if (info != NULL) {
2896     add_call_info_here(info);
2897   }
2898 }
2899 
2900 
2901 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2902   ShouldNotReachHere(); // Not needed on _LP64.
2903 }
2904 
2905 void LIR_Assembler::membar() {
2906   __ fence();
2907 }
2908 
2909 void LIR_Assembler::membar_acquire() {
2910   __ acquire();
2911 }
2912 
2913 void LIR_Assembler::membar_release() {
2914   __ release();
2915 }
2916 
2917 void LIR_Assembler::membar_loadload() {
2918   __ membar(Assembler::LoadLoad);
2919 }
2920 
2921 void LIR_Assembler::membar_storestore() {
2922   __ membar(Assembler::StoreStore);
2923 }
2924 
2925 void LIR_Assembler::membar_loadstore() {
2926   __ membar(Assembler::LoadStore);
2927 }
2928 
2929 void LIR_Assembler::membar_storeload() {
2930   __ membar(Assembler::StoreLoad);
2931 }
2932 
2933 void LIR_Assembler::on_spin_wait() {
2934   Unimplemented();
2935 }
2936 
2937 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2938   assert(patch_code == lir_patch_none, "Patch code not supported");
2939   LIR_Address* addr = addr_opr->as_address_ptr();
2940   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2941   if (addr->index()->is_illegal()) {
2942     __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2943   } else {
2944     assert(addr->disp() == 0, "can't have both: index and disp");
2945     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2946   }
2947 }
2948 
2949 
2950 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2951   ShouldNotReachHere();
2952 }
2953 
2954 
2955 #ifdef ASSERT
2956 // Emit run-time assertion.
2957 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2958   Unimplemented();
2959 }
2960 #endif
2961 
2962 
2963 void LIR_Assembler::peephole(LIR_List* lir) {
2964   // Optimize instruction pairs before emitting.
2965   LIR_OpList* inst = lir->instructions_list();
2966   for (int i = 1; i < inst->length(); i++) {
2967     LIR_Op* op = inst->at(i);
2968 
2969     // 2 register-register-moves
2970     if (op->code() == lir_move) {
2971       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2972               res2 = ((LIR_Op1*)op)->result_opr();
2973       if (in2->is_register() && res2->is_register()) {
2974         LIR_Op* prev = inst->at(i - 1);
2975         if (prev && prev->code() == lir_move) {
2976           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2977                   res1 = ((LIR_Op1*)prev)->result_opr();
2978           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2979             inst->remove_at(i);
2980           }
2981         }
2982       }
2983     }
2984 
2985   }
2986   return;
2987 }
2988 
2989 
2990 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2991   const LIR_Address *addr = src->as_address_ptr();
2992   assert(addr->disp() == 0 && addr->index()->is_illegal(), "use leal!");
2993   const Register Rptr = addr->base()->as_pointer_register(),
2994                  Rtmp = tmp->as_register();
2995   Register Rco = noreg;
2996   if (UseCompressedOops && data->is_oop()) {
2997     Rco = __ encode_heap_oop(Rtmp, data->as_register());
2998   }
2999 
3000   Label Lretry;
3001   __ bind(Lretry);
3002 
3003   if (data->type() == T_INT) {
3004     const Register Rold = dest->as_register(),
3005                    Rsrc = data->as_register();
3006     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3007     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3008     if (code == lir_xadd) {
3009       __ add(Rtmp, Rsrc, Rold);
3010       __ stwcx_(Rtmp, Rptr);
3011     } else {
3012       __ stwcx_(Rsrc, Rptr);
3013     }
3014   } else if (data->is_oop()) {
3015     assert(code == lir_xchg, "xadd for oops");
3016     const Register Rold = dest->as_register();
3017     if (UseCompressedOops) {
3018       assert_different_registers(Rptr, Rold, Rco);
3019       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3020       __ stwcx_(Rco, Rptr);
3021     } else {
3022       const Register Robj = data->as_register();
3023       assert_different_registers(Rptr, Rold, Robj);
3024       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3025       __ stdcx_(Robj, Rptr);
3026     }
3027   } else if (data->type() == T_LONG) {
3028     const Register Rold = dest->as_register_lo(),
3029                    Rsrc = data->as_register_lo();
3030     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3031     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3032     if (code == lir_xadd) {
3033       __ add(Rtmp, Rsrc, Rold);
3034       __ stdcx_(Rtmp, Rptr);
3035     } else {
3036       __ stdcx_(Rsrc, Rptr);
3037     }
3038   } else {
3039     ShouldNotReachHere();
3040   }
3041 
3042   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3043     __ bne_predict_not_taken(CCR0, Lretry);
3044   } else {
3045     __ bne(                  CCR0, Lretry);
3046   }
3047 
3048   if (UseCompressedOops && data->is_oop()) {
3049     __ decode_heap_oop(dest->as_register());
3050   }
3051 }
3052 
3053 
3054 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3055   Register obj = op->obj()->as_register();
3056   Register tmp = op->tmp()->as_pointer_register();
3057   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3058   ciKlass* exact_klass = op->exact_klass();
3059   intptr_t current_klass = op->current_klass();
3060   bool not_null = op->not_null();
3061   bool no_conflict = op->no_conflict();
3062 
3063   Label Lupdate, Ldo_update, Ldone;
3064 
3065   bool do_null = !not_null;
3066   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3067   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3068 
3069   assert(do_null || do_update, "why are we here?");
3070   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3071 
3072   __ verify_oop(obj);
3073 
3074   if (do_null) {
3075     if (!TypeEntries::was_null_seen(current_klass)) {
3076       __ cmpdi(CCR0, obj, 0);
3077       __ bne(CCR0, Lupdate);
3078       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3079       __ ori(R0, R0, TypeEntries::null_seen);
3080       if (do_update) {
3081         __ b(Ldo_update);
3082       } else {
3083         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3084       }
3085     } else {
3086       if (do_update) {
3087         __ cmpdi(CCR0, obj, 0);
3088         __ beq(CCR0, Ldone);
3089       }
3090     }
3091 #ifdef ASSERT
3092   } else {
3093     __ cmpdi(CCR0, obj, 0);
3094     __ bne(CCR0, Lupdate);
3095     __ stop("unexpect null obj", 0x9652);
3096 #endif
3097   }
3098 
3099   __ bind(Lupdate);
3100   if (do_update) {
3101     Label Lnext;
3102     const Register klass = R29_TOC; // kill and reload
3103     bool klass_reg_used = false;
3104 #ifdef ASSERT
3105     if (exact_klass != NULL) {
3106       Label ok;
3107       klass_reg_used = true;
3108       __ load_klass(klass, obj);
3109       metadata2reg(exact_klass->constant_encoding(), R0);
3110       __ cmpd(CCR0, klass, R0);
3111       __ beq(CCR0, ok);
3112       __ stop("exact klass and actual klass differ", 0x8564);
3113       __ bind(ok);
3114     }
3115 #endif
3116 
3117     if (!no_conflict) {
3118       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3119         klass_reg_used = true;
3120         if (exact_klass != NULL) {
3121           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3122           metadata2reg(exact_klass->constant_encoding(), klass);
3123         } else {
3124           __ load_klass(klass, obj);
3125           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3126         }
3127 
3128         // Like InterpreterMacroAssembler::profile_obj_type
3129         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3130         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3131         __ cmpd(CCR1, R0, klass);
3132         // Klass seen before, nothing to do (regardless of unknown bit).
3133         //beq(CCR1, do_nothing);
3134 
3135         __ andi_(R0, klass, TypeEntries::type_unknown);
3136         // Already unknown. Nothing to do anymore.
3137         //bne(CCR0, do_nothing);
3138         __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3139         __ beq(CCR0, Lnext);
3140 
3141         if (TypeEntries::is_type_none(current_klass)) {
3142           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3143           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3144           __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3145         }
3146 
3147       } else {
3148         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3149                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3150 
3151         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3152         __ andi_(R0, tmp, TypeEntries::type_unknown);
3153         // Already unknown. Nothing to do anymore.
3154         __ bne(CCR0, Lnext);
3155       }
3156 
3157       // Different than before. Cannot keep accurate profile.
3158       __ ori(R0, tmp, TypeEntries::type_unknown);
3159     } else {
3160       // There's a single possible klass at this profile point
3161       assert(exact_klass != NULL, "should be");
3162       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3163 
3164       if (TypeEntries::is_type_none(current_klass)) {
3165         klass_reg_used = true;
3166         metadata2reg(exact_klass->constant_encoding(), klass);
3167 
3168         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3169         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3170         __ cmpd(CCR1, R0, klass);
3171         // Klass seen before, nothing to do (regardless of unknown bit).
3172         __ beq(CCR1, Lnext);
3173 #ifdef ASSERT
3174         {
3175           Label ok;
3176           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3177           __ beq(CCR0, ok); // First time here.
3178 
3179           __ stop("unexpected profiling mismatch", 0x7865);
3180           __ bind(ok);
3181         }
3182 #endif
3183         // First time here. Set profile type.
3184         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3185       } else {
3186         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3187                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3188 
3189         // Already unknown. Nothing to do anymore.
3190         __ andi_(R0, tmp, TypeEntries::type_unknown);
3191         __ bne(CCR0, Lnext);
3192 
3193         // Different than before. Cannot keep accurate profile.
3194         __ ori(R0, tmp, TypeEntries::type_unknown);
3195       }
3196     }
3197 
3198     __ bind(Ldo_update);
3199     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3200 
3201     __ bind(Lnext);
3202     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3203   }
3204   __ bind(Ldone);
3205 }
3206 
3207 
3208 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3209   assert(op->crc()->is_single_cpu(), "crc must be register");
3210   assert(op->val()->is_single_cpu(), "byte value must be register");
3211   assert(op->result_opr()->is_single_cpu(), "result must be register");
3212   Register crc = op->crc()->as_register();
3213   Register val = op->val()->as_register();
3214   Register res = op->result_opr()->as_register();
3215 
3216   assert_different_registers(val, crc, res);
3217 
3218   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3219   __ kernel_crc32_singleByteReg(crc, val, res, true);
3220   __ mr(res, crc);
3221 }
3222 
3223 #undef __
--- EOF ---