1 /*
   2  * Copyright (c) 2016, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2016, 2017, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/collectedHeap.hpp"
  36 #include "gc/shared/barrierSet.hpp"
  37 #include "gc/shared/cardTableBarrierSet.hpp"
  38 #include "nativeInst_s390.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.inline.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_s390.inline.hpp"
  44 
  45 #define __ _masm->
  46 
  47 #ifndef PRODUCT
  48 #undef __
  49 #define __ (Verbose ? (_masm->block_comment(FILE_AND_LINE),_masm) : _masm)->
  50 #endif
  51 
  52 //------------------------------------------------------------
  53 
  54 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  55   // Not used on ZARCH_64
  56   ShouldNotCallThis();
  57   return false;
  58 }
  59 
  60 LIR_Opr LIR_Assembler::receiverOpr() {
  61   return FrameMap::Z_R2_oop_opr;
  62 }
  63 
  64 LIR_Opr LIR_Assembler::osrBufferPointer() {
  65   return FrameMap::Z_R2_opr;
  66 }
  67 
  68 int LIR_Assembler::initial_frame_size_in_bytes() const {
  69   return in_bytes(frame_map()->framesize_in_bytes());
  70 }
  71 
  72 // Inline cache check: done before the frame is built.
  73 // The inline cached class is in Z_inline_cache(Z_R9).
  74 // We fetch the class of the receiver and compare it with the cached class.
  75 // If they do not match we jump to the slow case.
  76 int LIR_Assembler::check_icache() {
  77   Register receiver = receiverOpr()->as_register();
  78   int offset = __ offset();
  79   __ inline_cache_check(receiver, Z_inline_cache);
  80   return offset;
  81 }
  82 
  83 void LIR_Assembler::clinit_barrier(ciMethod* method) {
  84   ShouldNotReachHere(); // not implemented
  85 }
  86 
  87 void LIR_Assembler::osr_entry() {
  88   // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp):
  89   //
  90   //   1. Create a new compiled activation.
  91   //   2. Initialize local variables in the compiled activation. The expression stack must be empty
  92   //      at the osr_bci; it is not initialized.
  93   //   3. Jump to the continuation address in compiled code to resume execution.
  94 
  95   // OSR entry point
  96   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
  97   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
  98   ValueStack* entry_state = osr_entry->end()->state();
  99   int number_of_locks = entry_state->locks_size();
 100 
 101   // Create a frame for the compiled activation.
 102   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 103 
 104   // OSR buffer is
 105   //
 106   // locals[nlocals-1..0]
 107   // monitors[number_of_locks-1..0]
 108   //
 109   // Locals is a direct copy of the interpreter frame so in the osr buffer
 110   // the first slot in the local array is the last local from the interpreter
 111   // and the last slot is local[0] (receiver) from the interpreter
 112   //
 113   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 114   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 115   // in the interpreter frame (the method lock if a sync method)
 116 
 117   // Initialize monitors in the compiled activation.
 118   //   I0: pointer to osr buffer
 119   //
 120   // All other registers are dead at this point and the locals will be
 121   // copied into place by code emitted in the IR.
 122 
 123   Register OSR_buf = osrBufferPointer()->as_register();
 124   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 125     int monitor_offset = BytesPerWord * method()->max_locals() +
 126       (2 * BytesPerWord) * (number_of_locks - 1);
 127     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 128     // the OSR buffer using 2 word entries: first the lock and then
 129     // the oop.
 130     for (int i = 0; i < number_of_locks; i++) {
 131       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 132       // Verify the interpreter's monitor has a non-null object.
 133       __ asm_assert_mem8_isnot_zero(slot_offset + 1*BytesPerWord, OSR_buf, "locked object is NULL", __LINE__);
 134       // Copy the lock field into the compiled activation.
 135       __ z_lg(Z_R1_scratch, slot_offset + 0, OSR_buf);
 136       __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_lock(i));
 137       __ z_lg(Z_R1_scratch, slot_offset + 1*BytesPerWord, OSR_buf);
 138       __ z_stg(Z_R1_scratch, frame_map()->address_for_monitor_object(i));
 139     }
 140   }
 141 }
 142 
 143 // --------------------------------------------------------------------------------------------
 144 
 145 address LIR_Assembler::emit_call_c(address a) {
 146   __ align_call_far_patchable(__ pc());
 147   address call_addr = __ call_c_opt(a);
 148   if (call_addr == NULL) {
 149     bailout("const section overflow");
 150   }
 151   return call_addr;
 152 }
 153 
 154 int LIR_Assembler::emit_exception_handler() {
 155   // If the last instruction is a call (typically to do a throw which
 156   // is coming at the end after block reordering) the return address
 157   // must still point into the code area in order to avoid assertion
 158   // failures when searching for the corresponding bci. => Add a nop.
 159   // (was bug 5/14/1999 - gri)
 160   __ nop();
 161 
 162   // Generate code for exception handler.
 163   address handler_base = __ start_a_stub(exception_handler_size());
 164   if (handler_base == NULL) {
 165     // Not enough space left for the handler.
 166     bailout("exception handler overflow");
 167     return -1;
 168   }
 169 
 170   int offset = code_offset();
 171 
 172   address a = Runtime1::entry_for (Runtime1::handle_exception_from_callee_id);
 173   address call_addr = emit_call_c(a);
 174   CHECK_BAILOUT_(-1);
 175   __ should_not_reach_here();
 176   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 177   __ end_a_stub();
 178 
 179   return offset;
 180 }
 181 
 182 // Emit the code to remove the frame from the stack in the exception
 183 // unwind path.
 184 int LIR_Assembler::emit_unwind_handler() {
 185 #ifndef PRODUCT
 186   if (CommentedAssembly) {
 187     _masm->block_comment("Unwind handler");
 188   }
 189 #endif
 190 
 191   int offset = code_offset();
 192   Register exception_oop_callee_saved = Z_R10; // Z_R10 is callee-saved.
 193   Register Rtmp1                      = Z_R11;
 194   Register Rtmp2                      = Z_R12;
 195 
 196   // Fetch the exception from TLS and clear out exception related thread state.
 197   Address exc_oop_addr = Address(Z_thread, JavaThread::exception_oop_offset());
 198   Address exc_pc_addr  = Address(Z_thread, JavaThread::exception_pc_offset());
 199   __ z_lg(Z_EXC_OOP, exc_oop_addr);
 200   __ clear_mem(exc_oop_addr, sizeof(oop));
 201   __ clear_mem(exc_pc_addr, sizeof(intptr_t));
 202 
 203   __ bind(_unwind_handler_entry);
 204   __ verify_not_null_oop(Z_EXC_OOP);
 205   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 206     __ lgr_if_needed(exception_oop_callee_saved, Z_EXC_OOP); // Preserve the exception.
 207   }
 208 
 209   // Preform needed unlocking.
 210   MonitorExitStub* stub = NULL;
 211   if (method()->is_synchronized()) {
 212     // Runtime1::monitorexit_id expects lock address in Z_R1_scratch.
 213     LIR_Opr lock = FrameMap::as_opr(Z_R1_scratch);
 214     monitor_address(0, lock);
 215     stub = new MonitorExitStub(lock, true, 0);
 216     __ unlock_object(Rtmp1, Rtmp2, lock->as_register(), *stub->entry());
 217     __ bind(*stub->continuation());
 218   }
 219 
 220   if (compilation()->env()->dtrace_method_probes()) {
 221     ShouldNotReachHere(); // Not supported.
 222 #if 0
 223     __ mov(rdi, r15_thread);
 224     __ mov_metadata(rsi, method()->constant_encoding());
 225     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 226 #endif
 227   }
 228 
 229   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 230     __ lgr_if_needed(Z_EXC_OOP, exception_oop_callee_saved);  // Restore the exception.
 231   }
 232 
 233   // Remove the activation and dispatch to the unwind handler.
 234   __ pop_frame();
 235   __ z_lg(Z_EXC_PC, _z_abi16(return_pc), Z_SP);
 236 
 237   // Z_EXC_OOP: exception oop
 238   // Z_EXC_PC: exception pc
 239 
 240   // Dispatch to the unwind logic.
 241   __ load_const_optimized(Z_R5, Runtime1::entry_for (Runtime1::unwind_exception_id));
 242   __ z_br(Z_R5);
 243 
 244   // Emit the slow path assembly.
 245   if (stub != NULL) {
 246     stub->emit_code(this);
 247   }
 248 
 249   return offset;
 250 }
 251 
 252 int LIR_Assembler::emit_deopt_handler() {
 253   // If the last instruction is a call (typically to do a throw which
 254   // is coming at the end after block reordering) the return address
 255   // must still point into the code area in order to avoid assertion
 256   // failures when searching for the corresponding bci. => Add a nop.
 257   // (was bug 5/14/1999 - gri)
 258   __ nop();
 259 
 260   // Generate code for exception handler.
 261   address handler_base = __ start_a_stub(deopt_handler_size());
 262   if (handler_base == NULL) {
 263     // Not enough space left for the handler.
 264     bailout("deopt handler overflow");
 265     return -1;
 266   }  int offset = code_offset();
 267   // Size must be constant (see HandlerImpl::emit_deopt_handler).
 268   __ load_const(Z_R1_scratch, SharedRuntime::deopt_blob()->unpack());
 269   __ call(Z_R1_scratch);
 270   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 271   __ end_a_stub();
 272 
 273   return offset;
 274 }
 275 
 276 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 277   if (o == NULL) {
 278     __ clear_reg(reg, true/*64bit*/, false/*set cc*/); // Must not kill cc set by cmove.
 279   } else {
 280     AddressLiteral a = __ allocate_oop_address(o);
 281     bool success = __ load_oop_from_toc(reg, a, reg);
 282     if (!success) {
 283       bailout("const section overflow");
 284     }
 285   }
 286 }
 287 
 288 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 289   // Allocate a new index in table to hold the object once it's been patched.
 290   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 291   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 292 
 293   AddressLiteral addrlit((intptr_t)0, oop_Relocation::spec(oop_index));
 294   assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
 295   // The NULL will be dynamically patched later so the sequence to
 296   // load the address literal must not be optimized.
 297   __ load_const(reg, addrlit);
 298 
 299   patching_epilog(patch, lir_patch_normal, reg, info);
 300 }
 301 
 302 void LIR_Assembler::metadata2reg(Metadata* md, Register reg) {
 303   bool success = __ set_metadata_constant(md, reg);
 304   if (!success) {
 305     bailout("const section overflow");
 306     return;
 307   }
 308 }
 309 
 310 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 311   // Allocate a new index in table to hold the klass once it's been patched.
 312   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 313   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 314   AddressLiteral addrlit((intptr_t)0, metadata_Relocation::spec(index));
 315   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 316   // The NULL will be dynamically patched later so the sequence to
 317   // load the address literal must not be optimized.
 318   __ load_const(reg, addrlit);
 319 
 320   patching_epilog(patch, lir_patch_normal, reg, info);
 321 }
 322 
 323 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 324   switch (op->code()) {
 325     case lir_idiv:
 326     case lir_irem:
 327       arithmetic_idiv(op->code(),
 328                       op->in_opr1(),
 329                       op->in_opr2(),
 330                       op->in_opr3(),
 331                       op->result_opr(),
 332                       op->info());
 333       break;
 334     case lir_fmad: {
 335       const FloatRegister opr1 = op->in_opr1()->as_double_reg(),
 336                           opr2 = op->in_opr2()->as_double_reg(),
 337                           opr3 = op->in_opr3()->as_double_reg(),
 338                           res  = op->result_opr()->as_double_reg();
 339       __ z_madbr(opr3, opr1, opr2);
 340       if (res != opr3) { __ z_ldr(res, opr3); }
 341     } break;
 342     case lir_fmaf: {
 343       const FloatRegister opr1 = op->in_opr1()->as_float_reg(),
 344                           opr2 = op->in_opr2()->as_float_reg(),
 345                           opr3 = op->in_opr3()->as_float_reg(),
 346                           res  = op->result_opr()->as_float_reg();
 347       __ z_maebr(opr3, opr1, opr2);
 348       if (res != opr3) { __ z_ler(res, opr3); }
 349     } break;
 350     default: ShouldNotReachHere(); break;
 351   }
 352 }
 353 
 354 
 355 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 356 #ifdef ASSERT
 357   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 358   if (op->block() != NULL)  { _branch_target_blocks.append(op->block()); }
 359   if (op->ublock() != NULL) { _branch_target_blocks.append(op->ublock()); }
 360 #endif
 361 
 362   if (op->cond() == lir_cond_always) {
 363     if (op->info() != NULL) { add_debug_info_for_branch(op->info()); }
 364     __ branch_optimized(Assembler::bcondAlways, *(op->label()));
 365   } else {
 366     Assembler::branch_condition acond = Assembler::bcondZero;
 367     if (op->code() == lir_cond_float_branch) {
 368       assert(op->ublock() != NULL, "must have unordered successor");
 369       __ branch_optimized(Assembler::bcondNotOrdered, *(op->ublock()->label()));
 370     }
 371     switch (op->cond()) {
 372       case lir_cond_equal:        acond = Assembler::bcondEqual;     break;
 373       case lir_cond_notEqual:     acond = Assembler::bcondNotEqual;  break;
 374       case lir_cond_less:         acond = Assembler::bcondLow;       break;
 375       case lir_cond_lessEqual:    acond = Assembler::bcondNotHigh;   break;
 376       case lir_cond_greaterEqual: acond = Assembler::bcondNotLow;    break;
 377       case lir_cond_greater:      acond = Assembler::bcondHigh;      break;
 378       case lir_cond_belowEqual:   acond = Assembler::bcondNotHigh;   break;
 379       case lir_cond_aboveEqual:   acond = Assembler::bcondNotLow;    break;
 380       default:                         ShouldNotReachHere();
 381     }
 382     __ branch_optimized(acond,*(op->label()));
 383   }
 384 }
 385 
 386 
 387 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 388   LIR_Opr src  = op->in_opr();
 389   LIR_Opr dest = op->result_opr();
 390 
 391   switch (op->bytecode()) {
 392     case Bytecodes::_i2l:
 393       __ move_reg_if_needed(dest->as_register_lo(), T_LONG, src->as_register(), T_INT);
 394       break;
 395 
 396     case Bytecodes::_l2i:
 397       __ move_reg_if_needed(dest->as_register(), T_INT, src->as_register_lo(), T_LONG);
 398       break;
 399 
 400     case Bytecodes::_i2b:
 401       __ move_reg_if_needed(dest->as_register(), T_BYTE, src->as_register(), T_INT);
 402       break;
 403 
 404     case Bytecodes::_i2c:
 405       __ move_reg_if_needed(dest->as_register(), T_CHAR, src->as_register(), T_INT);
 406       break;
 407 
 408     case Bytecodes::_i2s:
 409       __ move_reg_if_needed(dest->as_register(), T_SHORT, src->as_register(), T_INT);
 410       break;
 411 
 412     case Bytecodes::_f2d:
 413       assert(dest->is_double_fpu(), "check");
 414       __ move_freg_if_needed(dest->as_double_reg(), T_DOUBLE, src->as_float_reg(), T_FLOAT);
 415       break;
 416 
 417     case Bytecodes::_d2f:
 418       assert(dest->is_single_fpu(), "check");
 419       __ move_freg_if_needed(dest->as_float_reg(), T_FLOAT, src->as_double_reg(), T_DOUBLE);
 420       break;
 421 
 422     case Bytecodes::_i2f:
 423       __ z_cefbr(dest->as_float_reg(), src->as_register());
 424       break;
 425 
 426     case Bytecodes::_i2d:
 427       __ z_cdfbr(dest->as_double_reg(), src->as_register());
 428       break;
 429 
 430     case Bytecodes::_l2f:
 431       __ z_cegbr(dest->as_float_reg(), src->as_register_lo());
 432       break;
 433     case Bytecodes::_l2d:
 434       __ z_cdgbr(dest->as_double_reg(), src->as_register_lo());
 435       break;
 436 
 437     case Bytecodes::_f2i:
 438     case Bytecodes::_f2l: {
 439       Label done;
 440       FloatRegister Rsrc = src->as_float_reg();
 441       Register Rdst = (op->bytecode() == Bytecodes::_f2i ? dest->as_register() : dest->as_register_lo());
 442       __ clear_reg(Rdst, true, false);
 443       __ z_cebr(Rsrc, Rsrc);
 444       __ z_brno(done); // NaN -> 0
 445       if (op->bytecode() == Bytecodes::_f2i) {
 446         __ z_cfebr(Rdst, Rsrc, Assembler::to_zero);
 447       } else { // op->bytecode() == Bytecodes::_f2l
 448         __ z_cgebr(Rdst, Rsrc, Assembler::to_zero);
 449       }
 450       __ bind(done);
 451     }
 452     break;
 453 
 454     case Bytecodes::_d2i:
 455     case Bytecodes::_d2l: {
 456       Label done;
 457       FloatRegister Rsrc = src->as_double_reg();
 458       Register Rdst = (op->bytecode() == Bytecodes::_d2i ? dest->as_register() : dest->as_register_lo());
 459       __ clear_reg(Rdst, true, false);  // Don't set CC.
 460       __ z_cdbr(Rsrc, Rsrc);
 461       __ z_brno(done); // NaN -> 0
 462       if (op->bytecode() == Bytecodes::_d2i) {
 463         __ z_cfdbr(Rdst, Rsrc, Assembler::to_zero);
 464       } else { // Bytecodes::_d2l
 465         __ z_cgdbr(Rdst, Rsrc, Assembler::to_zero);
 466       }
 467       __ bind(done);
 468     }
 469     break;
 470 
 471     default: ShouldNotReachHere();
 472   }
 473 }
 474 
 475 void LIR_Assembler::align_call(LIR_Code code) {
 476   // End of call instruction must be 4 byte aligned.
 477   int offset = __ offset();
 478   switch (code) {
 479     case lir_icvirtual_call:
 480       offset += MacroAssembler::load_const_from_toc_size();
 481       // no break
 482     case lir_static_call:
 483     case lir_optvirtual_call:
 484     case lir_dynamic_call:
 485       offset += NativeCall::call_far_pcrelative_displacement_offset;
 486       break;
 487     case lir_virtual_call:   // currently, sparc-specific for niagara
 488     default: ShouldNotReachHere();
 489   }
 490   if ((offset & (NativeCall::call_far_pcrelative_displacement_alignment-1)) != 0) {
 491     __ nop();
 492   }
 493 }
 494 
 495 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 496   assert((__ offset() + NativeCall::call_far_pcrelative_displacement_offset) % NativeCall::call_far_pcrelative_displacement_alignment == 0,
 497          "must be aligned (offset=%d)", __ offset());
 498   assert(rtype == relocInfo::none ||
 499          rtype == relocInfo::opt_virtual_call_type ||
 500          rtype == relocInfo::static_call_type, "unexpected rtype");
 501   // Prepend each BRASL with a nop.
 502   __ relocate(rtype);
 503   __ z_nop();
 504   __ z_brasl(Z_R14, op->addr());
 505   add_call_info(code_offset(), op->info());
 506 }
 507 
 508 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 509   address virtual_call_oop_addr = NULL;
 510   AddressLiteral empty_ic((address) Universe::non_oop_word());
 511   virtual_call_oop_addr = __ pc();
 512   bool success = __ load_const_from_toc(Z_inline_cache, empty_ic);
 513   if (!success) {
 514     bailout("const section overflow");
 515     return;
 516   }
 517 
 518   // CALL to fixup routine. Fixup routine uses ScopeDesc info
 519   // to determine who we intended to call.
 520   __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
 521   call(op, relocInfo::none);
 522 }
 523 
 524 // not supported
 525 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 526   ShouldNotReachHere();
 527 }
 528 
 529 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 530   if (from_reg != to_reg) __ z_lgr(to_reg, from_reg);
 531 }
 532 
 533 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 534   assert(src->is_constant(), "should not call otherwise");
 535   assert(dest->is_stack(), "should not call otherwise");
 536   LIR_Const* c = src->as_constant_ptr();
 537 
 538   unsigned int lmem = 0;
 539   unsigned int lcon = 0;
 540   int64_t cbits = 0;
 541   Address dest_addr;
 542   switch (c->type()) {
 543     case T_INT:  // fall through
 544     case T_FLOAT:
 545       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 546       lmem = 4; lcon = 4; cbits = c->as_jint_bits();
 547       break;
 548 
 549     case T_ADDRESS:
 550       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 551       lmem = 8; lcon = 4; cbits = c->as_jint_bits();
 552       break;
 553 
 554     case T_OBJECT:
 555       dest_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 556       if (c->as_jobject() == NULL) {
 557         __ store_const(dest_addr, (int64_t)NULL_WORD, 8, 8);
 558       } else {
 559         jobject2reg(c->as_jobject(), Z_R1_scratch);
 560         __ reg2mem_opt(Z_R1_scratch, dest_addr, true);
 561       }
 562       return;
 563 
 564     case T_LONG:  // fall through
 565     case T_DOUBLE:
 566       dest_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 567       lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
 568       break;
 569 
 570     default:
 571       ShouldNotReachHere();
 572   }
 573 
 574   __ store_const(dest_addr, cbits, lmem, lcon);
 575 }
 576 
 577 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 578   assert(src->is_constant(), "should not call otherwise");
 579   assert(dest->is_address(), "should not call otherwise");
 580 
 581   LIR_Const* c = src->as_constant_ptr();
 582   Address addr = as_Address(dest->as_address_ptr());
 583 
 584   int store_offset = -1;
 585 
 586   if (dest->as_address_ptr()->index()->is_valid()) {
 587     switch (type) {
 588       case T_INT:    // fall through
 589       case T_FLOAT:
 590         __ load_const_optimized(Z_R0_scratch, c->as_jint_bits());
 591         store_offset = __ offset();
 592         if (Immediate::is_uimm12(addr.disp())) {
 593           __ z_st(Z_R0_scratch, addr);
 594         } else {
 595           __ z_sty(Z_R0_scratch, addr);
 596         }
 597         break;
 598 
 599       case T_ADDRESS:
 600         __ load_const_optimized(Z_R1_scratch, c->as_jint_bits());
 601         store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 602         break;
 603 
 604       case T_OBJECT:  // fall through
 605       case T_ARRAY:
 606         if (c->as_jobject() == NULL) {
 607           if (UseCompressedOops && !wide) {
 608             __ clear_reg(Z_R1_scratch, false);
 609             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 610           } else {
 611             __ clear_reg(Z_R1_scratch, true);
 612             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 613           }
 614         } else {
 615           jobject2reg(c->as_jobject(), Z_R1_scratch);
 616           if (UseCompressedOops && !wide) {
 617             __ encode_heap_oop(Z_R1_scratch);
 618             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 619           } else {
 620             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 621           }
 622         }
 623         assert(store_offset >= 0, "check");
 624         break;
 625 
 626       case T_LONG:    // fall through
 627       case T_DOUBLE:
 628         __ load_const_optimized(Z_R1_scratch, (int64_t)(c->as_jlong_bits()));
 629         store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 630         break;
 631 
 632       case T_BOOLEAN: // fall through
 633       case T_BYTE:
 634         __ load_const_optimized(Z_R0_scratch, (int8_t)(c->as_jint()));
 635         store_offset = __ offset();
 636         if (Immediate::is_uimm12(addr.disp())) {
 637           __ z_stc(Z_R0_scratch, addr);
 638         } else {
 639           __ z_stcy(Z_R0_scratch, addr);
 640         }
 641         break;
 642 
 643       case T_CHAR:    // fall through
 644       case T_SHORT:
 645         __ load_const_optimized(Z_R0_scratch, (int16_t)(c->as_jint()));
 646         store_offset = __ offset();
 647         if (Immediate::is_uimm12(addr.disp())) {
 648           __ z_sth(Z_R0_scratch, addr);
 649         } else {
 650           __ z_sthy(Z_R0_scratch, addr);
 651         }
 652         break;
 653 
 654       default:
 655         ShouldNotReachHere();
 656     }
 657 
 658   } else { // no index
 659 
 660     unsigned int lmem = 0;
 661     unsigned int lcon = 0;
 662     int64_t cbits = 0;
 663 
 664     switch (type) {
 665       case T_INT:    // fall through
 666       case T_FLOAT:
 667         lmem = 4; lcon = 4; cbits = c->as_jint_bits();
 668         break;
 669 
 670       case T_ADDRESS:
 671         lmem = 8; lcon = 4; cbits = c->as_jint_bits();
 672         break;
 673 
 674       case T_OBJECT:  // fall through
 675       case T_ARRAY:
 676         if (c->as_jobject() == NULL) {
 677           if (UseCompressedOops && !wide) {
 678             store_offset = __ store_const(addr, (int32_t)NULL_WORD, 4, 4);
 679           } else {
 680             store_offset = __ store_const(addr, (int64_t)NULL_WORD, 8, 8);
 681           }
 682         } else {
 683           jobject2reg(c->as_jobject(), Z_R1_scratch);
 684           if (UseCompressedOops && !wide) {
 685             __ encode_heap_oop(Z_R1_scratch);
 686             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, false);
 687           } else {
 688             store_offset = __ reg2mem_opt(Z_R1_scratch, addr, true);
 689           }
 690         }
 691         assert(store_offset >= 0, "check");
 692         break;
 693 
 694       case T_LONG:    // fall through
 695       case T_DOUBLE:
 696         lmem = 8; lcon = 8; cbits = (int64_t)(c->as_jlong_bits());
 697         break;
 698 
 699       case T_BOOLEAN: // fall through
 700       case T_BYTE:
 701         lmem = 1; lcon = 1; cbits = (int8_t)(c->as_jint());
 702         break;
 703 
 704       case T_CHAR:    // fall through
 705       case T_SHORT:
 706         lmem = 2; lcon = 2; cbits = (int16_t)(c->as_jint());
 707         break;
 708 
 709       default:
 710         ShouldNotReachHere();
 711     }
 712 
 713     if (store_offset == -1) {
 714       store_offset = __ store_const(addr, cbits, lmem, lcon);
 715       assert(store_offset >= 0, "check");
 716     }
 717   }
 718 
 719   if (info != NULL) {
 720     add_debug_info_for_null_check(store_offset, info);
 721   }
 722 }
 723 
 724 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 725   assert(src->is_constant(), "should not call otherwise");
 726   assert(dest->is_register(), "should not call otherwise");
 727   LIR_Const* c = src->as_constant_ptr();
 728 
 729   switch (c->type()) {
 730     case T_INT: {
 731       assert(patch_code == lir_patch_none, "no patching handled here");
 732       __ load_const_optimized(dest->as_register(), c->as_jint());
 733       break;
 734     }
 735 
 736     case T_ADDRESS: {
 737       assert(patch_code == lir_patch_none, "no patching handled here");
 738       __ load_const_optimized(dest->as_register(), c->as_jint());
 739       break;
 740     }
 741 
 742     case T_LONG: {
 743       assert(patch_code == lir_patch_none, "no patching handled here");
 744       __ load_const_optimized(dest->as_register_lo(), (intptr_t)c->as_jlong());
 745       break;
 746     }
 747 
 748     case T_OBJECT: {
 749       if (patch_code != lir_patch_none) {
 750         jobject2reg_with_patching(dest->as_register(), info);
 751       } else {
 752         jobject2reg(c->as_jobject(), dest->as_register());
 753       }
 754       break;
 755     }
 756 
 757     case T_METADATA: {
 758       if (patch_code != lir_patch_none) {
 759         klass2reg_with_patching(dest->as_register(), info);
 760       } else {
 761         metadata2reg(c->as_metadata(), dest->as_register());
 762       }
 763       break;
 764     }
 765 
 766     case T_FLOAT: {
 767       Register toc_reg = Z_R1_scratch;
 768       __ load_toc(toc_reg);
 769       address const_addr = __ float_constant(c->as_jfloat());
 770       if (const_addr == NULL) {
 771         bailout("const section overflow");
 772         break;
 773       }
 774       int displ = const_addr - _masm->code()->consts()->start();
 775       if (dest->is_single_fpu()) {
 776         __ z_ley(dest->as_float_reg(), displ, toc_reg);
 777       } else {
 778         assert(dest->is_single_cpu(), "Must be a cpu register.");
 779         __ z_ly(dest->as_register(), displ, toc_reg);
 780       }
 781     }
 782     break;
 783 
 784     case T_DOUBLE: {
 785       Register toc_reg = Z_R1_scratch;
 786       __ load_toc(toc_reg);
 787       address const_addr = __ double_constant(c->as_jdouble());
 788       if (const_addr == NULL) {
 789         bailout("const section overflow");
 790         break;
 791       }
 792       int displ = const_addr - _masm->code()->consts()->start();
 793       if (dest->is_double_fpu()) {
 794         __ z_ldy(dest->as_double_reg(), displ, toc_reg);
 795       } else {
 796         assert(dest->is_double_cpu(), "Must be a long register.");
 797         __ z_lg(dest->as_register_lo(), displ, toc_reg);
 798       }
 799     }
 800     break;
 801 
 802     default:
 803       ShouldNotReachHere();
 804   }
 805 }
 806 
 807 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 808   if (addr->base()->is_illegal()) {
 809     Unimplemented();
 810   }
 811 
 812   Register base = addr->base()->as_pointer_register();
 813 
 814   if (addr->index()->is_illegal()) {
 815     return Address(base, addr->disp());
 816   } else if (addr->index()->is_cpu_register()) {
 817     Register index = addr->index()->as_pointer_register();
 818     return Address(base, index, addr->disp());
 819   } else if (addr->index()->is_constant()) {
 820     intptr_t addr_offset = addr->index()->as_constant_ptr()->as_jint() + addr->disp();
 821     return Address(base, addr_offset);
 822   } else {
 823     ShouldNotReachHere();
 824     return Address();
 825   }
 826 }
 827 
 828 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 829   switch (type) {
 830     case T_INT:
 831     case T_FLOAT: {
 832       Register tmp = Z_R1_scratch;
 833       Address from = frame_map()->address_for_slot(src->single_stack_ix());
 834       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
 835       __ mem2reg_opt(tmp, from, false);
 836       __ reg2mem_opt(tmp, to, false);
 837       break;
 838     }
 839     case T_ADDRESS:
 840     case T_OBJECT: {
 841       Register tmp = Z_R1_scratch;
 842       Address from = frame_map()->address_for_slot(src->single_stack_ix());
 843       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
 844       __ mem2reg_opt(tmp, from, true);
 845       __ reg2mem_opt(tmp, to, true);
 846       break;
 847     }
 848     case T_LONG:
 849     case T_DOUBLE: {
 850       Register tmp = Z_R1_scratch;
 851       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
 852       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
 853       __ mem2reg_opt(tmp, from, true);
 854       __ reg2mem_opt(tmp, to, true);
 855       break;
 856     }
 857 
 858     default:
 859       ShouldNotReachHere();
 860   }
 861 }
 862 
 863 // 4-byte accesses only! Don't use it to access 8 bytes!
 864 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 865   ShouldNotCallThis();
 866   return 0; // unused
 867 }
 868 
 869 // 4-byte accesses only! Don't use it to access 8 bytes!
 870 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 871   ShouldNotCallThis();
 872   return 0; // unused
 873 }
 874 
 875 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code,
 876                             CodeEmitInfo* info, bool wide, bool unaligned) {
 877 
 878   assert(type != T_METADATA, "load of metadata ptr not supported");
 879   LIR_Address* addr = src_opr->as_address_ptr();
 880   LIR_Opr to_reg = dest;
 881 
 882   Register src = addr->base()->as_pointer_register();
 883   Register disp_reg = Z_R0;
 884   int disp_value = addr->disp();
 885   bool needs_patching = (patch_code != lir_patch_none);
 886 
 887   if (addr->base()->type() == T_OBJECT) {
 888     __ verify_oop(src);
 889   }
 890 
 891   PatchingStub* patch = NULL;
 892   if (needs_patching) {
 893     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
 894     assert(!to_reg->is_double_cpu() ||
 895            patch_code == lir_patch_none ||
 896            patch_code == lir_patch_normal, "patching doesn't match register");
 897   }
 898 
 899   if (addr->index()->is_illegal()) {
 900     if (!Immediate::is_simm20(disp_value)) {
 901       if (needs_patching) {
 902         __ load_const(Z_R1_scratch, (intptr_t)0);
 903       } else {
 904         __ load_const_optimized(Z_R1_scratch, disp_value);
 905       }
 906       disp_reg = Z_R1_scratch;
 907       disp_value = 0;
 908     }
 909   } else {
 910     if (!Immediate::is_simm20(disp_value)) {
 911       __ load_const_optimized(Z_R1_scratch, disp_value);
 912       __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
 913       disp_reg = Z_R1_scratch;
 914       disp_value = 0;
 915     }
 916     disp_reg = addr->index()->as_pointer_register();
 917   }
 918 
 919   // Remember the offset of the load. The patching_epilog must be done
 920   // before the call to add_debug_info, otherwise the PcDescs don't get
 921   // entered in increasing order.
 922   int offset = code_offset();
 923 
 924   assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
 925 
 926   bool short_disp = Immediate::is_uimm12(disp_value);
 927 
 928   switch (type) {
 929     case T_BOOLEAN: // fall through
 930     case T_BYTE  :  __ z_lb(dest->as_register(),   disp_value, disp_reg, src); break;
 931     case T_CHAR  :  __ z_llgh(dest->as_register(), disp_value, disp_reg, src); break;
 932     case T_SHORT :
 933       if (short_disp) {
 934                     __ z_lh(dest->as_register(),   disp_value, disp_reg, src);
 935       } else {
 936                     __ z_lhy(dest->as_register(),  disp_value, disp_reg, src);
 937       }
 938       break;
 939     case T_INT   :
 940       if (short_disp) {
 941                     __ z_l(dest->as_register(),    disp_value, disp_reg, src);
 942       } else {
 943                     __ z_ly(dest->as_register(),   disp_value, disp_reg, src);
 944       }
 945       break;
 946     case T_ADDRESS:
 947       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 948         __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
 949         __ decode_klass_not_null(dest->as_register());
 950       } else {
 951         __ z_lg(dest->as_register(), disp_value, disp_reg, src);
 952       }
 953       break;
 954     case T_ARRAY : // fall through
 955     case T_OBJECT:
 956     {
 957       if (UseCompressedOops && !wide) {
 958         __ z_llgf(dest->as_register(), disp_value, disp_reg, src);
 959         __ oop_decoder(dest->as_register(), dest->as_register(), true);
 960       } else {
 961         __ z_lg(dest->as_register(), disp_value, disp_reg, src);
 962       }
 963       break;
 964     }
 965     case T_FLOAT:
 966       if (short_disp) {
 967                     __ z_le(dest->as_float_reg(),  disp_value, disp_reg, src);
 968       } else {
 969                     __ z_ley(dest->as_float_reg(), disp_value, disp_reg, src);
 970       }
 971       break;
 972     case T_DOUBLE:
 973       if (short_disp) {
 974                     __ z_ld(dest->as_double_reg(),  disp_value, disp_reg, src);
 975       } else {
 976                     __ z_ldy(dest->as_double_reg(), disp_value, disp_reg, src);
 977       }
 978       break;
 979     case T_LONG  :  __ z_lg(dest->as_register_lo(), disp_value, disp_reg, src); break;
 980     default      : ShouldNotReachHere();
 981   }
 982   if (type == T_ARRAY || type == T_OBJECT) {
 983     __ verify_oop(dest->as_register());
 984   }
 985 
 986   if (patch != NULL) {
 987     patching_epilog(patch, patch_code, src, info);
 988   }
 989   if (info != NULL) add_debug_info_for_null_check(offset, info);
 990 }
 991 
 992 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 993   assert(src->is_stack(), "should not call otherwise");
 994   assert(dest->is_register(), "should not call otherwise");
 995 
 996   if (dest->is_single_cpu()) {
 997     if (type == T_ARRAY || type == T_OBJECT) {
 998       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
 999       __ verify_oop(dest->as_register());
1000     } else if (type == T_METADATA) {
1001       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), true);
1002     } else {
1003       __ mem2reg_opt(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()), false);
1004     }
1005   } else if (dest->is_double_cpu()) {
1006     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix());
1007     __ mem2reg_opt(dest->as_register_lo(), src_addr_LO, true);
1008   } else if (dest->is_single_fpu()) {
1009     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1010     __ mem2freg_opt(dest->as_float_reg(), src_addr, false);
1011   } else if (dest->is_double_fpu()) {
1012     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1013     __ mem2freg_opt(dest->as_double_reg(), src_addr, true);
1014   } else {
1015     ShouldNotReachHere();
1016   }
1017 }
1018 
1019 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1020   assert(src->is_register(), "should not call otherwise");
1021   assert(dest->is_stack(), "should not call otherwise");
1022 
1023   if (src->is_single_cpu()) {
1024     const Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
1025     if (type == T_OBJECT || type == T_ARRAY) {
1026       __ verify_oop(src->as_register());
1027       __ reg2mem_opt(src->as_register(), dst, true);
1028     } else if (type == T_METADATA) {
1029       __ reg2mem_opt(src->as_register(), dst, true);
1030     } else {
1031       __ reg2mem_opt(src->as_register(), dst, false);
1032     }
1033   } else if (src->is_double_cpu()) {
1034     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix());
1035     __ reg2mem_opt(src->as_register_lo(), dstLO, true);
1036   } else if (src->is_single_fpu()) {
1037     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
1038     __ freg2mem_opt(src->as_float_reg(), dst_addr, false);
1039   } else if (src->is_double_fpu()) {
1040     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
1041     __ freg2mem_opt(src->as_double_reg(), dst_addr, true);
1042   } else {
1043     ShouldNotReachHere();
1044   }
1045 }
1046 
1047 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1048   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1049     if (from_reg->is_double_fpu()) {
1050       // double to double moves
1051       assert(to_reg->is_double_fpu(), "should match");
1052       __ z_ldr(to_reg->as_double_reg(), from_reg->as_double_reg());
1053     } else {
1054       // float to float moves
1055       assert(to_reg->is_single_fpu(), "should match");
1056       __ z_ler(to_reg->as_float_reg(), from_reg->as_float_reg());
1057     }
1058   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1059     if (from_reg->is_double_cpu()) {
1060       __ z_lgr(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1061     } else if (to_reg->is_double_cpu()) {
1062       // int to int moves
1063       __ z_lgr(to_reg->as_register_lo(), from_reg->as_register());
1064     } else {
1065       // int to int moves
1066       __ z_lgr(to_reg->as_register(), from_reg->as_register());
1067     }
1068   } else {
1069     ShouldNotReachHere();
1070   }
1071   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1072     __ verify_oop(to_reg->as_register());
1073   }
1074 }
1075 
1076 void LIR_Assembler::reg2mem(LIR_Opr from, LIR_Opr dest_opr, BasicType type,
1077                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1078                             bool wide, bool unaligned) {
1079   assert(type != T_METADATA, "store of metadata ptr not supported");
1080   LIR_Address* addr = dest_opr->as_address_ptr();
1081 
1082   Register dest = addr->base()->as_pointer_register();
1083   Register disp_reg = Z_R0;
1084   int disp_value = addr->disp();
1085   bool needs_patching = (patch_code != lir_patch_none);
1086 
1087   if (addr->base()->is_oop_register()) {
1088     __ verify_oop(dest);
1089   }
1090 
1091   PatchingStub* patch = NULL;
1092   if (needs_patching) {
1093     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1094     assert(!from->is_double_cpu() ||
1095            patch_code == lir_patch_none ||
1096            patch_code == lir_patch_normal, "patching doesn't match register");
1097   }
1098 
1099   assert(!needs_patching || (!Immediate::is_simm20(disp_value) && addr->index()->is_illegal()), "assumption");
1100   if (addr->index()->is_illegal()) {
1101     if (!Immediate::is_simm20(disp_value)) {
1102       if (needs_patching) {
1103         __ load_const(Z_R1_scratch, (intptr_t)0);
1104       } else {
1105         __ load_const_optimized(Z_R1_scratch, disp_value);
1106       }
1107       disp_reg = Z_R1_scratch;
1108       disp_value = 0;
1109     }
1110   } else {
1111     if (!Immediate::is_simm20(disp_value)) {
1112       __ load_const_optimized(Z_R1_scratch, disp_value);
1113       __ z_la(Z_R1_scratch, 0, Z_R1_scratch, addr->index()->as_register());
1114       disp_reg = Z_R1_scratch;
1115       disp_value = 0;
1116     }
1117     disp_reg = addr->index()->as_pointer_register();
1118   }
1119 
1120   assert(disp_reg != Z_R0 || Immediate::is_simm20(disp_value), "should have set this up");
1121 
1122   if (type == T_ARRAY || type == T_OBJECT) {
1123     __ verify_oop(from->as_register());
1124   }
1125 
1126   bool short_disp = Immediate::is_uimm12(disp_value);
1127 
1128   // Remember the offset of the store. The patching_epilog must be done
1129   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1130   // entered in increasing order.
1131   int offset = code_offset();
1132   switch (type) {
1133     case T_BOOLEAN: // fall through
1134     case T_BYTE  :
1135       if (short_disp) {
1136                     __ z_stc(from->as_register(),  disp_value, disp_reg, dest);
1137       } else {
1138                     __ z_stcy(from->as_register(), disp_value, disp_reg, dest);
1139       }
1140       break;
1141     case T_CHAR  : // fall through
1142     case T_SHORT :
1143       if (short_disp) {
1144                     __ z_sth(from->as_register(),  disp_value, disp_reg, dest);
1145       } else {
1146                     __ z_sthy(from->as_register(), disp_value, disp_reg, dest);
1147       }
1148       break;
1149     case T_INT   :
1150       if (short_disp) {
1151                     __ z_st(from->as_register(),  disp_value, disp_reg, dest);
1152       } else {
1153                     __ z_sty(from->as_register(), disp_value, disp_reg, dest);
1154       }
1155       break;
1156     case T_LONG  :  __ z_stg(from->as_register_lo(), disp_value, disp_reg, dest); break;
1157     case T_ADDRESS: __ z_stg(from->as_register(),    disp_value, disp_reg, dest); break;
1158       break;
1159     case T_ARRAY : // fall through
1160     case T_OBJECT:
1161       {
1162         if (UseCompressedOops && !wide) {
1163           Register compressed_src = Z_R14;
1164           __ oop_encoder(compressed_src, from->as_register(), true, (disp_reg != Z_R1) ? Z_R1 : Z_R0, -1, true);
1165           offset = code_offset();
1166           if (short_disp) {
1167             __ z_st(compressed_src,  disp_value, disp_reg, dest);
1168           } else {
1169             __ z_sty(compressed_src, disp_value, disp_reg, dest);
1170           }
1171         } else {
1172           __ z_stg(from->as_register(), disp_value, disp_reg, dest);
1173         }
1174         break;
1175       }
1176     case T_FLOAT :
1177       if (short_disp) {
1178         __ z_ste(from->as_float_reg(),  disp_value, disp_reg, dest);
1179       } else {
1180         __ z_stey(from->as_float_reg(), disp_value, disp_reg, dest);
1181       }
1182       break;
1183     case T_DOUBLE:
1184       if (short_disp) {
1185         __ z_std(from->as_double_reg(),  disp_value, disp_reg, dest);
1186       } else {
1187         __ z_stdy(from->as_double_reg(), disp_value, disp_reg, dest);
1188       }
1189       break;
1190     default: ShouldNotReachHere();
1191   }
1192 
1193   if (patch != NULL) {
1194     patching_epilog(patch, patch_code, dest, info);
1195   }
1196 
1197   if (info != NULL) add_debug_info_for_null_check(offset, info);
1198 }
1199 
1200 
1201 void LIR_Assembler::return_op(LIR_Opr result) {
1202   assert(result->is_illegal() ||
1203          (result->is_single_cpu() && result->as_register() == Z_R2) ||
1204          (result->is_double_cpu() && result->as_register_lo() == Z_R2) ||
1205          (result->is_single_fpu() && result->as_float_reg() == Z_F0) ||
1206          (result->is_double_fpu() && result->as_double_reg() == Z_F0), "convention");
1207 
1208   if (SafepointMechanism::uses_thread_local_poll()) {
1209     __ z_lg(Z_R1_scratch, Address(Z_thread, Thread::polling_page_offset()));
1210   } else {
1211     AddressLiteral pp(os::get_polling_page());
1212     __ load_const_optimized(Z_R1_scratch, pp);
1213   }
1214 
1215   // Pop the frame before the safepoint code.
1216   __ pop_frame_restore_retPC(initial_frame_size_in_bytes());
1217 
1218   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1219     __ reserved_stack_check(Z_R14);
1220   }
1221 
1222   // We need to mark the code position where the load from the safepoint
1223   // polling page was emitted as relocInfo::poll_return_type here.
1224   __ relocate(relocInfo::poll_return_type);
1225   __ load_from_polling_page(Z_R1_scratch);
1226 
1227   __ z_br(Z_R14); // Return to caller.
1228 }
1229 
1230 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1231   const Register poll_addr = tmp->as_register_lo();
1232   if (SafepointMechanism::uses_thread_local_poll()) {
1233     __ z_lg(poll_addr, Address(Z_thread, Thread::polling_page_offset()));
1234   } else {
1235     AddressLiteral pp(os::get_polling_page());
1236     __ load_const_optimized(poll_addr, pp);
1237   }
1238   guarantee(info != NULL, "Shouldn't be NULL");
1239   add_debug_info_for_branch(info);
1240   int offset = __ offset();
1241   __ relocate(relocInfo::poll_type);
1242   __ load_from_polling_page(poll_addr);
1243   return offset;
1244 }
1245 
1246 void LIR_Assembler::emit_static_call_stub() {
1247 
1248   // Stub is fixed up when the corresponding call is converted from calling
1249   // compiled code to calling interpreted code.
1250 
1251   address call_pc = __ pc();
1252   address stub = __ start_a_stub(call_stub_size());
1253   if (stub == NULL) {
1254     bailout("static call stub overflow");
1255     return;
1256   }
1257 
1258   int start = __ offset();
1259 
1260   __ relocate(static_stub_Relocation::spec(call_pc));
1261 
1262   // See also Matcher::interpreter_method_oop_reg().
1263   AddressLiteral meta = __ allocate_metadata_address(NULL);
1264   bool success = __ load_const_from_toc(Z_method, meta);
1265 
1266   __ set_inst_mark();
1267   AddressLiteral a((address)-1);
1268   success = success && __ load_const_from_toc(Z_R1, a);
1269   if (!success) {
1270     bailout("const section overflow");
1271     return;
1272   }
1273 
1274   __ z_br(Z_R1);
1275   assert(__ offset() - start <= call_stub_size(), "stub too big");
1276   __ end_a_stub(); // Update current stubs pointer and restore insts_end.
1277 }
1278 
1279 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1280   bool unsigned_comp = condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual;
1281   if (opr1->is_single_cpu()) {
1282     Register reg1 = opr1->as_register();
1283     if (opr2->is_single_cpu()) {
1284       // cpu register - cpu register
1285       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1286         __ z_clgr(reg1, opr2->as_register());
1287       } else {
1288         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
1289         if (unsigned_comp) {
1290           __ z_clr(reg1, opr2->as_register());
1291         } else {
1292           __ z_cr(reg1, opr2->as_register());
1293         }
1294       }
1295     } else if (opr2->is_stack()) {
1296       // cpu register - stack
1297       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
1298         __ z_cg(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1299       } else {
1300         if (unsigned_comp) {
1301           __ z_cly(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1302         } else {
1303           __ z_cy(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
1304         }
1305       }
1306     } else if (opr2->is_constant()) {
1307       // cpu register - constant
1308       LIR_Const* c = opr2->as_constant_ptr();
1309       if (c->type() == T_INT) {
1310         if (unsigned_comp) {
1311           __ z_clfi(reg1, c->as_jint());
1312         } else {
1313           __ z_cfi(reg1, c->as_jint());
1314         }
1315       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
1316         // In 64bit oops are single register.
1317         jobject o = c->as_jobject();
1318         if (o == NULL) {
1319           __ z_ltgr(reg1, reg1);
1320         } else {
1321           jobject2reg(o, Z_R1_scratch);
1322           __ z_cgr(reg1, Z_R1_scratch);
1323         }
1324       } else {
1325         fatal("unexpected type: %s", basictype_to_str(c->type()));
1326       }
1327       // cpu register - address
1328     } else if (opr2->is_address()) {
1329       if (op->info() != NULL) {
1330         add_debug_info_for_null_check_here(op->info());
1331       }
1332       if (unsigned_comp) {
1333         __ z_cly(reg1, as_Address(opr2->as_address_ptr()));
1334       } else {
1335         __ z_cy(reg1, as_Address(opr2->as_address_ptr()));
1336       }
1337     } else {
1338       ShouldNotReachHere();
1339     }
1340 
1341   } else if (opr1->is_double_cpu()) {
1342     assert(!unsigned_comp, "unexpected");
1343     Register xlo = opr1->as_register_lo();
1344     Register xhi = opr1->as_register_hi();
1345     if (opr2->is_double_cpu()) {
1346       __ z_cgr(xlo, opr2->as_register_lo());
1347     } else if (opr2->is_constant()) {
1348       // cpu register - constant 0
1349       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
1350       __ z_ltgr(xlo, xlo);
1351     } else {
1352       ShouldNotReachHere();
1353     }
1354 
1355   } else if (opr1->is_single_fpu()) {
1356     if (opr2->is_single_fpu()) {
1357       __ z_cebr(opr1->as_float_reg(), opr2->as_float_reg());
1358     } else {
1359       // stack slot
1360       Address addr = frame_map()->address_for_slot(opr2->single_stack_ix());
1361       if (Immediate::is_uimm12(addr.disp())) {
1362         __ z_ceb(opr1->as_float_reg(), addr);
1363       } else {
1364         __ z_ley(Z_fscratch_1, addr);
1365         __ z_cebr(opr1->as_float_reg(), Z_fscratch_1);
1366       }
1367     }
1368   } else if (opr1->is_double_fpu()) {
1369     if (opr2->is_double_fpu()) {
1370     __ z_cdbr(opr1->as_double_reg(), opr2->as_double_reg());
1371     } else {
1372       // stack slot
1373       Address addr = frame_map()->address_for_slot(opr2->double_stack_ix());
1374       if (Immediate::is_uimm12(addr.disp())) {
1375         __ z_cdb(opr1->as_double_reg(), addr);
1376       } else {
1377         __ z_ldy(Z_fscratch_1, addr);
1378         __ z_cdbr(opr1->as_double_reg(), Z_fscratch_1);
1379       }
1380     }
1381   } else {
1382     ShouldNotReachHere();
1383   }
1384 }
1385 
1386 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
1387   Label    done;
1388   Register dreg = dst->as_register();
1389 
1390   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1391     assert((left->is_single_fpu() && right->is_single_fpu()) ||
1392            (left->is_double_fpu() && right->is_double_fpu()), "unexpected operand types");
1393     bool is_single = left->is_single_fpu();
1394     bool is_unordered_less = (code == lir_ucmp_fd2i);
1395     FloatRegister lreg = is_single ? left->as_float_reg() : left->as_double_reg();
1396     FloatRegister rreg = is_single ? right->as_float_reg() : right->as_double_reg();
1397     if (is_single) {
1398       __ z_cebr(lreg, rreg);
1399     } else {
1400       __ z_cdbr(lreg, rreg);
1401     }
1402     if (VM_Version::has_LoadStoreConditional()) {
1403       Register one       = Z_R0_scratch;
1404       Register minus_one = Z_R1_scratch;
1405       __ z_lghi(minus_one, -1);
1406       __ z_lghi(one,  1);
1407       __ z_lghi(dreg, 0);
1408       __ z_locgr(dreg, one,       is_unordered_less ? Assembler::bcondHigh            : Assembler::bcondHighOrNotOrdered);
1409       __ z_locgr(dreg, minus_one, is_unordered_less ? Assembler::bcondLowOrNotOrdered : Assembler::bcondLow);
1410     } else {
1411       __ clear_reg(dreg, true, false);
1412       __ z_bre(done); // if (left == right) dst = 0
1413 
1414       // if (left > right || ((code ~= cmpg) && (left <> right)) dst := 1
1415       __ z_lhi(dreg, 1);
1416       __ z_brc(is_unordered_less ? Assembler::bcondHigh : Assembler::bcondHighOrNotOrdered, done);
1417 
1418       // if (left < right || ((code ~= cmpl) && (left <> right)) dst := -1
1419       __ z_lhi(dreg, -1);
1420     }
1421   } else {
1422     assert(code == lir_cmp_l2i, "check");
1423     if (VM_Version::has_LoadStoreConditional()) {
1424       Register one       = Z_R0_scratch;
1425       Register minus_one = Z_R1_scratch;
1426       __ z_cgr(left->as_register_lo(), right->as_register_lo());
1427       __ z_lghi(minus_one, -1);
1428       __ z_lghi(one,  1);
1429       __ z_lghi(dreg, 0);
1430       __ z_locgr(dreg, one, Assembler::bcondHigh);
1431       __ z_locgr(dreg, minus_one, Assembler::bcondLow);
1432     } else {
1433       __ z_cgr(left->as_register_lo(), right->as_register_lo());
1434       __ z_lghi(dreg,  0);     // eq value
1435       __ z_bre(done);
1436       __ z_lghi(dreg,  1);     // gt value
1437       __ z_brh(done);
1438       __ z_lghi(dreg, -1);     // lt value
1439     }
1440   }
1441   __ bind(done);
1442 }
1443 
1444 // result = condition ? opr1 : opr2
1445 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1446   Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
1447   switch (condition) {
1448     case lir_cond_equal:        acond = Assembler::bcondEqual;    ncond = Assembler::bcondNotEqual; break;
1449     case lir_cond_notEqual:     acond = Assembler::bcondNotEqual; ncond = Assembler::bcondEqual;    break;
1450     case lir_cond_less:         acond = Assembler::bcondLow;      ncond = Assembler::bcondNotLow;   break;
1451     case lir_cond_lessEqual:    acond = Assembler::bcondNotHigh;  ncond = Assembler::bcondHigh;     break;
1452     case lir_cond_greaterEqual: acond = Assembler::bcondNotLow;   ncond = Assembler::bcondLow;      break;
1453     case lir_cond_greater:      acond = Assembler::bcondHigh;     ncond = Assembler::bcondNotHigh;  break;
1454     case lir_cond_belowEqual:   acond = Assembler::bcondNotHigh;  ncond = Assembler::bcondHigh;     break;
1455     case lir_cond_aboveEqual:   acond = Assembler::bcondNotLow;   ncond = Assembler::bcondLow;      break;
1456     default:                    ShouldNotReachHere();
1457   }
1458 
1459   if (opr1->is_cpu_register()) {
1460     reg2reg(opr1, result);
1461   } else if (opr1->is_stack()) {
1462     stack2reg(opr1, result, result->type());
1463   } else if (opr1->is_constant()) {
1464     const2reg(opr1, result, lir_patch_none, NULL);
1465   } else {
1466     ShouldNotReachHere();
1467   }
1468 
1469   if (VM_Version::has_LoadStoreConditional() && !opr2->is_constant()) {
1470     // Optimized version that does not require a branch.
1471     if (opr2->is_single_cpu()) {
1472       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
1473       __ z_locgr(result->as_register(), opr2->as_register(), ncond);
1474     } else if (opr2->is_double_cpu()) {
1475       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1476       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
1477       __ z_locgr(result->as_register_lo(), opr2->as_register_lo(), ncond);
1478     } else if (opr2->is_single_stack()) {
1479       __ z_loc(result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()), ncond);
1480     } else if (opr2->is_double_stack()) {
1481       __ z_locg(result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix()), ncond);
1482     } else {
1483       ShouldNotReachHere();
1484     }
1485   } else {
1486     Label skip;
1487     __ z_brc(acond, skip);
1488     if (opr2->is_cpu_register()) {
1489       reg2reg(opr2, result);
1490     } else if (opr2->is_stack()) {
1491       stack2reg(opr2, result, result->type());
1492     } else if (opr2->is_constant()) {
1493       const2reg(opr2, result, lir_patch_none, NULL);
1494     } else {
1495       ShouldNotReachHere();
1496     }
1497     __ bind(skip);
1498   }
1499 }
1500 
1501 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1502                              CodeEmitInfo* info, bool pop_fpu_stack) {
1503   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1504 
1505   if (left->is_single_cpu()) {
1506     assert(left == dest, "left and dest must be equal");
1507     Register lreg = left->as_register();
1508 
1509     if (right->is_single_cpu()) {
1510       // cpu register - cpu register
1511       Register rreg = right->as_register();
1512       switch (code) {
1513         case lir_add: __ z_ar (lreg, rreg); break;
1514         case lir_sub: __ z_sr (lreg, rreg); break;
1515         case lir_mul: __ z_msr(lreg, rreg); break;
1516         default: ShouldNotReachHere();
1517       }
1518 
1519     } else if (right->is_stack()) {
1520       // cpu register - stack
1521       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1522       switch (code) {
1523         case lir_add: __ z_ay(lreg, raddr); break;
1524         case lir_sub: __ z_sy(lreg, raddr); break;
1525         default: ShouldNotReachHere();
1526       }
1527 
1528     } else if (right->is_constant()) {
1529       // cpu register - constant
1530       jint c = right->as_constant_ptr()->as_jint();
1531       switch (code) {
1532         case lir_add: __ z_agfi(lreg, c);  break;
1533         case lir_sub: __ z_agfi(lreg, -c); break; // note: -min_jint == min_jint
1534         case lir_mul: __ z_msfi(lreg, c);  break;
1535         default: ShouldNotReachHere();
1536       }
1537 
1538     } else {
1539       ShouldNotReachHere();
1540     }
1541 
1542   } else if (left->is_double_cpu()) {
1543     assert(left == dest, "left and dest must be equal");
1544     Register lreg_lo = left->as_register_lo();
1545     Register lreg_hi = left->as_register_hi();
1546 
1547     if (right->is_double_cpu()) {
1548       // cpu register - cpu register
1549       Register rreg_lo = right->as_register_lo();
1550       Register rreg_hi = right->as_register_hi();
1551       assert_different_registers(lreg_lo, rreg_lo);
1552       switch (code) {
1553         case lir_add:
1554           __ z_agr(lreg_lo, rreg_lo);
1555           break;
1556         case lir_sub:
1557           __ z_sgr(lreg_lo, rreg_lo);
1558           break;
1559         case lir_mul:
1560           __ z_msgr(lreg_lo, rreg_lo);
1561           break;
1562         default:
1563           ShouldNotReachHere();
1564       }
1565 
1566     } else if (right->is_constant()) {
1567       // cpu register - constant
1568       jlong c = right->as_constant_ptr()->as_jlong_bits();
1569       switch (code) {
1570         case lir_add: __ z_agfi(lreg_lo, c); break;
1571         case lir_sub:
1572           if (c != min_jint) {
1573                       __ z_agfi(lreg_lo, -c);
1574           } else {
1575             // -min_jint cannot be represented as simm32 in z_agfi
1576             // min_jint sign extended:      0xffffffff80000000
1577             // -min_jint as 64 bit integer: 0x0000000080000000
1578             // 0x80000000 can be represented as uimm32 in z_algfi
1579             // lreg_lo := lreg_lo + -min_jint == lreg_lo + 0x80000000
1580                       __ z_algfi(lreg_lo, UCONST64(0x80000000));
1581           }
1582           break;
1583         case lir_mul: __ z_msgfi(lreg_lo, c); break;
1584         default:
1585           ShouldNotReachHere();
1586       }
1587 
1588     } else {
1589       ShouldNotReachHere();
1590     }
1591 
1592   } else if (left->is_single_fpu()) {
1593     assert(left == dest, "left and dest must be equal");
1594     FloatRegister lreg = left->as_float_reg();
1595     FloatRegister rreg = right->is_single_fpu() ? right->as_float_reg() : fnoreg;
1596     Address raddr;
1597 
1598     if (rreg == fnoreg) {
1599       assert(right->is_single_stack(), "constants should be loaded into register");
1600       raddr = frame_map()->address_for_slot(right->single_stack_ix());
1601       if (!Immediate::is_uimm12(raddr.disp())) {
1602         __ mem2freg_opt(rreg = Z_fscratch_1, raddr, false);
1603       }
1604     }
1605 
1606     if (rreg != fnoreg) {
1607       switch (code) {
1608         case lir_add: __ z_aebr(lreg, rreg);  break;
1609         case lir_sub: __ z_sebr(lreg, rreg);  break;
1610         case lir_mul_strictfp: // fall through
1611         case lir_mul: __ z_meebr(lreg, rreg); break;
1612         case lir_div_strictfp: // fall through
1613         case lir_div: __ z_debr(lreg, rreg);  break;
1614         default: ShouldNotReachHere();
1615       }
1616     } else {
1617       switch (code) {
1618         case lir_add: __ z_aeb(lreg, raddr);  break;
1619         case lir_sub: __ z_seb(lreg, raddr);  break;
1620         case lir_mul_strictfp: // fall through
1621         case lir_mul: __ z_meeb(lreg, raddr);  break;
1622         case lir_div_strictfp: // fall through
1623         case lir_div: __ z_deb(lreg, raddr);  break;
1624         default: ShouldNotReachHere();
1625       }
1626     }
1627   } else if (left->is_double_fpu()) {
1628     assert(left == dest, "left and dest must be equal");
1629     FloatRegister lreg = left->as_double_reg();
1630     FloatRegister rreg = right->is_double_fpu() ? right->as_double_reg() : fnoreg;
1631     Address raddr;
1632 
1633     if (rreg == fnoreg) {
1634       assert(right->is_double_stack(), "constants should be loaded into register");
1635       raddr = frame_map()->address_for_slot(right->double_stack_ix());
1636       if (!Immediate::is_uimm12(raddr.disp())) {
1637         __ mem2freg_opt(rreg = Z_fscratch_1, raddr, true);
1638       }
1639     }
1640 
1641     if (rreg != fnoreg) {
1642       switch (code) {
1643         case lir_add: __ z_adbr(lreg, rreg); break;
1644         case lir_sub: __ z_sdbr(lreg, rreg); break;
1645         case lir_mul_strictfp: // fall through
1646         case lir_mul: __ z_mdbr(lreg, rreg); break;
1647         case lir_div_strictfp: // fall through
1648         case lir_div: __ z_ddbr(lreg, rreg); break;
1649         default: ShouldNotReachHere();
1650       }
1651     } else {
1652       switch (code) {
1653         case lir_add: __ z_adb(lreg, raddr); break;
1654         case lir_sub: __ z_sdb(lreg, raddr); break;
1655         case lir_mul_strictfp: // fall through
1656         case lir_mul: __ z_mdb(lreg, raddr); break;
1657         case lir_div_strictfp: // fall through
1658         case lir_div: __ z_ddb(lreg, raddr); break;
1659         default: ShouldNotReachHere();
1660       }
1661     }
1662   } else if (left->is_address()) {
1663     assert(left == dest, "left and dest must be equal");
1664     assert(code == lir_add, "unsupported operation");
1665     assert(right->is_constant(), "unsupported operand");
1666     jint c = right->as_constant_ptr()->as_jint();
1667     LIR_Address* lir_addr = left->as_address_ptr();
1668     Address addr = as_Address(lir_addr);
1669     switch (lir_addr->type()) {
1670       case T_INT:
1671         __ add2mem_32(addr, c, Z_R1_scratch);
1672         break;
1673       case T_LONG:
1674         __ add2mem_64(addr, c, Z_R1_scratch);
1675         break;
1676       default:
1677         ShouldNotReachHere();
1678     }
1679   } else {
1680     ShouldNotReachHere();
1681   }
1682 }
1683 
1684 void LIR_Assembler::fpop() {
1685   // do nothing
1686 }
1687 
1688 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1689   switch (code) {
1690     case lir_sqrt: {
1691       assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt");
1692       FloatRegister src_reg = value->as_double_reg();
1693       FloatRegister dst_reg = dest->as_double_reg();
1694       __ z_sqdbr(dst_reg, src_reg);
1695       break;
1696     }
1697     case lir_abs: {
1698       assert(!thread->is_valid(), "there is no need for a thread_reg for fabs");
1699       FloatRegister src_reg = value->as_double_reg();
1700       FloatRegister dst_reg = dest->as_double_reg();
1701       __ z_lpdbr(dst_reg, src_reg);
1702       break;
1703     }
1704     default: {
1705       ShouldNotReachHere();
1706       break;
1707     }
1708   }
1709 }
1710 
1711 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1712   if (left->is_single_cpu()) {
1713     Register reg = left->as_register();
1714     if (right->is_constant()) {
1715       int val = right->as_constant_ptr()->as_jint();
1716       switch (code) {
1717         case lir_logic_and: __ z_nilf(reg, val); break;
1718         case lir_logic_or:  __ z_oilf(reg, val); break;
1719         case lir_logic_xor: __ z_xilf(reg, val); break;
1720         default: ShouldNotReachHere();
1721       }
1722     } else if (right->is_stack()) {
1723       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
1724       switch (code) {
1725         case lir_logic_and: __ z_ny(reg, raddr); break;
1726         case lir_logic_or:  __ z_oy(reg, raddr); break;
1727         case lir_logic_xor: __ z_xy(reg, raddr); break;
1728         default: ShouldNotReachHere();
1729       }
1730     } else {
1731       Register rright = right->as_register();
1732       switch (code) {
1733         case lir_logic_and: __ z_nr(reg, rright); break;
1734         case lir_logic_or : __ z_or(reg, rright); break;
1735         case lir_logic_xor: __ z_xr(reg, rright); break;
1736         default: ShouldNotReachHere();
1737       }
1738     }
1739     move_regs(reg, dst->as_register());
1740   } else {
1741     Register l_lo = left->as_register_lo();
1742     if (right->is_constant()) {
1743       __ load_const_optimized(Z_R1_scratch, right->as_constant_ptr()->as_jlong());
1744       switch (code) {
1745         case lir_logic_and:
1746           __ z_ngr(l_lo, Z_R1_scratch);
1747           break;
1748         case lir_logic_or:
1749           __ z_ogr(l_lo, Z_R1_scratch);
1750           break;
1751         case lir_logic_xor:
1752           __ z_xgr(l_lo, Z_R1_scratch);
1753           break;
1754         default: ShouldNotReachHere();
1755       }
1756     } else {
1757       Register r_lo;
1758       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
1759         r_lo = right->as_register();
1760       } else {
1761         r_lo = right->as_register_lo();
1762       }
1763       switch (code) {
1764         case lir_logic_and:
1765           __ z_ngr(l_lo, r_lo);
1766           break;
1767         case lir_logic_or:
1768           __ z_ogr(l_lo, r_lo);
1769           break;
1770         case lir_logic_xor:
1771           __ z_xgr(l_lo, r_lo);
1772           break;
1773         default: ShouldNotReachHere();
1774       }
1775     }
1776 
1777     Register dst_lo = dst->as_register_lo();
1778 
1779     move_regs(l_lo, dst_lo);
1780   }
1781 }
1782 
1783 // See operand selection in LIRGenerator::do_ArithmeticOp_Int().
1784 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
1785   if (left->is_double_cpu()) {
1786     // 64 bit integer case
1787     assert(left->is_double_cpu(), "left must be register");
1788     assert(right->is_double_cpu() || is_power_of_2_long(right->as_jlong()),
1789            "right must be register or power of 2 constant");
1790     assert(result->is_double_cpu(), "result must be register");
1791 
1792     Register lreg = left->as_register_lo();
1793     Register dreg = result->as_register_lo();
1794 
1795     if (right->is_constant()) {
1796       // Convert division by a power of two into some shifts and logical operations.
1797       Register treg1 = Z_R0_scratch;
1798       Register treg2 = Z_R1_scratch;
1799       jlong divisor = right->as_jlong();
1800       jlong log_divisor = log2_long(right->as_jlong());
1801 
1802       if (divisor == min_jlong) {
1803         // Min_jlong is special. Result is '0' except for min_jlong/min_jlong = 1.
1804         if (dreg == lreg) {
1805           NearLabel done;
1806           __ load_const_optimized(treg2, min_jlong);
1807           __ z_cgr(lreg, treg2);
1808           __ z_lghi(dreg, 0);           // Preserves condition code.
1809           __ z_brne(done);
1810           __ z_lghi(dreg, 1);           // min_jlong / min_jlong = 1
1811           __ bind(done);
1812         } else {
1813           assert_different_registers(dreg, lreg);
1814           NearLabel done;
1815           __ z_lghi(dreg, 0);
1816           __ compare64_and_branch(lreg, min_jlong, Assembler::bcondNotEqual, done);
1817           __ z_lghi(dreg, 1);
1818           __ bind(done);
1819         }
1820         return;
1821       }
1822       __ move_reg_if_needed(dreg, T_LONG, lreg, T_LONG);
1823       if (divisor == 2) {
1824         __ z_srlg(treg2, dreg, 63);     // dividend < 0 ? 1 : 0
1825       } else {
1826         __ z_srag(treg2, dreg, 63);     // dividend < 0 ? -1 : 0
1827         __ and_imm(treg2, divisor - 1, treg1, true);
1828       }
1829       if (code == lir_idiv) {
1830         __ z_agr(dreg, treg2);
1831         __ z_srag(dreg, dreg, log_divisor);
1832       } else {
1833         assert(code == lir_irem, "check");
1834         __ z_agr(treg2, dreg);
1835         __ and_imm(treg2, ~(divisor - 1), treg1, true);
1836         __ z_sgr(dreg, treg2);
1837       }
1838       return;
1839     }
1840 
1841     // Divisor is not a power of 2 constant.
1842     Register rreg = right->as_register_lo();
1843     Register treg = temp->as_register_lo();
1844     assert(right->is_double_cpu(), "right must be register");
1845     assert(lreg == Z_R11, "see ldivInOpr()");
1846     assert(rreg != lreg, "right register must not be same as left register");
1847     assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10) ||
1848            (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see ldivInOpr(), ldivOutOpr(), lremOutOpr()");
1849 
1850     Register R1 = lreg->predecessor();
1851     Register R2 = rreg;
1852     assert(code != lir_idiv || lreg==dreg, "see code below");
1853     if (code == lir_idiv) {
1854       __ z_lcgr(lreg, lreg);
1855     } else {
1856       __ clear_reg(dreg, true, false);
1857     }
1858     NearLabel done;
1859     __ compare64_and_branch(R2, -1, Assembler::bcondEqual, done);
1860     if (code == lir_idiv) {
1861       __ z_lcgr(lreg, lreg); // Revert lcgr above.
1862     }
1863     if (ImplicitDiv0Checks) {
1864       // No debug info because the idiv won't trap.
1865       // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1866       // which is unnecessary, too.
1867       add_debug_info_for_div0(__ offset(), info);
1868     }
1869     __ z_dsgr(R1, R2);
1870     __ bind(done);
1871     return;
1872   }
1873 
1874   // 32 bit integer case
1875 
1876   assert(left->is_single_cpu(), "left must be register");
1877   assert(right->is_single_cpu() || is_power_of_2(right->as_jint()), "right must be register or power of 2 constant");
1878   assert(result->is_single_cpu(), "result must be register");
1879 
1880   Register lreg = left->as_register();
1881   Register dreg = result->as_register();
1882 
1883   if (right->is_constant()) {
1884     // Convert division by a power of two into some shifts and logical operations.
1885     Register treg1 = Z_R0_scratch;
1886     Register treg2 = Z_R1_scratch;
1887     jlong divisor = right->as_jint();
1888     jlong log_divisor = log2_long(right->as_jint());
1889     __ move_reg_if_needed(dreg, T_LONG, lreg, T_INT); // sign extend
1890     if (divisor == 2) {
1891       __ z_srlg(treg2, dreg, 63);     // dividend < 0 ?  1 : 0
1892     } else {
1893       __ z_srag(treg2, dreg, 63);     // dividend < 0 ? -1 : 0
1894       __ and_imm(treg2, divisor - 1, treg1, true);
1895     }
1896     if (code == lir_idiv) {
1897       __ z_agr(dreg, treg2);
1898       __ z_srag(dreg, dreg, log_divisor);
1899     } else {
1900       assert(code == lir_irem, "check");
1901       __ z_agr(treg2, dreg);
1902       __ and_imm(treg2, ~(divisor - 1), treg1, true);
1903       __ z_sgr(dreg, treg2);
1904     }
1905     return;
1906   }
1907 
1908   // Divisor is not a power of 2 constant.
1909   Register rreg = right->as_register();
1910   Register treg = temp->as_register();
1911   assert(right->is_single_cpu(), "right must be register");
1912   assert(lreg == Z_R11, "left register must be rax,");
1913   assert(rreg != lreg, "right register must not be same as left register");
1914   assert((code == lir_idiv && dreg == Z_R11 && treg == Z_R10)
1915       || (code == lir_irem && dreg == Z_R10 && treg == Z_R11), "see divInOpr(), divOutOpr(), remOutOpr()");
1916 
1917   Register R1 = lreg->predecessor();
1918   Register R2 = rreg;
1919   __ move_reg_if_needed(lreg, T_LONG, lreg, T_INT); // sign extend
1920   if (ImplicitDiv0Checks) {
1921     // No debug info because the idiv won't trap.
1922     // Add_debug_info_for_div0 would instantiate another DivByZeroStub,
1923     // which is unnecessary, too.
1924     add_debug_info_for_div0(__ offset(), info);
1925   }
1926   __ z_dsgfr(R1, R2);
1927 }
1928 
1929 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1930   assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1931   assert(exceptionPC->as_register() == Z_EXC_PC, "should match");
1932 
1933   // Exception object is not added to oop map by LinearScan
1934   // (LinearScan assumes that no oops are in fixed registers).
1935   info->add_register_oop(exceptionOop);
1936 
1937   // Reuse the debug info from the safepoint poll for the throw op itself.
1938   __ get_PC(Z_EXC_PC);
1939   add_call_info(__ offset(), info); // for exception handler
1940   address stub = Runtime1::entry_for (compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1941                                                                     : Runtime1::handle_exception_nofpu_id);
1942   emit_call_c(stub);
1943 }
1944 
1945 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1946   assert(exceptionOop->as_register() == Z_EXC_OOP, "should match");
1947 
1948   __ branch_optimized(Assembler::bcondAlways, _unwind_handler_entry);
1949 }
1950 
1951 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1952   ciArrayKlass* default_type = op->expected_type();
1953   Register src = op->src()->as_register();
1954   Register dst = op->dst()->as_register();
1955   Register src_pos = op->src_pos()->as_register();
1956   Register dst_pos = op->dst_pos()->as_register();
1957   Register length  = op->length()->as_register();
1958   Register tmp = op->tmp()->as_register();
1959 
1960   CodeStub* stub = op->stub();
1961   int flags = op->flags();
1962   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1963   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1964 
1965   // If we don't know anything, just go through the generic arraycopy.
1966   if (default_type == NULL) {
1967     address copyfunc_addr = StubRoutines::generic_arraycopy();
1968 
1969     if (copyfunc_addr == NULL) {
1970       // Take a slow path for generic arraycopy.
1971       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
1972       __ bind(*stub->continuation());
1973       return;
1974     }
1975 
1976     Label done;
1977     // Save outgoing arguments in callee saved registers (C convention) in case
1978     // a call to System.arraycopy is needed.
1979     Register callee_saved_src     = Z_R10;
1980     Register callee_saved_src_pos = Z_R11;
1981     Register callee_saved_dst     = Z_R12;
1982     Register callee_saved_dst_pos = Z_R13;
1983     Register callee_saved_length  = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
1984 
1985     __ lgr_if_needed(callee_saved_src, src);
1986     __ lgr_if_needed(callee_saved_src_pos, src_pos);
1987     __ lgr_if_needed(callee_saved_dst, dst);
1988     __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
1989     __ lgr_if_needed(callee_saved_length, length);
1990 
1991     // C function requires 64 bit values.
1992     __ z_lgfr(src_pos, src_pos);
1993     __ z_lgfr(dst_pos, dst_pos);
1994     __ z_lgfr(length, length);
1995 
1996     // Pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint.
1997 
1998     // The arguments are in the corresponding registers.
1999     assert(Z_ARG1 == src,     "assumption");
2000     assert(Z_ARG2 == src_pos, "assumption");
2001     assert(Z_ARG3 == dst,     "assumption");
2002     assert(Z_ARG4 == dst_pos, "assumption");
2003     assert(Z_ARG5 == length,  "assumption");
2004 #ifndef PRODUCT
2005     if (PrintC1Statistics) {
2006       __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_generic_arraycopystub_cnt);
2007       __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2008     }
2009 #endif
2010     emit_call_c(copyfunc_addr);
2011     CHECK_BAILOUT();
2012 
2013     __ compare32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2014 
2015     __ z_lgr(tmp, Z_RET);
2016     __ z_xilf(tmp, -1);
2017 
2018     // Restore values from callee saved registers so they are where the stub
2019     // expects them.
2020     __ lgr_if_needed(src, callee_saved_src);
2021     __ lgr_if_needed(src_pos, callee_saved_src_pos);
2022     __ lgr_if_needed(dst, callee_saved_dst);
2023     __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2024     __ lgr_if_needed(length, callee_saved_length);
2025 
2026     __ z_sr(length, tmp);
2027     __ z_ar(src_pos, tmp);
2028     __ z_ar(dst_pos, tmp);
2029     __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2030 
2031     __ bind(*stub->continuation());
2032     return;
2033   }
2034 
2035   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2036 
2037   int elem_size = type2aelembytes(basic_type);
2038   int shift_amount;
2039 
2040   switch (elem_size) {
2041     case 1 :
2042       shift_amount = 0;
2043       break;
2044     case 2 :
2045       shift_amount = 1;
2046       break;
2047     case 4 :
2048       shift_amount = 2;
2049       break;
2050     case 8 :
2051       shift_amount = 3;
2052       break;
2053     default:
2054       shift_amount = -1;
2055       ShouldNotReachHere();
2056   }
2057 
2058   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2059   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2060   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2061   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2062 
2063   // Length and pos's are all sign extended at this point on 64bit.
2064 
2065   // test for NULL
2066   if (flags & LIR_OpArrayCopy::src_null_check) {
2067     __ compareU64_and_branch(src, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2068   }
2069   if (flags & LIR_OpArrayCopy::dst_null_check) {
2070     __ compareU64_and_branch(dst, (intptr_t)0, Assembler::bcondZero, *stub->entry());
2071   }
2072 
2073   // Check if negative.
2074   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2075     __ compare32_and_branch(src_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2076   }
2077   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2078     __ compare32_and_branch(dst_pos, (intptr_t)0, Assembler::bcondLow, *stub->entry());
2079   }
2080 
2081   // If the compiler was not able to prove that exact type of the source or the destination
2082   // of the arraycopy is an array type, check at runtime if the source or the destination is
2083   // an instance type.
2084   if (flags & LIR_OpArrayCopy::type_check) {
2085     assert(Klass::_lh_neutral_value == 0, "or replace z_lt instructions");
2086 
2087     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2088       __ load_klass(tmp, dst);
2089       __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2090       __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2091     }
2092 
2093     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2094       __ load_klass(tmp, src);
2095       __ z_lt(tmp, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2096       __ branch_optimized(Assembler::bcondNotLow, *stub->entry());
2097     }
2098   }
2099 
2100   if (flags & LIR_OpArrayCopy::src_range_check) {
2101     __ z_la(tmp, Address(src_pos, length));
2102     __ z_cl(tmp, src_length_addr);
2103     __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2104   }
2105   if (flags & LIR_OpArrayCopy::dst_range_check) {
2106     __ z_la(tmp, Address(dst_pos, length));
2107     __ z_cl(tmp, dst_length_addr);
2108     __ branch_optimized(Assembler::bcondHigh, *stub->entry());
2109   }
2110 
2111   if (flags & LIR_OpArrayCopy::length_positive_check) {
2112     __ z_ltr(length, length);
2113     __ branch_optimized(Assembler::bcondNegative, *stub->entry());
2114   }
2115 
2116   // Stubs require 64 bit values.
2117   __ z_lgfr(src_pos, src_pos); // int -> long
2118   __ z_lgfr(dst_pos, dst_pos); // int -> long
2119   __ z_lgfr(length, length);   // int -> long
2120 
2121   if (flags & LIR_OpArrayCopy::type_check) {
2122     // We don't know the array types are compatible.
2123     if (basic_type != T_OBJECT) {
2124       // Simple test for basic type arrays.
2125       if (UseCompressedClassPointers) {
2126         __ z_l(tmp, src_klass_addr);
2127         __ z_c(tmp, dst_klass_addr);
2128       } else {
2129         __ z_lg(tmp, src_klass_addr);
2130         __ z_cg(tmp, dst_klass_addr);
2131       }
2132       __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2133     } else {
2134       // For object arrays, if src is a sub class of dst then we can
2135       // safely do the copy.
2136       NearLabel cont, slow;
2137       Register src_klass = Z_R1_scratch;
2138       Register dst_klass = Z_R10;
2139 
2140       __ load_klass(src_klass, src);
2141       __ load_klass(dst_klass, dst);
2142 
2143       __ check_klass_subtype_fast_path(src_klass, dst_klass, tmp, &cont, &slow, NULL);
2144 
2145       store_parameter(src_klass, 0); // sub
2146       store_parameter(dst_klass, 1); // super
2147       emit_call_c(Runtime1::entry_for (Runtime1::slow_subtype_check_id));
2148       CHECK_BAILOUT();
2149       // Sets condition code 0 for match (2 otherwise).
2150       __ branch_optimized(Assembler::bcondEqual, cont);
2151 
2152       __ bind(slow);
2153 
2154       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2155       if (copyfunc_addr != NULL) { // use stub if available
2156         // Src is not a sub class of dst so we have to do a
2157         // per-element check.
2158 
2159         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2160         if ((flags & mask) != mask) {
2161           // Check that at least both of them object arrays.
2162           assert(flags & mask, "one of the two should be known to be an object array");
2163 
2164           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2165             __ load_klass(tmp, src);
2166           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2167             __ load_klass(tmp, dst);
2168           }
2169           Address klass_lh_addr(tmp, Klass::layout_helper_offset());
2170           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2171           __ load_const_optimized(Z_R1_scratch, objArray_lh);
2172           __ z_c(Z_R1_scratch, klass_lh_addr);
2173           __ branch_optimized(Assembler::bcondNotEqual, *stub->entry());
2174         }
2175 
2176         // Save outgoing arguments in callee saved registers (C convention) in case
2177         // a call to System.arraycopy is needed.
2178         Register callee_saved_src     = Z_R10;
2179         Register callee_saved_src_pos = Z_R11;
2180         Register callee_saved_dst     = Z_R12;
2181         Register callee_saved_dst_pos = Z_R13;
2182         Register callee_saved_length  = Z_ARG5; // Z_ARG5 == Z_R6 is callee saved.
2183 
2184         __ lgr_if_needed(callee_saved_src, src);
2185         __ lgr_if_needed(callee_saved_src_pos, src_pos);
2186         __ lgr_if_needed(callee_saved_dst, dst);
2187         __ lgr_if_needed(callee_saved_dst_pos, dst_pos);
2188         __ lgr_if_needed(callee_saved_length, length);
2189 
2190         __ z_llgfr(length, length); // Higher 32bits must be null.
2191 
2192         __ z_sllg(Z_ARG1, src_pos, shift_amount); // index -> byte offset
2193         __ z_sllg(Z_ARG2, dst_pos, shift_amount); // index -> byte offset
2194 
2195         __ z_la(Z_ARG1, Address(src, Z_ARG1, arrayOopDesc::base_offset_in_bytes(basic_type)));
2196         assert_different_registers(Z_ARG1, dst, dst_pos, length);
2197         __ z_la(Z_ARG2, Address(dst, Z_ARG2, arrayOopDesc::base_offset_in_bytes(basic_type)));
2198         assert_different_registers(Z_ARG2, dst, length);
2199 
2200         __ z_lgr(Z_ARG3, length);
2201         assert_different_registers(Z_ARG3, dst);
2202 
2203         __ load_klass(Z_ARG5, dst);
2204         __ z_lg(Z_ARG5, Address(Z_ARG5, ObjArrayKlass::element_klass_offset()));
2205         __ z_lg(Z_ARG4, Address(Z_ARG5, Klass::super_check_offset_offset()));
2206         emit_call_c(copyfunc_addr);
2207         CHECK_BAILOUT();
2208 
2209 #ifndef PRODUCT
2210         if (PrintC1Statistics) {
2211           NearLabel failed;
2212           __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondNotEqual, failed);
2213           __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_cnt);
2214           __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2215           __ bind(failed);
2216         }
2217 #endif
2218 
2219         __ compareU32_and_branch(Z_RET, (intptr_t)0, Assembler::bcondEqual, *stub->continuation());
2220 
2221 #ifndef PRODUCT
2222         if (PrintC1Statistics) {
2223           __ load_const_optimized(Z_R1_scratch, (address)&Runtime1::_arraycopy_checkcast_attempt_cnt);
2224           __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2225         }
2226 #endif
2227 
2228         __ z_lgr(tmp, Z_RET);
2229         __ z_xilf(tmp, -1);
2230 
2231         // Restore previously spilled arguments
2232         __ lgr_if_needed(src, callee_saved_src);
2233         __ lgr_if_needed(src_pos, callee_saved_src_pos);
2234         __ lgr_if_needed(dst, callee_saved_dst);
2235         __ lgr_if_needed(dst_pos, callee_saved_dst_pos);
2236         __ lgr_if_needed(length, callee_saved_length);
2237 
2238         __ z_sr(length, tmp);
2239         __ z_ar(src_pos, tmp);
2240         __ z_ar(dst_pos, tmp);
2241       }
2242 
2243       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2244 
2245       __ bind(cont);
2246     }
2247   }
2248 
2249 #ifdef ASSERT
2250   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2251     // Sanity check the known type with the incoming class. For the
2252     // primitive case the types must match exactly with src.klass and
2253     // dst.klass each exactly matching the default type. For the
2254     // object array case, if no type check is needed then either the
2255     // dst type is exactly the expected type and the src type is a
2256     // subtype which we can't check or src is the same array as dst
2257     // but not necessarily exactly of type default_type.
2258     NearLabel known_ok, halt;
2259     metadata2reg(default_type->constant_encoding(), tmp);
2260     if (UseCompressedClassPointers) {
2261       __ encode_klass_not_null(tmp);
2262     }
2263 
2264     if (basic_type != T_OBJECT) {
2265       if (UseCompressedClassPointers)         { __ z_c (tmp, dst_klass_addr); }
2266       else                                    { __ z_cg(tmp, dst_klass_addr); }
2267       __ branch_optimized(Assembler::bcondNotEqual, halt);
2268       if (UseCompressedClassPointers)         { __ z_c (tmp, src_klass_addr); }
2269       else                                    { __ z_cg(tmp, src_klass_addr); }
2270       __ branch_optimized(Assembler::bcondEqual, known_ok);
2271     } else {
2272       if (UseCompressedClassPointers)         { __ z_c (tmp, dst_klass_addr); }
2273       else                                    { __ z_cg(tmp, dst_klass_addr); }
2274       __ branch_optimized(Assembler::bcondEqual, known_ok);
2275       __ compareU64_and_branch(src, dst, Assembler::bcondEqual, known_ok);
2276     }
2277     __ bind(halt);
2278     __ stop("incorrect type information in arraycopy");
2279     __ bind(known_ok);
2280   }
2281 #endif
2282 
2283 #ifndef PRODUCT
2284   if (PrintC1Statistics) {
2285     __ load_const_optimized(Z_R1_scratch, Runtime1::arraycopy_count_address(basic_type));
2286     __ add2mem_32(Address(Z_R1_scratch), 1, Z_R0_scratch);
2287   }
2288 #endif
2289 
2290   __ z_sllg(tmp, src_pos, shift_amount); // index -> byte offset
2291   __ z_sllg(Z_R1_scratch, dst_pos, shift_amount); // index -> byte offset
2292 
2293   assert_different_registers(Z_ARG1, dst, dst_pos, length);
2294   __ z_la(Z_ARG1, Address(src, tmp, arrayOopDesc::base_offset_in_bytes(basic_type)));
2295   assert_different_registers(Z_ARG2, length);
2296   __ z_la(Z_ARG2, Address(dst, Z_R1_scratch, arrayOopDesc::base_offset_in_bytes(basic_type)));
2297   __ lgr_if_needed(Z_ARG3, length);
2298 
2299   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2300   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2301   const char *name;
2302   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2303   __ call_VM_leaf(entry);
2304 
2305   __ bind(*stub->continuation());
2306 }
2307 
2308 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2309   if (dest->is_single_cpu()) {
2310     if (left->type() == T_OBJECT) {
2311       switch (code) {
2312         case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2313         case lir_shr:  __ z_srag (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2314         case lir_ushr: __ z_srlg (dest->as_register(), left->as_register(), 0, count->as_register()); break;
2315         default: ShouldNotReachHere();
2316       }
2317     } else {
2318       assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2319       Register masked_count = Z_R1_scratch;
2320       __ z_lr(masked_count, count->as_register());
2321       __ z_nill(masked_count, 31);
2322       switch (code) {
2323         case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), 0, masked_count); break;
2324         case lir_shr:  __ z_sra  (dest->as_register(), 0, masked_count); break;
2325         case lir_ushr: __ z_srl  (dest->as_register(), 0, masked_count); break;
2326         default: ShouldNotReachHere();
2327       }
2328     }
2329   } else {
2330     switch (code) {
2331       case lir_shl:  __ z_sllg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2332       case lir_shr:  __ z_srag (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2333       case lir_ushr: __ z_srlg (dest->as_register_lo(), left->as_register_lo(), 0, count->as_register()); break;
2334       default: ShouldNotReachHere();
2335     }
2336   }
2337 }
2338 
2339 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2340   if (left->type() == T_OBJECT) {
2341     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2342     Register l = left->as_register();
2343     Register d = dest->as_register_lo();
2344     switch (code) {
2345       case lir_shl:  __ z_sllg (d, l, count); break;
2346       case lir_shr:  __ z_srag (d, l, count); break;
2347       case lir_ushr: __ z_srlg (d, l, count); break;
2348       default: ShouldNotReachHere();
2349     }
2350     return;
2351   }
2352   if (dest->is_single_cpu()) {
2353     assert(code == lir_shl || left == dest, "left and dest must be equal for 2 operand form right shifts");
2354     count = count & 0x1F; // Java spec
2355     switch (code) {
2356       case lir_shl:  __ z_sllg (dest->as_register(), left->as_register(), count); break;
2357       case lir_shr:  __ z_sra  (dest->as_register(), count); break;
2358       case lir_ushr: __ z_srl  (dest->as_register(), count); break;
2359       default: ShouldNotReachHere();
2360     }
2361   } else if (dest->is_double_cpu()) {
2362     count = count & 63; // Java spec
2363     Register l = left->as_pointer_register();
2364     Register d = dest->as_pointer_register();
2365     switch (code) {
2366       case lir_shl:  __ z_sllg (d, l, count); break;
2367       case lir_shr:  __ z_srag (d, l, count); break;
2368       case lir_ushr: __ z_srlg (d, l, count); break;
2369       default: ShouldNotReachHere();
2370     }
2371   } else {
2372     ShouldNotReachHere();
2373   }
2374 }
2375 
2376 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2377   if (op->init_check()) {
2378     // Make sure klass is initialized & doesn't have finalizer.
2379     const int state_offset = in_bytes(InstanceKlass::init_state_offset());
2380     Register iklass = op->klass()->as_register();
2381     add_debug_info_for_null_check_here(op->stub()->info());
2382     if (Immediate::is_uimm12(state_offset)) {
2383       __ z_cli(state_offset, iklass, InstanceKlass::fully_initialized);
2384     } else {
2385       __ z_cliy(state_offset, iklass, InstanceKlass::fully_initialized);
2386     }
2387     __ branch_optimized(Assembler::bcondNotEqual, *op->stub()->entry()); // Use long branch, because slow_case might be far.
2388   }
2389   __ allocate_object(op->obj()->as_register(),
2390                      op->tmp1()->as_register(),
2391                      op->tmp2()->as_register(),
2392                      op->header_size(),
2393                      op->object_size(),
2394                      op->klass()->as_register(),
2395                      *op->stub()->entry());
2396   __ bind(*op->stub()->continuation());
2397   __ verify_oop(op->obj()->as_register());
2398 }
2399 
2400 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2401   Register len = op->len()->as_register();
2402   __ move_reg_if_needed(len, T_LONG, len, T_INT); // sign extend
2403 
2404   if (UseSlowPath ||
2405       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2406       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2407     __ z_brul(*op->stub()->entry());
2408   } else {
2409     __ allocate_array(op->obj()->as_register(),
2410                       op->len()->as_register(),
2411                       op->tmp1()->as_register(),
2412                       op->tmp2()->as_register(),
2413                       arrayOopDesc::header_size(op->type()),
2414                       type2aelembytes(op->type()),
2415                       op->klass()->as_register(),
2416                       *op->stub()->entry());
2417   }
2418   __ bind(*op->stub()->continuation());
2419 }
2420 
2421 void LIR_Assembler::type_profile_helper(Register mdo, ciMethodData *md, ciProfileData *data,
2422                                         Register recv, Register tmp1, Label* update_done) {
2423   uint i;
2424   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2425     Label next_test;
2426     // See if the receiver is receiver[n].
2427     Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2428     __ z_cg(recv, receiver_addr);
2429     __ z_brne(next_test);
2430     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
2431     __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2432     __ branch_optimized(Assembler::bcondAlways, *update_done);
2433     __ bind(next_test);
2434   }
2435 
2436   // Didn't find receiver; find next empty slot and fill it in.
2437   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2438     Label next_test;
2439     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
2440     __ z_ltg(Z_R0_scratch, recv_addr);
2441     __ z_brne(next_test);
2442     __ z_stg(recv, recv_addr);
2443     __ load_const_optimized(tmp1, DataLayout::counter_increment);
2444     __ z_stg(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)), mdo);
2445     __ branch_optimized(Assembler::bcondAlways, *update_done);
2446     __ bind(next_test);
2447   }
2448 }
2449 
2450 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2451                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2452   Unimplemented();
2453 }
2454 
2455 void LIR_Assembler::store_parameter(Register r, int param_num) {
2456   assert(param_num >= 0, "invalid num");
2457   int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2458   assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2459   __ z_stg(r, offset_in_bytes, Z_SP);
2460 }
2461 
2462 void LIR_Assembler::store_parameter(jint c, int param_num) {
2463   assert(param_num >= 0, "invalid num");
2464   int offset_in_bytes = param_num * BytesPerWord + FrameMap::first_available_sp_in_frame;
2465   assert(offset_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2466   __ store_const(Address(Z_SP, offset_in_bytes), c, Z_R1_scratch, true);
2467 }
2468 
2469 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2470   // We always need a stub for the failure case.
2471   CodeStub* stub = op->stub();
2472   Register obj = op->object()->as_register();
2473   Register k_RInfo = op->tmp1()->as_register();
2474   Register klass_RInfo = op->tmp2()->as_register();
2475   Register dst = op->result_opr()->as_register();
2476   Register Rtmp1 = Z_R1_scratch;
2477   ciKlass* k = op->klass();
2478 
2479   assert(!op->tmp3()->is_valid(), "tmp3's not needed");
2480 
2481   // Check if it needs to be profiled.
2482   ciMethodData* md = NULL;
2483   ciProfileData* data = NULL;
2484 
2485   if (op->should_profile()) {
2486     ciMethod* method = op->profiled_method();
2487     assert(method != NULL, "Should have method");
2488     int bci = op->profiled_bci();
2489     md = method->method_data_or_null();
2490     assert(md != NULL, "Sanity");
2491     data = md->bci_to_data(bci);
2492     assert(data != NULL,                "need data for type check");
2493     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2494   }
2495 
2496   // Temp operands do not overlap with inputs, if this is their last
2497   // use (end of range is exclusive), so a register conflict is possible.
2498   if (obj == k_RInfo) {
2499     k_RInfo = dst;
2500   } else if (obj == klass_RInfo) {
2501     klass_RInfo = dst;
2502   }
2503   assert_different_registers(obj, k_RInfo, klass_RInfo);
2504 
2505   if (op->should_profile()) {
2506     NearLabel not_null;
2507     __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2508     // Object is null; update MDO and exit.
2509     Register mdo = klass_RInfo;
2510     metadata2reg(md->constant_encoding(), mdo);
2511     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2512     int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2513     __ or2mem_8(data_addr, header_bits);
2514     __ branch_optimized(Assembler::bcondAlways, *obj_is_null);
2515     __ bind(not_null);
2516   } else {
2517     __ compareU64_and_branch(obj, (intptr_t) 0, Assembler::bcondEqual, *obj_is_null);
2518   }
2519 
2520   NearLabel profile_cast_failure, profile_cast_success;
2521   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
2522   Label *success_target = op->should_profile() ? &profile_cast_success : success;
2523 
2524   // Patching may screw with our temporaries on sparc,
2525   // so let's do it before loading the class.
2526   if (k->is_loaded()) {
2527     metadata2reg(k->constant_encoding(), k_RInfo);
2528   } else {
2529     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2530   }
2531   assert(obj != k_RInfo, "must be different");
2532 
2533   __ verify_oop(obj);
2534 
2535   // Get object class.
2536   // Not a safepoint as obj null check happens earlier.
2537   if (op->fast_check()) {
2538     if (UseCompressedClassPointers) {
2539       __ load_klass(klass_RInfo, obj);
2540       __ compareU64_and_branch(k_RInfo, klass_RInfo, Assembler::bcondNotEqual, *failure_target);
2541     } else {
2542       __ z_cg(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
2543       __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2544     }
2545     // Successful cast, fall through to profile or jump.
2546   } else {
2547     bool need_slow_path = !k->is_loaded() ||
2548                           ((int) k->super_check_offset() == in_bytes(Klass::secondary_super_cache_offset()));
2549     intptr_t super_check_offset = k->is_loaded() ? k->super_check_offset() : -1L;
2550     __ load_klass(klass_RInfo, obj);
2551     // Perform the fast part of the checking logic.
2552     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1,
2553                                      (need_slow_path ? success_target : NULL),
2554                                      failure_target, NULL,
2555                                      RegisterOrConstant(super_check_offset));
2556     if (need_slow_path) {
2557       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2558       address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2559       store_parameter(klass_RInfo, 0); // sub
2560       store_parameter(k_RInfo, 1);     // super
2561       emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2562       CHECK_BAILOUT();
2563       __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2564       // Fall through to success case.
2565     }
2566   }
2567 
2568   if (op->should_profile()) {
2569     Register mdo = klass_RInfo, recv = k_RInfo;
2570     assert_different_registers(obj, mdo, recv);
2571     __ bind(profile_cast_success);
2572     metadata2reg(md->constant_encoding(), mdo);
2573     __ load_klass(recv, obj);
2574     type_profile_helper(mdo, md, data, recv, Rtmp1, success);
2575     __ branch_optimized(Assembler::bcondAlways, *success);
2576 
2577     __ bind(profile_cast_failure);
2578     metadata2reg(md->constant_encoding(), mdo);
2579     __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2580     __ branch_optimized(Assembler::bcondAlways, *failure);
2581   } else {
2582     __ branch_optimized(Assembler::bcondAlways, *success);
2583   }
2584 }
2585 
2586 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2587   LIR_Code code = op->code();
2588   if (code == lir_store_check) {
2589     Register value = op->object()->as_register();
2590     Register array = op->array()->as_register();
2591     Register k_RInfo = op->tmp1()->as_register();
2592     Register klass_RInfo = op->tmp2()->as_register();
2593     Register Rtmp1 = Z_R1_scratch;
2594 
2595     CodeStub* stub = op->stub();
2596 
2597     // Check if it needs to be profiled.
2598     ciMethodData* md = NULL;
2599     ciProfileData* data = NULL;
2600 
2601     assert_different_registers(value, k_RInfo, klass_RInfo);
2602 
2603     if (op->should_profile()) {
2604       ciMethod* method = op->profiled_method();
2605       assert(method != NULL, "Should have method");
2606       int bci = op->profiled_bci();
2607       md = method->method_data_or_null();
2608       assert(md != NULL, "Sanity");
2609       data = md->bci_to_data(bci);
2610       assert(data != NULL,                "need data for type check");
2611       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2612     }
2613     NearLabel profile_cast_success, profile_cast_failure, done;
2614     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
2615     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
2616 
2617     if (op->should_profile()) {
2618       NearLabel not_null;
2619       __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondNotEqual, not_null);
2620       // Object is null; update MDO and exit.
2621       Register mdo = klass_RInfo;
2622       metadata2reg(md->constant_encoding(), mdo);
2623       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset()));
2624       int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant());
2625       __ or2mem_8(data_addr, header_bits);
2626       __ branch_optimized(Assembler::bcondAlways, done);
2627       __ bind(not_null);
2628     } else {
2629       __ compareU64_and_branch(value, (intptr_t) 0, Assembler::bcondEqual, done);
2630     }
2631 
2632     add_debug_info_for_null_check_here(op->info_for_exception());
2633     __ load_klass(k_RInfo, array);
2634     __ load_klass(klass_RInfo, value);
2635 
2636     // Get instance klass (it's already uncompressed).
2637     __ z_lg(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
2638     // Perform the fast part of the checking logic.
2639     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
2640     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2641     address a = Runtime1::entry_for (Runtime1::slow_subtype_check_id);
2642     store_parameter(klass_RInfo, 0); // sub
2643     store_parameter(k_RInfo, 1);     // super
2644     emit_call_c(a); // Sets condition code 0 for match (2 otherwise).
2645     CHECK_BAILOUT();
2646     __ branch_optimized(Assembler::bcondNotEqual, *failure_target);
2647     // Fall through to success case.
2648 
2649     if (op->should_profile()) {
2650       Register mdo = klass_RInfo, recv = k_RInfo;
2651       assert_different_registers(value, mdo, recv);
2652       __ bind(profile_cast_success);
2653       metadata2reg(md->constant_encoding(), mdo);
2654       __ load_klass(recv, value);
2655       type_profile_helper(mdo, md, data, recv, Rtmp1, &done);
2656       __ branch_optimized(Assembler::bcondAlways, done);
2657 
2658       __ bind(profile_cast_failure);
2659       metadata2reg(md->constant_encoding(), mdo);
2660       __ add2mem_64(Address(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())), -(int)DataLayout::counter_increment, Rtmp1);
2661       __ branch_optimized(Assembler::bcondAlways, *stub->entry());
2662     }
2663 
2664     __ bind(done);
2665   } else {
2666     if (code == lir_checkcast) {
2667       Register obj = op->object()->as_register();
2668       Register dst = op->result_opr()->as_register();
2669       NearLabel success;
2670       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
2671       __ bind(success);
2672       __ lgr_if_needed(dst, obj);
2673     } else {
2674       if (code == lir_instanceof) {
2675         Register obj = op->object()->as_register();
2676         Register dst = op->result_opr()->as_register();
2677         NearLabel success, failure, done;
2678         emit_typecheck_helper(op, &success, &failure, &failure);
2679         __ bind(failure);
2680         __ clear_reg(dst);
2681         __ branch_optimized(Assembler::bcondAlways, done);
2682         __ bind(success);
2683         __ load_const_optimized(dst, 1);
2684         __ bind(done);
2685       } else {
2686         ShouldNotReachHere();
2687       }
2688     }
2689   }
2690 }
2691 
2692 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2693   Register addr = op->addr()->as_pointer_register();
2694   Register t1_cmp = Z_R1_scratch;
2695   if (op->code() == lir_cas_long) {
2696     assert(VM_Version::supports_cx8(), "wrong machine");
2697     Register cmp_value_lo = op->cmp_value()->as_register_lo();
2698     Register new_value_lo = op->new_value()->as_register_lo();
2699     __ z_lgr(t1_cmp, cmp_value_lo);
2700     // Perform the compare and swap operation.
2701     __ z_csg(t1_cmp, new_value_lo, 0, addr);
2702   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2703     Register cmp_value = op->cmp_value()->as_register();
2704     Register new_value = op->new_value()->as_register();
2705     if (op->code() == lir_cas_obj) {
2706       if (UseCompressedOops) {
2707                  t1_cmp = op->tmp1()->as_register();
2708         Register t2_new = op->tmp2()->as_register();
2709         assert_different_registers(cmp_value, new_value, addr, t1_cmp, t2_new);
2710         __ oop_encoder(t1_cmp, cmp_value, true /*maybe null*/);
2711         __ oop_encoder(t2_new, new_value, true /*maybe null*/);
2712         __ z_cs(t1_cmp, t2_new, 0, addr);
2713       } else {
2714         __ z_lgr(t1_cmp, cmp_value);
2715         __ z_csg(t1_cmp, new_value, 0, addr);
2716       }
2717     } else {
2718       __ z_lr(t1_cmp, cmp_value);
2719       __ z_cs(t1_cmp, new_value, 0, addr);
2720     }
2721   } else {
2722     ShouldNotReachHere(); // new lir_cas_??
2723   }
2724 }
2725 
2726 void LIR_Assembler::set_24bit_FPU() {
2727   ShouldNotCallThis(); // x86 only
2728 }
2729 
2730 void LIR_Assembler::reset_FPU() {
2731   ShouldNotCallThis(); // x86 only
2732 }
2733 
2734 void LIR_Assembler::breakpoint() {
2735   Unimplemented();
2736   //  __ breakpoint_trap();
2737 }
2738 
2739 void LIR_Assembler::push(LIR_Opr opr) {
2740   ShouldNotCallThis(); // unused
2741 }
2742 
2743 void LIR_Assembler::pop(LIR_Opr opr) {
2744   ShouldNotCallThis(); // unused
2745 }
2746 
2747 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2748   Address addr = frame_map()->address_for_monitor_lock(monitor_no);
2749   __ add2reg(dst_opr->as_register(), addr.disp(), addr.base());
2750 }
2751 
2752 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2753   Register obj = op->obj_opr()->as_register();  // May not be an oop.
2754   Register hdr = op->hdr_opr()->as_register();
2755   Register lock = op->lock_opr()->as_register();
2756   if (!UseFastLocking) {
2757     __ branch_optimized(Assembler::bcondAlways, *op->stub()->entry());
2758   } else if (op->code() == lir_lock) {
2759     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2760     // Add debug info for NullPointerException only if one is possible.
2761     if (op->info() != NULL) {
2762       add_debug_info_for_null_check_here(op->info());
2763     }
2764     __ lock_object(hdr, obj, lock, *op->stub()->entry());
2765     // done
2766   } else if (op->code() == lir_unlock) {
2767     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2768     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2769   } else {
2770     ShouldNotReachHere();
2771   }
2772   __ bind(*op->stub()->continuation());
2773 }
2774 
2775 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2776   ciMethod* method = op->profiled_method();
2777   int bci          = op->profiled_bci();
2778   ciMethod* callee = op->profiled_callee();
2779 
2780   // Update counter for all call types.
2781   ciMethodData* md = method->method_data_or_null();
2782   assert(md != NULL, "Sanity");
2783   ciProfileData* data = md->bci_to_data(bci);
2784   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2785   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2786   Register mdo  = op->mdo()->as_register();
2787   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2788   Register tmp1 = op->tmp1()->as_register_lo();
2789   metadata2reg(md->constant_encoding(), mdo);
2790 
2791   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2792   // Perform additional virtual call profiling for invokevirtual and
2793   // invokeinterface bytecodes
2794   if (op->should_profile_receiver_type()) {
2795     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2796     Register recv = op->recv()->as_register();
2797     assert_different_registers(mdo, tmp1, recv);
2798     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2799     ciKlass* known_klass = op->known_holder();
2800     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2801       // We know the type that will be seen at this call site; we can
2802       // statically update the MethodData* rather than needing to do
2803       // dynamic tests on the receiver type.
2804 
2805       // NOTE: we should probably put a lock around this search to
2806       // avoid collisions by concurrent compilations.
2807       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2808       uint i;
2809       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2810         ciKlass* receiver = vc_data->receiver(i);
2811         if (known_klass->equals(receiver)) {
2812           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2813           __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2814           return;
2815         }
2816       }
2817 
2818       // Receiver type not found in profile data. Select an empty slot.
2819 
2820       // Note that this is less efficient than it should be because it
2821       // always does a write to the receiver part of the
2822       // VirtualCallData rather than just the first time.
2823       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2824         ciKlass* receiver = vc_data->receiver(i);
2825         if (receiver == NULL) {
2826           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2827           metadata2reg(known_klass->constant_encoding(), tmp1);
2828           __ z_stg(tmp1, recv_addr);
2829           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2830           __ add2mem_64(data_addr, DataLayout::counter_increment, tmp1);
2831           return;
2832         }
2833       }
2834     } else {
2835       __ load_klass(recv, recv);
2836       NearLabel update_done;
2837       type_profile_helper(mdo, md, data, recv, tmp1, &update_done);
2838       // Receiver did not match any saved receiver and there is no empty row for it.
2839       // Increment total counter to indicate polymorphic case.
2840       __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2841       __ bind(update_done);
2842     }
2843   } else {
2844     // static call
2845     __ add2mem_64(counter_addr, DataLayout::counter_increment, tmp1);
2846   }
2847 }
2848 
2849 void LIR_Assembler::align_backward_branch_target() {
2850   __ align(OptoLoopAlignment);
2851 }
2852 
2853 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2854   ShouldNotCallThis(); // There are no delay slots on ZARCH_64.
2855 }
2856 
2857 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2858   // tmp must be unused
2859   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2860   assert(left->is_register(), "can only handle registers");
2861 
2862   if (left->is_single_cpu()) {
2863     __ z_lcr(dest->as_register(), left->as_register());
2864   } else if (left->is_single_fpu()) {
2865     __ z_lcebr(dest->as_float_reg(), left->as_float_reg());
2866   } else if (left->is_double_fpu()) {
2867     __ z_lcdbr(dest->as_double_reg(), left->as_double_reg());
2868   } else {
2869     assert(left->is_double_cpu(), "Must be a long");
2870     __ z_lcgr(dest->as_register_lo(), left->as_register_lo());
2871   }
2872 }
2873 
2874 void LIR_Assembler::fxch(int i) {
2875   ShouldNotCallThis(); // x86 only
2876 }
2877 
2878 void LIR_Assembler::fld(int i) {
2879   ShouldNotCallThis(); // x86 only
2880 }
2881 
2882 void LIR_Assembler::ffree(int i) {
2883   ShouldNotCallThis(); // x86 only
2884 }
2885 
2886 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2887                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2888   assert(!tmp->is_valid(), "don't need temporary");
2889   emit_call_c(dest);
2890   CHECK_BAILOUT();
2891   if (info != NULL) {
2892     add_call_info_here(info);
2893   }
2894 }
2895 
2896 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2897   ShouldNotCallThis(); // not needed on ZARCH_64
2898 }
2899 
2900 void LIR_Assembler::membar() {
2901   __ z_fence();
2902 }
2903 
2904 void LIR_Assembler::membar_acquire() {
2905   __ z_acquire();
2906 }
2907 
2908 void LIR_Assembler::membar_release() {
2909   __ z_release();
2910 }
2911 
2912 void LIR_Assembler::membar_loadload() {
2913   __ z_acquire();
2914 }
2915 
2916 void LIR_Assembler::membar_storestore() {
2917   __ z_release();
2918 }
2919 
2920 void LIR_Assembler::membar_loadstore() {
2921   __ z_acquire();
2922 }
2923 
2924 void LIR_Assembler::membar_storeload() {
2925   __ z_fence();
2926 }
2927 
2928 void LIR_Assembler::on_spin_wait() {
2929   Unimplemented();
2930 }
2931 
2932 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2933   assert(patch_code == lir_patch_none, "Patch code not supported");
2934   LIR_Address* addr = addr_opr->as_address_ptr();
2935   assert(addr->scale() == LIR_Address::times_1, "scaling unsupported");
2936   __ load_address(dest->as_pointer_register(), as_Address(addr));
2937 }
2938 
2939 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2940   ShouldNotCallThis(); // unused
2941 }
2942 
2943 #ifdef ASSERT
2944 // Emit run-time assertion.
2945 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2946   Unimplemented();
2947 }
2948 #endif
2949 
2950 void LIR_Assembler::peephole(LIR_List*) {
2951   // Do nothing for now.
2952 }
2953 
2954 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2955   assert(code == lir_xadd, "lir_xchg not supported");
2956   Address src_addr = as_Address(src->as_address_ptr());
2957   Register base = src_addr.base();
2958   intptr_t disp = src_addr.disp();
2959   if (src_addr.index()->is_valid()) {
2960     // LAA and LAAG do not support index register.
2961     __ load_address(Z_R1_scratch, src_addr);
2962     base = Z_R1_scratch;
2963     disp = 0;
2964   }
2965   if (data->type() == T_INT) {
2966     __ z_laa(dest->as_register(), data->as_register(), disp, base);
2967   } else if (data->type() == T_LONG) {
2968     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
2969     __ z_laag(dest->as_register_lo(), data->as_register_lo(), disp, base);
2970   } else {
2971     ShouldNotReachHere();
2972   }
2973 }
2974 
2975 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2976   Register obj = op->obj()->as_register();
2977   Register tmp1 = op->tmp()->as_pointer_register();
2978   Register tmp2 = Z_R1_scratch;
2979   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2980   ciKlass* exact_klass = op->exact_klass();
2981   intptr_t current_klass = op->current_klass();
2982   bool not_null = op->not_null();
2983   bool no_conflict = op->no_conflict();
2984 
2985   Label update, next, none, null_seen, init_klass;
2986 
2987   bool do_null = !not_null;
2988   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2989   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2990 
2991   assert(do_null || do_update, "why are we here?");
2992   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2993 
2994   __ verify_oop(obj);
2995 
2996   if (do_null || tmp1 != obj DEBUG_ONLY(|| true)) {
2997     __ z_ltgr(tmp1, obj);
2998   }
2999   if (do_null) {
3000     __ z_brnz(update);
3001     if (!TypeEntries::was_null_seen(current_klass)) {
3002       __ z_lg(tmp1, mdo_addr);
3003       __ z_oill(tmp1, TypeEntries::null_seen);
3004       __ z_stg(tmp1, mdo_addr);
3005     }
3006     if (do_update) {
3007       __ z_bru(next);
3008     }
3009   } else {
3010     __ asm_assert_ne("unexpect null obj", __LINE__);
3011   }
3012 
3013   __ bind(update);
3014 
3015   if (do_update) {
3016 #ifdef ASSERT
3017     if (exact_klass != NULL) {
3018       __ load_klass(tmp1, tmp1);
3019       metadata2reg(exact_klass->constant_encoding(), tmp2);
3020       __ z_cgr(tmp1, tmp2);
3021       __ asm_assert_eq("exact klass and actual klass differ", __LINE__);
3022     }
3023 #endif
3024 
3025     Label do_update;
3026     __ z_lg(tmp2, mdo_addr);
3027 
3028     if (!no_conflict) {
3029       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3030         if (exact_klass != NULL) {
3031           metadata2reg(exact_klass->constant_encoding(), tmp1);
3032         } else {
3033           __ load_klass(tmp1, tmp1);
3034         }
3035 
3036         // Klass seen before: nothing to do (regardless of unknown bit).
3037         __ z_lgr(Z_R0_scratch, tmp2);
3038         assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3039         __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3040         __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3041 
3042         // Already unknown: Nothing to do anymore.
3043         __ z_tmll(tmp2, TypeEntries::type_unknown);
3044         __ z_brc(Assembler::bcondAllOne, next);
3045 
3046         if (TypeEntries::is_type_none(current_klass)) {
3047           __ z_lgr(Z_R0_scratch, tmp2);
3048           assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3049           __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3050           __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, init_klass);
3051         }
3052       } else {
3053         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3054                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3055 
3056         // Already unknown: Nothing to do anymore.
3057         __ z_tmll(tmp2, TypeEntries::type_unknown);
3058         __ z_brc(Assembler::bcondAllOne, next);
3059       }
3060 
3061       // Different than before. Cannot keep accurate profile.
3062       __ z_oill(tmp2, TypeEntries::type_unknown);
3063       __ z_bru(do_update);
3064     } else {
3065       // There's a single possible klass at this profile point.
3066       assert(exact_klass != NULL, "should be");
3067       if (TypeEntries::is_type_none(current_klass)) {
3068         metadata2reg(exact_klass->constant_encoding(), tmp1);
3069         __ z_lgr(Z_R0_scratch, tmp2);
3070         assert(Immediate::is_uimm(~TypeEntries::type_klass_mask, 16), "or change following instruction");
3071         __ z_nill(Z_R0_scratch, TypeEntries::type_klass_mask & 0xFFFF);
3072         __ compareU64_and_branch(Z_R0_scratch, tmp1, Assembler::bcondEqual, next);
3073 #ifdef ASSERT
3074         {
3075           Label ok;
3076           __ z_lgr(Z_R0_scratch, tmp2);
3077           assert(Immediate::is_uimm(~TypeEntries::type_mask, 16), "or change following instruction");
3078           __ z_nill(Z_R0_scratch, TypeEntries::type_mask & 0xFFFF);
3079           __ compareU64_and_branch(Z_R0_scratch, (intptr_t)0, Assembler::bcondEqual, ok);
3080           __ stop("unexpected profiling mismatch");
3081           __ bind(ok);
3082         }
3083 #endif
3084 
3085       } else {
3086         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3087                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3088 
3089         // Already unknown: Nothing to do anymore.
3090         __ z_tmll(tmp2, TypeEntries::type_unknown);
3091         __ z_brc(Assembler::bcondAllOne, next);
3092         __ z_oill(tmp2, TypeEntries::type_unknown);
3093         __ z_bru(do_update);
3094       }
3095     }
3096 
3097     __ bind(init_klass);
3098     // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3099     __ z_ogr(tmp2, tmp1);
3100 
3101     __ bind(do_update);
3102     __ z_stg(tmp2, mdo_addr);
3103 
3104     __ bind(next);
3105   }
3106 }
3107 
3108 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3109   assert(op->crc()->is_single_cpu(), "crc must be register");
3110   assert(op->val()->is_single_cpu(), "byte value must be register");
3111   assert(op->result_opr()->is_single_cpu(), "result must be register");
3112   Register crc = op->crc()->as_register();
3113   Register val = op->val()->as_register();
3114   Register res = op->result_opr()->as_register();
3115 
3116   assert_different_registers(val, crc, res);
3117 
3118   __ load_const_optimized(res, StubRoutines::crc_table_addr());
3119   __ kernel_crc32_singleByteReg(crc, val, res, true);
3120   __ z_lgfr(res, crc);
3121 }
3122 
3123 #undef __