1 /*
   2  * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/disassembler.hpp"
  30 #include "gc/shared/barrierSet.hpp"
  31 #include "gc/shared/barrierSetAssembler.hpp"
  32 #include "gc/shared/collectedHeap.inline.hpp"
  33 #include "interpreter/interpreter.hpp"
  34 #include "memory/resourceArea.hpp"
  35 #include "memory/universe.hpp"
  36 #include "oops/accessDecorators.hpp"
  37 #include "oops/klass.inline.hpp"
  38 #include "prims/methodHandles.hpp"
  39 #include "runtime/biasedLocking.hpp"
  40 #include "runtime/flags/flagSetting.hpp"
  41 #include "runtime/interfaceSupport.inline.hpp"
  42 #include "runtime/objectMonitor.hpp"
  43 #include "runtime/os.hpp"
  44 #include "runtime/safepoint.hpp"
  45 #include "runtime/safepointMechanism.hpp"
  46 #include "runtime/sharedRuntime.hpp"
  47 #include "runtime/stubRoutines.hpp"
  48 #include "runtime/thread.hpp"
  49 #include "utilities/macros.hpp"
  50 #include "crc32c.h"
  51 #ifdef COMPILER2
  52 #include "opto/intrinsicnode.hpp"
  53 #endif
  54 
  55 #ifdef PRODUCT
  56 #define BLOCK_COMMENT(str) /* nothing */
  57 #define STOP(error) stop(error)
  58 #else
  59 #define BLOCK_COMMENT(str) block_comment(str)
  60 #define STOP(error) block_comment(error); stop(error)
  61 #endif
  62 
  63 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  64 
  65 #ifdef ASSERT
  66 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  67 #endif
  68 
  69 static Assembler::Condition reverse[] = {
  70     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  71     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  72     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  73     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  74     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  75     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  76     Assembler::above          /* belowEqual    = 0x6 */ ,
  77     Assembler::belowEqual     /* above         = 0x7 */ ,
  78     Assembler::positive       /* negative      = 0x8 */ ,
  79     Assembler::negative       /* positive      = 0x9 */ ,
  80     Assembler::noParity       /* parity        = 0xa */ ,
  81     Assembler::parity         /* noParity      = 0xb */ ,
  82     Assembler::greaterEqual   /* less          = 0xc */ ,
  83     Assembler::less           /* greaterEqual  = 0xd */ ,
  84     Assembler::greater        /* lessEqual     = 0xe */ ,
  85     Assembler::lessEqual      /* greater       = 0xf, */
  86 
  87 };
  88 
  89 
  90 // Implementation of MacroAssembler
  91 
  92 // First all the versions that have distinct versions depending on 32/64 bit
  93 // Unless the difference is trivial (1 line or so).
  94 
  95 #ifndef _LP64
  96 
  97 // 32bit versions
  98 
  99 Address MacroAssembler::as_Address(AddressLiteral adr) {
 100   return Address(adr.target(), adr.rspec());
 101 }
 102 
 103 Address MacroAssembler::as_Address(ArrayAddress adr) {
 104   return Address::make_array(adr);
 105 }
 106 
 107 void MacroAssembler::call_VM_leaf_base(address entry_point,
 108                                        int number_of_arguments) {
 109   call(RuntimeAddress(entry_point));
 110   increment(rsp, number_of_arguments * wordSize);
 111 }
 112 
 113 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 114   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 115 }
 116 
 117 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 118   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 119 }
 120 
 121 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
 122   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 123 }
 124 
 125 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
 126   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 127 }
 128 
 129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 130   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 131   bs->obj_equals(this, src1, obj);
 132 }
 133 
 134 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 135   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 136   bs->obj_equals(this, src1, obj);
 137 }
 138 
 139 void MacroAssembler::extend_sign(Register hi, Register lo) {
 140   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 141   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 142     cdql();
 143   } else {
 144     movl(hi, lo);
 145     sarl(hi, 31);
 146   }
 147 }
 148 
 149 void MacroAssembler::jC2(Register tmp, Label& L) {
 150   // set parity bit if FPU flag C2 is set (via rax)
 151   save_rax(tmp);
 152   fwait(); fnstsw_ax();
 153   sahf();
 154   restore_rax(tmp);
 155   // branch
 156   jcc(Assembler::parity, L);
 157 }
 158 
 159 void MacroAssembler::jnC2(Register tmp, Label& L) {
 160   // set parity bit if FPU flag C2 is set (via rax)
 161   save_rax(tmp);
 162   fwait(); fnstsw_ax();
 163   sahf();
 164   restore_rax(tmp);
 165   // branch
 166   jcc(Assembler::noParity, L);
 167 }
 168 
 169 // 32bit can do a case table jump in one instruction but we no longer allow the base
 170 // to be installed in the Address class
 171 void MacroAssembler::jump(ArrayAddress entry) {
 172   jmp(as_Address(entry));
 173 }
 174 
 175 // Note: y_lo will be destroyed
 176 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 177   // Long compare for Java (semantics as described in JVM spec.)
 178   Label high, low, done;
 179 
 180   cmpl(x_hi, y_hi);
 181   jcc(Assembler::less, low);
 182   jcc(Assembler::greater, high);
 183   // x_hi is the return register
 184   xorl(x_hi, x_hi);
 185   cmpl(x_lo, y_lo);
 186   jcc(Assembler::below, low);
 187   jcc(Assembler::equal, done);
 188 
 189   bind(high);
 190   xorl(x_hi, x_hi);
 191   increment(x_hi);
 192   jmp(done);
 193 
 194   bind(low);
 195   xorl(x_hi, x_hi);
 196   decrementl(x_hi);
 197 
 198   bind(done);
 199 }
 200 
 201 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 202     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 203 }
 204 
 205 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 206   // leal(dst, as_Address(adr));
 207   // see note in movl as to why we must use a move
 208   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 209 }
 210 
 211 void MacroAssembler::leave() {
 212   mov(rsp, rbp);
 213   pop(rbp);
 214 }
 215 
 216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 217   // Multiplication of two Java long values stored on the stack
 218   // as illustrated below. Result is in rdx:rax.
 219   //
 220   // rsp ---> [  ??  ] \               \
 221   //            ....    | y_rsp_offset  |
 222   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 223   //          [ y_hi ]                  | (in bytes)
 224   //            ....                    |
 225   //          [ x_lo ]                 /
 226   //          [ x_hi ]
 227   //            ....
 228   //
 229   // Basic idea: lo(result) = lo(x_lo * y_lo)
 230   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 231   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 232   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 233   Label quick;
 234   // load x_hi, y_hi and check if quick
 235   // multiplication is possible
 236   movl(rbx, x_hi);
 237   movl(rcx, y_hi);
 238   movl(rax, rbx);
 239   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 240   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 241   // do full multiplication
 242   // 1st step
 243   mull(y_lo);                                    // x_hi * y_lo
 244   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 245   // 2nd step
 246   movl(rax, x_lo);
 247   mull(rcx);                                     // x_lo * y_hi
 248   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 249   // 3rd step
 250   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 251   movl(rax, x_lo);
 252   mull(y_lo);                                    // x_lo * y_lo
 253   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 254 }
 255 
 256 void MacroAssembler::lneg(Register hi, Register lo) {
 257   negl(lo);
 258   adcl(hi, 0);
 259   negl(hi);
 260 }
 261 
 262 void MacroAssembler::lshl(Register hi, Register lo) {
 263   // Java shift left long support (semantics as described in JVM spec., p.305)
 264   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 265   // shift value is in rcx !
 266   assert(hi != rcx, "must not use rcx");
 267   assert(lo != rcx, "must not use rcx");
 268   const Register s = rcx;                        // shift count
 269   const int      n = BitsPerWord;
 270   Label L;
 271   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 272   cmpl(s, n);                                    // if (s < n)
 273   jcc(Assembler::less, L);                       // else (s >= n)
 274   movl(hi, lo);                                  // x := x << n
 275   xorl(lo, lo);
 276   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 277   bind(L);                                       // s (mod n) < n
 278   shldl(hi, lo);                                 // x := x << s
 279   shll(lo);
 280 }
 281 
 282 
 283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 284   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 285   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 286   assert(hi != rcx, "must not use rcx");
 287   assert(lo != rcx, "must not use rcx");
 288   const Register s = rcx;                        // shift count
 289   const int      n = BitsPerWord;
 290   Label L;
 291   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 292   cmpl(s, n);                                    // if (s < n)
 293   jcc(Assembler::less, L);                       // else (s >= n)
 294   movl(lo, hi);                                  // x := x >> n
 295   if (sign_extension) sarl(hi, 31);
 296   else                xorl(hi, hi);
 297   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 298   bind(L);                                       // s (mod n) < n
 299   shrdl(lo, hi);                                 // x := x >> s
 300   if (sign_extension) sarl(hi);
 301   else                shrl(hi);
 302 }
 303 
 304 void MacroAssembler::movoop(Register dst, jobject obj) {
 305   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::movoop(Address dst, jobject obj) {
 309   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 313   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 314 }
 315 
 316 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 317   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 318 }
 319 
 320 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 321   // scratch register is not used,
 322   // it is defined to match parameters of 64-bit version of this method.
 323   if (src.is_lval()) {
 324     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 325   } else {
 326     movl(dst, as_Address(src));
 327   }
 328 }
 329 
 330 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 331   movl(as_Address(dst), src);
 332 }
 333 
 334 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 335   movl(dst, as_Address(src));
 336 }
 337 
 338 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 339 void MacroAssembler::movptr(Address dst, intptr_t src) {
 340   movl(dst, src);
 341 }
 342 
 343 
 344 void MacroAssembler::pop_callee_saved_registers() {
 345   pop(rcx);
 346   pop(rdx);
 347   pop(rdi);
 348   pop(rsi);
 349 }
 350 
 351 void MacroAssembler::pop_fTOS() {
 352   fld_d(Address(rsp, 0));
 353   addl(rsp, 2 * wordSize);
 354 }
 355 
 356 void MacroAssembler::push_callee_saved_registers() {
 357   push(rsi);
 358   push(rdi);
 359   push(rdx);
 360   push(rcx);
 361 }
 362 
 363 void MacroAssembler::push_fTOS() {
 364   subl(rsp, 2 * wordSize);
 365   fstp_d(Address(rsp, 0));
 366 }
 367 
 368 
 369 void MacroAssembler::pushoop(jobject obj) {
 370   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 371 }
 372 
 373 void MacroAssembler::pushklass(Metadata* obj) {
 374   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 375 }
 376 
 377 void MacroAssembler::pushptr(AddressLiteral src) {
 378   if (src.is_lval()) {
 379     push_literal32((int32_t)src.target(), src.rspec());
 380   } else {
 381     pushl(as_Address(src));
 382   }
 383 }
 384 
 385 void MacroAssembler::set_word_if_not_zero(Register dst) {
 386   xorl(dst, dst);
 387   set_byte_if_not_zero(dst);
 388 }
 389 
 390 static void pass_arg0(MacroAssembler* masm, Register arg) {
 391   masm->push(arg);
 392 }
 393 
 394 static void pass_arg1(MacroAssembler* masm, Register arg) {
 395   masm->push(arg);
 396 }
 397 
 398 static void pass_arg2(MacroAssembler* masm, Register arg) {
 399   masm->push(arg);
 400 }
 401 
 402 static void pass_arg3(MacroAssembler* masm, Register arg) {
 403   masm->push(arg);
 404 }
 405 
 406 #ifndef PRODUCT
 407 extern "C" void findpc(intptr_t x);
 408 #endif
 409 
 410 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 411   // In order to get locks to work, we need to fake a in_VM state
 412   JavaThread* thread = JavaThread::current();
 413   JavaThreadState saved_state = thread->thread_state();
 414   thread->set_thread_state(_thread_in_vm);
 415   if (ShowMessageBoxOnError) {
 416     JavaThread* thread = JavaThread::current();
 417     JavaThreadState saved_state = thread->thread_state();
 418     thread->set_thread_state(_thread_in_vm);
 419     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 420       ttyLocker ttyl;
 421       BytecodeCounter::print();
 422     }
 423     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 424     // This is the value of eip which points to where verify_oop will return.
 425     if (os::message_box(msg, "Execution stopped, print registers?")) {
 426       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 427       BREAKPOINT;
 428     }
 429   } else {
 430     ttyLocker ttyl;
 431     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
 432   }
 433   // Don't assert holding the ttyLock
 434     assert(false, "DEBUG MESSAGE: %s", msg);
 435   ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 436 }
 437 
 438 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 439   ttyLocker ttyl;
 440   FlagSetting fs(Debugging, true);
 441   tty->print_cr("eip = 0x%08x", eip);
 442 #ifndef PRODUCT
 443   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 444     tty->cr();
 445     findpc(eip);
 446     tty->cr();
 447   }
 448 #endif
 449 #define PRINT_REG(rax) \
 450   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 451   PRINT_REG(rax);
 452   PRINT_REG(rbx);
 453   PRINT_REG(rcx);
 454   PRINT_REG(rdx);
 455   PRINT_REG(rdi);
 456   PRINT_REG(rsi);
 457   PRINT_REG(rbp);
 458   PRINT_REG(rsp);
 459 #undef PRINT_REG
 460   // Print some words near top of staack.
 461   int* dump_sp = (int*) rsp;
 462   for (int col1 = 0; col1 < 8; col1++) {
 463     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 464     os::print_location(tty, *dump_sp++);
 465   }
 466   for (int row = 0; row < 16; row++) {
 467     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 468     for (int col = 0; col < 8; col++) {
 469       tty->print(" 0x%08x", *dump_sp++);
 470     }
 471     tty->cr();
 472   }
 473   // Print some instructions around pc:
 474   Disassembler::decode((address)eip-64, (address)eip);
 475   tty->print_cr("--------");
 476   Disassembler::decode((address)eip, (address)eip+32);
 477 }
 478 
 479 void MacroAssembler::stop(const char* msg) {
 480   ExternalAddress message((address)msg);
 481   // push address of message
 482   pushptr(message.addr());
 483   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 484   pusha();                                            // push registers
 485   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 486   hlt();
 487 }
 488 
 489 void MacroAssembler::warn(const char* msg) {
 490   push_CPU_state();
 491 
 492   ExternalAddress message((address) msg);
 493   // push address of message
 494   pushptr(message.addr());
 495 
 496   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 497   addl(rsp, wordSize);       // discard argument
 498   pop_CPU_state();
 499 }
 500 
 501 void MacroAssembler::print_state() {
 502   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 503   pusha();                                            // push registers
 504 
 505   push_CPU_state();
 506   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 507   pop_CPU_state();
 508 
 509   popa();
 510   addl(rsp, wordSize);
 511 }
 512 
 513 #else // _LP64
 514 
 515 // 64 bit versions
 516 
 517 Address MacroAssembler::as_Address(AddressLiteral adr) {
 518   // amd64 always does this as a pc-rel
 519   // we can be absolute or disp based on the instruction type
 520   // jmp/call are displacements others are absolute
 521   assert(!adr.is_lval(), "must be rval");
 522   assert(reachable(adr), "must be");
 523   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 524 
 525 }
 526 
 527 Address MacroAssembler::as_Address(ArrayAddress adr) {
 528   AddressLiteral base = adr.base();
 529   lea(rscratch1, base);
 530   Address index = adr.index();
 531   assert(index._disp == 0, "must not have disp"); // maybe it can?
 532   Address array(rscratch1, index._index, index._scale, index._disp);
 533   return array;
 534 }
 535 
 536 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 537   Label L, E;
 538 
 539 #ifdef _WIN64
 540   // Windows always allocates space for it's register args
 541   assert(num_args <= 4, "only register arguments supported");
 542   subq(rsp,  frame::arg_reg_save_area_bytes);
 543 #endif
 544 
 545   // Align stack if necessary
 546   testl(rsp, 15);
 547   jcc(Assembler::zero, L);
 548 
 549   subq(rsp, 8);
 550   {
 551     call(RuntimeAddress(entry_point));
 552   }
 553   addq(rsp, 8);
 554   jmp(E);
 555 
 556   bind(L);
 557   {
 558     call(RuntimeAddress(entry_point));
 559   }
 560 
 561   bind(E);
 562 
 563 #ifdef _WIN64
 564   // restore stack pointer
 565   addq(rsp, frame::arg_reg_save_area_bytes);
 566 #endif
 567 
 568 }
 569 
 570 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 571   assert(!src2.is_lval(), "should use cmpptr");
 572 
 573   if (reachable(src2)) {
 574     cmpq(src1, as_Address(src2));
 575   } else {
 576     lea(rscratch1, src2);
 577     Assembler::cmpq(src1, Address(rscratch1, 0));
 578   }
 579 }
 580 
 581 int MacroAssembler::corrected_idivq(Register reg) {
 582   // Full implementation of Java ldiv and lrem; checks for special
 583   // case as described in JVM spec., p.243 & p.271.  The function
 584   // returns the (pc) offset of the idivl instruction - may be needed
 585   // for implicit exceptions.
 586   //
 587   //         normal case                           special case
 588   //
 589   // input : rax: dividend                         min_long
 590   //         reg: divisor   (may not be eax/edx)   -1
 591   //
 592   // output: rax: quotient  (= rax idiv reg)       min_long
 593   //         rdx: remainder (= rax irem reg)       0
 594   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 595   static const int64_t min_long = 0x8000000000000000;
 596   Label normal_case, special_case;
 597 
 598   // check for special case
 599   cmp64(rax, ExternalAddress((address) &min_long));
 600   jcc(Assembler::notEqual, normal_case);
 601   xorl(rdx, rdx); // prepare rdx for possible special case (where
 602                   // remainder = 0)
 603   cmpq(reg, -1);
 604   jcc(Assembler::equal, special_case);
 605 
 606   // handle normal case
 607   bind(normal_case);
 608   cdqq();
 609   int idivq_offset = offset();
 610   idivq(reg);
 611 
 612   // normal and special case exit
 613   bind(special_case);
 614 
 615   return idivq_offset;
 616 }
 617 
 618 void MacroAssembler::decrementq(Register reg, int value) {
 619   if (value == min_jint) { subq(reg, value); return; }
 620   if (value <  0) { incrementq(reg, -value); return; }
 621   if (value == 0) {                        ; return; }
 622   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 623   /* else */      { subq(reg, value)       ; return; }
 624 }
 625 
 626 void MacroAssembler::decrementq(Address dst, int value) {
 627   if (value == min_jint) { subq(dst, value); return; }
 628   if (value <  0) { incrementq(dst, -value); return; }
 629   if (value == 0) {                        ; return; }
 630   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 631   /* else */      { subq(dst, value)       ; return; }
 632 }
 633 
 634 void MacroAssembler::incrementq(AddressLiteral dst) {
 635   if (reachable(dst)) {
 636     incrementq(as_Address(dst));
 637   } else {
 638     lea(rscratch1, dst);
 639     incrementq(Address(rscratch1, 0));
 640   }
 641 }
 642 
 643 void MacroAssembler::incrementq(Register reg, int value) {
 644   if (value == min_jint) { addq(reg, value); return; }
 645   if (value <  0) { decrementq(reg, -value); return; }
 646   if (value == 0) {                        ; return; }
 647   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 648   /* else */      { addq(reg, value)       ; return; }
 649 }
 650 
 651 void MacroAssembler::incrementq(Address dst, int value) {
 652   if (value == min_jint) { addq(dst, value); return; }
 653   if (value <  0) { decrementq(dst, -value); return; }
 654   if (value == 0) {                        ; return; }
 655   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 656   /* else */      { addq(dst, value)       ; return; }
 657 }
 658 
 659 // 32bit can do a case table jump in one instruction but we no longer allow the base
 660 // to be installed in the Address class
 661 void MacroAssembler::jump(ArrayAddress entry) {
 662   lea(rscratch1, entry.base());
 663   Address dispatch = entry.index();
 664   assert(dispatch._base == noreg, "must be");
 665   dispatch._base = rscratch1;
 666   jmp(dispatch);
 667 }
 668 
 669 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 670   ShouldNotReachHere(); // 64bit doesn't use two regs
 671   cmpq(x_lo, y_lo);
 672 }
 673 
 674 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 675     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 676 }
 677 
 678 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 679   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 680   movptr(dst, rscratch1);
 681 }
 682 
 683 void MacroAssembler::leave() {
 684   // %%% is this really better? Why not on 32bit too?
 685   emit_int8((unsigned char)0xC9); // LEAVE
 686 }
 687 
 688 void MacroAssembler::lneg(Register hi, Register lo) {
 689   ShouldNotReachHere(); // 64bit doesn't use two regs
 690   negq(lo);
 691 }
 692 
 693 void MacroAssembler::movoop(Register dst, jobject obj) {
 694   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 695 }
 696 
 697 void MacroAssembler::movoop(Address dst, jobject obj) {
 698   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 699   movq(dst, rscratch1);
 700 }
 701 
 702 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 703   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 704 }
 705 
 706 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 707   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 708   movq(dst, rscratch1);
 709 }
 710 
 711 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 712   if (src.is_lval()) {
 713     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 714   } else {
 715     if (reachable(src)) {
 716       movq(dst, as_Address(src));
 717     } else {
 718       lea(scratch, src);
 719       movq(dst, Address(scratch, 0));
 720     }
 721   }
 722 }
 723 
 724 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 725   movq(as_Address(dst), src);
 726 }
 727 
 728 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 729   movq(dst, as_Address(src));
 730 }
 731 
 732 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 733 void MacroAssembler::movptr(Address dst, intptr_t src) {
 734   mov64(rscratch1, src);
 735   movq(dst, rscratch1);
 736 }
 737 
 738 // These are mostly for initializing NULL
 739 void MacroAssembler::movptr(Address dst, int32_t src) {
 740   movslq(dst, src);
 741 }
 742 
 743 void MacroAssembler::movptr(Register dst, int32_t src) {
 744   mov64(dst, (intptr_t)src);
 745 }
 746 
 747 void MacroAssembler::pushoop(jobject obj) {
 748   movoop(rscratch1, obj);
 749   push(rscratch1);
 750 }
 751 
 752 void MacroAssembler::pushklass(Metadata* obj) {
 753   mov_metadata(rscratch1, obj);
 754   push(rscratch1);
 755 }
 756 
 757 void MacroAssembler::pushptr(AddressLiteral src) {
 758   lea(rscratch1, src);
 759   if (src.is_lval()) {
 760     push(rscratch1);
 761   } else {
 762     pushq(Address(rscratch1, 0));
 763   }
 764 }
 765 
 766 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 767   // we must set sp to zero to clear frame
 768   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 769   // must clear fp, so that compiled frames are not confused; it is
 770   // possible that we need it only for debugging
 771   if (clear_fp) {
 772     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 773   }
 774 
 775   // Always clear the pc because it could have been set by make_walkable()
 776   movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 777   vzeroupper();
 778 }
 779 
 780 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 781                                          Register last_java_fp,
 782                                          address  last_java_pc) {
 783   vzeroupper();
 784   // determine last_java_sp register
 785   if (!last_java_sp->is_valid()) {
 786     last_java_sp = rsp;
 787   }
 788 
 789   // last_java_fp is optional
 790   if (last_java_fp->is_valid()) {
 791     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 792            last_java_fp);
 793   }
 794 
 795   // last_java_pc is optional
 796   if (last_java_pc != NULL) {
 797     Address java_pc(r15_thread,
 798                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 799     lea(rscratch1, InternalAddress(last_java_pc));
 800     movptr(java_pc, rscratch1);
 801   }
 802 
 803   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 804 }
 805 
 806 static void pass_arg0(MacroAssembler* masm, Register arg) {
 807   if (c_rarg0 != arg ) {
 808     masm->mov(c_rarg0, arg);
 809   }
 810 }
 811 
 812 static void pass_arg1(MacroAssembler* masm, Register arg) {
 813   if (c_rarg1 != arg ) {
 814     masm->mov(c_rarg1, arg);
 815   }
 816 }
 817 
 818 static void pass_arg2(MacroAssembler* masm, Register arg) {
 819   if (c_rarg2 != arg ) {
 820     masm->mov(c_rarg2, arg);
 821   }
 822 }
 823 
 824 static void pass_arg3(MacroAssembler* masm, Register arg) {
 825   if (c_rarg3 != arg ) {
 826     masm->mov(c_rarg3, arg);
 827   }
 828 }
 829 
 830 void MacroAssembler::stop(const char* msg) {
 831   address rip = pc();
 832   pusha(); // get regs on stack
 833   lea(c_rarg0, ExternalAddress((address) msg));
 834   lea(c_rarg1, InternalAddress(rip));
 835   movq(c_rarg2, rsp); // pass pointer to regs array
 836   andq(rsp, -16); // align stack as required by ABI
 837   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 838   hlt();
 839 }
 840 
 841 void MacroAssembler::warn(const char* msg) {
 842   push(rbp);
 843   movq(rbp, rsp);
 844   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 845   push_CPU_state();   // keeps alignment at 16 bytes
 846   lea(c_rarg0, ExternalAddress((address) msg));
 847   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 848   call(rax);
 849   pop_CPU_state();
 850   mov(rsp, rbp);
 851   pop(rbp);
 852 }
 853 
 854 void MacroAssembler::print_state() {
 855   address rip = pc();
 856   pusha();            // get regs on stack
 857   push(rbp);
 858   movq(rbp, rsp);
 859   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 860   push_CPU_state();   // keeps alignment at 16 bytes
 861 
 862   lea(c_rarg0, InternalAddress(rip));
 863   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 864   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 865 
 866   pop_CPU_state();
 867   mov(rsp, rbp);
 868   pop(rbp);
 869   popa();
 870 }
 871 
 872 #ifndef PRODUCT
 873 extern "C" void findpc(intptr_t x);
 874 #endif
 875 
 876 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 877   // In order to get locks to work, we need to fake a in_VM state
 878   if (ShowMessageBoxOnError) {
 879     JavaThread* thread = JavaThread::current();
 880     JavaThreadState saved_state = thread->thread_state();
 881     thread->set_thread_state(_thread_in_vm);
 882 #ifndef PRODUCT
 883     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 884       ttyLocker ttyl;
 885       BytecodeCounter::print();
 886     }
 887 #endif
 888     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 889     // XXX correct this offset for amd64
 890     // This is the value of eip which points to where verify_oop will return.
 891     if (os::message_box(msg, "Execution stopped, print registers?")) {
 892       print_state64(pc, regs);
 893       BREAKPOINT;
 894       assert(false, "start up GDB");
 895     }
 896     ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
 897   } else {
 898     ttyLocker ttyl;
 899     ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
 900                     msg);
 901     assert(false, "DEBUG MESSAGE: %s", msg);
 902   }
 903 }
 904 
 905 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 906   ttyLocker ttyl;
 907   FlagSetting fs(Debugging, true);
 908   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 909 #ifndef PRODUCT
 910   tty->cr();
 911   findpc(pc);
 912   tty->cr();
 913 #endif
 914 #define PRINT_REG(rax, value) \
 915   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 916   PRINT_REG(rax, regs[15]);
 917   PRINT_REG(rbx, regs[12]);
 918   PRINT_REG(rcx, regs[14]);
 919   PRINT_REG(rdx, regs[13]);
 920   PRINT_REG(rdi, regs[8]);
 921   PRINT_REG(rsi, regs[9]);
 922   PRINT_REG(rbp, regs[10]);
 923   PRINT_REG(rsp, regs[11]);
 924   PRINT_REG(r8 , regs[7]);
 925   PRINT_REG(r9 , regs[6]);
 926   PRINT_REG(r10, regs[5]);
 927   PRINT_REG(r11, regs[4]);
 928   PRINT_REG(r12, regs[3]);
 929   PRINT_REG(r13, regs[2]);
 930   PRINT_REG(r14, regs[1]);
 931   PRINT_REG(r15, regs[0]);
 932 #undef PRINT_REG
 933   // Print some words near top of staack.
 934   int64_t* rsp = (int64_t*) regs[11];
 935   int64_t* dump_sp = rsp;
 936   for (int col1 = 0; col1 < 8; col1++) {
 937     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 938     os::print_location(tty, *dump_sp++);
 939   }
 940   for (int row = 0; row < 25; row++) {
 941     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 942     for (int col = 0; col < 4; col++) {
 943       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 944     }
 945     tty->cr();
 946   }
 947   // Print some instructions around pc:
 948   Disassembler::decode((address)pc-64, (address)pc);
 949   tty->print_cr("--------");
 950   Disassembler::decode((address)pc, (address)pc+32);
 951 }
 952 
 953 #endif // _LP64
 954 
 955 // Now versions that are common to 32/64 bit
 956 
 957 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 958   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 959 }
 960 
 961 void MacroAssembler::addptr(Register dst, Register src) {
 962   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 963 }
 964 
 965 void MacroAssembler::addptr(Address dst, Register src) {
 966   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 967 }
 968 
 969 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
 970   if (reachable(src)) {
 971     Assembler::addsd(dst, as_Address(src));
 972   } else {
 973     lea(rscratch1, src);
 974     Assembler::addsd(dst, Address(rscratch1, 0));
 975   }
 976 }
 977 
 978 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
 979   if (reachable(src)) {
 980     addss(dst, as_Address(src));
 981   } else {
 982     lea(rscratch1, src);
 983     addss(dst, Address(rscratch1, 0));
 984   }
 985 }
 986 
 987 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
 988   if (reachable(src)) {
 989     Assembler::addpd(dst, as_Address(src));
 990   } else {
 991     lea(rscratch1, src);
 992     Assembler::addpd(dst, Address(rscratch1, 0));
 993   }
 994 }
 995 
 996 void MacroAssembler::align(int modulus) {
 997   align(modulus, offset());
 998 }
 999 
1000 void MacroAssembler::align(int modulus, int target) {
1001   if (target % modulus != 0) {
1002     nop(modulus - (target % modulus));
1003   }
1004 }
1005 
1006 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
1007   // Used in sign-masking with aligned address.
1008   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1009   if (reachable(src)) {
1010     Assembler::andpd(dst, as_Address(src));
1011   } else {
1012     lea(rscratch1, src);
1013     Assembler::andpd(dst, Address(rscratch1, 0));
1014   }
1015 }
1016 
1017 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1018   // Used in sign-masking with aligned address.
1019   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1020   if (reachable(src)) {
1021     Assembler::andps(dst, as_Address(src));
1022   } else {
1023     lea(rscratch1, src);
1024     Assembler::andps(dst, Address(rscratch1, 0));
1025   }
1026 }
1027 
1028 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1029   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1030 }
1031 
1032 void MacroAssembler::atomic_incl(Address counter_addr) {
1033   lock();
1034   incrementl(counter_addr);
1035 }
1036 
1037 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1038   if (reachable(counter_addr)) {
1039     atomic_incl(as_Address(counter_addr));
1040   } else {
1041     lea(scr, counter_addr);
1042     atomic_incl(Address(scr, 0));
1043   }
1044 }
1045 
1046 #ifdef _LP64
1047 void MacroAssembler::atomic_incq(Address counter_addr) {
1048   lock();
1049   incrementq(counter_addr);
1050 }
1051 
1052 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1053   if (reachable(counter_addr)) {
1054     atomic_incq(as_Address(counter_addr));
1055   } else {
1056     lea(scr, counter_addr);
1057     atomic_incq(Address(scr, 0));
1058   }
1059 }
1060 #endif
1061 
1062 // Writes to stack successive pages until offset reached to check for
1063 // stack overflow + shadow pages.  This clobbers tmp.
1064 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1065   movptr(tmp, rsp);
1066   // Bang stack for total size given plus shadow page size.
1067   // Bang one page at a time because large size can bang beyond yellow and
1068   // red zones.
1069   Label loop;
1070   bind(loop);
1071   movl(Address(tmp, (-os::vm_page_size())), size );
1072   subptr(tmp, os::vm_page_size());
1073   subl(size, os::vm_page_size());
1074   jcc(Assembler::greater, loop);
1075 
1076   // Bang down shadow pages too.
1077   // At this point, (tmp-0) is the last address touched, so don't
1078   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1079   // was post-decremented.)  Skip this address by starting at i=1, and
1080   // touch a few more pages below.  N.B.  It is important to touch all
1081   // the way down including all pages in the shadow zone.
1082   for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1083     // this could be any sized move but this is can be a debugging crumb
1084     // so the bigger the better.
1085     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1086   }
1087 }
1088 
1089 void MacroAssembler::reserved_stack_check() {
1090     // testing if reserved zone needs to be enabled
1091     Label no_reserved_zone_enabling;
1092     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1093     NOT_LP64(get_thread(rsi);)
1094 
1095     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1096     jcc(Assembler::below, no_reserved_zone_enabling);
1097 
1098     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1099     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1100     should_not_reach_here();
1101 
1102     bind(no_reserved_zone_enabling);
1103 }
1104 
1105 int MacroAssembler::biased_locking_enter(Register lock_reg,
1106                                          Register obj_reg,
1107                                          Register swap_reg,
1108                                          Register tmp_reg,
1109                                          bool swap_reg_contains_mark,
1110                                          Label& done,
1111                                          Label* slow_case,
1112                                          BiasedLockingCounters* counters) {
1113   assert(UseBiasedLocking, "why call this otherwise?");
1114   assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1115   assert(tmp_reg != noreg, "tmp_reg must be supplied");
1116   assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1117   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1118   Address mark_addr      (obj_reg, oopDesc::mark_offset_in_bytes());
1119   NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1120 
1121   if (PrintBiasedLockingStatistics && counters == NULL) {
1122     counters = BiasedLocking::counters();
1123   }
1124   // Biased locking
1125   // See whether the lock is currently biased toward our thread and
1126   // whether the epoch is still valid
1127   // Note that the runtime guarantees sufficient alignment of JavaThread
1128   // pointers to allow age to be placed into low bits
1129   // First check to see whether biasing is even enabled for this object
1130   Label cas_label;
1131   int null_check_offset = -1;
1132   if (!swap_reg_contains_mark) {
1133     null_check_offset = offset();
1134     movptr(swap_reg, mark_addr);
1135   }
1136   movptr(tmp_reg, swap_reg);
1137   andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1138   cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1139   jcc(Assembler::notEqual, cas_label);
1140   // The bias pattern is present in the object's header. Need to check
1141   // whether the bias owner and the epoch are both still current.
1142 #ifndef _LP64
1143   // Note that because there is no current thread register on x86_32 we
1144   // need to store off the mark word we read out of the object to
1145   // avoid reloading it and needing to recheck invariants below. This
1146   // store is unfortunate but it makes the overall code shorter and
1147   // simpler.
1148   movptr(saved_mark_addr, swap_reg);
1149 #endif
1150   if (swap_reg_contains_mark) {
1151     null_check_offset = offset();
1152   }
1153   load_prototype_header(tmp_reg, obj_reg);
1154 #ifdef _LP64
1155   orptr(tmp_reg, r15_thread);
1156   xorptr(tmp_reg, swap_reg);
1157   Register header_reg = tmp_reg;
1158 #else
1159   xorptr(tmp_reg, swap_reg);
1160   get_thread(swap_reg);
1161   xorptr(swap_reg, tmp_reg);
1162   Register header_reg = swap_reg;
1163 #endif
1164   andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1165   if (counters != NULL) {
1166     cond_inc32(Assembler::zero,
1167                ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1168   }
1169   jcc(Assembler::equal, done);
1170 
1171   Label try_revoke_bias;
1172   Label try_rebias;
1173 
1174   // At this point we know that the header has the bias pattern and
1175   // that we are not the bias owner in the current epoch. We need to
1176   // figure out more details about the state of the header in order to
1177   // know what operations can be legally performed on the object's
1178   // header.
1179 
1180   // If the low three bits in the xor result aren't clear, that means
1181   // the prototype header is no longer biased and we have to revoke
1182   // the bias on this object.
1183   testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1184   jccb(Assembler::notZero, try_revoke_bias);
1185 
1186   // Biasing is still enabled for this data type. See whether the
1187   // epoch of the current bias is still valid, meaning that the epoch
1188   // bits of the mark word are equal to the epoch bits of the
1189   // prototype header. (Note that the prototype header's epoch bits
1190   // only change at a safepoint.) If not, attempt to rebias the object
1191   // toward the current thread. Note that we must be absolutely sure
1192   // that the current epoch is invalid in order to do this because
1193   // otherwise the manipulations it performs on the mark word are
1194   // illegal.
1195   testptr(header_reg, markOopDesc::epoch_mask_in_place);
1196   jccb(Assembler::notZero, try_rebias);
1197 
1198   // The epoch of the current bias is still valid but we know nothing
1199   // about the owner; it might be set or it might be clear. Try to
1200   // acquire the bias of the object using an atomic operation. If this
1201   // fails we will go in to the runtime to revoke the object's bias.
1202   // Note that we first construct the presumed unbiased header so we
1203   // don't accidentally blow away another thread's valid bias.
1204   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1205   andptr(swap_reg,
1206          markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1207 #ifdef _LP64
1208   movptr(tmp_reg, swap_reg);
1209   orptr(tmp_reg, r15_thread);
1210 #else
1211   get_thread(tmp_reg);
1212   orptr(tmp_reg, swap_reg);
1213 #endif
1214   lock();
1215   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1216   // If the biasing toward our thread failed, this means that
1217   // another thread succeeded in biasing it toward itself and we
1218   // need to revoke that bias. The revocation will occur in the
1219   // interpreter runtime in the slow case.
1220   if (counters != NULL) {
1221     cond_inc32(Assembler::zero,
1222                ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1223   }
1224   if (slow_case != NULL) {
1225     jcc(Assembler::notZero, *slow_case);
1226   }
1227   jmp(done);
1228 
1229   bind(try_rebias);
1230   // At this point we know the epoch has expired, meaning that the
1231   // current "bias owner", if any, is actually invalid. Under these
1232   // circumstances _only_, we are allowed to use the current header's
1233   // value as the comparison value when doing the cas to acquire the
1234   // bias in the current epoch. In other words, we allow transfer of
1235   // the bias from one thread to another directly in this situation.
1236   //
1237   // FIXME: due to a lack of registers we currently blow away the age
1238   // bits in this situation. Should attempt to preserve them.
1239   load_prototype_header(tmp_reg, obj_reg);
1240 #ifdef _LP64
1241   orptr(tmp_reg, r15_thread);
1242 #else
1243   get_thread(swap_reg);
1244   orptr(tmp_reg, swap_reg);
1245   movptr(swap_reg, saved_mark_addr);
1246 #endif
1247   lock();
1248   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1249   // If the biasing toward our thread failed, then another thread
1250   // succeeded in biasing it toward itself and we need to revoke that
1251   // bias. The revocation will occur in the runtime in the slow case.
1252   if (counters != NULL) {
1253     cond_inc32(Assembler::zero,
1254                ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1255   }
1256   if (slow_case != NULL) {
1257     jcc(Assembler::notZero, *slow_case);
1258   }
1259   jmp(done);
1260 
1261   bind(try_revoke_bias);
1262   // The prototype mark in the klass doesn't have the bias bit set any
1263   // more, indicating that objects of this data type are not supposed
1264   // to be biased any more. We are going to try to reset the mark of
1265   // this object to the prototype value and fall through to the
1266   // CAS-based locking scheme. Note that if our CAS fails, it means
1267   // that another thread raced us for the privilege of revoking the
1268   // bias of this particular object, so it's okay to continue in the
1269   // normal locking code.
1270   //
1271   // FIXME: due to a lack of registers we currently blow away the age
1272   // bits in this situation. Should attempt to preserve them.
1273   NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1274   load_prototype_header(tmp_reg, obj_reg);
1275   lock();
1276   cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1277   // Fall through to the normal CAS-based lock, because no matter what
1278   // the result of the above CAS, some thread must have succeeded in
1279   // removing the bias bit from the object's header.
1280   if (counters != NULL) {
1281     cond_inc32(Assembler::zero,
1282                ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1283   }
1284 
1285   bind(cas_label);
1286 
1287   return null_check_offset;
1288 }
1289 
1290 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1291   assert(UseBiasedLocking, "why call this otherwise?");
1292 
1293   // Check for biased locking unlock case, which is a no-op
1294   // Note: we do not have to check the thread ID for two reasons.
1295   // First, the interpreter checks for IllegalMonitorStateException at
1296   // a higher level. Second, if the bias was revoked while we held the
1297   // lock, the object could not be rebiased toward another thread, so
1298   // the bias bit would be clear.
1299   movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1300   andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1301   cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1302   jcc(Assembler::equal, done);
1303 }
1304 
1305 #ifdef COMPILER2
1306 
1307 #if INCLUDE_RTM_OPT
1308 
1309 // Update rtm_counters based on abort status
1310 // input: abort_status
1311 //        rtm_counters (RTMLockingCounters*)
1312 // flags are killed
1313 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1314 
1315   atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1316   if (PrintPreciseRTMLockingStatistics) {
1317     for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1318       Label check_abort;
1319       testl(abort_status, (1<<i));
1320       jccb(Assembler::equal, check_abort);
1321       atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1322       bind(check_abort);
1323     }
1324   }
1325 }
1326 
1327 // Branch if (random & (count-1) != 0), count is 2^n
1328 // tmp, scr and flags are killed
1329 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1330   assert(tmp == rax, "");
1331   assert(scr == rdx, "");
1332   rdtsc(); // modifies EDX:EAX
1333   andptr(tmp, count-1);
1334   jccb(Assembler::notZero, brLabel);
1335 }
1336 
1337 // Perform abort ratio calculation, set no_rtm bit if high ratio
1338 // input:  rtm_counters_Reg (RTMLockingCounters* address)
1339 // tmpReg, rtm_counters_Reg and flags are killed
1340 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1341                                                  Register rtm_counters_Reg,
1342                                                  RTMLockingCounters* rtm_counters,
1343                                                  Metadata* method_data) {
1344   Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1345 
1346   if (RTMLockingCalculationDelay > 0) {
1347     // Delay calculation
1348     movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1349     testptr(tmpReg, tmpReg);
1350     jccb(Assembler::equal, L_done);
1351   }
1352   // Abort ratio calculation only if abort_count > RTMAbortThreshold
1353   //   Aborted transactions = abort_count * 100
1354   //   All transactions = total_count *  RTMTotalCountIncrRate
1355   //   Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1356 
1357   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1358   cmpptr(tmpReg, RTMAbortThreshold);
1359   jccb(Assembler::below, L_check_always_rtm2);
1360   imulptr(tmpReg, tmpReg, 100);
1361 
1362   Register scrReg = rtm_counters_Reg;
1363   movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1364   imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1365   imulptr(scrReg, scrReg, RTMAbortRatio);
1366   cmpptr(tmpReg, scrReg);
1367   jccb(Assembler::below, L_check_always_rtm1);
1368   if (method_data != NULL) {
1369     // set rtm_state to "no rtm" in MDO
1370     mov_metadata(tmpReg, method_data);
1371     lock();
1372     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1373   }
1374   jmpb(L_done);
1375   bind(L_check_always_rtm1);
1376   // Reload RTMLockingCounters* address
1377   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1378   bind(L_check_always_rtm2);
1379   movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1380   cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1381   jccb(Assembler::below, L_done);
1382   if (method_data != NULL) {
1383     // set rtm_state to "always rtm" in MDO
1384     mov_metadata(tmpReg, method_data);
1385     lock();
1386     orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387   }
1388   bind(L_done);
1389 }
1390 
1391 // Update counters and perform abort ratio calculation
1392 // input:  abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395                                    Register rtm_counters_Reg,
1396                                    RTMLockingCounters* rtm_counters,
1397                                    Metadata* method_data,
1398                                    bool profile_rtm) {
1399 
1400   assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401   // update rtm counters based on rax value at abort
1402   // reads abort_status_Reg, updates flags
1403   lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404   rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405   if (profile_rtm) {
1406     // Save abort status because abort_status_Reg is used by following code.
1407     if (RTMRetryCount > 0) {
1408       push(abort_status_Reg);
1409     }
1410     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411     rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412     // restore abort status
1413     if (RTMRetryCount > 0) {
1414       pop(abort_status_Reg);
1415     }
1416   }
1417 }
1418 
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 //       : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425   Label doneRetry;
1426   assert(abort_status_Reg == rax, "");
1427   // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428   // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429   // if reason is in 0x6 and retry count != 0 then retry
1430   andptr(abort_status_Reg, 0x6);
1431   jccb(Assembler::zero, doneRetry);
1432   testl(retry_count_Reg, retry_count_Reg);
1433   jccb(Assembler::zero, doneRetry);
1434   pause();
1435   decrementl(retry_count_Reg);
1436   jmp(retryLabel);
1437   bind(doneRetry);
1438 }
1439 
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 //       : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 //       : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447                                             Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448   Label SpinLoop, SpinExit, doneRetry;
1449   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450 
1451   testl(retry_count_Reg, retry_count_Reg);
1452   jccb(Assembler::zero, doneRetry);
1453   decrementl(retry_count_Reg);
1454   movptr(scr_Reg, RTMSpinLoopCount);
1455 
1456   bind(SpinLoop);
1457   pause();
1458   decrementl(scr_Reg);
1459   jccb(Assembler::lessEqual, SpinExit);
1460   movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461   testptr(tmp_Reg, tmp_Reg);
1462   jccb(Assembler::notZero, SpinLoop);
1463 
1464   bind(SpinExit);
1465   jmp(retryLabel);
1466   bind(doneRetry);
1467   incrementl(retry_count_Reg); // clear z flag
1468 }
1469 
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473                                        Register retry_on_abort_count_Reg,
1474                                        RTMLockingCounters* stack_rtm_counters,
1475                                        Metadata* method_data, bool profile_rtm,
1476                                        Label& DONE_LABEL, Label& IsInflated) {
1477   assert(UseRTMForStackLocks, "why call this otherwise?");
1478   assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479   assert(tmpReg == rax, "");
1480   assert(scrReg == rdx, "");
1481   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482 
1483   if (RTMRetryCount > 0) {
1484     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485     bind(L_rtm_retry);
1486   }
1487   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1488   testptr(tmpReg, markOopDesc::monitor_value);  // inflated vs stack-locked|neutral|biased
1489   jcc(Assembler::notZero, IsInflated);
1490 
1491   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492     Label L_noincrement;
1493     if (RTMTotalCountIncrRate > 1) {
1494       // tmpReg, scrReg and flags are killed
1495       branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1496     }
1497     assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498     atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499     bind(L_noincrement);
1500   }
1501   xbegin(L_on_abort);
1502   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));       // fetch markword
1503   andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504   cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1505   jcc(Assembler::equal, DONE_LABEL);        // all done if unlocked
1506 
1507   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508   if (UseRTMXendForLockBusy) {
1509     xend();
1510     movptr(abort_status_Reg, 0x2);   // Set the abort status to 2 (so we can retry)
1511     jmp(L_decrement_retry);
1512   }
1513   else {
1514     xabort(0);
1515   }
1516   bind(L_on_abort);
1517   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518     rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519   }
1520   bind(L_decrement_retry);
1521   if (RTMRetryCount > 0) {
1522     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524   }
1525 }
1526 
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 //         boxReg (on-stack box address (displaced header location) - KILLED)
1530 //         tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532                                           Register scrReg, Register retry_on_busy_count_Reg,
1533                                           Register retry_on_abort_count_Reg,
1534                                           RTMLockingCounters* rtm_counters,
1535                                           Metadata* method_data, bool profile_rtm,
1536                                           Label& DONE_LABEL) {
1537   assert(UseRTMLocking, "why call this otherwise?");
1538   assert(tmpReg == rax, "");
1539   assert(scrReg == rdx, "");
1540   Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541   int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542 
1543   // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545   movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546 
1547   if (RTMRetryCount > 0) {
1548     movl(retry_on_busy_count_Reg, RTMRetryCount);  // Retry on lock busy
1549     movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550     bind(L_rtm_retry);
1551   }
1552   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553     Label L_noincrement;
1554     if (RTMTotalCountIncrRate > 1) {
1555       // tmpReg, scrReg and flags are killed
1556       branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1557     }
1558     assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559     atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560     bind(L_noincrement);
1561   }
1562   xbegin(L_on_abort);
1563   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1564   movptr(tmpReg, Address(tmpReg, owner_offset));
1565   testptr(tmpReg, tmpReg);
1566   jcc(Assembler::zero, DONE_LABEL);
1567   if (UseRTMXendForLockBusy) {
1568     xend();
1569     jmp(L_decrement_retry);
1570   }
1571   else {
1572     xabort(0);
1573   }
1574   bind(L_on_abort);
1575   Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576   if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577     rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578   }
1579   if (RTMRetryCount > 0) {
1580     // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581     rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582   }
1583 
1584   movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585   testptr(tmpReg, tmpReg) ;
1586   jccb(Assembler::notZero, L_decrement_retry) ;
1587 
1588   // Appears unlocked - try to swing _owner from null to non-null.
1589   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591   Register threadReg = r15_thread;
1592 #else
1593   get_thread(scrReg);
1594   Register threadReg = scrReg;
1595 #endif
1596   lock();
1597   cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1598 
1599   if (RTMRetryCount > 0) {
1600     // success done else retry
1601     jccb(Assembler::equal, DONE_LABEL) ;
1602     bind(L_decrement_retry);
1603     // Spin and retry if lock is busy.
1604     rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1605   }
1606   else {
1607     bind(L_decrement_retry);
1608   }
1609 }
1610 
1611 #endif //  INCLUDE_RTM_OPT
1612 
1613 // Fast_Lock and Fast_Unlock used by C2
1614 
1615 // Because the transitions from emitted code to the runtime
1616 // monitorenter/exit helper stubs are so slow it's critical that
1617 // we inline both the stack-locking fast-path and the inflated fast path.
1618 //
1619 // See also: cmpFastLock and cmpFastUnlock.
1620 //
1621 // What follows is a specialized inline transliteration of the code
1622 // in slow_enter() and slow_exit().  If we're concerned about I$ bloat
1623 // another option would be to emit TrySlowEnter and TrySlowExit methods
1624 // at startup-time.  These methods would accept arguments as
1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1626 // indications in the icc.ZFlag.  Fast_Lock and Fast_Unlock would simply
1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1628 // In practice, however, the # of lock sites is bounded and is usually small.
1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1630 // if the processor uses simple bimodal branch predictors keyed by EIP
1631 // Since the helper routines would be called from multiple synchronization
1632 // sites.
1633 //
1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1636 // to those specialized methods.  That'd give us a mostly platform-independent
1637 // implementation that the JITs could optimize and inline at their pleasure.
1638 // Done correctly, the only time we'd need to cross to native could would be
1639 // to park() or unpark() threads.  We'd also need a few more unsafe operators
1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1641 // (b) explicit barriers or fence operations.
1642 //
1643 // TODO:
1644 //
1645 // *  Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1646 //    This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1647 //    Given TLAB allocation, Self is usually manifested in a register, so passing it into
1648 //    the lock operators would typically be faster than reifying Self.
1649 //
1650 // *  Ideally I'd define the primitives as:
1651 //       fast_lock   (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1652 //       fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1653 //    Unfortunately ADLC bugs prevent us from expressing the ideal form.
1654 //    Instead, we're stuck with a rather awkward and brittle register assignments below.
1655 //    Furthermore the register assignments are overconstrained, possibly resulting in
1656 //    sub-optimal code near the synchronization site.
1657 //
1658 // *  Eliminate the sp-proximity tests and just use "== Self" tests instead.
1659 //    Alternately, use a better sp-proximity test.
1660 //
1661 // *  Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1662 //    Either one is sufficient to uniquely identify a thread.
1663 //    TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1664 //
1665 // *  Intrinsify notify() and notifyAll() for the common cases where the
1666 //    object is locked by the calling thread but the waitlist is empty.
1667 //    avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1668 //
1669 // *  use jccb and jmpb instead of jcc and jmp to improve code density.
1670 //    But beware of excessive branch density on AMD Opterons.
1671 //
1672 // *  Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1673 //    or failure of the fast-path.  If the fast-path fails then we pass
1674 //    control to the slow-path, typically in C.  In Fast_Lock and
1675 //    Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1676 //    will emit a conditional branch immediately after the node.
1677 //    So we have branches to branches and lots of ICC.ZF games.
1678 //    Instead, it might be better to have C2 pass a "FailureLabel"
1679 //    into Fast_Lock and Fast_Unlock.  In the case of success, control
1680 //    will drop through the node.  ICC.ZF is undefined at exit.
1681 //    In the case of failure, the node will branch directly to the
1682 //    FailureLabel
1683 
1684 
1685 // obj: object to lock
1686 // box: on-stack box address (displaced header location) - KILLED
1687 // rax,: tmp -- KILLED
1688 // scr: tmp -- KILLED
1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1690                                Register scrReg, Register cx1Reg, Register cx2Reg,
1691                                BiasedLockingCounters* counters,
1692                                RTMLockingCounters* rtm_counters,
1693                                RTMLockingCounters* stack_rtm_counters,
1694                                Metadata* method_data,
1695                                bool use_rtm, bool profile_rtm) {
1696   // Ensure the register assignments are disjoint
1697   assert(tmpReg == rax, "");
1698 
1699   if (use_rtm) {
1700     assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1701   } else {
1702     assert(cx1Reg == noreg, "");
1703     assert(cx2Reg == noreg, "");
1704     assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1705   }
1706 
1707   if (counters != NULL) {
1708     atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1709   }
1710 
1711   // Possible cases that we'll encounter in fast_lock
1712   // ------------------------------------------------
1713   // * Inflated
1714   //    -- unlocked
1715   //    -- Locked
1716   //       = by self
1717   //       = by other
1718   // * biased
1719   //    -- by Self
1720   //    -- by other
1721   // * neutral
1722   // * stack-locked
1723   //    -- by self
1724   //       = sp-proximity test hits
1725   //       = sp-proximity test generates false-negative
1726   //    -- by other
1727   //
1728 
1729   Label IsInflated, DONE_LABEL;
1730 
1731   // it's stack-locked, biased or neutral
1732   // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1733   // order to reduce the number of conditional branches in the most common cases.
1734   // Beware -- there's a subtle invariant that fetch of the markword
1735   // at [FETCH], below, will never observe a biased encoding (*101b).
1736   // If this invariant is not held we risk exclusion (safety) failure.
1737   if (UseBiasedLocking && !UseOptoBiasInlining) {
1738     biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1739   }
1740 
1741 #if INCLUDE_RTM_OPT
1742   if (UseRTMForStackLocks && use_rtm) {
1743     rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1744                       stack_rtm_counters, method_data, profile_rtm,
1745                       DONE_LABEL, IsInflated);
1746   }
1747 #endif // INCLUDE_RTM_OPT
1748 
1749   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));          // [FETCH]
1750   testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1751   jccb(Assembler::notZero, IsInflated);
1752 
1753   // Attempt stack-locking ...
1754   orptr (tmpReg, markOopDesc::unlocked_value);
1755   movptr(Address(boxReg, 0), tmpReg);          // Anticipate successful CAS
1756   lock();
1757   cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes()));      // Updates tmpReg
1758   if (counters != NULL) {
1759     cond_inc32(Assembler::equal,
1760                ExternalAddress((address)counters->fast_path_entry_count_addr()));
1761   }
1762   jcc(Assembler::equal, DONE_LABEL);           // Success
1763 
1764   // Recursive locking.
1765   // The object is stack-locked: markword contains stack pointer to BasicLock.
1766   // Locked by current thread if difference with current SP is less than one page.
1767   subptr(tmpReg, rsp);
1768   // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1769   andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1770   movptr(Address(boxReg, 0), tmpReg);
1771   if (counters != NULL) {
1772     cond_inc32(Assembler::equal,
1773                ExternalAddress((address)counters->fast_path_entry_count_addr()));
1774   }
1775   jmp(DONE_LABEL);
1776 
1777   bind(IsInflated);
1778   // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1779 
1780 #if INCLUDE_RTM_OPT
1781   // Use the same RTM locking code in 32- and 64-bit VM.
1782   if (use_rtm) {
1783     rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1784                          rtm_counters, method_data, profile_rtm, DONE_LABEL);
1785   } else {
1786 #endif // INCLUDE_RTM_OPT
1787 
1788 #ifndef _LP64
1789   // The object is inflated.
1790 
1791   // boxReg refers to the on-stack BasicLock in the current frame.
1792   // We'd like to write:
1793   //   set box->_displaced_header = markOopDesc::unused_mark().  Any non-0 value suffices.
1794   // This is convenient but results a ST-before-CAS penalty.  The following CAS suffers
1795   // additional latency as we have another ST in the store buffer that must drain.
1796 
1797   // avoid ST-before-CAS
1798   // register juggle because we need tmpReg for cmpxchgptr below
1799   movptr(scrReg, boxReg);
1800   movptr(boxReg, tmpReg);                   // consider: LEA box, [tmp-2]
1801 
1802   // Optimistic form: consider XORL tmpReg,tmpReg
1803   movptr(tmpReg, NULL_WORD);
1804 
1805   // Appears unlocked - try to swing _owner from null to non-null.
1806   // Ideally, I'd manifest "Self" with get_thread and then attempt
1807   // to CAS the register containing Self into m->Owner.
1808   // But we don't have enough registers, so instead we can either try to CAS
1809   // rsp or the address of the box (in scr) into &m->owner.  If the CAS succeeds
1810   // we later store "Self" into m->Owner.  Transiently storing a stack address
1811   // (rsp or the address of the box) into  m->owner is harmless.
1812   // Invariant: tmpReg == 0.  tmpReg is EAX which is the implicit cmpxchg comparand.
1813   lock();
1814   cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815   movptr(Address(scrReg, 0), 3);          // box->_displaced_header = 3
1816   // If we weren't able to swing _owner from NULL to the BasicLock
1817   // then take the slow path.
1818   jccb  (Assembler::notZero, DONE_LABEL);
1819   // update _owner from BasicLock to thread
1820   get_thread (scrReg);                    // beware: clobbers ICCs
1821   movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1822   xorptr(boxReg, boxReg);                 // set icc.ZFlag = 1 to indicate success
1823 
1824   // If the CAS fails we can either retry or pass control to the slow-path.
1825   // We use the latter tactic.
1826   // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1827   // If the CAS was successful ...
1828   //   Self has acquired the lock
1829   //   Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1830   // Intentional fall-through into DONE_LABEL ...
1831 #else // _LP64
1832   // It's inflated
1833   movq(scrReg, tmpReg);
1834   xorq(tmpReg, tmpReg);
1835 
1836   lock();
1837   cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1838   // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1839   // Without cast to int32_t movptr will destroy r10 which is typically obj.
1840   movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1841   // Intentional fall-through into DONE_LABEL ...
1842   // Propagate ICC.ZF from CAS above into DONE_LABEL.
1843 #endif // _LP64
1844 #if INCLUDE_RTM_OPT
1845   } // use_rtm()
1846 #endif
1847   // DONE_LABEL is a hot target - we'd really like to place it at the
1848   // start of cache line by padding with NOPs.
1849   // See the AMD and Intel software optimization manuals for the
1850   // most efficient "long" NOP encodings.
1851   // Unfortunately none of our alignment mechanisms suffice.
1852   bind(DONE_LABEL);
1853 
1854   // At DONE_LABEL the icc ZFlag is set as follows ...
1855   // Fast_Unlock uses the same protocol.
1856   // ZFlag == 1 -> Success
1857   // ZFlag == 0 -> Failure - force control through the slow-path
1858 }
1859 
1860 // obj: object to unlock
1861 // box: box address (displaced header location), killed.  Must be EAX.
1862 // tmp: killed, cannot be obj nor box.
1863 //
1864 // Some commentary on balanced locking:
1865 //
1866 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1867 // Methods that don't have provably balanced locking are forced to run in the
1868 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1869 // The interpreter provides two properties:
1870 // I1:  At return-time the interpreter automatically and quietly unlocks any
1871 //      objects acquired the current activation (frame).  Recall that the
1872 //      interpreter maintains an on-stack list of locks currently held by
1873 //      a frame.
1874 // I2:  If a method attempts to unlock an object that is not held by the
1875 //      the frame the interpreter throws IMSX.
1876 //
1877 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1878 // B() doesn't have provably balanced locking so it runs in the interpreter.
1879 // Control returns to A() and A() unlocks O.  By I1 and I2, above, we know that O
1880 // is still locked by A().
1881 //
1882 // The only other source of unbalanced locking would be JNI.  The "Java Native Interface:
1883 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1884 // should not be unlocked by "normal" java-level locking and vice-versa.  The specification
1885 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1886 // Arguably given that the spec legislates the JNI case as undefined our implementation
1887 // could reasonably *avoid* checking owner in Fast_Unlock().
1888 // In the interest of performance we elide m->Owner==Self check in unlock.
1889 // A perfectly viable alternative is to elide the owner check except when
1890 // Xcheck:jni is enabled.
1891 
1892 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1893   assert(boxReg == rax, "");
1894   assert_different_registers(objReg, boxReg, tmpReg);
1895 
1896   Label DONE_LABEL, Stacked, CheckSucc;
1897 
1898   // Critically, the biased locking test must have precedence over
1899   // and appear before the (box->dhw == 0) recursive stack-lock test.
1900   if (UseBiasedLocking && !UseOptoBiasInlining) {
1901     biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1902   }
1903 
1904 #if INCLUDE_RTM_OPT
1905   if (UseRTMForStackLocks && use_rtm) {
1906     assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1907     Label L_regular_unlock;
1908     movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));           // fetch markword
1909     andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1910     cmpptr(tmpReg, markOopDesc::unlocked_value);            // bits = 001 unlocked
1911     jccb(Assembler::notEqual, L_regular_unlock);  // if !HLE RegularLock
1912     xend();                                       // otherwise end...
1913     jmp(DONE_LABEL);                              // ... and we're done
1914     bind(L_regular_unlock);
1915   }
1916 #endif
1917 
1918   cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1919   jcc   (Assembler::zero, DONE_LABEL);            // 0 indicates recursive stack-lock
1920   movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));             // Examine the object's markword
1921   testptr(tmpReg, markOopDesc::monitor_value);    // Inflated?
1922   jccb  (Assembler::zero, Stacked);
1923 
1924   // It's inflated.
1925 #if INCLUDE_RTM_OPT
1926   if (use_rtm) {
1927     Label L_regular_inflated_unlock;
1928     int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1929     movptr(boxReg, Address(tmpReg, owner_offset));
1930     testptr(boxReg, boxReg);
1931     jccb(Assembler::notZero, L_regular_inflated_unlock);
1932     xend();
1933     jmpb(DONE_LABEL);
1934     bind(L_regular_inflated_unlock);
1935   }
1936 #endif
1937 
1938   // Despite our balanced locking property we still check that m->_owner == Self
1939   // as java routines or native JNI code called by this thread might
1940   // have released the lock.
1941   // Refer to the comments in synchronizer.cpp for how we might encode extra
1942   // state in _succ so we can avoid fetching EntryList|cxq.
1943   //
1944   // I'd like to add more cases in fast_lock() and fast_unlock() --
1945   // such as recursive enter and exit -- but we have to be wary of
1946   // I$ bloat, T$ effects and BP$ effects.
1947   //
1948   // If there's no contention try a 1-0 exit.  That is, exit without
1949   // a costly MEMBAR or CAS.  See synchronizer.cpp for details on how
1950   // we detect and recover from the race that the 1-0 exit admits.
1951   //
1952   // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
1953   // before it STs null into _owner, releasing the lock.  Updates
1954   // to data protected by the critical section must be visible before
1955   // we drop the lock (and thus before any other thread could acquire
1956   // the lock and observe the fields protected by the lock).
1957   // IA32's memory-model is SPO, so STs are ordered with respect to
1958   // each other and there's no need for an explicit barrier (fence).
1959   // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
1960 #ifndef _LP64
1961   get_thread (boxReg);
1962 
1963   // Note that we could employ various encoding schemes to reduce
1964   // the number of loads below (currently 4) to just 2 or 3.
1965   // Refer to the comments in synchronizer.cpp.
1966   // In practice the chain of fetches doesn't seem to impact performance, however.
1967   xorptr(boxReg, boxReg);
1968   orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1969   jccb  (Assembler::notZero, DONE_LABEL);
1970   movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1971   orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1972   jccb  (Assembler::notZero, CheckSucc);
1973   movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1974   jmpb  (DONE_LABEL);
1975 
1976   bind (Stacked);
1977   // It's not inflated and it's not recursively stack-locked and it's not biased.
1978   // It must be stack-locked.
1979   // Try to reset the header to displaced header.
1980   // The "box" value on the stack is stable, so we can reload
1981   // and be assured we observe the same value as above.
1982   movptr(tmpReg, Address(boxReg, 0));
1983   lock();
1984   cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
1985   // Intention fall-thru into DONE_LABEL
1986 
1987   // DONE_LABEL is a hot target - we'd really like to place it at the
1988   // start of cache line by padding with NOPs.
1989   // See the AMD and Intel software optimization manuals for the
1990   // most efficient "long" NOP encodings.
1991   // Unfortunately none of our alignment mechanisms suffice.
1992   bind (CheckSucc);
1993 #else // _LP64
1994   // It's inflated
1995   xorptr(boxReg, boxReg);
1996   orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1997   jccb  (Assembler::notZero, DONE_LABEL);
1998   movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1999   orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2000   jccb  (Assembler::notZero, CheckSucc);
2001   movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2002   jmpb  (DONE_LABEL);
2003 
2004   // Try to avoid passing control into the slow_path ...
2005   Label LSuccess, LGoSlowPath ;
2006   bind  (CheckSucc);
2007 
2008   // The following optional optimization can be elided if necessary
2009   // Effectively: if (succ == null) goto SlowPath
2010   // The code reduces the window for a race, however,
2011   // and thus benefits performance.
2012   cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2013   jccb  (Assembler::zero, LGoSlowPath);
2014 
2015   xorptr(boxReg, boxReg);
2016   movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2017 
2018   // Memory barrier/fence
2019   // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2020   // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2021   // This is faster on Nehalem and AMD Shanghai/Barcelona.
2022   // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2023   // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2024   // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2025   lock(); addl(Address(rsp, 0), 0);
2026 
2027   cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2028   jccb  (Assembler::notZero, LSuccess);
2029 
2030   // Rare inopportune interleaving - race.
2031   // The successor vanished in the small window above.
2032   // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2033   // We need to ensure progress and succession.
2034   // Try to reacquire the lock.
2035   // If that fails then the new owner is responsible for succession and this
2036   // thread needs to take no further action and can exit via the fast path (success).
2037   // If the re-acquire succeeds then pass control into the slow path.
2038   // As implemented, this latter mode is horrible because we generated more
2039   // coherence traffic on the lock *and* artifically extended the critical section
2040   // length while by virtue of passing control into the slow path.
2041 
2042   // box is really RAX -- the following CMPXCHG depends on that binding
2043   // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2044   lock();
2045   cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2046   // There's no successor so we tried to regrab the lock.
2047   // If that didn't work, then another thread grabbed the
2048   // lock so we're done (and exit was a success).
2049   jccb  (Assembler::notEqual, LSuccess);
2050   // Intentional fall-through into slow-path
2051 
2052   bind  (LGoSlowPath);
2053   orl   (boxReg, 1);                      // set ICC.ZF=0 to indicate failure
2054   jmpb  (DONE_LABEL);
2055 
2056   bind  (LSuccess);
2057   testl (boxReg, 0);                      // set ICC.ZF=1 to indicate success
2058   jmpb  (DONE_LABEL);
2059 
2060   bind  (Stacked);
2061   movptr(tmpReg, Address (boxReg, 0));      // re-fetch
2062   lock();
2063   cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2064 
2065 #endif
2066   bind(DONE_LABEL);
2067 }
2068 #endif // COMPILER2
2069 
2070 void MacroAssembler::c2bool(Register x) {
2071   // implements x == 0 ? 0 : 1
2072   // note: must only look at least-significant byte of x
2073   //       since C-style booleans are stored in one byte
2074   //       only! (was bug)
2075   andl(x, 0xFF);
2076   setb(Assembler::notZero, x);
2077 }
2078 
2079 // Wouldn't need if AddressLiteral version had new name
2080 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2081   Assembler::call(L, rtype);
2082 }
2083 
2084 void MacroAssembler::call(Register entry) {
2085   Assembler::call(entry);
2086 }
2087 
2088 void MacroAssembler::call(AddressLiteral entry) {
2089   if (reachable(entry)) {
2090     Assembler::call_literal(entry.target(), entry.rspec());
2091   } else {
2092     lea(rscratch1, entry);
2093     Assembler::call(rscratch1);
2094   }
2095 }
2096 
2097 void MacroAssembler::ic_call(address entry, jint method_index) {
2098   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2099   movptr(rax, (intptr_t)Universe::non_oop_word());
2100   call(AddressLiteral(entry, rh));
2101 }
2102 
2103 // Implementation of call_VM versions
2104 
2105 void MacroAssembler::call_VM(Register oop_result,
2106                              address entry_point,
2107                              bool check_exceptions) {
2108   Label C, E;
2109   call(C, relocInfo::none);
2110   jmp(E);
2111 
2112   bind(C);
2113   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2114   ret(0);
2115 
2116   bind(E);
2117 }
2118 
2119 void MacroAssembler::call_VM(Register oop_result,
2120                              address entry_point,
2121                              Register arg_1,
2122                              bool check_exceptions) {
2123   Label C, E;
2124   call(C, relocInfo::none);
2125   jmp(E);
2126 
2127   bind(C);
2128   pass_arg1(this, arg_1);
2129   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2130   ret(0);
2131 
2132   bind(E);
2133 }
2134 
2135 void MacroAssembler::call_VM(Register oop_result,
2136                              address entry_point,
2137                              Register arg_1,
2138                              Register arg_2,
2139                              bool check_exceptions) {
2140   Label C, E;
2141   call(C, relocInfo::none);
2142   jmp(E);
2143 
2144   bind(C);
2145 
2146   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2147 
2148   pass_arg2(this, arg_2);
2149   pass_arg1(this, arg_1);
2150   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2151   ret(0);
2152 
2153   bind(E);
2154 }
2155 
2156 void MacroAssembler::call_VM(Register oop_result,
2157                              address entry_point,
2158                              Register arg_1,
2159                              Register arg_2,
2160                              Register arg_3,
2161                              bool check_exceptions) {
2162   Label C, E;
2163   call(C, relocInfo::none);
2164   jmp(E);
2165 
2166   bind(C);
2167 
2168   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2169   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2170   pass_arg3(this, arg_3);
2171 
2172   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2173   pass_arg2(this, arg_2);
2174 
2175   pass_arg1(this, arg_1);
2176   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2177   ret(0);
2178 
2179   bind(E);
2180 }
2181 
2182 void MacroAssembler::call_VM(Register oop_result,
2183                              Register last_java_sp,
2184                              address entry_point,
2185                              int number_of_arguments,
2186                              bool check_exceptions) {
2187   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2188   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2189 }
2190 
2191 void MacroAssembler::call_VM(Register oop_result,
2192                              Register last_java_sp,
2193                              address entry_point,
2194                              Register arg_1,
2195                              bool check_exceptions) {
2196   pass_arg1(this, arg_1);
2197   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2198 }
2199 
2200 void MacroAssembler::call_VM(Register oop_result,
2201                              Register last_java_sp,
2202                              address entry_point,
2203                              Register arg_1,
2204                              Register arg_2,
2205                              bool check_exceptions) {
2206 
2207   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2208   pass_arg2(this, arg_2);
2209   pass_arg1(this, arg_1);
2210   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2211 }
2212 
2213 void MacroAssembler::call_VM(Register oop_result,
2214                              Register last_java_sp,
2215                              address entry_point,
2216                              Register arg_1,
2217                              Register arg_2,
2218                              Register arg_3,
2219                              bool check_exceptions) {
2220   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2221   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2222   pass_arg3(this, arg_3);
2223   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2224   pass_arg2(this, arg_2);
2225   pass_arg1(this, arg_1);
2226   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2227 }
2228 
2229 void MacroAssembler::super_call_VM(Register oop_result,
2230                                    Register last_java_sp,
2231                                    address entry_point,
2232                                    int number_of_arguments,
2233                                    bool check_exceptions) {
2234   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2235   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2236 }
2237 
2238 void MacroAssembler::super_call_VM(Register oop_result,
2239                                    Register last_java_sp,
2240                                    address entry_point,
2241                                    Register arg_1,
2242                                    bool check_exceptions) {
2243   pass_arg1(this, arg_1);
2244   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2245 }
2246 
2247 void MacroAssembler::super_call_VM(Register oop_result,
2248                                    Register last_java_sp,
2249                                    address entry_point,
2250                                    Register arg_1,
2251                                    Register arg_2,
2252                                    bool check_exceptions) {
2253 
2254   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2255   pass_arg2(this, arg_2);
2256   pass_arg1(this, arg_1);
2257   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2258 }
2259 
2260 void MacroAssembler::super_call_VM(Register oop_result,
2261                                    Register last_java_sp,
2262                                    address entry_point,
2263                                    Register arg_1,
2264                                    Register arg_2,
2265                                    Register arg_3,
2266                                    bool check_exceptions) {
2267   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2268   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2269   pass_arg3(this, arg_3);
2270   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2271   pass_arg2(this, arg_2);
2272   pass_arg1(this, arg_1);
2273   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2274 }
2275 
2276 void MacroAssembler::call_VM_base(Register oop_result,
2277                                   Register java_thread,
2278                                   Register last_java_sp,
2279                                   address  entry_point,
2280                                   int      number_of_arguments,
2281                                   bool     check_exceptions) {
2282   // determine java_thread register
2283   if (!java_thread->is_valid()) {
2284 #ifdef _LP64
2285     java_thread = r15_thread;
2286 #else
2287     java_thread = rdi;
2288     get_thread(java_thread);
2289 #endif // LP64
2290   }
2291   // determine last_java_sp register
2292   if (!last_java_sp->is_valid()) {
2293     last_java_sp = rsp;
2294   }
2295   // debugging support
2296   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
2297   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2298 #ifdef ASSERT
2299   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2300   // r12 is the heapbase.
2301   LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2302 #endif // ASSERT
2303 
2304   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
2305   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2306 
2307   // push java thread (becomes first argument of C function)
2308 
2309   NOT_LP64(push(java_thread); number_of_arguments++);
2310   LP64_ONLY(mov(c_rarg0, r15_thread));
2311 
2312   // set last Java frame before call
2313   assert(last_java_sp != rbp, "can't use ebp/rbp");
2314 
2315   // Only interpreter should have to set fp
2316   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2317 
2318   // do the call, remove parameters
2319   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2320 
2321   // restore the thread (cannot use the pushed argument since arguments
2322   // may be overwritten by C code generated by an optimizing compiler);
2323   // however can use the register value directly if it is callee saved.
2324   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2325     // rdi & rsi (also r15) are callee saved -> nothing to do
2326 #ifdef ASSERT
2327     guarantee(java_thread != rax, "change this code");
2328     push(rax);
2329     { Label L;
2330       get_thread(rax);
2331       cmpptr(java_thread, rax);
2332       jcc(Assembler::equal, L);
2333       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2334       bind(L);
2335     }
2336     pop(rax);
2337 #endif
2338   } else {
2339     get_thread(java_thread);
2340   }
2341   // reset last Java frame
2342   // Only interpreter should have to clear fp
2343   reset_last_Java_frame(java_thread, true);
2344 
2345    // C++ interp handles this in the interpreter
2346   check_and_handle_popframe(java_thread);
2347   check_and_handle_earlyret(java_thread);
2348 
2349   if (check_exceptions) {
2350     // check for pending exceptions (java_thread is set upon return)
2351     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2352 #ifndef _LP64
2353     jump_cc(Assembler::notEqual,
2354             RuntimeAddress(StubRoutines::forward_exception_entry()));
2355 #else
2356     // This used to conditionally jump to forward_exception however it is
2357     // possible if we relocate that the branch will not reach. So we must jump
2358     // around so we can always reach
2359 
2360     Label ok;
2361     jcc(Assembler::equal, ok);
2362     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2363     bind(ok);
2364 #endif // LP64
2365   }
2366 
2367   // get oop result if there is one and reset the value in the thread
2368   if (oop_result->is_valid()) {
2369     get_vm_result(oop_result, java_thread);
2370   }
2371 }
2372 
2373 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2374 
2375   // Calculate the value for last_Java_sp
2376   // somewhat subtle. call_VM does an intermediate call
2377   // which places a return address on the stack just under the
2378   // stack pointer as the user finsihed with it. This allows
2379   // use to retrieve last_Java_pc from last_Java_sp[-1].
2380   // On 32bit we then have to push additional args on the stack to accomplish
2381   // the actual requested call. On 64bit call_VM only can use register args
2382   // so the only extra space is the return address that call_VM created.
2383   // This hopefully explains the calculations here.
2384 
2385 #ifdef _LP64
2386   // We've pushed one address, correct last_Java_sp
2387   lea(rax, Address(rsp, wordSize));
2388 #else
2389   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2390 #endif // LP64
2391 
2392   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2393 
2394 }
2395 
2396 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2397 void MacroAssembler::call_VM_leaf0(address entry_point) {
2398   MacroAssembler::call_VM_leaf_base(entry_point, 0);
2399 }
2400 
2401 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2402   call_VM_leaf_base(entry_point, number_of_arguments);
2403 }
2404 
2405 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2406   pass_arg0(this, arg_0);
2407   call_VM_leaf(entry_point, 1);
2408 }
2409 
2410 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2411 
2412   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2413   pass_arg1(this, arg_1);
2414   pass_arg0(this, arg_0);
2415   call_VM_leaf(entry_point, 2);
2416 }
2417 
2418 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2419   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2420   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2421   pass_arg2(this, arg_2);
2422   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2423   pass_arg1(this, arg_1);
2424   pass_arg0(this, arg_0);
2425   call_VM_leaf(entry_point, 3);
2426 }
2427 
2428 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2429   pass_arg0(this, arg_0);
2430   MacroAssembler::call_VM_leaf_base(entry_point, 1);
2431 }
2432 
2433 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2434 
2435   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2436   pass_arg1(this, arg_1);
2437   pass_arg0(this, arg_0);
2438   MacroAssembler::call_VM_leaf_base(entry_point, 2);
2439 }
2440 
2441 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2442   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2443   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2444   pass_arg2(this, arg_2);
2445   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2446   pass_arg1(this, arg_1);
2447   pass_arg0(this, arg_0);
2448   MacroAssembler::call_VM_leaf_base(entry_point, 3);
2449 }
2450 
2451 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2452   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2453   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2454   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2455   pass_arg3(this, arg_3);
2456   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2457   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2458   pass_arg2(this, arg_2);
2459   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2460   pass_arg1(this, arg_1);
2461   pass_arg0(this, arg_0);
2462   MacroAssembler::call_VM_leaf_base(entry_point, 4);
2463 }
2464 
2465 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2466   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2467   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2468   verify_oop(oop_result, "broken oop in call_VM_base");
2469 }
2470 
2471 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2472   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2473   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2474 }
2475 
2476 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2477 }
2478 
2479 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2480 }
2481 
2482 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2483   if (reachable(src1)) {
2484     cmpl(as_Address(src1), imm);
2485   } else {
2486     lea(rscratch1, src1);
2487     cmpl(Address(rscratch1, 0), imm);
2488   }
2489 }
2490 
2491 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2492   assert(!src2.is_lval(), "use cmpptr");
2493   if (reachable(src2)) {
2494     cmpl(src1, as_Address(src2));
2495   } else {
2496     lea(rscratch1, src2);
2497     cmpl(src1, Address(rscratch1, 0));
2498   }
2499 }
2500 
2501 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2502   Assembler::cmpl(src1, imm);
2503 }
2504 
2505 void MacroAssembler::cmp32(Register src1, Address src2) {
2506   Assembler::cmpl(src1, src2);
2507 }
2508 
2509 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2510   ucomisd(opr1, opr2);
2511 
2512   Label L;
2513   if (unordered_is_less) {
2514     movl(dst, -1);
2515     jcc(Assembler::parity, L);
2516     jcc(Assembler::below , L);
2517     movl(dst, 0);
2518     jcc(Assembler::equal , L);
2519     increment(dst);
2520   } else { // unordered is greater
2521     movl(dst, 1);
2522     jcc(Assembler::parity, L);
2523     jcc(Assembler::above , L);
2524     movl(dst, 0);
2525     jcc(Assembler::equal , L);
2526     decrementl(dst);
2527   }
2528   bind(L);
2529 }
2530 
2531 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2532   ucomiss(opr1, opr2);
2533 
2534   Label L;
2535   if (unordered_is_less) {
2536     movl(dst, -1);
2537     jcc(Assembler::parity, L);
2538     jcc(Assembler::below , L);
2539     movl(dst, 0);
2540     jcc(Assembler::equal , L);
2541     increment(dst);
2542   } else { // unordered is greater
2543     movl(dst, 1);
2544     jcc(Assembler::parity, L);
2545     jcc(Assembler::above , L);
2546     movl(dst, 0);
2547     jcc(Assembler::equal , L);
2548     decrementl(dst);
2549   }
2550   bind(L);
2551 }
2552 
2553 
2554 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2555   if (reachable(src1)) {
2556     cmpb(as_Address(src1), imm);
2557   } else {
2558     lea(rscratch1, src1);
2559     cmpb(Address(rscratch1, 0), imm);
2560   }
2561 }
2562 
2563 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2564 #ifdef _LP64
2565   if (src2.is_lval()) {
2566     movptr(rscratch1, src2);
2567     Assembler::cmpq(src1, rscratch1);
2568   } else if (reachable(src2)) {
2569     cmpq(src1, as_Address(src2));
2570   } else {
2571     lea(rscratch1, src2);
2572     Assembler::cmpq(src1, Address(rscratch1, 0));
2573   }
2574 #else
2575   if (src2.is_lval()) {
2576     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2577   } else {
2578     cmpl(src1, as_Address(src2));
2579   }
2580 #endif // _LP64
2581 }
2582 
2583 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2584   assert(src2.is_lval(), "not a mem-mem compare");
2585 #ifdef _LP64
2586   // moves src2's literal address
2587   movptr(rscratch1, src2);
2588   Assembler::cmpq(src1, rscratch1);
2589 #else
2590   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2591 #endif // _LP64
2592 }
2593 
2594 void MacroAssembler::cmpoop(Register src1, Register src2) {
2595   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2596   bs->obj_equals(this, src1, src2);
2597 }
2598 
2599 void MacroAssembler::cmpoop(Register src1, Address src2) {
2600   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2601   bs->obj_equals(this, src1, src2);
2602 }
2603 
2604 #ifdef _LP64
2605 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2606   movoop(rscratch1, src2);
2607   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2608   bs->obj_equals(this, src1, rscratch1);
2609 }
2610 #endif
2611 
2612 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2613   if (reachable(adr)) {
2614     lock();
2615     cmpxchgptr(reg, as_Address(adr));
2616   } else {
2617     lea(rscratch1, adr);
2618     lock();
2619     cmpxchgptr(reg, Address(rscratch1, 0));
2620   }
2621 }
2622 
2623 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2624   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2625 }
2626 
2627 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2628   if (reachable(src)) {
2629     Assembler::comisd(dst, as_Address(src));
2630   } else {
2631     lea(rscratch1, src);
2632     Assembler::comisd(dst, Address(rscratch1, 0));
2633   }
2634 }
2635 
2636 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2637   if (reachable(src)) {
2638     Assembler::comiss(dst, as_Address(src));
2639   } else {
2640     lea(rscratch1, src);
2641     Assembler::comiss(dst, Address(rscratch1, 0));
2642   }
2643 }
2644 
2645 
2646 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2647   Condition negated_cond = negate_condition(cond);
2648   Label L;
2649   jcc(negated_cond, L);
2650   pushf(); // Preserve flags
2651   atomic_incl(counter_addr);
2652   popf();
2653   bind(L);
2654 }
2655 
2656 int MacroAssembler::corrected_idivl(Register reg) {
2657   // Full implementation of Java idiv and irem; checks for
2658   // special case as described in JVM spec., p.243 & p.271.
2659   // The function returns the (pc) offset of the idivl
2660   // instruction - may be needed for implicit exceptions.
2661   //
2662   //         normal case                           special case
2663   //
2664   // input : rax,: dividend                         min_int
2665   //         reg: divisor   (may not be rax,/rdx)   -1
2666   //
2667   // output: rax,: quotient  (= rax, idiv reg)       min_int
2668   //         rdx: remainder (= rax, irem reg)       0
2669   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2670   const int min_int = 0x80000000;
2671   Label normal_case, special_case;
2672 
2673   // check for special case
2674   cmpl(rax, min_int);
2675   jcc(Assembler::notEqual, normal_case);
2676   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2677   cmpl(reg, -1);
2678   jcc(Assembler::equal, special_case);
2679 
2680   // handle normal case
2681   bind(normal_case);
2682   cdql();
2683   int idivl_offset = offset();
2684   idivl(reg);
2685 
2686   // normal and special case exit
2687   bind(special_case);
2688 
2689   return idivl_offset;
2690 }
2691 
2692 
2693 
2694 void MacroAssembler::decrementl(Register reg, int value) {
2695   if (value == min_jint) {subl(reg, value) ; return; }
2696   if (value <  0) { incrementl(reg, -value); return; }
2697   if (value == 0) {                        ; return; }
2698   if (value == 1 && UseIncDec) { decl(reg) ; return; }
2699   /* else */      { subl(reg, value)       ; return; }
2700 }
2701 
2702 void MacroAssembler::decrementl(Address dst, int value) {
2703   if (value == min_jint) {subl(dst, value) ; return; }
2704   if (value <  0) { incrementl(dst, -value); return; }
2705   if (value == 0) {                        ; return; }
2706   if (value == 1 && UseIncDec) { decl(dst) ; return; }
2707   /* else */      { subl(dst, value)       ; return; }
2708 }
2709 
2710 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2711   assert (shift_value > 0, "illegal shift value");
2712   Label _is_positive;
2713   testl (reg, reg);
2714   jcc (Assembler::positive, _is_positive);
2715   int offset = (1 << shift_value) - 1 ;
2716 
2717   if (offset == 1) {
2718     incrementl(reg);
2719   } else {
2720     addl(reg, offset);
2721   }
2722 
2723   bind (_is_positive);
2724   sarl(reg, shift_value);
2725 }
2726 
2727 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2728   if (reachable(src)) {
2729     Assembler::divsd(dst, as_Address(src));
2730   } else {
2731     lea(rscratch1, src);
2732     Assembler::divsd(dst, Address(rscratch1, 0));
2733   }
2734 }
2735 
2736 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2737   if (reachable(src)) {
2738     Assembler::divss(dst, as_Address(src));
2739   } else {
2740     lea(rscratch1, src);
2741     Assembler::divss(dst, Address(rscratch1, 0));
2742   }
2743 }
2744 
2745 // !defined(COMPILER2) is because of stupid core builds
2746 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2747 void MacroAssembler::empty_FPU_stack() {
2748   if (VM_Version::supports_mmx()) {
2749     emms();
2750   } else {
2751     for (int i = 8; i-- > 0; ) ffree(i);
2752   }
2753 }
2754 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2755 
2756 
2757 void MacroAssembler::enter() {
2758   push(rbp);
2759   mov(rbp, rsp);
2760 }
2761 
2762 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2763 void MacroAssembler::fat_nop() {
2764   if (UseAddressNop) {
2765     addr_nop_5();
2766   } else {
2767     emit_int8(0x26); // es:
2768     emit_int8(0x2e); // cs:
2769     emit_int8(0x64); // fs:
2770     emit_int8(0x65); // gs:
2771     emit_int8((unsigned char)0x90);
2772   }
2773 }
2774 
2775 void MacroAssembler::fcmp(Register tmp) {
2776   fcmp(tmp, 1, true, true);
2777 }
2778 
2779 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2780   assert(!pop_right || pop_left, "usage error");
2781   if (VM_Version::supports_cmov()) {
2782     assert(tmp == noreg, "unneeded temp");
2783     if (pop_left) {
2784       fucomip(index);
2785     } else {
2786       fucomi(index);
2787     }
2788     if (pop_right) {
2789       fpop();
2790     }
2791   } else {
2792     assert(tmp != noreg, "need temp");
2793     if (pop_left) {
2794       if (pop_right) {
2795         fcompp();
2796       } else {
2797         fcomp(index);
2798       }
2799     } else {
2800       fcom(index);
2801     }
2802     // convert FPU condition into eflags condition via rax,
2803     save_rax(tmp);
2804     fwait(); fnstsw_ax();
2805     sahf();
2806     restore_rax(tmp);
2807   }
2808   // condition codes set as follows:
2809   //
2810   // CF (corresponds to C0) if x < y
2811   // PF (corresponds to C2) if unordered
2812   // ZF (corresponds to C3) if x = y
2813 }
2814 
2815 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2816   fcmp2int(dst, unordered_is_less, 1, true, true);
2817 }
2818 
2819 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2820   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2821   Label L;
2822   if (unordered_is_less) {
2823     movl(dst, -1);
2824     jcc(Assembler::parity, L);
2825     jcc(Assembler::below , L);
2826     movl(dst, 0);
2827     jcc(Assembler::equal , L);
2828     increment(dst);
2829   } else { // unordered is greater
2830     movl(dst, 1);
2831     jcc(Assembler::parity, L);
2832     jcc(Assembler::above , L);
2833     movl(dst, 0);
2834     jcc(Assembler::equal , L);
2835     decrementl(dst);
2836   }
2837   bind(L);
2838 }
2839 
2840 void MacroAssembler::fld_d(AddressLiteral src) {
2841   fld_d(as_Address(src));
2842 }
2843 
2844 void MacroAssembler::fld_s(AddressLiteral src) {
2845   fld_s(as_Address(src));
2846 }
2847 
2848 void MacroAssembler::fld_x(AddressLiteral src) {
2849   Assembler::fld_x(as_Address(src));
2850 }
2851 
2852 void MacroAssembler::fldcw(AddressLiteral src) {
2853   Assembler::fldcw(as_Address(src));
2854 }
2855 
2856 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2857   if (reachable(src)) {
2858     Assembler::mulpd(dst, as_Address(src));
2859   } else {
2860     lea(rscratch1, src);
2861     Assembler::mulpd(dst, Address(rscratch1, 0));
2862   }
2863 }
2864 
2865 void MacroAssembler::increase_precision() {
2866   subptr(rsp, BytesPerWord);
2867   fnstcw(Address(rsp, 0));
2868   movl(rax, Address(rsp, 0));
2869   orl(rax, 0x300);
2870   push(rax);
2871   fldcw(Address(rsp, 0));
2872   pop(rax);
2873 }
2874 
2875 void MacroAssembler::restore_precision() {
2876   fldcw(Address(rsp, 0));
2877   addptr(rsp, BytesPerWord);
2878 }
2879 
2880 void MacroAssembler::fpop() {
2881   ffree();
2882   fincstp();
2883 }
2884 
2885 void MacroAssembler::load_float(Address src) {
2886   if (UseSSE >= 1) {
2887     movflt(xmm0, src);
2888   } else {
2889     LP64_ONLY(ShouldNotReachHere());
2890     NOT_LP64(fld_s(src));
2891   }
2892 }
2893 
2894 void MacroAssembler::store_float(Address dst) {
2895   if (UseSSE >= 1) {
2896     movflt(dst, xmm0);
2897   } else {
2898     LP64_ONLY(ShouldNotReachHere());
2899     NOT_LP64(fstp_s(dst));
2900   }
2901 }
2902 
2903 void MacroAssembler::load_double(Address src) {
2904   if (UseSSE >= 2) {
2905     movdbl(xmm0, src);
2906   } else {
2907     LP64_ONLY(ShouldNotReachHere());
2908     NOT_LP64(fld_d(src));
2909   }
2910 }
2911 
2912 void MacroAssembler::store_double(Address dst) {
2913   if (UseSSE >= 2) {
2914     movdbl(dst, xmm0);
2915   } else {
2916     LP64_ONLY(ShouldNotReachHere());
2917     NOT_LP64(fstp_d(dst));
2918   }
2919 }
2920 
2921 void MacroAssembler::fremr(Register tmp) {
2922   save_rax(tmp);
2923   { Label L;
2924     bind(L);
2925     fprem();
2926     fwait(); fnstsw_ax();
2927 #ifdef _LP64
2928     testl(rax, 0x400);
2929     jcc(Assembler::notEqual, L);
2930 #else
2931     sahf();
2932     jcc(Assembler::parity, L);
2933 #endif // _LP64
2934   }
2935   restore_rax(tmp);
2936   // Result is in ST0.
2937   // Note: fxch & fpop to get rid of ST1
2938   // (otherwise FPU stack could overflow eventually)
2939   fxch(1);
2940   fpop();
2941 }
2942 
2943 // dst = c = a * b + c
2944 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2945   Assembler::vfmadd231sd(c, a, b);
2946   if (dst != c) {
2947     movdbl(dst, c);
2948   }
2949 }
2950 
2951 // dst = c = a * b + c
2952 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2953   Assembler::vfmadd231ss(c, a, b);
2954   if (dst != c) {
2955     movflt(dst, c);
2956   }
2957 }
2958 
2959 // dst = c = a * b + c
2960 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2961   Assembler::vfmadd231pd(c, a, b, vector_len);
2962   if (dst != c) {
2963     vmovdqu(dst, c);
2964   }
2965 }
2966 
2967 // dst = c = a * b + c
2968 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2969   Assembler::vfmadd231ps(c, a, b, vector_len);
2970   if (dst != c) {
2971     vmovdqu(dst, c);
2972   }
2973 }
2974 
2975 // dst = c = a * b + c
2976 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2977   Assembler::vfmadd231pd(c, a, b, vector_len);
2978   if (dst != c) {
2979     vmovdqu(dst, c);
2980   }
2981 }
2982 
2983 // dst = c = a * b + c
2984 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2985   Assembler::vfmadd231ps(c, a, b, vector_len);
2986   if (dst != c) {
2987     vmovdqu(dst, c);
2988   }
2989 }
2990 
2991 void MacroAssembler::incrementl(AddressLiteral dst) {
2992   if (reachable(dst)) {
2993     incrementl(as_Address(dst));
2994   } else {
2995     lea(rscratch1, dst);
2996     incrementl(Address(rscratch1, 0));
2997   }
2998 }
2999 
3000 void MacroAssembler::incrementl(ArrayAddress dst) {
3001   incrementl(as_Address(dst));
3002 }
3003 
3004 void MacroAssembler::incrementl(Register reg, int value) {
3005   if (value == min_jint) {addl(reg, value) ; return; }
3006   if (value <  0) { decrementl(reg, -value); return; }
3007   if (value == 0) {                        ; return; }
3008   if (value == 1 && UseIncDec) { incl(reg) ; return; }
3009   /* else */      { addl(reg, value)       ; return; }
3010 }
3011 
3012 void MacroAssembler::incrementl(Address dst, int value) {
3013   if (value == min_jint) {addl(dst, value) ; return; }
3014   if (value <  0) { decrementl(dst, -value); return; }
3015   if (value == 0) {                        ; return; }
3016   if (value == 1 && UseIncDec) { incl(dst) ; return; }
3017   /* else */      { addl(dst, value)       ; return; }
3018 }
3019 
3020 void MacroAssembler::jump(AddressLiteral dst) {
3021   if (reachable(dst)) {
3022     jmp_literal(dst.target(), dst.rspec());
3023   } else {
3024     lea(rscratch1, dst);
3025     jmp(rscratch1);
3026   }
3027 }
3028 
3029 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3030   if (reachable(dst)) {
3031     InstructionMark im(this);
3032     relocate(dst.reloc());
3033     const int short_size = 2;
3034     const int long_size = 6;
3035     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3036     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3037       // 0111 tttn #8-bit disp
3038       emit_int8(0x70 | cc);
3039       emit_int8((offs - short_size) & 0xFF);
3040     } else {
3041       // 0000 1111 1000 tttn #32-bit disp
3042       emit_int8(0x0F);
3043       emit_int8((unsigned char)(0x80 | cc));
3044       emit_int32(offs - long_size);
3045     }
3046   } else {
3047 #ifdef ASSERT
3048     warning("reversing conditional branch");
3049 #endif /* ASSERT */
3050     Label skip;
3051     jccb(reverse[cc], skip);
3052     lea(rscratch1, dst);
3053     Assembler::jmp(rscratch1);
3054     bind(skip);
3055   }
3056 }
3057 
3058 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3059   if (reachable(src)) {
3060     Assembler::ldmxcsr(as_Address(src));
3061   } else {
3062     lea(rscratch1, src);
3063     Assembler::ldmxcsr(Address(rscratch1, 0));
3064   }
3065 }
3066 
3067 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3068   int off;
3069   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3070     off = offset();
3071     movsbl(dst, src); // movsxb
3072   } else {
3073     off = load_unsigned_byte(dst, src);
3074     shll(dst, 24);
3075     sarl(dst, 24);
3076   }
3077   return off;
3078 }
3079 
3080 // Note: load_signed_short used to be called load_signed_word.
3081 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3082 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3083 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3084 int MacroAssembler::load_signed_short(Register dst, Address src) {
3085   int off;
3086   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3087     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3088     // version but this is what 64bit has always done. This seems to imply
3089     // that users are only using 32bits worth.
3090     off = offset();
3091     movswl(dst, src); // movsxw
3092   } else {
3093     off = load_unsigned_short(dst, src);
3094     shll(dst, 16);
3095     sarl(dst, 16);
3096   }
3097   return off;
3098 }
3099 
3100 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3101   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3102   // and "3.9 Partial Register Penalties", p. 22).
3103   int off;
3104   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3105     off = offset();
3106     movzbl(dst, src); // movzxb
3107   } else {
3108     xorl(dst, dst);
3109     off = offset();
3110     movb(dst, src);
3111   }
3112   return off;
3113 }
3114 
3115 // Note: load_unsigned_short used to be called load_unsigned_word.
3116 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3117   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3118   // and "3.9 Partial Register Penalties", p. 22).
3119   int off;
3120   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3121     off = offset();
3122     movzwl(dst, src); // movzxw
3123   } else {
3124     xorl(dst, dst);
3125     off = offset();
3126     movw(dst, src);
3127   }
3128   return off;
3129 }
3130 
3131 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3132   switch (size_in_bytes) {
3133 #ifndef _LP64
3134   case  8:
3135     assert(dst2 != noreg, "second dest register required");
3136     movl(dst,  src);
3137     movl(dst2, src.plus_disp(BytesPerInt));
3138     break;
3139 #else
3140   case  8:  movq(dst, src); break;
3141 #endif
3142   case  4:  movl(dst, src); break;
3143   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3144   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3145   default:  ShouldNotReachHere();
3146   }
3147 }
3148 
3149 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3150   switch (size_in_bytes) {
3151 #ifndef _LP64
3152   case  8:
3153     assert(src2 != noreg, "second source register required");
3154     movl(dst,                        src);
3155     movl(dst.plus_disp(BytesPerInt), src2);
3156     break;
3157 #else
3158   case  8:  movq(dst, src); break;
3159 #endif
3160   case  4:  movl(dst, src); break;
3161   case  2:  movw(dst, src); break;
3162   case  1:  movb(dst, src); break;
3163   default:  ShouldNotReachHere();
3164   }
3165 }
3166 
3167 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3168   if (reachable(dst)) {
3169     movl(as_Address(dst), src);
3170   } else {
3171     lea(rscratch1, dst);
3172     movl(Address(rscratch1, 0), src);
3173   }
3174 }
3175 
3176 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3177   if (reachable(src)) {
3178     movl(dst, as_Address(src));
3179   } else {
3180     lea(rscratch1, src);
3181     movl(dst, Address(rscratch1, 0));
3182   }
3183 }
3184 
3185 // C++ bool manipulation
3186 
3187 void MacroAssembler::movbool(Register dst, Address src) {
3188   if(sizeof(bool) == 1)
3189     movb(dst, src);
3190   else if(sizeof(bool) == 2)
3191     movw(dst, src);
3192   else if(sizeof(bool) == 4)
3193     movl(dst, src);
3194   else
3195     // unsupported
3196     ShouldNotReachHere();
3197 }
3198 
3199 void MacroAssembler::movbool(Address dst, bool boolconst) {
3200   if(sizeof(bool) == 1)
3201     movb(dst, (int) boolconst);
3202   else if(sizeof(bool) == 2)
3203     movw(dst, (int) boolconst);
3204   else if(sizeof(bool) == 4)
3205     movl(dst, (int) boolconst);
3206   else
3207     // unsupported
3208     ShouldNotReachHere();
3209 }
3210 
3211 void MacroAssembler::movbool(Address dst, Register src) {
3212   if(sizeof(bool) == 1)
3213     movb(dst, src);
3214   else if(sizeof(bool) == 2)
3215     movw(dst, src);
3216   else if(sizeof(bool) == 4)
3217     movl(dst, src);
3218   else
3219     // unsupported
3220     ShouldNotReachHere();
3221 }
3222 
3223 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3224   movb(as_Address(dst), src);
3225 }
3226 
3227 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3228   if (reachable(src)) {
3229     movdl(dst, as_Address(src));
3230   } else {
3231     lea(rscratch1, src);
3232     movdl(dst, Address(rscratch1, 0));
3233   }
3234 }
3235 
3236 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3237   if (reachable(src)) {
3238     movq(dst, as_Address(src));
3239   } else {
3240     lea(rscratch1, src);
3241     movq(dst, Address(rscratch1, 0));
3242   }
3243 }
3244 
3245 #ifdef COMPILER2
3246 void MacroAssembler::setvectmask(Register dst, Register src) {
3247   guarantee(PostLoopMultiversioning, "must be");
3248   Assembler::movl(dst, 1);
3249   Assembler::shlxl(dst, dst, src);
3250   Assembler::decl(dst);
3251   Assembler::kmovdl(k1, dst);
3252   Assembler::movl(dst, src);
3253 }
3254 
3255 void MacroAssembler::restorevectmask() {
3256   guarantee(PostLoopMultiversioning, "must be");
3257   Assembler::knotwl(k1, k0);
3258 }
3259 #endif // COMPILER2
3260 
3261 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3262   if (reachable(src)) {
3263     if (UseXmmLoadAndClearUpper) {
3264       movsd (dst, as_Address(src));
3265     } else {
3266       movlpd(dst, as_Address(src));
3267     }
3268   } else {
3269     lea(rscratch1, src);
3270     if (UseXmmLoadAndClearUpper) {
3271       movsd (dst, Address(rscratch1, 0));
3272     } else {
3273       movlpd(dst, Address(rscratch1, 0));
3274     }
3275   }
3276 }
3277 
3278 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3279   if (reachable(src)) {
3280     movss(dst, as_Address(src));
3281   } else {
3282     lea(rscratch1, src);
3283     movss(dst, Address(rscratch1, 0));
3284   }
3285 }
3286 
3287 void MacroAssembler::movptr(Register dst, Register src) {
3288   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3289 }
3290 
3291 void MacroAssembler::movptr(Register dst, Address src) {
3292   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3293 }
3294 
3295 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3296 void MacroAssembler::movptr(Register dst, intptr_t src) {
3297   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3298 }
3299 
3300 void MacroAssembler::movptr(Address dst, Register src) {
3301   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3302 }
3303 
3304 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3305     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3306     Assembler::movdqu(dst, src);
3307 }
3308 
3309 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3310     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3311     Assembler::movdqu(dst, src);
3312 }
3313 
3314 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3315     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3316     Assembler::movdqu(dst, src);
3317 }
3318 
3319 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3320   if (reachable(src)) {
3321     movdqu(dst, as_Address(src));
3322   } else {
3323     lea(scratchReg, src);
3324     movdqu(dst, Address(scratchReg, 0));
3325   }
3326 }
3327 
3328 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3329     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3330     Assembler::vmovdqu(dst, src);
3331 }
3332 
3333 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3334     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3335     Assembler::vmovdqu(dst, src);
3336 }
3337 
3338 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3339     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3340     Assembler::vmovdqu(dst, src);
3341 }
3342 
3343 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3344   if (reachable(src)) {
3345     vmovdqu(dst, as_Address(src));
3346   }
3347   else {
3348     lea(rscratch1, src);
3349     vmovdqu(dst, Address(rscratch1, 0));
3350   }
3351 }
3352 
3353 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3354   if (reachable(src)) {
3355     Assembler::evmovdquq(dst, as_Address(src), vector_len);
3356   } else {
3357     lea(rscratch, src);
3358     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3359   }
3360 }
3361 
3362 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3363   if (reachable(src)) {
3364     Assembler::movdqa(dst, as_Address(src));
3365   } else {
3366     lea(rscratch1, src);
3367     Assembler::movdqa(dst, Address(rscratch1, 0));
3368   }
3369 }
3370 
3371 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3372   if (reachable(src)) {
3373     Assembler::movsd(dst, as_Address(src));
3374   } else {
3375     lea(rscratch1, src);
3376     Assembler::movsd(dst, Address(rscratch1, 0));
3377   }
3378 }
3379 
3380 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3381   if (reachable(src)) {
3382     Assembler::movss(dst, as_Address(src));
3383   } else {
3384     lea(rscratch1, src);
3385     Assembler::movss(dst, Address(rscratch1, 0));
3386   }
3387 }
3388 
3389 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3390   if (reachable(src)) {
3391     Assembler::mulsd(dst, as_Address(src));
3392   } else {
3393     lea(rscratch1, src);
3394     Assembler::mulsd(dst, Address(rscratch1, 0));
3395   }
3396 }
3397 
3398 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3399   if (reachable(src)) {
3400     Assembler::mulss(dst, as_Address(src));
3401   } else {
3402     lea(rscratch1, src);
3403     Assembler::mulss(dst, Address(rscratch1, 0));
3404   }
3405 }
3406 
3407 void MacroAssembler::null_check(Register reg, int offset) {
3408   if (needs_explicit_null_check(offset)) {
3409     // provoke OS NULL exception if reg = NULL by
3410     // accessing M[reg] w/o changing any (non-CC) registers
3411     // NOTE: cmpl is plenty here to provoke a segv
3412     cmpptr(rax, Address(reg, 0));
3413     // Note: should probably use testl(rax, Address(reg, 0));
3414     //       may be shorter code (however, this version of
3415     //       testl needs to be implemented first)
3416   } else {
3417     // nothing to do, (later) access of M[reg + offset]
3418     // will provoke OS NULL exception if reg = NULL
3419   }
3420 }
3421 
3422 void MacroAssembler::os_breakpoint() {
3423   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3424   // (e.g., MSVC can't call ps() otherwise)
3425   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3426 }
3427 
3428 void MacroAssembler::unimplemented(const char* what) {
3429   const char* buf = NULL;
3430   {
3431     ResourceMark rm;
3432     stringStream ss;
3433     ss.print("unimplemented: %s", what);
3434     buf = code_string(ss.as_string());
3435   }
3436   stop(buf);
3437 }
3438 
3439 #ifdef _LP64
3440 #define XSTATE_BV 0x200
3441 #endif
3442 
3443 void MacroAssembler::pop_CPU_state() {
3444   pop_FPU_state();
3445   pop_IU_state();
3446 }
3447 
3448 void MacroAssembler::pop_FPU_state() {
3449 #ifndef _LP64
3450   frstor(Address(rsp, 0));
3451 #else
3452   fxrstor(Address(rsp, 0));
3453 #endif
3454   addptr(rsp, FPUStateSizeInWords * wordSize);
3455 }
3456 
3457 void MacroAssembler::pop_IU_state() {
3458   popa();
3459   LP64_ONLY(addq(rsp, 8));
3460   popf();
3461 }
3462 
3463 // Save Integer and Float state
3464 // Warning: Stack must be 16 byte aligned (64bit)
3465 void MacroAssembler::push_CPU_state() {
3466   push_IU_state();
3467   push_FPU_state();
3468 }
3469 
3470 void MacroAssembler::push_FPU_state() {
3471   subptr(rsp, FPUStateSizeInWords * wordSize);
3472 #ifndef _LP64
3473   fnsave(Address(rsp, 0));
3474   fwait();
3475 #else
3476   fxsave(Address(rsp, 0));
3477 #endif // LP64
3478 }
3479 
3480 void MacroAssembler::push_IU_state() {
3481   // Push flags first because pusha kills them
3482   pushf();
3483   // Make sure rsp stays 16-byte aligned
3484   LP64_ONLY(subq(rsp, 8));
3485   pusha();
3486 }
3487 
3488 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3489   if (!java_thread->is_valid()) {
3490     java_thread = rdi;
3491     get_thread(java_thread);
3492   }
3493   // we must set sp to zero to clear frame
3494   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3495   if (clear_fp) {
3496     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3497   }
3498 
3499   // Always clear the pc because it could have been set by make_walkable()
3500   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3501 
3502   vzeroupper();
3503 }
3504 
3505 void MacroAssembler::restore_rax(Register tmp) {
3506   if (tmp == noreg) pop(rax);
3507   else if (tmp != rax) mov(rax, tmp);
3508 }
3509 
3510 void MacroAssembler::round_to(Register reg, int modulus) {
3511   addptr(reg, modulus - 1);
3512   andptr(reg, -modulus);
3513 }
3514 
3515 void MacroAssembler::save_rax(Register tmp) {
3516   if (tmp == noreg) push(rax);
3517   else if (tmp != rax) mov(tmp, rax);
3518 }
3519 
3520 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3521   if (SafepointMechanism::uses_thread_local_poll()) {
3522 #ifdef _LP64
3523     assert(thread_reg == r15_thread, "should be");
3524 #else
3525     if (thread_reg == noreg) {
3526       thread_reg = temp_reg;
3527       get_thread(thread_reg);
3528     }
3529 #endif
3530     testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3531     jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3532   } else {
3533     cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3534         SafepointSynchronize::_not_synchronized);
3535     jcc(Assembler::notEqual, slow_path);
3536   }
3537 }
3538 
3539 // Calls to C land
3540 //
3541 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3542 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3543 // has to be reset to 0. This is required to allow proper stack traversal.
3544 void MacroAssembler::set_last_Java_frame(Register java_thread,
3545                                          Register last_java_sp,
3546                                          Register last_java_fp,
3547                                          address  last_java_pc) {
3548   vzeroupper();
3549   // determine java_thread register
3550   if (!java_thread->is_valid()) {
3551     java_thread = rdi;
3552     get_thread(java_thread);
3553   }
3554   // determine last_java_sp register
3555   if (!last_java_sp->is_valid()) {
3556     last_java_sp = rsp;
3557   }
3558 
3559   // last_java_fp is optional
3560 
3561   if (last_java_fp->is_valid()) {
3562     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3563   }
3564 
3565   // last_java_pc is optional
3566 
3567   if (last_java_pc != NULL) {
3568     lea(Address(java_thread,
3569                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3570         InternalAddress(last_java_pc));
3571 
3572   }
3573   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3574 }
3575 
3576 void MacroAssembler::shlptr(Register dst, int imm8) {
3577   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3578 }
3579 
3580 void MacroAssembler::shrptr(Register dst, int imm8) {
3581   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3582 }
3583 
3584 void MacroAssembler::sign_extend_byte(Register reg) {
3585   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3586     movsbl(reg, reg); // movsxb
3587   } else {
3588     shll(reg, 24);
3589     sarl(reg, 24);
3590   }
3591 }
3592 
3593 void MacroAssembler::sign_extend_short(Register reg) {
3594   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3595     movswl(reg, reg); // movsxw
3596   } else {
3597     shll(reg, 16);
3598     sarl(reg, 16);
3599   }
3600 }
3601 
3602 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3603   assert(reachable(src), "Address should be reachable");
3604   testl(dst, as_Address(src));
3605 }
3606 
3607 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3608   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3609   Assembler::pcmpeqb(dst, src);
3610 }
3611 
3612 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3613   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3614   Assembler::pcmpeqw(dst, src);
3615 }
3616 
3617 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3618   assert((dst->encoding() < 16),"XMM register should be 0-15");
3619   Assembler::pcmpestri(dst, src, imm8);
3620 }
3621 
3622 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3623   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3624   Assembler::pcmpestri(dst, src, imm8);
3625 }
3626 
3627 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3628   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3629   Assembler::pmovzxbw(dst, src);
3630 }
3631 
3632 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3633   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3634   Assembler::pmovzxbw(dst, src);
3635 }
3636 
3637 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3638   assert((src->encoding() < 16),"XMM register should be 0-15");
3639   Assembler::pmovmskb(dst, src);
3640 }
3641 
3642 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3643   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3644   Assembler::ptest(dst, src);
3645 }
3646 
3647 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3648   if (reachable(src)) {
3649     Assembler::sqrtsd(dst, as_Address(src));
3650   } else {
3651     lea(rscratch1, src);
3652     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3653   }
3654 }
3655 
3656 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3657   if (reachable(src)) {
3658     Assembler::sqrtss(dst, as_Address(src));
3659   } else {
3660     lea(rscratch1, src);
3661     Assembler::sqrtss(dst, Address(rscratch1, 0));
3662   }
3663 }
3664 
3665 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3666   if (reachable(src)) {
3667     Assembler::subsd(dst, as_Address(src));
3668   } else {
3669     lea(rscratch1, src);
3670     Assembler::subsd(dst, Address(rscratch1, 0));
3671   }
3672 }
3673 
3674 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3675   if (reachable(src)) {
3676     Assembler::subss(dst, as_Address(src));
3677   } else {
3678     lea(rscratch1, src);
3679     Assembler::subss(dst, Address(rscratch1, 0));
3680   }
3681 }
3682 
3683 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3684   if (reachable(src)) {
3685     Assembler::ucomisd(dst, as_Address(src));
3686   } else {
3687     lea(rscratch1, src);
3688     Assembler::ucomisd(dst, Address(rscratch1, 0));
3689   }
3690 }
3691 
3692 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3693   if (reachable(src)) {
3694     Assembler::ucomiss(dst, as_Address(src));
3695   } else {
3696     lea(rscratch1, src);
3697     Assembler::ucomiss(dst, Address(rscratch1, 0));
3698   }
3699 }
3700 
3701 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3702   // Used in sign-bit flipping with aligned address.
3703   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3704   if (reachable(src)) {
3705     Assembler::xorpd(dst, as_Address(src));
3706   } else {
3707     lea(rscratch1, src);
3708     Assembler::xorpd(dst, Address(rscratch1, 0));
3709   }
3710 }
3711 
3712 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3713   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3714     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3715   }
3716   else {
3717     Assembler::xorpd(dst, src);
3718   }
3719 }
3720 
3721 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3722   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3723     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3724   } else {
3725     Assembler::xorps(dst, src);
3726   }
3727 }
3728 
3729 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
3730   // Used in sign-bit flipping with aligned address.
3731   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3732   if (reachable(src)) {
3733     Assembler::xorps(dst, as_Address(src));
3734   } else {
3735     lea(rscratch1, src);
3736     Assembler::xorps(dst, Address(rscratch1, 0));
3737   }
3738 }
3739 
3740 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3741   // Used in sign-bit flipping with aligned address.
3742   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3743   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3744   if (reachable(src)) {
3745     Assembler::pshufb(dst, as_Address(src));
3746   } else {
3747     lea(rscratch1, src);
3748     Assembler::pshufb(dst, Address(rscratch1, 0));
3749   }
3750 }
3751 
3752 // AVX 3-operands instructions
3753 
3754 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3755   if (reachable(src)) {
3756     vaddsd(dst, nds, as_Address(src));
3757   } else {
3758     lea(rscratch1, src);
3759     vaddsd(dst, nds, Address(rscratch1, 0));
3760   }
3761 }
3762 
3763 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3764   if (reachable(src)) {
3765     vaddss(dst, nds, as_Address(src));
3766   } else {
3767     lea(rscratch1, src);
3768     vaddss(dst, nds, Address(rscratch1, 0));
3769   }
3770 }
3771 
3772 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3773   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3774   vandps(dst, nds, negate_field, vector_len);
3775 }
3776 
3777 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3778   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3779   vandpd(dst, nds, negate_field, vector_len);
3780 }
3781 
3782 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3783   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3784   Assembler::vpaddb(dst, nds, src, vector_len);
3785 }
3786 
3787 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3788   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3789   Assembler::vpaddb(dst, nds, src, vector_len);
3790 }
3791 
3792 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3793   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3794   Assembler::vpaddw(dst, nds, src, vector_len);
3795 }
3796 
3797 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3798   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3799   Assembler::vpaddw(dst, nds, src, vector_len);
3800 }
3801 
3802 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3803   if (reachable(src)) {
3804     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3805   } else {
3806     lea(rscratch1, src);
3807     Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
3808   }
3809 }
3810 
3811 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3812   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3813   Assembler::vpbroadcastw(dst, src, vector_len);
3814 }
3815 
3816 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3817   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3818   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3819 }
3820 
3821 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3822   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3823   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3824 }
3825 
3826 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3827   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3828   Assembler::vpmovzxbw(dst, src, vector_len);
3829 }
3830 
3831 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3832   assert((src->encoding() < 16),"XMM register should be 0-15");
3833   Assembler::vpmovmskb(dst, src);
3834 }
3835 
3836 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3837   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3838   Assembler::vpmullw(dst, nds, src, vector_len);
3839 }
3840 
3841 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3842   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3843   Assembler::vpmullw(dst, nds, src, vector_len);
3844 }
3845 
3846 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3847   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3848   Assembler::vpsubb(dst, nds, src, vector_len);
3849 }
3850 
3851 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3852   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3853   Assembler::vpsubb(dst, nds, src, vector_len);
3854 }
3855 
3856 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3857   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3858   Assembler::vpsubw(dst, nds, src, vector_len);
3859 }
3860 
3861 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3862   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3863   Assembler::vpsubw(dst, nds, src, vector_len);
3864 }
3865 
3866 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3867   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3868   Assembler::vpsraw(dst, nds, shift, vector_len);
3869 }
3870 
3871 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3872   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3873   Assembler::vpsraw(dst, nds, shift, vector_len);
3874 }
3875 
3876 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3877   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3878   Assembler::vpsrlw(dst, nds, shift, vector_len);
3879 }
3880 
3881 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3882   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3883   Assembler::vpsrlw(dst, nds, shift, vector_len);
3884 }
3885 
3886 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3887   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3888   Assembler::vpsllw(dst, nds, shift, vector_len);
3889 }
3890 
3891 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3892   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3893   Assembler::vpsllw(dst, nds, shift, vector_len);
3894 }
3895 
3896 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3897   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3898   Assembler::vptest(dst, src);
3899 }
3900 
3901 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3902   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3903   Assembler::punpcklbw(dst, src);
3904 }
3905 
3906 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3907   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3908   Assembler::pshufd(dst, src, mode);
3909 }
3910 
3911 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3912   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3913   Assembler::pshuflw(dst, src, mode);
3914 }
3915 
3916 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3917   if (reachable(src)) {
3918     vandpd(dst, nds, as_Address(src), vector_len);
3919   } else {
3920     lea(rscratch1, src);
3921     vandpd(dst, nds, Address(rscratch1, 0), vector_len);
3922   }
3923 }
3924 
3925 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3926   if (reachable(src)) {
3927     vandps(dst, nds, as_Address(src), vector_len);
3928   } else {
3929     lea(rscratch1, src);
3930     vandps(dst, nds, Address(rscratch1, 0), vector_len);
3931   }
3932 }
3933 
3934 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3935   if (reachable(src)) {
3936     vdivsd(dst, nds, as_Address(src));
3937   } else {
3938     lea(rscratch1, src);
3939     vdivsd(dst, nds, Address(rscratch1, 0));
3940   }
3941 }
3942 
3943 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3944   if (reachable(src)) {
3945     vdivss(dst, nds, as_Address(src));
3946   } else {
3947     lea(rscratch1, src);
3948     vdivss(dst, nds, Address(rscratch1, 0));
3949   }
3950 }
3951 
3952 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3953   if (reachable(src)) {
3954     vmulsd(dst, nds, as_Address(src));
3955   } else {
3956     lea(rscratch1, src);
3957     vmulsd(dst, nds, Address(rscratch1, 0));
3958   }
3959 }
3960 
3961 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3962   if (reachable(src)) {
3963     vmulss(dst, nds, as_Address(src));
3964   } else {
3965     lea(rscratch1, src);
3966     vmulss(dst, nds, Address(rscratch1, 0));
3967   }
3968 }
3969 
3970 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3971   if (reachable(src)) {
3972     vsubsd(dst, nds, as_Address(src));
3973   } else {
3974     lea(rscratch1, src);
3975     vsubsd(dst, nds, Address(rscratch1, 0));
3976   }
3977 }
3978 
3979 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3980   if (reachable(src)) {
3981     vsubss(dst, nds, as_Address(src));
3982   } else {
3983     lea(rscratch1, src);
3984     vsubss(dst, nds, Address(rscratch1, 0));
3985   }
3986 }
3987 
3988 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3989   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3990   vxorps(dst, nds, src, Assembler::AVX_128bit);
3991 }
3992 
3993 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3994   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3995   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3996 }
3997 
3998 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
3999   if (reachable(src)) {
4000     vxorpd(dst, nds, as_Address(src), vector_len);
4001   } else {
4002     lea(rscratch1, src);
4003     vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4004   }
4005 }
4006 
4007 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4008   if (reachable(src)) {
4009     vxorps(dst, nds, as_Address(src), vector_len);
4010   } else {
4011     lea(rscratch1, src);
4012     vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4013   }
4014 }
4015 
4016 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4017   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4018   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4019   // The inverted mask is sign-extended
4020   andptr(possibly_jweak, inverted_jweak_mask);
4021 }
4022 
4023 void MacroAssembler::resolve_jobject(Register value,
4024                                      Register thread,
4025                                      Register tmp) {
4026   assert_different_registers(value, thread, tmp);
4027   Label done, not_weak;
4028   testptr(value, value);
4029   jcc(Assembler::zero, done);                // Use NULL as-is.
4030   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4031   jcc(Assembler::zero, not_weak);
4032   // Resolve jweak.
4033   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4034                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4035   verify_oop(value);
4036   jmp(done);
4037   bind(not_weak);
4038   // Resolve (untagged) jobject.
4039   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4040   verify_oop(value);
4041   bind(done);
4042 }
4043 
4044 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4045   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4046 }
4047 
4048 // Force generation of a 4 byte immediate value even if it fits into 8bit
4049 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4050   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4051 }
4052 
4053 void MacroAssembler::subptr(Register dst, Register src) {
4054   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4055 }
4056 
4057 // C++ bool manipulation
4058 void MacroAssembler::testbool(Register dst) {
4059   if(sizeof(bool) == 1)
4060     testb(dst, 0xff);
4061   else if(sizeof(bool) == 2) {
4062     // testw implementation needed for two byte bools
4063     ShouldNotReachHere();
4064   } else if(sizeof(bool) == 4)
4065     testl(dst, dst);
4066   else
4067     // unsupported
4068     ShouldNotReachHere();
4069 }
4070 
4071 void MacroAssembler::testptr(Register dst, Register src) {
4072   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4073 }
4074 
4075 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4076 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4077                                    Register var_size_in_bytes,
4078                                    int con_size_in_bytes,
4079                                    Register t1,
4080                                    Register t2,
4081                                    Label& slow_case) {
4082   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4083   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4084 }
4085 
4086 // Defines obj, preserves var_size_in_bytes
4087 void MacroAssembler::eden_allocate(Register thread, Register obj,
4088                                    Register var_size_in_bytes,
4089                                    int con_size_in_bytes,
4090                                    Register t1,
4091                                    Label& slow_case) {
4092   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4093   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4094 }
4095 
4096 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4097 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4098   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4099   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4100   Label done;
4101 
4102   testptr(length_in_bytes, length_in_bytes);
4103   jcc(Assembler::zero, done);
4104 
4105   // initialize topmost word, divide index by 2, check if odd and test if zero
4106   // note: for the remaining code to work, index must be a multiple of BytesPerWord
4107 #ifdef ASSERT
4108   {
4109     Label L;
4110     testptr(length_in_bytes, BytesPerWord - 1);
4111     jcc(Assembler::zero, L);
4112     stop("length must be a multiple of BytesPerWord");
4113     bind(L);
4114   }
4115 #endif
4116   Register index = length_in_bytes;
4117   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
4118   if (UseIncDec) {
4119     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
4120   } else {
4121     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
4122     shrptr(index, 1);
4123   }
4124 #ifndef _LP64
4125   // index could have not been a multiple of 8 (i.e., bit 2 was set)
4126   {
4127     Label even;
4128     // note: if index was a multiple of 8, then it cannot
4129     //       be 0 now otherwise it must have been 0 before
4130     //       => if it is even, we don't need to check for 0 again
4131     jcc(Assembler::carryClear, even);
4132     // clear topmost word (no jump would be needed if conditional assignment worked here)
4133     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4134     // index could be 0 now, must check again
4135     jcc(Assembler::zero, done);
4136     bind(even);
4137   }
4138 #endif // !_LP64
4139   // initialize remaining object fields: index is a multiple of 2 now
4140   {
4141     Label loop;
4142     bind(loop);
4143     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4144     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4145     decrement(index);
4146     jcc(Assembler::notZero, loop);
4147   }
4148 
4149   bind(done);
4150 }
4151 
4152 // Look up the method for a megamorphic invokeinterface call.
4153 // The target method is determined by <intf_klass, itable_index>.
4154 // The receiver klass is in recv_klass.
4155 // On success, the result will be in method_result, and execution falls through.
4156 // On failure, execution transfers to the given label.
4157 void MacroAssembler::lookup_interface_method(Register recv_klass,
4158                                              Register intf_klass,
4159                                              RegisterOrConstant itable_index,
4160                                              Register method_result,
4161                                              Register scan_temp,
4162                                              Label& L_no_such_interface,
4163                                              bool return_method) {
4164   assert_different_registers(recv_klass, intf_klass, scan_temp);
4165   assert_different_registers(method_result, intf_klass, scan_temp);
4166   assert(recv_klass != method_result || !return_method,
4167          "recv_klass can be destroyed when method isn't needed");
4168 
4169   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4170          "caller must use same register for non-constant itable index as for method");
4171 
4172   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4173   int vtable_base = in_bytes(Klass::vtable_start_offset());
4174   int itentry_off = itableMethodEntry::method_offset_in_bytes();
4175   int scan_step   = itableOffsetEntry::size() * wordSize;
4176   int vte_size    = vtableEntry::size_in_bytes();
4177   Address::ScaleFactor times_vte_scale = Address::times_ptr;
4178   assert(vte_size == wordSize, "else adjust times_vte_scale");
4179 
4180   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4181 
4182   // %%% Could store the aligned, prescaled offset in the klassoop.
4183   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4184 
4185   if (return_method) {
4186     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4187     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4188     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4189   }
4190 
4191   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4192   //   if (scan->interface() == intf) {
4193   //     result = (klass + scan->offset() + itable_index);
4194   //   }
4195   // }
4196   Label search, found_method;
4197 
4198   for (int peel = 1; peel >= 0; peel--) {
4199     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4200     cmpptr(intf_klass, method_result);
4201 
4202     if (peel) {
4203       jccb(Assembler::equal, found_method);
4204     } else {
4205       jccb(Assembler::notEqual, search);
4206       // (invert the test to fall through to found_method...)
4207     }
4208 
4209     if (!peel)  break;
4210 
4211     bind(search);
4212 
4213     // Check that the previous entry is non-null.  A null entry means that
4214     // the receiver class doesn't implement the interface, and wasn't the
4215     // same as when the caller was compiled.
4216     testptr(method_result, method_result);
4217     jcc(Assembler::zero, L_no_such_interface);
4218     addptr(scan_temp, scan_step);
4219   }
4220 
4221   bind(found_method);
4222 
4223   if (return_method) {
4224     // Got a hit.
4225     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4226     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4227   }
4228 }
4229 
4230 
4231 // virtual method calling
4232 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4233                                            RegisterOrConstant vtable_index,
4234                                            Register method_result) {
4235   const int base = in_bytes(Klass::vtable_start_offset());
4236   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4237   Address vtable_entry_addr(recv_klass,
4238                             vtable_index, Address::times_ptr,
4239                             base + vtableEntry::method_offset_in_bytes());
4240   movptr(method_result, vtable_entry_addr);
4241 }
4242 
4243 
4244 void MacroAssembler::check_klass_subtype(Register sub_klass,
4245                            Register super_klass,
4246                            Register temp_reg,
4247                            Label& L_success) {
4248   Label L_failure;
4249   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
4250   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4251   bind(L_failure);
4252 }
4253 
4254 
4255 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4256                                                    Register super_klass,
4257                                                    Register temp_reg,
4258                                                    Label* L_success,
4259                                                    Label* L_failure,
4260                                                    Label* L_slow_path,
4261                                         RegisterOrConstant super_check_offset) {
4262   assert_different_registers(sub_klass, super_klass, temp_reg);
4263   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4264   if (super_check_offset.is_register()) {
4265     assert_different_registers(sub_klass, super_klass,
4266                                super_check_offset.as_register());
4267   } else if (must_load_sco) {
4268     assert(temp_reg != noreg, "supply either a temp or a register offset");
4269   }
4270 
4271   Label L_fallthrough;
4272   int label_nulls = 0;
4273   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4274   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4275   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4276   assert(label_nulls <= 1, "at most one NULL in the batch");
4277 
4278   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4279   int sco_offset = in_bytes(Klass::super_check_offset_offset());
4280   Address super_check_offset_addr(super_klass, sco_offset);
4281 
4282   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4283   // range of a jccb.  If this routine grows larger, reconsider at
4284   // least some of these.
4285 #define local_jcc(assembler_cond, label)                                \
4286   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
4287   else                             jcc( assembler_cond, label) /*omit semi*/
4288 
4289   // Hacked jmp, which may only be used just before L_fallthrough.
4290 #define final_jmp(label)                                                \
4291   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
4292   else                            jmp(label)                /*omit semi*/
4293 
4294   // If the pointers are equal, we are done (e.g., String[] elements).
4295   // This self-check enables sharing of secondary supertype arrays among
4296   // non-primary types such as array-of-interface.  Otherwise, each such
4297   // type would need its own customized SSA.
4298   // We move this check to the front of the fast path because many
4299   // type checks are in fact trivially successful in this manner,
4300   // so we get a nicely predicted branch right at the start of the check.
4301   cmpptr(sub_klass, super_klass);
4302   local_jcc(Assembler::equal, *L_success);
4303 
4304   // Check the supertype display:
4305   if (must_load_sco) {
4306     // Positive movl does right thing on LP64.
4307     movl(temp_reg, super_check_offset_addr);
4308     super_check_offset = RegisterOrConstant(temp_reg);
4309   }
4310   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4311   cmpptr(super_klass, super_check_addr); // load displayed supertype
4312 
4313   // This check has worked decisively for primary supers.
4314   // Secondary supers are sought in the super_cache ('super_cache_addr').
4315   // (Secondary supers are interfaces and very deeply nested subtypes.)
4316   // This works in the same check above because of a tricky aliasing
4317   // between the super_cache and the primary super display elements.
4318   // (The 'super_check_addr' can address either, as the case requires.)
4319   // Note that the cache is updated below if it does not help us find
4320   // what we need immediately.
4321   // So if it was a primary super, we can just fail immediately.
4322   // Otherwise, it's the slow path for us (no success at this point).
4323 
4324   if (super_check_offset.is_register()) {
4325     local_jcc(Assembler::equal, *L_success);
4326     cmpl(super_check_offset.as_register(), sc_offset);
4327     if (L_failure == &L_fallthrough) {
4328       local_jcc(Assembler::equal, *L_slow_path);
4329     } else {
4330       local_jcc(Assembler::notEqual, *L_failure);
4331       final_jmp(*L_slow_path);
4332     }
4333   } else if (super_check_offset.as_constant() == sc_offset) {
4334     // Need a slow path; fast failure is impossible.
4335     if (L_slow_path == &L_fallthrough) {
4336       local_jcc(Assembler::equal, *L_success);
4337     } else {
4338       local_jcc(Assembler::notEqual, *L_slow_path);
4339       final_jmp(*L_success);
4340     }
4341   } else {
4342     // No slow path; it's a fast decision.
4343     if (L_failure == &L_fallthrough) {
4344       local_jcc(Assembler::equal, *L_success);
4345     } else {
4346       local_jcc(Assembler::notEqual, *L_failure);
4347       final_jmp(*L_success);
4348     }
4349   }
4350 
4351   bind(L_fallthrough);
4352 
4353 #undef local_jcc
4354 #undef final_jmp
4355 }
4356 
4357 
4358 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4359                                                    Register super_klass,
4360                                                    Register temp_reg,
4361                                                    Register temp2_reg,
4362                                                    Label* L_success,
4363                                                    Label* L_failure,
4364                                                    bool set_cond_codes) {
4365   assert_different_registers(sub_klass, super_klass, temp_reg);
4366   if (temp2_reg != noreg)
4367     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4368 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4369 
4370   Label L_fallthrough;
4371   int label_nulls = 0;
4372   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4373   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4374   assert(label_nulls <= 1, "at most one NULL in the batch");
4375 
4376   // a couple of useful fields in sub_klass:
4377   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4378   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4379   Address secondary_supers_addr(sub_klass, ss_offset);
4380   Address super_cache_addr(     sub_klass, sc_offset);
4381 
4382   // Do a linear scan of the secondary super-klass chain.
4383   // This code is rarely used, so simplicity is a virtue here.
4384   // The repne_scan instruction uses fixed registers, which we must spill.
4385   // Don't worry too much about pre-existing connections with the input regs.
4386 
4387   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4388   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4389 
4390   // Get super_klass value into rax (even if it was in rdi or rcx).
4391   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4392   if (super_klass != rax || UseCompressedOops) {
4393     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4394     mov(rax, super_klass);
4395   }
4396   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4397   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4398 
4399 #ifndef PRODUCT
4400   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4401   ExternalAddress pst_counter_addr((address) pst_counter);
4402   NOT_LP64(  incrementl(pst_counter_addr) );
4403   LP64_ONLY( lea(rcx, pst_counter_addr) );
4404   LP64_ONLY( incrementl(Address(rcx, 0)) );
4405 #endif //PRODUCT
4406 
4407   // We will consult the secondary-super array.
4408   movptr(rdi, secondary_supers_addr);
4409   // Load the array length.  (Positive movl does right thing on LP64.)
4410   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4411   // Skip to start of data.
4412   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4413 
4414   // Scan RCX words at [RDI] for an occurrence of RAX.
4415   // Set NZ/Z based on last compare.
4416   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4417   // not change flags (only scas instruction which is repeated sets flags).
4418   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4419 
4420     testptr(rax,rax); // Set Z = 0
4421     repne_scan();
4422 
4423   // Unspill the temp. registers:
4424   if (pushed_rdi)  pop(rdi);
4425   if (pushed_rcx)  pop(rcx);
4426   if (pushed_rax)  pop(rax);
4427 
4428   if (set_cond_codes) {
4429     // Special hack for the AD files:  rdi is guaranteed non-zero.
4430     assert(!pushed_rdi, "rdi must be left non-NULL");
4431     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4432   }
4433 
4434   if (L_failure == &L_fallthrough)
4435         jccb(Assembler::notEqual, *L_failure);
4436   else  jcc(Assembler::notEqual, *L_failure);
4437 
4438   // Success.  Cache the super we found and proceed in triumph.
4439   movptr(super_cache_addr, super_klass);
4440 
4441   if (L_success != &L_fallthrough) {
4442     jmp(*L_success);
4443   }
4444 
4445 #undef IS_A_TEMP
4446 
4447   bind(L_fallthrough);
4448 }
4449 
4450 
4451 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4452   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4453 
4454   Label L_fallthrough;
4455   if (L_fast_path == NULL) {
4456     L_fast_path = &L_fallthrough;
4457   }
4458 
4459   // Fast path check: class is fully initialized
4460   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4461   jcc(Assembler::equal, *L_fast_path);
4462 
4463   // Fast path check: current thread is initializer thread
4464   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4465   if (L_slow_path != NULL) {
4466     jcc(Assembler::notEqual, *L_slow_path);
4467   } else {
4468     jcc(Assembler::equal, *L_fast_path);
4469   }
4470 
4471   bind(L_fallthrough);
4472 }
4473 
4474 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4475   if (VM_Version::supports_cmov()) {
4476     cmovl(cc, dst, src);
4477   } else {
4478     Label L;
4479     jccb(negate_condition(cc), L);
4480     movl(dst, src);
4481     bind(L);
4482   }
4483 }
4484 
4485 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4486   if (VM_Version::supports_cmov()) {
4487     cmovl(cc, dst, src);
4488   } else {
4489     Label L;
4490     jccb(negate_condition(cc), L);
4491     movl(dst, src);
4492     bind(L);
4493   }
4494 }
4495 
4496 void MacroAssembler::verify_oop(Register reg, const char* s) {
4497   if (!VerifyOops) return;
4498 
4499   // Pass register number to verify_oop_subroutine
4500   const char* b = NULL;
4501   {
4502     ResourceMark rm;
4503     stringStream ss;
4504     ss.print("verify_oop: %s: %s", reg->name(), s);
4505     b = code_string(ss.as_string());
4506   }
4507   BLOCK_COMMENT("verify_oop {");
4508 #ifdef _LP64
4509   push(rscratch1);                    // save r10, trashed by movptr()
4510 #endif
4511   push(rax);                          // save rax,
4512   push(reg);                          // pass register argument
4513   ExternalAddress buffer((address) b);
4514   // avoid using pushptr, as it modifies scratch registers
4515   // and our contract is not to modify anything
4516   movptr(rax, buffer.addr());
4517   push(rax);
4518   // call indirectly to solve generation ordering problem
4519   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4520   call(rax);
4521   // Caller pops the arguments (oop, message) and restores rax, r10
4522   BLOCK_COMMENT("} verify_oop");
4523 }
4524 
4525 
4526 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4527                                                       Register tmp,
4528                                                       int offset) {
4529   intptr_t value = *delayed_value_addr;
4530   if (value != 0)
4531     return RegisterOrConstant(value + offset);
4532 
4533   // load indirectly to solve generation ordering problem
4534   movptr(tmp, ExternalAddress((address) delayed_value_addr));
4535 
4536 #ifdef ASSERT
4537   { Label L;
4538     testptr(tmp, tmp);
4539     if (WizardMode) {
4540       const char* buf = NULL;
4541       {
4542         ResourceMark rm;
4543         stringStream ss;
4544         ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4545         buf = code_string(ss.as_string());
4546       }
4547       jcc(Assembler::notZero, L);
4548       STOP(buf);
4549     } else {
4550       jccb(Assembler::notZero, L);
4551       hlt();
4552     }
4553     bind(L);
4554   }
4555 #endif
4556 
4557   if (offset != 0)
4558     addptr(tmp, offset);
4559 
4560   return RegisterOrConstant(tmp);
4561 }
4562 
4563 
4564 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4565                                          int extra_slot_offset) {
4566   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4567   int stackElementSize = Interpreter::stackElementSize;
4568   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4569 #ifdef ASSERT
4570   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4571   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4572 #endif
4573   Register             scale_reg    = noreg;
4574   Address::ScaleFactor scale_factor = Address::no_scale;
4575   if (arg_slot.is_constant()) {
4576     offset += arg_slot.as_constant() * stackElementSize;
4577   } else {
4578     scale_reg    = arg_slot.as_register();
4579     scale_factor = Address::times(stackElementSize);
4580   }
4581   offset += wordSize;           // return PC is on stack
4582   return Address(rsp, scale_reg, scale_factor, offset);
4583 }
4584 
4585 
4586 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4587   if (!VerifyOops) return;
4588 
4589   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4590   // Pass register number to verify_oop_subroutine
4591   const char* b = NULL;
4592   {
4593     ResourceMark rm;
4594     stringStream ss;
4595     ss.print("verify_oop_addr: %s", s);
4596     b = code_string(ss.as_string());
4597   }
4598 #ifdef _LP64
4599   push(rscratch1);                    // save r10, trashed by movptr()
4600 #endif
4601   push(rax);                          // save rax,
4602   // addr may contain rsp so we will have to adjust it based on the push
4603   // we just did (and on 64 bit we do two pushes)
4604   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4605   // stores rax into addr which is backwards of what was intended.
4606   if (addr.uses(rsp)) {
4607     lea(rax, addr);
4608     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4609   } else {
4610     pushptr(addr);
4611   }
4612 
4613   ExternalAddress buffer((address) b);
4614   // pass msg argument
4615   // avoid using pushptr, as it modifies scratch registers
4616   // and our contract is not to modify anything
4617   movptr(rax, buffer.addr());
4618   push(rax);
4619 
4620   // call indirectly to solve generation ordering problem
4621   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4622   call(rax);
4623   // Caller pops the arguments (addr, message) and restores rax, r10.
4624 }
4625 
4626 void MacroAssembler::verify_tlab() {
4627 #ifdef ASSERT
4628   if (UseTLAB && VerifyOops) {
4629     Label next, ok;
4630     Register t1 = rsi;
4631     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4632 
4633     push(t1);
4634     NOT_LP64(push(thread_reg));
4635     NOT_LP64(get_thread(thread_reg));
4636 
4637     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4638     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4639     jcc(Assembler::aboveEqual, next);
4640     STOP("assert(top >= start)");
4641     should_not_reach_here();
4642 
4643     bind(next);
4644     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4645     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4646     jcc(Assembler::aboveEqual, ok);
4647     STOP("assert(top <= end)");
4648     should_not_reach_here();
4649 
4650     bind(ok);
4651     NOT_LP64(pop(thread_reg));
4652     pop(t1);
4653   }
4654 #endif
4655 }
4656 
4657 class ControlWord {
4658  public:
4659   int32_t _value;
4660 
4661   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4662   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4663   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4664   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4665   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4666   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4667   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4668   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4669 
4670   void print() const {
4671     // rounding control
4672     const char* rc;
4673     switch (rounding_control()) {
4674       case 0: rc = "round near"; break;
4675       case 1: rc = "round down"; break;
4676       case 2: rc = "round up  "; break;
4677       case 3: rc = "chop      "; break;
4678     };
4679     // precision control
4680     const char* pc;
4681     switch (precision_control()) {
4682       case 0: pc = "24 bits "; break;
4683       case 1: pc = "reserved"; break;
4684       case 2: pc = "53 bits "; break;
4685       case 3: pc = "64 bits "; break;
4686     };
4687     // flags
4688     char f[9];
4689     f[0] = ' ';
4690     f[1] = ' ';
4691     f[2] = (precision   ()) ? 'P' : 'p';
4692     f[3] = (underflow   ()) ? 'U' : 'u';
4693     f[4] = (overflow    ()) ? 'O' : 'o';
4694     f[5] = (zero_divide ()) ? 'Z' : 'z';
4695     f[6] = (denormalized()) ? 'D' : 'd';
4696     f[7] = (invalid     ()) ? 'I' : 'i';
4697     f[8] = '\x0';
4698     // output
4699     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4700   }
4701 
4702 };
4703 
4704 class StatusWord {
4705  public:
4706   int32_t _value;
4707 
4708   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4709   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4710   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4711   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4712   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4713   int  top() const                     { return  (_value >> 11) & 7      ; }
4714   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4715   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4716   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4717   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4718   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4719   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4720   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4721   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4722 
4723   void print() const {
4724     // condition codes
4725     char c[5];
4726     c[0] = (C3()) ? '3' : '-';
4727     c[1] = (C2()) ? '2' : '-';
4728     c[2] = (C1()) ? '1' : '-';
4729     c[3] = (C0()) ? '0' : '-';
4730     c[4] = '\x0';
4731     // flags
4732     char f[9];
4733     f[0] = (error_status()) ? 'E' : '-';
4734     f[1] = (stack_fault ()) ? 'S' : '-';
4735     f[2] = (precision   ()) ? 'P' : '-';
4736     f[3] = (underflow   ()) ? 'U' : '-';
4737     f[4] = (overflow    ()) ? 'O' : '-';
4738     f[5] = (zero_divide ()) ? 'Z' : '-';
4739     f[6] = (denormalized()) ? 'D' : '-';
4740     f[7] = (invalid     ()) ? 'I' : '-';
4741     f[8] = '\x0';
4742     // output
4743     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4744   }
4745 
4746 };
4747 
4748 class TagWord {
4749  public:
4750   int32_t _value;
4751 
4752   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4753 
4754   void print() const {
4755     printf("%04x", _value & 0xFFFF);
4756   }
4757 
4758 };
4759 
4760 class FPU_Register {
4761  public:
4762   int32_t _m0;
4763   int32_t _m1;
4764   int16_t _ex;
4765 
4766   bool is_indefinite() const           {
4767     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4768   }
4769 
4770   void print() const {
4771     char  sign = (_ex < 0) ? '-' : '+';
4772     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4773     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4774   };
4775 
4776 };
4777 
4778 class FPU_State {
4779  public:
4780   enum {
4781     register_size       = 10,
4782     number_of_registers =  8,
4783     register_mask       =  7
4784   };
4785 
4786   ControlWord  _control_word;
4787   StatusWord   _status_word;
4788   TagWord      _tag_word;
4789   int32_t      _error_offset;
4790   int32_t      _error_selector;
4791   int32_t      _data_offset;
4792   int32_t      _data_selector;
4793   int8_t       _register[register_size * number_of_registers];
4794 
4795   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4796   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4797 
4798   const char* tag_as_string(int tag) const {
4799     switch (tag) {
4800       case 0: return "valid";
4801       case 1: return "zero";
4802       case 2: return "special";
4803       case 3: return "empty";
4804     }
4805     ShouldNotReachHere();
4806     return NULL;
4807   }
4808 
4809   void print() const {
4810     // print computation registers
4811     { int t = _status_word.top();
4812       for (int i = 0; i < number_of_registers; i++) {
4813         int j = (i - t) & register_mask;
4814         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4815         st(j)->print();
4816         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4817       }
4818     }
4819     printf("\n");
4820     // print control registers
4821     printf("ctrl = "); _control_word.print(); printf("\n");
4822     printf("stat = "); _status_word .print(); printf("\n");
4823     printf("tags = "); _tag_word    .print(); printf("\n");
4824   }
4825 
4826 };
4827 
4828 class Flag_Register {
4829  public:
4830   int32_t _value;
4831 
4832   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4833   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4834   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4835   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4836   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4837   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4838   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4839 
4840   void print() const {
4841     // flags
4842     char f[8];
4843     f[0] = (overflow       ()) ? 'O' : '-';
4844     f[1] = (direction      ()) ? 'D' : '-';
4845     f[2] = (sign           ()) ? 'S' : '-';
4846     f[3] = (zero           ()) ? 'Z' : '-';
4847     f[4] = (auxiliary_carry()) ? 'A' : '-';
4848     f[5] = (parity         ()) ? 'P' : '-';
4849     f[6] = (carry          ()) ? 'C' : '-';
4850     f[7] = '\x0';
4851     // output
4852     printf("%08x  flags = %s", _value, f);
4853   }
4854 
4855 };
4856 
4857 class IU_Register {
4858  public:
4859   int32_t _value;
4860 
4861   void print() const {
4862     printf("%08x  %11d", _value, _value);
4863   }
4864 
4865 };
4866 
4867 class IU_State {
4868  public:
4869   Flag_Register _eflags;
4870   IU_Register   _rdi;
4871   IU_Register   _rsi;
4872   IU_Register   _rbp;
4873   IU_Register   _rsp;
4874   IU_Register   _rbx;
4875   IU_Register   _rdx;
4876   IU_Register   _rcx;
4877   IU_Register   _rax;
4878 
4879   void print() const {
4880     // computation registers
4881     printf("rax,  = "); _rax.print(); printf("\n");
4882     printf("rbx,  = "); _rbx.print(); printf("\n");
4883     printf("rcx  = "); _rcx.print(); printf("\n");
4884     printf("rdx  = "); _rdx.print(); printf("\n");
4885     printf("rdi  = "); _rdi.print(); printf("\n");
4886     printf("rsi  = "); _rsi.print(); printf("\n");
4887     printf("rbp,  = "); _rbp.print(); printf("\n");
4888     printf("rsp  = "); _rsp.print(); printf("\n");
4889     printf("\n");
4890     // control registers
4891     printf("flgs = "); _eflags.print(); printf("\n");
4892   }
4893 };
4894 
4895 
4896 class CPU_State {
4897  public:
4898   FPU_State _fpu_state;
4899   IU_State  _iu_state;
4900 
4901   void print() const {
4902     printf("--------------------------------------------------\n");
4903     _iu_state .print();
4904     printf("\n");
4905     _fpu_state.print();
4906     printf("--------------------------------------------------\n");
4907   }
4908 
4909 };
4910 
4911 
4912 static void _print_CPU_state(CPU_State* state) {
4913   state->print();
4914 };
4915 
4916 
4917 void MacroAssembler::print_CPU_state() {
4918   push_CPU_state();
4919   push(rsp);                // pass CPU state
4920   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4921   addptr(rsp, wordSize);       // discard argument
4922   pop_CPU_state();
4923 }
4924 
4925 
4926 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4927   static int counter = 0;
4928   FPU_State* fs = &state->_fpu_state;
4929   counter++;
4930   // For leaf calls, only verify that the top few elements remain empty.
4931   // We only need 1 empty at the top for C2 code.
4932   if( stack_depth < 0 ) {
4933     if( fs->tag_for_st(7) != 3 ) {
4934       printf("FPR7 not empty\n");
4935       state->print();
4936       assert(false, "error");
4937       return false;
4938     }
4939     return true;                // All other stack states do not matter
4940   }
4941 
4942   assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
4943          "bad FPU control word");
4944 
4945   // compute stack depth
4946   int i = 0;
4947   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4948   int d = i;
4949   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4950   // verify findings
4951   if (i != FPU_State::number_of_registers) {
4952     // stack not contiguous
4953     printf("%s: stack not contiguous at ST%d\n", s, i);
4954     state->print();
4955     assert(false, "error");
4956     return false;
4957   }
4958   // check if computed stack depth corresponds to expected stack depth
4959   if (stack_depth < 0) {
4960     // expected stack depth is -stack_depth or less
4961     if (d > -stack_depth) {
4962       // too many elements on the stack
4963       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4964       state->print();
4965       assert(false, "error");
4966       return false;
4967     }
4968   } else {
4969     // expected stack depth is stack_depth
4970     if (d != stack_depth) {
4971       // wrong stack depth
4972       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4973       state->print();
4974       assert(false, "error");
4975       return false;
4976     }
4977   }
4978   // everything is cool
4979   return true;
4980 }
4981 
4982 
4983 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4984   if (!VerifyFPU) return;
4985   push_CPU_state();
4986   push(rsp);                // pass CPU state
4987   ExternalAddress msg((address) s);
4988   // pass message string s
4989   pushptr(msg.addr());
4990   push(stack_depth);        // pass stack depth
4991   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4992   addptr(rsp, 3 * wordSize);   // discard arguments
4993   // check for error
4994   { Label L;
4995     testl(rax, rax);
4996     jcc(Assembler::notZero, L);
4997     int3();                  // break if error condition
4998     bind(L);
4999   }
5000   pop_CPU_state();
5001 }
5002 
5003 void MacroAssembler::restore_cpu_control_state_after_jni() {
5004   // Either restore the MXCSR register after returning from the JNI Call
5005   // or verify that it wasn't changed (with -Xcheck:jni flag).
5006   if (VM_Version::supports_sse()) {
5007     if (RestoreMXCSROnJNICalls) {
5008       ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5009     } else if (CheckJNICalls) {
5010       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5011     }
5012   }
5013   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5014   vzeroupper();
5015   // Reset k1 to 0xffff.
5016 
5017 #ifdef COMPILER2
5018   if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5019     push(rcx);
5020     movl(rcx, 0xffff);
5021     kmovwl(k1, rcx);
5022     pop(rcx);
5023   }
5024 #endif // COMPILER2
5025 
5026 #ifndef _LP64
5027   // Either restore the x87 floating pointer control word after returning
5028   // from the JNI call or verify that it wasn't changed.
5029   if (CheckJNICalls) {
5030     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5031   }
5032 #endif // _LP64
5033 }
5034 
5035 // ((OopHandle)result).resolve();
5036 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5037   assert_different_registers(result, tmp);
5038 
5039   // Only 64 bit platforms support GCs that require a tmp register
5040   // Only IN_HEAP loads require a thread_tmp register
5041   // OopHandle::resolve is an indirection like jobject.
5042   access_load_at(T_OBJECT, IN_NATIVE,
5043                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5044 }
5045 
5046 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5047   load_method_holder(mirror, method);
5048   // get mirror
5049   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5050   movptr(mirror, Address(mirror, mirror_offset));
5051   resolve_oop_handle(mirror, tmp);
5052 }
5053 
5054 void MacroAssembler::load_method_holder(Register holder, Register method) {
5055   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
5056   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
5057   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
5058 }
5059 
5060 void MacroAssembler::load_klass(Register dst, Register src) {
5061 #ifdef _LP64
5062   if (UseCompressedClassPointers) {
5063     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5064     decode_klass_not_null(dst);
5065   } else
5066 #endif
5067     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5068 }
5069 
5070 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5071   load_klass(dst, src);
5072   movptr(dst, Address(dst, Klass::prototype_header_offset()));
5073 }
5074 
5075 void MacroAssembler::store_klass(Register dst, Register src) {
5076 #ifdef _LP64
5077   if (UseCompressedClassPointers) {
5078     encode_klass_not_null(src);
5079     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5080   } else
5081 #endif
5082     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5083 }
5084 
5085 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5086                                     Register tmp1, Register thread_tmp) {
5087   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5088   decorators = AccessInternal::decorator_fixup(decorators);
5089   bool as_raw = (decorators & AS_RAW) != 0;
5090   if (as_raw) {
5091     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5092   } else {
5093     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5094   }
5095 }
5096 
5097 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5098                                      Register tmp1, Register tmp2) {
5099   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5100   decorators = AccessInternal::decorator_fixup(decorators);
5101   bool as_raw = (decorators & AS_RAW) != 0;
5102   if (as_raw) {
5103     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5104   } else {
5105     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5106   }
5107 }
5108 
5109 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5110   // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5111   if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5112     decorators |= ACCESS_READ | ACCESS_WRITE;
5113   }
5114   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5115   return bs->resolve(this, decorators, obj);
5116 }
5117 
5118 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5119                                    Register thread_tmp, DecoratorSet decorators) {
5120   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5121 }
5122 
5123 // Doesn't do verfication, generates fixed size code
5124 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5125                                             Register thread_tmp, DecoratorSet decorators) {
5126   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5127 }
5128 
5129 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5130                                     Register tmp2, DecoratorSet decorators) {
5131   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5132 }
5133 
5134 // Used for storing NULLs.
5135 void MacroAssembler::store_heap_oop_null(Address dst) {
5136   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5137 }
5138 
5139 #ifdef _LP64
5140 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5141   if (UseCompressedClassPointers) {
5142     // Store to klass gap in destination
5143     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5144   }
5145 }
5146 
5147 #ifdef ASSERT
5148 void MacroAssembler::verify_heapbase(const char* msg) {
5149   assert (UseCompressedOops, "should be compressed");
5150   assert (Universe::heap() != NULL, "java heap should be initialized");
5151   if (CheckCompressedOops) {
5152     Label ok;
5153     push(rscratch1); // cmpptr trashes rscratch1
5154     cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5155     jcc(Assembler::equal, ok);
5156     STOP(msg);
5157     bind(ok);
5158     pop(rscratch1);
5159   }
5160 }
5161 #endif
5162 
5163 // Algorithm must match oop.inline.hpp encode_heap_oop.
5164 void MacroAssembler::encode_heap_oop(Register r) {
5165 #ifdef ASSERT
5166   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5167 #endif
5168   verify_oop(r, "broken oop in encode_heap_oop");
5169   if (Universe::narrow_oop_base() == NULL) {
5170     if (Universe::narrow_oop_shift() != 0) {
5171       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5172       shrq(r, LogMinObjAlignmentInBytes);
5173     }
5174     return;
5175   }
5176   testq(r, r);
5177   cmovq(Assembler::equal, r, r12_heapbase);
5178   subq(r, r12_heapbase);
5179   shrq(r, LogMinObjAlignmentInBytes);
5180 }
5181 
5182 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5183 #ifdef ASSERT
5184   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5185   if (CheckCompressedOops) {
5186     Label ok;
5187     testq(r, r);
5188     jcc(Assembler::notEqual, ok);
5189     STOP("null oop passed to encode_heap_oop_not_null");
5190     bind(ok);
5191   }
5192 #endif
5193   verify_oop(r, "broken oop in encode_heap_oop_not_null");
5194   if (Universe::narrow_oop_base() != NULL) {
5195     subq(r, r12_heapbase);
5196   }
5197   if (Universe::narrow_oop_shift() != 0) {
5198     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5199     shrq(r, LogMinObjAlignmentInBytes);
5200   }
5201 }
5202 
5203 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5204 #ifdef ASSERT
5205   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5206   if (CheckCompressedOops) {
5207     Label ok;
5208     testq(src, src);
5209     jcc(Assembler::notEqual, ok);
5210     STOP("null oop passed to encode_heap_oop_not_null2");
5211     bind(ok);
5212   }
5213 #endif
5214   verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5215   if (dst != src) {
5216     movq(dst, src);
5217   }
5218   if (Universe::narrow_oop_base() != NULL) {
5219     subq(dst, r12_heapbase);
5220   }
5221   if (Universe::narrow_oop_shift() != 0) {
5222     assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5223     shrq(dst, LogMinObjAlignmentInBytes);
5224   }
5225 }
5226 
5227 void  MacroAssembler::decode_heap_oop(Register r) {
5228 #ifdef ASSERT
5229   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5230 #endif
5231   if (Universe::narrow_oop_base() == NULL) {
5232     if (Universe::narrow_oop_shift() != 0) {
5233       assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5234       shlq(r, LogMinObjAlignmentInBytes);
5235     }
5236   } else {
5237     Label done;
5238     shlq(r, LogMinObjAlignmentInBytes);
5239     jccb(Assembler::equal, done);
5240     addq(r, r12_heapbase);
5241     bind(done);
5242   }
5243   verify_oop(r, "broken oop in decode_heap_oop");
5244 }
5245 
5246 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
5247   // Note: it will change flags
5248   assert (UseCompressedOops, "should only be used for compressed headers");
5249   assert (Universe::heap() != NULL, "java heap should be initialized");
5250   // Cannot assert, unverified entry point counts instructions (see .ad file)
5251   // vtableStubs also counts instructions in pd_code_size_limit.
5252   // Also do not verify_oop as this is called by verify_oop.
5253   if (Universe::narrow_oop_shift() != 0) {
5254     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5255     shlq(r, LogMinObjAlignmentInBytes);
5256     if (Universe::narrow_oop_base() != NULL) {
5257       addq(r, r12_heapbase);
5258     }
5259   } else {
5260     assert (Universe::narrow_oop_base() == NULL, "sanity");
5261   }
5262 }
5263 
5264 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5265   // Note: it will change flags
5266   assert (UseCompressedOops, "should only be used for compressed headers");
5267   assert (Universe::heap() != NULL, "java heap should be initialized");
5268   // Cannot assert, unverified entry point counts instructions (see .ad file)
5269   // vtableStubs also counts instructions in pd_code_size_limit.
5270   // Also do not verify_oop as this is called by verify_oop.
5271   if (Universe::narrow_oop_shift() != 0) {
5272     assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5273     if (LogMinObjAlignmentInBytes == Address::times_8) {
5274       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5275     } else {
5276       if (dst != src) {
5277         movq(dst, src);
5278       }
5279       shlq(dst, LogMinObjAlignmentInBytes);
5280       if (Universe::narrow_oop_base() != NULL) {
5281         addq(dst, r12_heapbase);
5282       }
5283     }
5284   } else {
5285     assert (Universe::narrow_oop_base() == NULL, "sanity");
5286     if (dst != src) {
5287       movq(dst, src);
5288     }
5289   }
5290 }
5291 
5292 void MacroAssembler::encode_klass_not_null(Register r) {
5293   if (Universe::narrow_klass_base() != NULL) {
5294     // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5295     assert(r != r12_heapbase, "Encoding a klass in r12");
5296     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5297     subq(r, r12_heapbase);
5298   }
5299   if (Universe::narrow_klass_shift() != 0) {
5300     assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5301     shrq(r, LogKlassAlignmentInBytes);
5302   }
5303   if (Universe::narrow_klass_base() != NULL) {
5304     reinit_heapbase();
5305   }
5306 }
5307 
5308 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5309   if (dst == src) {
5310     encode_klass_not_null(src);
5311   } else {
5312     if (Universe::narrow_klass_base() != NULL) {
5313       mov64(dst, (int64_t)Universe::narrow_klass_base());
5314       negq(dst);
5315       addq(dst, src);
5316     } else {
5317       movptr(dst, src);
5318     }
5319     if (Universe::narrow_klass_shift() != 0) {
5320       assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5321       shrq(dst, LogKlassAlignmentInBytes);
5322     }
5323   }
5324 }
5325 
5326 // Function instr_size_for_decode_klass_not_null() counts the instructions
5327 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5328 // when (Universe::heap() != NULL).  Hence, if the instructions they
5329 // generate change, then this method needs to be updated.
5330 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5331   assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5332   if (Universe::narrow_klass_base() != NULL) {
5333     // mov64 + addq + shlq? + mov64  (for reinit_heapbase()).
5334     return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
5335   } else {
5336     // longest load decode klass function, mov64, leaq
5337     return 16;
5338   }
5339 }
5340 
5341 // !!! If the instructions that get generated here change then function
5342 // instr_size_for_decode_klass_not_null() needs to get updated.
5343 void  MacroAssembler::decode_klass_not_null(Register r) {
5344   // Note: it will change flags
5345   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5346   assert(r != r12_heapbase, "Decoding a klass in r12");
5347   // Cannot assert, unverified entry point counts instructions (see .ad file)
5348   // vtableStubs also counts instructions in pd_code_size_limit.
5349   // Also do not verify_oop as this is called by verify_oop.
5350   if (Universe::narrow_klass_shift() != 0) {
5351     assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5352     shlq(r, LogKlassAlignmentInBytes);
5353   }
5354   // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5355   if (Universe::narrow_klass_base() != NULL) {
5356     mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
5357     addq(r, r12_heapbase);
5358     reinit_heapbase();
5359   }
5360 }
5361 
5362 void  MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5363   // Note: it will change flags
5364   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5365   if (dst == src) {
5366     decode_klass_not_null(dst);
5367   } else {
5368     // Cannot assert, unverified entry point counts instructions (see .ad file)
5369     // vtableStubs also counts instructions in pd_code_size_limit.
5370     // Also do not verify_oop as this is called by verify_oop.
5371     mov64(dst, (int64_t)Universe::narrow_klass_base());
5372     if (Universe::narrow_klass_shift() != 0) {
5373       assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
5374       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5375       leaq(dst, Address(dst, src, Address::times_8, 0));
5376     } else {
5377       addq(dst, src);
5378     }
5379   }
5380 }
5381 
5382 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5383   assert (UseCompressedOops, "should only be used for compressed headers");
5384   assert (Universe::heap() != NULL, "java heap should be initialized");
5385   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5386   int oop_index = oop_recorder()->find_index(obj);
5387   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5388   mov_narrow_oop(dst, oop_index, rspec);
5389 }
5390 
5391 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5392   assert (UseCompressedOops, "should only be used for compressed headers");
5393   assert (Universe::heap() != NULL, "java heap should be initialized");
5394   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5395   int oop_index = oop_recorder()->find_index(obj);
5396   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5397   mov_narrow_oop(dst, oop_index, rspec);
5398 }
5399 
5400 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5401   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5402   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5403   int klass_index = oop_recorder()->find_index(k);
5404   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5405   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5406 }
5407 
5408 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5409   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5410   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5411   int klass_index = oop_recorder()->find_index(k);
5412   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5413   mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
5414 }
5415 
5416 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5417   assert (UseCompressedOops, "should only be used for compressed headers");
5418   assert (Universe::heap() != NULL, "java heap should be initialized");
5419   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5420   int oop_index = oop_recorder()->find_index(obj);
5421   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5422   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5423 }
5424 
5425 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5426   assert (UseCompressedOops, "should only be used for compressed headers");
5427   assert (Universe::heap() != NULL, "java heap should be initialized");
5428   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5429   int oop_index = oop_recorder()->find_index(obj);
5430   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5431   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5432 }
5433 
5434 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5435   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5436   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5437   int klass_index = oop_recorder()->find_index(k);
5438   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5439   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5440 }
5441 
5442 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5443   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5444   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5445   int klass_index = oop_recorder()->find_index(k);
5446   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5447   Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
5448 }
5449 
5450 void MacroAssembler::reinit_heapbase() {
5451   if (UseCompressedOops || UseCompressedClassPointers) {
5452     if (Universe::heap() != NULL) {
5453       if (Universe::narrow_oop_base() == NULL) {
5454         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5455       } else {
5456         mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
5457       }
5458     } else {
5459       movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5460     }
5461   }
5462 }
5463 
5464 #endif // _LP64
5465 
5466 // C2 compiled method's prolog code.
5467 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5468 
5469   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5470   // NativeJump::patch_verified_entry will be able to patch out the entry
5471   // code safely. The push to verify stack depth is ok at 5 bytes,
5472   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5473   // stack bang then we must use the 6 byte frame allocation even if
5474   // we have no frame. :-(
5475   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5476 
5477   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5478   // Remove word for return addr
5479   framesize -= wordSize;
5480   stack_bang_size -= wordSize;
5481 
5482   // Calls to C2R adapters often do not accept exceptional returns.
5483   // We require that their callers must bang for them.  But be careful, because
5484   // some VM calls (such as call site linkage) can use several kilobytes of
5485   // stack.  But the stack safety zone should account for that.
5486   // See bugs 4446381, 4468289, 4497237.
5487   if (stack_bang_size > 0) {
5488     generate_stack_overflow_check(stack_bang_size);
5489 
5490     // We always push rbp, so that on return to interpreter rbp, will be
5491     // restored correctly and we can correct the stack.
5492     push(rbp);
5493     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5494     if (PreserveFramePointer) {
5495       mov(rbp, rsp);
5496     }
5497     // Remove word for ebp
5498     framesize -= wordSize;
5499 
5500     // Create frame
5501     if (framesize) {
5502       subptr(rsp, framesize);
5503     }
5504   } else {
5505     // Create frame (force generation of a 4 byte immediate value)
5506     subptr_imm32(rsp, framesize);
5507 
5508     // Save RBP register now.
5509     framesize -= wordSize;
5510     movptr(Address(rsp, framesize), rbp);
5511     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5512     if (PreserveFramePointer) {
5513       movptr(rbp, rsp);
5514       if (framesize > 0) {
5515         addptr(rbp, framesize);
5516       }
5517     }
5518   }
5519 
5520   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5521     framesize -= wordSize;
5522     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5523   }
5524 
5525 #ifndef _LP64
5526   // If method sets FPU control word do it now
5527   if (fp_mode_24b) {
5528     fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5529   }
5530   if (UseSSE >= 2 && VerifyFPU) {
5531     verify_FPU(0, "FPU stack must be clean on entry");
5532   }
5533 #endif
5534 
5535 #ifdef ASSERT
5536   if (VerifyStackAtCalls) {
5537     Label L;
5538     push(rax);
5539     mov(rax, rsp);
5540     andptr(rax, StackAlignmentInBytes-1);
5541     cmpptr(rax, StackAlignmentInBytes-wordSize);
5542     pop(rax);
5543     jcc(Assembler::equal, L);
5544     STOP("Stack is not properly aligned!");
5545     bind(L);
5546   }
5547 #endif
5548 
5549   if (!is_stub) {
5550     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5551     bs->nmethod_entry_barrier(this);
5552   }
5553 }
5554 
5555 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
5556 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5557   // cnt - number of qwords (8-byte words).
5558   // base - start address, qword aligned.
5559   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5560   if (UseAVX >= 2) {
5561     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5562   } else {
5563     pxor(xtmp, xtmp);
5564   }
5565   jmp(L_zero_64_bytes);
5566 
5567   BIND(L_loop);
5568   if (UseAVX >= 2) {
5569     vmovdqu(Address(base,  0), xtmp);
5570     vmovdqu(Address(base, 32), xtmp);
5571   } else {
5572     movdqu(Address(base,  0), xtmp);
5573     movdqu(Address(base, 16), xtmp);
5574     movdqu(Address(base, 32), xtmp);
5575     movdqu(Address(base, 48), xtmp);
5576   }
5577   addptr(base, 64);
5578 
5579   BIND(L_zero_64_bytes);
5580   subptr(cnt, 8);
5581   jccb(Assembler::greaterEqual, L_loop);
5582   addptr(cnt, 4);
5583   jccb(Assembler::less, L_tail);
5584   // Copy trailing 32 bytes
5585   if (UseAVX >= 2) {
5586     vmovdqu(Address(base, 0), xtmp);
5587   } else {
5588     movdqu(Address(base,  0), xtmp);
5589     movdqu(Address(base, 16), xtmp);
5590   }
5591   addptr(base, 32);
5592   subptr(cnt, 4);
5593 
5594   BIND(L_tail);
5595   addptr(cnt, 4);
5596   jccb(Assembler::lessEqual, L_end);
5597   decrement(cnt);
5598 
5599   BIND(L_sloop);
5600   movq(Address(base, 0), xtmp);
5601   addptr(base, 8);
5602   decrement(cnt);
5603   jccb(Assembler::greaterEqual, L_sloop);
5604   BIND(L_end);
5605 }
5606 
5607 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5608   // cnt - number of qwords (8-byte words).
5609   // base - start address, qword aligned.
5610   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5611   assert(base==rdi, "base register must be edi for rep stos");
5612   assert(tmp==rax,   "tmp register must be eax for rep stos");
5613   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5614   assert(InitArrayShortSize % BytesPerLong == 0,
5615     "InitArrayShortSize should be the multiple of BytesPerLong");
5616 
5617   Label DONE;
5618 
5619   if (!is_large || !UseXMMForObjInit) {
5620     xorptr(tmp, tmp);
5621   }
5622 
5623   if (!is_large) {
5624     Label LOOP, LONG;
5625     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5626     jccb(Assembler::greater, LONG);
5627 
5628     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5629 
5630     decrement(cnt);
5631     jccb(Assembler::negative, DONE); // Zero length
5632 
5633     // Use individual pointer-sized stores for small counts:
5634     BIND(LOOP);
5635     movptr(Address(base, cnt, Address::times_ptr), tmp);
5636     decrement(cnt);
5637     jccb(Assembler::greaterEqual, LOOP);
5638     jmpb(DONE);
5639 
5640     BIND(LONG);
5641   }
5642 
5643   // Use longer rep-prefixed ops for non-small counts:
5644   if (UseFastStosb) {
5645     shlptr(cnt, 3); // convert to number of bytes
5646     rep_stosb();
5647   } else if (UseXMMForObjInit) {
5648     movptr(tmp, base);
5649     xmm_clear_mem(tmp, cnt, xtmp);
5650   } else {
5651     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5652     rep_stos();
5653   }
5654 
5655   BIND(DONE);
5656 }
5657 
5658 #ifdef COMPILER2
5659 
5660 // IndexOf for constant substrings with size >= 8 chars
5661 // which don't need to be loaded through stack.
5662 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5663                                       Register cnt1, Register cnt2,
5664                                       int int_cnt2,  Register result,
5665                                       XMMRegister vec, Register tmp,
5666                                       int ae) {
5667   ShortBranchVerifier sbv(this);
5668   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5669   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5670 
5671   // This method uses the pcmpestri instruction with bound registers
5672   //   inputs:
5673   //     xmm - substring
5674   //     rax - substring length (elements count)
5675   //     mem - scanned string
5676   //     rdx - string length (elements count)
5677   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5678   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5679   //   outputs:
5680   //     rcx - matched index in string
5681   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5682   int mode   = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5683   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5684   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5685   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5686 
5687   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5688         RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5689         MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5690 
5691   // Note, inline_string_indexOf() generates checks:
5692   // if (substr.count > string.count) return -1;
5693   // if (substr.count == 0) return 0;
5694   assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5695 
5696   // Load substring.
5697   if (ae == StrIntrinsicNode::UL) {
5698     pmovzxbw(vec, Address(str2, 0));
5699   } else {
5700     movdqu(vec, Address(str2, 0));
5701   }
5702   movl(cnt2, int_cnt2);
5703   movptr(result, str1); // string addr
5704 
5705   if (int_cnt2 > stride) {
5706     jmpb(SCAN_TO_SUBSTR);
5707 
5708     // Reload substr for rescan, this code
5709     // is executed only for large substrings (> 8 chars)
5710     bind(RELOAD_SUBSTR);
5711     if (ae == StrIntrinsicNode::UL) {
5712       pmovzxbw(vec, Address(str2, 0));
5713     } else {
5714       movdqu(vec, Address(str2, 0));
5715     }
5716     negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5717 
5718     bind(RELOAD_STR);
5719     // We came here after the beginning of the substring was
5720     // matched but the rest of it was not so we need to search
5721     // again. Start from the next element after the previous match.
5722 
5723     // cnt2 is number of substring reminding elements and
5724     // cnt1 is number of string reminding elements when cmp failed.
5725     // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5726     subl(cnt1, cnt2);
5727     addl(cnt1, int_cnt2);
5728     movl(cnt2, int_cnt2); // Now restore cnt2
5729 
5730     decrementl(cnt1);     // Shift to next element
5731     cmpl(cnt1, cnt2);
5732     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5733 
5734     addptr(result, (1<<scale1));
5735 
5736   } // (int_cnt2 > 8)
5737 
5738   // Scan string for start of substr in 16-byte vectors
5739   bind(SCAN_TO_SUBSTR);
5740   pcmpestri(vec, Address(result, 0), mode);
5741   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
5742   subl(cnt1, stride);
5743   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5744   cmpl(cnt1, cnt2);
5745   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
5746   addptr(result, 16);
5747   jmpb(SCAN_TO_SUBSTR);
5748 
5749   // Found a potential substr
5750   bind(FOUND_CANDIDATE);
5751   // Matched whole vector if first element matched (tmp(rcx) == 0).
5752   if (int_cnt2 == stride) {
5753     jccb(Assembler::overflow, RET_FOUND);    // OF == 1
5754   } else { // int_cnt2 > 8
5755     jccb(Assembler::overflow, FOUND_SUBSTR);
5756   }
5757   // After pcmpestri tmp(rcx) contains matched element index
5758   // Compute start addr of substr
5759   lea(result, Address(result, tmp, scale1));
5760 
5761   // Make sure string is still long enough
5762   subl(cnt1, tmp);
5763   cmpl(cnt1, cnt2);
5764   if (int_cnt2 == stride) {
5765     jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5766   } else { // int_cnt2 > 8
5767     jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5768   }
5769   // Left less then substring.
5770 
5771   bind(RET_NOT_FOUND);
5772   movl(result, -1);
5773   jmp(EXIT);
5774 
5775   if (int_cnt2 > stride) {
5776     // This code is optimized for the case when whole substring
5777     // is matched if its head is matched.
5778     bind(MATCH_SUBSTR_HEAD);
5779     pcmpestri(vec, Address(result, 0), mode);
5780     // Reload only string if does not match
5781     jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5782 
5783     Label CONT_SCAN_SUBSTR;
5784     // Compare the rest of substring (> 8 chars).
5785     bind(FOUND_SUBSTR);
5786     // First 8 chars are already matched.
5787     negptr(cnt2);
5788     addptr(cnt2, stride);
5789 
5790     bind(SCAN_SUBSTR);
5791     subl(cnt1, stride);
5792     cmpl(cnt2, -stride); // Do not read beyond substring
5793     jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5794     // Back-up strings to avoid reading beyond substring:
5795     // cnt1 = cnt1 - cnt2 + 8
5796     addl(cnt1, cnt2); // cnt2 is negative
5797     addl(cnt1, stride);
5798     movl(cnt2, stride); negptr(cnt2);
5799     bind(CONT_SCAN_SUBSTR);
5800     if (int_cnt2 < (int)G) {
5801       int tail_off1 = int_cnt2<<scale1;
5802       int tail_off2 = int_cnt2<<scale2;
5803       if (ae == StrIntrinsicNode::UL) {
5804         pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
5805       } else {
5806         movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
5807       }
5808       pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
5809     } else {
5810       // calculate index in register to avoid integer overflow (int_cnt2*2)
5811       movl(tmp, int_cnt2);
5812       addptr(tmp, cnt2);
5813       if (ae == StrIntrinsicNode::UL) {
5814         pmovzxbw(vec, Address(str2, tmp, scale2, 0));
5815       } else {
5816         movdqu(vec, Address(str2, tmp, scale2, 0));
5817       }
5818       pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
5819     }
5820     // Need to reload strings pointers if not matched whole vector
5821     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
5822     addptr(cnt2, stride);
5823     jcc(Assembler::negative, SCAN_SUBSTR);
5824     // Fall through if found full substring
5825 
5826   } // (int_cnt2 > 8)
5827 
5828   bind(RET_FOUND);
5829   // Found result if we matched full small substring.
5830   // Compute substr offset
5831   subptr(result, str1);
5832   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
5833     shrl(result, 1); // index
5834   }
5835   bind(EXIT);
5836 
5837 } // string_indexofC8
5838 
5839 // Small strings are loaded through stack if they cross page boundary.
5840 void MacroAssembler::string_indexof(Register str1, Register str2,
5841                                     Register cnt1, Register cnt2,
5842                                     int int_cnt2,  Register result,
5843                                     XMMRegister vec, Register tmp,
5844                                     int ae) {
5845   ShortBranchVerifier sbv(this);
5846   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5847   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5848 
5849   //
5850   // int_cnt2 is length of small (< 8 chars) constant substring
5851   // or (-1) for non constant substring in which case its length
5852   // is in cnt2 register.
5853   //
5854   // Note, inline_string_indexOf() generates checks:
5855   // if (substr.count > string.count) return -1;
5856   // if (substr.count == 0) return 0;
5857   //
5858   int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5859   assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
5860   // This method uses the pcmpestri instruction with bound registers
5861   //   inputs:
5862   //     xmm - substring
5863   //     rax - substring length (elements count)
5864   //     mem - scanned string
5865   //     rdx - string length (elements count)
5866   //     0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5867   //     0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5868   //   outputs:
5869   //     rcx - matched index in string
5870   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5871   int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5872   Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5873   Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5874 
5875   Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
5876         RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
5877         FOUND_CANDIDATE;
5878 
5879   { //========================================================
5880     // We don't know where these strings are located
5881     // and we can't read beyond them. Load them through stack.
5882     Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
5883 
5884     movptr(tmp, rsp); // save old SP
5885 
5886     if (int_cnt2 > 0) {     // small (< 8 chars) constant substring
5887       if (int_cnt2 == (1>>scale2)) { // One byte
5888         assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
5889         load_unsigned_byte(result, Address(str2, 0));
5890         movdl(vec, result); // move 32 bits
5891       } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) {  // Three bytes
5892         // Not enough header space in 32-bit VM: 12+3 = 15.
5893         movl(result, Address(str2, -1));
5894         shrl(result, 8);
5895         movdl(vec, result); // move 32 bits
5896       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) {  // One char
5897         load_unsigned_short(result, Address(str2, 0));
5898         movdl(vec, result); // move 32 bits
5899       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
5900         movdl(vec, Address(str2, 0)); // move 32 bits
5901       } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
5902         movq(vec, Address(str2, 0));  // move 64 bits
5903       } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
5904         // Array header size is 12 bytes in 32-bit VM
5905         // + 6 bytes for 3 chars == 18 bytes,
5906         // enough space to load vec and shift.
5907         assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
5908         if (ae == StrIntrinsicNode::UL) {
5909           int tail_off = int_cnt2-8;
5910           pmovzxbw(vec, Address(str2, tail_off));
5911           psrldq(vec, -2*tail_off);
5912         }
5913         else {
5914           int tail_off = int_cnt2*(1<<scale2);
5915           movdqu(vec, Address(str2, tail_off-16));
5916           psrldq(vec, 16-tail_off);
5917         }
5918       }
5919     } else { // not constant substring
5920       cmpl(cnt2, stride);
5921       jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
5922 
5923       // We can read beyond string if srt+16 does not cross page boundary
5924       // since heaps are aligned and mapped by pages.
5925       assert(os::vm_page_size() < (int)G, "default page should be small");
5926       movl(result, str2); // We need only low 32 bits
5927       andl(result, (os::vm_page_size()-1));
5928       cmpl(result, (os::vm_page_size()-16));
5929       jccb(Assembler::belowEqual, CHECK_STR);
5930 
5931       // Move small strings to stack to allow load 16 bytes into vec.
5932       subptr(rsp, 16);
5933       int stk_offset = wordSize-(1<<scale2);
5934       push(cnt2);
5935 
5936       bind(COPY_SUBSTR);
5937       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
5938         load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
5939         movb(Address(rsp, cnt2, scale2, stk_offset), result);
5940       } else if (ae == StrIntrinsicNode::UU) {
5941         load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
5942         movw(Address(rsp, cnt2, scale2, stk_offset), result);
5943       }
5944       decrement(cnt2);
5945       jccb(Assembler::notZero, COPY_SUBSTR);
5946 
5947       pop(cnt2);
5948       movptr(str2, rsp);  // New substring address
5949     } // non constant
5950 
5951     bind(CHECK_STR);
5952     cmpl(cnt1, stride);
5953     jccb(Assembler::aboveEqual, BIG_STRINGS);
5954 
5955     // Check cross page boundary.
5956     movl(result, str1); // We need only low 32 bits
5957     andl(result, (os::vm_page_size()-1));
5958     cmpl(result, (os::vm_page_size()-16));
5959     jccb(Assembler::belowEqual, BIG_STRINGS);
5960 
5961     subptr(rsp, 16);
5962     int stk_offset = -(1<<scale1);
5963     if (int_cnt2 < 0) { // not constant
5964       push(cnt2);
5965       stk_offset += wordSize;
5966     }
5967     movl(cnt2, cnt1);
5968 
5969     bind(COPY_STR);
5970     if (ae == StrIntrinsicNode::LL) {
5971       load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
5972       movb(Address(rsp, cnt2, scale1, stk_offset), result);
5973     } else {
5974       load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
5975       movw(Address(rsp, cnt2, scale1, stk_offset), result);
5976     }
5977     decrement(cnt2);
5978     jccb(Assembler::notZero, COPY_STR);
5979 
5980     if (int_cnt2 < 0) { // not constant
5981       pop(cnt2);
5982     }
5983     movptr(str1, rsp);  // New string address
5984 
5985     bind(BIG_STRINGS);
5986     // Load substring.
5987     if (int_cnt2 < 0) { // -1
5988       if (ae == StrIntrinsicNode::UL) {
5989         pmovzxbw(vec, Address(str2, 0));
5990       } else {
5991         movdqu(vec, Address(str2, 0));
5992       }
5993       push(cnt2);       // substr count
5994       push(str2);       // substr addr
5995       push(str1);       // string addr
5996     } else {
5997       // Small (< 8 chars) constant substrings are loaded already.
5998       movl(cnt2, int_cnt2);
5999     }
6000     push(tmp);  // original SP
6001 
6002   } // Finished loading
6003 
6004   //========================================================
6005   // Start search
6006   //
6007 
6008   movptr(result, str1); // string addr
6009 
6010   if (int_cnt2  < 0) {  // Only for non constant substring
6011     jmpb(SCAN_TO_SUBSTR);
6012 
6013     // SP saved at sp+0
6014     // String saved at sp+1*wordSize
6015     // Substr saved at sp+2*wordSize
6016     // Substr count saved at sp+3*wordSize
6017 
6018     // Reload substr for rescan, this code
6019     // is executed only for large substrings (> 8 chars)
6020     bind(RELOAD_SUBSTR);
6021     movptr(str2, Address(rsp, 2*wordSize));
6022     movl(cnt2, Address(rsp, 3*wordSize));
6023     if (ae == StrIntrinsicNode::UL) {
6024       pmovzxbw(vec, Address(str2, 0));
6025     } else {
6026       movdqu(vec, Address(str2, 0));
6027     }
6028     // We came here after the beginning of the substring was
6029     // matched but the rest of it was not so we need to search
6030     // again. Start from the next element after the previous match.
6031     subptr(str1, result); // Restore counter
6032     if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6033       shrl(str1, 1);
6034     }
6035     addl(cnt1, str1);
6036     decrementl(cnt1);   // Shift to next element
6037     cmpl(cnt1, cnt2);
6038     jcc(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6039 
6040     addptr(result, (1<<scale1));
6041   } // non constant
6042 
6043   // Scan string for start of substr in 16-byte vectors
6044   bind(SCAN_TO_SUBSTR);
6045   assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6046   pcmpestri(vec, Address(result, 0), mode);
6047   jccb(Assembler::below, FOUND_CANDIDATE);   // CF == 1
6048   subl(cnt1, stride);
6049   jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6050   cmpl(cnt1, cnt2);
6051   jccb(Assembler::negative, RET_NOT_FOUND);  // Left less then substring
6052   addptr(result, 16);
6053 
6054   bind(ADJUST_STR);
6055   cmpl(cnt1, stride); // Do not read beyond string
6056   jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6057   // Back-up string to avoid reading beyond string.
6058   lea(result, Address(result, cnt1, scale1, -16));
6059   movl(cnt1, stride);
6060   jmpb(SCAN_TO_SUBSTR);
6061 
6062   // Found a potential substr
6063   bind(FOUND_CANDIDATE);
6064   // After pcmpestri tmp(rcx) contains matched element index
6065 
6066   // Make sure string is still long enough
6067   subl(cnt1, tmp);
6068   cmpl(cnt1, cnt2);
6069   jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6070   // Left less then substring.
6071 
6072   bind(RET_NOT_FOUND);
6073   movl(result, -1);
6074   jmp(CLEANUP);
6075 
6076   bind(FOUND_SUBSTR);
6077   // Compute start addr of substr
6078   lea(result, Address(result, tmp, scale1));
6079   if (int_cnt2 > 0) { // Constant substring
6080     // Repeat search for small substring (< 8 chars)
6081     // from new point without reloading substring.
6082     // Have to check that we don't read beyond string.
6083     cmpl(tmp, stride-int_cnt2);
6084     jccb(Assembler::greater, ADJUST_STR);
6085     // Fall through if matched whole substring.
6086   } else { // non constant
6087     assert(int_cnt2 == -1, "should be != 0");
6088 
6089     addl(tmp, cnt2);
6090     // Found result if we matched whole substring.
6091     cmpl(tmp, stride);
6092     jcc(Assembler::lessEqual, RET_FOUND);
6093 
6094     // Repeat search for small substring (<= 8 chars)
6095     // from new point 'str1' without reloading substring.
6096     cmpl(cnt2, stride);
6097     // Have to check that we don't read beyond string.
6098     jccb(Assembler::lessEqual, ADJUST_STR);
6099 
6100     Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6101     // Compare the rest of substring (> 8 chars).
6102     movptr(str1, result);
6103 
6104     cmpl(tmp, cnt2);
6105     // First 8 chars are already matched.
6106     jccb(Assembler::equal, CHECK_NEXT);
6107 
6108     bind(SCAN_SUBSTR);
6109     pcmpestri(vec, Address(str1, 0), mode);
6110     // Need to reload strings pointers if not matched whole vector
6111     jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6112 
6113     bind(CHECK_NEXT);
6114     subl(cnt2, stride);
6115     jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6116     addptr(str1, 16);
6117     if (ae == StrIntrinsicNode::UL) {
6118       addptr(str2, 8);
6119     } else {
6120       addptr(str2, 16);
6121     }
6122     subl(cnt1, stride);
6123     cmpl(cnt2, stride); // Do not read beyond substring
6124     jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6125     // Back-up strings to avoid reading beyond substring.
6126 
6127     if (ae == StrIntrinsicNode::UL) {
6128       lea(str2, Address(str2, cnt2, scale2, -8));
6129       lea(str1, Address(str1, cnt2, scale1, -16));
6130     } else {
6131       lea(str2, Address(str2, cnt2, scale2, -16));
6132       lea(str1, Address(str1, cnt2, scale1, -16));
6133     }
6134     subl(cnt1, cnt2);
6135     movl(cnt2, stride);
6136     addl(cnt1, stride);
6137     bind(CONT_SCAN_SUBSTR);
6138     if (ae == StrIntrinsicNode::UL) {
6139       pmovzxbw(vec, Address(str2, 0));
6140     } else {
6141       movdqu(vec, Address(str2, 0));
6142     }
6143     jmp(SCAN_SUBSTR);
6144 
6145     bind(RET_FOUND_LONG);
6146     movptr(str1, Address(rsp, wordSize));
6147   } // non constant
6148 
6149   bind(RET_FOUND);
6150   // Compute substr offset
6151   subptr(result, str1);
6152   if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6153     shrl(result, 1); // index
6154   }
6155   bind(CLEANUP);
6156   pop(rsp); // restore SP
6157 
6158 } // string_indexof
6159 
6160 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6161                                          XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6162   ShortBranchVerifier sbv(this);
6163   assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6164 
6165   int stride = 8;
6166 
6167   Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6168         SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6169         RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6170         FOUND_SEQ_CHAR, DONE_LABEL;
6171 
6172   movptr(result, str1);
6173   if (UseAVX >= 2) {
6174     cmpl(cnt1, stride);
6175     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6176     cmpl(cnt1, 2*stride);
6177     jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6178     movdl(vec1, ch);
6179     vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6180     vpxor(vec2, vec2);
6181     movl(tmp, cnt1);
6182     andl(tmp, 0xFFFFFFF0);  //vector count (in chars)
6183     andl(cnt1,0x0000000F);  //tail count (in chars)
6184 
6185     bind(SCAN_TO_16_CHAR_LOOP);
6186     vmovdqu(vec3, Address(result, 0));
6187     vpcmpeqw(vec3, vec3, vec1, 1);
6188     vptest(vec2, vec3);
6189     jcc(Assembler::carryClear, FOUND_CHAR);
6190     addptr(result, 32);
6191     subl(tmp, 2*stride);
6192     jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6193     jmp(SCAN_TO_8_CHAR);
6194     bind(SCAN_TO_8_CHAR_INIT);
6195     movdl(vec1, ch);
6196     pshuflw(vec1, vec1, 0x00);
6197     pshufd(vec1, vec1, 0);
6198     pxor(vec2, vec2);
6199   }
6200   bind(SCAN_TO_8_CHAR);
6201   cmpl(cnt1, stride);
6202   if (UseAVX >= 2) {
6203     jcc(Assembler::less, SCAN_TO_CHAR);
6204   } else {
6205     jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
6206     movdl(vec1, ch);
6207     pshuflw(vec1, vec1, 0x00);
6208     pshufd(vec1, vec1, 0);
6209     pxor(vec2, vec2);
6210   }
6211   movl(tmp, cnt1);
6212   andl(tmp, 0xFFFFFFF8);  //vector count (in chars)
6213   andl(cnt1,0x00000007);  //tail count (in chars)
6214 
6215   bind(SCAN_TO_8_CHAR_LOOP);
6216   movdqu(vec3, Address(result, 0));
6217   pcmpeqw(vec3, vec1);
6218   ptest(vec2, vec3);
6219   jcc(Assembler::carryClear, FOUND_CHAR);
6220   addptr(result, 16);
6221   subl(tmp, stride);
6222   jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6223   bind(SCAN_TO_CHAR);
6224   testl(cnt1, cnt1);
6225   jcc(Assembler::zero, RET_NOT_FOUND);
6226   bind(SCAN_TO_CHAR_LOOP);
6227   load_unsigned_short(tmp, Address(result, 0));
6228   cmpl(ch, tmp);
6229   jccb(Assembler::equal, FOUND_SEQ_CHAR);
6230   addptr(result, 2);
6231   subl(cnt1, 1);
6232   jccb(Assembler::zero, RET_NOT_FOUND);
6233   jmp(SCAN_TO_CHAR_LOOP);
6234 
6235   bind(RET_NOT_FOUND);
6236   movl(result, -1);
6237   jmpb(DONE_LABEL);
6238 
6239   bind(FOUND_CHAR);
6240   if (UseAVX >= 2) {
6241     vpmovmskb(tmp, vec3);
6242   } else {
6243     pmovmskb(tmp, vec3);
6244   }
6245   bsfl(ch, tmp);
6246   addl(result, ch);
6247 
6248   bind(FOUND_SEQ_CHAR);
6249   subptr(result, str1);
6250   shrl(result, 1);
6251 
6252   bind(DONE_LABEL);
6253 } // string_indexof_char
6254 
6255 // helper function for string_compare
6256 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6257                                         Address::ScaleFactor scale, Address::ScaleFactor scale1,
6258                                         Address::ScaleFactor scale2, Register index, int ae) {
6259   if (ae == StrIntrinsicNode::LL) {
6260     load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6261     load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6262   } else if (ae == StrIntrinsicNode::UU) {
6263     load_unsigned_short(elem1, Address(str1, index, scale, 0));
6264     load_unsigned_short(elem2, Address(str2, index, scale, 0));
6265   } else {
6266     load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6267     load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6268   }
6269 }
6270 
6271 // Compare strings, used for char[] and byte[].
6272 void MacroAssembler::string_compare(Register str1, Register str2,
6273                                     Register cnt1, Register cnt2, Register result,
6274                                     XMMRegister vec1, int ae) {
6275   ShortBranchVerifier sbv(this);
6276   Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6277   Label COMPARE_WIDE_VECTORS_LOOP_FAILED;  // used only _LP64 && AVX3
6278   int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6279   int stride2x2 = 0x40;
6280   Address::ScaleFactor scale = Address::no_scale;
6281   Address::ScaleFactor scale1 = Address::no_scale;
6282   Address::ScaleFactor scale2 = Address::no_scale;
6283 
6284   if (ae != StrIntrinsicNode::LL) {
6285     stride2x2 = 0x20;
6286   }
6287 
6288   if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6289     shrl(cnt2, 1);
6290   }
6291   // Compute the minimum of the string lengths and the
6292   // difference of the string lengths (stack).
6293   // Do the conditional move stuff
6294   movl(result, cnt1);
6295   subl(cnt1, cnt2);
6296   push(cnt1);
6297   cmov32(Assembler::lessEqual, cnt2, result);    // cnt2 = min(cnt1, cnt2)
6298 
6299   // Is the minimum length zero?
6300   testl(cnt2, cnt2);
6301   jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6302   if (ae == StrIntrinsicNode::LL) {
6303     // Load first bytes
6304     load_unsigned_byte(result, Address(str1, 0));  // result = str1[0]
6305     load_unsigned_byte(cnt1, Address(str2, 0));    // cnt1   = str2[0]
6306   } else if (ae == StrIntrinsicNode::UU) {
6307     // Load first characters
6308     load_unsigned_short(result, Address(str1, 0));
6309     load_unsigned_short(cnt1, Address(str2, 0));
6310   } else {
6311     load_unsigned_byte(result, Address(str1, 0));
6312     load_unsigned_short(cnt1, Address(str2, 0));
6313   }
6314   subl(result, cnt1);
6315   jcc(Assembler::notZero,  POP_LABEL);
6316 
6317   if (ae == StrIntrinsicNode::UU) {
6318     // Divide length by 2 to get number of chars
6319     shrl(cnt2, 1);
6320   }
6321   cmpl(cnt2, 1);
6322   jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6323 
6324   // Check if the strings start at the same location and setup scale and stride
6325   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6326     cmpptr(str1, str2);
6327     jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6328     if (ae == StrIntrinsicNode::LL) {
6329       scale = Address::times_1;
6330       stride = 16;
6331     } else {
6332       scale = Address::times_2;
6333       stride = 8;
6334     }
6335   } else {
6336     scale1 = Address::times_1;
6337     scale2 = Address::times_2;
6338     // scale not used
6339     stride = 8;
6340   }
6341 
6342   if (UseAVX >= 2 && UseSSE42Intrinsics) {
6343     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6344     Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6345     Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6346     Label COMPARE_TAIL_LONG;
6347     Label COMPARE_WIDE_VECTORS_LOOP_AVX3;  // used only _LP64 && AVX3
6348 
6349     int pcmpmask = 0x19;
6350     if (ae == StrIntrinsicNode::LL) {
6351       pcmpmask &= ~0x01;
6352     }
6353 
6354     // Setup to compare 16-chars (32-bytes) vectors,
6355     // start from first character again because it has aligned address.
6356     if (ae == StrIntrinsicNode::LL) {
6357       stride2 = 32;
6358     } else {
6359       stride2 = 16;
6360     }
6361     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6362       adr_stride = stride << scale;
6363     } else {
6364       adr_stride1 = 8;  //stride << scale1;
6365       adr_stride2 = 16; //stride << scale2;
6366     }
6367 
6368     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6369     // rax and rdx are used by pcmpestri as elements counters
6370     movl(result, cnt2);
6371     andl(cnt2, ~(stride2-1));   // cnt2 holds the vector count
6372     jcc(Assembler::zero, COMPARE_TAIL_LONG);
6373 
6374     // fast path : compare first 2 8-char vectors.
6375     bind(COMPARE_16_CHARS);
6376     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6377       movdqu(vec1, Address(str1, 0));
6378     } else {
6379       pmovzxbw(vec1, Address(str1, 0));
6380     }
6381     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6382     jccb(Assembler::below, COMPARE_INDEX_CHAR);
6383 
6384     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6385       movdqu(vec1, Address(str1, adr_stride));
6386       pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6387     } else {
6388       pmovzxbw(vec1, Address(str1, adr_stride1));
6389       pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6390     }
6391     jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6392     addl(cnt1, stride);
6393 
6394     // Compare the characters at index in cnt1
6395     bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6396     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6397     subl(result, cnt2);
6398     jmp(POP_LABEL);
6399 
6400     // Setup the registers to start vector comparison loop
6401     bind(COMPARE_WIDE_VECTORS);
6402     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6403       lea(str1, Address(str1, result, scale));
6404       lea(str2, Address(str2, result, scale));
6405     } else {
6406       lea(str1, Address(str1, result, scale1));
6407       lea(str2, Address(str2, result, scale2));
6408     }
6409     subl(result, stride2);
6410     subl(cnt2, stride2);
6411     jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6412     negptr(result);
6413 
6414     //  In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6415     bind(COMPARE_WIDE_VECTORS_LOOP);
6416 
6417 #ifdef _LP64
6418     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6419       cmpl(cnt2, stride2x2);
6420       jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6421       testl(cnt2, stride2x2-1);   // cnt2 holds the vector count
6422       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2);   // means we cannot subtract by 0x40
6423 
6424       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6425       if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6426         evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6427         evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6428       } else {
6429         vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6430         evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6431       }
6432       kortestql(k7, k7);
6433       jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED);     // miscompare
6434       addptr(result, stride2x2);  // update since we already compared at this addr
6435       subl(cnt2, stride2x2);      // and sub the size too
6436       jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6437 
6438       vpxor(vec1, vec1);
6439       jmpb(COMPARE_WIDE_TAIL);
6440     }//if (VM_Version::supports_avx512vlbw())
6441 #endif // _LP64
6442 
6443 
6444     bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6445     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6446       vmovdqu(vec1, Address(str1, result, scale));
6447       vpxor(vec1, Address(str2, result, scale));
6448     } else {
6449       vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6450       vpxor(vec1, Address(str2, result, scale2));
6451     }
6452     vptest(vec1, vec1);
6453     jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6454     addptr(result, stride2);
6455     subl(cnt2, stride2);
6456     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6457     // clean upper bits of YMM registers
6458     vpxor(vec1, vec1);
6459 
6460     // compare wide vectors tail
6461     bind(COMPARE_WIDE_TAIL);
6462     testptr(result, result);
6463     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6464 
6465     movl(result, stride2);
6466     movl(cnt2, result);
6467     negptr(result);
6468     jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6469 
6470     // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6471     bind(VECTOR_NOT_EQUAL);
6472     // clean upper bits of YMM registers
6473     vpxor(vec1, vec1);
6474     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6475       lea(str1, Address(str1, result, scale));
6476       lea(str2, Address(str2, result, scale));
6477     } else {
6478       lea(str1, Address(str1, result, scale1));
6479       lea(str2, Address(str2, result, scale2));
6480     }
6481     jmp(COMPARE_16_CHARS);
6482 
6483     // Compare tail chars, length between 1 to 15 chars
6484     bind(COMPARE_TAIL_LONG);
6485     movl(cnt2, result);
6486     cmpl(cnt2, stride);
6487     jcc(Assembler::less, COMPARE_SMALL_STR);
6488 
6489     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6490       movdqu(vec1, Address(str1, 0));
6491     } else {
6492       pmovzxbw(vec1, Address(str1, 0));
6493     }
6494     pcmpestri(vec1, Address(str2, 0), pcmpmask);
6495     jcc(Assembler::below, COMPARE_INDEX_CHAR);
6496     subptr(cnt2, stride);
6497     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6498     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6499       lea(str1, Address(str1, result, scale));
6500       lea(str2, Address(str2, result, scale));
6501     } else {
6502       lea(str1, Address(str1, result, scale1));
6503       lea(str2, Address(str2, result, scale2));
6504     }
6505     negptr(cnt2);
6506     jmpb(WHILE_HEAD_LABEL);
6507 
6508     bind(COMPARE_SMALL_STR);
6509   } else if (UseSSE42Intrinsics) {
6510     Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6511     int pcmpmask = 0x19;
6512     // Setup to compare 8-char (16-byte) vectors,
6513     // start from first character again because it has aligned address.
6514     movl(result, cnt2);
6515     andl(cnt2, ~(stride - 1));   // cnt2 holds the vector count
6516     if (ae == StrIntrinsicNode::LL) {
6517       pcmpmask &= ~0x01;
6518     }
6519     jcc(Assembler::zero, COMPARE_TAIL);
6520     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6521       lea(str1, Address(str1, result, scale));
6522       lea(str2, Address(str2, result, scale));
6523     } else {
6524       lea(str1, Address(str1, result, scale1));
6525       lea(str2, Address(str2, result, scale2));
6526     }
6527     negptr(result);
6528 
6529     // pcmpestri
6530     //   inputs:
6531     //     vec1- substring
6532     //     rax - negative string length (elements count)
6533     //     mem - scanned string
6534     //     rdx - string length (elements count)
6535     //     pcmpmask - cmp mode: 11000 (string compare with negated result)
6536     //               + 00 (unsigned bytes) or  + 01 (unsigned shorts)
6537     //   outputs:
6538     //     rcx - first mismatched element index
6539     assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6540 
6541     bind(COMPARE_WIDE_VECTORS);
6542     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6543       movdqu(vec1, Address(str1, result, scale));
6544       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6545     } else {
6546       pmovzxbw(vec1, Address(str1, result, scale1));
6547       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6548     }
6549     // After pcmpestri cnt1(rcx) contains mismatched element index
6550 
6551     jccb(Assembler::below, VECTOR_NOT_EQUAL);  // CF==1
6552     addptr(result, stride);
6553     subptr(cnt2, stride);
6554     jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6555 
6556     // compare wide vectors tail
6557     testptr(result, result);
6558     jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6559 
6560     movl(cnt2, stride);
6561     movl(result, stride);
6562     negptr(result);
6563     if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6564       movdqu(vec1, Address(str1, result, scale));
6565       pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6566     } else {
6567       pmovzxbw(vec1, Address(str1, result, scale1));
6568       pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6569     }
6570     jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6571 
6572     // Mismatched characters in the vectors
6573     bind(VECTOR_NOT_EQUAL);
6574     addptr(cnt1, result);
6575     load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6576     subl(result, cnt2);
6577     jmpb(POP_LABEL);
6578 
6579     bind(COMPARE_TAIL); // limit is zero
6580     movl(cnt2, result);
6581     // Fallthru to tail compare
6582   }
6583   // Shift str2 and str1 to the end of the arrays, negate min
6584   if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6585     lea(str1, Address(str1, cnt2, scale));
6586     lea(str2, Address(str2, cnt2, scale));
6587   } else {
6588     lea(str1, Address(str1, cnt2, scale1));
6589     lea(str2, Address(str2, cnt2, scale2));
6590   }
6591   decrementl(cnt2);  // first character was compared already
6592   negptr(cnt2);
6593 
6594   // Compare the rest of the elements
6595   bind(WHILE_HEAD_LABEL);
6596   load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6597   subl(result, cnt1);
6598   jccb(Assembler::notZero, POP_LABEL);
6599   increment(cnt2);
6600   jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6601 
6602   // Strings are equal up to min length.  Return the length difference.
6603   bind(LENGTH_DIFF_LABEL);
6604   pop(result);
6605   if (ae == StrIntrinsicNode::UU) {
6606     // Divide diff by 2 to get number of chars
6607     sarl(result, 1);
6608   }
6609   jmpb(DONE_LABEL);
6610 
6611 #ifdef _LP64
6612   if (VM_Version::supports_avx512vlbw()) {
6613 
6614     bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6615 
6616     kmovql(cnt1, k7);
6617     notq(cnt1);
6618     bsfq(cnt2, cnt1);
6619     if (ae != StrIntrinsicNode::LL) {
6620       // Divide diff by 2 to get number of chars
6621       sarl(cnt2, 1);
6622     }
6623     addq(result, cnt2);
6624     if (ae == StrIntrinsicNode::LL) {
6625       load_unsigned_byte(cnt1, Address(str2, result));
6626       load_unsigned_byte(result, Address(str1, result));
6627     } else if (ae == StrIntrinsicNode::UU) {
6628       load_unsigned_short(cnt1, Address(str2, result, scale));
6629       load_unsigned_short(result, Address(str1, result, scale));
6630     } else {
6631       load_unsigned_short(cnt1, Address(str2, result, scale2));
6632       load_unsigned_byte(result, Address(str1, result, scale1));
6633     }
6634     subl(result, cnt1);
6635     jmpb(POP_LABEL);
6636   }//if (VM_Version::supports_avx512vlbw())
6637 #endif // _LP64
6638 
6639   // Discard the stored length difference
6640   bind(POP_LABEL);
6641   pop(cnt1);
6642 
6643   // That's it
6644   bind(DONE_LABEL);
6645   if(ae == StrIntrinsicNode::UL) {
6646     negl(result);
6647   }
6648 
6649 }
6650 
6651 // Search for Non-ASCII character (Negative byte value) in a byte array,
6652 // return true if it has any and false otherwise.
6653 //   ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6654 //   @HotSpotIntrinsicCandidate
6655 //   private static boolean hasNegatives(byte[] ba, int off, int len) {
6656 //     for (int i = off; i < off + len; i++) {
6657 //       if (ba[i] < 0) {
6658 //         return true;
6659 //       }
6660 //     }
6661 //     return false;
6662 //   }
6663 void MacroAssembler::has_negatives(Register ary1, Register len,
6664   Register result, Register tmp1,
6665   XMMRegister vec1, XMMRegister vec2) {
6666   // rsi: byte array
6667   // rcx: len
6668   // rax: result
6669   ShortBranchVerifier sbv(this);
6670   assert_different_registers(ary1, len, result, tmp1);
6671   assert_different_registers(vec1, vec2);
6672   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6673 
6674   // len == 0
6675   testl(len, len);
6676   jcc(Assembler::zero, FALSE_LABEL);
6677 
6678   if ((UseAVX > 2) && // AVX512
6679     VM_Version::supports_avx512vlbw() &&
6680     VM_Version::supports_bmi2()) {
6681 
6682     Label test_64_loop, test_tail;
6683     Register tmp3_aliased = len;
6684 
6685     movl(tmp1, len);
6686     vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6687 
6688     andl(tmp1, 64 - 1);   // tail count (in chars) 0x3F
6689     andl(len, ~(64 - 1));    // vector count (in chars)
6690     jccb(Assembler::zero, test_tail);
6691 
6692     lea(ary1, Address(ary1, len, Address::times_1));
6693     negptr(len);
6694 
6695     bind(test_64_loop);
6696     // Check whether our 64 elements of size byte contain negatives
6697     evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6698     kortestql(k2, k2);
6699     jcc(Assembler::notZero, TRUE_LABEL);
6700 
6701     addptr(len, 64);
6702     jccb(Assembler::notZero, test_64_loop);
6703 
6704 
6705     bind(test_tail);
6706     // bail out when there is nothing to be done
6707     testl(tmp1, -1);
6708     jcc(Assembler::zero, FALSE_LABEL);
6709 
6710     // ~(~0 << len) applied up to two times (for 32-bit scenario)
6711 #ifdef _LP64
6712     mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6713     shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6714     notq(tmp3_aliased);
6715     kmovql(k3, tmp3_aliased);
6716 #else
6717     Label k_init;
6718     jmp(k_init);
6719 
6720     // We could not read 64-bits from a general purpose register thus we move
6721     // data required to compose 64 1's to the instruction stream
6722     // We emit 64 byte wide series of elements from 0..63 which later on would
6723     // be used as a compare targets with tail count contained in tmp1 register.
6724     // Result would be a k register having tmp1 consecutive number or 1
6725     // counting from least significant bit.
6726     address tmp = pc();
6727     emit_int64(0x0706050403020100);
6728     emit_int64(0x0F0E0D0C0B0A0908);
6729     emit_int64(0x1716151413121110);
6730     emit_int64(0x1F1E1D1C1B1A1918);
6731     emit_int64(0x2726252423222120);
6732     emit_int64(0x2F2E2D2C2B2A2928);
6733     emit_int64(0x3736353433323130);
6734     emit_int64(0x3F3E3D3C3B3A3938);
6735 
6736     bind(k_init);
6737     lea(len, InternalAddress(tmp));
6738     // create mask to test for negative byte inside a vector
6739     evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6740     evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6741 
6742 #endif
6743     evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6744     ktestq(k2, k3);
6745     jcc(Assembler::notZero, TRUE_LABEL);
6746 
6747     jmp(FALSE_LABEL);
6748   } else {
6749     movl(result, len); // copy
6750 
6751     if (UseAVX == 2 && UseSSE >= 2) {
6752       // With AVX2, use 32-byte vector compare
6753       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6754 
6755       // Compare 32-byte vectors
6756       andl(result, 0x0000001f);  //   tail count (in bytes)
6757       andl(len, 0xffffffe0);   // vector count (in bytes)
6758       jccb(Assembler::zero, COMPARE_TAIL);
6759 
6760       lea(ary1, Address(ary1, len, Address::times_1));
6761       negptr(len);
6762 
6763       movl(tmp1, 0x80808080);   // create mask to test for Unicode chars in vector
6764       movdl(vec2, tmp1);
6765       vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6766 
6767       bind(COMPARE_WIDE_VECTORS);
6768       vmovdqu(vec1, Address(ary1, len, Address::times_1));
6769       vptest(vec1, vec2);
6770       jccb(Assembler::notZero, TRUE_LABEL);
6771       addptr(len, 32);
6772       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6773 
6774       testl(result, result);
6775       jccb(Assembler::zero, FALSE_LABEL);
6776 
6777       vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6778       vptest(vec1, vec2);
6779       jccb(Assembler::notZero, TRUE_LABEL);
6780       jmpb(FALSE_LABEL);
6781 
6782       bind(COMPARE_TAIL); // len is zero
6783       movl(len, result);
6784       // Fallthru to tail compare
6785     } else if (UseSSE42Intrinsics) {
6786       // With SSE4.2, use double quad vector compare
6787       Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6788 
6789       // Compare 16-byte vectors
6790       andl(result, 0x0000000f);  //   tail count (in bytes)
6791       andl(len, 0xfffffff0);   // vector count (in bytes)
6792       jcc(Assembler::zero, COMPARE_TAIL);
6793 
6794       lea(ary1, Address(ary1, len, Address::times_1));
6795       negptr(len);
6796 
6797       movl(tmp1, 0x80808080);
6798       movdl(vec2, tmp1);
6799       pshufd(vec2, vec2, 0);
6800 
6801       bind(COMPARE_WIDE_VECTORS);
6802       movdqu(vec1, Address(ary1, len, Address::times_1));
6803       ptest(vec1, vec2);
6804       jcc(Assembler::notZero, TRUE_LABEL);
6805       addptr(len, 16);
6806       jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6807 
6808       testl(result, result);
6809       jcc(Assembler::zero, FALSE_LABEL);
6810 
6811       movdqu(vec1, Address(ary1, result, Address::times_1, -16));
6812       ptest(vec1, vec2);
6813       jccb(Assembler::notZero, TRUE_LABEL);
6814       jmpb(FALSE_LABEL);
6815 
6816       bind(COMPARE_TAIL); // len is zero
6817       movl(len, result);
6818       // Fallthru to tail compare
6819     }
6820   }
6821   // Compare 4-byte vectors
6822   andl(len, 0xfffffffc); // vector count (in bytes)
6823   jccb(Assembler::zero, COMPARE_CHAR);
6824 
6825   lea(ary1, Address(ary1, len, Address::times_1));
6826   negptr(len);
6827 
6828   bind(COMPARE_VECTORS);
6829   movl(tmp1, Address(ary1, len, Address::times_1));
6830   andl(tmp1, 0x80808080);
6831   jccb(Assembler::notZero, TRUE_LABEL);
6832   addptr(len, 4);
6833   jcc(Assembler::notZero, COMPARE_VECTORS);
6834 
6835   // Compare trailing char (final 2 bytes), if any
6836   bind(COMPARE_CHAR);
6837   testl(result, 0x2);   // tail  char
6838   jccb(Assembler::zero, COMPARE_BYTE);
6839   load_unsigned_short(tmp1, Address(ary1, 0));
6840   andl(tmp1, 0x00008080);
6841   jccb(Assembler::notZero, TRUE_LABEL);
6842   subptr(result, 2);
6843   lea(ary1, Address(ary1, 2));
6844 
6845   bind(COMPARE_BYTE);
6846   testl(result, 0x1);   // tail  byte
6847   jccb(Assembler::zero, FALSE_LABEL);
6848   load_unsigned_byte(tmp1, Address(ary1, 0));
6849   andl(tmp1, 0x00000080);
6850   jccb(Assembler::notEqual, TRUE_LABEL);
6851   jmpb(FALSE_LABEL);
6852 
6853   bind(TRUE_LABEL);
6854   movl(result, 1);   // return true
6855   jmpb(DONE);
6856 
6857   bind(FALSE_LABEL);
6858   xorl(result, result); // return false
6859 
6860   // That's it
6861   bind(DONE);
6862   if (UseAVX >= 2 && UseSSE >= 2) {
6863     // clean upper bits of YMM registers
6864     vpxor(vec1, vec1);
6865     vpxor(vec2, vec2);
6866   }
6867 }
6868 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
6869 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6870                                    Register limit, Register result, Register chr,
6871                                    XMMRegister vec1, XMMRegister vec2, bool is_char) {
6872   ShortBranchVerifier sbv(this);
6873   Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
6874 
6875   int length_offset  = arrayOopDesc::length_offset_in_bytes();
6876   int base_offset    = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
6877 
6878   if (is_array_equ) {
6879     // Check the input args
6880     cmpoop(ary1, ary2);
6881     jcc(Assembler::equal, TRUE_LABEL);
6882 
6883     // Need additional checks for arrays_equals.
6884     testptr(ary1, ary1);
6885     jcc(Assembler::zero, FALSE_LABEL);
6886     testptr(ary2, ary2);
6887     jcc(Assembler::zero, FALSE_LABEL);
6888 
6889     // Check the lengths
6890     movl(limit, Address(ary1, length_offset));
6891     cmpl(limit, Address(ary2, length_offset));
6892     jcc(Assembler::notEqual, FALSE_LABEL);
6893   }
6894 
6895   // count == 0
6896   testl(limit, limit);
6897   jcc(Assembler::zero, TRUE_LABEL);
6898 
6899   if (is_array_equ) {
6900     // Load array address
6901     lea(ary1, Address(ary1, base_offset));
6902     lea(ary2, Address(ary2, base_offset));
6903   }
6904 
6905   if (is_array_equ && is_char) {
6906     // arrays_equals when used for char[].
6907     shll(limit, 1);      // byte count != 0
6908   }
6909   movl(result, limit); // copy
6910 
6911   if (UseAVX >= 2) {
6912     // With AVX2, use 32-byte vector compare
6913     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6914 
6915     // Compare 32-byte vectors
6916     andl(result, 0x0000001f);  //   tail count (in bytes)
6917     andl(limit, 0xffffffe0);   // vector count (in bytes)
6918     jcc(Assembler::zero, COMPARE_TAIL);
6919 
6920     lea(ary1, Address(ary1, limit, Address::times_1));
6921     lea(ary2, Address(ary2, limit, Address::times_1));
6922     negptr(limit);
6923 
6924     bind(COMPARE_WIDE_VECTORS);
6925 
6926 #ifdef _LP64
6927     if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6928       Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
6929 
6930       cmpl(limit, -64);
6931       jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6932 
6933       bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6934 
6935       evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
6936       evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
6937       kortestql(k7, k7);
6938       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
6939       addptr(limit, 64);  // update since we already compared at this addr
6940       cmpl(limit, -64);
6941       jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6942 
6943       // At this point we may still need to compare -limit+result bytes.
6944       // We could execute the next two instruction and just continue via non-wide path:
6945       //  cmpl(limit, 0);
6946       //  jcc(Assembler::equal, COMPARE_TAIL);  // true
6947       // But since we stopped at the points ary{1,2}+limit which are
6948       // not farther than 64 bytes from the ends of arrays ary{1,2}+result
6949       // (|limit| <= 32 and result < 32),
6950       // we may just compare the last 64 bytes.
6951       //
6952       addptr(result, -64);   // it is safe, bc we just came from this area
6953       evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
6954       evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
6955       kortestql(k7, k7);
6956       jcc(Assembler::aboveEqual, FALSE_LABEL);     // miscompare
6957 
6958       jmp(TRUE_LABEL);
6959 
6960       bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6961 
6962     }//if (VM_Version::supports_avx512vlbw())
6963 #endif //_LP64
6964 
6965     vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6966     vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6967     vpxor(vec1, vec2);
6968 
6969     vptest(vec1, vec1);
6970     jcc(Assembler::notZero, FALSE_LABEL);
6971     addptr(limit, 32);
6972     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6973 
6974     testl(result, result);
6975     jcc(Assembler::zero, TRUE_LABEL);
6976 
6977     vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6978     vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6979     vpxor(vec1, vec2);
6980 
6981     vptest(vec1, vec1);
6982     jccb(Assembler::notZero, FALSE_LABEL);
6983     jmpb(TRUE_LABEL);
6984 
6985     bind(COMPARE_TAIL); // limit is zero
6986     movl(limit, result);
6987     // Fallthru to tail compare
6988   } else if (UseSSE42Intrinsics) {
6989     // With SSE4.2, use double quad vector compare
6990     Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6991 
6992     // Compare 16-byte vectors
6993     andl(result, 0x0000000f);  //   tail count (in bytes)
6994     andl(limit, 0xfffffff0);   // vector count (in bytes)
6995     jcc(Assembler::zero, COMPARE_TAIL);
6996 
6997     lea(ary1, Address(ary1, limit, Address::times_1));
6998     lea(ary2, Address(ary2, limit, Address::times_1));
6999     negptr(limit);
7000 
7001     bind(COMPARE_WIDE_VECTORS);
7002     movdqu(vec1, Address(ary1, limit, Address::times_1));
7003     movdqu(vec2, Address(ary2, limit, Address::times_1));
7004     pxor(vec1, vec2);
7005 
7006     ptest(vec1, vec1);
7007     jcc(Assembler::notZero, FALSE_LABEL);
7008     addptr(limit, 16);
7009     jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7010 
7011     testl(result, result);
7012     jcc(Assembler::zero, TRUE_LABEL);
7013 
7014     movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7015     movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7016     pxor(vec1, vec2);
7017 
7018     ptest(vec1, vec1);
7019     jccb(Assembler::notZero, FALSE_LABEL);
7020     jmpb(TRUE_LABEL);
7021 
7022     bind(COMPARE_TAIL); // limit is zero
7023     movl(limit, result);
7024     // Fallthru to tail compare
7025   }
7026 
7027   // Compare 4-byte vectors
7028   andl(limit, 0xfffffffc); // vector count (in bytes)
7029   jccb(Assembler::zero, COMPARE_CHAR);
7030 
7031   lea(ary1, Address(ary1, limit, Address::times_1));
7032   lea(ary2, Address(ary2, limit, Address::times_1));
7033   negptr(limit);
7034 
7035   bind(COMPARE_VECTORS);
7036   movl(chr, Address(ary1, limit, Address::times_1));
7037   cmpl(chr, Address(ary2, limit, Address::times_1));
7038   jccb(Assembler::notEqual, FALSE_LABEL);
7039   addptr(limit, 4);
7040   jcc(Assembler::notZero, COMPARE_VECTORS);
7041 
7042   // Compare trailing char (final 2 bytes), if any
7043   bind(COMPARE_CHAR);
7044   testl(result, 0x2);   // tail  char
7045   jccb(Assembler::zero, COMPARE_BYTE);
7046   load_unsigned_short(chr, Address(ary1, 0));
7047   load_unsigned_short(limit, Address(ary2, 0));
7048   cmpl(chr, limit);
7049   jccb(Assembler::notEqual, FALSE_LABEL);
7050 
7051   if (is_array_equ && is_char) {
7052     bind(COMPARE_BYTE);
7053   } else {
7054     lea(ary1, Address(ary1, 2));
7055     lea(ary2, Address(ary2, 2));
7056 
7057     bind(COMPARE_BYTE);
7058     testl(result, 0x1);   // tail  byte
7059     jccb(Assembler::zero, TRUE_LABEL);
7060     load_unsigned_byte(chr, Address(ary1, 0));
7061     load_unsigned_byte(limit, Address(ary2, 0));
7062     cmpl(chr, limit);
7063     jccb(Assembler::notEqual, FALSE_LABEL);
7064   }
7065   bind(TRUE_LABEL);
7066   movl(result, 1);   // return true
7067   jmpb(DONE);
7068 
7069   bind(FALSE_LABEL);
7070   xorl(result, result); // return false
7071 
7072   // That's it
7073   bind(DONE);
7074   if (UseAVX >= 2) {
7075     // clean upper bits of YMM registers
7076     vpxor(vec1, vec1);
7077     vpxor(vec2, vec2);
7078   }
7079 }
7080 
7081 #endif
7082 
7083 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7084                                    Register to, Register value, Register count,
7085                                    Register rtmp, XMMRegister xtmp) {
7086   ShortBranchVerifier sbv(this);
7087   assert_different_registers(to, value, count, rtmp);
7088   Label L_exit;
7089   Label L_fill_2_bytes, L_fill_4_bytes;
7090 
7091   int shift = -1;
7092   switch (t) {
7093     case T_BYTE:
7094       shift = 2;
7095       break;
7096     case T_SHORT:
7097       shift = 1;
7098       break;
7099     case T_INT:
7100       shift = 0;
7101       break;
7102     default: ShouldNotReachHere();
7103   }
7104 
7105   if (t == T_BYTE) {
7106     andl(value, 0xff);
7107     movl(rtmp, value);
7108     shll(rtmp, 8);
7109     orl(value, rtmp);
7110   }
7111   if (t == T_SHORT) {
7112     andl(value, 0xffff);
7113   }
7114   if (t == T_BYTE || t == T_SHORT) {
7115     movl(rtmp, value);
7116     shll(rtmp, 16);
7117     orl(value, rtmp);
7118   }
7119 
7120   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7121   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7122   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7123     Label L_skip_align2;
7124     // align source address at 4 bytes address boundary
7125     if (t == T_BYTE) {
7126       Label L_skip_align1;
7127       // One byte misalignment happens only for byte arrays
7128       testptr(to, 1);
7129       jccb(Assembler::zero, L_skip_align1);
7130       movb(Address(to, 0), value);
7131       increment(to);
7132       decrement(count);
7133       BIND(L_skip_align1);
7134     }
7135     // Two bytes misalignment happens only for byte and short (char) arrays
7136     testptr(to, 2);
7137     jccb(Assembler::zero, L_skip_align2);
7138     movw(Address(to, 0), value);
7139     addptr(to, 2);
7140     subl(count, 1<<(shift-1));
7141     BIND(L_skip_align2);
7142   }
7143   if (UseSSE < 2) {
7144     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7145     // Fill 32-byte chunks
7146     subl(count, 8 << shift);
7147     jcc(Assembler::less, L_check_fill_8_bytes);
7148     align(16);
7149 
7150     BIND(L_fill_32_bytes_loop);
7151 
7152     for (int i = 0; i < 32; i += 4) {
7153       movl(Address(to, i), value);
7154     }
7155 
7156     addptr(to, 32);
7157     subl(count, 8 << shift);
7158     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7159     BIND(L_check_fill_8_bytes);
7160     addl(count, 8 << shift);
7161     jccb(Assembler::zero, L_exit);
7162     jmpb(L_fill_8_bytes);
7163 
7164     //
7165     // length is too short, just fill qwords
7166     //
7167     BIND(L_fill_8_bytes_loop);
7168     movl(Address(to, 0), value);
7169     movl(Address(to, 4), value);
7170     addptr(to, 8);
7171     BIND(L_fill_8_bytes);
7172     subl(count, 1 << (shift + 1));
7173     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7174     // fall through to fill 4 bytes
7175   } else {
7176     Label L_fill_32_bytes;
7177     if (!UseUnalignedLoadStores) {
7178       // align to 8 bytes, we know we are 4 byte aligned to start
7179       testptr(to, 4);
7180       jccb(Assembler::zero, L_fill_32_bytes);
7181       movl(Address(to, 0), value);
7182       addptr(to, 4);
7183       subl(count, 1<<shift);
7184     }
7185     BIND(L_fill_32_bytes);
7186     {
7187       assert( UseSSE >= 2, "supported cpu only" );
7188       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7189       movdl(xtmp, value);
7190       if (UseAVX > 2 && UseUnalignedLoadStores) {
7191         // Fill 64-byte chunks
7192         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7193         vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7194 
7195         subl(count, 16 << shift);
7196         jcc(Assembler::less, L_check_fill_32_bytes);
7197         align(16);
7198 
7199         BIND(L_fill_64_bytes_loop);
7200         evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7201         addptr(to, 64);
7202         subl(count, 16 << shift);
7203         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7204 
7205         BIND(L_check_fill_32_bytes);
7206         addl(count, 8 << shift);
7207         jccb(Assembler::less, L_check_fill_8_bytes);
7208         vmovdqu(Address(to, 0), xtmp);
7209         addptr(to, 32);
7210         subl(count, 8 << shift);
7211 
7212         BIND(L_check_fill_8_bytes);
7213       } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7214         // Fill 64-byte chunks
7215         Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7216         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7217 
7218         subl(count, 16 << shift);
7219         jcc(Assembler::less, L_check_fill_32_bytes);
7220         align(16);
7221 
7222         BIND(L_fill_64_bytes_loop);
7223         vmovdqu(Address(to, 0), xtmp);
7224         vmovdqu(Address(to, 32), xtmp);
7225         addptr(to, 64);
7226         subl(count, 16 << shift);
7227         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7228 
7229         BIND(L_check_fill_32_bytes);
7230         addl(count, 8 << shift);
7231         jccb(Assembler::less, L_check_fill_8_bytes);
7232         vmovdqu(Address(to, 0), xtmp);
7233         addptr(to, 32);
7234         subl(count, 8 << shift);
7235 
7236         BIND(L_check_fill_8_bytes);
7237         // clean upper bits of YMM registers
7238         movdl(xtmp, value);
7239         pshufd(xtmp, xtmp, 0);
7240       } else {
7241         // Fill 32-byte chunks
7242         pshufd(xtmp, xtmp, 0);
7243 
7244         subl(count, 8 << shift);
7245         jcc(Assembler::less, L_check_fill_8_bytes);
7246         align(16);
7247 
7248         BIND(L_fill_32_bytes_loop);
7249 
7250         if (UseUnalignedLoadStores) {
7251           movdqu(Address(to, 0), xtmp);
7252           movdqu(Address(to, 16), xtmp);
7253         } else {
7254           movq(Address(to, 0), xtmp);
7255           movq(Address(to, 8), xtmp);
7256           movq(Address(to, 16), xtmp);
7257           movq(Address(to, 24), xtmp);
7258         }
7259 
7260         addptr(to, 32);
7261         subl(count, 8 << shift);
7262         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7263 
7264         BIND(L_check_fill_8_bytes);
7265       }
7266       addl(count, 8 << shift);
7267       jccb(Assembler::zero, L_exit);
7268       jmpb(L_fill_8_bytes);
7269 
7270       //
7271       // length is too short, just fill qwords
7272       //
7273       BIND(L_fill_8_bytes_loop);
7274       movq(Address(to, 0), xtmp);
7275       addptr(to, 8);
7276       BIND(L_fill_8_bytes);
7277       subl(count, 1 << (shift + 1));
7278       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7279     }
7280   }
7281   // fill trailing 4 bytes
7282   BIND(L_fill_4_bytes);
7283   testl(count, 1<<shift);
7284   jccb(Assembler::zero, L_fill_2_bytes);
7285   movl(Address(to, 0), value);
7286   if (t == T_BYTE || t == T_SHORT) {
7287     Label L_fill_byte;
7288     addptr(to, 4);
7289     BIND(L_fill_2_bytes);
7290     // fill trailing 2 bytes
7291     testl(count, 1<<(shift-1));
7292     jccb(Assembler::zero, L_fill_byte);
7293     movw(Address(to, 0), value);
7294     if (t == T_BYTE) {
7295       addptr(to, 2);
7296       BIND(L_fill_byte);
7297       // fill trailing byte
7298       testl(count, 1);
7299       jccb(Assembler::zero, L_exit);
7300       movb(Address(to, 0), value);
7301     } else {
7302       BIND(L_fill_byte);
7303     }
7304   } else {
7305     BIND(L_fill_2_bytes);
7306   }
7307   BIND(L_exit);
7308 }
7309 
7310 // encode char[] to byte[] in ISO_8859_1
7311    //@HotSpotIntrinsicCandidate
7312    //private static int implEncodeISOArray(byte[] sa, int sp,
7313    //byte[] da, int dp, int len) {
7314    //  int i = 0;
7315    //  for (; i < len; i++) {
7316    //    char c = StringUTF16.getChar(sa, sp++);
7317    //    if (c > '\u00FF')
7318    //      break;
7319    //    da[dp++] = (byte)c;
7320    //  }
7321    //  return i;
7322    //}
7323 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7324   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7325   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7326   Register tmp5, Register result) {
7327 
7328   // rsi: src
7329   // rdi: dst
7330   // rdx: len
7331   // rcx: tmp5
7332   // rax: result
7333   ShortBranchVerifier sbv(this);
7334   assert_different_registers(src, dst, len, tmp5, result);
7335   Label L_done, L_copy_1_char, L_copy_1_char_exit;
7336 
7337   // set result
7338   xorl(result, result);
7339   // check for zero length
7340   testl(len, len);
7341   jcc(Assembler::zero, L_done);
7342 
7343   movl(result, len);
7344 
7345   // Setup pointers
7346   lea(src, Address(src, len, Address::times_2)); // char[]
7347   lea(dst, Address(dst, len, Address::times_1)); // byte[]
7348   negptr(len);
7349 
7350   if (UseSSE42Intrinsics || UseAVX >= 2) {
7351     Label L_copy_8_chars, L_copy_8_chars_exit;
7352     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7353 
7354     if (UseAVX >= 2) {
7355       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7356       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7357       movdl(tmp1Reg, tmp5);
7358       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7359       jmp(L_chars_32_check);
7360 
7361       bind(L_copy_32_chars);
7362       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7363       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7364       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7365       vptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7366       jccb(Assembler::notZero, L_copy_32_chars_exit);
7367       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7368       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7369       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7370 
7371       bind(L_chars_32_check);
7372       addptr(len, 32);
7373       jcc(Assembler::lessEqual, L_copy_32_chars);
7374 
7375       bind(L_copy_32_chars_exit);
7376       subptr(len, 16);
7377       jccb(Assembler::greater, L_copy_16_chars_exit);
7378 
7379     } else if (UseSSE42Intrinsics) {
7380       movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vector
7381       movdl(tmp1Reg, tmp5);
7382       pshufd(tmp1Reg, tmp1Reg, 0);
7383       jmpb(L_chars_16_check);
7384     }
7385 
7386     bind(L_copy_16_chars);
7387     if (UseAVX >= 2) {
7388       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7389       vptest(tmp2Reg, tmp1Reg);
7390       jcc(Assembler::notZero, L_copy_16_chars_exit);
7391       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7392       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7393     } else {
7394       if (UseAVX > 0) {
7395         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7396         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7397         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7398       } else {
7399         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7400         por(tmp2Reg, tmp3Reg);
7401         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7402         por(tmp2Reg, tmp4Reg);
7403       }
7404       ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in  vector
7405       jccb(Assembler::notZero, L_copy_16_chars_exit);
7406       packuswb(tmp3Reg, tmp4Reg);
7407     }
7408     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7409 
7410     bind(L_chars_16_check);
7411     addptr(len, 16);
7412     jcc(Assembler::lessEqual, L_copy_16_chars);
7413 
7414     bind(L_copy_16_chars_exit);
7415     if (UseAVX >= 2) {
7416       // clean upper bits of YMM registers
7417       vpxor(tmp2Reg, tmp2Reg);
7418       vpxor(tmp3Reg, tmp3Reg);
7419       vpxor(tmp4Reg, tmp4Reg);
7420       movdl(tmp1Reg, tmp5);
7421       pshufd(tmp1Reg, tmp1Reg, 0);
7422     }
7423     subptr(len, 8);
7424     jccb(Assembler::greater, L_copy_8_chars_exit);
7425 
7426     bind(L_copy_8_chars);
7427     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7428     ptest(tmp3Reg, tmp1Reg);
7429     jccb(Assembler::notZero, L_copy_8_chars_exit);
7430     packuswb(tmp3Reg, tmp1Reg);
7431     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7432     addptr(len, 8);
7433     jccb(Assembler::lessEqual, L_copy_8_chars);
7434 
7435     bind(L_copy_8_chars_exit);
7436     subptr(len, 8);
7437     jccb(Assembler::zero, L_done);
7438   }
7439 
7440   bind(L_copy_1_char);
7441   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7442   testl(tmp5, 0xff00);      // check if Unicode char
7443   jccb(Assembler::notZero, L_copy_1_char_exit);
7444   movb(Address(dst, len, Address::times_1, 0), tmp5);
7445   addptr(len, 1);
7446   jccb(Assembler::less, L_copy_1_char);
7447 
7448   bind(L_copy_1_char_exit);
7449   addptr(result, len); // len is negative count of not processed elements
7450 
7451   bind(L_done);
7452 }
7453 
7454 #ifdef _LP64
7455 /**
7456  * Helper for multiply_to_len().
7457  */
7458 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7459   addq(dest_lo, src1);
7460   adcq(dest_hi, 0);
7461   addq(dest_lo, src2);
7462   adcq(dest_hi, 0);
7463 }
7464 
7465 /**
7466  * Multiply 64 bit by 64 bit first loop.
7467  */
7468 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7469                                            Register y, Register y_idx, Register z,
7470                                            Register carry, Register product,
7471                                            Register idx, Register kdx) {
7472   //
7473   //  jlong carry, x[], y[], z[];
7474   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7475   //    huge_128 product = y[idx] * x[xstart] + carry;
7476   //    z[kdx] = (jlong)product;
7477   //    carry  = (jlong)(product >>> 64);
7478   //  }
7479   //  z[xstart] = carry;
7480   //
7481 
7482   Label L_first_loop, L_first_loop_exit;
7483   Label L_one_x, L_one_y, L_multiply;
7484 
7485   decrementl(xstart);
7486   jcc(Assembler::negative, L_one_x);
7487 
7488   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
7489   rorq(x_xstart, 32); // convert big-endian to little-endian
7490 
7491   bind(L_first_loop);
7492   decrementl(idx);
7493   jcc(Assembler::negative, L_first_loop_exit);
7494   decrementl(idx);
7495   jcc(Assembler::negative, L_one_y);
7496   movq(y_idx, Address(y, idx, Address::times_4,  0));
7497   rorq(y_idx, 32); // convert big-endian to little-endian
7498   bind(L_multiply);
7499   movq(product, x_xstart);
7500   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7501   addq(product, carry);
7502   adcq(rdx, 0);
7503   subl(kdx, 2);
7504   movl(Address(z, kdx, Address::times_4,  4), product);
7505   shrq(product, 32);
7506   movl(Address(z, kdx, Address::times_4,  0), product);
7507   movq(carry, rdx);
7508   jmp(L_first_loop);
7509 
7510   bind(L_one_y);
7511   movl(y_idx, Address(y,  0));
7512   jmp(L_multiply);
7513 
7514   bind(L_one_x);
7515   movl(x_xstart, Address(x,  0));
7516   jmp(L_first_loop);
7517 
7518   bind(L_first_loop_exit);
7519 }
7520 
7521 /**
7522  * Multiply 64 bit by 64 bit and add 128 bit.
7523  */
7524 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7525                                             Register yz_idx, Register idx,
7526                                             Register carry, Register product, int offset) {
7527   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7528   //     z[kdx] = (jlong)product;
7529 
7530   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
7531   rorq(yz_idx, 32); // convert big-endian to little-endian
7532   movq(product, x_xstart);
7533   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
7534   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
7535   rorq(yz_idx, 32); // convert big-endian to little-endian
7536 
7537   add2_with_carry(rdx, product, carry, yz_idx);
7538 
7539   movl(Address(z, idx, Address::times_4,  offset+4), product);
7540   shrq(product, 32);
7541   movl(Address(z, idx, Address::times_4,  offset), product);
7542 
7543 }
7544 
7545 /**
7546  * Multiply 128 bit by 128 bit. Unrolled inner loop.
7547  */
7548 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7549                                              Register yz_idx, Register idx, Register jdx,
7550                                              Register carry, Register product,
7551                                              Register carry2) {
7552   //   jlong carry, x[], y[], z[];
7553   //   int kdx = ystart+1;
7554   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7555   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7556   //     z[kdx+idx+1] = (jlong)product;
7557   //     jlong carry2  = (jlong)(product >>> 64);
7558   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7559   //     z[kdx+idx] = (jlong)product;
7560   //     carry  = (jlong)(product >>> 64);
7561   //   }
7562   //   idx += 2;
7563   //   if (idx > 0) {
7564   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7565   //     z[kdx+idx] = (jlong)product;
7566   //     carry  = (jlong)(product >>> 64);
7567   //   }
7568   //
7569 
7570   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7571 
7572   movl(jdx, idx);
7573   andl(jdx, 0xFFFFFFFC);
7574   shrl(jdx, 2);
7575 
7576   bind(L_third_loop);
7577   subl(jdx, 1);
7578   jcc(Assembler::negative, L_third_loop_exit);
7579   subl(idx, 4);
7580 
7581   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7582   movq(carry2, rdx);
7583 
7584   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7585   movq(carry, rdx);
7586   jmp(L_third_loop);
7587 
7588   bind (L_third_loop_exit);
7589 
7590   andl (idx, 0x3);
7591   jcc(Assembler::zero, L_post_third_loop_done);
7592 
7593   Label L_check_1;
7594   subl(idx, 2);
7595   jcc(Assembler::negative, L_check_1);
7596 
7597   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7598   movq(carry, rdx);
7599 
7600   bind (L_check_1);
7601   addl (idx, 0x2);
7602   andl (idx, 0x1);
7603   subl(idx, 1);
7604   jcc(Assembler::negative, L_post_third_loop_done);
7605 
7606   movl(yz_idx, Address(y, idx, Address::times_4,  0));
7607   movq(product, x_xstart);
7608   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7609   movl(yz_idx, Address(z, idx, Address::times_4,  0));
7610 
7611   add2_with_carry(rdx, product, yz_idx, carry);
7612 
7613   movl(Address(z, idx, Address::times_4,  0), product);
7614   shrq(product, 32);
7615 
7616   shlq(rdx, 32);
7617   orq(product, rdx);
7618   movq(carry, product);
7619 
7620   bind(L_post_third_loop_done);
7621 }
7622 
7623 /**
7624  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7625  *
7626  */
7627 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7628                                                   Register carry, Register carry2,
7629                                                   Register idx, Register jdx,
7630                                                   Register yz_idx1, Register yz_idx2,
7631                                                   Register tmp, Register tmp3, Register tmp4) {
7632   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7633 
7634   //   jlong carry, x[], y[], z[];
7635   //   int kdx = ystart+1;
7636   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7637   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7638   //     jlong carry2  = (jlong)(tmp3 >>> 64);
7639   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
7640   //     carry  = (jlong)(tmp4 >>> 64);
7641   //     z[kdx+idx+1] = (jlong)tmp3;
7642   //     z[kdx+idx] = (jlong)tmp4;
7643   //   }
7644   //   idx += 2;
7645   //   if (idx > 0) {
7646   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7647   //     z[kdx+idx] = (jlong)yz_idx1;
7648   //     carry  = (jlong)(yz_idx1 >>> 64);
7649   //   }
7650   //
7651 
7652   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7653 
7654   movl(jdx, idx);
7655   andl(jdx, 0xFFFFFFFC);
7656   shrl(jdx, 2);
7657 
7658   bind(L_third_loop);
7659   subl(jdx, 1);
7660   jcc(Assembler::negative, L_third_loop_exit);
7661   subl(idx, 4);
7662 
7663   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
7664   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7665   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
7666   rorxq(yz_idx2, yz_idx2, 32);
7667 
7668   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
7669   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
7670 
7671   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
7672   rorxq(yz_idx1, yz_idx1, 32);
7673   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
7674   rorxq(yz_idx2, yz_idx2, 32);
7675 
7676   if (VM_Version::supports_adx()) {
7677     adcxq(tmp3, carry);
7678     adoxq(tmp3, yz_idx1);
7679 
7680     adcxq(tmp4, tmp);
7681     adoxq(tmp4, yz_idx2);
7682 
7683     movl(carry, 0); // does not affect flags
7684     adcxq(carry2, carry);
7685     adoxq(carry2, carry);
7686   } else {
7687     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7688     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7689   }
7690   movq(carry, carry2);
7691 
7692   movl(Address(z, idx, Address::times_4, 12), tmp3);
7693   shrq(tmp3, 32);
7694   movl(Address(z, idx, Address::times_4,  8), tmp3);
7695 
7696   movl(Address(z, idx, Address::times_4,  4), tmp4);
7697   shrq(tmp4, 32);
7698   movl(Address(z, idx, Address::times_4,  0), tmp4);
7699 
7700   jmp(L_third_loop);
7701 
7702   bind (L_third_loop_exit);
7703 
7704   andl (idx, 0x3);
7705   jcc(Assembler::zero, L_post_third_loop_done);
7706 
7707   Label L_check_1;
7708   subl(idx, 2);
7709   jcc(Assembler::negative, L_check_1);
7710 
7711   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
7712   rorxq(yz_idx1, yz_idx1, 32);
7713   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
7714   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
7715   rorxq(yz_idx2, yz_idx2, 32);
7716 
7717   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7718 
7719   movl(Address(z, idx, Address::times_4,  4), tmp3);
7720   shrq(tmp3, 32);
7721   movl(Address(z, idx, Address::times_4,  0), tmp3);
7722   movq(carry, tmp4);
7723 
7724   bind (L_check_1);
7725   addl (idx, 0x2);
7726   andl (idx, 0x1);
7727   subl(idx, 1);
7728   jcc(Assembler::negative, L_post_third_loop_done);
7729   movl(tmp4, Address(y, idx, Address::times_4,  0));
7730   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
7731   movl(tmp4, Address(z, idx, Address::times_4,  0));
7732 
7733   add2_with_carry(carry2, tmp3, tmp4, carry);
7734 
7735   movl(Address(z, idx, Address::times_4,  0), tmp3);
7736   shrq(tmp3, 32);
7737 
7738   shlq(carry2, 32);
7739   orq(tmp3, carry2);
7740   movq(carry, tmp3);
7741 
7742   bind(L_post_third_loop_done);
7743 }
7744 
7745 /**
7746  * Code for BigInteger::multiplyToLen() instrinsic.
7747  *
7748  * rdi: x
7749  * rax: xlen
7750  * rsi: y
7751  * rcx: ylen
7752  * r8:  z
7753  * r11: zlen
7754  * r12: tmp1
7755  * r13: tmp2
7756  * r14: tmp3
7757  * r15: tmp4
7758  * rbx: tmp5
7759  *
7760  */
7761 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7762                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7763   ShortBranchVerifier sbv(this);
7764   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7765 
7766   push(tmp1);
7767   push(tmp2);
7768   push(tmp3);
7769   push(tmp4);
7770   push(tmp5);
7771 
7772   push(xlen);
7773   push(zlen);
7774 
7775   const Register idx = tmp1;
7776   const Register kdx = tmp2;
7777   const Register xstart = tmp3;
7778 
7779   const Register y_idx = tmp4;
7780   const Register carry = tmp5;
7781   const Register product  = xlen;
7782   const Register x_xstart = zlen;  // reuse register
7783 
7784   // First Loop.
7785   //
7786   //  final static long LONG_MASK = 0xffffffffL;
7787   //  int xstart = xlen - 1;
7788   //  int ystart = ylen - 1;
7789   //  long carry = 0;
7790   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7791   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7792   //    z[kdx] = (int)product;
7793   //    carry = product >>> 32;
7794   //  }
7795   //  z[xstart] = (int)carry;
7796   //
7797 
7798   movl(idx, ylen);      // idx = ylen;
7799   movl(kdx, zlen);      // kdx = xlen+ylen;
7800   xorq(carry, carry);   // carry = 0;
7801 
7802   Label L_done;
7803 
7804   movl(xstart, xlen);
7805   decrementl(xstart);
7806   jcc(Assembler::negative, L_done);
7807 
7808   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7809 
7810   Label L_second_loop;
7811   testl(kdx, kdx);
7812   jcc(Assembler::zero, L_second_loop);
7813 
7814   Label L_carry;
7815   subl(kdx, 1);
7816   jcc(Assembler::zero, L_carry);
7817 
7818   movl(Address(z, kdx, Address::times_4,  0), carry);
7819   shrq(carry, 32);
7820   subl(kdx, 1);
7821 
7822   bind(L_carry);
7823   movl(Address(z, kdx, Address::times_4,  0), carry);
7824 
7825   // Second and third (nested) loops.
7826   //
7827   // for (int i = xstart-1; i >= 0; i--) { // Second loop
7828   //   carry = 0;
7829   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7830   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7831   //                    (z[k] & LONG_MASK) + carry;
7832   //     z[k] = (int)product;
7833   //     carry = product >>> 32;
7834   //   }
7835   //   z[i] = (int)carry;
7836   // }
7837   //
7838   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7839 
7840   const Register jdx = tmp1;
7841 
7842   bind(L_second_loop);
7843   xorl(carry, carry);    // carry = 0;
7844   movl(jdx, ylen);       // j = ystart+1
7845 
7846   subl(xstart, 1);       // i = xstart-1;
7847   jcc(Assembler::negative, L_done);
7848 
7849   push (z);
7850 
7851   Label L_last_x;
7852   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7853   subl(xstart, 1);       // i = xstart-1;
7854   jcc(Assembler::negative, L_last_x);
7855 
7856   if (UseBMI2Instructions) {
7857     movq(rdx,  Address(x, xstart, Address::times_4,  0));
7858     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7859   } else {
7860     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
7861     rorq(x_xstart, 32);  // convert big-endian to little-endian
7862   }
7863 
7864   Label L_third_loop_prologue;
7865   bind(L_third_loop_prologue);
7866 
7867   push (x);
7868   push (xstart);
7869   push (ylen);
7870 
7871 
7872   if (UseBMI2Instructions) {
7873     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7874   } else { // !UseBMI2Instructions
7875     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7876   }
7877 
7878   pop(ylen);
7879   pop(xlen);
7880   pop(x);
7881   pop(z);
7882 
7883   movl(tmp3, xlen);
7884   addl(tmp3, 1);
7885   movl(Address(z, tmp3, Address::times_4,  0), carry);
7886   subl(tmp3, 1);
7887   jccb(Assembler::negative, L_done);
7888 
7889   shrq(carry, 32);
7890   movl(Address(z, tmp3, Address::times_4,  0), carry);
7891   jmp(L_second_loop);
7892 
7893   // Next infrequent code is moved outside loops.
7894   bind(L_last_x);
7895   if (UseBMI2Instructions) {
7896     movl(rdx, Address(x,  0));
7897   } else {
7898     movl(x_xstart, Address(x,  0));
7899   }
7900   jmp(L_third_loop_prologue);
7901 
7902   bind(L_done);
7903 
7904   pop(zlen);
7905   pop(xlen);
7906 
7907   pop(tmp5);
7908   pop(tmp4);
7909   pop(tmp3);
7910   pop(tmp2);
7911   pop(tmp1);
7912 }
7913 
7914 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7915   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7916   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7917   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7918   Label VECTOR8_TAIL, VECTOR4_TAIL;
7919   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7920   Label SAME_TILL_END, DONE;
7921   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7922 
7923   //scale is in rcx in both Win64 and Unix
7924   ShortBranchVerifier sbv(this);
7925 
7926   shlq(length);
7927   xorq(result, result);
7928 
7929   if ((UseAVX > 2) &&
7930       VM_Version::supports_avx512vlbw()) {
7931     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7932 
7933     cmpq(length, 64);
7934     jcc(Assembler::less, VECTOR32_TAIL);
7935     movq(tmp1, length);
7936     andq(tmp1, 0x3F);      // tail count
7937     andq(length, ~(0x3F)); //vector count
7938 
7939     bind(VECTOR64_LOOP);
7940     // AVX512 code to compare 64 byte vectors.
7941     evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7942     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7943     kortestql(k7, k7);
7944     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
7945     addq(result, 64);
7946     subq(length, 64);
7947     jccb(Assembler::notZero, VECTOR64_LOOP);
7948 
7949     //bind(VECTOR64_TAIL);
7950     testq(tmp1, tmp1);
7951     jcc(Assembler::zero, SAME_TILL_END);
7952 
7953     //bind(VECTOR64_TAIL);
7954     // AVX512 code to compare upto 63 byte vectors.
7955     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7956     shlxq(tmp2, tmp2, tmp1);
7957     notq(tmp2);
7958     kmovql(k3, tmp2);
7959 
7960     evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
7961     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7962 
7963     ktestql(k7, k3);
7964     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
7965 
7966     bind(VECTOR64_NOT_EQUAL);
7967     kmovql(tmp1, k7);
7968     notq(tmp1);
7969     tzcntq(tmp1, tmp1);
7970     addq(result, tmp1);
7971     shrq(result);
7972     jmp(DONE);
7973     bind(VECTOR32_TAIL);
7974   }
7975 
7976   cmpq(length, 8);
7977   jcc(Assembler::equal, VECTOR8_LOOP);
7978   jcc(Assembler::less, VECTOR4_TAIL);
7979 
7980   if (UseAVX >= 2) {
7981     Label VECTOR16_TAIL, VECTOR32_LOOP;
7982 
7983     cmpq(length, 16);
7984     jcc(Assembler::equal, VECTOR16_LOOP);
7985     jcc(Assembler::less, VECTOR8_LOOP);
7986 
7987     cmpq(length, 32);
7988     jccb(Assembler::less, VECTOR16_TAIL);
7989 
7990     subq(length, 32);
7991     bind(VECTOR32_LOOP);
7992     vmovdqu(rymm0, Address(obja, result));
7993     vmovdqu(rymm1, Address(objb, result));
7994     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7995     vptest(rymm2, rymm2);
7996     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7997     addq(result, 32);
7998     subq(length, 32);
7999     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8000     addq(length, 32);
8001     jcc(Assembler::equal, SAME_TILL_END);
8002     //falling through if less than 32 bytes left //close the branch here.
8003 
8004     bind(VECTOR16_TAIL);
8005     cmpq(length, 16);
8006     jccb(Assembler::less, VECTOR8_TAIL);
8007     bind(VECTOR16_LOOP);
8008     movdqu(rymm0, Address(obja, result));
8009     movdqu(rymm1, Address(objb, result));
8010     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8011     ptest(rymm2, rymm2);
8012     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8013     addq(result, 16);
8014     subq(length, 16);
8015     jcc(Assembler::equal, SAME_TILL_END);
8016     //falling through if less than 16 bytes left
8017   } else {//regular intrinsics
8018 
8019     cmpq(length, 16);
8020     jccb(Assembler::less, VECTOR8_TAIL);
8021 
8022     subq(length, 16);
8023     bind(VECTOR16_LOOP);
8024     movdqu(rymm0, Address(obja, result));
8025     movdqu(rymm1, Address(objb, result));
8026     pxor(rymm0, rymm1);
8027     ptest(rymm0, rymm0);
8028     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8029     addq(result, 16);
8030     subq(length, 16);
8031     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8032     addq(length, 16);
8033     jcc(Assembler::equal, SAME_TILL_END);
8034     //falling through if less than 16 bytes left
8035   }
8036 
8037   bind(VECTOR8_TAIL);
8038   cmpq(length, 8);
8039   jccb(Assembler::less, VECTOR4_TAIL);
8040   bind(VECTOR8_LOOP);
8041   movq(tmp1, Address(obja, result));
8042   movq(tmp2, Address(objb, result));
8043   xorq(tmp1, tmp2);
8044   testq(tmp1, tmp1);
8045   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8046   addq(result, 8);
8047   subq(length, 8);
8048   jcc(Assembler::equal, SAME_TILL_END);
8049   //falling through if less than 8 bytes left
8050 
8051   bind(VECTOR4_TAIL);
8052   cmpq(length, 4);
8053   jccb(Assembler::less, BYTES_TAIL);
8054   bind(VECTOR4_LOOP);
8055   movl(tmp1, Address(obja, result));
8056   xorl(tmp1, Address(objb, result));
8057   testl(tmp1, tmp1);
8058   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8059   addq(result, 4);
8060   subq(length, 4);
8061   jcc(Assembler::equal, SAME_TILL_END);
8062   //falling through if less than 4 bytes left
8063 
8064   bind(BYTES_TAIL);
8065   bind(BYTES_LOOP);
8066   load_unsigned_byte(tmp1, Address(obja, result));
8067   load_unsigned_byte(tmp2, Address(objb, result));
8068   xorl(tmp1, tmp2);
8069   testl(tmp1, tmp1);
8070   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8071   decq(length);
8072   jcc(Assembler::zero, SAME_TILL_END);
8073   incq(result);
8074   load_unsigned_byte(tmp1, Address(obja, result));
8075   load_unsigned_byte(tmp2, Address(objb, result));
8076   xorl(tmp1, tmp2);
8077   testl(tmp1, tmp1);
8078   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8079   decq(length);
8080   jcc(Assembler::zero, SAME_TILL_END);
8081   incq(result);
8082   load_unsigned_byte(tmp1, Address(obja, result));
8083   load_unsigned_byte(tmp2, Address(objb, result));
8084   xorl(tmp1, tmp2);
8085   testl(tmp1, tmp1);
8086   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8087   jmp(SAME_TILL_END);
8088 
8089   if (UseAVX >= 2) {
8090     bind(VECTOR32_NOT_EQUAL);
8091     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8092     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8093     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8094     vpmovmskb(tmp1, rymm0);
8095     bsfq(tmp1, tmp1);
8096     addq(result, tmp1);
8097     shrq(result);
8098     jmp(DONE);
8099   }
8100 
8101   bind(VECTOR16_NOT_EQUAL);
8102   if (UseAVX >= 2) {
8103     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8104     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8105     pxor(rymm0, rymm2);
8106   } else {
8107     pcmpeqb(rymm2, rymm2);
8108     pxor(rymm0, rymm1);
8109     pcmpeqb(rymm0, rymm1);
8110     pxor(rymm0, rymm2);
8111   }
8112   pmovmskb(tmp1, rymm0);
8113   bsfq(tmp1, tmp1);
8114   addq(result, tmp1);
8115   shrq(result);
8116   jmpb(DONE);
8117 
8118   bind(VECTOR8_NOT_EQUAL);
8119   bind(VECTOR4_NOT_EQUAL);
8120   bsfq(tmp1, tmp1);
8121   shrq(tmp1, 3);
8122   addq(result, tmp1);
8123   bind(BYTES_NOT_EQUAL);
8124   shrq(result);
8125   jmpb(DONE);
8126 
8127   bind(SAME_TILL_END);
8128   mov64(result, -1);
8129 
8130   bind(DONE);
8131 }
8132 
8133 //Helper functions for square_to_len()
8134 
8135 /**
8136  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8137  * Preserves x and z and modifies rest of the registers.
8138  */
8139 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8140   // Perform square and right shift by 1
8141   // Handle odd xlen case first, then for even xlen do the following
8142   // jlong carry = 0;
8143   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8144   //     huge_128 product = x[j:j+1] * x[j:j+1];
8145   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8146   //     z[i+2:i+3] = (jlong)(product >>> 1);
8147   //     carry = (jlong)product;
8148   // }
8149 
8150   xorq(tmp5, tmp5);     // carry
8151   xorq(rdxReg, rdxReg);
8152   xorl(tmp1, tmp1);     // index for x
8153   xorl(tmp4, tmp4);     // index for z
8154 
8155   Label L_first_loop, L_first_loop_exit;
8156 
8157   testl(xlen, 1);
8158   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8159 
8160   // Square and right shift by 1 the odd element using 32 bit multiply
8161   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8162   imulq(raxReg, raxReg);
8163   shrq(raxReg, 1);
8164   adcq(tmp5, 0);
8165   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8166   incrementl(tmp1);
8167   addl(tmp4, 2);
8168 
8169   // Square and  right shift by 1 the rest using 64 bit multiply
8170   bind(L_first_loop);
8171   cmpptr(tmp1, xlen);
8172   jccb(Assembler::equal, L_first_loop_exit);
8173 
8174   // Square
8175   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
8176   rorq(raxReg, 32);    // convert big-endian to little-endian
8177   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
8178 
8179   // Right shift by 1 and save carry
8180   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8181   rcrq(rdxReg, 1);
8182   rcrq(raxReg, 1);
8183   adcq(tmp5, 0);
8184 
8185   // Store result in z
8186   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8187   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8188 
8189   // Update indices for x and z
8190   addl(tmp1, 2);
8191   addl(tmp4, 4);
8192   jmp(L_first_loop);
8193 
8194   bind(L_first_loop_exit);
8195 }
8196 
8197 
8198 /**
8199  * Perform the following multiply add operation using BMI2 instructions
8200  * carry:sum = sum + op1*op2 + carry
8201  * op2 should be in rdx
8202  * op2 is preserved, all other registers are modified
8203  */
8204 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8205   // assert op2 is rdx
8206   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
8207   addq(sum, carry);
8208   adcq(tmp2, 0);
8209   addq(sum, op1);
8210   adcq(tmp2, 0);
8211   movq(carry, tmp2);
8212 }
8213 
8214 /**
8215  * Perform the following multiply add operation:
8216  * carry:sum = sum + op1*op2 + carry
8217  * Preserves op1, op2 and modifies rest of registers
8218  */
8219 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8220   // rdx:rax = op1 * op2
8221   movq(raxReg, op2);
8222   mulq(op1);
8223 
8224   //  rdx:rax = sum + carry + rdx:rax
8225   addq(sum, carry);
8226   adcq(rdxReg, 0);
8227   addq(sum, raxReg);
8228   adcq(rdxReg, 0);
8229 
8230   // carry:sum = rdx:sum
8231   movq(carry, rdxReg);
8232 }
8233 
8234 /**
8235  * Add 64 bit long carry into z[] with carry propogation.
8236  * Preserves z and carry register values and modifies rest of registers.
8237  *
8238  */
8239 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8240   Label L_fourth_loop, L_fourth_loop_exit;
8241 
8242   movl(tmp1, 1);
8243   subl(zlen, 2);
8244   addq(Address(z, zlen, Address::times_4, 0), carry);
8245 
8246   bind(L_fourth_loop);
8247   jccb(Assembler::carryClear, L_fourth_loop_exit);
8248   subl(zlen, 2);
8249   jccb(Assembler::negative, L_fourth_loop_exit);
8250   addq(Address(z, zlen, Address::times_4, 0), tmp1);
8251   jmp(L_fourth_loop);
8252   bind(L_fourth_loop_exit);
8253 }
8254 
8255 /**
8256  * Shift z[] left by 1 bit.
8257  * Preserves x, len, z and zlen registers and modifies rest of the registers.
8258  *
8259  */
8260 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8261 
8262   Label L_fifth_loop, L_fifth_loop_exit;
8263 
8264   // Fifth loop
8265   // Perform primitiveLeftShift(z, zlen, 1)
8266 
8267   const Register prev_carry = tmp1;
8268   const Register new_carry = tmp4;
8269   const Register value = tmp2;
8270   const Register zidx = tmp3;
8271 
8272   // int zidx, carry;
8273   // long value;
8274   // carry = 0;
8275   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8276   //    (carry:value)  = (z[i] << 1) | carry ;
8277   //    z[i] = value;
8278   // }
8279 
8280   movl(zidx, zlen);
8281   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8282 
8283   bind(L_fifth_loop);
8284   decl(zidx);  // Use decl to preserve carry flag
8285   decl(zidx);
8286   jccb(Assembler::negative, L_fifth_loop_exit);
8287 
8288   if (UseBMI2Instructions) {
8289      movq(value, Address(z, zidx, Address::times_4, 0));
8290      rclq(value, 1);
8291      rorxq(value, value, 32);
8292      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
8293   }
8294   else {
8295     // clear new_carry
8296     xorl(new_carry, new_carry);
8297 
8298     // Shift z[i] by 1, or in previous carry and save new carry
8299     movq(value, Address(z, zidx, Address::times_4, 0));
8300     shlq(value, 1);
8301     adcl(new_carry, 0);
8302 
8303     orq(value, prev_carry);
8304     rorq(value, 0x20);
8305     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
8306 
8307     // Set previous carry = new carry
8308     movl(prev_carry, new_carry);
8309   }
8310   jmp(L_fifth_loop);
8311 
8312   bind(L_fifth_loop_exit);
8313 }
8314 
8315 
8316 /**
8317  * Code for BigInteger::squareToLen() intrinsic
8318  *
8319  * rdi: x
8320  * rsi: len
8321  * r8:  z
8322  * rcx: zlen
8323  * r12: tmp1
8324  * r13: tmp2
8325  * r14: tmp3
8326  * r15: tmp4
8327  * rbx: tmp5
8328  *
8329  */
8330 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8331 
8332   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8333   push(tmp1);
8334   push(tmp2);
8335   push(tmp3);
8336   push(tmp4);
8337   push(tmp5);
8338 
8339   // First loop
8340   // Store the squares, right shifted one bit (i.e., divided by 2).
8341   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8342 
8343   // Add in off-diagonal sums.
8344   //
8345   // Second, third (nested) and fourth loops.
8346   // zlen +=2;
8347   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8348   //    carry = 0;
8349   //    long op2 = x[xidx:xidx+1];
8350   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8351   //       k -= 2;
8352   //       long op1 = x[j:j+1];
8353   //       long sum = z[k:k+1];
8354   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8355   //       z[k:k+1] = sum;
8356   //    }
8357   //    add_one_64(z, k, carry, tmp_regs);
8358   // }
8359 
8360   const Register carry = tmp5;
8361   const Register sum = tmp3;
8362   const Register op1 = tmp4;
8363   Register op2 = tmp2;
8364 
8365   push(zlen);
8366   push(len);
8367   addl(zlen,2);
8368   bind(L_second_loop);
8369   xorq(carry, carry);
8370   subl(zlen, 4);
8371   subl(len, 2);
8372   push(zlen);
8373   push(len);
8374   cmpl(len, 0);
8375   jccb(Assembler::lessEqual, L_second_loop_exit);
8376 
8377   // Multiply an array by one 64 bit long.
8378   if (UseBMI2Instructions) {
8379     op2 = rdxReg;
8380     movq(op2, Address(x, len, Address::times_4,  0));
8381     rorxq(op2, op2, 32);
8382   }
8383   else {
8384     movq(op2, Address(x, len, Address::times_4,  0));
8385     rorq(op2, 32);
8386   }
8387 
8388   bind(L_third_loop);
8389   decrementl(len);
8390   jccb(Assembler::negative, L_third_loop_exit);
8391   decrementl(len);
8392   jccb(Assembler::negative, L_last_x);
8393 
8394   movq(op1, Address(x, len, Address::times_4,  0));
8395   rorq(op1, 32);
8396 
8397   bind(L_multiply);
8398   subl(zlen, 2);
8399   movq(sum, Address(z, zlen, Address::times_4,  0));
8400 
8401   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8402   if (UseBMI2Instructions) {
8403     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8404   }
8405   else {
8406     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8407   }
8408 
8409   movq(Address(z, zlen, Address::times_4, 0), sum);
8410 
8411   jmp(L_third_loop);
8412   bind(L_third_loop_exit);
8413 
8414   // Fourth loop
8415   // Add 64 bit long carry into z with carry propogation.
8416   // Uses offsetted zlen.
8417   add_one_64(z, zlen, carry, tmp1);
8418 
8419   pop(len);
8420   pop(zlen);
8421   jmp(L_second_loop);
8422 
8423   // Next infrequent code is moved outside loops.
8424   bind(L_last_x);
8425   movl(op1, Address(x, 0));
8426   jmp(L_multiply);
8427 
8428   bind(L_second_loop_exit);
8429   pop(len);
8430   pop(zlen);
8431   pop(len);
8432   pop(zlen);
8433 
8434   // Fifth loop
8435   // Shift z left 1 bit.
8436   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8437 
8438   // z[zlen-1] |= x[len-1] & 1;
8439   movl(tmp3, Address(x, len, Address::times_4, -4));
8440   andl(tmp3, 1);
8441   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
8442 
8443   pop(tmp5);
8444   pop(tmp4);
8445   pop(tmp3);
8446   pop(tmp2);
8447   pop(tmp1);
8448 }
8449 
8450 /**
8451  * Helper function for mul_add()
8452  * Multiply the in[] by int k and add to out[] starting at offset offs using
8453  * 128 bit by 32 bit multiply and return the carry in tmp5.
8454  * Only quad int aligned length of in[] is operated on in this function.
8455  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8456  * This function preserves out, in and k registers.
8457  * len and offset point to the appropriate index in "in" & "out" correspondingly
8458  * tmp5 has the carry.
8459  * other registers are temporary and are modified.
8460  *
8461  */
8462 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8463   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8464   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8465 
8466   Label L_first_loop, L_first_loop_exit;
8467 
8468   movl(tmp1, len);
8469   shrl(tmp1, 2);
8470 
8471   bind(L_first_loop);
8472   subl(tmp1, 1);
8473   jccb(Assembler::negative, L_first_loop_exit);
8474 
8475   subl(len, 4);
8476   subl(offset, 4);
8477 
8478   Register op2 = tmp2;
8479   const Register sum = tmp3;
8480   const Register op1 = tmp4;
8481   const Register carry = tmp5;
8482 
8483   if (UseBMI2Instructions) {
8484     op2 = rdxReg;
8485   }
8486 
8487   movq(op1, Address(in, len, Address::times_4,  8));
8488   rorq(op1, 32);
8489   movq(sum, Address(out, offset, Address::times_4,  8));
8490   rorq(sum, 32);
8491   if (UseBMI2Instructions) {
8492     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8493   }
8494   else {
8495     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8496   }
8497   // Store back in big endian from little endian
8498   rorq(sum, 0x20);
8499   movq(Address(out, offset, Address::times_4,  8), sum);
8500 
8501   movq(op1, Address(in, len, Address::times_4,  0));
8502   rorq(op1, 32);
8503   movq(sum, Address(out, offset, Address::times_4,  0));
8504   rorq(sum, 32);
8505   if (UseBMI2Instructions) {
8506     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8507   }
8508   else {
8509     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8510   }
8511   // Store back in big endian from little endian
8512   rorq(sum, 0x20);
8513   movq(Address(out, offset, Address::times_4,  0), sum);
8514 
8515   jmp(L_first_loop);
8516   bind(L_first_loop_exit);
8517 }
8518 
8519 /**
8520  * Code for BigInteger::mulAdd() intrinsic
8521  *
8522  * rdi: out
8523  * rsi: in
8524  * r11: offs (out.length - offset)
8525  * rcx: len
8526  * r8:  k
8527  * r12: tmp1
8528  * r13: tmp2
8529  * r14: tmp3
8530  * r15: tmp4
8531  * rbx: tmp5
8532  * Multiply the in[] by word k and add to out[], return the carry in rax
8533  */
8534 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8535    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8536    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8537 
8538   Label L_carry, L_last_in, L_done;
8539 
8540 // carry = 0;
8541 // for (int j=len-1; j >= 0; j--) {
8542 //    long product = (in[j] & LONG_MASK) * kLong +
8543 //                   (out[offs] & LONG_MASK) + carry;
8544 //    out[offs--] = (int)product;
8545 //    carry = product >>> 32;
8546 // }
8547 //
8548   push(tmp1);
8549   push(tmp2);
8550   push(tmp3);
8551   push(tmp4);
8552   push(tmp5);
8553 
8554   Register op2 = tmp2;
8555   const Register sum = tmp3;
8556   const Register op1 = tmp4;
8557   const Register carry =  tmp5;
8558 
8559   if (UseBMI2Instructions) {
8560     op2 = rdxReg;
8561     movl(op2, k);
8562   }
8563   else {
8564     movl(op2, k);
8565   }
8566 
8567   xorq(carry, carry);
8568 
8569   //First loop
8570 
8571   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8572   //The carry is in tmp5
8573   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8574 
8575   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8576   decrementl(len);
8577   jccb(Assembler::negative, L_carry);
8578   decrementl(len);
8579   jccb(Assembler::negative, L_last_in);
8580 
8581   movq(op1, Address(in, len, Address::times_4,  0));
8582   rorq(op1, 32);
8583 
8584   subl(offs, 2);
8585   movq(sum, Address(out, offs, Address::times_4,  0));
8586   rorq(sum, 32);
8587 
8588   if (UseBMI2Instructions) {
8589     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8590   }
8591   else {
8592     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8593   }
8594 
8595   // Store back in big endian from little endian
8596   rorq(sum, 0x20);
8597   movq(Address(out, offs, Address::times_4,  0), sum);
8598 
8599   testl(len, len);
8600   jccb(Assembler::zero, L_carry);
8601 
8602   //Multiply the last in[] entry, if any
8603   bind(L_last_in);
8604   movl(op1, Address(in, 0));
8605   movl(sum, Address(out, offs, Address::times_4,  -4));
8606 
8607   movl(raxReg, k);
8608   mull(op1); //tmp4 * eax -> edx:eax
8609   addl(sum, carry);
8610   adcl(rdxReg, 0);
8611   addl(sum, raxReg);
8612   adcl(rdxReg, 0);
8613   movl(carry, rdxReg);
8614 
8615   movl(Address(out, offs, Address::times_4,  -4), sum);
8616 
8617   bind(L_carry);
8618   //return tmp5/carry as carry in rax
8619   movl(rax, carry);
8620 
8621   bind(L_done);
8622   pop(tmp5);
8623   pop(tmp4);
8624   pop(tmp3);
8625   pop(tmp2);
8626   pop(tmp1);
8627 }
8628 #endif
8629 
8630 /**
8631  * Emits code to update CRC-32 with a byte value according to constants in table
8632  *
8633  * @param [in,out]crc   Register containing the crc.
8634  * @param [in]val       Register containing the byte to fold into the CRC.
8635  * @param [in]table     Register containing the table of crc constants.
8636  *
8637  * uint32_t crc;
8638  * val = crc_table[(val ^ crc) & 0xFF];
8639  * crc = val ^ (crc >> 8);
8640  *
8641  */
8642 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8643   xorl(val, crc);
8644   andl(val, 0xFF);
8645   shrl(crc, 8); // unsigned shift
8646   xorl(crc, Address(table, val, Address::times_4, 0));
8647 }
8648 
8649 /**
8650 * Fold four 128-bit data chunks
8651 */
8652 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8653   evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8654   evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8655   evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8656   evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8657 }
8658 
8659 /**
8660  * Fold 128-bit data chunk
8661  */
8662 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8663   if (UseAVX > 0) {
8664     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8665     vpclmulldq(xcrc, xK, xcrc); // [63:0]
8666     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8667     pxor(xcrc, xtmp);
8668   } else {
8669     movdqa(xtmp, xcrc);
8670     pclmulhdq(xtmp, xK);   // [123:64]
8671     pclmulldq(xcrc, xK);   // [63:0]
8672     pxor(xcrc, xtmp);
8673     movdqu(xtmp, Address(buf, offset));
8674     pxor(xcrc, xtmp);
8675   }
8676 }
8677 
8678 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8679   if (UseAVX > 0) {
8680     vpclmulhdq(xtmp, xK, xcrc);
8681     vpclmulldq(xcrc, xK, xcrc);
8682     pxor(xcrc, xbuf);
8683     pxor(xcrc, xtmp);
8684   } else {
8685     movdqa(xtmp, xcrc);
8686     pclmulhdq(xtmp, xK);
8687     pclmulldq(xcrc, xK);
8688     pxor(xcrc, xbuf);
8689     pxor(xcrc, xtmp);
8690   }
8691 }
8692 
8693 /**
8694  * 8-bit folds to compute 32-bit CRC
8695  *
8696  * uint64_t xcrc;
8697  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8698  */
8699 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8700   movdl(tmp, xcrc);
8701   andl(tmp, 0xFF);
8702   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8703   psrldq(xcrc, 1); // unsigned shift one byte
8704   pxor(xcrc, xtmp);
8705 }
8706 
8707 /**
8708  * uint32_t crc;
8709  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8710  */
8711 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8712   movl(tmp, crc);
8713   andl(tmp, 0xFF);
8714   shrl(crc, 8);
8715   xorl(crc, Address(table, tmp, Address::times_4, 0));
8716 }
8717 
8718 /**
8719  * @param crc   register containing existing CRC (32-bit)
8720  * @param buf   register pointing to input byte buffer (byte*)
8721  * @param len   register containing number of bytes
8722  * @param table register that will contain address of CRC table
8723  * @param tmp   scratch register
8724  */
8725 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8726   assert_different_registers(crc, buf, len, table, tmp, rax);
8727 
8728   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8729   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8730 
8731   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8732   // context for the registers used, where all instructions below are using 128-bit mode
8733   // On EVEX without VL and BW, these instructions will all be AVX.
8734   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8735   notl(crc); // ~crc
8736   cmpl(len, 16);
8737   jcc(Assembler::less, L_tail);
8738 
8739   // Align buffer to 16 bytes
8740   movl(tmp, buf);
8741   andl(tmp, 0xF);
8742   jccb(Assembler::zero, L_aligned);
8743   subl(tmp,  16);
8744   addl(len, tmp);
8745 
8746   align(4);
8747   BIND(L_align_loop);
8748   movsbl(rax, Address(buf, 0)); // load byte with sign extension
8749   update_byte_crc32(crc, rax, table);
8750   increment(buf);
8751   incrementl(tmp);
8752   jccb(Assembler::less, L_align_loop);
8753 
8754   BIND(L_aligned);
8755   movl(tmp, len); // save
8756   shrl(len, 4);
8757   jcc(Assembler::zero, L_tail_restore);
8758 
8759   // Fold total 512 bits of polynomial on each iteration
8760   if (VM_Version::supports_vpclmulqdq()) {
8761     Label Parallel_loop, L_No_Parallel;
8762 
8763     cmpl(len, 8);
8764     jccb(Assembler::less, L_No_Parallel);
8765 
8766     movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8767     evmovdquq(xmm1, Address(buf, 0), Assembler::AVX_512bit);
8768     movdl(xmm5, crc);
8769     evpxorq(xmm1, xmm1, xmm5, Assembler::AVX_512bit);
8770     addptr(buf, 64);
8771     subl(len, 7);
8772     evshufi64x2(xmm0, xmm0, xmm0, 0x00, Assembler::AVX_512bit); //propagate the mask from 128 bits to 512 bits
8773 
8774     BIND(Parallel_loop);
8775     fold_128bit_crc32_avx512(xmm1, xmm0, xmm5, buf, 0);
8776     addptr(buf, 64);
8777     subl(len, 4);
8778     jcc(Assembler::greater, Parallel_loop);
8779 
8780     vextracti64x2(xmm2, xmm1, 0x01);
8781     vextracti64x2(xmm3, xmm1, 0x02);
8782     vextracti64x2(xmm4, xmm1, 0x03);
8783     jmp(L_fold_512b);
8784 
8785     BIND(L_No_Parallel);
8786   }
8787   // Fold crc into first bytes of vector
8788   movdqa(xmm1, Address(buf, 0));
8789   movdl(rax, xmm1);
8790   xorl(crc, rax);
8791   if (VM_Version::supports_sse4_1()) {
8792     pinsrd(xmm1, crc, 0);
8793   } else {
8794     pinsrw(xmm1, crc, 0);
8795     shrl(crc, 16);
8796     pinsrw(xmm1, crc, 1);
8797   }
8798   addptr(buf, 16);
8799   subl(len, 4); // len > 0
8800   jcc(Assembler::less, L_fold_tail);
8801 
8802   movdqa(xmm2, Address(buf,  0));
8803   movdqa(xmm3, Address(buf, 16));
8804   movdqa(xmm4, Address(buf, 32));
8805   addptr(buf, 48);
8806   subl(len, 3);
8807   jcc(Assembler::lessEqual, L_fold_512b);
8808 
8809   // Fold total 512 bits of polynomial on each iteration,
8810   // 128 bits per each of 4 parallel streams.
8811   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8812 
8813   align(32);
8814   BIND(L_fold_512b_loop);
8815   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
8816   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8817   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8818   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8819   addptr(buf, 64);
8820   subl(len, 4);
8821   jcc(Assembler::greater, L_fold_512b_loop);
8822 
8823   // Fold 512 bits to 128 bits.
8824   BIND(L_fold_512b);
8825   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8826   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8827   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8828   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8829 
8830   // Fold the rest of 128 bits data chunks
8831   BIND(L_fold_tail);
8832   addl(len, 3);
8833   jccb(Assembler::lessEqual, L_fold_128b);
8834   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8835 
8836   BIND(L_fold_tail_loop);
8837   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
8838   addptr(buf, 16);
8839   decrementl(len);
8840   jccb(Assembler::greater, L_fold_tail_loop);
8841 
8842   // Fold 128 bits in xmm1 down into 32 bits in crc register.
8843   BIND(L_fold_128b);
8844   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8845   if (UseAVX > 0) {
8846     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8847     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8848     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8849   } else {
8850     movdqa(xmm2, xmm0);
8851     pclmulqdq(xmm2, xmm1, 0x1);
8852     movdqa(xmm3, xmm0);
8853     pand(xmm3, xmm2);
8854     pclmulqdq(xmm0, xmm3, 0x1);
8855   }
8856   psrldq(xmm1, 8);
8857   psrldq(xmm2, 4);
8858   pxor(xmm0, xmm1);
8859   pxor(xmm0, xmm2);
8860 
8861   // 8 8-bit folds to compute 32-bit CRC.
8862   for (int j = 0; j < 4; j++) {
8863     fold_8bit_crc32(xmm0, table, xmm1, rax);
8864   }
8865   movdl(crc, xmm0); // mov 32 bits to general register
8866   for (int j = 0; j < 4; j++) {
8867     fold_8bit_crc32(crc, table, rax);
8868   }
8869 
8870   BIND(L_tail_restore);
8871   movl(len, tmp); // restore
8872   BIND(L_tail);
8873   andl(len, 0xf);
8874   jccb(Assembler::zero, L_exit);
8875 
8876   // Fold the rest of bytes
8877   align(4);
8878   BIND(L_tail_loop);
8879   movsbl(rax, Address(buf, 0)); // load byte with sign extension
8880   update_byte_crc32(crc, rax, table);
8881   increment(buf);
8882   decrementl(len);
8883   jccb(Assembler::greater, L_tail_loop);
8884 
8885   BIND(L_exit);
8886   notl(crc); // ~c
8887 }
8888 
8889 #ifdef _LP64
8890 // S. Gueron / Information Processing Letters 112 (2012) 184
8891 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8892 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8893 // Output: the 64-bit carry-less product of B * CONST
8894 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8895                                      Register tmp1, Register tmp2, Register tmp3) {
8896   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8897   if (n > 0) {
8898     addq(tmp3, n * 256 * 8);
8899   }
8900   //    Q1 = TABLEExt[n][B & 0xFF];
8901   movl(tmp1, in);
8902   andl(tmp1, 0x000000FF);
8903   shll(tmp1, 3);
8904   addq(tmp1, tmp3);
8905   movq(tmp1, Address(tmp1, 0));
8906 
8907   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
8908   movl(tmp2, in);
8909   shrl(tmp2, 8);
8910   andl(tmp2, 0x000000FF);
8911   shll(tmp2, 3);
8912   addq(tmp2, tmp3);
8913   movq(tmp2, Address(tmp2, 0));
8914 
8915   shlq(tmp2, 8);
8916   xorq(tmp1, tmp2);
8917 
8918   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
8919   movl(tmp2, in);
8920   shrl(tmp2, 16);
8921   andl(tmp2, 0x000000FF);
8922   shll(tmp2, 3);
8923   addq(tmp2, tmp3);
8924   movq(tmp2, Address(tmp2, 0));
8925 
8926   shlq(tmp2, 16);
8927   xorq(tmp1, tmp2);
8928 
8929   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
8930   shrl(in, 24);
8931   andl(in, 0x000000FF);
8932   shll(in, 3);
8933   addq(in, tmp3);
8934   movq(in, Address(in, 0));
8935 
8936   shlq(in, 24);
8937   xorq(in, tmp1);
8938   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8939 }
8940 
8941 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8942                                       Register in_out,
8943                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8944                                       XMMRegister w_xtmp2,
8945                                       Register tmp1,
8946                                       Register n_tmp2, Register n_tmp3) {
8947   if (is_pclmulqdq_supported) {
8948     movdl(w_xtmp1, in_out); // modified blindly
8949 
8950     movl(tmp1, const_or_pre_comp_const_index);
8951     movdl(w_xtmp2, tmp1);
8952     pclmulqdq(w_xtmp1, w_xtmp2, 0);
8953 
8954     movdq(in_out, w_xtmp1);
8955   } else {
8956     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8957   }
8958 }
8959 
8960 // Recombination Alternative 2: No bit-reflections
8961 // T1 = (CRC_A * U1) << 1
8962 // T2 = (CRC_B * U2) << 1
8963 // C1 = T1 >> 32
8964 // C2 = T2 >> 32
8965 // T1 = T1 & 0xFFFFFFFF
8966 // T2 = T2 & 0xFFFFFFFF
8967 // T1 = CRC32(0, T1)
8968 // T2 = CRC32(0, T2)
8969 // C1 = C1 ^ T1
8970 // C2 = C2 ^ T2
8971 // CRC = C1 ^ C2 ^ CRC_C
8972 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8973                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8974                                      Register tmp1, Register tmp2,
8975                                      Register n_tmp3) {
8976   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8977   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8978   shlq(in_out, 1);
8979   movl(tmp1, in_out);
8980   shrq(in_out, 32);
8981   xorl(tmp2, tmp2);
8982   crc32(tmp2, tmp1, 4);
8983   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8984   shlq(in1, 1);
8985   movl(tmp1, in1);
8986   shrq(in1, 32);
8987   xorl(tmp2, tmp2);
8988   crc32(tmp2, tmp1, 4);
8989   xorl(in1, tmp2);
8990   xorl(in_out, in1);
8991   xorl(in_out, in2);
8992 }
8993 
8994 // Set N to predefined value
8995 // Subtract from a lenght of a buffer
8996 // execute in a loop:
8997 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8998 // for i = 1 to N do
8999 //  CRC_A = CRC32(CRC_A, A[i])
9000 //  CRC_B = CRC32(CRC_B, B[i])
9001 //  CRC_C = CRC32(CRC_C, C[i])
9002 // end for
9003 // Recombine
9004 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9005                                        Register in_out1, Register in_out2, Register in_out3,
9006                                        Register tmp1, Register tmp2, Register tmp3,
9007                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9008                                        Register tmp4, Register tmp5,
9009                                        Register n_tmp6) {
9010   Label L_processPartitions;
9011   Label L_processPartition;
9012   Label L_exit;
9013 
9014   bind(L_processPartitions);
9015   cmpl(in_out1, 3 * size);
9016   jcc(Assembler::less, L_exit);
9017     xorl(tmp1, tmp1);
9018     xorl(tmp2, tmp2);
9019     movq(tmp3, in_out2);
9020     addq(tmp3, size);
9021 
9022     bind(L_processPartition);
9023       crc32(in_out3, Address(in_out2, 0), 8);
9024       crc32(tmp1, Address(in_out2, size), 8);
9025       crc32(tmp2, Address(in_out2, size * 2), 8);
9026       addq(in_out2, 8);
9027       cmpq(in_out2, tmp3);
9028       jcc(Assembler::less, L_processPartition);
9029     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9030             w_xtmp1, w_xtmp2, w_xtmp3,
9031             tmp4, tmp5,
9032             n_tmp6);
9033     addq(in_out2, 2 * size);
9034     subl(in_out1, 3 * size);
9035     jmp(L_processPartitions);
9036 
9037   bind(L_exit);
9038 }
9039 #else
9040 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9041                                      Register tmp1, Register tmp2, Register tmp3,
9042                                      XMMRegister xtmp1, XMMRegister xtmp2) {
9043   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9044   if (n > 0) {
9045     addl(tmp3, n * 256 * 8);
9046   }
9047   //    Q1 = TABLEExt[n][B & 0xFF];
9048   movl(tmp1, in_out);
9049   andl(tmp1, 0x000000FF);
9050   shll(tmp1, 3);
9051   addl(tmp1, tmp3);
9052   movq(xtmp1, Address(tmp1, 0));
9053 
9054   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
9055   movl(tmp2, in_out);
9056   shrl(tmp2, 8);
9057   andl(tmp2, 0x000000FF);
9058   shll(tmp2, 3);
9059   addl(tmp2, tmp3);
9060   movq(xtmp2, Address(tmp2, 0));
9061 
9062   psllq(xtmp2, 8);
9063   pxor(xtmp1, xtmp2);
9064 
9065   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
9066   movl(tmp2, in_out);
9067   shrl(tmp2, 16);
9068   andl(tmp2, 0x000000FF);
9069   shll(tmp2, 3);
9070   addl(tmp2, tmp3);
9071   movq(xtmp2, Address(tmp2, 0));
9072 
9073   psllq(xtmp2, 16);
9074   pxor(xtmp1, xtmp2);
9075 
9076   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
9077   shrl(in_out, 24);
9078   andl(in_out, 0x000000FF);
9079   shll(in_out, 3);
9080   addl(in_out, tmp3);
9081   movq(xtmp2, Address(in_out, 0));
9082 
9083   psllq(xtmp2, 24);
9084   pxor(xtmp1, xtmp2); // Result in CXMM
9085   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9086 }
9087 
9088 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9089                                       Register in_out,
9090                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9091                                       XMMRegister w_xtmp2,
9092                                       Register tmp1,
9093                                       Register n_tmp2, Register n_tmp3) {
9094   if (is_pclmulqdq_supported) {
9095     movdl(w_xtmp1, in_out);
9096 
9097     movl(tmp1, const_or_pre_comp_const_index);
9098     movdl(w_xtmp2, tmp1);
9099     pclmulqdq(w_xtmp1, w_xtmp2, 0);
9100     // Keep result in XMM since GPR is 32 bit in length
9101   } else {
9102     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9103   }
9104 }
9105 
9106 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9107                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9108                                      Register tmp1, Register tmp2,
9109                                      Register n_tmp3) {
9110   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9111   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9112 
9113   psllq(w_xtmp1, 1);
9114   movdl(tmp1, w_xtmp1);
9115   psrlq(w_xtmp1, 32);
9116   movdl(in_out, w_xtmp1);
9117 
9118   xorl(tmp2, tmp2);
9119   crc32(tmp2, tmp1, 4);
9120   xorl(in_out, tmp2);
9121 
9122   psllq(w_xtmp2, 1);
9123   movdl(tmp1, w_xtmp2);
9124   psrlq(w_xtmp2, 32);
9125   movdl(in1, w_xtmp2);
9126 
9127   xorl(tmp2, tmp2);
9128   crc32(tmp2, tmp1, 4);
9129   xorl(in1, tmp2);
9130   xorl(in_out, in1);
9131   xorl(in_out, in2);
9132 }
9133 
9134 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9135                                        Register in_out1, Register in_out2, Register in_out3,
9136                                        Register tmp1, Register tmp2, Register tmp3,
9137                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9138                                        Register tmp4, Register tmp5,
9139                                        Register n_tmp6) {
9140   Label L_processPartitions;
9141   Label L_processPartition;
9142   Label L_exit;
9143 
9144   bind(L_processPartitions);
9145   cmpl(in_out1, 3 * size);
9146   jcc(Assembler::less, L_exit);
9147     xorl(tmp1, tmp1);
9148     xorl(tmp2, tmp2);
9149     movl(tmp3, in_out2);
9150     addl(tmp3, size);
9151 
9152     bind(L_processPartition);
9153       crc32(in_out3, Address(in_out2, 0), 4);
9154       crc32(tmp1, Address(in_out2, size), 4);
9155       crc32(tmp2, Address(in_out2, size*2), 4);
9156       crc32(in_out3, Address(in_out2, 0+4), 4);
9157       crc32(tmp1, Address(in_out2, size+4), 4);
9158       crc32(tmp2, Address(in_out2, size*2+4), 4);
9159       addl(in_out2, 8);
9160       cmpl(in_out2, tmp3);
9161       jcc(Assembler::less, L_processPartition);
9162 
9163         push(tmp3);
9164         push(in_out1);
9165         push(in_out2);
9166         tmp4 = tmp3;
9167         tmp5 = in_out1;
9168         n_tmp6 = in_out2;
9169 
9170       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9171             w_xtmp1, w_xtmp2, w_xtmp3,
9172             tmp4, tmp5,
9173             n_tmp6);
9174 
9175         pop(in_out2);
9176         pop(in_out1);
9177         pop(tmp3);
9178 
9179     addl(in_out2, 2 * size);
9180     subl(in_out1, 3 * size);
9181     jmp(L_processPartitions);
9182 
9183   bind(L_exit);
9184 }
9185 #endif //LP64
9186 
9187 #ifdef _LP64
9188 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9189 // Input: A buffer I of L bytes.
9190 // Output: the CRC32C value of the buffer.
9191 // Notations:
9192 // Write L = 24N + r, with N = floor (L/24).
9193 // r = L mod 24 (0 <= r < 24).
9194 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9195 // N quadwords, and R consists of r bytes.
9196 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9197 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9198 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9199 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9200 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9201                                           Register tmp1, Register tmp2, Register tmp3,
9202                                           Register tmp4, Register tmp5, Register tmp6,
9203                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9204                                           bool is_pclmulqdq_supported) {
9205   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9206   Label L_wordByWord;
9207   Label L_byteByByteProlog;
9208   Label L_byteByByte;
9209   Label L_exit;
9210 
9211   if (is_pclmulqdq_supported ) {
9212     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9213     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9214 
9215     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9216     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9217 
9218     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9219     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9220     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9221   } else {
9222     const_or_pre_comp_const_index[0] = 1;
9223     const_or_pre_comp_const_index[1] = 0;
9224 
9225     const_or_pre_comp_const_index[2] = 3;
9226     const_or_pre_comp_const_index[3] = 2;
9227 
9228     const_or_pre_comp_const_index[4] = 5;
9229     const_or_pre_comp_const_index[5] = 4;
9230    }
9231   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9232                     in2, in1, in_out,
9233                     tmp1, tmp2, tmp3,
9234                     w_xtmp1, w_xtmp2, w_xtmp3,
9235                     tmp4, tmp5,
9236                     tmp6);
9237   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9238                     in2, in1, in_out,
9239                     tmp1, tmp2, tmp3,
9240                     w_xtmp1, w_xtmp2, w_xtmp3,
9241                     tmp4, tmp5,
9242                     tmp6);
9243   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9244                     in2, in1, in_out,
9245                     tmp1, tmp2, tmp3,
9246                     w_xtmp1, w_xtmp2, w_xtmp3,
9247                     tmp4, tmp5,
9248                     tmp6);
9249   movl(tmp1, in2);
9250   andl(tmp1, 0x00000007);
9251   negl(tmp1);
9252   addl(tmp1, in2);
9253   addq(tmp1, in1);
9254 
9255   BIND(L_wordByWord);
9256   cmpq(in1, tmp1);
9257   jcc(Assembler::greaterEqual, L_byteByByteProlog);
9258     crc32(in_out, Address(in1, 0), 4);
9259     addq(in1, 4);
9260     jmp(L_wordByWord);
9261 
9262   BIND(L_byteByByteProlog);
9263   andl(in2, 0x00000007);
9264   movl(tmp2, 1);
9265 
9266   BIND(L_byteByByte);
9267   cmpl(tmp2, in2);
9268   jccb(Assembler::greater, L_exit);
9269     crc32(in_out, Address(in1, 0), 1);
9270     incq(in1);
9271     incl(tmp2);
9272     jmp(L_byteByByte);
9273 
9274   BIND(L_exit);
9275 }
9276 #else
9277 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9278                                           Register tmp1, Register  tmp2, Register tmp3,
9279                                           Register tmp4, Register  tmp5, Register tmp6,
9280                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9281                                           bool is_pclmulqdq_supported) {
9282   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9283   Label L_wordByWord;
9284   Label L_byteByByteProlog;
9285   Label L_byteByByte;
9286   Label L_exit;
9287 
9288   if (is_pclmulqdq_supported) {
9289     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9290     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9291 
9292     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9293     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9294 
9295     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9296     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9297   } else {
9298     const_or_pre_comp_const_index[0] = 1;
9299     const_or_pre_comp_const_index[1] = 0;
9300 
9301     const_or_pre_comp_const_index[2] = 3;
9302     const_or_pre_comp_const_index[3] = 2;
9303 
9304     const_or_pre_comp_const_index[4] = 5;
9305     const_or_pre_comp_const_index[5] = 4;
9306   }
9307   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9308                     in2, in1, in_out,
9309                     tmp1, tmp2, tmp3,
9310                     w_xtmp1, w_xtmp2, w_xtmp3,
9311                     tmp4, tmp5,
9312                     tmp6);
9313   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9314                     in2, in1, in_out,
9315                     tmp1, tmp2, tmp3,
9316                     w_xtmp1, w_xtmp2, w_xtmp3,
9317                     tmp4, tmp5,
9318                     tmp6);
9319   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9320                     in2, in1, in_out,
9321                     tmp1, tmp2, tmp3,
9322                     w_xtmp1, w_xtmp2, w_xtmp3,
9323                     tmp4, tmp5,
9324                     tmp6);
9325   movl(tmp1, in2);
9326   andl(tmp1, 0x00000007);
9327   negl(tmp1);
9328   addl(tmp1, in2);
9329   addl(tmp1, in1);
9330 
9331   BIND(L_wordByWord);
9332   cmpl(in1, tmp1);
9333   jcc(Assembler::greaterEqual, L_byteByByteProlog);
9334     crc32(in_out, Address(in1,0), 4);
9335     addl(in1, 4);
9336     jmp(L_wordByWord);
9337 
9338   BIND(L_byteByByteProlog);
9339   andl(in2, 0x00000007);
9340   movl(tmp2, 1);
9341 
9342   BIND(L_byteByByte);
9343   cmpl(tmp2, in2);
9344   jccb(Assembler::greater, L_exit);
9345     movb(tmp1, Address(in1, 0));
9346     crc32(in_out, tmp1, 1);
9347     incl(in1);
9348     incl(tmp2);
9349     jmp(L_byteByByte);
9350 
9351   BIND(L_exit);
9352 }
9353 #endif // LP64
9354 #undef BIND
9355 #undef BLOCK_COMMENT
9356 
9357 // Compress char[] array to byte[].
9358 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9359 //   @HotSpotIntrinsicCandidate
9360 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9361 //     for (int i = 0; i < len; i++) {
9362 //       int c = src[srcOff++];
9363 //       if (c >>> 8 != 0) {
9364 //         return 0;
9365 //       }
9366 //       dst[dstOff++] = (byte)c;
9367 //     }
9368 //     return len;
9369 //   }
9370 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9371   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9372   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9373   Register tmp5, Register result) {
9374   Label copy_chars_loop, return_length, return_zero, done;
9375 
9376   // rsi: src
9377   // rdi: dst
9378   // rdx: len
9379   // rcx: tmp5
9380   // rax: result
9381 
9382   // rsi holds start addr of source char[] to be compressed
9383   // rdi holds start addr of destination byte[]
9384   // rdx holds length
9385 
9386   assert(len != result, "");
9387 
9388   // save length for return
9389   push(len);
9390 
9391   if ((UseAVX > 2) && // AVX512
9392     VM_Version::supports_avx512vlbw() &&
9393     VM_Version::supports_bmi2()) {
9394 
9395     Label copy_32_loop, copy_loop_tail, below_threshold;
9396 
9397     // alignment
9398     Label post_alignment;
9399 
9400     // if length of the string is less than 16, handle it in an old fashioned way
9401     testl(len, -32);
9402     jcc(Assembler::zero, below_threshold);
9403 
9404     // First check whether a character is compressable ( <= 0xFF).
9405     // Create mask to test for Unicode chars inside zmm vector
9406     movl(result, 0x00FF);
9407     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9408 
9409     testl(len, -64);
9410     jcc(Assembler::zero, post_alignment);
9411 
9412     movl(tmp5, dst);
9413     andl(tmp5, (32 - 1));
9414     negl(tmp5);
9415     andl(tmp5, (32 - 1));
9416 
9417     // bail out when there is nothing to be done
9418     testl(tmp5, 0xFFFFFFFF);
9419     jcc(Assembler::zero, post_alignment);
9420 
9421     // ~(~0 << len), where len is the # of remaining elements to process
9422     movl(result, 0xFFFFFFFF);
9423     shlxl(result, result, tmp5);
9424     notl(result);
9425     kmovdl(k3, result);
9426 
9427     evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9428     evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9429     ktestd(k2, k3);
9430     jcc(Assembler::carryClear, return_zero);
9431 
9432     evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9433 
9434     addptr(src, tmp5);
9435     addptr(src, tmp5);
9436     addptr(dst, tmp5);
9437     subl(len, tmp5);
9438 
9439     bind(post_alignment);
9440     // end of alignment
9441 
9442     movl(tmp5, len);
9443     andl(tmp5, (32 - 1));    // tail count (in chars)
9444     andl(len, ~(32 - 1));    // vector count (in chars)
9445     jcc(Assembler::zero, copy_loop_tail);
9446 
9447     lea(src, Address(src, len, Address::times_2));
9448     lea(dst, Address(dst, len, Address::times_1));
9449     negptr(len);
9450 
9451     bind(copy_32_loop);
9452     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9453     evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9454     kortestdl(k2, k2);
9455     jcc(Assembler::carryClear, return_zero);
9456 
9457     // All elements in current processed chunk are valid candidates for
9458     // compression. Write a truncated byte elements to the memory.
9459     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9460     addptr(len, 32);
9461     jcc(Assembler::notZero, copy_32_loop);
9462 
9463     bind(copy_loop_tail);
9464     // bail out when there is nothing to be done
9465     testl(tmp5, 0xFFFFFFFF);
9466     jcc(Assembler::zero, return_length);
9467 
9468     movl(len, tmp5);
9469 
9470     // ~(~0 << len), where len is the # of remaining elements to process
9471     movl(result, 0xFFFFFFFF);
9472     shlxl(result, result, len);
9473     notl(result);
9474 
9475     kmovdl(k3, result);
9476 
9477     evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9478     evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9479     ktestd(k2, k3);
9480     jcc(Assembler::carryClear, return_zero);
9481 
9482     evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9483     jmp(return_length);
9484 
9485     bind(below_threshold);
9486   }
9487 
9488   if (UseSSE42Intrinsics) {
9489     Label copy_32_loop, copy_16, copy_tail;
9490 
9491     movl(result, len);
9492 
9493     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
9494 
9495     // vectored compression
9496     andl(len, 0xfffffff0);    // vector count (in chars)
9497     andl(result, 0x0000000f);    // tail count (in chars)
9498     testl(len, len);
9499     jcc(Assembler::zero, copy_16);
9500 
9501     // compress 16 chars per iter
9502     movdl(tmp1Reg, tmp5);
9503     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
9504     pxor(tmp4Reg, tmp4Reg);
9505 
9506     lea(src, Address(src, len, Address::times_2));
9507     lea(dst, Address(dst, len, Address::times_1));
9508     negptr(len);
9509 
9510     bind(copy_32_loop);
9511     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
9512     por(tmp4Reg, tmp2Reg);
9513     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9514     por(tmp4Reg, tmp3Reg);
9515     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
9516     jcc(Assembler::notZero, return_zero);
9517     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
9518     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9519     addptr(len, 16);
9520     jcc(Assembler::notZero, copy_32_loop);
9521 
9522     // compress next vector of 8 chars (if any)
9523     bind(copy_16);
9524     movl(len, result);
9525     andl(len, 0xfffffff8);    // vector count (in chars)
9526     andl(result, 0x00000007);    // tail count (in chars)
9527     testl(len, len);
9528     jccb(Assembler::zero, copy_tail);
9529 
9530     movdl(tmp1Reg, tmp5);
9531     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
9532     pxor(tmp3Reg, tmp3Reg);
9533 
9534     movdqu(tmp2Reg, Address(src, 0));
9535     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
9536     jccb(Assembler::notZero, return_zero);
9537     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
9538     movq(Address(dst, 0), tmp2Reg);
9539     addptr(src, 16);
9540     addptr(dst, 8);
9541 
9542     bind(copy_tail);
9543     movl(len, result);
9544   }
9545   // compress 1 char per iter
9546   testl(len, len);
9547   jccb(Assembler::zero, return_length);
9548   lea(src, Address(src, len, Address::times_2));
9549   lea(dst, Address(dst, len, Address::times_1));
9550   negptr(len);
9551 
9552   bind(copy_chars_loop);
9553   load_unsigned_short(result, Address(src, len, Address::times_2));
9554   testl(result, 0xff00);      // check if Unicode char
9555   jccb(Assembler::notZero, return_zero);
9556   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
9557   increment(len);
9558   jcc(Assembler::notZero, copy_chars_loop);
9559 
9560   // if compression succeeded, return length
9561   bind(return_length);
9562   pop(result);
9563   jmpb(done);
9564 
9565   // if compression failed, return 0
9566   bind(return_zero);
9567   xorl(result, result);
9568   addptr(rsp, wordSize);
9569 
9570   bind(done);
9571 }
9572 
9573 // Inflate byte[] array to char[].
9574 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9575 //   @HotSpotIntrinsicCandidate
9576 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9577 //     for (int i = 0; i < len; i++) {
9578 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9579 //     }
9580 //   }
9581 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9582   XMMRegister tmp1, Register tmp2) {
9583   Label copy_chars_loop, done, below_threshold;
9584   // rsi: src
9585   // rdi: dst
9586   // rdx: len
9587   // rcx: tmp2
9588 
9589   // rsi holds start addr of source byte[] to be inflated
9590   // rdi holds start addr of destination char[]
9591   // rdx holds length
9592   assert_different_registers(src, dst, len, tmp2);
9593 
9594   if ((UseAVX > 2) && // AVX512
9595     VM_Version::supports_avx512vlbw() &&
9596     VM_Version::supports_bmi2()) {
9597 
9598     Label copy_32_loop, copy_tail;
9599     Register tmp3_aliased = len;
9600 
9601     // if length of the string is less than 16, handle it in an old fashioned way
9602     testl(len, -16);
9603     jcc(Assembler::zero, below_threshold);
9604 
9605     // In order to use only one arithmetic operation for the main loop we use
9606     // this pre-calculation
9607     movl(tmp2, len);
9608     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9609     andl(len, -32);     // vector count
9610     jccb(Assembler::zero, copy_tail);
9611 
9612     lea(src, Address(src, len, Address::times_1));
9613     lea(dst, Address(dst, len, Address::times_2));
9614     negptr(len);
9615 
9616 
9617     // inflate 32 chars per iter
9618     bind(copy_32_loop);
9619     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9620     evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9621     addptr(len, 32);
9622     jcc(Assembler::notZero, copy_32_loop);
9623 
9624     bind(copy_tail);
9625     // bail out when there is nothing to be done
9626     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9627     jcc(Assembler::zero, done);
9628 
9629     // ~(~0 << length), where length is the # of remaining elements to process
9630     movl(tmp3_aliased, -1);
9631     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9632     notl(tmp3_aliased);
9633     kmovdl(k2, tmp3_aliased);
9634     evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9635     evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9636 
9637     jmp(done);
9638   }
9639   if (UseSSE42Intrinsics) {
9640     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9641 
9642     movl(tmp2, len);
9643 
9644     if (UseAVX > 1) {
9645       andl(tmp2, (16 - 1));
9646       andl(len, -16);
9647       jccb(Assembler::zero, copy_new_tail);
9648     } else {
9649       andl(tmp2, 0x00000007);   // tail count (in chars)
9650       andl(len, 0xfffffff8);    // vector count (in chars)
9651       jccb(Assembler::zero, copy_tail);
9652     }
9653 
9654     // vectored inflation
9655     lea(src, Address(src, len, Address::times_1));
9656     lea(dst, Address(dst, len, Address::times_2));
9657     negptr(len);
9658 
9659     if (UseAVX > 1) {
9660       bind(copy_16_loop);
9661       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9662       vmovdqu(Address(dst, len, Address::times_2), tmp1);
9663       addptr(len, 16);
9664       jcc(Assembler::notZero, copy_16_loop);
9665 
9666       bind(below_threshold);
9667       bind(copy_new_tail);
9668       if ((UseAVX > 2) &&
9669         VM_Version::supports_avx512vlbw() &&
9670         VM_Version::supports_bmi2()) {
9671         movl(tmp2, len);
9672       } else {
9673         movl(len, tmp2);
9674       }
9675       andl(tmp2, 0x00000007);
9676       andl(len, 0xFFFFFFF8);
9677       jccb(Assembler::zero, copy_tail);
9678 
9679       pmovzxbw(tmp1, Address(src, 0));
9680       movdqu(Address(dst, 0), tmp1);
9681       addptr(src, 8);
9682       addptr(dst, 2 * 8);
9683 
9684       jmp(copy_tail, true);
9685     }
9686 
9687     // inflate 8 chars per iter
9688     bind(copy_8_loop);
9689     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
9690     movdqu(Address(dst, len, Address::times_2), tmp1);
9691     addptr(len, 8);
9692     jcc(Assembler::notZero, copy_8_loop);
9693 
9694     bind(copy_tail);
9695     movl(len, tmp2);
9696 
9697     cmpl(len, 4);
9698     jccb(Assembler::less, copy_bytes);
9699 
9700     movdl(tmp1, Address(src, 0));  // load 4 byte chars
9701     pmovzxbw(tmp1, tmp1);
9702     movq(Address(dst, 0), tmp1);
9703     subptr(len, 4);
9704     addptr(src, 4);
9705     addptr(dst, 8);
9706 
9707     bind(copy_bytes);
9708   } else {
9709     bind(below_threshold);
9710   }
9711 
9712   testl(len, len);
9713   jccb(Assembler::zero, done);
9714   lea(src, Address(src, len, Address::times_1));
9715   lea(dst, Address(dst, len, Address::times_2));
9716   negptr(len);
9717 
9718   // inflate 1 char per iter
9719   bind(copy_chars_loop);
9720   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
9721   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
9722   increment(len);
9723   jcc(Assembler::notZero, copy_chars_loop);
9724 
9725   bind(done);
9726 }
9727 
9728 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9729   switch (cond) {
9730     // Note some conditions are synonyms for others
9731     case Assembler::zero:         return Assembler::notZero;
9732     case Assembler::notZero:      return Assembler::zero;
9733     case Assembler::less:         return Assembler::greaterEqual;
9734     case Assembler::lessEqual:    return Assembler::greater;
9735     case Assembler::greater:      return Assembler::lessEqual;
9736     case Assembler::greaterEqual: return Assembler::less;
9737     case Assembler::below:        return Assembler::aboveEqual;
9738     case Assembler::belowEqual:   return Assembler::above;
9739     case Assembler::above:        return Assembler::belowEqual;
9740     case Assembler::aboveEqual:   return Assembler::below;
9741     case Assembler::overflow:     return Assembler::noOverflow;
9742     case Assembler::noOverflow:   return Assembler::overflow;
9743     case Assembler::negative:     return Assembler::positive;
9744     case Assembler::positive:     return Assembler::negative;
9745     case Assembler::parity:       return Assembler::noParity;
9746     case Assembler::noParity:     return Assembler::parity;
9747   }
9748   ShouldNotReachHere(); return Assembler::overflow;
9749 }
9750 
9751 SkipIfEqual::SkipIfEqual(
9752     MacroAssembler* masm, const bool* flag_addr, bool value) {
9753   _masm = masm;
9754   _masm->cmp8(ExternalAddress((address)flag_addr), value);
9755   _masm->jcc(Assembler::equal, _label);
9756 }
9757 
9758 SkipIfEqual::~SkipIfEqual() {
9759   _masm->bind(_label);
9760 }
9761 
9762 // 32-bit Windows has its own fast-path implementation
9763 // of get_thread
9764 #if !defined(WIN32) || defined(_LP64)
9765 
9766 // This is simply a call to Thread::current()
9767 void MacroAssembler::get_thread(Register thread) {
9768   if (thread != rax) {
9769     push(rax);
9770   }
9771   LP64_ONLY(push(rdi);)
9772   LP64_ONLY(push(rsi);)
9773   push(rdx);
9774   push(rcx);
9775 #ifdef _LP64
9776   push(r8);
9777   push(r9);
9778   push(r10);
9779   push(r11);
9780 #endif
9781 
9782   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9783 
9784 #ifdef _LP64
9785   pop(r11);
9786   pop(r10);
9787   pop(r9);
9788   pop(r8);
9789 #endif
9790   pop(rcx);
9791   pop(rdx);
9792   LP64_ONLY(pop(rsi);)
9793   LP64_ONLY(pop(rdi);)
9794   if (thread != rax) {
9795     mov(thread, rax);
9796     pop(rax);
9797   }
9798 }
9799 
9800 #endif