1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  23  */
  24 
  25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  public:
  42   // Support for VM calls
  43   //
  44   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  45   // may customize this version by overriding it for its purposes (e.g., to save/restore
  46   // additional registers when doing a VM call).
  47 
  48   virtual void call_VM_leaf_base(
  49     address entry_point,               // the entry point
  50     int     number_of_arguments        // the number of arguments to pop after the call
  51   );
  52 
  53  protected:
  54   // This is the base routine called by the different versions of call_VM. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   //
  58   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  59   // returns the register which contains the thread upon return. If a thread register has been
  60   // specified, the return value will correspond to that register. If no last_java_sp is specified
  61   // (noreg) than rsp will be used instead.
  62   virtual void call_VM_base(           // returns the register containing the thread upon return
  63     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  64     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  65     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  66     address  entry_point,              // the entry point
  67     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  68     bool     check_exceptions          // whether to check for pending exceptions after return
  69   );
  70 
  71   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  72 
  73   // helpers for FPU flag access
  74   // tmp is a temporary register, if none is available use noreg
  75   void save_rax   (Register tmp);
  76   void restore_rax(Register tmp);
  77 
  78  public:
  79   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  80 
  81  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82  // The implementation is only non-empty for the InterpreterMacroAssembler,
  83  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84  virtual void check_and_handle_popframe(Register java_thread);
  85  virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   Address as_Address(AddressLiteral adr);
  88   Address as_Address(ArrayAddress adr);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99   static bool uses_implicit_null_check(void* address);
 100 
 101   // Required platform-specific helpers for Label::patch_instructions.
 102   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 103   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 104     unsigned char op = branch[0];
 105     assert(op == 0xE8 /* call */ ||
 106         op == 0xE9 /* jmp */ ||
 107         op == 0xEB /* short jmp */ ||
 108         (op & 0xF0) == 0x70 /* short jcc */ ||
 109         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 110         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 111         "Invalid opcode at patch point");
 112 
 113     if (op == 0xEB || (op & 0xF0) == 0x70) {
 114       // short offset operators (jmp and jcc)
 115       char* disp = (char*) &branch[1];
 116       int imm8 = target - (address) &disp[1];
 117       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
 118       *disp = imm8;
 119     } else {
 120       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 121       int imm32 = target - (address) &disp[1];
 122       *disp = imm32;
 123     }
 124   }
 125 
 126   // The following 4 methods return the offset of the appropriate move instruction
 127 
 128   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 129   int load_unsigned_byte(Register dst, Address src);
 130   int load_unsigned_short(Register dst, Address src);
 131 
 132   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 133   int load_signed_byte(Register dst, Address src);
 134   int load_signed_short(Register dst, Address src);
 135 
 136   // Support for sign-extension (hi:lo = extend_sign(lo))
 137   void extend_sign(Register hi, Register lo);
 138 
 139   // Load and store values by size and signed-ness
 140   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 141   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 142 
 143   // Support for inc/dec with optimal instruction selection depending on value
 144 
 145   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 146   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 147 
 148   void decrementl(Address dst, int value = 1);
 149   void decrementl(Register reg, int value = 1);
 150 
 151   void decrementq(Register reg, int value = 1);
 152   void decrementq(Address dst, int value = 1);
 153 
 154   void incrementl(Address dst, int value = 1);
 155   void incrementl(Register reg, int value = 1);
 156 
 157   void incrementq(Register reg, int value = 1);
 158   void incrementq(Address dst, int value = 1);
 159 
 160 #ifdef COMPILER2
 161   // special instructions for EVEX
 162   void setvectmask(Register dst, Register src);
 163   void restorevectmask();
 164 #endif
 165 
 166   // Support optimal SSE move instructions.
 167   void movflt(XMMRegister dst, XMMRegister src) {
 168     if (dst-> encoding() == src->encoding()) return;
 169     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 170     else                       { movss (dst, src); return; }
 171   }
 172   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 173   void movflt(XMMRegister dst, AddressLiteral src);
 174   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 175 
 176   void movdbl(XMMRegister dst, XMMRegister src) {
 177     if (dst-> encoding() == src->encoding()) return;
 178     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 179     else                       { movsd (dst, src); return; }
 180   }
 181 
 182   void movdbl(XMMRegister dst, AddressLiteral src);
 183 
 184   void movdbl(XMMRegister dst, Address src) {
 185     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 186     else                         { movlpd(dst, src); return; }
 187   }
 188   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 189 
 190   void incrementl(AddressLiteral dst);
 191   void incrementl(ArrayAddress dst);
 192 
 193   void incrementq(AddressLiteral dst);
 194 
 195   // Alignment
 196   void align(int modulus);
 197   void align(int modulus, int target);
 198 
 199   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 200   void fat_nop();
 201 
 202   // Stack frame creation/removal
 203   void enter();
 204   void leave();
 205 
 206   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 207   // The pointer will be loaded into the thread register.
 208   void get_thread(Register thread);
 209 
 210 
 211   // Support for VM calls
 212   //
 213   // It is imperative that all calls into the VM are handled via the call_VM macros.
 214   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 215   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 216 
 217 
 218   void call_VM(Register oop_result,
 219                address entry_point,
 220                bool check_exceptions = true);
 221   void call_VM(Register oop_result,
 222                address entry_point,
 223                Register arg_1,
 224                bool check_exceptions = true);
 225   void call_VM(Register oop_result,
 226                address entry_point,
 227                Register arg_1, Register arg_2,
 228                bool check_exceptions = true);
 229   void call_VM(Register oop_result,
 230                address entry_point,
 231                Register arg_1, Register arg_2, Register arg_3,
 232                bool check_exceptions = true);
 233 
 234   // Overloadings with last_Java_sp
 235   void call_VM(Register oop_result,
 236                Register last_java_sp,
 237                address entry_point,
 238                int number_of_arguments = 0,
 239                bool check_exceptions = true);
 240   void call_VM(Register oop_result,
 241                Register last_java_sp,
 242                address entry_point,
 243                Register arg_1, bool
 244                check_exceptions = true);
 245   void call_VM(Register oop_result,
 246                Register last_java_sp,
 247                address entry_point,
 248                Register arg_1, Register arg_2,
 249                bool check_exceptions = true);
 250   void call_VM(Register oop_result,
 251                Register last_java_sp,
 252                address entry_point,
 253                Register arg_1, Register arg_2, Register arg_3,
 254                bool check_exceptions = true);
 255 
 256   void get_vm_result  (Register oop_result, Register thread);
 257   void get_vm_result_2(Register metadata_result, Register thread);
 258 
 259   // These always tightly bind to MacroAssembler::call_VM_base
 260   // bypassing the virtual implementation
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 263   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 264   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 265   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 266 
 267   void call_VM_leaf0(address entry_point);
 268   void call_VM_leaf(address entry_point,
 269                     int number_of_arguments = 0);
 270   void call_VM_leaf(address entry_point,
 271                     Register arg_1);
 272   void call_VM_leaf(address entry_point,
 273                     Register arg_1, Register arg_2);
 274   void call_VM_leaf(address entry_point,
 275                     Register arg_1, Register arg_2, Register arg_3);
 276 
 277   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 278   // bypassing the virtual implementation
 279   void super_call_VM_leaf(address entry_point);
 280   void super_call_VM_leaf(address entry_point, Register arg_1);
 281   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 282   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 283   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 284 
 285   // last Java Frame (fills frame anchor)
 286   void set_last_Java_frame(Register thread,
 287                            Register last_java_sp,
 288                            Register last_java_fp,
 289                            address last_java_pc);
 290 
 291   // thread in the default location (r15_thread on 64bit)
 292   void set_last_Java_frame(Register last_java_sp,
 293                            Register last_java_fp,
 294                            address last_java_pc);
 295 
 296   void reset_last_Java_frame(Register thread, bool clear_fp);
 297 
 298   // thread in the default location (r15_thread on 64bit)
 299   void reset_last_Java_frame(bool clear_fp);
 300 
 301   // jobjects
 302   void clear_jweak_tag(Register possibly_jweak);
 303   void resolve_jobject(Register value, Register thread, Register tmp);
 304 
 305   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 306   void c2bool(Register x);
 307 
 308   // C++ bool manipulation
 309 
 310   void movbool(Register dst, Address src);
 311   void movbool(Address dst, bool boolconst);
 312   void movbool(Address dst, Register src);
 313   void testbool(Register dst);
 314 
 315   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 316   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 317 
 318   void load_method_holder(Register holder, Register method);
 319 
 320   // oop manipulations
 321   void load_klass(Register dst, Register src);
 322   void store_klass(Register dst, Register src);
 323 
 324   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 325                       Register tmp1, Register thread_tmp);
 326   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 327                        Register tmp1, Register tmp2);
 328 
 329   // Resolves obj access. Result is placed in the same register.
 330   // All other registers are preserved.
 331   void resolve(DecoratorSet decorators, Register obj);
 332 
 333   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 334                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 335   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 336                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 337   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 338                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 339 
 340   // Used for storing NULL. All other oop constants should be
 341   // stored using routines that take a jobject.
 342   void store_heap_oop_null(Address dst);
 343 
 344   void load_prototype_header(Register dst, Register src);
 345 
 346 #ifdef _LP64
 347   void store_klass_gap(Register dst, Register src);
 348 
 349   // This dummy is to prevent a call to store_heap_oop from
 350   // converting a zero (like NULL) into a Register by giving
 351   // the compiler two choices it can't resolve
 352 
 353   void store_heap_oop(Address dst, void* dummy);
 354 
 355   void encode_heap_oop(Register r);
 356   void decode_heap_oop(Register r);
 357   void encode_heap_oop_not_null(Register r);
 358   void decode_heap_oop_not_null(Register r);
 359   void encode_heap_oop_not_null(Register dst, Register src);
 360   void decode_heap_oop_not_null(Register dst, Register src);
 361 
 362   void set_narrow_oop(Register dst, jobject obj);
 363   void set_narrow_oop(Address dst, jobject obj);
 364   void cmp_narrow_oop(Register dst, jobject obj);
 365   void cmp_narrow_oop(Address dst, jobject obj);
 366 
 367   void encode_klass_not_null(Register r);
 368   void decode_klass_not_null(Register r);
 369   void encode_klass_not_null(Register dst, Register src);
 370   void decode_klass_not_null(Register dst, Register src);
 371   void set_narrow_klass(Register dst, Klass* k);
 372   void set_narrow_klass(Address dst, Klass* k);
 373   void cmp_narrow_klass(Register dst, Klass* k);
 374   void cmp_narrow_klass(Address dst, Klass* k);
 375 
 376   // Returns the byte size of the instructions generated by decode_klass_not_null()
 377   // when compressed klass pointers are being used.
 378   static int instr_size_for_decode_klass_not_null();
 379 
 380   // if heap base register is used - reinit it with the correct value
 381   void reinit_heapbase();
 382 
 383   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 384 
 385 #endif // _LP64
 386 
 387   // Int division/remainder for Java
 388   // (as idivl, but checks for special case as described in JVM spec.)
 389   // returns idivl instruction offset for implicit exception handling
 390   int corrected_idivl(Register reg);
 391 
 392   // Long division/remainder for Java
 393   // (as idivq, but checks for special case as described in JVM spec.)
 394   // returns idivq instruction offset for implicit exception handling
 395   int corrected_idivq(Register reg);
 396 
 397   void int3();
 398 
 399   // Long operation macros for a 32bit cpu
 400   // Long negation for Java
 401   void lneg(Register hi, Register lo);
 402 
 403   // Long multiplication for Java
 404   // (destroys contents of eax, ebx, ecx and edx)
 405   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 406 
 407   // Long shifts for Java
 408   // (semantics as described in JVM spec.)
 409   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 410   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 411 
 412   // Long compare for Java
 413   // (semantics as described in JVM spec.)
 414   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 415 
 416 
 417   // misc
 418 
 419   // Sign extension
 420   void sign_extend_short(Register reg);
 421   void sign_extend_byte(Register reg);
 422 
 423   // Division by power of 2, rounding towards 0
 424   void division_with_shift(Register reg, int shift_value);
 425 
 426   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 427   //
 428   // CF (corresponds to C0) if x < y
 429   // PF (corresponds to C2) if unordered
 430   // ZF (corresponds to C3) if x = y
 431   //
 432   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 433   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 434   void fcmp(Register tmp);
 435   // Variant of the above which allows y to be further down the stack
 436   // and which only pops x and y if specified. If pop_right is
 437   // specified then pop_left must also be specified.
 438   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 439 
 440   // Floating-point comparison for Java
 441   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 442   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 443   // (semantics as described in JVM spec.)
 444   void fcmp2int(Register dst, bool unordered_is_less);
 445   // Variant of the above which allows y to be further down the stack
 446   // and which only pops x and y if specified. If pop_right is
 447   // specified then pop_left must also be specified.
 448   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 449 
 450   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 451   // tmp is a temporary register, if none is available use noreg
 452   void fremr(Register tmp);
 453 
 454   // dst = c = a * b + c
 455   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 456   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 457 
 458   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 459   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 460   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 461   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 462 
 463 
 464   // same as fcmp2int, but using SSE2
 465   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 466   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 467 
 468   // branch to L if FPU flag C2 is set/not set
 469   // tmp is a temporary register, if none is available use noreg
 470   void jC2 (Register tmp, Label& L);
 471   void jnC2(Register tmp, Label& L);
 472 
 473   // Pop ST (ffree & fincstp combined)
 474   void fpop();
 475 
 476   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 477   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 478   void load_float(Address src);
 479 
 480   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 481   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 482   void store_float(Address dst);
 483 
 484   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 485   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 486   void load_double(Address src);
 487 
 488   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 489   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 490   void store_double(Address dst);
 491 
 492   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 493   void push_fTOS();
 494 
 495   // pops double TOS element from CPU stack and pushes on FPU stack
 496   void pop_fTOS();
 497 
 498   void empty_FPU_stack();
 499 
 500   void push_IU_state();
 501   void pop_IU_state();
 502 
 503   void push_FPU_state();
 504   void pop_FPU_state();
 505 
 506   void push_CPU_state();
 507   void pop_CPU_state();
 508 
 509   // Round up to a power of two
 510   void round_to(Register reg, int modulus);
 511 
 512   // Callee saved registers handling
 513   void push_callee_saved_registers();
 514   void pop_callee_saved_registers();
 515 
 516   // allocation
 517   void eden_allocate(
 518     Register thread,                   // Current thread
 519     Register obj,                      // result: pointer to object after successful allocation
 520     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 521     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 522     Register t1,                       // temp register
 523     Label&   slow_case                 // continuation point if fast allocation fails
 524   );
 525   void tlab_allocate(
 526     Register thread,                   // Current thread
 527     Register obj,                      // result: pointer to object after successful allocation
 528     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 529     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 530     Register t1,                       // temp register
 531     Register t2,                       // temp register
 532     Label&   slow_case                 // continuation point if fast allocation fails
 533   );
 534   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 535 
 536   // interface method calling
 537   void lookup_interface_method(Register recv_klass,
 538                                Register intf_klass,
 539                                RegisterOrConstant itable_index,
 540                                Register method_result,
 541                                Register scan_temp,
 542                                Label& no_such_interface,
 543                                bool return_method = true);
 544 
 545   // virtual method calling
 546   void lookup_virtual_method(Register recv_klass,
 547                              RegisterOrConstant vtable_index,
 548                              Register method_result);
 549 
 550   // Test sub_klass against super_klass, with fast and slow paths.
 551 
 552   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 553   // One of the three labels can be NULL, meaning take the fall-through.
 554   // If super_check_offset is -1, the value is loaded up from super_klass.
 555   // No registers are killed, except temp_reg.
 556   void check_klass_subtype_fast_path(Register sub_klass,
 557                                      Register super_klass,
 558                                      Register temp_reg,
 559                                      Label* L_success,
 560                                      Label* L_failure,
 561                                      Label* L_slow_path,
 562                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 563 
 564   // The rest of the type check; must be wired to a corresponding fast path.
 565   // It does not repeat the fast path logic, so don't use it standalone.
 566   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 567   // Updates the sub's secondary super cache as necessary.
 568   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 569   void check_klass_subtype_slow_path(Register sub_klass,
 570                                      Register super_klass,
 571                                      Register temp_reg,
 572                                      Register temp2_reg,
 573                                      Label* L_success,
 574                                      Label* L_failure,
 575                                      bool set_cond_codes = false);
 576 
 577   // Simplified, combined version, good for typical uses.
 578   // Falls through on failure.
 579   void check_klass_subtype(Register sub_klass,
 580                            Register super_klass,
 581                            Register temp_reg,
 582                            Label& L_success);
 583 
 584   void clinit_barrier(Register klass,
 585                       Register thread,
 586                       Label* L_fast_path = NULL,
 587                       Label* L_slow_path = NULL);
 588 
 589   // method handles (JSR 292)
 590   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 591 
 592   //----
 593   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 594 
 595   // Debugging
 596 
 597   // only if +VerifyOops
 598   // TODO: Make these macros with file and line like sparc version!
 599   void verify_oop(Register reg, const char* s = "broken oop");
 600   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 601 
 602   // TODO: verify method and klass metadata (compare against vptr?)
 603   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 604   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 605 
 606 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 607 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 608 
 609   // only if +VerifyFPU
 610   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 611 
 612   // Verify or restore cpu control state after JNI call
 613   void restore_cpu_control_state_after_jni();
 614 
 615   // prints msg, dumps registers and stops execution
 616   void stop(const char* msg);
 617 
 618   // prints msg and continues
 619   void warn(const char* msg);
 620 
 621   // dumps registers and other state
 622   void print_state();
 623 
 624   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 625   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 626   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 627   static void print_state64(int64_t pc, int64_t regs[]);
 628 
 629   void os_breakpoint();
 630 
 631   void untested()                                { stop("untested"); }
 632 
 633   void unimplemented(const char* what = "");
 634 
 635   void should_not_reach_here()                   { stop("should not reach here"); }
 636 
 637   void print_CPU_state();
 638 
 639   // Stack overflow checking
 640   void bang_stack_with_offset(int offset) {
 641     // stack grows down, caller passes positive offset
 642     assert(offset > 0, "must bang with negative offset");
 643     movl(Address(rsp, (-offset)), rax);
 644   }
 645 
 646   // Writes to stack successive pages until offset reached to check for
 647   // stack overflow + shadow pages.  Also, clobbers tmp
 648   void bang_stack_size(Register size, Register tmp);
 649 
 650   // Check for reserved stack access in method being exited (for JIT)
 651   void reserved_stack_check();
 652 
 653   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 654                                                 Register tmp,
 655                                                 int offset);
 656 
 657   // If thread_reg is != noreg the code assumes the register passed contains
 658   // the thread (required on 64 bit).
 659   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 660 
 661   void verify_tlab();
 662 
 663   // Biased locking support
 664   // lock_reg and obj_reg must be loaded up with the appropriate values.
 665   // swap_reg must be rax, and is killed.
 666   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 667   // be killed; if not supplied, push/pop will be used internally to
 668   // allocate a temporary (inefficient, avoid if possible).
 669   // Optional slow case is for implementations (interpreter and C1) which branch to
 670   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 671   // Returns offset of first potentially-faulting instruction for null
 672   // check info (currently consumed only by C1). If
 673   // swap_reg_contains_mark is true then returns -1 as it is assumed
 674   // the calling code has already passed any potential faults.
 675   int biased_locking_enter(Register lock_reg, Register obj_reg,
 676                            Register swap_reg, Register tmp_reg,
 677                            bool swap_reg_contains_mark,
 678                            Label& done, Label* slow_case = NULL,
 679                            BiasedLockingCounters* counters = NULL);
 680   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 681 #ifdef COMPILER2
 682   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 683   // See full desription in macroAssembler_x86.cpp.
 684   void fast_lock(Register obj, Register box, Register tmp,
 685                  Register scr, Register cx1, Register cx2,
 686                  BiasedLockingCounters* counters,
 687                  RTMLockingCounters* rtm_counters,
 688                  RTMLockingCounters* stack_rtm_counters,
 689                  Metadata* method_data,
 690                  bool use_rtm, bool profile_rtm);
 691   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 692 #if INCLUDE_RTM_OPT
 693   void rtm_counters_update(Register abort_status, Register rtm_counters);
 694   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 695   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 696                                    RTMLockingCounters* rtm_counters,
 697                                    Metadata* method_data);
 698   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 699                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 700   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 701   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 702   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 703                          Register retry_on_abort_count,
 704                          RTMLockingCounters* stack_rtm_counters,
 705                          Metadata* method_data, bool profile_rtm,
 706                          Label& DONE_LABEL, Label& IsInflated);
 707   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 708                             Register scr, Register retry_on_busy_count,
 709                             Register retry_on_abort_count,
 710                             RTMLockingCounters* rtm_counters,
 711                             Metadata* method_data, bool profile_rtm,
 712                             Label& DONE_LABEL);
 713 #endif
 714 #endif
 715 
 716   Condition negate_condition(Condition cond);
 717 
 718   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 719   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 720   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 721   // here in MacroAssembler. The major exception to this rule is call
 722 
 723   // Arithmetics
 724 
 725 
 726   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 727   void addptr(Address dst, Register src);
 728 
 729   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 730   void addptr(Register dst, int32_t src);
 731   void addptr(Register dst, Register src);
 732   void addptr(Register dst, RegisterOrConstant src) {
 733     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 734     else                   addptr(dst,       src.as_register());
 735   }
 736 
 737   void andptr(Register dst, int32_t src);
 738   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 739 
 740   void cmp8(AddressLiteral src1, int imm);
 741 
 742   // renamed to drag out the casting of address to int32_t/intptr_t
 743   void cmp32(Register src1, int32_t imm);
 744 
 745   void cmp32(AddressLiteral src1, int32_t imm);
 746   // compare reg - mem, or reg - &mem
 747   void cmp32(Register src1, AddressLiteral src2);
 748 
 749   void cmp32(Register src1, Address src2);
 750 
 751 #ifndef _LP64
 752   void cmpklass(Address dst, Metadata* obj);
 753   void cmpklass(Register dst, Metadata* obj);
 754   void cmpoop(Address dst, jobject obj);
 755   void cmpoop_raw(Address dst, jobject obj);
 756 #endif // _LP64
 757 
 758   void cmpoop(Register src1, Register src2);
 759   void cmpoop(Register src1, Address src2);
 760   void cmpoop(Register dst, jobject obj);
 761   void cmpoop_raw(Register dst, jobject obj);
 762 
 763   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 764   void cmpptr(Address src1, AddressLiteral src2);
 765 
 766   void cmpptr(Register src1, AddressLiteral src2);
 767 
 768   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 769   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 770   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 771 
 772   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 773   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 774 
 775   // cmp64 to avoild hiding cmpq
 776   void cmp64(Register src1, AddressLiteral src);
 777 
 778   void cmpxchgptr(Register reg, Address adr);
 779 
 780   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 781 
 782 
 783   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 784   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 785 
 786 
 787   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 788 
 789   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 790 
 791   void shlptr(Register dst, int32_t shift);
 792   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 793 
 794   void shrptr(Register dst, int32_t shift);
 795   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 796 
 797   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 798   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 799 
 800   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 801 
 802   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 803   void subptr(Register dst, int32_t src);
 804   // Force generation of a 4 byte immediate value even if it fits into 8bit
 805   void subptr_imm32(Register dst, int32_t src);
 806   void subptr(Register dst, Register src);
 807   void subptr(Register dst, RegisterOrConstant src) {
 808     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 809     else                   subptr(dst,       src.as_register());
 810   }
 811 
 812   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 813   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 814 
 815   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 816   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 817 
 818   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 819 
 820 
 821 
 822   // Helper functions for statistics gathering.
 823   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 824   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 825   // Unconditional atomic increment.
 826   void atomic_incl(Address counter_addr);
 827   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 828 #ifdef _LP64
 829   void atomic_incq(Address counter_addr);
 830   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 831 #endif
 832   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 833   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 834 
 835   void lea(Register dst, AddressLiteral adr);
 836   void lea(Address dst, AddressLiteral adr);
 837   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 838 
 839   void leal32(Register dst, Address src) { leal(dst, src); }
 840 
 841   // Import other testl() methods from the parent class or else
 842   // they will be hidden by the following overriding declaration.
 843   using Assembler::testl;
 844   void testl(Register dst, AddressLiteral src);
 845 
 846   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 847   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 848   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 849   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 850 
 851   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 852   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 853   void testptr(Register src1, Register src2);
 854 
 855   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 856   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 857 
 858   // Calls
 859 
 860   void call(Label& L, relocInfo::relocType rtype);
 861   void call(Register entry);
 862 
 863   // NOTE: this call transfers to the effective address of entry NOT
 864   // the address contained by entry. This is because this is more natural
 865   // for jumps/calls.
 866   void call(AddressLiteral entry);
 867 
 868   // Emit the CompiledIC call idiom
 869   void ic_call(address entry, jint method_index = 0);
 870 
 871   // Jumps
 872 
 873   // NOTE: these jumps tranfer to the effective address of dst NOT
 874   // the address contained by dst. This is because this is more natural
 875   // for jumps/calls.
 876   void jump(AddressLiteral dst);
 877   void jump_cc(Condition cc, AddressLiteral dst);
 878 
 879   // 32bit can do a case table jump in one instruction but we no longer allow the base
 880   // to be installed in the Address class. This jump will tranfers to the address
 881   // contained in the location described by entry (not the address of entry)
 882   void jump(ArrayAddress entry);
 883 
 884   // Floating
 885 
 886   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 887   void andpd(XMMRegister dst, AddressLiteral src);
 888   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 889 
 890   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 891   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 892   void andps(XMMRegister dst, AddressLiteral src);
 893 
 894   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 895   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 896   void comiss(XMMRegister dst, AddressLiteral src);
 897 
 898   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 899   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 900   void comisd(XMMRegister dst, AddressLiteral src);
 901 
 902   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 903   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 904 
 905   void fldcw(Address src) { Assembler::fldcw(src); }
 906   void fldcw(AddressLiteral src);
 907 
 908   void fld_s(int index)   { Assembler::fld_s(index); }
 909   void fld_s(Address src) { Assembler::fld_s(src); }
 910   void fld_s(AddressLiteral src);
 911 
 912   void fld_d(Address src) { Assembler::fld_d(src); }
 913   void fld_d(AddressLiteral src);
 914 
 915   void fld_x(Address src) { Assembler::fld_x(src); }
 916   void fld_x(AddressLiteral src);
 917 
 918   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 919   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 920 
 921   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 922   void ldmxcsr(AddressLiteral src);
 923 
 924 #ifdef _LP64
 925  private:
 926   void sha256_AVX2_one_round_compute(
 927     Register  reg_old_h,
 928     Register  reg_a,
 929     Register  reg_b,
 930     Register  reg_c,
 931     Register  reg_d,
 932     Register  reg_e,
 933     Register  reg_f,
 934     Register  reg_g,
 935     Register  reg_h,
 936     int iter);
 937   void sha256_AVX2_four_rounds_compute_first(int start);
 938   void sha256_AVX2_four_rounds_compute_last(int start);
 939   void sha256_AVX2_one_round_and_sched(
 940         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 941         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 942         XMMRegister xmm_2,     /* ymm6 */
 943         XMMRegister xmm_3,     /* ymm7 */
 944         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 945         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 946         Register    reg_c,      /* edi */
 947         Register    reg_d,      /* esi */
 948         Register    reg_e,      /* r8d */
 949         Register    reg_f,      /* r9d */
 950         Register    reg_g,      /* r10d */
 951         Register    reg_h,      /* r11d */
 952         int iter);
 953 
 954   void addm(int disp, Register r1, Register r2);
 955   void gfmul(XMMRegister tmp0, XMMRegister t);
 956   void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
 957                      XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
 958   void generateHtbl_one_block(Register htbl);
 959   void generateHtbl_eight_blocks(Register htbl);
 960  public:
 961   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 962                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 963                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 964                    bool multi_block, XMMRegister shuf_mask);
 965   void avx_ghash(Register state, Register htbl, Register data, Register blocks);
 966 #endif
 967 
 968 #ifdef _LP64
 969  private:
 970   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 971                                      Register e, Register f, Register g, Register h, int iteration);
 972 
 973   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 974                                           Register a, Register b, Register c, Register d, Register e, Register f,
 975                                           Register g, Register h, int iteration);
 976 
 977   void addmq(int disp, Register r1, Register r2);
 978  public:
 979   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 980                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 981                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 982                    XMMRegister shuf_mask);
 983 #endif
 984 
 985   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 986                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 987                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 988                  bool multi_block);
 989 
 990 #ifdef _LP64
 991   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 992                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 993                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 994                    bool multi_block, XMMRegister shuf_mask);
 995 #else
 996   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 997                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 998                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 999                    bool multi_block);
1000 #endif
1001 
1002   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1003                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1004                 Register rax, Register rcx, Register rdx, Register tmp);
1005 
1006 #ifdef _LP64
1007   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1008                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1009                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1010 
1011   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1012                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1013                   Register rax, Register rcx, Register rdx, Register r11);
1014 
1015   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1016                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1017                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1018 
1019   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1022                 Register tmp3, Register tmp4);
1023 
1024   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1025                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1026                 Register rax, Register rcx, Register rdx, Register tmp1,
1027                 Register tmp2, Register tmp3, Register tmp4);
1028   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1029                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1030                 Register rax, Register rcx, Register rdx, Register tmp1,
1031                 Register tmp2, Register tmp3, Register tmp4);
1032 #else
1033   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1034                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1035                 Register rax, Register rcx, Register rdx, Register tmp1);
1036 
1037   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1038                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1039                 Register rax, Register rcx, Register rdx, Register tmp);
1040 
1041   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1042                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1043                 Register rdx, Register tmp);
1044 
1045   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1046                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1047                 Register rax, Register rbx, Register rdx);
1048 
1049   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1050                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1051                 Register rax, Register rcx, Register rdx, Register tmp);
1052 
1053   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1054                         Register edx, Register ebx, Register esi, Register edi,
1055                         Register ebp, Register esp);
1056 
1057   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1058                          Register esi, Register edi, Register ebp, Register esp);
1059 
1060   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1061                         Register edx, Register ebx, Register esi, Register edi,
1062                         Register ebp, Register esp);
1063 
1064   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1065                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1066                 Register rax, Register rcx, Register rdx, Register tmp);
1067 #endif
1068 
1069   void increase_precision();
1070   void restore_precision();
1071 
1072 private:
1073 
1074   // these are private because users should be doing movflt/movdbl
1075 
1076   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1077   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1078   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1079   void movss(XMMRegister dst, AddressLiteral src);
1080 
1081   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1082   void movlpd(XMMRegister dst, AddressLiteral src);
1083 
1084 public:
1085 
1086   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1087   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1088   void addsd(XMMRegister dst, AddressLiteral src);
1089 
1090   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1091   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1092   void addss(XMMRegister dst, AddressLiteral src);
1093 
1094   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1095   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1096   void addpd(XMMRegister dst, AddressLiteral src);
1097 
1098   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1099   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1100   void divsd(XMMRegister dst, AddressLiteral src);
1101 
1102   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1103   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1104   void divss(XMMRegister dst, AddressLiteral src);
1105 
1106   // Move Unaligned Double Quadword
1107   void movdqu(Address     dst, XMMRegister src);
1108   void movdqu(XMMRegister dst, Address src);
1109   void movdqu(XMMRegister dst, XMMRegister src);
1110   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1111   // AVX Unaligned forms
1112   void vmovdqu(Address     dst, XMMRegister src);
1113   void vmovdqu(XMMRegister dst, Address src);
1114   void vmovdqu(XMMRegister dst, XMMRegister src);
1115   void vmovdqu(XMMRegister dst, AddressLiteral src);
1116   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1117   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1118   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1119   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1120 
1121   // Move Aligned Double Quadword
1122   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1123   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1124   void movdqa(XMMRegister dst, AddressLiteral src);
1125 
1126   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1127   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1128   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1129   void movsd(XMMRegister dst, AddressLiteral src);
1130 
1131   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1132   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1133   void mulpd(XMMRegister dst, AddressLiteral src);
1134 
1135   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1136   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1137   void mulsd(XMMRegister dst, AddressLiteral src);
1138 
1139   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1140   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1141   void mulss(XMMRegister dst, AddressLiteral src);
1142 
1143   // Carry-Less Multiplication Quadword
1144   void pclmulldq(XMMRegister dst, XMMRegister src) {
1145     // 0x00 - multiply lower 64 bits [0:63]
1146     Assembler::pclmulqdq(dst, src, 0x00);
1147   }
1148   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1149     // 0x11 - multiply upper 64 bits [64:127]
1150     Assembler::pclmulqdq(dst, src, 0x11);
1151   }
1152 
1153   void pcmpeqb(XMMRegister dst, XMMRegister src);
1154   void pcmpeqw(XMMRegister dst, XMMRegister src);
1155 
1156   void pcmpestri(XMMRegister dst, Address src, int imm8);
1157   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1158 
1159   void pmovzxbw(XMMRegister dst, XMMRegister src);
1160   void pmovzxbw(XMMRegister dst, Address src);
1161 
1162   void pmovmskb(Register dst, XMMRegister src);
1163 
1164   void ptest(XMMRegister dst, XMMRegister src);
1165 
1166   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1167   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1168   void sqrtsd(XMMRegister dst, AddressLiteral src);
1169 
1170   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1171   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1172   void sqrtss(XMMRegister dst, AddressLiteral src);
1173 
1174   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1175   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1176   void subsd(XMMRegister dst, AddressLiteral src);
1177 
1178   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1179   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1180   void subss(XMMRegister dst, AddressLiteral src);
1181 
1182   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1183   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1184   void ucomiss(XMMRegister dst, AddressLiteral src);
1185 
1186   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1187   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1188   void ucomisd(XMMRegister dst, AddressLiteral src);
1189 
1190   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1191   void xorpd(XMMRegister dst, XMMRegister src);
1192   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1193   void xorpd(XMMRegister dst, AddressLiteral src);
1194 
1195   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1196   void xorps(XMMRegister dst, XMMRegister src);
1197   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1198   void xorps(XMMRegister dst, AddressLiteral src);
1199 
1200   // Shuffle Bytes
1201   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1202   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1203   void pshufb(XMMRegister dst, AddressLiteral src);
1204   // AVX 3-operands instructions
1205 
1206   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1207   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1208   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1209 
1210   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1211   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1212   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1213 
1214   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1215   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1216 
1217   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1218   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1219 
1220   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1221   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1222 
1223   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1224   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1225   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1226 
1227   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1228   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1229 
1230   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1231 
1232   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1233 
1234   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1235   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1236 
1237   void vpmovmskb(Register dst, XMMRegister src);
1238 
1239   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1240   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1241 
1242   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1243   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1244 
1245   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1246   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1247 
1248   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1249   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1250 
1251   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1252   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1253 
1254   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1255   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1256 
1257   void vptest(XMMRegister dst, XMMRegister src);
1258 
1259   void punpcklbw(XMMRegister dst, XMMRegister src);
1260   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1261 
1262   void pshufd(XMMRegister dst, Address src, int mode);
1263   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1264 
1265   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1266   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1267 
1268   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1269   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1270   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1271 
1272   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1273   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1274   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1275 
1276   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1277   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1278   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1279 
1280   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1281   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1282   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1283 
1284   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1285   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1286   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1287 
1288   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1289   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1290   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1291 
1292   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1293   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1294   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1295 
1296   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1297   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1298   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1299 
1300   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1301   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1302 
1303   // AVX Vector instructions
1304 
1305   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1306   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1307   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1308 
1309   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1310   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1311   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1312 
1313   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1314     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1315       Assembler::vpxor(dst, nds, src, vector_len);
1316     else
1317       Assembler::vxorpd(dst, nds, src, vector_len);
1318   }
1319   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1320     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1321       Assembler::vpxor(dst, nds, src, vector_len);
1322     else
1323       Assembler::vxorpd(dst, nds, src, vector_len);
1324   }
1325 
1326   // Simple version for AVX2 256bit vectors
1327   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1328   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1329 
1330   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1331     if (UseAVX > 2) {
1332       Assembler::vinserti32x4(dst, dst, src, imm8);
1333     } else if (UseAVX > 1) {
1334       // vinserti128 is available only in AVX2
1335       Assembler::vinserti128(dst, nds, src, imm8);
1336     } else {
1337       Assembler::vinsertf128(dst, nds, src, imm8);
1338     }
1339   }
1340 
1341   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1342     if (UseAVX > 2) {
1343       Assembler::vinserti32x4(dst, dst, src, imm8);
1344     } else if (UseAVX > 1) {
1345       // vinserti128 is available only in AVX2
1346       Assembler::vinserti128(dst, nds, src, imm8);
1347     } else {
1348       Assembler::vinsertf128(dst, nds, src, imm8);
1349     }
1350   }
1351 
1352   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1353     if (UseAVX > 2) {
1354       Assembler::vextracti32x4(dst, src, imm8);
1355     } else if (UseAVX > 1) {
1356       // vextracti128 is available only in AVX2
1357       Assembler::vextracti128(dst, src, imm8);
1358     } else {
1359       Assembler::vextractf128(dst, src, imm8);
1360     }
1361   }
1362 
1363   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1364     if (UseAVX > 2) {
1365       Assembler::vextracti32x4(dst, src, imm8);
1366     } else if (UseAVX > 1) {
1367       // vextracti128 is available only in AVX2
1368       Assembler::vextracti128(dst, src, imm8);
1369     } else {
1370       Assembler::vextractf128(dst, src, imm8);
1371     }
1372   }
1373 
1374   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1375   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1376     vinserti128(dst, dst, src, 1);
1377   }
1378   void vinserti128_high(XMMRegister dst, Address src) {
1379     vinserti128(dst, dst, src, 1);
1380   }
1381   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1382     vextracti128(dst, src, 1);
1383   }
1384   void vextracti128_high(Address dst, XMMRegister src) {
1385     vextracti128(dst, src, 1);
1386   }
1387 
1388   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1389     if (UseAVX > 2) {
1390       Assembler::vinsertf32x4(dst, dst, src, 1);
1391     } else {
1392       Assembler::vinsertf128(dst, dst, src, 1);
1393     }
1394   }
1395 
1396   void vinsertf128_high(XMMRegister dst, Address src) {
1397     if (UseAVX > 2) {
1398       Assembler::vinsertf32x4(dst, dst, src, 1);
1399     } else {
1400       Assembler::vinsertf128(dst, dst, src, 1);
1401     }
1402   }
1403 
1404   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1405     if (UseAVX > 2) {
1406       Assembler::vextractf32x4(dst, src, 1);
1407     } else {
1408       Assembler::vextractf128(dst, src, 1);
1409     }
1410   }
1411 
1412   void vextractf128_high(Address dst, XMMRegister src) {
1413     if (UseAVX > 2) {
1414       Assembler::vextractf32x4(dst, src, 1);
1415     } else {
1416       Assembler::vextractf128(dst, src, 1);
1417     }
1418   }
1419 
1420   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1421   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1422     Assembler::vinserti64x4(dst, dst, src, 1);
1423   }
1424   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1425     Assembler::vinsertf64x4(dst, dst, src, 1);
1426   }
1427   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1428     Assembler::vextracti64x4(dst, src, 1);
1429   }
1430   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1431     Assembler::vextractf64x4(dst, src, 1);
1432   }
1433   void vextractf64x4_high(Address dst, XMMRegister src) {
1434     Assembler::vextractf64x4(dst, src, 1);
1435   }
1436   void vinsertf64x4_high(XMMRegister dst, Address src) {
1437     Assembler::vinsertf64x4(dst, dst, src, 1);
1438   }
1439 
1440   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1441   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1442     vinserti128(dst, dst, src, 0);
1443   }
1444   void vinserti128_low(XMMRegister dst, Address src) {
1445     vinserti128(dst, dst, src, 0);
1446   }
1447   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1448     vextracti128(dst, src, 0);
1449   }
1450   void vextracti128_low(Address dst, XMMRegister src) {
1451     vextracti128(dst, src, 0);
1452   }
1453 
1454   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1455     if (UseAVX > 2) {
1456       Assembler::vinsertf32x4(dst, dst, src, 0);
1457     } else {
1458       Assembler::vinsertf128(dst, dst, src, 0);
1459     }
1460   }
1461 
1462   void vinsertf128_low(XMMRegister dst, Address src) {
1463     if (UseAVX > 2) {
1464       Assembler::vinsertf32x4(dst, dst, src, 0);
1465     } else {
1466       Assembler::vinsertf128(dst, dst, src, 0);
1467     }
1468   }
1469 
1470   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1471     if (UseAVX > 2) {
1472       Assembler::vextractf32x4(dst, src, 0);
1473     } else {
1474       Assembler::vextractf128(dst, src, 0);
1475     }
1476   }
1477 
1478   void vextractf128_low(Address dst, XMMRegister src) {
1479     if (UseAVX > 2) {
1480       Assembler::vextractf32x4(dst, src, 0);
1481     } else {
1482       Assembler::vextractf128(dst, src, 0);
1483     }
1484   }
1485 
1486   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1487   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1488     Assembler::vinserti64x4(dst, dst, src, 0);
1489   }
1490   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1491     Assembler::vinsertf64x4(dst, dst, src, 0);
1492   }
1493   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1494     Assembler::vextracti64x4(dst, src, 0);
1495   }
1496   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1497     Assembler::vextractf64x4(dst, src, 0);
1498   }
1499   void vextractf64x4_low(Address dst, XMMRegister src) {
1500     Assembler::vextractf64x4(dst, src, 0);
1501   }
1502   void vinsertf64x4_low(XMMRegister dst, Address src) {
1503     Assembler::vinsertf64x4(dst, dst, src, 0);
1504   }
1505 
1506   // Carry-Less Multiplication Quadword
1507   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1508     // 0x00 - multiply lower 64 bits [0:63]
1509     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1510   }
1511   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1512     // 0x11 - multiply upper 64 bits [64:127]
1513     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1514   }
1515   void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1516     // 0x10 - multiply nds[0:63] and src[64:127]
1517     Assembler::vpclmulqdq(dst, nds, src, 0x10);
1518   }
1519   void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1520     //0x01 - multiply nds[64:127] and src[0:63]
1521     Assembler::vpclmulqdq(dst, nds, src, 0x01);
1522   }
1523 
1524   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1525     // 0x00 - multiply lower 64 bits [0:63]
1526     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1527   }
1528   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1529     // 0x11 - multiply upper 64 bits [64:127]
1530     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1531   }
1532 
1533   // Data
1534 
1535   void cmov32( Condition cc, Register dst, Address  src);
1536   void cmov32( Condition cc, Register dst, Register src);
1537 
1538   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1539 
1540   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1541   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1542 
1543   void movoop(Register dst, jobject obj);
1544   void movoop(Address dst, jobject obj);
1545 
1546   void mov_metadata(Register dst, Metadata* obj);
1547   void mov_metadata(Address dst, Metadata* obj);
1548 
1549   void movptr(ArrayAddress dst, Register src);
1550   // can this do an lea?
1551   void movptr(Register dst, ArrayAddress src);
1552 
1553   void movptr(Register dst, Address src);
1554 
1555 #ifdef _LP64
1556   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1557 #else
1558   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1559 #endif
1560 
1561   void movptr(Register dst, intptr_t src);
1562   void movptr(Register dst, Register src);
1563   void movptr(Address dst, intptr_t src);
1564 
1565   void movptr(Address dst, Register src);
1566 
1567   void movptr(Register dst, RegisterOrConstant src) {
1568     if (src.is_constant()) movptr(dst, src.as_constant());
1569     else                   movptr(dst, src.as_register());
1570   }
1571 
1572 #ifdef _LP64
1573   // Generally the next two are only used for moving NULL
1574   // Although there are situations in initializing the mark word where
1575   // they could be used. They are dangerous.
1576 
1577   // They only exist on LP64 so that int32_t and intptr_t are not the same
1578   // and we have ambiguous declarations.
1579 
1580   void movptr(Address dst, int32_t imm32);
1581   void movptr(Register dst, int32_t imm32);
1582 #endif // _LP64
1583 
1584   // to avoid hiding movl
1585   void mov32(AddressLiteral dst, Register src);
1586   void mov32(Register dst, AddressLiteral src);
1587 
1588   // to avoid hiding movb
1589   void movbyte(ArrayAddress dst, int src);
1590 
1591   // Import other mov() methods from the parent class or else
1592   // they will be hidden by the following overriding declaration.
1593   using Assembler::movdl;
1594   using Assembler::movq;
1595   void movdl(XMMRegister dst, AddressLiteral src);
1596   void movq(XMMRegister dst, AddressLiteral src);
1597 
1598   // Can push value or effective address
1599   void pushptr(AddressLiteral src);
1600 
1601   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1602   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1603 
1604   void pushoop(jobject obj);
1605   void pushklass(Metadata* obj);
1606 
1607   // sign extend as need a l to ptr sized element
1608   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1609   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1610 
1611   // C2 compiled method's prolog code.
1612   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1613 
1614   // clear memory of size 'cnt' qwords, starting at 'base';
1615   // if 'is_large' is set, do not try to produce short loop
1616   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1617 
1618   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1619   void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1620 
1621 #ifdef COMPILER2
1622   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1623                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1624 
1625   // IndexOf strings.
1626   // Small strings are loaded through stack if they cross page boundary.
1627   void string_indexof(Register str1, Register str2,
1628                       Register cnt1, Register cnt2,
1629                       int int_cnt2,  Register result,
1630                       XMMRegister vec, Register tmp,
1631                       int ae);
1632 
1633   // IndexOf for constant substrings with size >= 8 elements
1634   // which don't need to be loaded through stack.
1635   void string_indexofC8(Register str1, Register str2,
1636                       Register cnt1, Register cnt2,
1637                       int int_cnt2,  Register result,
1638                       XMMRegister vec, Register tmp,
1639                       int ae);
1640 
1641     // Smallest code: we don't need to load through stack,
1642     // check string tail.
1643 
1644   // helper function for string_compare
1645   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1646                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1647                           Address::ScaleFactor scale2, Register index, int ae);
1648   // Compare strings.
1649   void string_compare(Register str1, Register str2,
1650                       Register cnt1, Register cnt2, Register result,
1651                       XMMRegister vec1, int ae);
1652 
1653   // Search for Non-ASCII character (Negative byte value) in a byte array,
1654   // return true if it has any and false otherwise.
1655   void has_negatives(Register ary1, Register len,
1656                      Register result, Register tmp1,
1657                      XMMRegister vec1, XMMRegister vec2);
1658 
1659   // Compare char[] or byte[] arrays.
1660   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1661                      Register limit, Register result, Register chr,
1662                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1663 
1664 #endif
1665 
1666   // Fill primitive arrays
1667   void generate_fill(BasicType t, bool aligned,
1668                      Register to, Register value, Register count,
1669                      Register rtmp, XMMRegister xtmp);
1670 
1671   void encode_iso_array(Register src, Register dst, Register len,
1672                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1673                         XMMRegister tmp4, Register tmp5, Register result);
1674 
1675 #ifdef _LP64
1676   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1677   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1678                              Register y, Register y_idx, Register z,
1679                              Register carry, Register product,
1680                              Register idx, Register kdx);
1681   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1682                               Register yz_idx, Register idx,
1683                               Register carry, Register product, int offset);
1684   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1685                                     Register carry, Register carry2,
1686                                     Register idx, Register jdx,
1687                                     Register yz_idx1, Register yz_idx2,
1688                                     Register tmp, Register tmp3, Register tmp4);
1689   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1690                                Register yz_idx, Register idx, Register jdx,
1691                                Register carry, Register product,
1692                                Register carry2);
1693   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1694                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1695   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1696                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1697   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1698                             Register tmp2);
1699   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1700                        Register rdxReg, Register raxReg);
1701   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1702   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1703                        Register tmp3, Register tmp4);
1704   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1705                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1706 
1707   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1708                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1709                Register raxReg);
1710   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1711                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1712                Register raxReg);
1713   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1714                            Register result, Register tmp1, Register tmp2,
1715                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1716 #endif
1717 
1718   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1719   void update_byte_crc32(Register crc, Register val, Register table);
1720   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1721   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1722   // Note on a naming convention:
1723   // Prefix w = register only used on a Westmere+ architecture
1724   // Prefix n = register only used on a Nehalem architecture
1725 #ifdef _LP64
1726   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1727                        Register tmp1, Register tmp2, Register tmp3);
1728 #else
1729   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1730                        Register tmp1, Register tmp2, Register tmp3,
1731                        XMMRegister xtmp1, XMMRegister xtmp2);
1732 #endif
1733   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1734                         Register in_out,
1735                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1736                         XMMRegister w_xtmp2,
1737                         Register tmp1,
1738                         Register n_tmp2, Register n_tmp3);
1739   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1740                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1741                        Register tmp1, Register tmp2,
1742                        Register n_tmp3);
1743   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1744                          Register in_out1, Register in_out2, Register in_out3,
1745                          Register tmp1, Register tmp2, Register tmp3,
1746                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1747                          Register tmp4, Register tmp5,
1748                          Register n_tmp6);
1749   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1750                             Register tmp1, Register tmp2, Register tmp3,
1751                             Register tmp4, Register tmp5, Register tmp6,
1752                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1753                             bool is_pclmulqdq_supported);
1754   // Fold 128-bit data chunk
1755   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1756   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1757   // Fold 8-bit data
1758   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1759   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1760   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1761 
1762   // Compress char[] array to byte[].
1763   void char_array_compress(Register src, Register dst, Register len,
1764                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1765                            XMMRegister tmp4, Register tmp5, Register result);
1766 
1767   // Inflate byte[] array to char[].
1768   void byte_array_inflate(Register src, Register dst, Register len,
1769                           XMMRegister tmp1, Register tmp2);
1770 
1771 };
1772 
1773 /**
1774  * class SkipIfEqual:
1775  *
1776  * Instantiating this class will result in assembly code being output that will
1777  * jump around any code emitted between the creation of the instance and it's
1778  * automatic destruction at the end of a scope block, depending on the value of
1779  * the flag passed to the constructor, which will be checked at run-time.
1780  */
1781 class SkipIfEqual {
1782  private:
1783   MacroAssembler* _masm;
1784   Label _label;
1785 
1786  public:
1787    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1788    ~SkipIfEqual();
1789 };
1790 
1791 #endif // CPU_X86_MACROASSEMBLER_X86_HPP