1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc_interface/collectedHeap.inline.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/cardTableModRefBS.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc_implementation/g1/g1CollectedHeap.inline.hpp"
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc_implementation/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
58 _is_lval = false;
59 _target = target;
60 switch (rtype) {
61 case relocInfo::oop_type:
62 case relocInfo::metadata_type:
63 // Oops are a special case. Normally they would be their own section
64 // but in cases like icBuffer they are literals in the code stream that
65 // we don't have a section for. We use none so that we get a literal address
66 // which is always patchable.
67 break;
68 case relocInfo::external_word_type:
69 _rspec = external_word_Relocation::spec(target);
70 break;
71 case relocInfo::internal_word_type:
72 _rspec = internal_word_Relocation::spec(target);
73 break;
74 case relocInfo::opt_virtual_call_type:
75 _rspec = opt_virtual_call_Relocation::spec();
76 break;
77 case relocInfo::static_call_type:
78 _rspec = static_call_Relocation::spec();
79 break;
80 case relocInfo::runtime_call_type:
81 _rspec = runtime_call_Relocation::spec();
82 break;
83 case relocInfo::poll_type:
84 case relocInfo::poll_return_type:
85 _rspec = Relocation::spec_simple(rtype);
86 break;
87 case relocInfo::none:
88 break;
89 default:
90 ShouldNotReachHere();
91 break;
92 }
93 }
94
95 // Implementation of Address
96
97 #ifdef _LP64
98
99 Address Address::make_array(ArrayAddress adr) {
100 // Not implementable on 64bit machines
101 // Should have been handled higher up the call chain.
102 ShouldNotReachHere();
103 return Address();
104 }
105
106 // exceedingly dangerous constructor
107 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
108 _base = noreg;
109 _index = noreg;
110 _scale = no_scale;
111 _disp = disp;
112 switch (rtype) {
113 case relocInfo::external_word_type:
114 _rspec = external_word_Relocation::spec(loc);
115 break;
116 case relocInfo::internal_word_type:
117 _rspec = internal_word_Relocation::spec(loc);
118 break;
119 case relocInfo::runtime_call_type:
120 // HMM
121 _rspec = runtime_call_Relocation::spec();
122 break;
123 case relocInfo::poll_type:
124 case relocInfo::poll_return_type:
125 _rspec = Relocation::spec_simple(rtype);
126 break;
127 case relocInfo::none:
128 break;
129 default:
130 ShouldNotReachHere();
131 }
132 }
133 #else // LP64
134
135 Address Address::make_array(ArrayAddress adr) {
136 AddressLiteral base = adr.base();
137 Address index = adr.index();
138 assert(index._disp == 0, "must not have disp"); // maybe it can?
139 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
140 array._rspec = base._rspec;
141 return array;
142 }
143
144 // exceedingly dangerous constructor
145 Address::Address(address loc, RelocationHolder spec) {
146 _base = noreg;
147 _index = noreg;
148 _scale = no_scale;
149 _disp = (intptr_t) loc;
150 _rspec = spec;
151 }
152
153 #endif // _LP64
154
155
156
157 // Convert the raw encoding form into the form expected by the constructor for
158 // Address. An index of 4 (rsp) corresponds to having no index, so convert
159 // that to noreg for the Address constructor.
160 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
161 RelocationHolder rspec;
162 if (disp_reloc != relocInfo::none) {
163 rspec = Relocation::spec_simple(disp_reloc);
164 }
165 bool valid_index = index != rsp->encoding();
166 if (valid_index) {
167 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
168 madr._rspec = rspec;
169 return madr;
170 } else {
171 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
172 madr._rspec = rspec;
173 return madr;
174 }
175 }
176
177 // Implementation of Assembler
178
179 int AbstractAssembler::code_fill_byte() {
180 return (u_char)'\xF4'; // hlt
181 }
182
183 // make this go away someday
184 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
185 if (rtype == relocInfo::none)
186 emit_int32(data);
187 else emit_data(data, Relocation::spec_simple(rtype), format);
188 }
189
190 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
191 assert(imm_operand == 0, "default format must be immediate in this file");
192 assert(inst_mark() != NULL, "must be inside InstructionMark");
193 if (rspec.type() != relocInfo::none) {
194 #ifdef ASSERT
195 check_relocation(rspec, format);
196 #endif
197 // Do not use AbstractAssembler::relocate, which is not intended for
198 // embedded words. Instead, relocate to the enclosing instruction.
199
200 // hack. call32 is too wide for mask so use disp32
201 if (format == call32_operand)
202 code_section()->relocate(inst_mark(), rspec, disp32_operand);
203 else
204 code_section()->relocate(inst_mark(), rspec, format);
205 }
206 emit_int32(data);
207 }
208
209 static int encode(Register r) {
210 int enc = r->encoding();
211 if (enc >= 8) {
212 enc -= 8;
213 }
214 return enc;
215 }
216
217 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
218 assert(dst->has_byte_register(), "must have byte register");
219 assert(isByte(op1) && isByte(op2), "wrong opcode");
220 assert(isByte(imm8), "not a byte");
221 assert((op1 & 0x01) == 0, "should be 8bit operation");
222 emit_int8(op1);
223 emit_int8(op2 | encode(dst));
224 emit_int8(imm8);
225 }
226
227
228 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
229 assert(isByte(op1) && isByte(op2), "wrong opcode");
230 assert((op1 & 0x01) == 1, "should be 32bit operation");
231 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
232 if (is8bit(imm32)) {
233 emit_int8(op1 | 0x02); // set sign bit
234 emit_int8(op2 | encode(dst));
235 emit_int8(imm32 & 0xFF);
236 } else {
237 emit_int8(op1);
238 emit_int8(op2 | encode(dst));
239 emit_int32(imm32);
240 }
241 }
242
243 // Force generation of a 4 byte immediate value even if it fits into 8bit
244 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
245 assert(isByte(op1) && isByte(op2), "wrong opcode");
246 assert((op1 & 0x01) == 1, "should be 32bit operation");
247 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
248 emit_int8(op1);
249 emit_int8(op2 | encode(dst));
250 emit_int32(imm32);
251 }
252
253 // immediate-to-memory forms
254 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
255 assert((op1 & 0x01) == 1, "should be 32bit operation");
256 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
257 if (is8bit(imm32)) {
258 emit_int8(op1 | 0x02); // set sign bit
259 emit_operand(rm, adr, 1);
260 emit_int8(imm32 & 0xFF);
261 } else {
262 emit_int8(op1);
263 emit_operand(rm, adr, 4);
264 emit_int32(imm32);
265 }
266 }
267
268
269 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
270 assert(isByte(op1) && isByte(op2), "wrong opcode");
271 emit_int8(op1);
272 emit_int8(op2 | encode(dst) << 3 | encode(src));
273 }
274
275
276 void Assembler::emit_operand(Register reg, Register base, Register index,
277 Address::ScaleFactor scale, int disp,
278 RelocationHolder const& rspec,
279 int rip_relative_correction) {
280 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
281
282 // Encode the registers as needed in the fields they are used in
283
284 int regenc = encode(reg) << 3;
285 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
286 int baseenc = base->is_valid() ? encode(base) : 0;
287
288 if (base->is_valid()) {
289 if (index->is_valid()) {
290 assert(scale != Address::no_scale, "inconsistent address");
291 // [base + index*scale + disp]
292 if (disp == 0 && rtype == relocInfo::none &&
293 base != rbp LP64_ONLY(&& base != r13)) {
294 // [base + index*scale]
295 // [00 reg 100][ss index base]
296 assert(index != rsp, "illegal addressing mode");
297 emit_int8(0x04 | regenc);
298 emit_int8(scale << 6 | indexenc | baseenc);
299 } else if (is8bit(disp) && rtype == relocInfo::none) {
300 // [base + index*scale + imm8]
301 // [01 reg 100][ss index base] imm8
302 assert(index != rsp, "illegal addressing mode");
303 emit_int8(0x44 | regenc);
304 emit_int8(scale << 6 | indexenc | baseenc);
305 emit_int8(disp & 0xFF);
306 } else {
307 // [base + index*scale + disp32]
308 // [10 reg 100][ss index base] disp32
309 assert(index != rsp, "illegal addressing mode");
310 emit_int8(0x84 | regenc);
311 emit_int8(scale << 6 | indexenc | baseenc);
312 emit_data(disp, rspec, disp32_operand);
313 }
314 } else if (base == rsp LP64_ONLY(|| base == r12)) {
315 // [rsp + disp]
316 if (disp == 0 && rtype == relocInfo::none) {
317 // [rsp]
318 // [00 reg 100][00 100 100]
319 emit_int8(0x04 | regenc);
320 emit_int8(0x24);
321 } else if (is8bit(disp) && rtype == relocInfo::none) {
322 // [rsp + imm8]
323 // [01 reg 100][00 100 100] disp8
324 emit_int8(0x44 | regenc);
325 emit_int8(0x24);
326 emit_int8(disp & 0xFF);
327 } else {
328 // [rsp + imm32]
329 // [10 reg 100][00 100 100] disp32
330 emit_int8(0x84 | regenc);
331 emit_int8(0x24);
332 emit_data(disp, rspec, disp32_operand);
333 }
334 } else {
335 // [base + disp]
336 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
337 if (disp == 0 && rtype == relocInfo::none &&
338 base != rbp LP64_ONLY(&& base != r13)) {
339 // [base]
340 // [00 reg base]
341 emit_int8(0x00 | regenc | baseenc);
342 } else if (is8bit(disp) && rtype == relocInfo::none) {
343 // [base + disp8]
344 // [01 reg base] disp8
345 emit_int8(0x40 | regenc | baseenc);
346 emit_int8(disp & 0xFF);
347 } else {
348 // [base + disp32]
349 // [10 reg base] disp32
350 emit_int8(0x80 | regenc | baseenc);
351 emit_data(disp, rspec, disp32_operand);
352 }
353 }
354 } else {
355 if (index->is_valid()) {
356 assert(scale != Address::no_scale, "inconsistent address");
357 // [index*scale + disp]
358 // [00 reg 100][ss index 101] disp32
359 assert(index != rsp, "illegal addressing mode");
360 emit_int8(0x04 | regenc);
361 emit_int8(scale << 6 | indexenc | 0x05);
362 emit_data(disp, rspec, disp32_operand);
363 } else if (rtype != relocInfo::none ) {
364 // [disp] (64bit) RIP-RELATIVE (32bit) abs
365 // [00 000 101] disp32
366
367 emit_int8(0x05 | regenc);
368 // Note that the RIP-rel. correction applies to the generated
369 // disp field, but _not_ to the target address in the rspec.
370
371 // disp was created by converting the target address minus the pc
372 // at the start of the instruction. That needs more correction here.
373 // intptr_t disp = target - next_ip;
374 assert(inst_mark() != NULL, "must be inside InstructionMark");
375 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
376 int64_t adjusted = disp;
377 // Do rip-rel adjustment for 64bit
378 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
379 assert(is_simm32(adjusted),
380 "must be 32bit offset (RIP relative address)");
381 emit_data((int32_t) adjusted, rspec, disp32_operand);
382
383 } else {
384 // 32bit never did this, did everything as the rip-rel/disp code above
385 // [disp] ABSOLUTE
386 // [00 reg 100][00 100 101] disp32
387 emit_int8(0x04 | regenc);
388 emit_int8(0x25);
389 emit_data(disp, rspec, disp32_operand);
390 }
391 }
392 }
393
394 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
395 Address::ScaleFactor scale, int disp,
396 RelocationHolder const& rspec) {
397 emit_operand((Register)reg, base, index, scale, disp, rspec);
398 }
399
400 // Secret local extension to Assembler::WhichOperand:
401 #define end_pc_operand (_WhichOperand_limit)
402
403 address Assembler::locate_operand(address inst, WhichOperand which) {
404 // Decode the given instruction, and return the address of
405 // an embedded 32-bit operand word.
406
407 // If "which" is disp32_operand, selects the displacement portion
408 // of an effective address specifier.
409 // If "which" is imm64_operand, selects the trailing immediate constant.
410 // If "which" is call32_operand, selects the displacement of a call or jump.
411 // Caller is responsible for ensuring that there is such an operand,
412 // and that it is 32/64 bits wide.
413
414 // If "which" is end_pc_operand, find the end of the instruction.
415
416 address ip = inst;
417 bool is_64bit = false;
418
419 debug_only(bool has_disp32 = false);
420 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
421
422 again_after_prefix:
423 switch (0xFF & *ip++) {
424
425 // These convenience macros generate groups of "case" labels for the switch.
426 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
427 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
428 case (x)+4: case (x)+5: case (x)+6: case (x)+7
429 #define REP16(x) REP8((x)+0): \
430 case REP8((x)+8)
431
432 case CS_segment:
433 case SS_segment:
434 case DS_segment:
435 case ES_segment:
436 case FS_segment:
437 case GS_segment:
438 // Seems dubious
439 LP64_ONLY(assert(false, "shouldn't have that prefix"));
440 assert(ip == inst+1, "only one prefix allowed");
441 goto again_after_prefix;
442
443 case 0x67:
444 case REX:
445 case REX_B:
446 case REX_X:
447 case REX_XB:
448 case REX_R:
449 case REX_RB:
450 case REX_RX:
451 case REX_RXB:
452 NOT_LP64(assert(false, "64bit prefixes"));
453 goto again_after_prefix;
454
455 case REX_W:
456 case REX_WB:
457 case REX_WX:
458 case REX_WXB:
459 case REX_WR:
460 case REX_WRB:
461 case REX_WRX:
462 case REX_WRXB:
463 NOT_LP64(assert(false, "64bit prefixes"));
464 is_64bit = true;
465 goto again_after_prefix;
466
467 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
468 case 0x88: // movb a, r
469 case 0x89: // movl a, r
470 case 0x8A: // movb r, a
471 case 0x8B: // movl r, a
472 case 0x8F: // popl a
473 debug_only(has_disp32 = true);
474 break;
475
476 case 0x68: // pushq #32
477 if (which == end_pc_operand) {
478 return ip + 4;
479 }
480 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
481 return ip; // not produced by emit_operand
482
483 case 0x66: // movw ... (size prefix)
484 again_after_size_prefix2:
485 switch (0xFF & *ip++) {
486 case REX:
487 case REX_B:
488 case REX_X:
489 case REX_XB:
490 case REX_R:
491 case REX_RB:
492 case REX_RX:
493 case REX_RXB:
494 case REX_W:
495 case REX_WB:
496 case REX_WX:
497 case REX_WXB:
498 case REX_WR:
499 case REX_WRB:
500 case REX_WRX:
501 case REX_WRXB:
502 NOT_LP64(assert(false, "64bit prefix found"));
503 goto again_after_size_prefix2;
504 case 0x8B: // movw r, a
505 case 0x89: // movw a, r
506 debug_only(has_disp32 = true);
507 break;
508 case 0xC7: // movw a, #16
509 debug_only(has_disp32 = true);
510 tail_size = 2; // the imm16
511 break;
512 case 0x0F: // several SSE/SSE2 variants
513 ip--; // reparse the 0x0F
514 goto again_after_prefix;
515 default:
516 ShouldNotReachHere();
517 }
518 break;
519
520 case REP8(0xB8): // movl/q r, #32/#64(oop?)
521 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
522 // these asserts are somewhat nonsensical
523 #ifndef _LP64
524 assert(which == imm_operand || which == disp32_operand,
525 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
526 #else
527 assert((which == call32_operand || which == imm_operand) && is_64bit ||
528 which == narrow_oop_operand && !is_64bit,
529 err_msg("which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)));
530 #endif // _LP64
531 return ip;
532
533 case 0x69: // imul r, a, #32
534 case 0xC7: // movl a, #32(oop?)
535 tail_size = 4;
536 debug_only(has_disp32 = true); // has both kinds of operands!
537 break;
538
539 case 0x0F: // movx..., etc.
540 switch (0xFF & *ip++) {
541 case 0x3A: // pcmpestri
542 tail_size = 1;
543 case 0x38: // ptest, pmovzxbw
544 ip++; // skip opcode
545 debug_only(has_disp32 = true); // has both kinds of operands!
546 break;
547
548 case 0x70: // pshufd r, r/a, #8
549 debug_only(has_disp32 = true); // has both kinds of operands!
550 case 0x73: // psrldq r, #8
551 tail_size = 1;
552 break;
553
554 case 0x12: // movlps
555 case 0x28: // movaps
556 case 0x2E: // ucomiss
557 case 0x2F: // comiss
558 case 0x54: // andps
559 case 0x55: // andnps
560 case 0x56: // orps
561 case 0x57: // xorps
562 case 0x6E: // movd
563 case 0x7E: // movd
564 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
565 debug_only(has_disp32 = true);
566 break;
567
568 case 0xAD: // shrd r, a, %cl
569 case 0xAF: // imul r, a
570 case 0xBE: // movsbl r, a (movsxb)
571 case 0xBF: // movswl r, a (movsxw)
572 case 0xB6: // movzbl r, a (movzxb)
573 case 0xB7: // movzwl r, a (movzxw)
574 case REP16(0x40): // cmovl cc, r, a
575 case 0xB0: // cmpxchgb
576 case 0xB1: // cmpxchg
577 case 0xC1: // xaddl
578 case 0xC7: // cmpxchg8
579 case REP16(0x90): // setcc a
580 debug_only(has_disp32 = true);
581 // fall out of the switch to decode the address
582 break;
583
584 case 0xC4: // pinsrw r, a, #8
585 debug_only(has_disp32 = true);
586 case 0xC5: // pextrw r, r, #8
587 tail_size = 1; // the imm8
588 break;
589
590 case 0xAC: // shrd r, a, #8
591 debug_only(has_disp32 = true);
592 tail_size = 1; // the imm8
593 break;
594
595 case REP16(0x80): // jcc rdisp32
596 if (which == end_pc_operand) return ip + 4;
597 assert(which == call32_operand, "jcc has no disp32 or imm");
598 return ip;
599 default:
600 ShouldNotReachHere();
601 }
602 break;
603
604 case 0x81: // addl a, #32; addl r, #32
605 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
606 // on 32bit in the case of cmpl, the imm might be an oop
607 tail_size = 4;
608 debug_only(has_disp32 = true); // has both kinds of operands!
609 break;
610
611 case 0x83: // addl a, #8; addl r, #8
612 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
613 debug_only(has_disp32 = true); // has both kinds of operands!
614 tail_size = 1;
615 break;
616
617 case 0x9B:
618 switch (0xFF & *ip++) {
619 case 0xD9: // fnstcw a
620 debug_only(has_disp32 = true);
621 break;
622 default:
623 ShouldNotReachHere();
624 }
625 break;
626
627 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
628 case REP4(0x10): // adc...
629 case REP4(0x20): // and...
630 case REP4(0x30): // xor...
631 case REP4(0x08): // or...
632 case REP4(0x18): // sbb...
633 case REP4(0x28): // sub...
634 case 0xF7: // mull a
635 case 0x8D: // lea r, a
636 case 0x87: // xchg r, a
637 case REP4(0x38): // cmp...
638 case 0x85: // test r, a
639 debug_only(has_disp32 = true); // has both kinds of operands!
640 break;
641
642 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
643 case 0xC6: // movb a, #8
644 case 0x80: // cmpb a, #8
645 case 0x6B: // imul r, a, #8
646 debug_only(has_disp32 = true); // has both kinds of operands!
647 tail_size = 1; // the imm8
648 break;
649
650 case 0xC4: // VEX_3bytes
651 case 0xC5: // VEX_2bytes
652 assert((UseAVX > 0), "shouldn't have VEX prefix");
653 assert(ip == inst+1, "no prefixes allowed");
654 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
655 // but they have prefix 0x0F and processed when 0x0F processed above.
656 //
657 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
658 // instructions (these instructions are not supported in 64-bit mode).
659 // To distinguish them bits [7:6] are set in the VEX second byte since
660 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
661 // those VEX bits REX and vvvv bits are inverted.
662 //
663 // Fortunately C2 doesn't generate these instructions so we don't need
664 // to check for them in product version.
665
666 // Check second byte
667 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
668
669 // First byte
670 if ((0xFF & *inst) == VEX_3bytes) {
671 ip++; // third byte
672 is_64bit = ((VEX_W & *ip) == VEX_W);
673 }
674 ip++; // opcode
675 // To find the end of instruction (which == end_pc_operand).
676 switch (0xFF & *ip) {
677 case 0x61: // pcmpestri r, r/a, #8
678 case 0x70: // pshufd r, r/a, #8
679 case 0x73: // psrldq r, #8
680 tail_size = 1; // the imm8
681 break;
682 default:
683 break;
684 }
685 ip++; // skip opcode
686 debug_only(has_disp32 = true); // has both kinds of operands!
687 break;
688
689 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
690 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
691 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
692 case 0xDD: // fld_d a; fst_d a; fstp_d a
693 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
694 case 0xDF: // fild_d a; fistp_d a
695 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
696 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
697 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
698 debug_only(has_disp32 = true);
699 break;
700
701 case 0xE8: // call rdisp32
702 case 0xE9: // jmp rdisp32
703 if (which == end_pc_operand) return ip + 4;
704 assert(which == call32_operand, "call has no disp32 or imm");
705 return ip;
706
707 case 0xF0: // Lock
708 assert(os::is_MP(), "only on MP");
709 goto again_after_prefix;
710
711 case 0xF3: // For SSE
712 case 0xF2: // For SSE2
713 switch (0xFF & *ip++) {
714 case REX:
715 case REX_B:
716 case REX_X:
717 case REX_XB:
718 case REX_R:
719 case REX_RB:
720 case REX_RX:
721 case REX_RXB:
722 case REX_W:
723 case REX_WB:
724 case REX_WX:
725 case REX_WXB:
726 case REX_WR:
727 case REX_WRB:
728 case REX_WRX:
729 case REX_WRXB:
730 NOT_LP64(assert(false, "found 64bit prefix"));
731 ip++;
732 default:
733 ip++;
734 }
735 debug_only(has_disp32 = true); // has both kinds of operands!
736 break;
737
738 default:
739 ShouldNotReachHere();
740
741 #undef REP8
742 #undef REP16
743 }
744
745 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
746 #ifdef _LP64
747 assert(which != imm_operand, "instruction is not a movq reg, imm64");
748 #else
749 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
750 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
751 #endif // LP64
752 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
753
754 // parse the output of emit_operand
755 int op2 = 0xFF & *ip++;
756 int base = op2 & 0x07;
757 int op3 = -1;
758 const int b100 = 4;
759 const int b101 = 5;
760 if (base == b100 && (op2 >> 6) != 3) {
761 op3 = 0xFF & *ip++;
762 base = op3 & 0x07; // refetch the base
763 }
764 // now ip points at the disp (if any)
765
766 switch (op2 >> 6) {
767 case 0:
768 // [00 reg 100][ss index base]
769 // [00 reg 100][00 100 esp]
770 // [00 reg base]
771 // [00 reg 100][ss index 101][disp32]
772 // [00 reg 101] [disp32]
773
774 if (base == b101) {
775 if (which == disp32_operand)
776 return ip; // caller wants the disp32
777 ip += 4; // skip the disp32
778 }
779 break;
780
781 case 1:
782 // [01 reg 100][ss index base][disp8]
783 // [01 reg 100][00 100 esp][disp8]
784 // [01 reg base] [disp8]
785 ip += 1; // skip the disp8
786 break;
787
788 case 2:
789 // [10 reg 100][ss index base][disp32]
790 // [10 reg 100][00 100 esp][disp32]
791 // [10 reg base] [disp32]
792 if (which == disp32_operand)
793 return ip; // caller wants the disp32
794 ip += 4; // skip the disp32
795 break;
796
797 case 3:
798 // [11 reg base] (not a memory addressing mode)
799 break;
800 }
801
802 if (which == end_pc_operand) {
803 return ip + tail_size;
804 }
805
806 #ifdef _LP64
807 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
808 #else
809 assert(which == imm_operand, "instruction has only an imm field");
810 #endif // LP64
811 return ip;
812 }
813
814 address Assembler::locate_next_instruction(address inst) {
815 // Secretly share code with locate_operand:
816 return locate_operand(inst, end_pc_operand);
817 }
818
819
820 #ifdef ASSERT
821 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
822 address inst = inst_mark();
823 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
824 address opnd;
825
826 Relocation* r = rspec.reloc();
827 if (r->type() == relocInfo::none) {
828 return;
829 } else if (r->is_call() || format == call32_operand) {
830 // assert(format == imm32_operand, "cannot specify a nonzero format");
831 opnd = locate_operand(inst, call32_operand);
832 } else if (r->is_data()) {
833 assert(format == imm_operand || format == disp32_operand
834 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
835 opnd = locate_operand(inst, (WhichOperand)format);
836 } else {
837 assert(format == imm_operand, "cannot specify a format");
838 return;
839 }
840 assert(opnd == pc(), "must put operand where relocs can find it");
841 }
842 #endif // ASSERT
843
844 void Assembler::emit_operand32(Register reg, Address adr) {
845 assert(reg->encoding() < 8, "no extended registers");
846 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
847 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
848 adr._rspec);
849 }
850
851 void Assembler::emit_operand(Register reg, Address adr,
852 int rip_relative_correction) {
853 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
854 adr._rspec,
855 rip_relative_correction);
856 }
857
858 void Assembler::emit_operand(XMMRegister reg, Address adr) {
859 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
860 adr._rspec);
861 }
862
863 // MMX operations
864 void Assembler::emit_operand(MMXRegister reg, Address adr) {
865 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
866 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
867 }
868
869 // work around gcc (3.2.1-7a) bug
870 void Assembler::emit_operand(Address adr, MMXRegister reg) {
871 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
872 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
873 }
874
875
876 void Assembler::emit_farith(int b1, int b2, int i) {
877 assert(isByte(b1) && isByte(b2), "wrong opcode");
878 assert(0 <= i && i < 8, "illegal stack offset");
879 emit_int8(b1);
880 emit_int8(b2 + i);
881 }
882
883
884 // Now the Assembler instructions (identical for 32/64 bits)
885
886 void Assembler::adcl(Address dst, int32_t imm32) {
887 InstructionMark im(this);
888 prefix(dst);
889 emit_arith_operand(0x81, rdx, dst, imm32);
890 }
891
892 void Assembler::adcl(Address dst, Register src) {
893 InstructionMark im(this);
894 prefix(dst, src);
895 emit_int8(0x11);
896 emit_operand(src, dst);
897 }
898
899 void Assembler::adcl(Register dst, int32_t imm32) {
900 prefix(dst);
901 emit_arith(0x81, 0xD0, dst, imm32);
902 }
903
904 void Assembler::adcl(Register dst, Address src) {
905 InstructionMark im(this);
906 prefix(src, dst);
907 emit_int8(0x13);
908 emit_operand(dst, src);
909 }
910
911 void Assembler::adcl(Register dst, Register src) {
912 (void) prefix_and_encode(dst->encoding(), src->encoding());
913 emit_arith(0x13, 0xC0, dst, src);
914 }
915
916 void Assembler::addl(Address dst, int32_t imm32) {
917 InstructionMark im(this);
918 prefix(dst);
919 emit_arith_operand(0x81, rax, dst, imm32);
920 }
921
922 void Assembler::addl(Address dst, Register src) {
923 InstructionMark im(this);
924 prefix(dst, src);
925 emit_int8(0x01);
926 emit_operand(src, dst);
927 }
928
929 void Assembler::addl(Register dst, int32_t imm32) {
930 prefix(dst);
931 emit_arith(0x81, 0xC0, dst, imm32);
932 }
933
934 void Assembler::addl(Register dst, Address src) {
935 InstructionMark im(this);
936 prefix(src, dst);
937 emit_int8(0x03);
938 emit_operand(dst, src);
939 }
940
941 void Assembler::addl(Register dst, Register src) {
942 (void) prefix_and_encode(dst->encoding(), src->encoding());
943 emit_arith(0x03, 0xC0, dst, src);
944 }
945
946 void Assembler::addr_nop_4() {
947 assert(UseAddressNop, "no CPU support");
948 // 4 bytes: NOP DWORD PTR [EAX+0]
949 emit_int8(0x0F);
950 emit_int8(0x1F);
951 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
952 emit_int8(0); // 8-bits offset (1 byte)
953 }
954
955 void Assembler::addr_nop_5() {
956 assert(UseAddressNop, "no CPU support");
957 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
958 emit_int8(0x0F);
959 emit_int8(0x1F);
960 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
961 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
962 emit_int8(0); // 8-bits offset (1 byte)
963 }
964
965 void Assembler::addr_nop_7() {
966 assert(UseAddressNop, "no CPU support");
967 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
968 emit_int8(0x0F);
969 emit_int8(0x1F);
970 emit_int8((unsigned char)0x80);
971 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
972 emit_int32(0); // 32-bits offset (4 bytes)
973 }
974
975 void Assembler::addr_nop_8() {
976 assert(UseAddressNop, "no CPU support");
977 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
978 emit_int8(0x0F);
979 emit_int8(0x1F);
980 emit_int8((unsigned char)0x84);
981 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
982 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
983 emit_int32(0); // 32-bits offset (4 bytes)
984 }
985
986 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
987 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
988 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
989 }
990
991 void Assembler::addsd(XMMRegister dst, Address src) {
992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
993 emit_simd_arith(0x58, dst, src, VEX_SIMD_F2);
994 }
995
996 void Assembler::addss(XMMRegister dst, XMMRegister src) {
997 NOT_LP64(assert(VM_Version::supports_sse(), ""));
998 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
999 }
1000
1001 void Assembler::addss(XMMRegister dst, Address src) {
1002 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1003 emit_simd_arith(0x58, dst, src, VEX_SIMD_F3);
1004 }
1005
1006 void Assembler::aesdec(XMMRegister dst, Address src) {
1007 assert(VM_Version::supports_aes(), "");
1008 InstructionMark im(this);
1009 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1010 emit_int8((unsigned char)0xDE);
1011 emit_operand(dst, src);
1012 }
1013
1014 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1015 assert(VM_Version::supports_aes(), "");
1016 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1017 emit_int8((unsigned char)0xDE);
1018 emit_int8(0xC0 | encode);
1019 }
1020
1021 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1022 assert(VM_Version::supports_aes(), "");
1023 InstructionMark im(this);
1024 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1025 emit_int8((unsigned char)0xDF);
1026 emit_operand(dst, src);
1027 }
1028
1029 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1030 assert(VM_Version::supports_aes(), "");
1031 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1032 emit_int8((unsigned char)0xDF);
1033 emit_int8((unsigned char)(0xC0 | encode));
1034 }
1035
1036 void Assembler::aesenc(XMMRegister dst, Address src) {
1037 assert(VM_Version::supports_aes(), "");
1038 InstructionMark im(this);
1039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1040 emit_int8((unsigned char)0xDC);
1041 emit_operand(dst, src);
1042 }
1043
1044 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1045 assert(VM_Version::supports_aes(), "");
1046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1047 emit_int8((unsigned char)0xDC);
1048 emit_int8(0xC0 | encode);
1049 }
1050
1051 void Assembler::aesenclast(XMMRegister dst, Address src) {
1052 assert(VM_Version::supports_aes(), "");
1053 InstructionMark im(this);
1054 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1055 emit_int8((unsigned char)0xDD);
1056 emit_operand(dst, src);
1057 }
1058
1059 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1060 assert(VM_Version::supports_aes(), "");
1061 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
1062 emit_int8((unsigned char)0xDD);
1063 emit_int8((unsigned char)(0xC0 | encode));
1064 }
1065
1066
1067 void Assembler::andl(Address dst, int32_t imm32) {
1068 InstructionMark im(this);
1069 prefix(dst);
1070 emit_int8((unsigned char)0x81);
1071 emit_operand(rsp, dst, 4);
1072 emit_int32(imm32);
1073 }
1074
1075 void Assembler::andl(Register dst, int32_t imm32) {
1076 prefix(dst);
1077 emit_arith(0x81, 0xE0, dst, imm32);
1078 }
1079
1080 void Assembler::andl(Register dst, Address src) {
1081 InstructionMark im(this);
1082 prefix(src, dst);
1083 emit_int8(0x23);
1084 emit_operand(dst, src);
1085 }
1086
1087 void Assembler::andl(Register dst, Register src) {
1088 (void) prefix_and_encode(dst->encoding(), src->encoding());
1089 emit_arith(0x23, 0xC0, dst, src);
1090 }
1091
1092 void Assembler::andnl(Register dst, Register src1, Register src2) {
1093 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1094 int encode = vex_prefix_0F38_and_encode(dst, src1, src2);
1095 emit_int8((unsigned char)0xF2);
1096 emit_int8((unsigned char)(0xC0 | encode));
1097 }
1098
1099 void Assembler::andnl(Register dst, Register src1, Address src2) {
1100 InstructionMark im(this);
1101 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1102 vex_prefix_0F38(dst, src1, src2);
1103 emit_int8((unsigned char)0xF2);
1104 emit_operand(dst, src2);
1105 }
1106
1107 void Assembler::bsfl(Register dst, Register src) {
1108 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1109 emit_int8(0x0F);
1110 emit_int8((unsigned char)0xBC);
1111 emit_int8((unsigned char)(0xC0 | encode));
1112 }
1113
1114 void Assembler::bsrl(Register dst, Register src) {
1115 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1116 emit_int8(0x0F);
1117 emit_int8((unsigned char)0xBD);
1118 emit_int8((unsigned char)(0xC0 | encode));
1119 }
1120
1121 void Assembler::bswapl(Register reg) { // bswap
1122 int encode = prefix_and_encode(reg->encoding());
1123 emit_int8(0x0F);
1124 emit_int8((unsigned char)(0xC8 | encode));
1125 }
1126
1127 void Assembler::blsil(Register dst, Register src) {
1128 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1129 int encode = vex_prefix_0F38_and_encode(rbx, dst, src);
1130 emit_int8((unsigned char)0xF3);
1131 emit_int8((unsigned char)(0xC0 | encode));
1132 }
1133
1134 void Assembler::blsil(Register dst, Address src) {
1135 InstructionMark im(this);
1136 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1137 vex_prefix_0F38(rbx, dst, src);
1138 emit_int8((unsigned char)0xF3);
1139 emit_operand(rbx, src);
1140 }
1141
1142 void Assembler::blsmskl(Register dst, Register src) {
1143 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1144 int encode = vex_prefix_0F38_and_encode(rdx, dst, src);
1145 emit_int8((unsigned char)0xF3);
1146 emit_int8((unsigned char)(0xC0 | encode));
1147 }
1148
1149 void Assembler::blsmskl(Register dst, Address src) {
1150 InstructionMark im(this);
1151 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1152 vex_prefix_0F38(rdx, dst, src);
1153 emit_int8((unsigned char)0xF3);
1154 emit_operand(rdx, src);
1155 }
1156
1157 void Assembler::blsrl(Register dst, Register src) {
1158 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1159 int encode = vex_prefix_0F38_and_encode(rcx, dst, src);
1160 emit_int8((unsigned char)0xF3);
1161 emit_int8((unsigned char)(0xC0 | encode));
1162 }
1163
1164 void Assembler::blsrl(Register dst, Address src) {
1165 InstructionMark im(this);
1166 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1167 vex_prefix_0F38(rcx, dst, src);
1168 emit_int8((unsigned char)0xF3);
1169 emit_operand(rcx, src);
1170 }
1171
1172 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1173 // suspect disp32 is always good
1174 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1175
1176 if (L.is_bound()) {
1177 const int long_size = 5;
1178 int offs = (int)( target(L) - pc() );
1179 assert(offs <= 0, "assembler error");
1180 InstructionMark im(this);
1181 // 1110 1000 #32-bit disp
1182 emit_int8((unsigned char)0xE8);
1183 emit_data(offs - long_size, rtype, operand);
1184 } else {
1185 InstructionMark im(this);
1186 // 1110 1000 #32-bit disp
1187 L.add_patch_at(code(), locator());
1188
1189 emit_int8((unsigned char)0xE8);
1190 emit_data(int(0), rtype, operand);
1191 }
1192 }
1193
1194 void Assembler::call(Register dst) {
1195 int encode = prefix_and_encode(dst->encoding());
1196 emit_int8((unsigned char)0xFF);
1197 emit_int8((unsigned char)(0xD0 | encode));
1198 }
1199
1200
1201 void Assembler::call(Address adr) {
1202 InstructionMark im(this);
1203 prefix(adr);
1204 emit_int8((unsigned char)0xFF);
1205 emit_operand(rdx, adr);
1206 }
1207
1208 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1209 assert(entry != NULL, "call most probably wrong");
1210 InstructionMark im(this);
1211 emit_int8((unsigned char)0xE8);
1212 intptr_t disp = entry - (pc() + sizeof(int32_t));
1213 assert(is_simm32(disp), "must be 32bit offset (call2)");
1214 // Technically, should use call32_operand, but this format is
1215 // implied by the fact that we're emitting a call instruction.
1216
1217 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1218 emit_data((int) disp, rspec, operand);
1219 }
1220
1221 void Assembler::cdql() {
1222 emit_int8((unsigned char)0x99);
1223 }
1224
1225 void Assembler::cld() {
1226 emit_int8((unsigned char)0xFC);
1227 }
1228
1229 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1230 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1231 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1232 emit_int8(0x0F);
1233 emit_int8(0x40 | cc);
1234 emit_int8((unsigned char)(0xC0 | encode));
1235 }
1236
1237
1238 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1239 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1240 prefix(src, dst);
1241 emit_int8(0x0F);
1242 emit_int8(0x40 | cc);
1243 emit_operand(dst, src);
1244 }
1245
1246 void Assembler::cmpb(Address dst, int imm8) {
1247 InstructionMark im(this);
1248 prefix(dst);
1249 emit_int8((unsigned char)0x80);
1250 emit_operand(rdi, dst, 1);
1251 emit_int8(imm8);
1252 }
1253
1254 void Assembler::cmpl(Address dst, int32_t imm32) {
1255 InstructionMark im(this);
1256 prefix(dst);
1257 emit_int8((unsigned char)0x81);
1258 emit_operand(rdi, dst, 4);
1259 emit_int32(imm32);
1260 }
1261
1262 void Assembler::cmpl(Register dst, int32_t imm32) {
1263 prefix(dst);
1264 emit_arith(0x81, 0xF8, dst, imm32);
1265 }
1266
1267 void Assembler::cmpl(Register dst, Register src) {
1268 (void) prefix_and_encode(dst->encoding(), src->encoding());
1269 emit_arith(0x3B, 0xC0, dst, src);
1270 }
1271
1272
1273 void Assembler::cmpl(Register dst, Address src) {
1274 InstructionMark im(this);
1275 prefix(src, dst);
1276 emit_int8((unsigned char)0x3B);
1277 emit_operand(dst, src);
1278 }
1279
1280 void Assembler::cmpw(Address dst, int imm16) {
1281 InstructionMark im(this);
1282 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1283 emit_int8(0x66);
1284 emit_int8((unsigned char)0x81);
1285 emit_operand(rdi, dst, 2);
1286 emit_int16(imm16);
1287 }
1288
1289 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1290 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1291 // The ZF is set if the compared values were equal, and cleared otherwise.
1292 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1293 InstructionMark im(this);
1294 prefix(adr, reg);
1295 emit_int8(0x0F);
1296 emit_int8((unsigned char)0xB1);
1297 emit_operand(reg, adr);
1298 }
1299
1300 void Assembler::comisd(XMMRegister dst, Address src) {
1301 // NOTE: dbx seems to decode this as comiss even though the
1302 // 0x66 is there. Strangly ucomisd comes out correct
1303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1304 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1305 }
1306
1307 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1309 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_66);
1310 }
1311
1312 void Assembler::comiss(XMMRegister dst, Address src) {
1313 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1314 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1315 }
1316
1317 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1318 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1319 emit_simd_arith_nonds(0x2F, dst, src, VEX_SIMD_NONE);
1320 }
1321
1322 void Assembler::cpuid() {
1323 emit_int8(0x0F);
1324 emit_int8((unsigned char)0xA2);
1325 }
1326
1327 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1329 emit_simd_arith_nonds(0xE6, dst, src, VEX_SIMD_F3);
1330 }
1331
1332 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1334 emit_simd_arith_nonds(0x5B, dst, src, VEX_SIMD_NONE);
1335 }
1336
1337 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1339 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1340 }
1341
1342 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1343 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1344 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F2);
1345 }
1346
1347 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2);
1350 emit_int8(0x2A);
1351 emit_int8((unsigned char)(0xC0 | encode));
1352 }
1353
1354 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1356 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1357 }
1358
1359 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1360 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1361 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3);
1362 emit_int8(0x2A);
1363 emit_int8((unsigned char)(0xC0 | encode));
1364 }
1365
1366 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1367 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1368 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3);
1369 }
1370
1371 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1373 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1374 }
1375
1376 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1377 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1378 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1379 }
1380
1381
1382 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1384 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2);
1385 emit_int8(0x2C);
1386 emit_int8((unsigned char)(0xC0 | encode));
1387 }
1388
1389 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1390 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1391 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F3);
1392 emit_int8(0x2C);
1393 emit_int8((unsigned char)(0xC0 | encode));
1394 }
1395
1396 void Assembler::decl(Address dst) {
1397 // Don't use it directly. Use MacroAssembler::decrement() instead.
1398 InstructionMark im(this);
1399 prefix(dst);
1400 emit_int8((unsigned char)0xFF);
1401 emit_operand(rcx, dst);
1402 }
1403
1404 void Assembler::divsd(XMMRegister dst, Address src) {
1405 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1406 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1407 }
1408
1409 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1411 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F2);
1412 }
1413
1414 void Assembler::divss(XMMRegister dst, Address src) {
1415 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1416 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1417 }
1418
1419 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1420 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1421 emit_simd_arith(0x5E, dst, src, VEX_SIMD_F3);
1422 }
1423
1424 void Assembler::emms() {
1425 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1426 emit_int8(0x0F);
1427 emit_int8(0x77);
1428 }
1429
1430 void Assembler::hlt() {
1431 emit_int8((unsigned char)0xF4);
1432 }
1433
1434 void Assembler::idivl(Register src) {
1435 int encode = prefix_and_encode(src->encoding());
1436 emit_int8((unsigned char)0xF7);
1437 emit_int8((unsigned char)(0xF8 | encode));
1438 }
1439
1440 void Assembler::divl(Register src) { // Unsigned
1441 int encode = prefix_and_encode(src->encoding());
1442 emit_int8((unsigned char)0xF7);
1443 emit_int8((unsigned char)(0xF0 | encode));
1444 }
1445
1446 void Assembler::imull(Register dst, Register src) {
1447 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1448 emit_int8(0x0F);
1449 emit_int8((unsigned char)0xAF);
1450 emit_int8((unsigned char)(0xC0 | encode));
1451 }
1452
1453
1454 void Assembler::imull(Register dst, Register src, int value) {
1455 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1456 if (is8bit(value)) {
1457 emit_int8(0x6B);
1458 emit_int8((unsigned char)(0xC0 | encode));
1459 emit_int8(value & 0xFF);
1460 } else {
1461 emit_int8(0x69);
1462 emit_int8((unsigned char)(0xC0 | encode));
1463 emit_int32(value);
1464 }
1465 }
1466
1467 void Assembler::imull(Register dst, Address src) {
1468 InstructionMark im(this);
1469 prefix(src, dst);
1470 emit_int8(0x0F);
1471 emit_int8((unsigned char) 0xAF);
1472 emit_operand(dst, src);
1473 }
1474
1475
1476 void Assembler::incl(Address dst) {
1477 // Don't use it directly. Use MacroAssembler::increment() instead.
1478 InstructionMark im(this);
1479 prefix(dst);
1480 emit_int8((unsigned char)0xFF);
1481 emit_operand(rax, dst);
1482 }
1483
1484 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1485 InstructionMark im(this);
1486 assert((0 <= cc) && (cc < 16), "illegal cc");
1487 if (L.is_bound()) {
1488 address dst = target(L);
1489 assert(dst != NULL, "jcc most probably wrong");
1490
1491 const int short_size = 2;
1492 const int long_size = 6;
1493 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1494 if (maybe_short && is8bit(offs - short_size)) {
1495 // 0111 tttn #8-bit disp
1496 emit_int8(0x70 | cc);
1497 emit_int8((offs - short_size) & 0xFF);
1498 } else {
1499 // 0000 1111 1000 tttn #32-bit disp
1500 assert(is_simm32(offs - long_size),
1501 "must be 32bit offset (call4)");
1502 emit_int8(0x0F);
1503 emit_int8((unsigned char)(0x80 | cc));
1504 emit_int32(offs - long_size);
1505 }
1506 } else {
1507 // Note: could eliminate cond. jumps to this jump if condition
1508 // is the same however, seems to be rather unlikely case.
1509 // Note: use jccb() if label to be bound is very close to get
1510 // an 8-bit displacement
1511 L.add_patch_at(code(), locator());
1512 emit_int8(0x0F);
1513 emit_int8((unsigned char)(0x80 | cc));
1514 emit_int32(0);
1515 }
1516 }
1517
1518 void Assembler::jccb(Condition cc, Label& L) {
1519 if (L.is_bound()) {
1520 const int short_size = 2;
1521 address entry = target(L);
1522 #ifdef ASSERT
1523 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1524 intptr_t delta = short_branch_delta();
1525 if (delta != 0) {
1526 dist += (dist < 0 ? (-delta) :delta);
1527 }
1528 assert(is8bit(dist), "Dispacement too large for a short jmp");
1529 #endif
1530 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1531 // 0111 tttn #8-bit disp
1532 emit_int8(0x70 | cc);
1533 emit_int8((offs - short_size) & 0xFF);
1534 } else {
1535 InstructionMark im(this);
1536 L.add_patch_at(code(), locator());
1537 emit_int8(0x70 | cc);
1538 emit_int8(0);
1539 }
1540 }
1541
1542 void Assembler::jmp(Address adr) {
1543 InstructionMark im(this);
1544 prefix(adr);
1545 emit_int8((unsigned char)0xFF);
1546 emit_operand(rsp, adr);
1547 }
1548
1549 void Assembler::jmp(Label& L, bool maybe_short) {
1550 if (L.is_bound()) {
1551 address entry = target(L);
1552 assert(entry != NULL, "jmp most probably wrong");
1553 InstructionMark im(this);
1554 const int short_size = 2;
1555 const int long_size = 5;
1556 intptr_t offs = entry - pc();
1557 if (maybe_short && is8bit(offs - short_size)) {
1558 emit_int8((unsigned char)0xEB);
1559 emit_int8((offs - short_size) & 0xFF);
1560 } else {
1561 emit_int8((unsigned char)0xE9);
1562 emit_int32(offs - long_size);
1563 }
1564 } else {
1565 // By default, forward jumps are always 32-bit displacements, since
1566 // we can't yet know where the label will be bound. If you're sure that
1567 // the forward jump will not run beyond 256 bytes, use jmpb to
1568 // force an 8-bit displacement.
1569 InstructionMark im(this);
1570 L.add_patch_at(code(), locator());
1571 emit_int8((unsigned char)0xE9);
1572 emit_int32(0);
1573 }
1574 }
1575
1576 void Assembler::jmp(Register entry) {
1577 int encode = prefix_and_encode(entry->encoding());
1578 emit_int8((unsigned char)0xFF);
1579 emit_int8((unsigned char)(0xE0 | encode));
1580 }
1581
1582 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
1583 InstructionMark im(this);
1584 emit_int8((unsigned char)0xE9);
1585 assert(dest != NULL, "must have a target");
1586 intptr_t disp = dest - (pc() + sizeof(int32_t));
1587 assert(is_simm32(disp), "must be 32bit offset (jmp)");
1588 emit_data(disp, rspec.reloc(), call32_operand);
1589 }
1590
1591 void Assembler::jmpb(Label& L) {
1592 if (L.is_bound()) {
1593 const int short_size = 2;
1594 address entry = target(L);
1595 assert(entry != NULL, "jmp most probably wrong");
1596 #ifdef ASSERT
1597 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1598 intptr_t delta = short_branch_delta();
1599 if (delta != 0) {
1600 dist += (dist < 0 ? (-delta) :delta);
1601 }
1602 assert(is8bit(dist), "Dispacement too large for a short jmp");
1603 #endif
1604 intptr_t offs = entry - pc();
1605 emit_int8((unsigned char)0xEB);
1606 emit_int8((offs - short_size) & 0xFF);
1607 } else {
1608 InstructionMark im(this);
1609 L.add_patch_at(code(), locator());
1610 emit_int8((unsigned char)0xEB);
1611 emit_int8(0);
1612 }
1613 }
1614
1615 void Assembler::ldmxcsr( Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 prefix(src);
1619 emit_int8(0x0F);
1620 emit_int8((unsigned char)0xAE);
1621 emit_operand(as_Register(2), src);
1622 }
1623
1624 void Assembler::leal(Register dst, Address src) {
1625 InstructionMark im(this);
1626 #ifdef _LP64
1627 emit_int8(0x67); // addr32
1628 prefix(src, dst);
1629 #endif // LP64
1630 emit_int8((unsigned char)0x8D);
1631 emit_operand(dst, src);
1632 }
1633
1634 void Assembler::lfence() {
1635 emit_int8(0x0F);
1636 emit_int8((unsigned char)0xAE);
1637 emit_int8((unsigned char)0xE8);
1638 }
1639
1640 void Assembler::lock() {
1641 emit_int8((unsigned char)0xF0);
1642 }
1643
1644 void Assembler::lzcntl(Register dst, Register src) {
1645 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
1646 emit_int8((unsigned char)0xF3);
1647 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1648 emit_int8(0x0F);
1649 emit_int8((unsigned char)0xBD);
1650 emit_int8((unsigned char)(0xC0 | encode));
1651 }
1652
1653 // Emit mfence instruction
1654 void Assembler::mfence() {
1655 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
1656 emit_int8(0x0F);
1657 emit_int8((unsigned char)0xAE);
1658 emit_int8((unsigned char)0xF0);
1659 }
1660
1661 void Assembler::mov(Register dst, Register src) {
1662 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
1663 }
1664
1665 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
1666 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1667 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_66);
1668 }
1669
1670 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
1671 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1672 emit_simd_arith_nonds(0x28, dst, src, VEX_SIMD_NONE);
1673 }
1674
1675 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
1676 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1677 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE);
1678 emit_int8(0x16);
1679 emit_int8((unsigned char)(0xC0 | encode));
1680 }
1681
1682 void Assembler::movb(Register dst, Address src) {
1683 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
1684 InstructionMark im(this);
1685 prefix(src, dst, true);
1686 emit_int8((unsigned char)0x8A);
1687 emit_operand(dst, src);
1688 }
1689
1690
1691 void Assembler::movb(Address dst, int imm8) {
1692 InstructionMark im(this);
1693 prefix(dst);
1694 emit_int8((unsigned char)0xC6);
1695 emit_operand(rax, dst, 1);
1696 emit_int8(imm8);
1697 }
1698
1699
1700 void Assembler::movb(Address dst, Register src) {
1701 assert(src->has_byte_register(), "must have byte register");
1702 InstructionMark im(this);
1703 prefix(dst, src, true);
1704 emit_int8((unsigned char)0x88);
1705 emit_operand(src, dst);
1706 }
1707
1708 void Assembler::movdl(XMMRegister dst, Register src) {
1709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1710 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_66);
1711 emit_int8(0x6E);
1712 emit_int8((unsigned char)(0xC0 | encode));
1713 }
1714
1715 void Assembler::movdl(Register dst, XMMRegister src) {
1716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1717 // swap src/dst to get correct prefix
1718 int encode = simd_prefix_and_encode(src, dst, VEX_SIMD_66);
1719 emit_int8(0x7E);
1720 emit_int8((unsigned char)(0xC0 | encode));
1721 }
1722
1723 void Assembler::movdl(XMMRegister dst, Address src) {
1724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1725 InstructionMark im(this);
1726 simd_prefix(dst, src, VEX_SIMD_66);
1727 emit_int8(0x6E);
1728 emit_operand(dst, src);
1729 }
1730
1731 void Assembler::movdl(Address dst, XMMRegister src) {
1732 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1733 InstructionMark im(this);
1734 simd_prefix(dst, src, VEX_SIMD_66);
1735 emit_int8(0x7E);
1736 emit_operand(src, dst);
1737 }
1738
1739 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1742 }
1743
1744 void Assembler::movdqa(XMMRegister dst, Address src) {
1745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1746 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_66);
1747 }
1748
1749 void Assembler::movdqu(XMMRegister dst, Address src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1752 }
1753
1754 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
1755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1756 emit_simd_arith_nonds(0x6F, dst, src, VEX_SIMD_F3);
1757 }
1758
1759 void Assembler::movdqu(Address dst, XMMRegister src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 simd_prefix(dst, src, VEX_SIMD_F3);
1763 emit_int8(0x7F);
1764 emit_operand(src, dst);
1765 }
1766
1767 // Move Unaligned 256bit Vector
1768 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
1769 assert(UseAVX > 0, "");
1770 bool vector256 = true;
1771 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1772 emit_int8(0x6F);
1773 emit_int8((unsigned char)(0xC0 | encode));
1774 }
1775
1776 void Assembler::vmovdqu(XMMRegister dst, Address src) {
1777 assert(UseAVX > 0, "");
1778 InstructionMark im(this);
1779 bool vector256 = true;
1780 vex_prefix(dst, xnoreg, src, VEX_SIMD_F3, vector256);
1781 emit_int8(0x6F);
1782 emit_operand(dst, src);
1783 }
1784
1785 void Assembler::vmovdqu(Address dst, XMMRegister src) {
1786 assert(UseAVX > 0, "");
1787 InstructionMark im(this);
1788 bool vector256 = true;
1789 // swap src<->dst for encoding
1790 assert(src != xnoreg, "sanity");
1791 vex_prefix(src, xnoreg, dst, VEX_SIMD_F3, vector256);
1792 emit_int8(0x7F);
1793 emit_operand(src, dst);
1794 }
1795
1796 // Uses zero extension on 64bit
1797
1798 void Assembler::movl(Register dst, int32_t imm32) {
1799 int encode = prefix_and_encode(dst->encoding());
1800 emit_int8((unsigned char)(0xB8 | encode));
1801 emit_int32(imm32);
1802 }
1803
1804 void Assembler::movl(Register dst, Register src) {
1805 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1806 emit_int8((unsigned char)0x8B);
1807 emit_int8((unsigned char)(0xC0 | encode));
1808 }
1809
1810 void Assembler::movl(Register dst, Address src) {
1811 InstructionMark im(this);
1812 prefix(src, dst);
1813 emit_int8((unsigned char)0x8B);
1814 emit_operand(dst, src);
1815 }
1816
1817 void Assembler::movl(Address dst, int32_t imm32) {
1818 InstructionMark im(this);
1819 prefix(dst);
1820 emit_int8((unsigned char)0xC7);
1821 emit_operand(rax, dst, 4);
1822 emit_int32(imm32);
1823 }
1824
1825 void Assembler::movl(Address dst, Register src) {
1826 InstructionMark im(this);
1827 prefix(dst, src);
1828 emit_int8((unsigned char)0x89);
1829 emit_operand(src, dst);
1830 }
1831
1832 // New cpus require to use movsd and movss to avoid partial register stall
1833 // when loading from memory. But for old Opteron use movlpd instead of movsd.
1834 // The selection is done in MacroAssembler::movdbl() and movflt().
1835 void Assembler::movlpd(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 emit_simd_arith(0x12, dst, src, VEX_SIMD_66);
1838 }
1839
1840 void Assembler::movq( MMXRegister dst, Address src ) {
1841 assert( VM_Version::supports_mmx(), "" );
1842 emit_int8(0x0F);
1843 emit_int8(0x6F);
1844 emit_operand(dst, src);
1845 }
1846
1847 void Assembler::movq( Address dst, MMXRegister src ) {
1848 assert( VM_Version::supports_mmx(), "" );
1849 emit_int8(0x0F);
1850 emit_int8(0x7F);
1851 // workaround gcc (3.2.1-7a) bug
1852 // In that version of gcc with only an emit_operand(MMX, Address)
1853 // gcc will tail jump and try and reverse the parameters completely
1854 // obliterating dst in the process. By having a version available
1855 // that doesn't need to swap the args at the tail jump the bug is
1856 // avoided.
1857 emit_operand(dst, src);
1858 }
1859
1860 void Assembler::movq(XMMRegister dst, Address src) {
1861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1862 InstructionMark im(this);
1863 simd_prefix(dst, src, VEX_SIMD_F3);
1864 emit_int8(0x7E);
1865 emit_operand(dst, src);
1866 }
1867
1868 void Assembler::movq(Address dst, XMMRegister src) {
1869 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1870 InstructionMark im(this);
1871 simd_prefix(dst, src, VEX_SIMD_66);
1872 emit_int8((unsigned char)0xD6);
1873 emit_operand(src, dst);
1874 }
1875
1876 void Assembler::movsbl(Register dst, Address src) { // movsxb
1877 InstructionMark im(this);
1878 prefix(src, dst);
1879 emit_int8(0x0F);
1880 emit_int8((unsigned char)0xBE);
1881 emit_operand(dst, src);
1882 }
1883
1884 void Assembler::movsbl(Register dst, Register src) { // movsxb
1885 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1886 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1887 emit_int8(0x0F);
1888 emit_int8((unsigned char)0xBE);
1889 emit_int8((unsigned char)(0xC0 | encode));
1890 }
1891
1892 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
1893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1894 emit_simd_arith(0x10, dst, src, VEX_SIMD_F2);
1895 }
1896
1897 void Assembler::movsd(XMMRegister dst, Address src) {
1898 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1899 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F2);
1900 }
1901
1902 void Assembler::movsd(Address dst, XMMRegister src) {
1903 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1904 InstructionMark im(this);
1905 simd_prefix(dst, src, VEX_SIMD_F2);
1906 emit_int8(0x11);
1907 emit_operand(src, dst);
1908 }
1909
1910 void Assembler::movss(XMMRegister dst, XMMRegister src) {
1911 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1912 emit_simd_arith(0x10, dst, src, VEX_SIMD_F3);
1913 }
1914
1915 void Assembler::movss(XMMRegister dst, Address src) {
1916 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1917 emit_simd_arith_nonds(0x10, dst, src, VEX_SIMD_F3);
1918 }
1919
1920 void Assembler::movss(Address dst, XMMRegister src) {
1921 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1922 InstructionMark im(this);
1923 simd_prefix(dst, src, VEX_SIMD_F3);
1924 emit_int8(0x11);
1925 emit_operand(src, dst);
1926 }
1927
1928 void Assembler::movswl(Register dst, Address src) { // movsxw
1929 InstructionMark im(this);
1930 prefix(src, dst);
1931 emit_int8(0x0F);
1932 emit_int8((unsigned char)0xBF);
1933 emit_operand(dst, src);
1934 }
1935
1936 void Assembler::movswl(Register dst, Register src) { // movsxw
1937 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1938 emit_int8(0x0F);
1939 emit_int8((unsigned char)0xBF);
1940 emit_int8((unsigned char)(0xC0 | encode));
1941 }
1942
1943 void Assembler::movw(Address dst, int imm16) {
1944 InstructionMark im(this);
1945
1946 emit_int8(0x66); // switch to 16-bit mode
1947 prefix(dst);
1948 emit_int8((unsigned char)0xC7);
1949 emit_operand(rax, dst, 2);
1950 emit_int16(imm16);
1951 }
1952
1953 void Assembler::movw(Register dst, Address src) {
1954 InstructionMark im(this);
1955 emit_int8(0x66);
1956 prefix(src, dst);
1957 emit_int8((unsigned char)0x8B);
1958 emit_operand(dst, src);
1959 }
1960
1961 void Assembler::movw(Address dst, Register src) {
1962 InstructionMark im(this);
1963 emit_int8(0x66);
1964 prefix(dst, src);
1965 emit_int8((unsigned char)0x89);
1966 emit_operand(src, dst);
1967 }
1968
1969 void Assembler::movzbl(Register dst, Address src) { // movzxb
1970 InstructionMark im(this);
1971 prefix(src, dst);
1972 emit_int8(0x0F);
1973 emit_int8((unsigned char)0xB6);
1974 emit_operand(dst, src);
1975 }
1976
1977 void Assembler::movzbl(Register dst, Register src) { // movzxb
1978 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
1979 int encode = prefix_and_encode(dst->encoding(), src->encoding(), true);
1980 emit_int8(0x0F);
1981 emit_int8((unsigned char)0xB6);
1982 emit_int8(0xC0 | encode);
1983 }
1984
1985 void Assembler::movzwl(Register dst, Address src) { // movzxw
1986 InstructionMark im(this);
1987 prefix(src, dst);
1988 emit_int8(0x0F);
1989 emit_int8((unsigned char)0xB7);
1990 emit_operand(dst, src);
1991 }
1992
1993 void Assembler::movzwl(Register dst, Register src) { // movzxw
1994 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1995 emit_int8(0x0F);
1996 emit_int8((unsigned char)0xB7);
1997 emit_int8(0xC0 | encode);
1998 }
1999
2000 void Assembler::mull(Address src) {
2001 InstructionMark im(this);
2002 prefix(src);
2003 emit_int8((unsigned char)0xF7);
2004 emit_operand(rsp, src);
2005 }
2006
2007 void Assembler::mull(Register src) {
2008 int encode = prefix_and_encode(src->encoding());
2009 emit_int8((unsigned char)0xF7);
2010 emit_int8((unsigned char)(0xE0 | encode));
2011 }
2012
2013 void Assembler::mulsd(XMMRegister dst, Address src) {
2014 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2015 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2016 }
2017
2018 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2020 emit_simd_arith(0x59, dst, src, VEX_SIMD_F2);
2021 }
2022
2023 void Assembler::mulss(XMMRegister dst, Address src) {
2024 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2025 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2026 }
2027
2028 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2029 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2030 emit_simd_arith(0x59, dst, src, VEX_SIMD_F3);
2031 }
2032
2033 void Assembler::negl(Register dst) {
2034 int encode = prefix_and_encode(dst->encoding());
2035 emit_int8((unsigned char)0xF7);
2036 emit_int8((unsigned char)(0xD8 | encode));
2037 }
2038
2039 void Assembler::nop(int i) {
2040 #ifdef ASSERT
2041 assert(i > 0, " ");
2042 // The fancy nops aren't currently recognized by debuggers making it a
2043 // pain to disassemble code while debugging. If asserts are on clearly
2044 // speed is not an issue so simply use the single byte traditional nop
2045 // to do alignment.
2046
2047 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2048 return;
2049
2050 #endif // ASSERT
2051
2052 if (UseAddressNop && VM_Version::is_intel()) {
2053 //
2054 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2055 // 1: 0x90
2056 // 2: 0x66 0x90
2057 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2058 // 4: 0x0F 0x1F 0x40 0x00
2059 // 5: 0x0F 0x1F 0x44 0x00 0x00
2060 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2061 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2062 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2063 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2064 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2065 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2066
2067 // The rest coding is Intel specific - don't use consecutive address nops
2068
2069 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2070 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2071 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2072 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2073
2074 while(i >= 15) {
2075 // For Intel don't generate consecutive addess nops (mix with regular nops)
2076 i -= 15;
2077 emit_int8(0x66); // size prefix
2078 emit_int8(0x66); // size prefix
2079 emit_int8(0x66); // size prefix
2080 addr_nop_8();
2081 emit_int8(0x66); // size prefix
2082 emit_int8(0x66); // size prefix
2083 emit_int8(0x66); // size prefix
2084 emit_int8((unsigned char)0x90);
2085 // nop
2086 }
2087 switch (i) {
2088 case 14:
2089 emit_int8(0x66); // size prefix
2090 case 13:
2091 emit_int8(0x66); // size prefix
2092 case 12:
2093 addr_nop_8();
2094 emit_int8(0x66); // size prefix
2095 emit_int8(0x66); // size prefix
2096 emit_int8(0x66); // size prefix
2097 emit_int8((unsigned char)0x90);
2098 // nop
2099 break;
2100 case 11:
2101 emit_int8(0x66); // size prefix
2102 case 10:
2103 emit_int8(0x66); // size prefix
2104 case 9:
2105 emit_int8(0x66); // size prefix
2106 case 8:
2107 addr_nop_8();
2108 break;
2109 case 7:
2110 addr_nop_7();
2111 break;
2112 case 6:
2113 emit_int8(0x66); // size prefix
2114 case 5:
2115 addr_nop_5();
2116 break;
2117 case 4:
2118 addr_nop_4();
2119 break;
2120 case 3:
2121 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2122 emit_int8(0x66); // size prefix
2123 case 2:
2124 emit_int8(0x66); // size prefix
2125 case 1:
2126 emit_int8((unsigned char)0x90);
2127 // nop
2128 break;
2129 default:
2130 assert(i == 0, " ");
2131 }
2132 return;
2133 }
2134 if (UseAddressNop && VM_Version::is_amd()) {
2135 //
2136 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2137 // 1: 0x90
2138 // 2: 0x66 0x90
2139 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2140 // 4: 0x0F 0x1F 0x40 0x00
2141 // 5: 0x0F 0x1F 0x44 0x00 0x00
2142 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2143 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2144 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2145 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2146 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2147 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2148
2149 // The rest coding is AMD specific - use consecutive address nops
2150
2151 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2152 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2153 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2154 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2155 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2156 // Size prefixes (0x66) are added for larger sizes
2157
2158 while(i >= 22) {
2159 i -= 11;
2160 emit_int8(0x66); // size prefix
2161 emit_int8(0x66); // size prefix
2162 emit_int8(0x66); // size prefix
2163 addr_nop_8();
2164 }
2165 // Generate first nop for size between 21-12
2166 switch (i) {
2167 case 21:
2168 i -= 1;
2169 emit_int8(0x66); // size prefix
2170 case 20:
2171 case 19:
2172 i -= 1;
2173 emit_int8(0x66); // size prefix
2174 case 18:
2175 case 17:
2176 i -= 1;
2177 emit_int8(0x66); // size prefix
2178 case 16:
2179 case 15:
2180 i -= 8;
2181 addr_nop_8();
2182 break;
2183 case 14:
2184 case 13:
2185 i -= 7;
2186 addr_nop_7();
2187 break;
2188 case 12:
2189 i -= 6;
2190 emit_int8(0x66); // size prefix
2191 addr_nop_5();
2192 break;
2193 default:
2194 assert(i < 12, " ");
2195 }
2196
2197 // Generate second nop for size between 11-1
2198 switch (i) {
2199 case 11:
2200 emit_int8(0x66); // size prefix
2201 case 10:
2202 emit_int8(0x66); // size prefix
2203 case 9:
2204 emit_int8(0x66); // size prefix
2205 case 8:
2206 addr_nop_8();
2207 break;
2208 case 7:
2209 addr_nop_7();
2210 break;
2211 case 6:
2212 emit_int8(0x66); // size prefix
2213 case 5:
2214 addr_nop_5();
2215 break;
2216 case 4:
2217 addr_nop_4();
2218 break;
2219 case 3:
2220 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2221 emit_int8(0x66); // size prefix
2222 case 2:
2223 emit_int8(0x66); // size prefix
2224 case 1:
2225 emit_int8((unsigned char)0x90);
2226 // nop
2227 break;
2228 default:
2229 assert(i == 0, " ");
2230 }
2231 return;
2232 }
2233
2234 // Using nops with size prefixes "0x66 0x90".
2235 // From AMD Optimization Guide:
2236 // 1: 0x90
2237 // 2: 0x66 0x90
2238 // 3: 0x66 0x66 0x90
2239 // 4: 0x66 0x66 0x66 0x90
2240 // 5: 0x66 0x66 0x90 0x66 0x90
2241 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2242 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2243 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2244 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2245 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2246 //
2247 while(i > 12) {
2248 i -= 4;
2249 emit_int8(0x66); // size prefix
2250 emit_int8(0x66);
2251 emit_int8(0x66);
2252 emit_int8((unsigned char)0x90);
2253 // nop
2254 }
2255 // 1 - 12 nops
2256 if(i > 8) {
2257 if(i > 9) {
2258 i -= 1;
2259 emit_int8(0x66);
2260 }
2261 i -= 3;
2262 emit_int8(0x66);
2263 emit_int8(0x66);
2264 emit_int8((unsigned char)0x90);
2265 }
2266 // 1 - 8 nops
2267 if(i > 4) {
2268 if(i > 6) {
2269 i -= 1;
2270 emit_int8(0x66);
2271 }
2272 i -= 3;
2273 emit_int8(0x66);
2274 emit_int8(0x66);
2275 emit_int8((unsigned char)0x90);
2276 }
2277 switch (i) {
2278 case 4:
2279 emit_int8(0x66);
2280 case 3:
2281 emit_int8(0x66);
2282 case 2:
2283 emit_int8(0x66);
2284 case 1:
2285 emit_int8((unsigned char)0x90);
2286 break;
2287 default:
2288 assert(i == 0, " ");
2289 }
2290 }
2291
2292 void Assembler::notl(Register dst) {
2293 int encode = prefix_and_encode(dst->encoding());
2294 emit_int8((unsigned char)0xF7);
2295 emit_int8((unsigned char)(0xD0 | encode));
2296 }
2297
2298 void Assembler::orl(Address dst, int32_t imm32) {
2299 InstructionMark im(this);
2300 prefix(dst);
2301 emit_arith_operand(0x81, rcx, dst, imm32);
2302 }
2303
2304 void Assembler::orl(Register dst, int32_t imm32) {
2305 prefix(dst);
2306 emit_arith(0x81, 0xC8, dst, imm32);
2307 }
2308
2309 void Assembler::orl(Register dst, Address src) {
2310 InstructionMark im(this);
2311 prefix(src, dst);
2312 emit_int8(0x0B);
2313 emit_operand(dst, src);
2314 }
2315
2316 void Assembler::orl(Register dst, Register src) {
2317 (void) prefix_and_encode(dst->encoding(), src->encoding());
2318 emit_arith(0x0B, 0xC0, dst, src);
2319 }
2320
2321 void Assembler::orl(Address dst, Register src) {
2322 InstructionMark im(this);
2323 prefix(dst, src);
2324 emit_int8(0x09);
2325 emit_operand(src, dst);
2326 }
2327
2328 void Assembler::packuswb(XMMRegister dst, Address src) {
2329 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2330 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2331 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2332 }
2333
2334 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2336 emit_simd_arith(0x67, dst, src, VEX_SIMD_66);
2337 }
2338
2339 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
2340 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
2341 emit_vex_arith(0x67, dst, nds, src, VEX_SIMD_66, vector256);
2342 }
2343
2344 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, bool vector256) {
2345 assert(VM_Version::supports_avx2(), "");
2346 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true, vector256);
2347 emit_int8(0x00);
2348 emit_int8(0xC0 | encode);
2349 emit_int8(imm8);
2350 }
2351
2352 void Assembler::pause() {
2353 emit_int8((unsigned char)0xF3);
2354 emit_int8((unsigned char)0x90);
2355 }
2356
2357 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2358 assert(VM_Version::supports_sse4_2(), "");
2359 InstructionMark im(this);
2360 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2361 emit_int8(0x61);
2362 emit_operand(dst, src);
2363 emit_int8(imm8);
2364 }
2365
2366 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2367 assert(VM_Version::supports_sse4_2(), "");
2368 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
2369 emit_int8(0x61);
2370 emit_int8((unsigned char)(0xC0 | encode));
2371 emit_int8(imm8);
2372 }
2373
2374 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
2375 assert(VM_Version::supports_sse4_1(), "");
2376 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2377 emit_int8(0x16);
2378 emit_int8((unsigned char)(0xC0 | encode));
2379 emit_int8(imm8);
2380 }
2381
2382 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
2383 assert(VM_Version::supports_sse4_1(), "");
2384 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2385 emit_int8(0x16);
2386 emit_int8((unsigned char)(0xC0 | encode));
2387 emit_int8(imm8);
2388 }
2389
2390 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
2391 assert(VM_Version::supports_sse4_1(), "");
2392 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, false);
2393 emit_int8(0x22);
2394 emit_int8((unsigned char)(0xC0 | encode));
2395 emit_int8(imm8);
2396 }
2397
2398 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
2399 assert(VM_Version::supports_sse4_1(), "");
2400 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, true);
2401 emit_int8(0x22);
2402 emit_int8((unsigned char)(0xC0 | encode));
2403 emit_int8(imm8);
2404 }
2405
2406 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
2407 assert(VM_Version::supports_sse4_1(), "");
2408 InstructionMark im(this);
2409 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2410 emit_int8(0x30);
2411 emit_operand(dst, src);
2412 }
2413
2414 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2415 assert(VM_Version::supports_sse4_1(), "");
2416 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2417 emit_int8(0x30);
2418 emit_int8((unsigned char)(0xC0 | encode));
2419 }
2420
2421 // generic
2422 void Assembler::pop(Register dst) {
2423 int encode = prefix_and_encode(dst->encoding());
2424 emit_int8(0x58 | encode);
2425 }
2426
2427 void Assembler::popcntl(Register dst, Address src) {
2428 assert(VM_Version::supports_popcnt(), "must support");
2429 InstructionMark im(this);
2430 emit_int8((unsigned char)0xF3);
2431 prefix(src, dst);
2432 emit_int8(0x0F);
2433 emit_int8((unsigned char)0xB8);
2434 emit_operand(dst, src);
2435 }
2436
2437 void Assembler::popcntl(Register dst, Register src) {
2438 assert(VM_Version::supports_popcnt(), "must support");
2439 emit_int8((unsigned char)0xF3);
2440 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2441 emit_int8(0x0F);
2442 emit_int8((unsigned char)0xB8);
2443 emit_int8((unsigned char)(0xC0 | encode));
2444 }
2445
2446 void Assembler::popf() {
2447 emit_int8((unsigned char)0x9D);
2448 }
2449
2450 #ifndef _LP64 // no 32bit push/pop on amd64
2451 void Assembler::popl(Address dst) {
2452 // NOTE: this will adjust stack by 8byte on 64bits
2453 InstructionMark im(this);
2454 prefix(dst);
2455 emit_int8((unsigned char)0x8F);
2456 emit_operand(rax, dst);
2457 }
2458 #endif
2459
2460 void Assembler::prefetch_prefix(Address src) {
2461 prefix(src);
2462 emit_int8(0x0F);
2463 }
2464
2465 void Assembler::prefetchnta(Address src) {
2466 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2467 InstructionMark im(this);
2468 prefetch_prefix(src);
2469 emit_int8(0x18);
2470 emit_operand(rax, src); // 0, src
2471 }
2472
2473 void Assembler::prefetchr(Address src) {
2474 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2475 InstructionMark im(this);
2476 prefetch_prefix(src);
2477 emit_int8(0x0D);
2478 emit_operand(rax, src); // 0, src
2479 }
2480
2481 void Assembler::prefetcht0(Address src) {
2482 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2483 InstructionMark im(this);
2484 prefetch_prefix(src);
2485 emit_int8(0x18);
2486 emit_operand(rcx, src); // 1, src
2487 }
2488
2489 void Assembler::prefetcht1(Address src) {
2490 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2491 InstructionMark im(this);
2492 prefetch_prefix(src);
2493 emit_int8(0x18);
2494 emit_operand(rdx, src); // 2, src
2495 }
2496
2497 void Assembler::prefetcht2(Address src) {
2498 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
2499 InstructionMark im(this);
2500 prefetch_prefix(src);
2501 emit_int8(0x18);
2502 emit_operand(rbx, src); // 3, src
2503 }
2504
2505 void Assembler::prefetchw(Address src) {
2506 assert(VM_Version::supports_3dnow_prefetch(), "must support");
2507 InstructionMark im(this);
2508 prefetch_prefix(src);
2509 emit_int8(0x0D);
2510 emit_operand(rcx, src); // 1, src
2511 }
2512
2513 void Assembler::prefix(Prefix p) {
2514 emit_int8(p);
2515 }
2516
2517 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
2518 assert(VM_Version::supports_ssse3(), "");
2519 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2520 emit_int8(0x00);
2521 emit_int8((unsigned char)(0xC0 | encode));
2522 }
2523
2524 void Assembler::pshufb(XMMRegister dst, Address src) {
2525 assert(VM_Version::supports_ssse3(), "");
2526 InstructionMark im(this);
2527 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2528 emit_int8(0x00);
2529 emit_operand(dst, src);
2530 }
2531
2532 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
2533 assert(isByte(mode), "invalid value");
2534 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2535 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_66);
2536 emit_int8(mode & 0xFF);
2537
2538 }
2539
2540 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
2541 assert(isByte(mode), "invalid value");
2542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2543 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2544 InstructionMark im(this);
2545 simd_prefix(dst, src, VEX_SIMD_66);
2546 emit_int8(0x70);
2547 emit_operand(dst, src);
2548 emit_int8(mode & 0xFF);
2549 }
2550
2551 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
2552 assert(isByte(mode), "invalid value");
2553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2554 emit_simd_arith_nonds(0x70, dst, src, VEX_SIMD_F2);
2555 emit_int8(mode & 0xFF);
2556 }
2557
2558 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
2559 assert(isByte(mode), "invalid value");
2560 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2561 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2562 InstructionMark im(this);
2563 simd_prefix(dst, src, VEX_SIMD_F2);
2564 emit_int8(0x70);
2565 emit_operand(dst, src);
2566 emit_int8(mode & 0xFF);
2567 }
2568
2569 void Assembler::psrldq(XMMRegister dst, int shift) {
2570 // Shift 128 bit value in xmm register by number of bytes.
2571 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2572 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66);
2573 emit_int8(0x73);
2574 emit_int8((unsigned char)(0xC0 | encode));
2575 emit_int8(shift);
2576 }
2577
2578 void Assembler::ptest(XMMRegister dst, Address src) {
2579 assert(VM_Version::supports_sse4_1(), "");
2580 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2581 InstructionMark im(this);
2582 simd_prefix(dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2583 emit_int8(0x17);
2584 emit_operand(dst, src);
2585 }
2586
2587 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2588 assert(VM_Version::supports_sse4_1(), "");
2589 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
2590 emit_int8(0x17);
2591 emit_int8((unsigned char)(0xC0 | encode));
2592 }
2593
2594 void Assembler::vptest(XMMRegister dst, Address src) {
2595 assert(VM_Version::supports_avx(), "");
2596 InstructionMark im(this);
2597 bool vector256 = true;
2598 assert(dst != xnoreg, "sanity");
2599 int dst_enc = dst->encoding();
2600 // swap src<->dst for encoding
2601 vex_prefix(src, 0, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
2602 emit_int8(0x17);
2603 emit_operand(dst, src);
2604 }
2605
2606 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
2607 assert(VM_Version::supports_avx(), "");
2608 bool vector256 = true;
2609 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
2610 emit_int8(0x17);
2611 emit_int8((unsigned char)(0xC0 | encode));
2612 }
2613
2614 void Assembler::punpcklbw(XMMRegister dst, Address src) {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2616 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2617 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2618 }
2619
2620 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
2621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2622 emit_simd_arith(0x60, dst, src, VEX_SIMD_66);
2623 }
2624
2625 void Assembler::punpckldq(XMMRegister dst, Address src) {
2626 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2627 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2628 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2629 }
2630
2631 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
2632 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2633 emit_simd_arith(0x62, dst, src, VEX_SIMD_66);
2634 }
2635
2636 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
2637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2638 emit_simd_arith(0x6C, dst, src, VEX_SIMD_66);
2639 }
2640
2641 void Assembler::push(int32_t imm32) {
2642 // in 64bits we push 64bits onto the stack but only
2643 // take a 32bit immediate
2644 emit_int8(0x68);
2645 emit_int32(imm32);
2646 }
2647
2648 void Assembler::push(Register src) {
2649 int encode = prefix_and_encode(src->encoding());
2650
2651 emit_int8(0x50 | encode);
2652 }
2653
2654 void Assembler::pushf() {
2655 emit_int8((unsigned char)0x9C);
2656 }
2657
2658 #ifndef _LP64 // no 32bit push/pop on amd64
2659 void Assembler::pushl(Address src) {
2660 // Note this will push 64bit on 64bit
2661 InstructionMark im(this);
2662 prefix(src);
2663 emit_int8((unsigned char)0xFF);
2664 emit_operand(rsi, src);
2665 }
2666 #endif
2667
2668 void Assembler::rcll(Register dst, int imm8) {
2669 assert(isShiftCount(imm8), "illegal shift count");
2670 int encode = prefix_and_encode(dst->encoding());
2671 if (imm8 == 1) {
2672 emit_int8((unsigned char)0xD1);
2673 emit_int8((unsigned char)(0xD0 | encode));
2674 } else {
2675 emit_int8((unsigned char)0xC1);
2676 emit_int8((unsigned char)0xD0 | encode);
2677 emit_int8(imm8);
2678 }
2679 }
2680
2681 void Assembler::rdtsc() {
2682 emit_int8((unsigned char)0x0F);
2683 emit_int8((unsigned char)0x31);
2684 }
2685
2686 // copies data from [esi] to [edi] using rcx pointer sized words
2687 // generic
2688 void Assembler::rep_mov() {
2689 emit_int8((unsigned char)0xF3);
2690 // MOVSQ
2691 LP64_ONLY(prefix(REX_W));
2692 emit_int8((unsigned char)0xA5);
2693 }
2694
2695 // sets rcx bytes with rax, value at [edi]
2696 void Assembler::rep_stosb() {
2697 emit_int8((unsigned char)0xF3); // REP
2698 LP64_ONLY(prefix(REX_W));
2699 emit_int8((unsigned char)0xAA); // STOSB
2700 }
2701
2702 // sets rcx pointer sized words with rax, value at [edi]
2703 // generic
2704 void Assembler::rep_stos() {
2705 emit_int8((unsigned char)0xF3); // REP
2706 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
2707 emit_int8((unsigned char)0xAB);
2708 }
2709
2710 // scans rcx pointer sized words at [edi] for occurance of rax,
2711 // generic
2712 void Assembler::repne_scan() { // repne_scan
2713 emit_int8((unsigned char)0xF2);
2714 // SCASQ
2715 LP64_ONLY(prefix(REX_W));
2716 emit_int8((unsigned char)0xAF);
2717 }
2718
2719 #ifdef _LP64
2720 // scans rcx 4 byte words at [edi] for occurance of rax,
2721 // generic
2722 void Assembler::repne_scanl() { // repne_scan
2723 emit_int8((unsigned char)0xF2);
2724 // SCASL
2725 emit_int8((unsigned char)0xAF);
2726 }
2727 #endif
2728
2729 void Assembler::ret(int imm16) {
2730 if (imm16 == 0) {
2731 emit_int8((unsigned char)0xC3);
2732 } else {
2733 emit_int8((unsigned char)0xC2);
2734 emit_int16(imm16);
2735 }
2736 }
2737
2738 void Assembler::sahf() {
2739 #ifdef _LP64
2740 // Not supported in 64bit mode
2741 ShouldNotReachHere();
2742 #endif
2743 emit_int8((unsigned char)0x9E);
2744 }
2745
2746 void Assembler::sarl(Register dst, int imm8) {
2747 int encode = prefix_and_encode(dst->encoding());
2748 assert(isShiftCount(imm8), "illegal shift count");
2749 if (imm8 == 1) {
2750 emit_int8((unsigned char)0xD1);
2751 emit_int8((unsigned char)(0xF8 | encode));
2752 } else {
2753 emit_int8((unsigned char)0xC1);
2754 emit_int8((unsigned char)(0xF8 | encode));
2755 emit_int8(imm8);
2756 }
2757 }
2758
2759 void Assembler::sarl(Register dst) {
2760 int encode = prefix_and_encode(dst->encoding());
2761 emit_int8((unsigned char)0xD3);
2762 emit_int8((unsigned char)(0xF8 | encode));
2763 }
2764
2765 void Assembler::sbbl(Address dst, int32_t imm32) {
2766 InstructionMark im(this);
2767 prefix(dst);
2768 emit_arith_operand(0x81, rbx, dst, imm32);
2769 }
2770
2771 void Assembler::sbbl(Register dst, int32_t imm32) {
2772 prefix(dst);
2773 emit_arith(0x81, 0xD8, dst, imm32);
2774 }
2775
2776
2777 void Assembler::sbbl(Register dst, Address src) {
2778 InstructionMark im(this);
2779 prefix(src, dst);
2780 emit_int8(0x1B);
2781 emit_operand(dst, src);
2782 }
2783
2784 void Assembler::sbbl(Register dst, Register src) {
2785 (void) prefix_and_encode(dst->encoding(), src->encoding());
2786 emit_arith(0x1B, 0xC0, dst, src);
2787 }
2788
2789 void Assembler::setb(Condition cc, Register dst) {
2790 assert(0 <= cc && cc < 16, "illegal cc");
2791 int encode = prefix_and_encode(dst->encoding(), true);
2792 emit_int8(0x0F);
2793 emit_int8((unsigned char)0x90 | cc);
2794 emit_int8((unsigned char)(0xC0 | encode));
2795 }
2796
2797 void Assembler::shll(Register dst, int imm8) {
2798 assert(isShiftCount(imm8), "illegal shift count");
2799 int encode = prefix_and_encode(dst->encoding());
2800 if (imm8 == 1 ) {
2801 emit_int8((unsigned char)0xD1);
2802 emit_int8((unsigned char)(0xE0 | encode));
2803 } else {
2804 emit_int8((unsigned char)0xC1);
2805 emit_int8((unsigned char)(0xE0 | encode));
2806 emit_int8(imm8);
2807 }
2808 }
2809
2810 void Assembler::shll(Register dst) {
2811 int encode = prefix_and_encode(dst->encoding());
2812 emit_int8((unsigned char)0xD3);
2813 emit_int8((unsigned char)(0xE0 | encode));
2814 }
2815
2816 void Assembler::shrl(Register dst, int imm8) {
2817 assert(isShiftCount(imm8), "illegal shift count");
2818 int encode = prefix_and_encode(dst->encoding());
2819 emit_int8((unsigned char)0xC1);
2820 emit_int8((unsigned char)(0xE8 | encode));
2821 emit_int8(imm8);
2822 }
2823
2824 void Assembler::shrl(Register dst) {
2825 int encode = prefix_and_encode(dst->encoding());
2826 emit_int8((unsigned char)0xD3);
2827 emit_int8((unsigned char)(0xE8 | encode));
2828 }
2829
2830 // copies a single word from [esi] to [edi]
2831 void Assembler::smovl() {
2832 emit_int8((unsigned char)0xA5);
2833 }
2834
2835 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2837 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2838 }
2839
2840 void Assembler::sqrtsd(XMMRegister dst, Address src) {
2841 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2842 emit_simd_arith(0x51, dst, src, VEX_SIMD_F2);
2843 }
2844
2845 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
2846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2847 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2848 }
2849
2850 void Assembler::std() {
2851 emit_int8((unsigned char)0xFD);
2852 }
2853
2854 void Assembler::sqrtss(XMMRegister dst, Address src) {
2855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2856 emit_simd_arith(0x51, dst, src, VEX_SIMD_F3);
2857 }
2858
2859 void Assembler::stmxcsr( Address dst) {
2860 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2861 InstructionMark im(this);
2862 prefix(dst);
2863 emit_int8(0x0F);
2864 emit_int8((unsigned char)0xAE);
2865 emit_operand(as_Register(3), dst);
2866 }
2867
2868 void Assembler::subl(Address dst, int32_t imm32) {
2869 InstructionMark im(this);
2870 prefix(dst);
2871 emit_arith_operand(0x81, rbp, dst, imm32);
2872 }
2873
2874 void Assembler::subl(Address dst, Register src) {
2875 InstructionMark im(this);
2876 prefix(dst, src);
2877 emit_int8(0x29);
2878 emit_operand(src, dst);
2879 }
2880
2881 void Assembler::subl(Register dst, int32_t imm32) {
2882 prefix(dst);
2883 emit_arith(0x81, 0xE8, dst, imm32);
2884 }
2885
2886 // Force generation of a 4 byte immediate value even if it fits into 8bit
2887 void Assembler::subl_imm32(Register dst, int32_t imm32) {
2888 prefix(dst);
2889 emit_arith_imm32(0x81, 0xE8, dst, imm32);
2890 }
2891
2892 void Assembler::subl(Register dst, Address src) {
2893 InstructionMark im(this);
2894 prefix(src, dst);
2895 emit_int8(0x2B);
2896 emit_operand(dst, src);
2897 }
2898
2899 void Assembler::subl(Register dst, Register src) {
2900 (void) prefix_and_encode(dst->encoding(), src->encoding());
2901 emit_arith(0x2B, 0xC0, dst, src);
2902 }
2903
2904 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2905 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2906 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2907 }
2908
2909 void Assembler::subsd(XMMRegister dst, Address src) {
2910 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2911 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F2);
2912 }
2913
2914 void Assembler::subss(XMMRegister dst, XMMRegister src) {
2915 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2916 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2917 }
2918
2919 void Assembler::subss(XMMRegister dst, Address src) {
2920 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2921 emit_simd_arith(0x5C, dst, src, VEX_SIMD_F3);
2922 }
2923
2924 void Assembler::testb(Register dst, int imm8) {
2925 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2926 (void) prefix_and_encode(dst->encoding(), true);
2927 emit_arith_b(0xF6, 0xC0, dst, imm8);
2928 }
2929
2930 void Assembler::testl(Register dst, int32_t imm32) {
2931 // not using emit_arith because test
2932 // doesn't support sign-extension of
2933 // 8bit operands
2934 int encode = dst->encoding();
2935 if (encode == 0) {
2936 emit_int8((unsigned char)0xA9);
2937 } else {
2938 encode = prefix_and_encode(encode);
2939 emit_int8((unsigned char)0xF7);
2940 emit_int8((unsigned char)(0xC0 | encode));
2941 }
2942 emit_int32(imm32);
2943 }
2944
2945 void Assembler::testl(Register dst, Register src) {
2946 (void) prefix_and_encode(dst->encoding(), src->encoding());
2947 emit_arith(0x85, 0xC0, dst, src);
2948 }
2949
2950 void Assembler::testl(Register dst, Address src) {
2951 InstructionMark im(this);
2952 prefix(src, dst);
2953 emit_int8((unsigned char)0x85);
2954 emit_operand(dst, src);
2955 }
2956
2957 void Assembler::tzcntl(Register dst, Register src) {
2958 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2959 emit_int8((unsigned char)0xF3);
2960 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2961 emit_int8(0x0F);
2962 emit_int8((unsigned char)0xBC);
2963 emit_int8((unsigned char)0xC0 | encode);
2964 }
2965
2966 void Assembler::tzcntq(Register dst, Register src) {
2967 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
2968 emit_int8((unsigned char)0xF3);
2969 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
2970 emit_int8(0x0F);
2971 emit_int8((unsigned char)0xBC);
2972 emit_int8((unsigned char)(0xC0 | encode));
2973 }
2974
2975 void Assembler::ucomisd(XMMRegister dst, Address src) {
2976 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2977 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2978 }
2979
2980 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2982 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_66);
2983 }
2984
2985 void Assembler::ucomiss(XMMRegister dst, Address src) {
2986 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2987 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2988 }
2989
2990 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
2991 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2992 emit_simd_arith_nonds(0x2E, dst, src, VEX_SIMD_NONE);
2993 }
2994
2995 void Assembler::xabort(int8_t imm8) {
2996 emit_int8((unsigned char)0xC6);
2997 emit_int8((unsigned char)0xF8);
2998 emit_int8((unsigned char)(imm8 & 0xFF));
2999 }
3000
3001 void Assembler::xaddl(Address dst, Register src) {
3002 InstructionMark im(this);
3003 prefix(dst, src);
3004 emit_int8(0x0F);
3005 emit_int8((unsigned char)0xC1);
3006 emit_operand(src, dst);
3007 }
3008
3009 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3010 InstructionMark im(this);
3011 relocate(rtype);
3012 if (abort.is_bound()) {
3013 address entry = target(abort);
3014 assert(entry != NULL, "abort entry NULL");
3015 intptr_t offset = entry - pc();
3016 emit_int8((unsigned char)0xC7);
3017 emit_int8((unsigned char)0xF8);
3018 emit_int32(offset - 6); // 2 opcode + 4 address
3019 } else {
3020 abort.add_patch_at(code(), locator());
3021 emit_int8((unsigned char)0xC7);
3022 emit_int8((unsigned char)0xF8);
3023 emit_int32(0);
3024 }
3025 }
3026
3027 void Assembler::xchgl(Register dst, Address src) { // xchg
3028 InstructionMark im(this);
3029 prefix(src, dst);
3030 emit_int8((unsigned char)0x87);
3031 emit_operand(dst, src);
3032 }
3033
3034 void Assembler::xchgl(Register dst, Register src) {
3035 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3036 emit_int8((unsigned char)0x87);
3037 emit_int8((unsigned char)(0xC0 | encode));
3038 }
3039
3040 void Assembler::xend() {
3041 emit_int8((unsigned char)0x0F);
3042 emit_int8((unsigned char)0x01);
3043 emit_int8((unsigned char)0xD5);
3044 }
3045
3046 void Assembler::xgetbv() {
3047 emit_int8(0x0F);
3048 emit_int8(0x01);
3049 emit_int8((unsigned char)0xD0);
3050 }
3051
3052 void Assembler::xorl(Register dst, int32_t imm32) {
3053 prefix(dst);
3054 emit_arith(0x81, 0xF0, dst, imm32);
3055 }
3056
3057 void Assembler::xorl(Register dst, Address src) {
3058 InstructionMark im(this);
3059 prefix(src, dst);
3060 emit_int8(0x33);
3061 emit_operand(dst, src);
3062 }
3063
3064 void Assembler::xorl(Register dst, Register src) {
3065 (void) prefix_and_encode(dst->encoding(), src->encoding());
3066 emit_arith(0x33, 0xC0, dst, src);
3067 }
3068
3069
3070 // AVX 3-operands scalar float-point arithmetic instructions
3071
3072 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3073 assert(VM_Version::supports_avx(), "");
3074 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3075 }
3076
3077 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3078 assert(VM_Version::supports_avx(), "");
3079 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3080 }
3081
3082 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3083 assert(VM_Version::supports_avx(), "");
3084 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3085 }
3086
3087 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3088 assert(VM_Version::supports_avx(), "");
3089 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3090 }
3091
3092 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3093 assert(VM_Version::supports_avx(), "");
3094 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3095 }
3096
3097 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3098 assert(VM_Version::supports_avx(), "");
3099 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3100 }
3101
3102 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3103 assert(VM_Version::supports_avx(), "");
3104 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3105 }
3106
3107 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3108 assert(VM_Version::supports_avx(), "");
3109 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3110 }
3111
3112 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
3113 assert(VM_Version::supports_avx(), "");
3114 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3115 }
3116
3117 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3118 assert(VM_Version::supports_avx(), "");
3119 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3120 }
3121
3122 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
3123 assert(VM_Version::supports_avx(), "");
3124 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3125 }
3126
3127 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3128 assert(VM_Version::supports_avx(), "");
3129 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3130 }
3131
3132 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
3133 assert(VM_Version::supports_avx(), "");
3134 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3135 }
3136
3137 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3138 assert(VM_Version::supports_avx(), "");
3139 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F2, /* vector256 */ false);
3140 }
3141
3142 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
3143 assert(VM_Version::supports_avx(), "");
3144 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3145 }
3146
3147 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3148 assert(VM_Version::supports_avx(), "");
3149 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_F3, /* vector256 */ false);
3150 }
3151
3152 //====================VECTOR ARITHMETIC=====================================
3153
3154 // Float-point vector arithmetic
3155
3156 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
3157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3158 emit_simd_arith(0x58, dst, src, VEX_SIMD_66);
3159 }
3160
3161 void Assembler::addps(XMMRegister dst, XMMRegister src) {
3162 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3163 emit_simd_arith(0x58, dst, src, VEX_SIMD_NONE);
3164 }
3165
3166 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3167 assert(VM_Version::supports_avx(), "");
3168 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3169 }
3170
3171 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3172 assert(VM_Version::supports_avx(), "");
3173 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3174 }
3175
3176 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3177 assert(VM_Version::supports_avx(), "");
3178 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_66, vector256);
3179 }
3180
3181 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3182 assert(VM_Version::supports_avx(), "");
3183 emit_vex_arith(0x58, dst, nds, src, VEX_SIMD_NONE, vector256);
3184 }
3185
3186 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
3187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3188 emit_simd_arith(0x5C, dst, src, VEX_SIMD_66);
3189 }
3190
3191 void Assembler::subps(XMMRegister dst, XMMRegister src) {
3192 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3193 emit_simd_arith(0x5C, dst, src, VEX_SIMD_NONE);
3194 }
3195
3196 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3197 assert(VM_Version::supports_avx(), "");
3198 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3199 }
3200
3201 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3202 assert(VM_Version::supports_avx(), "");
3203 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3204 }
3205
3206 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3207 assert(VM_Version::supports_avx(), "");
3208 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_66, vector256);
3209 }
3210
3211 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3212 assert(VM_Version::supports_avx(), "");
3213 emit_vex_arith(0x5C, dst, nds, src, VEX_SIMD_NONE, vector256);
3214 }
3215
3216 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
3217 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3218 emit_simd_arith(0x59, dst, src, VEX_SIMD_66);
3219 }
3220
3221 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
3222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3223 emit_simd_arith(0x59, dst, src, VEX_SIMD_NONE);
3224 }
3225
3226 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3227 assert(VM_Version::supports_avx(), "");
3228 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3229 }
3230
3231 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3232 assert(VM_Version::supports_avx(), "");
3233 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3234 }
3235
3236 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3237 assert(VM_Version::supports_avx(), "");
3238 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_66, vector256);
3239 }
3240
3241 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3242 assert(VM_Version::supports_avx(), "");
3243 emit_vex_arith(0x59, dst, nds, src, VEX_SIMD_NONE, vector256);
3244 }
3245
3246 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
3247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3248 emit_simd_arith(0x5E, dst, src, VEX_SIMD_66);
3249 }
3250
3251 void Assembler::divps(XMMRegister dst, XMMRegister src) {
3252 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3253 emit_simd_arith(0x5E, dst, src, VEX_SIMD_NONE);
3254 }
3255
3256 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3257 assert(VM_Version::supports_avx(), "");
3258 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3259 }
3260
3261 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3262 assert(VM_Version::supports_avx(), "");
3263 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3264 }
3265
3266 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3267 assert(VM_Version::supports_avx(), "");
3268 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_66, vector256);
3269 }
3270
3271 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3272 assert(VM_Version::supports_avx(), "");
3273 emit_vex_arith(0x5E, dst, nds, src, VEX_SIMD_NONE, vector256);
3274 }
3275
3276 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
3277 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3278 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3279 }
3280
3281 void Assembler::andps(XMMRegister dst, XMMRegister src) {
3282 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3283 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3284 }
3285
3286 void Assembler::andps(XMMRegister dst, Address src) {
3287 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3288 emit_simd_arith(0x54, dst, src, VEX_SIMD_NONE);
3289 }
3290
3291 void Assembler::andpd(XMMRegister dst, Address src) {
3292 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3293 emit_simd_arith(0x54, dst, src, VEX_SIMD_66);
3294 }
3295
3296 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3297 assert(VM_Version::supports_avx(), "");
3298 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3299 }
3300
3301 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3302 assert(VM_Version::supports_avx(), "");
3303 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3304 }
3305
3306 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3307 assert(VM_Version::supports_avx(), "");
3308 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_66, vector256);
3309 }
3310
3311 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3312 assert(VM_Version::supports_avx(), "");
3313 emit_vex_arith(0x54, dst, nds, src, VEX_SIMD_NONE, vector256);
3314 }
3315
3316 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
3317 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3318 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3319 }
3320
3321 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
3322 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3323 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3324 }
3325
3326 void Assembler::xorpd(XMMRegister dst, Address src) {
3327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3328 emit_simd_arith(0x57, dst, src, VEX_SIMD_66);
3329 }
3330
3331 void Assembler::xorps(XMMRegister dst, Address src) {
3332 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3333 emit_simd_arith(0x57, dst, src, VEX_SIMD_NONE);
3334 }
3335
3336 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3337 assert(VM_Version::supports_avx(), "");
3338 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3339 }
3340
3341 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3342 assert(VM_Version::supports_avx(), "");
3343 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3344 }
3345
3346 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3347 assert(VM_Version::supports_avx(), "");
3348 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_66, vector256);
3349 }
3350
3351 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3352 assert(VM_Version::supports_avx(), "");
3353 emit_vex_arith(0x57, dst, nds, src, VEX_SIMD_NONE, vector256);
3354 }
3355
3356
3357 // Integer vector arithmetic
3358 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
3359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3360 emit_simd_arith(0xFC, dst, src, VEX_SIMD_66);
3361 }
3362
3363 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
3364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3365 emit_simd_arith(0xFD, dst, src, VEX_SIMD_66);
3366 }
3367
3368 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
3369 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3370 emit_simd_arith(0xFE, dst, src, VEX_SIMD_66);
3371 }
3372
3373 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
3374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3375 emit_simd_arith(0xD4, dst, src, VEX_SIMD_66);
3376 }
3377
3378 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3379 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3380 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3381 }
3382
3383 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3384 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3385 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3386 }
3387
3388 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3389 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3390 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3391 }
3392
3393 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3394 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3395 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3396 }
3397
3398 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3399 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3400 emit_vex_arith(0xFC, dst, nds, src, VEX_SIMD_66, vector256);
3401 }
3402
3403 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3404 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3405 emit_vex_arith(0xFD, dst, nds, src, VEX_SIMD_66, vector256);
3406 }
3407
3408 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3409 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3410 emit_vex_arith(0xFE, dst, nds, src, VEX_SIMD_66, vector256);
3411 }
3412
3413 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3414 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3415 emit_vex_arith(0xD4, dst, nds, src, VEX_SIMD_66, vector256);
3416 }
3417
3418 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
3419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3420 emit_simd_arith(0xF8, dst, src, VEX_SIMD_66);
3421 }
3422
3423 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
3424 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3425 emit_simd_arith(0xF9, dst, src, VEX_SIMD_66);
3426 }
3427
3428 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
3429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3430 emit_simd_arith(0xFA, dst, src, VEX_SIMD_66);
3431 }
3432
3433 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
3434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3435 emit_simd_arith(0xFB, dst, src, VEX_SIMD_66);
3436 }
3437
3438 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3439 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3440 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3441 }
3442
3443 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3444 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3445 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3446 }
3447
3448 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3449 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3450 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3451 }
3452
3453 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3454 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3455 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3456 }
3457
3458 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3459 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3460 emit_vex_arith(0xF8, dst, nds, src, VEX_SIMD_66, vector256);
3461 }
3462
3463 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3464 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3465 emit_vex_arith(0xF9, dst, nds, src, VEX_SIMD_66, vector256);
3466 }
3467
3468 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3469 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3470 emit_vex_arith(0xFA, dst, nds, src, VEX_SIMD_66, vector256);
3471 }
3472
3473 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3474 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3475 emit_vex_arith(0xFB, dst, nds, src, VEX_SIMD_66, vector256);
3476 }
3477
3478 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
3479 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3480 emit_simd_arith(0xD5, dst, src, VEX_SIMD_66);
3481 }
3482
3483 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
3484 assert(VM_Version::supports_sse4_1(), "");
3485 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38);
3486 emit_int8(0x40);
3487 emit_int8((unsigned char)(0xC0 | encode));
3488 }
3489
3490 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3491 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3492 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3493 }
3494
3495 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3496 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3497 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3498 emit_int8(0x40);
3499 emit_int8((unsigned char)(0xC0 | encode));
3500 }
3501
3502 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3503 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3504 emit_vex_arith(0xD5, dst, nds, src, VEX_SIMD_66, vector256);
3505 }
3506
3507 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3508 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3509 InstructionMark im(this);
3510 int dst_enc = dst->encoding();
3511 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3512 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, false, vector256);
3513 emit_int8(0x40);
3514 emit_operand(dst, src);
3515 }
3516
3517 // Shift packed integers left by specified number of bits.
3518 void Assembler::psllw(XMMRegister dst, int shift) {
3519 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3520 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3521 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3522 emit_int8(0x71);
3523 emit_int8((unsigned char)(0xC0 | encode));
3524 emit_int8(shift & 0xFF);
3525 }
3526
3527 void Assembler::pslld(XMMRegister dst, int shift) {
3528 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3529 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3530 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3531 emit_int8(0x72);
3532 emit_int8((unsigned char)(0xC0 | encode));
3533 emit_int8(shift & 0xFF);
3534 }
3535
3536 void Assembler::psllq(XMMRegister dst, int shift) {
3537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3538 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3539 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66);
3540 emit_int8(0x73);
3541 emit_int8((unsigned char)(0xC0 | encode));
3542 emit_int8(shift & 0xFF);
3543 }
3544
3545 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
3546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3547 emit_simd_arith(0xF1, dst, shift, VEX_SIMD_66);
3548 }
3549
3550 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
3551 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3552 emit_simd_arith(0xF2, dst, shift, VEX_SIMD_66);
3553 }
3554
3555 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
3556 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3557 emit_simd_arith(0xF3, dst, shift, VEX_SIMD_66);
3558 }
3559
3560 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3561 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3562 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
3563 emit_vex_arith(0x71, xmm6, dst, src, VEX_SIMD_66, vector256);
3564 emit_int8(shift & 0xFF);
3565 }
3566
3567 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3568 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3569 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
3570 emit_vex_arith(0x72, xmm6, dst, src, VEX_SIMD_66, vector256);
3571 emit_int8(shift & 0xFF);
3572 }
3573
3574 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3575 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3576 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
3577 emit_vex_arith(0x73, xmm6, dst, src, VEX_SIMD_66, vector256);
3578 emit_int8(shift & 0xFF);
3579 }
3580
3581 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3582 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3583 emit_vex_arith(0xF1, dst, src, shift, VEX_SIMD_66, vector256);
3584 }
3585
3586 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3587 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3588 emit_vex_arith(0xF2, dst, src, shift, VEX_SIMD_66, vector256);
3589 }
3590
3591 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3592 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3593 emit_vex_arith(0xF3, dst, src, shift, VEX_SIMD_66, vector256);
3594 }
3595
3596 // Shift packed integers logically right by specified number of bits.
3597 void Assembler::psrlw(XMMRegister dst, int shift) {
3598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3599 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
3600 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3601 emit_int8(0x71);
3602 emit_int8((unsigned char)(0xC0 | encode));
3603 emit_int8(shift & 0xFF);
3604 }
3605
3606 void Assembler::psrld(XMMRegister dst, int shift) {
3607 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3608 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
3609 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3610 emit_int8(0x72);
3611 emit_int8((unsigned char)(0xC0 | encode));
3612 emit_int8(shift & 0xFF);
3613 }
3614
3615 void Assembler::psrlq(XMMRegister dst, int shift) {
3616 // Do not confuse it with psrldq SSE2 instruction which
3617 // shifts 128 bit value in xmm register by number of bytes.
3618 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3619 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3620 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66);
3621 emit_int8(0x73);
3622 emit_int8((unsigned char)(0xC0 | encode));
3623 emit_int8(shift & 0xFF);
3624 }
3625
3626 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
3627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3628 emit_simd_arith(0xD1, dst, shift, VEX_SIMD_66);
3629 }
3630
3631 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
3632 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3633 emit_simd_arith(0xD2, dst, shift, VEX_SIMD_66);
3634 }
3635
3636 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
3637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3638 emit_simd_arith(0xD3, dst, shift, VEX_SIMD_66);
3639 }
3640
3641 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3642 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3643 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3644 emit_vex_arith(0x71, xmm2, dst, src, VEX_SIMD_66, vector256);
3645 emit_int8(shift & 0xFF);
3646 }
3647
3648 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3649 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3650 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3651 emit_vex_arith(0x72, xmm2, dst, src, VEX_SIMD_66, vector256);
3652 emit_int8(shift & 0xFF);
3653 }
3654
3655 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3656 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3657 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
3658 emit_vex_arith(0x73, xmm2, dst, src, VEX_SIMD_66, vector256);
3659 emit_int8(shift & 0xFF);
3660 }
3661
3662 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3663 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3664 emit_vex_arith(0xD1, dst, src, shift, VEX_SIMD_66, vector256);
3665 }
3666
3667 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3668 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3669 emit_vex_arith(0xD2, dst, src, shift, VEX_SIMD_66, vector256);
3670 }
3671
3672 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3673 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3674 emit_vex_arith(0xD3, dst, src, shift, VEX_SIMD_66, vector256);
3675 }
3676
3677 // Shift packed integers arithmetically right by specified number of bits.
3678 void Assembler::psraw(XMMRegister dst, int shift) {
3679 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3680 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3681 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3682 emit_int8(0x71);
3683 emit_int8((unsigned char)(0xC0 | encode));
3684 emit_int8(shift & 0xFF);
3685 }
3686
3687 void Assembler::psrad(XMMRegister dst, int shift) {
3688 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3689 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
3690 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66);
3691 emit_int8(0x72);
3692 emit_int8((unsigned char)(0xC0 | encode));
3693 emit_int8(shift & 0xFF);
3694 }
3695
3696 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
3697 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3698 emit_simd_arith(0xE1, dst, shift, VEX_SIMD_66);
3699 }
3700
3701 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
3702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3703 emit_simd_arith(0xE2, dst, shift, VEX_SIMD_66);
3704 }
3705
3706 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3707 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3708 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3709 emit_vex_arith(0x71, xmm4, dst, src, VEX_SIMD_66, vector256);
3710 emit_int8(shift & 0xFF);
3711 }
3712
3713 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, bool vector256) {
3714 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3715 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
3716 emit_vex_arith(0x72, xmm4, dst, src, VEX_SIMD_66, vector256);
3717 emit_int8(shift & 0xFF);
3718 }
3719
3720 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3721 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3722 emit_vex_arith(0xE1, dst, src, shift, VEX_SIMD_66, vector256);
3723 }
3724
3725 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, bool vector256) {
3726 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3727 emit_vex_arith(0xE2, dst, src, shift, VEX_SIMD_66, vector256);
3728 }
3729
3730
3731 // AND packed integers
3732 void Assembler::pand(XMMRegister dst, XMMRegister src) {
3733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3734 emit_simd_arith(0xDB, dst, src, VEX_SIMD_66);
3735 }
3736
3737 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3738 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3739 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3740 }
3741
3742 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3743 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3744 emit_vex_arith(0xDB, dst, nds, src, VEX_SIMD_66, vector256);
3745 }
3746
3747 void Assembler::por(XMMRegister dst, XMMRegister src) {
3748 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3749 emit_simd_arith(0xEB, dst, src, VEX_SIMD_66);
3750 }
3751
3752 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3753 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3754 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3755 }
3756
3757 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3758 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3759 emit_vex_arith(0xEB, dst, nds, src, VEX_SIMD_66, vector256);
3760 }
3761
3762 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
3763 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3764 emit_simd_arith(0xEF, dst, src, VEX_SIMD_66);
3765 }
3766
3767 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
3768 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3769 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3770 }
3771
3772 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
3773 assert(VM_Version::supports_avx() && !vector256 || VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
3774 emit_vex_arith(0xEF, dst, nds, src, VEX_SIMD_66, vector256);
3775 }
3776
3777
3778 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3779 assert(VM_Version::supports_avx(), "");
3780 bool vector256 = true;
3781 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3782 emit_int8(0x18);
3783 emit_int8((unsigned char)(0xC0 | encode));
3784 // 0x00 - insert into lower 128 bits
3785 // 0x01 - insert into upper 128 bits
3786 emit_int8(0x01);
3787 }
3788
3789 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
3790 assert(VM_Version::supports_avx(), "");
3791 InstructionMark im(this);
3792 bool vector256 = true;
3793 assert(dst != xnoreg, "sanity");
3794 int dst_enc = dst->encoding();
3795 // swap src<->dst for encoding
3796 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3797 emit_int8(0x18);
3798 emit_operand(dst, src);
3799 // 0x01 - insert into upper 128 bits
3800 emit_int8(0x01);
3801 }
3802
3803 void Assembler::vextractf128h(Address dst, XMMRegister src) {
3804 assert(VM_Version::supports_avx(), "");
3805 InstructionMark im(this);
3806 bool vector256 = true;
3807 assert(src != xnoreg, "sanity");
3808 int src_enc = src->encoding();
3809 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3810 emit_int8(0x19);
3811 emit_operand(src, dst);
3812 // 0x01 - extract from upper 128 bits
3813 emit_int8(0x01);
3814 }
3815
3816 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3817 assert(VM_Version::supports_avx2(), "");
3818 bool vector256 = true;
3819 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3820 emit_int8(0x38);
3821 emit_int8((unsigned char)(0xC0 | encode));
3822 // 0x00 - insert into lower 128 bits
3823 // 0x01 - insert into upper 128 bits
3824 emit_int8(0x01);
3825 }
3826
3827 void Assembler::vinserti128h(XMMRegister dst, Address src) {
3828 assert(VM_Version::supports_avx2(), "");
3829 InstructionMark im(this);
3830 bool vector256 = true;
3831 assert(dst != xnoreg, "sanity");
3832 int dst_enc = dst->encoding();
3833 // swap src<->dst for encoding
3834 vex_prefix(src, dst_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3835 emit_int8(0x38);
3836 emit_operand(dst, src);
3837 // 0x01 - insert into upper 128 bits
3838 emit_int8(0x01);
3839 }
3840
3841 void Assembler::vextracti128h(Address dst, XMMRegister src) {
3842 assert(VM_Version::supports_avx2(), "");
3843 InstructionMark im(this);
3844 bool vector256 = true;
3845 assert(src != xnoreg, "sanity");
3846 int src_enc = src->encoding();
3847 vex_prefix(dst, 0, src_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, false, vector256);
3848 emit_int8(0x39);
3849 emit_operand(src, dst);
3850 // 0x01 - extract from upper 128 bits
3851 emit_int8(0x01);
3852 }
3853
3854 // duplicate 4-bytes integer data from src into 8 locations in dest
3855 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
3856 assert(VM_Version::supports_avx2(), "");
3857 bool vector256 = true;
3858 int encode = vex_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_38);
3859 emit_int8(0x58);
3860 emit_int8((unsigned char)(0xC0 | encode));
3861 }
3862
3863 // Carry-Less Multiplication Quadword
3864 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
3865 assert(VM_Version::supports_clmul(), "");
3866 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A);
3867 emit_int8(0x44);
3868 emit_int8((unsigned char)(0xC0 | encode));
3869 emit_int8((unsigned char)mask);
3870 }
3871
3872 // Carry-Less Multiplication Quadword
3873 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
3874 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
3875 bool vector256 = false;
3876 int encode = vex_prefix_and_encode(dst, nds, src, VEX_SIMD_66, vector256, VEX_OPCODE_0F_3A);
3877 emit_int8(0x44);
3878 emit_int8((unsigned char)(0xC0 | encode));
3879 emit_int8((unsigned char)mask);
3880 }
3881
3882 void Assembler::vzeroupper() {
3883 assert(VM_Version::supports_avx(), "");
3884 (void)vex_prefix_and_encode(xmm0, xmm0, xmm0, VEX_SIMD_NONE);
3885 emit_int8(0x77);
3886 }
3887
3888
3889 #ifndef _LP64
3890 // 32bit only pieces of the assembler
3891
3892 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
3893 // NO PREFIX AS NEVER 64BIT
3894 InstructionMark im(this);
3895 emit_int8((unsigned char)0x81);
3896 emit_int8((unsigned char)(0xF8 | src1->encoding()));
3897 emit_data(imm32, rspec, 0);
3898 }
3899
3900 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
3901 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
3902 InstructionMark im(this);
3903 emit_int8((unsigned char)0x81);
3904 emit_operand(rdi, src1);
3905 emit_data(imm32, rspec, 0);
3906 }
3907
3908 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
3909 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
3910 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
3911 void Assembler::cmpxchg8(Address adr) {
3912 InstructionMark im(this);
3913 emit_int8(0x0F);
3914 emit_int8((unsigned char)0xC7);
3915 emit_operand(rcx, adr);
3916 }
3917
3918 void Assembler::decl(Register dst) {
3919 // Don't use it directly. Use MacroAssembler::decrementl() instead.
3920 emit_int8(0x48 | dst->encoding());
3921 }
3922
3923 #endif // _LP64
3924
3925 // 64bit typically doesn't use the x87 but needs to for the trig funcs
3926
3927 void Assembler::fabs() {
3928 emit_int8((unsigned char)0xD9);
3929 emit_int8((unsigned char)0xE1);
3930 }
3931
3932 void Assembler::fadd(int i) {
3933 emit_farith(0xD8, 0xC0, i);
3934 }
3935
3936 void Assembler::fadd_d(Address src) {
3937 InstructionMark im(this);
3938 emit_int8((unsigned char)0xDC);
3939 emit_operand32(rax, src);
3940 }
3941
3942 void Assembler::fadd_s(Address src) {
3943 InstructionMark im(this);
3944 emit_int8((unsigned char)0xD8);
3945 emit_operand32(rax, src);
3946 }
3947
3948 void Assembler::fadda(int i) {
3949 emit_farith(0xDC, 0xC0, i);
3950 }
3951
3952 void Assembler::faddp(int i) {
3953 emit_farith(0xDE, 0xC0, i);
3954 }
3955
3956 void Assembler::fchs() {
3957 emit_int8((unsigned char)0xD9);
3958 emit_int8((unsigned char)0xE0);
3959 }
3960
3961 void Assembler::fcom(int i) {
3962 emit_farith(0xD8, 0xD0, i);
3963 }
3964
3965 void Assembler::fcomp(int i) {
3966 emit_farith(0xD8, 0xD8, i);
3967 }
3968
3969 void Assembler::fcomp_d(Address src) {
3970 InstructionMark im(this);
3971 emit_int8((unsigned char)0xDC);
3972 emit_operand32(rbx, src);
3973 }
3974
3975 void Assembler::fcomp_s(Address src) {
3976 InstructionMark im(this);
3977 emit_int8((unsigned char)0xD8);
3978 emit_operand32(rbx, src);
3979 }
3980
3981 void Assembler::fcompp() {
3982 emit_int8((unsigned char)0xDE);
3983 emit_int8((unsigned char)0xD9);
3984 }
3985
3986 void Assembler::fcos() {
3987 emit_int8((unsigned char)0xD9);
3988 emit_int8((unsigned char)0xFF);
3989 }
3990
3991 void Assembler::fdecstp() {
3992 emit_int8((unsigned char)0xD9);
3993 emit_int8((unsigned char)0xF6);
3994 }
3995
3996 void Assembler::fdiv(int i) {
3997 emit_farith(0xD8, 0xF0, i);
3998 }
3999
4000 void Assembler::fdiv_d(Address src) {
4001 InstructionMark im(this);
4002 emit_int8((unsigned char)0xDC);
4003 emit_operand32(rsi, src);
4004 }
4005
4006 void Assembler::fdiv_s(Address src) {
4007 InstructionMark im(this);
4008 emit_int8((unsigned char)0xD8);
4009 emit_operand32(rsi, src);
4010 }
4011
4012 void Assembler::fdiva(int i) {
4013 emit_farith(0xDC, 0xF8, i);
4014 }
4015
4016 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
4017 // is erroneous for some of the floating-point instructions below.
4018
4019 void Assembler::fdivp(int i) {
4020 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
4021 }
4022
4023 void Assembler::fdivr(int i) {
4024 emit_farith(0xD8, 0xF8, i);
4025 }
4026
4027 void Assembler::fdivr_d(Address src) {
4028 InstructionMark im(this);
4029 emit_int8((unsigned char)0xDC);
4030 emit_operand32(rdi, src);
4031 }
4032
4033 void Assembler::fdivr_s(Address src) {
4034 InstructionMark im(this);
4035 emit_int8((unsigned char)0xD8);
4036 emit_operand32(rdi, src);
4037 }
4038
4039 void Assembler::fdivra(int i) {
4040 emit_farith(0xDC, 0xF0, i);
4041 }
4042
4043 void Assembler::fdivrp(int i) {
4044 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
4045 }
4046
4047 void Assembler::ffree(int i) {
4048 emit_farith(0xDD, 0xC0, i);
4049 }
4050
4051 void Assembler::fild_d(Address adr) {
4052 InstructionMark im(this);
4053 emit_int8((unsigned char)0xDF);
4054 emit_operand32(rbp, adr);
4055 }
4056
4057 void Assembler::fild_s(Address adr) {
4058 InstructionMark im(this);
4059 emit_int8((unsigned char)0xDB);
4060 emit_operand32(rax, adr);
4061 }
4062
4063 void Assembler::fincstp() {
4064 emit_int8((unsigned char)0xD9);
4065 emit_int8((unsigned char)0xF7);
4066 }
4067
4068 void Assembler::finit() {
4069 emit_int8((unsigned char)0x9B);
4070 emit_int8((unsigned char)0xDB);
4071 emit_int8((unsigned char)0xE3);
4072 }
4073
4074 void Assembler::fist_s(Address adr) {
4075 InstructionMark im(this);
4076 emit_int8((unsigned char)0xDB);
4077 emit_operand32(rdx, adr);
4078 }
4079
4080 void Assembler::fistp_d(Address adr) {
4081 InstructionMark im(this);
4082 emit_int8((unsigned char)0xDF);
4083 emit_operand32(rdi, adr);
4084 }
4085
4086 void Assembler::fistp_s(Address adr) {
4087 InstructionMark im(this);
4088 emit_int8((unsigned char)0xDB);
4089 emit_operand32(rbx, adr);
4090 }
4091
4092 void Assembler::fld1() {
4093 emit_int8((unsigned char)0xD9);
4094 emit_int8((unsigned char)0xE8);
4095 }
4096
4097 void Assembler::fld_d(Address adr) {
4098 InstructionMark im(this);
4099 emit_int8((unsigned char)0xDD);
4100 emit_operand32(rax, adr);
4101 }
4102
4103 void Assembler::fld_s(Address adr) {
4104 InstructionMark im(this);
4105 emit_int8((unsigned char)0xD9);
4106 emit_operand32(rax, adr);
4107 }
4108
4109
4110 void Assembler::fld_s(int index) {
4111 emit_farith(0xD9, 0xC0, index);
4112 }
4113
4114 void Assembler::fld_x(Address adr) {
4115 InstructionMark im(this);
4116 emit_int8((unsigned char)0xDB);
4117 emit_operand32(rbp, adr);
4118 }
4119
4120 void Assembler::fldcw(Address src) {
4121 InstructionMark im(this);
4122 emit_int8((unsigned char)0xD9);
4123 emit_operand32(rbp, src);
4124 }
4125
4126 void Assembler::fldenv(Address src) {
4127 InstructionMark im(this);
4128 emit_int8((unsigned char)0xD9);
4129 emit_operand32(rsp, src);
4130 }
4131
4132 void Assembler::fldlg2() {
4133 emit_int8((unsigned char)0xD9);
4134 emit_int8((unsigned char)0xEC);
4135 }
4136
4137 void Assembler::fldln2() {
4138 emit_int8((unsigned char)0xD9);
4139 emit_int8((unsigned char)0xED);
4140 }
4141
4142 void Assembler::fldz() {
4143 emit_int8((unsigned char)0xD9);
4144 emit_int8((unsigned char)0xEE);
4145 }
4146
4147 void Assembler::flog() {
4148 fldln2();
4149 fxch();
4150 fyl2x();
4151 }
4152
4153 void Assembler::flog10() {
4154 fldlg2();
4155 fxch();
4156 fyl2x();
4157 }
4158
4159 void Assembler::fmul(int i) {
4160 emit_farith(0xD8, 0xC8, i);
4161 }
4162
4163 void Assembler::fmul_d(Address src) {
4164 InstructionMark im(this);
4165 emit_int8((unsigned char)0xDC);
4166 emit_operand32(rcx, src);
4167 }
4168
4169 void Assembler::fmul_s(Address src) {
4170 InstructionMark im(this);
4171 emit_int8((unsigned char)0xD8);
4172 emit_operand32(rcx, src);
4173 }
4174
4175 void Assembler::fmula(int i) {
4176 emit_farith(0xDC, 0xC8, i);
4177 }
4178
4179 void Assembler::fmulp(int i) {
4180 emit_farith(0xDE, 0xC8, i);
4181 }
4182
4183 void Assembler::fnsave(Address dst) {
4184 InstructionMark im(this);
4185 emit_int8((unsigned char)0xDD);
4186 emit_operand32(rsi, dst);
4187 }
4188
4189 void Assembler::fnstcw(Address src) {
4190 InstructionMark im(this);
4191 emit_int8((unsigned char)0x9B);
4192 emit_int8((unsigned char)0xD9);
4193 emit_operand32(rdi, src);
4194 }
4195
4196 void Assembler::fnstsw_ax() {
4197 emit_int8((unsigned char)0xDF);
4198 emit_int8((unsigned char)0xE0);
4199 }
4200
4201 void Assembler::fprem() {
4202 emit_int8((unsigned char)0xD9);
4203 emit_int8((unsigned char)0xF8);
4204 }
4205
4206 void Assembler::fprem1() {
4207 emit_int8((unsigned char)0xD9);
4208 emit_int8((unsigned char)0xF5);
4209 }
4210
4211 void Assembler::frstor(Address src) {
4212 InstructionMark im(this);
4213 emit_int8((unsigned char)0xDD);
4214 emit_operand32(rsp, src);
4215 }
4216
4217 void Assembler::fsin() {
4218 emit_int8((unsigned char)0xD9);
4219 emit_int8((unsigned char)0xFE);
4220 }
4221
4222 void Assembler::fsqrt() {
4223 emit_int8((unsigned char)0xD9);
4224 emit_int8((unsigned char)0xFA);
4225 }
4226
4227 void Assembler::fst_d(Address adr) {
4228 InstructionMark im(this);
4229 emit_int8((unsigned char)0xDD);
4230 emit_operand32(rdx, adr);
4231 }
4232
4233 void Assembler::fst_s(Address adr) {
4234 InstructionMark im(this);
4235 emit_int8((unsigned char)0xD9);
4236 emit_operand32(rdx, adr);
4237 }
4238
4239 void Assembler::fstp_d(Address adr) {
4240 InstructionMark im(this);
4241 emit_int8((unsigned char)0xDD);
4242 emit_operand32(rbx, adr);
4243 }
4244
4245 void Assembler::fstp_d(int index) {
4246 emit_farith(0xDD, 0xD8, index);
4247 }
4248
4249 void Assembler::fstp_s(Address adr) {
4250 InstructionMark im(this);
4251 emit_int8((unsigned char)0xD9);
4252 emit_operand32(rbx, adr);
4253 }
4254
4255 void Assembler::fstp_x(Address adr) {
4256 InstructionMark im(this);
4257 emit_int8((unsigned char)0xDB);
4258 emit_operand32(rdi, adr);
4259 }
4260
4261 void Assembler::fsub(int i) {
4262 emit_farith(0xD8, 0xE0, i);
4263 }
4264
4265 void Assembler::fsub_d(Address src) {
4266 InstructionMark im(this);
4267 emit_int8((unsigned char)0xDC);
4268 emit_operand32(rsp, src);
4269 }
4270
4271 void Assembler::fsub_s(Address src) {
4272 InstructionMark im(this);
4273 emit_int8((unsigned char)0xD8);
4274 emit_operand32(rsp, src);
4275 }
4276
4277 void Assembler::fsuba(int i) {
4278 emit_farith(0xDC, 0xE8, i);
4279 }
4280
4281 void Assembler::fsubp(int i) {
4282 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
4283 }
4284
4285 void Assembler::fsubr(int i) {
4286 emit_farith(0xD8, 0xE8, i);
4287 }
4288
4289 void Assembler::fsubr_d(Address src) {
4290 InstructionMark im(this);
4291 emit_int8((unsigned char)0xDC);
4292 emit_operand32(rbp, src);
4293 }
4294
4295 void Assembler::fsubr_s(Address src) {
4296 InstructionMark im(this);
4297 emit_int8((unsigned char)0xD8);
4298 emit_operand32(rbp, src);
4299 }
4300
4301 void Assembler::fsubra(int i) {
4302 emit_farith(0xDC, 0xE0, i);
4303 }
4304
4305 void Assembler::fsubrp(int i) {
4306 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
4307 }
4308
4309 void Assembler::ftan() {
4310 emit_int8((unsigned char)0xD9);
4311 emit_int8((unsigned char)0xF2);
4312 emit_int8((unsigned char)0xDD);
4313 emit_int8((unsigned char)0xD8);
4314 }
4315
4316 void Assembler::ftst() {
4317 emit_int8((unsigned char)0xD9);
4318 emit_int8((unsigned char)0xE4);
4319 }
4320
4321 void Assembler::fucomi(int i) {
4322 // make sure the instruction is supported (introduced for P6, together with cmov)
4323 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4324 emit_farith(0xDB, 0xE8, i);
4325 }
4326
4327 void Assembler::fucomip(int i) {
4328 // make sure the instruction is supported (introduced for P6, together with cmov)
4329 guarantee(VM_Version::supports_cmov(), "illegal instruction");
4330 emit_farith(0xDF, 0xE8, i);
4331 }
4332
4333 void Assembler::fwait() {
4334 emit_int8((unsigned char)0x9B);
4335 }
4336
4337 void Assembler::fxch(int i) {
4338 emit_farith(0xD9, 0xC8, i);
4339 }
4340
4341 void Assembler::fyl2x() {
4342 emit_int8((unsigned char)0xD9);
4343 emit_int8((unsigned char)0xF1);
4344 }
4345
4346 void Assembler::frndint() {
4347 emit_int8((unsigned char)0xD9);
4348 emit_int8((unsigned char)0xFC);
4349 }
4350
4351 void Assembler::f2xm1() {
4352 emit_int8((unsigned char)0xD9);
4353 emit_int8((unsigned char)0xF0);
4354 }
4355
4356 void Assembler::fldl2e() {
4357 emit_int8((unsigned char)0xD9);
4358 emit_int8((unsigned char)0xEA);
4359 }
4360
4361 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
4362 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
4363 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
4364 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
4365
4366 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
4367 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4368 if (pre > 0) {
4369 emit_int8(simd_pre[pre]);
4370 }
4371 if (rex_w) {
4372 prefixq(adr, xreg);
4373 } else {
4374 prefix(adr, xreg);
4375 }
4376 if (opc > 0) {
4377 emit_int8(0x0F);
4378 int opc2 = simd_opc[opc];
4379 if (opc2 > 0) {
4380 emit_int8(opc2);
4381 }
4382 }
4383 }
4384
4385 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
4386 if (pre > 0) {
4387 emit_int8(simd_pre[pre]);
4388 }
4389 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) :
4390 prefix_and_encode(dst_enc, src_enc);
4391 if (opc > 0) {
4392 emit_int8(0x0F);
4393 int opc2 = simd_opc[opc];
4394 if (opc2 > 0) {
4395 emit_int8(opc2);
4396 }
4397 }
4398 return encode;
4399 }
4400
4401
4402 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, bool vex_w, int nds_enc, VexSimdPrefix pre, VexOpcode opc, bool vector256) {
4403 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
4404 prefix(VEX_3bytes);
4405
4406 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
4407 byte1 = (~byte1) & 0xE0;
4408 byte1 |= opc;
4409 emit_int8(byte1);
4410
4411 int byte2 = ((~nds_enc) & 0xf) << 3;
4412 byte2 |= (vex_w ? VEX_W : 0) | (vector256 ? 4 : 0) | pre;
4413 emit_int8(byte2);
4414 } else {
4415 prefix(VEX_2bytes);
4416
4417 int byte1 = vex_r ? VEX_R : 0;
4418 byte1 = (~byte1) & 0x80;
4419 byte1 |= ((~nds_enc) & 0xf) << 3;
4420 byte1 |= (vector256 ? 4 : 0) | pre;
4421 emit_int8(byte1);
4422 }
4423 }
4424
4425 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256){
4426 bool vex_r = (xreg_enc >= 8);
4427 bool vex_b = adr.base_needs_rex();
4428 bool vex_x = adr.index_needs_rex();
4429 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4430 }
4431
4432 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool vex_w, bool vector256) {
4433 bool vex_r = (dst_enc >= 8);
4434 bool vex_b = (src_enc >= 8);
4435 bool vex_x = false;
4436 vex_prefix(vex_r, vex_b, vex_x, vex_w, nds_enc, pre, opc, vector256);
4437 return (((dst_enc & 7) << 3) | (src_enc & 7));
4438 }
4439
4440
4441 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4442 if (UseAVX > 0) {
4443 int xreg_enc = xreg->encoding();
4444 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4445 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, rex_w, vector256);
4446 } else {
4447 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
4448 rex_prefix(adr, xreg, pre, opc, rex_w);
4449 }
4450 }
4451
4452 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, VexOpcode opc, bool rex_w, bool vector256) {
4453 int dst_enc = dst->encoding();
4454 int src_enc = src->encoding();
4455 if (UseAVX > 0) {
4456 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4457 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, rex_w, vector256);
4458 } else {
4459 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
4460 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, rex_w);
4461 }
4462 }
4463
4464 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4465 InstructionMark im(this);
4466 simd_prefix(dst, dst, src, pre);
4467 emit_int8(opcode);
4468 emit_operand(dst, src);
4469 }
4470
4471 void Assembler::emit_simd_arith(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4472 int encode = simd_prefix_and_encode(dst, dst, src, pre);
4473 emit_int8(opcode);
4474 emit_int8((unsigned char)(0xC0 | encode));
4475 }
4476
4477 // Versions with no second source register (non-destructive source).
4478 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, Address src, VexSimdPrefix pre) {
4479 InstructionMark im(this);
4480 simd_prefix(dst, xnoreg, src, pre);
4481 emit_int8(opcode);
4482 emit_operand(dst, src);
4483 }
4484
4485 void Assembler::emit_simd_arith_nonds(int opcode, XMMRegister dst, XMMRegister src, VexSimdPrefix pre) {
4486 int encode = simd_prefix_and_encode(dst, xnoreg, src, pre);
4487 emit_int8(opcode);
4488 emit_int8((unsigned char)(0xC0 | encode));
4489 }
4490
4491 // 3-operands AVX instructions
4492 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4493 Address src, VexSimdPrefix pre, bool vector256) {
4494 InstructionMark im(this);
4495 vex_prefix(dst, nds, src, pre, vector256);
4496 emit_int8(opcode);
4497 emit_operand(dst, src);
4498 }
4499
4500 void Assembler::emit_vex_arith(int opcode, XMMRegister dst, XMMRegister nds,
4501 XMMRegister src, VexSimdPrefix pre, bool vector256) {
4502 int encode = vex_prefix_and_encode(dst, nds, src, pre, vector256);
4503 emit_int8(opcode);
4504 emit_int8((unsigned char)(0xC0 | encode));
4505 }
4506
4507 #ifndef _LP64
4508
4509 void Assembler::incl(Register dst) {
4510 // Don't use it directly. Use MacroAssembler::incrementl() instead.
4511 emit_int8(0x40 | dst->encoding());
4512 }
4513
4514 void Assembler::lea(Register dst, Address src) {
4515 leal(dst, src);
4516 }
4517
4518 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
4519 InstructionMark im(this);
4520 emit_int8((unsigned char)0xC7);
4521 emit_operand(rax, dst);
4522 emit_data((int)imm32, rspec, 0);
4523 }
4524
4525 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
4526 InstructionMark im(this);
4527 int encode = prefix_and_encode(dst->encoding());
4528 emit_int8((unsigned char)(0xB8 | encode));
4529 emit_data((int)imm32, rspec, 0);
4530 }
4531
4532 void Assembler::popa() { // 32bit
4533 emit_int8(0x61);
4534 }
4535
4536 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
4537 InstructionMark im(this);
4538 emit_int8(0x68);
4539 emit_data(imm32, rspec, 0);
4540 }
4541
4542 void Assembler::pusha() { // 32bit
4543 emit_int8(0x60);
4544 }
4545
4546 void Assembler::set_byte_if_not_zero(Register dst) {
4547 emit_int8(0x0F);
4548 emit_int8((unsigned char)0x95);
4549 emit_int8((unsigned char)(0xE0 | dst->encoding()));
4550 }
4551
4552 void Assembler::shldl(Register dst, Register src) {
4553 emit_int8(0x0F);
4554 emit_int8((unsigned char)0xA5);
4555 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4556 }
4557
4558 void Assembler::shrdl(Register dst, Register src) {
4559 emit_int8(0x0F);
4560 emit_int8((unsigned char)0xAD);
4561 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
4562 }
4563
4564 #else // LP64
4565
4566 void Assembler::set_byte_if_not_zero(Register dst) {
4567 int enc = prefix_and_encode(dst->encoding(), true);
4568 emit_int8(0x0F);
4569 emit_int8((unsigned char)0x95);
4570 emit_int8((unsigned char)(0xE0 | enc));
4571 }
4572
4573 // 64bit only pieces of the assembler
4574 // This should only be used by 64bit instructions that can use rip-relative
4575 // it cannot be used by instructions that want an immediate value.
4576
4577 bool Assembler::reachable(AddressLiteral adr) {
4578 int64_t disp;
4579 // None will force a 64bit literal to the code stream. Likely a placeholder
4580 // for something that will be patched later and we need to certain it will
4581 // always be reachable.
4582 if (adr.reloc() == relocInfo::none) {
4583 return false;
4584 }
4585 if (adr.reloc() == relocInfo::internal_word_type) {
4586 // This should be rip relative and easily reachable.
4587 return true;
4588 }
4589 if (adr.reloc() == relocInfo::virtual_call_type ||
4590 adr.reloc() == relocInfo::opt_virtual_call_type ||
4591 adr.reloc() == relocInfo::static_call_type ||
4592 adr.reloc() == relocInfo::static_stub_type ) {
4593 // This should be rip relative within the code cache and easily
4594 // reachable until we get huge code caches. (At which point
4595 // ic code is going to have issues).
4596 return true;
4597 }
4598 if (adr.reloc() != relocInfo::external_word_type &&
4599 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
4600 adr.reloc() != relocInfo::poll_type && // relocs to identify them
4601 adr.reloc() != relocInfo::runtime_call_type ) {
4602 return false;
4603 }
4604
4605 // Stress the correction code
4606 if (ForceUnreachable) {
4607 // Must be runtimecall reloc, see if it is in the codecache
4608 // Flipping stuff in the codecache to be unreachable causes issues
4609 // with things like inline caches where the additional instructions
4610 // are not handled.
4611 if (CodeCache::find_blob(adr._target) == NULL) {
4612 return false;
4613 }
4614 }
4615 // For external_word_type/runtime_call_type if it is reachable from where we
4616 // are now (possibly a temp buffer) and where we might end up
4617 // anywhere in the codeCache then we are always reachable.
4618 // This would have to change if we ever save/restore shared code
4619 // to be more pessimistic.
4620 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
4621 if (!is_simm32(disp)) return false;
4622 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
4623 if (!is_simm32(disp)) return false;
4624
4625 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
4626
4627 // Because rip relative is a disp + address_of_next_instruction and we
4628 // don't know the value of address_of_next_instruction we apply a fudge factor
4629 // to make sure we will be ok no matter the size of the instruction we get placed into.
4630 // We don't have to fudge the checks above here because they are already worst case.
4631
4632 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
4633 // + 4 because better safe than sorry.
4634 const int fudge = 12 + 4;
4635 if (disp < 0) {
4636 disp -= fudge;
4637 } else {
4638 disp += fudge;
4639 }
4640 return is_simm32(disp);
4641 }
4642
4643 // Check if the polling page is not reachable from the code cache using rip-relative
4644 // addressing.
4645 bool Assembler::is_polling_page_far() {
4646 intptr_t addr = (intptr_t)os::get_polling_page();
4647 return ForceUnreachable ||
4648 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
4649 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
4650 }
4651
4652 void Assembler::emit_data64(jlong data,
4653 relocInfo::relocType rtype,
4654 int format) {
4655 if (rtype == relocInfo::none) {
4656 emit_int64(data);
4657 } else {
4658 emit_data64(data, Relocation::spec_simple(rtype), format);
4659 }
4660 }
4661
4662 void Assembler::emit_data64(jlong data,
4663 RelocationHolder const& rspec,
4664 int format) {
4665 assert(imm_operand == 0, "default format must be immediate in this file");
4666 assert(imm_operand == format, "must be immediate");
4667 assert(inst_mark() != NULL, "must be inside InstructionMark");
4668 // Do not use AbstractAssembler::relocate, which is not intended for
4669 // embedded words. Instead, relocate to the enclosing instruction.
4670 code_section()->relocate(inst_mark(), rspec, format);
4671 #ifdef ASSERT
4672 check_relocation(rspec, format);
4673 #endif
4674 emit_int64(data);
4675 }
4676
4677 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
4678 if (reg_enc >= 8) {
4679 prefix(REX_B);
4680 reg_enc -= 8;
4681 } else if (byteinst && reg_enc >= 4) {
4682 prefix(REX);
4683 }
4684 return reg_enc;
4685 }
4686
4687 int Assembler::prefixq_and_encode(int reg_enc) {
4688 if (reg_enc < 8) {
4689 prefix(REX_W);
4690 } else {
4691 prefix(REX_WB);
4692 reg_enc -= 8;
4693 }
4694 return reg_enc;
4695 }
4696
4697 int Assembler::prefix_and_encode(int dst_enc, int src_enc, bool byteinst) {
4698 if (dst_enc < 8) {
4699 if (src_enc >= 8) {
4700 prefix(REX_B);
4701 src_enc -= 8;
4702 } else if (byteinst && src_enc >= 4) {
4703 prefix(REX);
4704 }
4705 } else {
4706 if (src_enc < 8) {
4707 prefix(REX_R);
4708 } else {
4709 prefix(REX_RB);
4710 src_enc -= 8;
4711 }
4712 dst_enc -= 8;
4713 }
4714 return dst_enc << 3 | src_enc;
4715 }
4716
4717 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
4718 if (dst_enc < 8) {
4719 if (src_enc < 8) {
4720 prefix(REX_W);
4721 } else {
4722 prefix(REX_WB);
4723 src_enc -= 8;
4724 }
4725 } else {
4726 if (src_enc < 8) {
4727 prefix(REX_WR);
4728 } else {
4729 prefix(REX_WRB);
4730 src_enc -= 8;
4731 }
4732 dst_enc -= 8;
4733 }
4734 return dst_enc << 3 | src_enc;
4735 }
4736
4737 void Assembler::prefix(Register reg) {
4738 if (reg->encoding() >= 8) {
4739 prefix(REX_B);
4740 }
4741 }
4742
4743 void Assembler::prefix(Address adr) {
4744 if (adr.base_needs_rex()) {
4745 if (adr.index_needs_rex()) {
4746 prefix(REX_XB);
4747 } else {
4748 prefix(REX_B);
4749 }
4750 } else {
4751 if (adr.index_needs_rex()) {
4752 prefix(REX_X);
4753 }
4754 }
4755 }
4756
4757 void Assembler::prefixq(Address adr) {
4758 if (adr.base_needs_rex()) {
4759 if (adr.index_needs_rex()) {
4760 prefix(REX_WXB);
4761 } else {
4762 prefix(REX_WB);
4763 }
4764 } else {
4765 if (adr.index_needs_rex()) {
4766 prefix(REX_WX);
4767 } else {
4768 prefix(REX_W);
4769 }
4770 }
4771 }
4772
4773
4774 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
4775 if (reg->encoding() < 8) {
4776 if (adr.base_needs_rex()) {
4777 if (adr.index_needs_rex()) {
4778 prefix(REX_XB);
4779 } else {
4780 prefix(REX_B);
4781 }
4782 } else {
4783 if (adr.index_needs_rex()) {
4784 prefix(REX_X);
4785 } else if (byteinst && reg->encoding() >= 4 ) {
4786 prefix(REX);
4787 }
4788 }
4789 } else {
4790 if (adr.base_needs_rex()) {
4791 if (adr.index_needs_rex()) {
4792 prefix(REX_RXB);
4793 } else {
4794 prefix(REX_RB);
4795 }
4796 } else {
4797 if (adr.index_needs_rex()) {
4798 prefix(REX_RX);
4799 } else {
4800 prefix(REX_R);
4801 }
4802 }
4803 }
4804 }
4805
4806 void Assembler::prefixq(Address adr, Register src) {
4807 if (src->encoding() < 8) {
4808 if (adr.base_needs_rex()) {
4809 if (adr.index_needs_rex()) {
4810 prefix(REX_WXB);
4811 } else {
4812 prefix(REX_WB);
4813 }
4814 } else {
4815 if (adr.index_needs_rex()) {
4816 prefix(REX_WX);
4817 } else {
4818 prefix(REX_W);
4819 }
4820 }
4821 } else {
4822 if (adr.base_needs_rex()) {
4823 if (adr.index_needs_rex()) {
4824 prefix(REX_WRXB);
4825 } else {
4826 prefix(REX_WRB);
4827 }
4828 } else {
4829 if (adr.index_needs_rex()) {
4830 prefix(REX_WRX);
4831 } else {
4832 prefix(REX_WR);
4833 }
4834 }
4835 }
4836 }
4837
4838 void Assembler::prefix(Address adr, XMMRegister reg) {
4839 if (reg->encoding() < 8) {
4840 if (adr.base_needs_rex()) {
4841 if (adr.index_needs_rex()) {
4842 prefix(REX_XB);
4843 } else {
4844 prefix(REX_B);
4845 }
4846 } else {
4847 if (adr.index_needs_rex()) {
4848 prefix(REX_X);
4849 }
4850 }
4851 } else {
4852 if (adr.base_needs_rex()) {
4853 if (adr.index_needs_rex()) {
4854 prefix(REX_RXB);
4855 } else {
4856 prefix(REX_RB);
4857 }
4858 } else {
4859 if (adr.index_needs_rex()) {
4860 prefix(REX_RX);
4861 } else {
4862 prefix(REX_R);
4863 }
4864 }
4865 }
4866 }
4867
4868 void Assembler::prefixq(Address adr, XMMRegister src) {
4869 if (src->encoding() < 8) {
4870 if (adr.base_needs_rex()) {
4871 if (adr.index_needs_rex()) {
4872 prefix(REX_WXB);
4873 } else {
4874 prefix(REX_WB);
4875 }
4876 } else {
4877 if (adr.index_needs_rex()) {
4878 prefix(REX_WX);
4879 } else {
4880 prefix(REX_W);
4881 }
4882 }
4883 } else {
4884 if (adr.base_needs_rex()) {
4885 if (adr.index_needs_rex()) {
4886 prefix(REX_WRXB);
4887 } else {
4888 prefix(REX_WRB);
4889 }
4890 } else {
4891 if (adr.index_needs_rex()) {
4892 prefix(REX_WRX);
4893 } else {
4894 prefix(REX_WR);
4895 }
4896 }
4897 }
4898 }
4899
4900 void Assembler::adcq(Register dst, int32_t imm32) {
4901 (void) prefixq_and_encode(dst->encoding());
4902 emit_arith(0x81, 0xD0, dst, imm32);
4903 }
4904
4905 void Assembler::adcq(Register dst, Address src) {
4906 InstructionMark im(this);
4907 prefixq(src, dst);
4908 emit_int8(0x13);
4909 emit_operand(dst, src);
4910 }
4911
4912 void Assembler::adcq(Register dst, Register src) {
4913 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4914 emit_arith(0x13, 0xC0, dst, src);
4915 }
4916
4917 void Assembler::addq(Address dst, int32_t imm32) {
4918 InstructionMark im(this);
4919 prefixq(dst);
4920 emit_arith_operand(0x81, rax, dst,imm32);
4921 }
4922
4923 void Assembler::addq(Address dst, Register src) {
4924 InstructionMark im(this);
4925 prefixq(dst, src);
4926 emit_int8(0x01);
4927 emit_operand(src, dst);
4928 }
4929
4930 void Assembler::addq(Register dst, int32_t imm32) {
4931 (void) prefixq_and_encode(dst->encoding());
4932 emit_arith(0x81, 0xC0, dst, imm32);
4933 }
4934
4935 void Assembler::addq(Register dst, Address src) {
4936 InstructionMark im(this);
4937 prefixq(src, dst);
4938 emit_int8(0x03);
4939 emit_operand(dst, src);
4940 }
4941
4942 void Assembler::addq(Register dst, Register src) {
4943 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4944 emit_arith(0x03, 0xC0, dst, src);
4945 }
4946
4947 void Assembler::adcxq(Register dst, Register src) {
4948 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4949 emit_int8((unsigned char)0x66);
4950 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4951 emit_int8(0x0F);
4952 emit_int8(0x38);
4953 emit_int8((unsigned char)0xF6);
4954 emit_int8((unsigned char)(0xC0 | encode));
4955 }
4956
4957 void Assembler::adoxq(Register dst, Register src) {
4958 //assert(VM_Version::supports_adx(), "adx instructions not supported");
4959 emit_int8((unsigned char)0xF3);
4960 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4961 emit_int8(0x0F);
4962 emit_int8(0x38);
4963 emit_int8((unsigned char)0xF6);
4964 emit_int8((unsigned char)(0xC0 | encode));
4965 }
4966
4967 void Assembler::andq(Address dst, int32_t imm32) {
4968 InstructionMark im(this);
4969 prefixq(dst);
4970 emit_int8((unsigned char)0x81);
4971 emit_operand(rsp, dst, 4);
4972 emit_int32(imm32);
4973 }
4974
4975 void Assembler::andq(Register dst, int32_t imm32) {
4976 (void) prefixq_and_encode(dst->encoding());
4977 emit_arith(0x81, 0xE0, dst, imm32);
4978 }
4979
4980 void Assembler::andq(Register dst, Address src) {
4981 InstructionMark im(this);
4982 prefixq(src, dst);
4983 emit_int8(0x23);
4984 emit_operand(dst, src);
4985 }
4986
4987 void Assembler::andq(Register dst, Register src) {
4988 (void) prefixq_and_encode(dst->encoding(), src->encoding());
4989 emit_arith(0x23, 0xC0, dst, src);
4990 }
4991
4992 void Assembler::andnq(Register dst, Register src1, Register src2) {
4993 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
4994 int encode = vex_prefix_0F38_and_encode_q(dst, src1, src2);
4995 emit_int8((unsigned char)0xF2);
4996 emit_int8((unsigned char)(0xC0 | encode));
4997 }
4998
4999 void Assembler::andnq(Register dst, Register src1, Address src2) {
5000 InstructionMark im(this);
5001 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5002 vex_prefix_0F38_q(dst, src1, src2);
5003 emit_int8((unsigned char)0xF2);
5004 emit_operand(dst, src2);
5005 }
5006
5007 void Assembler::bsfq(Register dst, Register src) {
5008 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5009 emit_int8(0x0F);
5010 emit_int8((unsigned char)0xBC);
5011 emit_int8((unsigned char)(0xC0 | encode));
5012 }
5013
5014 void Assembler::bsrq(Register dst, Register src) {
5015 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5016 emit_int8(0x0F);
5017 emit_int8((unsigned char)0xBD);
5018 emit_int8((unsigned char)(0xC0 | encode));
5019 }
5020
5021 void Assembler::bswapq(Register reg) {
5022 int encode = prefixq_and_encode(reg->encoding());
5023 emit_int8(0x0F);
5024 emit_int8((unsigned char)(0xC8 | encode));
5025 }
5026
5027 void Assembler::blsiq(Register dst, Register src) {
5028 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5029 int encode = vex_prefix_0F38_and_encode_q(rbx, dst, src);
5030 emit_int8((unsigned char)0xF3);
5031 emit_int8((unsigned char)(0xC0 | encode));
5032 }
5033
5034 void Assembler::blsiq(Register dst, Address src) {
5035 InstructionMark im(this);
5036 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5037 vex_prefix_0F38_q(rbx, dst, src);
5038 emit_int8((unsigned char)0xF3);
5039 emit_operand(rbx, src);
5040 }
5041
5042 void Assembler::blsmskq(Register dst, Register src) {
5043 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5044 int encode = vex_prefix_0F38_and_encode_q(rdx, dst, src);
5045 emit_int8((unsigned char)0xF3);
5046 emit_int8((unsigned char)(0xC0 | encode));
5047 }
5048
5049 void Assembler::blsmskq(Register dst, Address src) {
5050 InstructionMark im(this);
5051 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5052 vex_prefix_0F38_q(rdx, dst, src);
5053 emit_int8((unsigned char)0xF3);
5054 emit_operand(rdx, src);
5055 }
5056
5057 void Assembler::blsrq(Register dst, Register src) {
5058 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5059 int encode = vex_prefix_0F38_and_encode_q(rcx, dst, src);
5060 emit_int8((unsigned char)0xF3);
5061 emit_int8((unsigned char)(0xC0 | encode));
5062 }
5063
5064 void Assembler::blsrq(Register dst, Address src) {
5065 InstructionMark im(this);
5066 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
5067 vex_prefix_0F38_q(rcx, dst, src);
5068 emit_int8((unsigned char)0xF3);
5069 emit_operand(rcx, src);
5070 }
5071
5072 void Assembler::cdqq() {
5073 prefix(REX_W);
5074 emit_int8((unsigned char)0x99);
5075 }
5076
5077 void Assembler::clflush(Address adr) {
5078 prefix(adr);
5079 emit_int8(0x0F);
5080 emit_int8((unsigned char)0xAE);
5081 emit_operand(rdi, adr);
5082 }
5083
5084 void Assembler::cmovq(Condition cc, Register dst, Register src) {
5085 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5086 emit_int8(0x0F);
5087 emit_int8(0x40 | cc);
5088 emit_int8((unsigned char)(0xC0 | encode));
5089 }
5090
5091 void Assembler::cmovq(Condition cc, Register dst, Address src) {
5092 InstructionMark im(this);
5093 prefixq(src, dst);
5094 emit_int8(0x0F);
5095 emit_int8(0x40 | cc);
5096 emit_operand(dst, src);
5097 }
5098
5099 void Assembler::cmpq(Address dst, int32_t imm32) {
5100 InstructionMark im(this);
5101 prefixq(dst);
5102 emit_int8((unsigned char)0x81);
5103 emit_operand(rdi, dst, 4);
5104 emit_int32(imm32);
5105 }
5106
5107 void Assembler::cmpq(Register dst, int32_t imm32) {
5108 (void) prefixq_and_encode(dst->encoding());
5109 emit_arith(0x81, 0xF8, dst, imm32);
5110 }
5111
5112 void Assembler::cmpq(Address dst, Register src) {
5113 InstructionMark im(this);
5114 prefixq(dst, src);
5115 emit_int8(0x3B);
5116 emit_operand(src, dst);
5117 }
5118
5119 void Assembler::cmpq(Register dst, Register src) {
5120 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5121 emit_arith(0x3B, 0xC0, dst, src);
5122 }
5123
5124 void Assembler::cmpq(Register dst, Address src) {
5125 InstructionMark im(this);
5126 prefixq(src, dst);
5127 emit_int8(0x3B);
5128 emit_operand(dst, src);
5129 }
5130
5131 void Assembler::cmpxchgq(Register reg, Address adr) {
5132 InstructionMark im(this);
5133 prefixq(adr, reg);
5134 emit_int8(0x0F);
5135 emit_int8((unsigned char)0xB1);
5136 emit_operand(reg, adr);
5137 }
5138
5139 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
5140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5141 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2);
5142 emit_int8(0x2A);
5143 emit_int8((unsigned char)(0xC0 | encode));
5144 }
5145
5146 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
5147 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5148 InstructionMark im(this);
5149 simd_prefix_q(dst, dst, src, VEX_SIMD_F2);
5150 emit_int8(0x2A);
5151 emit_operand(dst, src);
5152 }
5153
5154 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
5155 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5156 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3);
5157 emit_int8(0x2A);
5158 emit_int8((unsigned char)(0xC0 | encode));
5159 }
5160
5161 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
5162 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5163 InstructionMark im(this);
5164 simd_prefix_q(dst, dst, src, VEX_SIMD_F3);
5165 emit_int8(0x2A);
5166 emit_operand(dst, src);
5167 }
5168
5169 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
5170 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5171 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2);
5172 emit_int8(0x2C);
5173 emit_int8((unsigned char)(0xC0 | encode));
5174 }
5175
5176 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
5177 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5178 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F3);
5179 emit_int8(0x2C);
5180 emit_int8((unsigned char)(0xC0 | encode));
5181 }
5182
5183 void Assembler::decl(Register dst) {
5184 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5185 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
5186 int encode = prefix_and_encode(dst->encoding());
5187 emit_int8((unsigned char)0xFF);
5188 emit_int8((unsigned char)(0xC8 | encode));
5189 }
5190
5191 void Assembler::decq(Register dst) {
5192 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5193 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5194 int encode = prefixq_and_encode(dst->encoding());
5195 emit_int8((unsigned char)0xFF);
5196 emit_int8(0xC8 | encode);
5197 }
5198
5199 void Assembler::decq(Address dst) {
5200 // Don't use it directly. Use MacroAssembler::decrementq() instead.
5201 InstructionMark im(this);
5202 prefixq(dst);
5203 emit_int8((unsigned char)0xFF);
5204 emit_operand(rcx, dst);
5205 }
5206
5207 void Assembler::fxrstor(Address src) {
5208 prefixq(src);
5209 emit_int8(0x0F);
5210 emit_int8((unsigned char)0xAE);
5211 emit_operand(as_Register(1), src);
5212 }
5213
5214 void Assembler::fxsave(Address dst) {
5215 prefixq(dst);
5216 emit_int8(0x0F);
5217 emit_int8((unsigned char)0xAE);
5218 emit_operand(as_Register(0), dst);
5219 }
5220
5221 void Assembler::idivq(Register src) {
5222 int encode = prefixq_and_encode(src->encoding());
5223 emit_int8((unsigned char)0xF7);
5224 emit_int8((unsigned char)(0xF8 | encode));
5225 }
5226
5227 void Assembler::imulq(Register dst, Register src) {
5228 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5229 emit_int8(0x0F);
5230 emit_int8((unsigned char)0xAF);
5231 emit_int8((unsigned char)(0xC0 | encode));
5232 }
5233
5234 void Assembler::imulq(Register dst, Register src, int value) {
5235 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5236 if (is8bit(value)) {
5237 emit_int8(0x6B);
5238 emit_int8((unsigned char)(0xC0 | encode));
5239 emit_int8(value & 0xFF);
5240 } else {
5241 emit_int8(0x69);
5242 emit_int8((unsigned char)(0xC0 | encode));
5243 emit_int32(value);
5244 }
5245 }
5246
5247 void Assembler::imulq(Register dst, Address src) {
5248 InstructionMark im(this);
5249 prefixq(src, dst);
5250 emit_int8(0x0F);
5251 emit_int8((unsigned char) 0xAF);
5252 emit_operand(dst, src);
5253 }
5254
5255 void Assembler::incl(Register dst) {
5256 // Don't use it directly. Use MacroAssembler::incrementl() instead.
5257 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5258 int encode = prefix_and_encode(dst->encoding());
5259 emit_int8((unsigned char)0xFF);
5260 emit_int8((unsigned char)(0xC0 | encode));
5261 }
5262
5263 void Assembler::incq(Register dst) {
5264 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5265 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
5266 int encode = prefixq_and_encode(dst->encoding());
5267 emit_int8((unsigned char)0xFF);
5268 emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270
5271 void Assembler::incq(Address dst) {
5272 // Don't use it directly. Use MacroAssembler::incrementq() instead.
5273 InstructionMark im(this);
5274 prefixq(dst);
5275 emit_int8((unsigned char)0xFF);
5276 emit_operand(rax, dst);
5277 }
5278
5279 void Assembler::lea(Register dst, Address src) {
5280 leaq(dst, src);
5281 }
5282
5283 void Assembler::leaq(Register dst, Address src) {
5284 InstructionMark im(this);
5285 prefixq(src, dst);
5286 emit_int8((unsigned char)0x8D);
5287 emit_operand(dst, src);
5288 }
5289
5290 void Assembler::mov64(Register dst, int64_t imm64) {
5291 InstructionMark im(this);
5292 int encode = prefixq_and_encode(dst->encoding());
5293 emit_int8((unsigned char)(0xB8 | encode));
5294 emit_int64(imm64);
5295 }
5296
5297 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
5298 InstructionMark im(this);
5299 int encode = prefixq_and_encode(dst->encoding());
5300 emit_int8(0xB8 | encode);
5301 emit_data64(imm64, rspec);
5302 }
5303
5304 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
5305 InstructionMark im(this);
5306 int encode = prefix_and_encode(dst->encoding());
5307 emit_int8((unsigned char)(0xB8 | encode));
5308 emit_data((int)imm32, rspec, narrow_oop_operand);
5309 }
5310
5311 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
5312 InstructionMark im(this);
5313 prefix(dst);
5314 emit_int8((unsigned char)0xC7);
5315 emit_operand(rax, dst, 4);
5316 emit_data((int)imm32, rspec, narrow_oop_operand);
5317 }
5318
5319 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5320 InstructionMark im(this);
5321 int encode = prefix_and_encode(src1->encoding());
5322 emit_int8((unsigned char)0x81);
5323 emit_int8((unsigned char)(0xF8 | encode));
5324 emit_data((int)imm32, rspec, narrow_oop_operand);
5325 }
5326
5327 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5328 InstructionMark im(this);
5329 prefix(src1);
5330 emit_int8((unsigned char)0x81);
5331 emit_operand(rax, src1, 4);
5332 emit_data((int)imm32, rspec, narrow_oop_operand);
5333 }
5334
5335 void Assembler::lzcntq(Register dst, Register src) {
5336 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
5337 emit_int8((unsigned char)0xF3);
5338 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5339 emit_int8(0x0F);
5340 emit_int8((unsigned char)0xBD);
5341 emit_int8((unsigned char)(0xC0 | encode));
5342 }
5343
5344 void Assembler::movdq(XMMRegister dst, Register src) {
5345 // table D-1 says MMX/SSE2
5346 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5347 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_66);
5348 emit_int8(0x6E);
5349 emit_int8((unsigned char)(0xC0 | encode));
5350 }
5351
5352 void Assembler::movdq(Register dst, XMMRegister src) {
5353 // table D-1 says MMX/SSE2
5354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5355 // swap src/dst to get correct prefix
5356 int encode = simd_prefix_and_encode_q(src, dst, VEX_SIMD_66);
5357 emit_int8(0x7E);
5358 emit_int8((unsigned char)(0xC0 | encode));
5359 }
5360
5361 void Assembler::movq(Register dst, Register src) {
5362 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5363 emit_int8((unsigned char)0x8B);
5364 emit_int8((unsigned char)(0xC0 | encode));
5365 }
5366
5367 void Assembler::movq(Register dst, Address src) {
5368 InstructionMark im(this);
5369 prefixq(src, dst);
5370 emit_int8((unsigned char)0x8B);
5371 emit_operand(dst, src);
5372 }
5373
5374 void Assembler::movq(Address dst, Register src) {
5375 InstructionMark im(this);
5376 prefixq(dst, src);
5377 emit_int8((unsigned char)0x89);
5378 emit_operand(src, dst);
5379 }
5380
5381 void Assembler::movsbq(Register dst, Address src) {
5382 InstructionMark im(this);
5383 prefixq(src, dst);
5384 emit_int8(0x0F);
5385 emit_int8((unsigned char)0xBE);
5386 emit_operand(dst, src);
5387 }
5388
5389 void Assembler::movsbq(Register dst, Register src) {
5390 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5391 emit_int8(0x0F);
5392 emit_int8((unsigned char)0xBE);
5393 emit_int8((unsigned char)(0xC0 | encode));
5394 }
5395
5396 void Assembler::movslq(Register dst, int32_t imm32) {
5397 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
5398 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
5399 // as a result we shouldn't use until tested at runtime...
5400 ShouldNotReachHere();
5401 InstructionMark im(this);
5402 int encode = prefixq_and_encode(dst->encoding());
5403 emit_int8((unsigned char)(0xC7 | encode));
5404 emit_int32(imm32);
5405 }
5406
5407 void Assembler::movslq(Address dst, int32_t imm32) {
5408 assert(is_simm32(imm32), "lost bits");
5409 InstructionMark im(this);
5410 prefixq(dst);
5411 emit_int8((unsigned char)0xC7);
5412 emit_operand(rax, dst, 4);
5413 emit_int32(imm32);
5414 }
5415
5416 void Assembler::movslq(Register dst, Address src) {
5417 InstructionMark im(this);
5418 prefixq(src, dst);
5419 emit_int8(0x63);
5420 emit_operand(dst, src);
5421 }
5422
5423 void Assembler::movslq(Register dst, Register src) {
5424 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5425 emit_int8(0x63);
5426 emit_int8((unsigned char)(0xC0 | encode));
5427 }
5428
5429 void Assembler::movswq(Register dst, Address src) {
5430 InstructionMark im(this);
5431 prefixq(src, dst);
5432 emit_int8(0x0F);
5433 emit_int8((unsigned char)0xBF);
5434 emit_operand(dst, src);
5435 }
5436
5437 void Assembler::movswq(Register dst, Register src) {
5438 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5439 emit_int8((unsigned char)0x0F);
5440 emit_int8((unsigned char)0xBF);
5441 emit_int8((unsigned char)(0xC0 | encode));
5442 }
5443
5444 void Assembler::movzbq(Register dst, Address src) {
5445 InstructionMark im(this);
5446 prefixq(src, dst);
5447 emit_int8((unsigned char)0x0F);
5448 emit_int8((unsigned char)0xB6);
5449 emit_operand(dst, src);
5450 }
5451
5452 void Assembler::movzbq(Register dst, Register src) {
5453 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5454 emit_int8(0x0F);
5455 emit_int8((unsigned char)0xB6);
5456 emit_int8(0xC0 | encode);
5457 }
5458
5459 void Assembler::movzwq(Register dst, Address src) {
5460 InstructionMark im(this);
5461 prefixq(src, dst);
5462 emit_int8((unsigned char)0x0F);
5463 emit_int8((unsigned char)0xB7);
5464 emit_operand(dst, src);
5465 }
5466
5467 void Assembler::movzwq(Register dst, Register src) {
5468 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5469 emit_int8((unsigned char)0x0F);
5470 emit_int8((unsigned char)0xB7);
5471 emit_int8((unsigned char)(0xC0 | encode));
5472 }
5473
5474 void Assembler::mulq(Address src) {
5475 InstructionMark im(this);
5476 prefixq(src);
5477 emit_int8((unsigned char)0xF7);
5478 emit_operand(rsp, src);
5479 }
5480
5481 void Assembler::mulq(Register src) {
5482 int encode = prefixq_and_encode(src->encoding());
5483 emit_int8((unsigned char)0xF7);
5484 emit_int8((unsigned char)(0xE0 | encode));
5485 }
5486
5487 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
5488 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5489 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, true, false);
5490 emit_int8((unsigned char)0xF6);
5491 emit_int8((unsigned char)(0xC0 | encode));
5492 }
5493
5494 void Assembler::negq(Register dst) {
5495 int encode = prefixq_and_encode(dst->encoding());
5496 emit_int8((unsigned char)0xF7);
5497 emit_int8((unsigned char)(0xD8 | encode));
5498 }
5499
5500 void Assembler::notq(Register dst) {
5501 int encode = prefixq_and_encode(dst->encoding());
5502 emit_int8((unsigned char)0xF7);
5503 emit_int8((unsigned char)(0xD0 | encode));
5504 }
5505
5506 void Assembler::orq(Address dst, int32_t imm32) {
5507 InstructionMark im(this);
5508 prefixq(dst);
5509 emit_int8((unsigned char)0x81);
5510 emit_operand(rcx, dst, 4);
5511 emit_int32(imm32);
5512 }
5513
5514 void Assembler::orq(Register dst, int32_t imm32) {
5515 (void) prefixq_and_encode(dst->encoding());
5516 emit_arith(0x81, 0xC8, dst, imm32);
5517 }
5518
5519 void Assembler::orq(Register dst, Address src) {
5520 InstructionMark im(this);
5521 prefixq(src, dst);
5522 emit_int8(0x0B);
5523 emit_operand(dst, src);
5524 }
5525
5526 void Assembler::orq(Register dst, Register src) {
5527 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5528 emit_arith(0x0B, 0xC0, dst, src);
5529 }
5530
5531 void Assembler::popa() { // 64bit
5532 movq(r15, Address(rsp, 0));
5533 movq(r14, Address(rsp, wordSize));
5534 movq(r13, Address(rsp, 2 * wordSize));
5535 movq(r12, Address(rsp, 3 * wordSize));
5536 movq(r11, Address(rsp, 4 * wordSize));
5537 movq(r10, Address(rsp, 5 * wordSize));
5538 movq(r9, Address(rsp, 6 * wordSize));
5539 movq(r8, Address(rsp, 7 * wordSize));
5540 movq(rdi, Address(rsp, 8 * wordSize));
5541 movq(rsi, Address(rsp, 9 * wordSize));
5542 movq(rbp, Address(rsp, 10 * wordSize));
5543 // skip rsp
5544 movq(rbx, Address(rsp, 12 * wordSize));
5545 movq(rdx, Address(rsp, 13 * wordSize));
5546 movq(rcx, Address(rsp, 14 * wordSize));
5547 movq(rax, Address(rsp, 15 * wordSize));
5548
5549 addq(rsp, 16 * wordSize);
5550 }
5551
5552 void Assembler::popcntq(Register dst, Address src) {
5553 assert(VM_Version::supports_popcnt(), "must support");
5554 InstructionMark im(this);
5555 emit_int8((unsigned char)0xF3);
5556 prefixq(src, dst);
5557 emit_int8((unsigned char)0x0F);
5558 emit_int8((unsigned char)0xB8);
5559 emit_operand(dst, src);
5560 }
5561
5562 void Assembler::popcntq(Register dst, Register src) {
5563 assert(VM_Version::supports_popcnt(), "must support");
5564 emit_int8((unsigned char)0xF3);
5565 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5566 emit_int8((unsigned char)0x0F);
5567 emit_int8((unsigned char)0xB8);
5568 emit_int8((unsigned char)(0xC0 | encode));
5569 }
5570
5571 void Assembler::popq(Address dst) {
5572 InstructionMark im(this);
5573 prefixq(dst);
5574 emit_int8((unsigned char)0x8F);
5575 emit_operand(rax, dst);
5576 }
5577
5578 void Assembler::pusha() { // 64bit
5579 // we have to store original rsp. ABI says that 128 bytes
5580 // below rsp are local scratch.
5581 movq(Address(rsp, -5 * wordSize), rsp);
5582
5583 subq(rsp, 16 * wordSize);
5584
5585 movq(Address(rsp, 15 * wordSize), rax);
5586 movq(Address(rsp, 14 * wordSize), rcx);
5587 movq(Address(rsp, 13 * wordSize), rdx);
5588 movq(Address(rsp, 12 * wordSize), rbx);
5589 // skip rsp
5590 movq(Address(rsp, 10 * wordSize), rbp);
5591 movq(Address(rsp, 9 * wordSize), rsi);
5592 movq(Address(rsp, 8 * wordSize), rdi);
5593 movq(Address(rsp, 7 * wordSize), r8);
5594 movq(Address(rsp, 6 * wordSize), r9);
5595 movq(Address(rsp, 5 * wordSize), r10);
5596 movq(Address(rsp, 4 * wordSize), r11);
5597 movq(Address(rsp, 3 * wordSize), r12);
5598 movq(Address(rsp, 2 * wordSize), r13);
5599 movq(Address(rsp, wordSize), r14);
5600 movq(Address(rsp, 0), r15);
5601 }
5602
5603 void Assembler::pushq(Address src) {
5604 InstructionMark im(this);
5605 prefixq(src);
5606 emit_int8((unsigned char)0xFF);
5607 emit_operand(rsi, src);
5608 }
5609
5610 void Assembler::rclq(Register dst, int imm8) {
5611 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5612 int encode = prefixq_and_encode(dst->encoding());
5613 if (imm8 == 1) {
5614 emit_int8((unsigned char)0xD1);
5615 emit_int8((unsigned char)(0xD0 | encode));
5616 } else {
5617 emit_int8((unsigned char)0xC1);
5618 emit_int8((unsigned char)(0xD0 | encode));
5619 emit_int8(imm8);
5620 }
5621 }
5622
5623 void Assembler::rcrq(Register dst, int imm8) {
5624 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5625 int encode = prefixq_and_encode(dst->encoding());
5626 if (imm8 == 1) {
5627 emit_int8((unsigned char)0xD1);
5628 emit_int8((unsigned char)(0xD8 | encode));
5629 } else {
5630 emit_int8((unsigned char)0xC1);
5631 emit_int8((unsigned char)(0xD8 | encode));
5632 emit_int8(imm8);
5633 }
5634 }
5635
5636 void Assembler::rorq(Register dst, int imm8) {
5637 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5638 int encode = prefixq_and_encode(dst->encoding());
5639 if (imm8 == 1) {
5640 emit_int8((unsigned char)0xD1);
5641 emit_int8((unsigned char)(0xC8 | encode));
5642 } else {
5643 emit_int8((unsigned char)0xC1);
5644 emit_int8((unsigned char)(0xc8 | encode));
5645 emit_int8(imm8);
5646 }
5647 }
5648
5649 void Assembler::rorxq(Register dst, Register src, int imm8) {
5650 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
5651 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, true, false);
5652 emit_int8((unsigned char)0xF0);
5653 emit_int8((unsigned char)(0xC0 | encode));
5654 emit_int8(imm8);
5655 }
5656
5657 void Assembler::sarq(Register dst, int imm8) {
5658 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5659 int encode = prefixq_and_encode(dst->encoding());
5660 if (imm8 == 1) {
5661 emit_int8((unsigned char)0xD1);
5662 emit_int8((unsigned char)(0xF8 | encode));
5663 } else {
5664 emit_int8((unsigned char)0xC1);
5665 emit_int8((unsigned char)(0xF8 | encode));
5666 emit_int8(imm8);
5667 }
5668 }
5669
5670 void Assembler::sarq(Register dst) {
5671 int encode = prefixq_and_encode(dst->encoding());
5672 emit_int8((unsigned char)0xD3);
5673 emit_int8((unsigned char)(0xF8 | encode));
5674 }
5675
5676 void Assembler::sbbq(Address dst, int32_t imm32) {
5677 InstructionMark im(this);
5678 prefixq(dst);
5679 emit_arith_operand(0x81, rbx, dst, imm32);
5680 }
5681
5682 void Assembler::sbbq(Register dst, int32_t imm32) {
5683 (void) prefixq_and_encode(dst->encoding());
5684 emit_arith(0x81, 0xD8, dst, imm32);
5685 }
5686
5687 void Assembler::sbbq(Register dst, Address src) {
5688 InstructionMark im(this);
5689 prefixq(src, dst);
5690 emit_int8(0x1B);
5691 emit_operand(dst, src);
5692 }
5693
5694 void Assembler::sbbq(Register dst, Register src) {
5695 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5696 emit_arith(0x1B, 0xC0, dst, src);
5697 }
5698
5699 void Assembler::shlq(Register dst, int imm8) {
5700 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5701 int encode = prefixq_and_encode(dst->encoding());
5702 if (imm8 == 1) {
5703 emit_int8((unsigned char)0xD1);
5704 emit_int8((unsigned char)(0xE0 | encode));
5705 } else {
5706 emit_int8((unsigned char)0xC1);
5707 emit_int8((unsigned char)(0xE0 | encode));
5708 emit_int8(imm8);
5709 }
5710 }
5711
5712 void Assembler::shlq(Register dst) {
5713 int encode = prefixq_and_encode(dst->encoding());
5714 emit_int8((unsigned char)0xD3);
5715 emit_int8((unsigned char)(0xE0 | encode));
5716 }
5717
5718 void Assembler::shrq(Register dst, int imm8) {
5719 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5720 int encode = prefixq_and_encode(dst->encoding());
5721 emit_int8((unsigned char)0xC1);
5722 emit_int8((unsigned char)(0xE8 | encode));
5723 emit_int8(imm8);
5724 }
5725
5726 void Assembler::shrq(Register dst) {
5727 int encode = prefixq_and_encode(dst->encoding());
5728 emit_int8((unsigned char)0xD3);
5729 emit_int8(0xE8 | encode);
5730 }
5731
5732 void Assembler::subq(Address dst, int32_t imm32) {
5733 InstructionMark im(this);
5734 prefixq(dst);
5735 emit_arith_operand(0x81, rbp, dst, imm32);
5736 }
5737
5738 void Assembler::subq(Address dst, Register src) {
5739 InstructionMark im(this);
5740 prefixq(dst, src);
5741 emit_int8(0x29);
5742 emit_operand(src, dst);
5743 }
5744
5745 void Assembler::subq(Register dst, int32_t imm32) {
5746 (void) prefixq_and_encode(dst->encoding());
5747 emit_arith(0x81, 0xE8, dst, imm32);
5748 }
5749
5750 // Force generation of a 4 byte immediate value even if it fits into 8bit
5751 void Assembler::subq_imm32(Register dst, int32_t imm32) {
5752 (void) prefixq_and_encode(dst->encoding());
5753 emit_arith_imm32(0x81, 0xE8, dst, imm32);
5754 }
5755
5756 void Assembler::subq(Register dst, Address src) {
5757 InstructionMark im(this);
5758 prefixq(src, dst);
5759 emit_int8(0x2B);
5760 emit_operand(dst, src);
5761 }
5762
5763 void Assembler::subq(Register dst, Register src) {
5764 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5765 emit_arith(0x2B, 0xC0, dst, src);
5766 }
5767
5768 void Assembler::testq(Register dst, int32_t imm32) {
5769 // not using emit_arith because test
5770 // doesn't support sign-extension of
5771 // 8bit operands
5772 int encode = dst->encoding();
5773 if (encode == 0) {
5774 prefix(REX_W);
5775 emit_int8((unsigned char)0xA9);
5776 } else {
5777 encode = prefixq_and_encode(encode);
5778 emit_int8((unsigned char)0xF7);
5779 emit_int8((unsigned char)(0xC0 | encode));
5780 }
5781 emit_int32(imm32);
5782 }
5783
5784 void Assembler::testq(Register dst, Register src) {
5785 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5786 emit_arith(0x85, 0xC0, dst, src);
5787 }
5788
5789 void Assembler::xaddq(Address dst, Register src) {
5790 InstructionMark im(this);
5791 prefixq(dst, src);
5792 emit_int8(0x0F);
5793 emit_int8((unsigned char)0xC1);
5794 emit_operand(src, dst);
5795 }
5796
5797 void Assembler::xchgq(Register dst, Address src) {
5798 InstructionMark im(this);
5799 prefixq(src, dst);
5800 emit_int8((unsigned char)0x87);
5801 emit_operand(dst, src);
5802 }
5803
5804 void Assembler::xchgq(Register dst, Register src) {
5805 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
5806 emit_int8((unsigned char)0x87);
5807 emit_int8((unsigned char)(0xc0 | encode));
5808 }
5809
5810 void Assembler::xorq(Register dst, Register src) {
5811 (void) prefixq_and_encode(dst->encoding(), src->encoding());
5812 emit_arith(0x33, 0xC0, dst, src);
5813 }
5814
5815 void Assembler::xorq(Register dst, Address src) {
5816 InstructionMark im(this);
5817 prefixq(src, dst);
5818 emit_int8(0x33);
5819 emit_operand(dst, src);
5820 }
5821
5822 #endif // !LP64