2110 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2111 }
2112 const int Matcher::min_vector_size(const BasicType bt) {
2113 // For the moment limit the vector size to 8 bytes
2114 int size = 8 / type2aelembytes(bt);
2115 if (size < 2) size = 2;
2116 return size;
2117 }
2118
2119 // Vector ideal reg.
2120 const uint Matcher::vector_ideal_reg(int len) {
2121 switch(len) {
2122 case 8: return Op_VecD;
2123 case 16: return Op_VecX;
2124 }
2125 ShouldNotReachHere();
2126 return 0;
2127 }
2128
2129 const uint Matcher::vector_shift_count_ideal_reg(int size) {
2130 return Op_VecX;
2131 }
2132
2133 // AES support not yet implemented
2134 const bool Matcher::pass_original_key_for_aes() {
2135 return false;
2136 }
2137
2138 // x86 supports misaligned vectors store/load.
2139 const bool Matcher::misaligned_vectors_ok() {
2140 return !AlignVector; // can be changed by flag
2141 }
2142
2143 // false => size gets scaled to BytesPerLong, ok.
2144 const bool Matcher::init_array_count_is_in_bytes = false;
2145
2146 // Use conditional move (CMOVL)
2147 const int Matcher::long_cmove_cost() {
2148 // long cmoves are no more expensive than int cmoves
2149 return 0;
2150 }
16501 as_FloatRegister($src2$$reg));
16502 %}
16503 ins_pipe(vlogical64);
16504 %}
16505
16506 instruct vxor16B(vecX dst, vecX src1, vecX src2)
16507 %{
16508 predicate(n->as_Vector()->length_in_bytes() == 16);
16509 match(Set dst (XorV src1 src2));
16510 ins_cost(INSN_COST);
16511 format %{ "xor $dst,$src1,$src2\t# vector (16B)" %}
16512 ins_encode %{
16513 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16514 as_FloatRegister($src1$$reg),
16515 as_FloatRegister($src2$$reg));
16516 %}
16517 ins_pipe(vlogical128);
16518 %}
16519
16520 // ------------------------------ Shift ---------------------------------------
16521
16522 instruct vshiftcntL(vecX dst, iRegIorL2I cnt) %{
16523 match(Set dst (LShiftCntV cnt));
16524 format %{ "dup $dst, $cnt\t# shift count (vecX)" %}
16525 ins_encode %{
16526 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
16527 %}
16528 ins_pipe(vdup_reg_reg128);
16529 %}
16530
16531 // Right shifts on aarch64 SIMD are implemented as left shift by -ve amount
16532 instruct vshiftcntR(vecX dst, iRegIorL2I cnt) %{
16533 match(Set dst (RShiftCntV cnt));
16534 format %{ "dup $dst, $cnt\t# shift count (vecX)\n\tneg $dst, $dst\t T16B" %}
16535 ins_encode %{
16536 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
16537 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
16538 %}
16539 ins_pipe(vdup_reg_reg128);
16540 %}
16541
16542 instruct vsll8B(vecD dst, vecD src, vecX shift) %{
16543 predicate(n->as_Vector()->length() == 4 ||
16544 n->as_Vector()->length() == 8);
16545 match(Set dst (LShiftVB src shift));
16546 match(Set dst (RShiftVB src shift));
16547 ins_cost(INSN_COST);
16548 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %}
16549 ins_encode %{
16550 __ sshl(as_FloatRegister($dst$$reg), __ T8B,
16551 as_FloatRegister($src$$reg),
16552 as_FloatRegister($shift$$reg));
16553 %}
16554 ins_pipe(vshift64);
16555 %}
16556
16557 instruct vsll16B(vecX dst, vecX src, vecX shift) %{
16558 predicate(n->as_Vector()->length() == 16);
16559 match(Set dst (LShiftVB src shift));
16560 match(Set dst (RShiftVB src shift));
16561 ins_cost(INSN_COST);
16562 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %}
16563 ins_encode %{
16564 __ sshl(as_FloatRegister($dst$$reg), __ T16B,
16565 as_FloatRegister($src$$reg),
16566 as_FloatRegister($shift$$reg));
16567 %}
16568 ins_pipe(vshift128);
16569 %}
16570
16571 instruct vsrl8B(vecD dst, vecD src, vecX shift) %{
16572 predicate(n->as_Vector()->length() == 4 ||
16573 n->as_Vector()->length() == 8);
16574 match(Set dst (URShiftVB src shift));
16575 ins_cost(INSN_COST);
16576 format %{ "ushl $dst,$src,$shift\t# vector (8B)" %}
16577 ins_encode %{
16578 __ ushl(as_FloatRegister($dst$$reg), __ T8B,
16579 as_FloatRegister($src$$reg),
16580 as_FloatRegister($shift$$reg));
16581 %}
16582 ins_pipe(vshift64);
16583 %}
16584
16585 instruct vsrl16B(vecX dst, vecX src, vecX shift) %{
16586 predicate(n->as_Vector()->length() == 16);
16587 match(Set dst (URShiftVB src shift));
16588 ins_cost(INSN_COST);
16589 format %{ "ushl $dst,$src,$shift\t# vector (16B)" %}
16590 ins_encode %{
16591 __ ushl(as_FloatRegister($dst$$reg), __ T16B,
16592 as_FloatRegister($src$$reg),
16593 as_FloatRegister($shift$$reg));
16594 %}
16595 ins_pipe(vshift128);
16596 %}
16597
16598 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{
16599 predicate(n->as_Vector()->length() == 4 ||
16600 n->as_Vector()->length() == 8);
16601 match(Set dst (LShiftVB src shift));
16602 ins_cost(INSN_COST);
16603 format %{ "shl $dst, $src, $shift\t# vector (8B)" %}
16604 ins_encode %{
16605 int sh = (int)$shift$$constant;
16606 if (sh >= 8) {
16607 __ eor(as_FloatRegister($dst$$reg), __ T8B,
16608 as_FloatRegister($src$$reg),
16609 as_FloatRegister($src$$reg));
16610 } else {
16611 __ shl(as_FloatRegister($dst$$reg), __ T8B,
16612 as_FloatRegister($src$$reg), sh);
16613 }
16685
16686 instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
16687 predicate(n->as_Vector()->length() == 16);
16688 match(Set dst (URShiftVB src shift));
16689 ins_cost(INSN_COST);
16690 format %{ "ushr $dst, $src, $shift\t# vector (16B)" %}
16691 ins_encode %{
16692 int sh = (int)$shift$$constant;
16693 if (sh >= 8) {
16694 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16695 as_FloatRegister($src$$reg),
16696 as_FloatRegister($src$$reg));
16697 } else {
16698 __ ushr(as_FloatRegister($dst$$reg), __ T16B,
16699 as_FloatRegister($src$$reg), sh);
16700 }
16701 %}
16702 ins_pipe(vshift128_imm);
16703 %}
16704
16705 instruct vsll4S(vecD dst, vecD src, vecX shift) %{
16706 predicate(n->as_Vector()->length() == 2 ||
16707 n->as_Vector()->length() == 4);
16708 match(Set dst (LShiftVS src shift));
16709 match(Set dst (RShiftVS src shift));
16710 ins_cost(INSN_COST);
16711 format %{ "sshl $dst,$src,$shift\t# vector (4H)" %}
16712 ins_encode %{
16713 __ sshl(as_FloatRegister($dst$$reg), __ T4H,
16714 as_FloatRegister($src$$reg),
16715 as_FloatRegister($shift$$reg));
16716 %}
16717 ins_pipe(vshift64);
16718 %}
16719
16720 instruct vsll8S(vecX dst, vecX src, vecX shift) %{
16721 predicate(n->as_Vector()->length() == 8);
16722 match(Set dst (LShiftVS src shift));
16723 match(Set dst (RShiftVS src shift));
16724 ins_cost(INSN_COST);
16725 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %}
16726 ins_encode %{
16727 __ sshl(as_FloatRegister($dst$$reg), __ T8H,
16728 as_FloatRegister($src$$reg),
16729 as_FloatRegister($shift$$reg));
16730 %}
16731 ins_pipe(vshift128);
16732 %}
16733
16734 instruct vsrl4S(vecD dst, vecD src, vecX shift) %{
16735 predicate(n->as_Vector()->length() == 2 ||
16736 n->as_Vector()->length() == 4);
16737 match(Set dst (URShiftVS src shift));
16738 ins_cost(INSN_COST);
16739 format %{ "ushl $dst,$src,$shift\t# vector (4H)" %}
16740 ins_encode %{
16741 __ ushl(as_FloatRegister($dst$$reg), __ T4H,
16742 as_FloatRegister($src$$reg),
16743 as_FloatRegister($shift$$reg));
16744 %}
16745 ins_pipe(vshift64);
16746 %}
16747
16748 instruct vsrl8S(vecX dst, vecX src, vecX shift) %{
16749 predicate(n->as_Vector()->length() == 8);
16750 match(Set dst (URShiftVS src shift));
16751 ins_cost(INSN_COST);
16752 format %{ "ushl $dst,$src,$shift\t# vector (8H)" %}
16753 ins_encode %{
16754 __ ushl(as_FloatRegister($dst$$reg), __ T8H,
16755 as_FloatRegister($src$$reg),
16756 as_FloatRegister($shift$$reg));
16757 %}
16758 ins_pipe(vshift128);
16759 %}
16760
16761 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{
16762 predicate(n->as_Vector()->length() == 2 ||
16763 n->as_Vector()->length() == 4);
16764 match(Set dst (LShiftVS src shift));
16765 ins_cost(INSN_COST);
16766 format %{ "shl $dst, $src, $shift\t# vector (4H)" %}
16767 ins_encode %{
16768 int sh = (int)$shift$$constant;
16769 if (sh >= 16) {
16770 __ eor(as_FloatRegister($dst$$reg), __ T8B,
16771 as_FloatRegister($src$$reg),
16772 as_FloatRegister($src$$reg));
16773 } else {
16774 __ shl(as_FloatRegister($dst$$reg), __ T4H,
16775 as_FloatRegister($src$$reg), sh);
16776 }
16848
16849 instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
16850 predicate(n->as_Vector()->length() == 8);
16851 match(Set dst (URShiftVS src shift));
16852 ins_cost(INSN_COST);
16853 format %{ "ushr $dst, $src, $shift\t# vector (8H)" %}
16854 ins_encode %{
16855 int sh = (int)$shift$$constant;
16856 if (sh >= 16) {
16857 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16858 as_FloatRegister($src$$reg),
16859 as_FloatRegister($src$$reg));
16860 } else {
16861 __ ushr(as_FloatRegister($dst$$reg), __ T8H,
16862 as_FloatRegister($src$$reg), sh);
16863 }
16864 %}
16865 ins_pipe(vshift128_imm);
16866 %}
16867
16868 instruct vsll2I(vecD dst, vecD src, vecX shift) %{
16869 predicate(n->as_Vector()->length() == 2);
16870 match(Set dst (LShiftVI src shift));
16871 match(Set dst (RShiftVI src shift));
16872 ins_cost(INSN_COST);
16873 format %{ "sshl $dst,$src,$shift\t# vector (2S)" %}
16874 ins_encode %{
16875 __ sshl(as_FloatRegister($dst$$reg), __ T2S,
16876 as_FloatRegister($src$$reg),
16877 as_FloatRegister($shift$$reg));
16878 %}
16879 ins_pipe(vshift64);
16880 %}
16881
16882 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
16883 predicate(n->as_Vector()->length() == 4);
16884 match(Set dst (LShiftVI src shift));
16885 match(Set dst (RShiftVI src shift));
16886 ins_cost(INSN_COST);
16887 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %}
16888 ins_encode %{
16889 __ sshl(as_FloatRegister($dst$$reg), __ T4S,
16890 as_FloatRegister($src$$reg),
16891 as_FloatRegister($shift$$reg));
16892 %}
16893 ins_pipe(vshift128);
16894 %}
16895
16896 instruct vsrl2I(vecD dst, vecD src, vecX shift) %{
16897 predicate(n->as_Vector()->length() == 2);
16898 match(Set dst (URShiftVI src shift));
16899 ins_cost(INSN_COST);
16900 format %{ "ushl $dst,$src,$shift\t# vector (2S)" %}
16901 ins_encode %{
16902 __ ushl(as_FloatRegister($dst$$reg), __ T2S,
16903 as_FloatRegister($src$$reg),
16904 as_FloatRegister($shift$$reg));
16905 %}
16906 ins_pipe(vshift64);
16907 %}
16908
16909 instruct vsrl4I(vecX dst, vecX src, vecX shift) %{
16910 predicate(n->as_Vector()->length() == 4);
16911 match(Set dst (URShiftVI src shift));
16912 ins_cost(INSN_COST);
16913 format %{ "ushl $dst,$src,$shift\t# vector (4S)" %}
16914 ins_encode %{
16915 __ ushl(as_FloatRegister($dst$$reg), __ T4S,
16916 as_FloatRegister($src$$reg),
16917 as_FloatRegister($shift$$reg));
16918 %}
16919 ins_pipe(vshift128);
16920 %}
16921
16922 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
16923 predicate(n->as_Vector()->length() == 2);
16924 match(Set dst (LShiftVI src shift));
16925 ins_cost(INSN_COST);
16926 format %{ "shl $dst, $src, $shift\t# vector (2S)" %}
16927 ins_encode %{
16928 __ shl(as_FloatRegister($dst$$reg), __ T2S,
16929 as_FloatRegister($src$$reg),
16930 (int)$shift$$constant);
16931 %}
16932 ins_pipe(vshift64_imm);
16933 %}
16934
16935 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
16936 predicate(n->as_Vector()->length() == 4);
16937 match(Set dst (LShiftVI src shift));
16983 %}
16984 ins_pipe(vshift64_imm);
16985 %}
16986
16987 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
16988 predicate(n->as_Vector()->length() == 4);
16989 match(Set dst (URShiftVI src shift));
16990 ins_cost(INSN_COST);
16991 format %{ "ushr $dst, $src, $shift\t# vector (4S)" %}
16992 ins_encode %{
16993 __ ushr(as_FloatRegister($dst$$reg), __ T4S,
16994 as_FloatRegister($src$$reg),
16995 (int)$shift$$constant);
16996 %}
16997 ins_pipe(vshift128_imm);
16998 %}
16999
17000 instruct vsll2L(vecX dst, vecX src, vecX shift) %{
17001 predicate(n->as_Vector()->length() == 2);
17002 match(Set dst (LShiftVL src shift));
17003 match(Set dst (RShiftVL src shift));
17004 ins_cost(INSN_COST);
17005 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %}
17006 ins_encode %{
17007 __ sshl(as_FloatRegister($dst$$reg), __ T2D,
17008 as_FloatRegister($src$$reg),
17009 as_FloatRegister($shift$$reg));
17010 %}
17011 ins_pipe(vshift128);
17012 %}
17013
17014 instruct vsrl2L(vecX dst, vecX src, vecX shift) %{
17015 predicate(n->as_Vector()->length() == 2);
17016 match(Set dst (URShiftVL src shift));
17017 ins_cost(INSN_COST);
17018 format %{ "ushl $dst,$src,$shift\t# vector (2D)" %}
17019 ins_encode %{
17020 __ ushl(as_FloatRegister($dst$$reg), __ T2D,
17021 as_FloatRegister($src$$reg),
17022 as_FloatRegister($shift$$reg));
17023 %}
17024 ins_pipe(vshift128);
17025 %}
17026
17027 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
17028 predicate(n->as_Vector()->length() == 2);
17029 match(Set dst (LShiftVL src shift));
17030 ins_cost(INSN_COST);
17031 format %{ "shl $dst, $src, $shift\t# vector (2D)" %}
17032 ins_encode %{
17033 __ shl(as_FloatRegister($dst$$reg), __ T2D,
17034 as_FloatRegister($src$$reg),
17035 (int)$shift$$constant);
17036 %}
17037 ins_pipe(vshift128_imm);
17038 %}
17039
17040 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
17041 predicate(n->as_Vector()->length() == 2);
17042 match(Set dst (RShiftVL src shift));
|
2110 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2111 }
2112 const int Matcher::min_vector_size(const BasicType bt) {
2113 // For the moment limit the vector size to 8 bytes
2114 int size = 8 / type2aelembytes(bt);
2115 if (size < 2) size = 2;
2116 return size;
2117 }
2118
2119 // Vector ideal reg.
2120 const uint Matcher::vector_ideal_reg(int len) {
2121 switch(len) {
2122 case 8: return Op_VecD;
2123 case 16: return Op_VecX;
2124 }
2125 ShouldNotReachHere();
2126 return 0;
2127 }
2128
2129 const uint Matcher::vector_shift_count_ideal_reg(int size) {
2130 assert(MaxVectorSize >= size, "Length isn't supported");
2131 switch(size) {
2132 case 8: return Op_VecD;
2133 case 16: return Op_VecX;
2134 }
2135 ShouldNotReachHere();
2136 return 0;
2137 }
2138
2139 // AES support not yet implemented
2140 const bool Matcher::pass_original_key_for_aes() {
2141 return false;
2142 }
2143
2144 // x86 supports misaligned vectors store/load.
2145 const bool Matcher::misaligned_vectors_ok() {
2146 return !AlignVector; // can be changed by flag
2147 }
2148
2149 // false => size gets scaled to BytesPerLong, ok.
2150 const bool Matcher::init_array_count_is_in_bytes = false;
2151
2152 // Use conditional move (CMOVL)
2153 const int Matcher::long_cmove_cost() {
2154 // long cmoves are no more expensive than int cmoves
2155 return 0;
2156 }
16507 as_FloatRegister($src2$$reg));
16508 %}
16509 ins_pipe(vlogical64);
16510 %}
16511
16512 instruct vxor16B(vecX dst, vecX src1, vecX src2)
16513 %{
16514 predicate(n->as_Vector()->length_in_bytes() == 16);
16515 match(Set dst (XorV src1 src2));
16516 ins_cost(INSN_COST);
16517 format %{ "xor $dst,$src1,$src2\t# vector (16B)" %}
16518 ins_encode %{
16519 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16520 as_FloatRegister($src1$$reg),
16521 as_FloatRegister($src2$$reg));
16522 %}
16523 ins_pipe(vlogical128);
16524 %}
16525
16526 // ------------------------------ Shift ---------------------------------------
16527 instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{
16528 predicate(n->as_Vector()->length_in_bytes() == 8);
16529 match(Set dst (LShiftCntV cnt));
16530 match(Set dst (RShiftCntV cnt));
16531 format %{ "dup $dst, $cnt\t# shift count vector (8B)" %}
16532 ins_encode %{
16533 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg));
16534 %}
16535 ins_pipe(vdup_reg_reg64);
16536 %}
16537
16538 instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{
16539 predicate(n->as_Vector()->length_in_bytes() == 16);
16540 match(Set dst (LShiftCntV cnt));
16541 match(Set dst (RShiftCntV cnt));
16542 format %{ "dup $dst, $cnt\t# shift count vector (16B)" %}
16543 ins_encode %{
16544 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
16545 %}
16546 ins_pipe(vdup_reg_reg128);
16547 %}
16548
16549 instruct vsll8B(vecD dst, vecD src, vecD shift) %{
16550 predicate(n->as_Vector()->length() == 4 ||
16551 n->as_Vector()->length() == 8);
16552 match(Set dst (LShiftVB src shift));
16553 ins_cost(INSN_COST);
16554 format %{ "sshl $dst,$src,$shift\t# vector (8B)" %}
16555 ins_encode %{
16556 __ sshl(as_FloatRegister($dst$$reg), __ T8B,
16557 as_FloatRegister($src$$reg),
16558 as_FloatRegister($shift$$reg));
16559 %}
16560 ins_pipe(vshift64);
16561 %}
16562
16563 instruct vsll16B(vecX dst, vecX src, vecX shift) %{
16564 predicate(n->as_Vector()->length() == 16);
16565 match(Set dst (LShiftVB src shift));
16566 ins_cost(INSN_COST);
16567 format %{ "sshl $dst,$src,$shift\t# vector (16B)" %}
16568 ins_encode %{
16569 __ sshl(as_FloatRegister($dst$$reg), __ T16B,
16570 as_FloatRegister($src$$reg),
16571 as_FloatRegister($shift$$reg));
16572 %}
16573 ins_pipe(vshift128);
16574 %}
16575
16576 // Right shifts with vector shift count on aarch64 SIMD are implemented
16577 // as left shift by negative shift count.
16578 // There are two cases for vector shift count.
16579 //
16580 // Case 1: The vector shift count is from replication.
16581 // | |
16582 // LoadVector RShiftCntV
16583 // | /
16584 // RShiftVI
16585 // Note: In inner loop, multiple neg instructions are used, which can be
16586 // moved to outer loop and merge into one neg instruction.
16587 //
16588 // Case 2: The vector shift count is from loading.
16589 // This case isn't supported by middle-end now. But it's supported by
16590 // panama/vectorIntrinsics(JEP 338: Vector API).
16591 // | |
16592 // LoadVector LoadVector
16593 // | /
16594 // RShiftVI
16595 //
16596
16597 instruct vsra8B(vecD dst, vecD src, vecD shift, vecD tmp) %{
16598 predicate(n->as_Vector()->length() == 4 ||
16599 n->as_Vector()->length() == 8);
16600 match(Set dst (RShiftVB src shift));
16601 ins_cost(INSN_COST);
16602 effect(TEMP tmp);
16603 format %{ "negr $tmp,$shift\t"
16604 "sshl $dst,$src,$tmp\t# vector (8B)" %}
16605 ins_encode %{
16606 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
16607 as_FloatRegister($shift$$reg));
16608 __ sshl(as_FloatRegister($dst$$reg), __ T8B,
16609 as_FloatRegister($src$$reg),
16610 as_FloatRegister($tmp$$reg));
16611 %}
16612 ins_pipe(vshift64);
16613 %}
16614
16615 instruct vsra16B(vecX dst, vecX src, vecX shift, vecX tmp) %{
16616 predicate(n->as_Vector()->length() == 16);
16617 match(Set dst (RShiftVB src shift));
16618 ins_cost(INSN_COST);
16619 effect(TEMP tmp);
16620 format %{ "negr $tmp,$shift\t"
16621 "sshl $dst,$src,$tmp\t# vector (16B)" %}
16622 ins_encode %{
16623 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
16624 as_FloatRegister($shift$$reg));
16625 __ sshl(as_FloatRegister($dst$$reg), __ T16B,
16626 as_FloatRegister($src$$reg),
16627 as_FloatRegister($tmp$$reg));
16628 %}
16629 ins_pipe(vshift128);
16630 %}
16631
16632 instruct vsrl8B(vecD dst, vecD src, vecD shift, vecD tmp) %{
16633 predicate(n->as_Vector()->length() == 4 ||
16634 n->as_Vector()->length() == 8);
16635 match(Set dst (URShiftVB src shift));
16636 ins_cost(INSN_COST);
16637 effect(TEMP tmp);
16638 format %{ "negr $tmp,$shift\t"
16639 "ushl $dst,$src,$tmp\t# vector (8B)" %}
16640 ins_encode %{
16641 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
16642 as_FloatRegister($shift$$reg));
16643 __ ushl(as_FloatRegister($dst$$reg), __ T8B,
16644 as_FloatRegister($src$$reg),
16645 as_FloatRegister($tmp$$reg));
16646 %}
16647 ins_pipe(vshift64);
16648 %}
16649
16650 instruct vsrl16B(vecX dst, vecX src, vecX shift, vecX tmp) %{
16651 predicate(n->as_Vector()->length() == 16);
16652 match(Set dst (URShiftVB src shift));
16653 ins_cost(INSN_COST);
16654 effect(TEMP tmp);
16655 format %{ "negr $tmp,$shift\t"
16656 "ushl $dst,$src,$tmp\t# vector (16B)" %}
16657 ins_encode %{
16658 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
16659 as_FloatRegister($shift$$reg));
16660 __ ushl(as_FloatRegister($dst$$reg), __ T16B,
16661 as_FloatRegister($src$$reg),
16662 as_FloatRegister($tmp$$reg));
16663 %}
16664 ins_pipe(vshift128);
16665 %}
16666
16667 instruct vsll8B_imm(vecD dst, vecD src, immI shift) %{
16668 predicate(n->as_Vector()->length() == 4 ||
16669 n->as_Vector()->length() == 8);
16670 match(Set dst (LShiftVB src shift));
16671 ins_cost(INSN_COST);
16672 format %{ "shl $dst, $src, $shift\t# vector (8B)" %}
16673 ins_encode %{
16674 int sh = (int)$shift$$constant;
16675 if (sh >= 8) {
16676 __ eor(as_FloatRegister($dst$$reg), __ T8B,
16677 as_FloatRegister($src$$reg),
16678 as_FloatRegister($src$$reg));
16679 } else {
16680 __ shl(as_FloatRegister($dst$$reg), __ T8B,
16681 as_FloatRegister($src$$reg), sh);
16682 }
16754
16755 instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
16756 predicate(n->as_Vector()->length() == 16);
16757 match(Set dst (URShiftVB src shift));
16758 ins_cost(INSN_COST);
16759 format %{ "ushr $dst, $src, $shift\t# vector (16B)" %}
16760 ins_encode %{
16761 int sh = (int)$shift$$constant;
16762 if (sh >= 8) {
16763 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16764 as_FloatRegister($src$$reg),
16765 as_FloatRegister($src$$reg));
16766 } else {
16767 __ ushr(as_FloatRegister($dst$$reg), __ T16B,
16768 as_FloatRegister($src$$reg), sh);
16769 }
16770 %}
16771 ins_pipe(vshift128_imm);
16772 %}
16773
16774 instruct vsll4S(vecD dst, vecD src, vecD shift) %{
16775 predicate(n->as_Vector()->length() == 2 ||
16776 n->as_Vector()->length() == 4);
16777 match(Set dst (LShiftVS src shift));
16778 ins_cost(INSN_COST);
16779 format %{ "sshl $dst,$src,$shift\t# vector (4H)" %}
16780 ins_encode %{
16781 __ sshl(as_FloatRegister($dst$$reg), __ T4H,
16782 as_FloatRegister($src$$reg),
16783 as_FloatRegister($shift$$reg));
16784 %}
16785 ins_pipe(vshift64);
16786 %}
16787
16788 instruct vsll8S(vecX dst, vecX src, vecX shift) %{
16789 predicate(n->as_Vector()->length() == 8);
16790 match(Set dst (LShiftVS src shift));
16791 ins_cost(INSN_COST);
16792 format %{ "sshl $dst,$src,$shift\t# vector (8H)" %}
16793 ins_encode %{
16794 __ sshl(as_FloatRegister($dst$$reg), __ T8H,
16795 as_FloatRegister($src$$reg),
16796 as_FloatRegister($shift$$reg));
16797 %}
16798 ins_pipe(vshift128);
16799 %}
16800
16801 instruct vsra4S(vecD dst, vecD src, vecD shift, vecD tmp) %{
16802 predicate(n->as_Vector()->length() == 2 ||
16803 n->as_Vector()->length() == 4);
16804 match(Set dst (RShiftVS src shift));
16805 ins_cost(INSN_COST);
16806 effect(TEMP tmp);
16807 format %{ "negr $tmp,$shift\t"
16808 "sshl $dst,$src,$tmp\t# vector (4H)" %}
16809 ins_encode %{
16810 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
16811 as_FloatRegister($shift$$reg));
16812 __ sshl(as_FloatRegister($dst$$reg), __ T4H,
16813 as_FloatRegister($src$$reg),
16814 as_FloatRegister($tmp$$reg));
16815 %}
16816 ins_pipe(vshift64);
16817 %}
16818
16819 instruct vsra8S(vecX dst, vecX src, vecX shift, vecX tmp) %{
16820 predicate(n->as_Vector()->length() == 8);
16821 match(Set dst (RShiftVS src shift));
16822 ins_cost(INSN_COST);
16823 effect(TEMP tmp);
16824 format %{ "negr $tmp,$shift\t"
16825 "sshl $dst,$src,$tmp\t# vector (8H)" %}
16826 ins_encode %{
16827 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
16828 as_FloatRegister($shift$$reg));
16829 __ sshl(as_FloatRegister($dst$$reg), __ T8H,
16830 as_FloatRegister($src$$reg),
16831 as_FloatRegister($tmp$$reg));
16832 %}
16833 ins_pipe(vshift128);
16834 %}
16835
16836 instruct vsrl4S(vecD dst, vecD src, vecD shift, vecD tmp) %{
16837 predicate(n->as_Vector()->length() == 2 ||
16838 n->as_Vector()->length() == 4);
16839 match(Set dst (URShiftVS src shift));
16840 ins_cost(INSN_COST);
16841 effect(TEMP tmp);
16842 format %{ "negr $tmp,$shift\t"
16843 "ushl $dst,$src,$tmp\t# vector (4H)" %}
16844 ins_encode %{
16845 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
16846 as_FloatRegister($shift$$reg));
16847 __ ushl(as_FloatRegister($dst$$reg), __ T4H,
16848 as_FloatRegister($src$$reg),
16849 as_FloatRegister($tmp$$reg));
16850 %}
16851 ins_pipe(vshift64);
16852 %}
16853
16854 instruct vsrl8S(vecX dst, vecX src, vecX shift, vecX tmp) %{
16855 predicate(n->as_Vector()->length() == 8);
16856 match(Set dst (URShiftVS src shift));
16857 ins_cost(INSN_COST);
16858 effect(TEMP tmp);
16859 format %{ "negr $tmp,$shift\t"
16860 "ushl $dst,$src,$tmp\t# vector (8H)" %}
16861 ins_encode %{
16862 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
16863 as_FloatRegister($shift$$reg));
16864 __ ushl(as_FloatRegister($dst$$reg), __ T8H,
16865 as_FloatRegister($src$$reg),
16866 as_FloatRegister($tmp$$reg));
16867 %}
16868 ins_pipe(vshift128);
16869 %}
16870
16871 instruct vsll4S_imm(vecD dst, vecD src, immI shift) %{
16872 predicate(n->as_Vector()->length() == 2 ||
16873 n->as_Vector()->length() == 4);
16874 match(Set dst (LShiftVS src shift));
16875 ins_cost(INSN_COST);
16876 format %{ "shl $dst, $src, $shift\t# vector (4H)" %}
16877 ins_encode %{
16878 int sh = (int)$shift$$constant;
16879 if (sh >= 16) {
16880 __ eor(as_FloatRegister($dst$$reg), __ T8B,
16881 as_FloatRegister($src$$reg),
16882 as_FloatRegister($src$$reg));
16883 } else {
16884 __ shl(as_FloatRegister($dst$$reg), __ T4H,
16885 as_FloatRegister($src$$reg), sh);
16886 }
16958
16959 instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
16960 predicate(n->as_Vector()->length() == 8);
16961 match(Set dst (URShiftVS src shift));
16962 ins_cost(INSN_COST);
16963 format %{ "ushr $dst, $src, $shift\t# vector (8H)" %}
16964 ins_encode %{
16965 int sh = (int)$shift$$constant;
16966 if (sh >= 16) {
16967 __ eor(as_FloatRegister($dst$$reg), __ T16B,
16968 as_FloatRegister($src$$reg),
16969 as_FloatRegister($src$$reg));
16970 } else {
16971 __ ushr(as_FloatRegister($dst$$reg), __ T8H,
16972 as_FloatRegister($src$$reg), sh);
16973 }
16974 %}
16975 ins_pipe(vshift128_imm);
16976 %}
16977
16978 instruct vsll2I(vecD dst, vecD src, vecD shift) %{
16979 predicate(n->as_Vector()->length() == 2);
16980 match(Set dst (LShiftVI src shift));
16981 ins_cost(INSN_COST);
16982 format %{ "sshl $dst,$src,$shift\t# vector (2S)" %}
16983 ins_encode %{
16984 __ sshl(as_FloatRegister($dst$$reg), __ T2S,
16985 as_FloatRegister($src$$reg),
16986 as_FloatRegister($shift$$reg));
16987 %}
16988 ins_pipe(vshift64);
16989 %}
16990
16991 instruct vsll4I(vecX dst, vecX src, vecX shift) %{
16992 predicate(n->as_Vector()->length() == 4);
16993 match(Set dst (LShiftVI src shift));
16994 ins_cost(INSN_COST);
16995 format %{ "sshl $dst,$src,$shift\t# vector (4S)" %}
16996 ins_encode %{
16997 __ sshl(as_FloatRegister($dst$$reg), __ T4S,
16998 as_FloatRegister($src$$reg),
16999 as_FloatRegister($shift$$reg));
17000 %}
17001 ins_pipe(vshift128);
17002 %}
17003
17004 instruct vsra2I(vecD dst, vecD src, vecD shift, vecD tmp) %{
17005 predicate(n->as_Vector()->length() == 2);
17006 match(Set dst (RShiftVI src shift));
17007 ins_cost(INSN_COST);
17008 effect(TEMP tmp);
17009 format %{ "negr $tmp,$shift\t"
17010 "sshl $dst,$src,$tmp\t# vector (2S)" %}
17011 ins_encode %{
17012 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
17013 as_FloatRegister($shift$$reg));
17014 __ sshl(as_FloatRegister($dst$$reg), __ T2S,
17015 as_FloatRegister($src$$reg),
17016 as_FloatRegister($tmp$$reg));
17017 %}
17018 ins_pipe(vshift64);
17019 %}
17020
17021 instruct vsra4I(vecX dst, vecX src, vecX shift, vecX tmp) %{
17022 predicate(n->as_Vector()->length() == 4);
17023 match(Set dst (RShiftVI src shift));
17024 ins_cost(INSN_COST);
17025 effect(TEMP tmp);
17026 format %{ "negr $tmp,$shift\t"
17027 "sshl $dst,$src,$tmp\t# vector (4S)" %}
17028 ins_encode %{
17029 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
17030 as_FloatRegister($shift$$reg));
17031 __ sshl(as_FloatRegister($dst$$reg), __ T4S,
17032 as_FloatRegister($src$$reg),
17033 as_FloatRegister($tmp$$reg));
17034 %}
17035 ins_pipe(vshift128);
17036 %}
17037
17038 instruct vsrl2I(vecD dst, vecD src, vecD shift, vecD tmp) %{
17039 predicate(n->as_Vector()->length() == 2);
17040 match(Set dst (URShiftVI src shift));
17041 ins_cost(INSN_COST);
17042 effect(TEMP tmp);
17043 format %{ "negr $tmp,$shift\t"
17044 "ushl $dst,$src,$tmp\t# vector (2S)" %}
17045 ins_encode %{
17046 __ negr(as_FloatRegister($tmp$$reg), __ T8B,
17047 as_FloatRegister($shift$$reg));
17048 __ ushl(as_FloatRegister($dst$$reg), __ T2S,
17049 as_FloatRegister($src$$reg),
17050 as_FloatRegister($tmp$$reg));
17051 %}
17052 ins_pipe(vshift64);
17053 %}
17054
17055 instruct vsrl4I(vecX dst, vecX src, vecX shift, vecX tmp) %{
17056 predicate(n->as_Vector()->length() == 4);
17057 match(Set dst (URShiftVI src shift));
17058 ins_cost(INSN_COST);
17059 effect(TEMP tmp);
17060 format %{ "negr $tmp,$shift\t"
17061 "ushl $dst,$src,$tmp\t# vector (4S)" %}
17062 ins_encode %{
17063 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
17064 as_FloatRegister($shift$$reg));
17065 __ ushl(as_FloatRegister($dst$$reg), __ T4S,
17066 as_FloatRegister($src$$reg),
17067 as_FloatRegister($tmp$$reg));
17068 %}
17069 ins_pipe(vshift128);
17070 %}
17071
17072 instruct vsll2I_imm(vecD dst, vecD src, immI shift) %{
17073 predicate(n->as_Vector()->length() == 2);
17074 match(Set dst (LShiftVI src shift));
17075 ins_cost(INSN_COST);
17076 format %{ "shl $dst, $src, $shift\t# vector (2S)" %}
17077 ins_encode %{
17078 __ shl(as_FloatRegister($dst$$reg), __ T2S,
17079 as_FloatRegister($src$$reg),
17080 (int)$shift$$constant);
17081 %}
17082 ins_pipe(vshift64_imm);
17083 %}
17084
17085 instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
17086 predicate(n->as_Vector()->length() == 4);
17087 match(Set dst (LShiftVI src shift));
17133 %}
17134 ins_pipe(vshift64_imm);
17135 %}
17136
17137 instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
17138 predicate(n->as_Vector()->length() == 4);
17139 match(Set dst (URShiftVI src shift));
17140 ins_cost(INSN_COST);
17141 format %{ "ushr $dst, $src, $shift\t# vector (4S)" %}
17142 ins_encode %{
17143 __ ushr(as_FloatRegister($dst$$reg), __ T4S,
17144 as_FloatRegister($src$$reg),
17145 (int)$shift$$constant);
17146 %}
17147 ins_pipe(vshift128_imm);
17148 %}
17149
17150 instruct vsll2L(vecX dst, vecX src, vecX shift) %{
17151 predicate(n->as_Vector()->length() == 2);
17152 match(Set dst (LShiftVL src shift));
17153 ins_cost(INSN_COST);
17154 format %{ "sshl $dst,$src,$shift\t# vector (2D)" %}
17155 ins_encode %{
17156 __ sshl(as_FloatRegister($dst$$reg), __ T2D,
17157 as_FloatRegister($src$$reg),
17158 as_FloatRegister($shift$$reg));
17159 %}
17160 ins_pipe(vshift128);
17161 %}
17162
17163 instruct vsra2L(vecX dst, vecX src, vecX shift, vecX tmp) %{
17164 predicate(n->as_Vector()->length() == 2);
17165 match(Set dst (RShiftVL src shift));
17166 ins_cost(INSN_COST);
17167 effect(TEMP tmp);
17168 format %{ "negr $tmp,$shift\t"
17169 "sshl $dst,$src,$tmp\t# vector (2D)" %}
17170 ins_encode %{
17171 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
17172 as_FloatRegister($shift$$reg));
17173 __ sshl(as_FloatRegister($dst$$reg), __ T2D,
17174 as_FloatRegister($src$$reg),
17175 as_FloatRegister($tmp$$reg));
17176 %}
17177 ins_pipe(vshift128);
17178 %}
17179
17180 instruct vsrl2L(vecX dst, vecX src, vecX shift, vecX tmp) %{
17181 predicate(n->as_Vector()->length() == 2);
17182 match(Set dst (URShiftVL src shift));
17183 ins_cost(INSN_COST);
17184 effect(TEMP tmp);
17185 format %{ "negr $tmp,$shift\t"
17186 "ushl $dst,$src,$tmp\t# vector (2D)" %}
17187 ins_encode %{
17188 __ negr(as_FloatRegister($tmp$$reg), __ T16B,
17189 as_FloatRegister($shift$$reg));
17190 __ ushl(as_FloatRegister($dst$$reg), __ T2D,
17191 as_FloatRegister($src$$reg),
17192 as_FloatRegister($tmp$$reg));
17193 %}
17194 ins_pipe(vshift128);
17195 %}
17196
17197 instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
17198 predicate(n->as_Vector()->length() == 2);
17199 match(Set dst (LShiftVL src shift));
17200 ins_cost(INSN_COST);
17201 format %{ "shl $dst, $src, $shift\t# vector (2D)" %}
17202 ins_encode %{
17203 __ shl(as_FloatRegister($dst$$reg), __ T2D,
17204 as_FloatRegister($src$$reg),
17205 (int)$shift$$constant);
17206 %}
17207 ins_pipe(vshift128_imm);
17208 %}
17209
17210 instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
17211 predicate(n->as_Vector()->length() == 2);
17212 match(Set dst (RShiftVL src shift));
|