1 dnl Copyright (c) 2014, Red Hat Inc. All rights reserved.
2 dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
3 dnl
4 dnl This code is free software; you can redistribute it and/or modify it
5 dnl under the terms of the GNU General Public License version 2 only, as
6 dnl published by the Free Software Foundation.
7 dnl
8 dnl This code is distributed in the hope that it will be useful, but WITHOUT
9 dnl ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 dnl FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 dnl version 2 for more details (a copy is included in the LICENSE file that
12 dnl accompanied this code).
13 dnl
14 dnl You should have received a copy of the GNU General Public License version
15 dnl 2 along with this work; if not, write to the Free Software Foundation,
16 dnl Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
17 dnl
18 dnl Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
19 dnl or visit www.oracle.com if you need additional information or have any
20 dnl questions.
21 dnl
22 dnl
23 dnl Process this file with m4 aarch64_ad.m4 to generate the arithmetic
24 dnl and shift patterns patterns used in aarch64.ad.
25 dnl
26 // BEGIN This section of the file is automatically generated. Do not edit --------------
27 dnl
28 define(`ORL2I', `ifelse($1,I,orL2I)')
29 dnl
30 define(`BASE_SHIFT_INSN',
31 `
32 instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
33 iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
34 immI src3, rFlagsReg cr) %{
35 match(Set dst ($2$1 src1 ($4$1 src2 src3)));
36
37 ins_cost(1.9 * INSN_COST);
38 format %{ "$3 $dst, $src1, $src2, $5 $src3" %}
39
40 ins_encode %{
41 __ $3(as_Register($dst$$reg),
42 as_Register($src1$$reg),
43 as_Register($src2$$reg),
44 Assembler::$5,
216 %}
217
218 define(`UBFIZ_INSN',
219 // We can use ubfiz when masking by a positive number and then left shifting the result.
220 // We know that the mask is positive because imm$1_bitmask guarantees it.
221 `instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
222 %{
223 match(Set dst (LShift$1 (And$1 src mask) lshift));
224 predicate((exact_log2$5(n->in(1)->in(2)->get_$4() + 1) + (n->in(2)->get_int() & $3)) <= ($3 + 1));
225
226 ins_cost(INSN_COST);
227 format %{ "$2 $dst, $src, $lshift, $mask" %}
228 ins_encode %{
229 int lshift = $lshift$$constant & $3;
230 long mask = $mask$$constant;
231 int width = exact_log2$5(mask+1);
232 __ $2(as_Register($dst$$reg),
233 as_Register($src$$reg), lshift, width);
234 %}
235 ins_pipe(ialu_reg_shift);
236 %}')
237 UBFIZ_INSN(I, ubfizw, 31, int)
238 UBFIZ_INSN(L, ubfiz, 63, long, _long)
239
240 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
241 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
242 %{
243 match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
244 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
245
246 ins_cost(INSN_COST);
247 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
248 ins_encode %{
249 int lshift = $lshift$$constant & 63;
250 long mask = $mask$$constant;
251 int width = exact_log2(mask+1);
252 __ ubfiz(as_Register($dst$$reg),
253 as_Register($src$$reg), lshift, width);
254 %}
255 ins_pipe(ialu_reg_shift);
256 %}
464 __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
465 as_Register($src2$$reg), ext::$5, ($lshift$$constant));
466 %}
467 ins_pipe(ialu_reg_reg_shift);
468 %}')
469 dnl
470 dnl $1 $2 $3 $4 $5
471 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
472 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
473 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Add,add,uxtw)
474 dnl
475 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Sub,sub,uxtb)
476 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Sub,sub,uxth)
477 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Sub,sub,uxtw)
478 dnl
479 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Add,addw,uxtb)
480 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Add,addw,uxth)
481 dnl
482 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
483 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
484 dnl
485 // END This section of the file is automatically generated. Do not edit --------------
|
1 dnl Copyright (c) 2019, Red Hat Inc. All rights reserved.
2 dnl DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
3 dnl
4 dnl This code is free software; you can redistribute it and/or modify it
5 dnl under the terms of the GNU General Public License version 2 only, as
6 dnl published by the Free Software Foundation.
7 dnl
8 dnl This code is distributed in the hope that it will be useful, but WITHOUT
9 dnl ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 dnl FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 dnl version 2 for more details (a copy is included in the LICENSE file that
12 dnl accompanied this code).
13 dnl
14 dnl You should have received a copy of the GNU General Public License version
15 dnl 2 along with this work; if not, write to the Free Software Foundation,
16 dnl Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
17 dnl
18 dnl Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
19 dnl or visit www.oracle.com if you need additional information or have any
20 dnl questions.
21 dnl
22 dnl
23 dnl Process this file with m4 aarch64_ad.m4 to generate instructions used in
24 dnl aarch64.ad:
25 dnl 1. the arithmetic
26 dnl 2. shift patterns
27 dnl 3. vector reduce and/or/eor
28 dnl
29 // BEGIN This section of the file is automatically generated. Do not edit --------------
30 dnl
31 define(`ORL2I', `ifelse($1,I,orL2I)')
32 dnl
33 define(`BASE_SHIFT_INSN',
34 `
35 instruct $2$1_reg_$4_reg(iReg$1NoSp dst,
36 iReg$1`'ORL2I($1) src1, iReg$1`'ORL2I($1) src2,
37 immI src3, rFlagsReg cr) %{
38 match(Set dst ($2$1 src1 ($4$1 src2 src3)));
39
40 ins_cost(1.9 * INSN_COST);
41 format %{ "$3 $dst, $src1, $src2, $5 $src3" %}
42
43 ins_encode %{
44 __ $3(as_Register($dst$$reg),
45 as_Register($src1$$reg),
46 as_Register($src2$$reg),
47 Assembler::$5,
219 %}
220
221 define(`UBFIZ_INSN',
222 // We can use ubfiz when masking by a positive number and then left shifting the result.
223 // We know that the mask is positive because imm$1_bitmask guarantees it.
224 `instruct $2$1(iReg$1NoSp dst, iReg$1`'ORL2I($1) src, immI lshift, imm$1_bitmask mask)
225 %{
226 match(Set dst (LShift$1 (And$1 src mask) lshift));
227 predicate((exact_log2$5(n->in(1)->in(2)->get_$4() + 1) + (n->in(2)->get_int() & $3)) <= ($3 + 1));
228
229 ins_cost(INSN_COST);
230 format %{ "$2 $dst, $src, $lshift, $mask" %}
231 ins_encode %{
232 int lshift = $lshift$$constant & $3;
233 long mask = $mask$$constant;
234 int width = exact_log2$5(mask+1);
235 __ $2(as_Register($dst$$reg),
236 as_Register($src$$reg), lshift, width);
237 %}
238 ins_pipe(ialu_reg_shift);
239 %}')dnl
240 UBFIZ_INSN(I, ubfizw, 31, int)
241 UBFIZ_INSN(L, ubfiz, 63, long, _long)
242
243 // If there is a convert I to L block between and AndI and a LShiftL, we can also match ubfiz
244 instruct ubfizIConvI2L(iRegLNoSp dst, iRegIorL2I src, immI lshift, immI_bitmask mask)
245 %{
246 match(Set dst (LShiftL (ConvI2L (AndI src mask)) lshift));
247 predicate((exact_log2(n->in(1)->in(1)->in(2)->get_int() + 1) + (n->in(2)->get_int() & 63)) <= (63 + 1));
248
249 ins_cost(INSN_COST);
250 format %{ "ubfiz $dst, $src, $lshift, $mask" %}
251 ins_encode %{
252 int lshift = $lshift$$constant & 63;
253 long mask = $mask$$constant;
254 int width = exact_log2(mask+1);
255 __ ubfiz(as_Register($dst$$reg),
256 as_Register($src$$reg), lshift, width);
257 %}
258 ins_pipe(ialu_reg_shift);
259 %}
467 __ $4(as_Register($dst$$reg), as_Register($src1$$reg),
468 as_Register($src2$$reg), ext::$5, ($lshift$$constant));
469 %}
470 ins_pipe(ialu_reg_reg_shift);
471 %}')
472 dnl
473 dnl $1 $2 $3 $4 $5
474 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Add,add,uxtb)
475 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Add,add,uxth)
476 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Add,add,uxtw)
477 dnl
478 ADD_SUB_ZERO_EXTEND_SHIFT(L,255,Sub,sub,uxtb)
479 ADD_SUB_ZERO_EXTEND_SHIFT(L,65535,Sub,sub,uxth)
480 ADD_SUB_ZERO_EXTEND_SHIFT(L,4294967295,Sub,sub,uxtw)
481 dnl
482 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Add,addw,uxtb)
483 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Add,addw,uxth)
484 dnl
485 ADD_SUB_ZERO_EXTEND_SHIFT(I,255,Sub,subw,uxtb)
486 ADD_SUB_ZERO_EXTEND_SHIFT(I,65535,Sub,subw,uxth)
487 dnl
488 define(`REDUCE_LOGIC_OP_8B', `
489 instruct reduce_$1`'8B(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegINoSp tmp)
490 %{
491 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
492 match(Set dst ($2ReductionV src1 src2));
493 ins_cost(INSN_COST);
494 effect(TEMP_DEF dst, TEMP tmp);
495 format %{ "umov $tmp, $src2, S, 0\n\t"
496 "umov $dst, $src2, S, 1\n\t"
497 "$1w $dst, $dst, $tmp\n\t"
498 "$1w $dst, $dst, $dst, LSR #16\n\t"
499 "$1w $dst, $dst, $dst, LSR #8\n\t"
500 "$1w $dst, $src1, $dst\n\t"
501 "sxtb $dst, $dst\t $1 reduction8B"
502 %}
503 ins_encode %{
504 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0);
505 __ umov($dst$$Register, as_FloatRegister($src2$$reg), __ S, 1);
506 __ $1w($dst$$Register, $dst$$Register, $tmp$$Register);
507 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
508 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
509 __ $1w($dst$$Register, $src1$$Register, $dst$$Register);
510 __ sxtb($dst$$Register, $dst$$Register);
511 %}
512 ins_pipe(pipe_class_default);
513 %}')dnl
514 dnl $1 $2
515 REDUCE_LOGIC_OP_8B(and, And)
516 REDUCE_LOGIC_OP_8B(orr, Or)
517 REDUCE_LOGIC_OP_8B(eor, Xor)
518 define(`REDUCE_LOGIC_OP_16B', `
519 instruct reduce_$1`'16B(iRegINoSp dst, iRegIorL2I src1, vecX src2, iRegINoSp tmp)
520 %{
521 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
522 match(Set dst ($2ReductionV src1 src2));
523 ins_cost(INSN_COST);
524 effect(TEMP_DEF dst, TEMP tmp);
525 format %{ "umov $tmp, $src2, D, 0\n\t"
526 "umov $dst, $src2, D, 1\n\t"
527 "$3 $dst, $dst, $tmp\n\t"
528 "$3 $dst, $dst, $dst, LSR #32\n\t"
529 "$1w $dst, $dst, $dst, LSR #16\n\t"
530 "$1w $dst, $dst, $dst, LSR #8\n\t"
531 "$1w $dst, $src1, $dst\n\t"
532 "sxtb $dst, $dst\t $1 reduction16B"
533 %}
534 ins_encode %{
535 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ D, 0);
536 __ umov($dst$$Register, as_FloatRegister($src2$$reg), __ D, 1);
537 __ $3($dst$$Register, $dst$$Register, $tmp$$Register);
538 __ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
539 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
540 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
541 __ $1w($dst$$Register, $src1$$Register, $dst$$Register);
542 __ sxtb($dst$$Register, $dst$$Register);
543 %}
544 ins_pipe(pipe_class_default);
545 %}')dnl
546 dnl $1 $2 $3
547 REDUCE_LOGIC_OP_16B(and, And, andr)
548 REDUCE_LOGIC_OP_16B(orr, Or, orr )
549 REDUCE_LOGIC_OP_16B(eor, Xor, eor )
550 dnl
551 define(`REDUCE_LOGIC_OP_4S', `
552 instruct reduce_$1`'4S(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegINoSp tmp)
553 %{
554 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
555 match(Set dst ($2ReductionV src1 src2));
556 ins_cost(INSN_COST);
557 effect(TEMP_DEF dst, TEMP tmp);
558 format %{ "umov $tmp, $src2, S, 0\n\t"
559 "umov $dst, $src2, S, 1\n\t"
560 "$1w $dst, $dst, $tmp\n\t"
561 "$1w $dst, $dst, $dst, LSR #16\n\t"
562 "$1w $dst, $src1, $dst\n\t"
563 "sxth $dst, $dst\t $1 reduction4S"
564 %}
565 ins_encode %{
566 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0);
567 __ umov($dst$$Register, as_FloatRegister($src2$$reg), __ S, 1);
568 __ $1w($dst$$Register, $dst$$Register, $tmp$$Register);
569 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
570 __ $1w($dst$$Register, $src1$$Register, $dst$$Register);
571 __ sxth($dst$$Register, $dst$$Register);
572 %}
573 ins_pipe(pipe_class_default);
574 %}')dnl
575 dnl $1 $2
576 REDUCE_LOGIC_OP_4S(and, And)
577 REDUCE_LOGIC_OP_4S(orr, Or)
578 REDUCE_LOGIC_OP_4S(eor, Xor)
579 dnl
580 define(`REDUCE_LOGIC_OP_8S', `
581 instruct reduce_$1`'8S(iRegINoSp dst, iRegIorL2I src1, vecX src2, iRegINoSp tmp)
582 %{
583 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
584 match(Set dst ($2ReductionV src1 src2));
585 ins_cost(INSN_COST);
586 effect(TEMP_DEF dst, TEMP tmp);
587 format %{ "umov $tmp, $src2, D, 0\n\t"
588 "umov $dst, $src2, D, 1\n\t"
589 "$3 $dst, $dst, $tmp\n\t"
590 "$3 $dst, $dst, $dst, LSR #32\n\t"
591 "$1w $dst, $dst, $dst, LSR #16\n\t"
592 "$1w $dst, $src1, $dst\n\t"
593 "sxth $dst, $dst\t $1 reduction8S"
594 %}
595 ins_encode %{
596 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ D, 0);
597 __ umov($dst$$Register, as_FloatRegister($src2$$reg), __ D, 1);
598 __ $3($dst$$Register, $dst$$Register, $tmp$$Register);
599 __ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
600 __ $1w($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
601 __ $1w($dst$$Register, $src1$$Register, $dst$$Register);
602 __ sxth($dst$$Register, $dst$$Register);
603 %}
604 ins_pipe(pipe_class_default);
605 %}')dnl
606 dnl $1 $2 $3
607 REDUCE_LOGIC_OP_8S(and, And, andr)
608 REDUCE_LOGIC_OP_8S(orr, Or, orr )
609 REDUCE_LOGIC_OP_8S(eor, Xor, eor )
610 dnl
611 define(`REDUCE_LOGIC_OP_2I', `
612 instruct reduce_$1`'2I(iRegINoSp dst, iRegIorL2I src1, vecD src2, iRegINoSp tmp)
613 %{
614 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
615 match(Set dst ($2ReductionV src1 src2));
616 ins_cost(INSN_COST);
617 effect(TEMP_DEF dst, TEMP tmp);
618 format %{ "umov $tmp, $src2, S, 0\n\t"
619 "$1w $dst, $tmp, $src1\n\t"
620 "umov $tmp, $src2, S, 1\n\t"
621 "$1w $dst, $tmp, $dst\t $1 reduction2I"
622 %}
623 ins_encode %{
624 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 0);
625 __ $1w($dst$$Register, $tmp$$Register, $src1$$Register);
626 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ S, 1);
627 __ $1w($dst$$Register, $tmp$$Register, $dst$$Register);
628 %}
629 ins_pipe(pipe_class_default);
630 %}')dnl
631 dnl $1 $2
632 REDUCE_LOGIC_OP_2I(and, And)
633 REDUCE_LOGIC_OP_2I(orr, Or)
634 REDUCE_LOGIC_OP_2I(eor, Xor)
635 dnl
636 define(`REDUCE_LOGIC_OP_4I', `
637 instruct reduce_$1`'4I(iRegINoSp dst, iRegIorL2I src1, vecX src2, iRegINoSp tmp)
638 %{
639 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
640 match(Set dst ($2ReductionV src1 src2));
641 ins_cost(INSN_COST);
642 effect(TEMP_DEF dst, TEMP tmp);
643 format %{ "umov $tmp, $src2, D, 0\n\t"
644 "umov $dst, $src2, D, 1\n\t"
645 "$3 $dst, $dst, $tmp\n\t"
646 "$3 $dst, $dst, $dst, LSR #32\n\t"
647 "$1w $dst, $src1, $dst\t $1 reduction4I"
648 %}
649 ins_encode %{
650 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ D, 0);
651 __ umov($dst$$Register, as_FloatRegister($src2$$reg), __ D, 1);
652 __ $3($dst$$Register, $dst$$Register, $tmp$$Register);
653 __ $3($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
654 __ $1w($dst$$Register, $src1$$Register, $dst$$Register);
655 %}
656 ins_pipe(pipe_class_default);
657 %}')dnl
658 dnl $1 $2 $3
659 REDUCE_LOGIC_OP_4I(and, And, andr)
660 REDUCE_LOGIC_OP_4I(orr, Or, orr )
661 REDUCE_LOGIC_OP_4I(eor, Xor, eor )
662 dnl
663 define(`REDUCE_LOGIC_OP_2L', `
664 instruct reduce_$1`'2L(iRegLNoSp dst, iRegL src1, vecX src2, iRegLNoSp tmp)
665 %{
666 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
667 match(Set dst ($2ReductionV src1 src2));
668 ins_cost(INSN_COST);
669 effect(TEMP_DEF dst, TEMP tmp);
670 format %{ "umov $tmp, $src2, D, 0\n\t"
671 "$3 $dst, $src1, $tmp\n\t"
672 "umov $tmp, $src2, D, 1\n\t"
673 "$3 $dst, $dst, $tmp\t $1 reduction2L"
674 %}
675 ins_encode %{
676 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ D, 0);
677 __ $3($dst$$Register, $src1$$Register, $tmp$$Register);
678 __ umov($tmp$$Register, as_FloatRegister($src2$$reg), __ D, 1);
679 __ $3($dst$$Register, $dst$$Register, $tmp$$Register);
680 %}
681 ins_pipe(pipe_class_default);
682 %}')dnl
683 dnl $1 $2 $3
684 REDUCE_LOGIC_OP_2L(and, And, andr)
685 REDUCE_LOGIC_OP_2L(orr, Or, orr )
686 REDUCE_LOGIC_OP_2L(eor, Xor, eor )
687 dnl
688
689 // ------------------------------ Vector insert ---------------------------------
690 define(`VECTOR_INSERT_I', `
691 instruct insert$1`'(vec$2 dst, vec$2 src, iReg$3`'ORL2I($3) val, immI idx)
692 %{
693 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_$4);
694 match(Set dst (VectorInsert (Binary src val) idx));
695 ins_cost(INSN_COST);
696 format %{ "orr $dst, T$5, $src, $src\n\t"
697 "mov $dst, T$6, $idx, $val\t# insert into vector($1)" %}
698 ins_encode %{
699 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
700 __ orr(as_FloatRegister($dst$$reg), __ T$5,
701 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
702 }
703 __ mov(as_FloatRegister($dst$$reg), __ T$6, $idx$$constant, $val$$Register);
704 %}
705 ins_pipe(pipe_class_default);
706 %}')dnl
707 dnl $1 $2 $3 $4 $5 $6
708 VECTOR_INSERT_I(8B, D, I, BYTE, 8B, 8B)
709 VECTOR_INSERT_I(16B, X, I, BYTE, 16B, 16B)
710 VECTOR_INSERT_I(4S, D, I, SHORT, 8B, 4H)
711 VECTOR_INSERT_I(8S, X, I, SHORT, 16B, 8H)
712 VECTOR_INSERT_I(2I, D, I, INT, 8B, 2S)
713 VECTOR_INSERT_I(4I, X, I, INT, 16B, 4S)
714 VECTOR_INSERT_I(2L, X, L, LONG, 16B, 2D)
715 dnl
716 define(`VECTOR_INSERT_F', `
717 instruct insert$1`'(vec$2 dst, vec$2 src, vReg$3 val, immI idx)
718 %{
719 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_$4);
720 match(Set dst (VectorInsert (Binary src val) idx));
721 ins_cost(INSN_COST);
722 format %{ "orr $dst, T$5, $src, $src\n\t"
723 "ins $dst, $6, $val, $idx, 0\t# insert into vector($1)" %}
724 ins_encode %{
725 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
726 __ orr(as_FloatRegister($dst$$reg), __ T$5,
727 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
728 }
729 __ ins(as_FloatRegister($dst$$reg), __ $6,
730 as_FloatRegister($val$$reg), $idx$$constant, 0);
731 %}
732 ins_pipe(pipe_class_default);
733 %}')dnl
734 dnl $1 $2 $3 $4 $5 $6
735 VECTOR_INSERT_F(2F, D, F, FLOAT, 8B, S)
736 VECTOR_INSERT_F(4F, X, F, FLOAT, 16B, S)
737 VECTOR_INSERT_F(2D, X, D, DOUBLE, 16B, D)
738 dnl
739
740 // ------------------------------ Vector extract ---------------------------------
741 define(`VECTOR_EXTRACT_I', `
742 instruct extract$1$2`'(iReg$3NoSp dst, vec$4 src, immI idx)
743 %{
744 predicate(n->in(1)->bottom_type()->is_vect()->length() == $1);
745 match(Set dst (Extract$2 src idx));
746 ins_cost(INSN_COST);
747 format %{ "$5mov $dst, $src, $6, $idx\t# extract from vector($1$2)" %}
748 ins_encode %{
749 __ $5mov($dst$$Register, as_FloatRegister($src$$reg), __ $6, $idx$$constant);
750 %}
751 ins_pipe(pipe_class_default);
752 %}')dnl
753 dnl $1 $2 $3 $4 $5 $6
754 VECTOR_EXTRACT_I(8, B, I, D, s, B)
755 VECTOR_EXTRACT_I(16, B, I, X, s, B)
756 VECTOR_EXTRACT_I(4, S, I, D, s, H)
757 VECTOR_EXTRACT_I(8, S, I, X, s, H)
758 VECTOR_EXTRACT_I(2, I, I, D, u, S)
759 VECTOR_EXTRACT_I(4, I, I, X, u, S)
760 VECTOR_EXTRACT_I(2, L, L, X, u, D)
761 dnl
762 define(`VECTOR_EXTRACT_F', `
763 instruct extract$1$2`'(vReg$2 dst, vec$3 src, immI idx)
764 %{
765 predicate(n->in(1)->bottom_type()->is_vect()->length() == $1);
766 match(Set dst (Extract$2 src idx));
767 ins_cost(INSN_COST);
768 format %{ "ins $dst, $4, $src, 0, $idx\t# extract from vector($1$2)" %}
769 ins_encode %{
770 __ ins(as_FloatRegister($dst$$reg), __ $4,
771 as_FloatRegister($src$$reg), 0, $idx$$constant);
772 %}
773 ins_pipe(pipe_class_default);
774 %}')dnl
775 dnl $1 $2 $3 $4
776 VECTOR_EXTRACT_F(2, F, D, S)
777 VECTOR_EXTRACT_F(4, F, X, S)
778 VECTOR_EXTRACT_F(2, D, X, D)
779 dnl
780 // END This section of the file is automatically generated. Do not edit --------------
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