2089 if (!has_match_rule(opcode))
2090 return false;
2091
2092 bool ret_value = true;
2093 switch (opcode) {
2094 case Op_CacheWB:
2095 case Op_CacheWBPreSync:
2096 case Op_CacheWBPostSync:
2097 if (!VM_Version::supports_data_cache_line_flush()) {
2098 ret_value = false;
2099 }
2100 break;
2101 }
2102
2103 return ret_value; // Per default match rules are supported.
2104 }
2105
2106 // Identify extra cases that we might want to provide match rules for vector nodes and
2107 // other intrinsics guarded with vector length (vlen) and element type (bt).
2108 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
2109 if (!match_rule_supported(opcode)) {
2110 return false;
2111 }
2112
2113 // Special cases which require vector length
2114 switch (opcode) {
2115 case Op_MulAddVS2VI: {
2116 if (vlen != 4) {
2117 return false;
2118 }
2119 break;
2120 }
2121 }
2122
2123 return true; // Per default match rules are supported.
2124 }
2125
2126 const bool Matcher::has_predicated_vectors(void) {
2127 return false;
2128 }
2129
2130 const int Matcher::float_pressure(int default_pressure_threshold) {
2131 return default_pressure_threshold;
2132 }
2133
2134 int Matcher::regnum_to_fpu_offset(int regnum)
2135 {
2136 Unimplemented();
2137 return 0;
2138 }
2139
2140 // Is this branch offset short enough that a short branch can be used?
2141 //
2142 // NOTE: If the platform does not provide any short branch variants, then
2143 // this method should return false for offset 0.
2144 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2145 // The passed offset is relative to address of the branch.
2146
2147 return (-32768 <= offset && offset < 32768);
2148 }
2149
2156 // true just means we have fast l2f conversion
2157 const bool Matcher::convL2FSupported(void) {
2158 return true;
2159 }
2160
2161 // Vector width in bytes.
2162 const int Matcher::vector_width_in_bytes(BasicType bt) {
2163 int size = MIN2(16,(int)MaxVectorSize);
2164 // Minimum 2 values in vector
2165 if (size < 2*type2aelembytes(bt)) size = 0;
2166 // But never < 4
2167 if (size < 4) size = 0;
2168 return size;
2169 }
2170
2171 // Limits on vector size (number of elements) loaded into vector.
2172 const int Matcher::max_vector_size(const BasicType bt) {
2173 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2174 }
2175 const int Matcher::min_vector_size(const BasicType bt) {
2176 // For the moment limit the vector size to 8 bytes
2177 int size = 8 / type2aelembytes(bt);
2178 if (size < 2) size = 2;
2179 return size;
2180 }
2181
2182 // Vector ideal reg.
2183 const uint Matcher::vector_ideal_reg(int len) {
2184 switch(len) {
2185 case 8: return Op_VecD;
2186 case 16: return Op_VecX;
2187 }
2188 ShouldNotReachHere();
2189 return 0;
2190 }
2191
2192 // AES support not yet implemented
2193 const bool Matcher::pass_original_key_for_aes() {
2194 return false;
2195 }
2196
2197 // aarch64 supports misaligned vectors store/load.
2198 const bool Matcher::misaligned_vectors_ok() {
2199 return true;
2200 }
2201
2202 // false => size gets scaled to BytesPerLong, ok.
2203 const bool Matcher::init_array_count_is_in_bytes = false;
2204
2807 // need to do this the hard way until we can manage relocs
2808 // for 32 bit constants
2809 __ movoop(rscratch2, (jobject)con);
2810 __ encode_klass_not_null(rscratch2);
2811 loadStore(_masm, &MacroAssembler::strw, rscratch2, $mem->opcode(),
2812 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2813 %}
2814
2815 // This encoding class is generated automatically from ad_encode.m4.
2816 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2817 enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
2818 C2_MacroAssembler _masm(&cbuf);
2819 __ membar(Assembler::StoreStore);
2820 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
2821 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2822 %}
2823
2824 // END Non-volatile memory access
2825
2826 // Vector loads and stores
2827 enc_class aarch64_enc_ldrvS(vecD dst, memory mem) %{
2828 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2829 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
2830 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2831 %}
2832
2833 enc_class aarch64_enc_ldrvD(vecD dst, memory mem) %{
2834 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2835 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
2836 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2837 %}
2838
2839 enc_class aarch64_enc_ldrvQ(vecX dst, memory mem) %{
2840 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2841 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
2842 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2843 %}
2844
2845 enc_class aarch64_enc_strvS(vecD src, memory mem) %{
2846 FloatRegister src_reg = as_FloatRegister($src$$reg);
2847 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::S,
2848 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2849 %}
2850
2851 enc_class aarch64_enc_strvD(vecD src, memory mem) %{
2852 FloatRegister src_reg = as_FloatRegister($src$$reg);
2853 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::D,
2854 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2855 %}
2856
2857 enc_class aarch64_enc_strvQ(vecX src, memory mem) %{
2858 FloatRegister src_reg = as_FloatRegister($src$$reg);
2859 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::Q,
2860 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2861 %}
2862
2863 // volatile loads and stores
2864
3909 operand immI_le_4()
3910 %{
3911 predicate(n->get_int() <= 4);
3912 match(ConI);
3913
3914 op_cost(0);
3915 format %{ %}
3916 interface(CONST_INTER);
3917 %}
3918
3919 operand immI_31()
3920 %{
3921 predicate(n->get_int() == 31);
3922 match(ConI);
3923
3924 op_cost(0);
3925 format %{ %}
3926 interface(CONST_INTER);
3927 %}
3928
3929 operand immI_8()
3930 %{
3931 predicate(n->get_int() == 8);
3932 match(ConI);
3933
3934 op_cost(0);
3935 format %{ %}
3936 interface(CONST_INTER);
3937 %}
3938
3939 operand immI_16()
3940 %{
3941 predicate(n->get_int() == 16);
3942 match(ConI);
3943
3944 op_cost(0);
3945 format %{ %}
3946 interface(CONST_INTER);
3947 %}
3948
10811 ins_pipe(ialu_reg_reg_vshift);
10812 %}
10813
10814 // Shift Right Arithmetic Immediate
10815 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10816 match(Set dst (RShiftL src1 src2));
10817
10818 ins_cost(INSN_COST);
10819 format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
10820
10821 ins_encode %{
10822 __ asr(as_Register($dst$$reg),
10823 as_Register($src1$$reg),
10824 $src2$$constant & 0x3f);
10825 %}
10826
10827 ins_pipe(ialu_reg_shift);
10828 %}
10829
10830 // BEGIN This section of the file is automatically generated. Do not edit --------------
10831
10832 instruct regL_not_reg(iRegLNoSp dst,
10833 iRegL src1, immL_M1 m1,
10834 rFlagsReg cr) %{
10835 match(Set dst (XorL src1 m1));
10836 ins_cost(INSN_COST);
10837 format %{ "eon $dst, $src1, zr" %}
10838
10839 ins_encode %{
10840 __ eon(as_Register($dst$$reg),
10841 as_Register($src1$$reg),
10842 zr,
10843 Assembler::LSL, 0);
10844 %}
10845
10846 ins_pipe(ialu_reg);
10847 %}
10848 instruct regI_not_reg(iRegINoSp dst,
10849 iRegIorL2I src1, immI_M1 m1,
10850 rFlagsReg cr) %{
15967 ins_pipe(vdup_reg_freg128);
15968 %}
15969
15970 instruct replicate2D(vecX dst, vRegD src)
15971 %{
15972 predicate(n->as_Vector()->length() == 2);
15973 match(Set dst (ReplicateD src));
15974 ins_cost(INSN_COST);
15975 format %{ "dup $dst, $src\t# vector (2D)" %}
15976 ins_encode %{
15977 __ dup(as_FloatRegister($dst$$reg), __ T2D,
15978 as_FloatRegister($src$$reg));
15979 %}
15980 ins_pipe(vdup_reg_dreg128);
15981 %}
15982
15983 // ====================REDUCTION ARITHMETIC====================================
15984
15985 instruct reduce_add2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp, iRegINoSp tmp2)
15986 %{
15987 match(Set dst (AddReductionVI isrc vsrc));
15988 ins_cost(INSN_COST);
15989 effect(TEMP tmp, TEMP tmp2);
15990 format %{ "umov $tmp, $vsrc, S, 0\n\t"
15991 "umov $tmp2, $vsrc, S, 1\n\t"
15992 "addw $tmp, $isrc, $tmp\n\t"
15993 "addw $dst, $tmp, $tmp2\t# add reduction2I"
15994 %}
15995 ins_encode %{
15996 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
15997 __ umov($tmp2$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
15998 __ addw($tmp$$Register, $isrc$$Register, $tmp$$Register);
15999 __ addw($dst$$Register, $tmp$$Register, $tmp2$$Register);
16000 %}
16001 ins_pipe(pipe_class_default);
16002 %}
16003
16004 instruct reduce_add4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp, iRegINoSp itmp)
16005 %{
16006 match(Set dst (AddReductionVI isrc vsrc));
16007 ins_cost(INSN_COST);
16008 effect(TEMP vtmp, TEMP itmp);
16009 format %{ "addv $vtmp, T4S, $vsrc\n\t"
16010 "umov $itmp, $vtmp, S, 0\n\t"
16011 "addw $dst, $itmp, $isrc\t# add reduction4I"
16012 %}
16013 ins_encode %{
16014 __ addv(as_FloatRegister($vtmp$$reg), __ T4S,
16015 as_FloatRegister($vsrc$$reg));
16016 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
16017 __ addw($dst$$Register, $itmp$$Register, $isrc$$Register);
16018 %}
16019 ins_pipe(pipe_class_default);
16020 %}
16021
16022 instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
16023 %{
16024 match(Set dst (MulReductionVI isrc vsrc));
16025 ins_cost(INSN_COST);
16026 effect(TEMP tmp, TEMP dst);
16027 format %{ "umov $tmp, $vsrc, S, 0\n\t"
16028 "mul $dst, $tmp, $isrc\n\t"
16029 "umov $tmp, $vsrc, S, 1\n\t"
16030 "mul $dst, $tmp, $dst\t# mul reduction2I"
16031 %}
16032 ins_encode %{
16033 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
16034 __ mul($dst$$Register, $tmp$$Register, $isrc$$Register);
16035 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
16036 __ mul($dst$$Register, $tmp$$Register, $dst$$Register);
16037 %}
16038 ins_pipe(pipe_class_default);
16039 %}
16040
16041 instruct reduce_mul4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp, iRegINoSp itmp)
16042 %{
16043 match(Set dst (MulReductionVI isrc vsrc));
16044 ins_cost(INSN_COST);
16045 effect(TEMP vtmp, TEMP itmp, TEMP dst);
16046 format %{ "ins $vtmp, D, $vsrc, 0, 1\n\t"
16047 "mulv $vtmp, T2S, $vtmp, $vsrc\n\t"
16048 "umov $itmp, $vtmp, S, 0\n\t"
16049 "mul $dst, $itmp, $isrc\n\t"
16050 "umov $itmp, $vtmp, S, 1\n\t"
16051 "mul $dst, $itmp, $dst\t# mul reduction4I"
16052 %}
16053 ins_encode %{
16054 __ ins(as_FloatRegister($vtmp$$reg), __ D,
16055 as_FloatRegister($vsrc$$reg), 0, 1);
16056 __ mulv(as_FloatRegister($vtmp$$reg), __ T2S,
16057 as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
16058 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
16059 __ mul($dst$$Register, $itmp$$Register, $isrc$$Register);
16060 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 1);
16061 __ mul($dst$$Register, $itmp$$Register, $dst$$Register);
16062 %}
17012 ins_encode %{
17013 __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17014 %}
17015 ins_pipe(vsqrt_fp128);
17016 %}
17017
17018 instruct vsqrt2D(vecX dst, vecX src)
17019 %{
17020 predicate(n->as_Vector()->length() == 2);
17021 match(Set dst (SqrtVD src));
17022 format %{ "fsqrt $dst, $src\t# vector (2D)" %}
17023 ins_encode %{
17024 __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
17025 as_FloatRegister($src$$reg));
17026 %}
17027 ins_pipe(vsqrt_fp128);
17028 %}
17029
17030 // --------------------------------- ABS --------------------------------------
17031
17032 instruct vabs2F(vecD dst, vecD src)
17033 %{
17034 predicate(n->as_Vector()->length() == 2);
17035 match(Set dst (AbsVF src));
17036 ins_cost(INSN_COST * 3);
17037 format %{ "fabs $dst,$src\t# vector (2S)" %}
17038 ins_encode %{
17039 __ fabs(as_FloatRegister($dst$$reg), __ T2S,
17040 as_FloatRegister($src$$reg));
17041 %}
17042 ins_pipe(vunop_fp64);
17043 %}
17044
17045 instruct vabs4F(vecX dst, vecX src)
17046 %{
17047 predicate(n->as_Vector()->length() == 4);
17048 match(Set dst (AbsVF src));
17049 ins_cost(INSN_COST * 3);
17050 format %{ "fabs $dst,$src\t# vector (4S)" %}
17051 ins_encode %{
17052 __ fabs(as_FloatRegister($dst$$reg), __ T4S,
17053 as_FloatRegister($src$$reg));
17054 %}
17055 ins_pipe(vunop_fp128);
17056 %}
17057
17058 instruct vabs2D(vecX dst, vecX src)
17059 %{
17060 predicate(n->as_Vector()->length() == 2);
17061 match(Set dst (AbsVD src));
17062 ins_cost(INSN_COST * 3);
17063 format %{ "fabs $dst,$src\t# vector (2D)" %}
17064 ins_encode %{
17065 __ fabs(as_FloatRegister($dst$$reg), __ T2D,
17066 as_FloatRegister($src$$reg));
17067 %}
17068 ins_pipe(vunop_fp128);
17069 %}
17070
17071 // --------------------------------- NEG --------------------------------------
17072
17073 instruct vneg2F(vecD dst, vecD src)
17074 %{
17075 predicate(n->as_Vector()->length() == 2);
17076 match(Set dst (NegVF src));
17077 ins_cost(INSN_COST * 3);
17078 format %{ "fneg $dst,$src\t# vector (2S)" %}
17079 ins_encode %{
17080 __ fneg(as_FloatRegister($dst$$reg), __ T2S,
17081 as_FloatRegister($src$$reg));
17082 %}
17083 ins_pipe(vunop_fp64);
17084 %}
17085
17086 instruct vneg4F(vecX dst, vecX src)
17187 %}
17188 ins_pipe(vlogical64);
17189 %}
17190
17191 instruct vxor16B(vecX dst, vecX src1, vecX src2)
17192 %{
17193 predicate(n->as_Vector()->length_in_bytes() == 16);
17194 match(Set dst (XorV src1 src2));
17195 ins_cost(INSN_COST);
17196 format %{ "xor $dst,$src1,$src2\t# vector (16B)" %}
17197 ins_encode %{
17198 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17199 as_FloatRegister($src1$$reg),
17200 as_FloatRegister($src2$$reg));
17201 %}
17202 ins_pipe(vlogical128);
17203 %}
17204
17205 // ------------------------------ Shift ---------------------------------------
17206 instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{
17207 predicate(n->as_Vector()->length_in_bytes() == 8);
17208 match(Set dst (LShiftCntV cnt));
17209 match(Set dst (RShiftCntV cnt));
17210 format %{ "dup $dst, $cnt\t# shift count vector (8B)" %}
17211 ins_encode %{
17212 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg));
17213 %}
17214 ins_pipe(vdup_reg_reg64);
17215 %}
17216
17217 instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{
17218 predicate(n->as_Vector()->length_in_bytes() == 16);
17219 match(Set dst (LShiftCntV cnt));
17220 match(Set dst (RShiftCntV cnt));
17221 format %{ "dup $dst, $cnt\t# shift count vector (16B)" %}
17222 ins_encode %{
17223 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
17224 %}
17225 ins_pipe(vdup_reg_reg128);
17226 %}
17227
18039 %}
18040
18041 instruct vpopcount2I(vecD dst, vecD src) %{
18042 predicate(UsePopCountInstruction && n->as_Vector()->length() == 2);
18043 match(Set dst (PopCountVI src));
18044 format %{
18045 "cnt $dst, $src\t# vector (8B)\n\t"
18046 "uaddlp $dst, $dst\t# vector (8B)\n\t"
18047 "uaddlp $dst, $dst\t# vector (4H)"
18048 %}
18049 ins_encode %{
18050 __ cnt(as_FloatRegister($dst$$reg), __ T8B,
18051 as_FloatRegister($src$$reg));
18052 __ uaddlp(as_FloatRegister($dst$$reg), __ T8B,
18053 as_FloatRegister($dst$$reg));
18054 __ uaddlp(as_FloatRegister($dst$$reg), __ T4H,
18055 as_FloatRegister($dst$$reg));
18056 %}
18057 ins_pipe(pipe_class_default);
18058 %}
18059
18060 //----------PEEPHOLE RULES-----------------------------------------------------
18061 // These must follow all instruction definitions as they use the names
18062 // defined in the instructions definitions.
18063 //
18064 // peepmatch ( root_instr_name [preceding_instruction]* );
18065 //
18066 // peepconstraint %{
18067 // (instruction_number.operand_name relational_op instruction_number.operand_name
18068 // [, ...] );
18069 // // instruction numbers are zero-based using left to right order in peepmatch
18070 //
18071 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
18072 // // provide an instruction_number.operand_name for each operand that appears
18073 // // in the replacement instruction's match rule
18074 //
18075 // ---------VM FLAGS---------------------------------------------------------
18076 //
18077 // All peephole optimizations can be turned off using -XX:-OptoPeephole
18078 //
|
2089 if (!has_match_rule(opcode))
2090 return false;
2091
2092 bool ret_value = true;
2093 switch (opcode) {
2094 case Op_CacheWB:
2095 case Op_CacheWBPreSync:
2096 case Op_CacheWBPostSync:
2097 if (!VM_Version::supports_data_cache_line_flush()) {
2098 ret_value = false;
2099 }
2100 break;
2101 }
2102
2103 return ret_value; // Per default match rules are supported.
2104 }
2105
2106 // Identify extra cases that we might want to provide match rules for vector nodes and
2107 // other intrinsics guarded with vector length (vlen) and element type (bt).
2108 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
2109 if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
2110 return false;
2111 }
2112
2113 // Special cases which require vector length
2114 switch (opcode) {
2115 case Op_MulAddVS2VI: {
2116 if (vlen != 4) {
2117 return false;
2118 }
2119 break;
2120 }
2121 case Op_VectorLoadShuffle:
2122 case Op_VectorRearrange:
2123 if (vlen < 4) {
2124 return false;
2125 }
2126 break;
2127 }
2128
2129 return true; // Per default match rules are supported.
2130 }
2131
2132 const bool Matcher::has_predicated_vectors(void) {
2133 return false;
2134 }
2135
2136 bool Matcher::supports_vector_variable_shifts(void) {
2137 return true;
2138 }
2139
2140 const int Matcher::float_pressure(int default_pressure_threshold) {
2141 return default_pressure_threshold;
2142 }
2143
2144 int Matcher::regnum_to_fpu_offset(int regnum)
2145 {
2146 Unimplemented();
2147 return 0;
2148 }
2149
2150 // Is this branch offset short enough that a short branch can be used?
2151 //
2152 // NOTE: If the platform does not provide any short branch variants, then
2153 // this method should return false for offset 0.
2154 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2155 // The passed offset is relative to address of the branch.
2156
2157 return (-32768 <= offset && offset < 32768);
2158 }
2159
2166 // true just means we have fast l2f conversion
2167 const bool Matcher::convL2FSupported(void) {
2168 return true;
2169 }
2170
2171 // Vector width in bytes.
2172 const int Matcher::vector_width_in_bytes(BasicType bt) {
2173 int size = MIN2(16,(int)MaxVectorSize);
2174 // Minimum 2 values in vector
2175 if (size < 2*type2aelembytes(bt)) size = 0;
2176 // But never < 4
2177 if (size < 4) size = 0;
2178 return size;
2179 }
2180
2181 // Limits on vector size (number of elements) loaded into vector.
2182 const int Matcher::max_vector_size(const BasicType bt) {
2183 return vector_width_in_bytes(bt)/type2aelembytes(bt);
2184 }
2185 const int Matcher::min_vector_size(const BasicType bt) {
2186 int max_size = max_vector_size(bt);
2187 // Limit the vector size to 8 bytes
2188 int size = 8 / type2aelembytes(bt);
2189 if (bt == T_BYTE) {
2190 // To support vector api shuffle/rearrange.
2191 size = 4;
2192 } else if (bt == T_BOOLEAN) {
2193 // To support vector api load/store mask.
2194 size = 2;
2195 }
2196 if (size < 2) size = 2;
2197 return MIN2(size,max_size);
2198 }
2199
2200 // Vector ideal reg.
2201 const uint Matcher::vector_ideal_reg(int len) {
2202 switch(len) {
2203 // For 16-bit/32-bit mask vector, reuse VecD.
2204 case 2:
2205 case 4:
2206 case 8: return Op_VecD;
2207 case 16: return Op_VecX;
2208 }
2209 ShouldNotReachHere();
2210 return 0;
2211 }
2212
2213 // AES support not yet implemented
2214 const bool Matcher::pass_original_key_for_aes() {
2215 return false;
2216 }
2217
2218 // aarch64 supports misaligned vectors store/load.
2219 const bool Matcher::misaligned_vectors_ok() {
2220 return true;
2221 }
2222
2223 // false => size gets scaled to BytesPerLong, ok.
2224 const bool Matcher::init_array_count_is_in_bytes = false;
2225
2828 // need to do this the hard way until we can manage relocs
2829 // for 32 bit constants
2830 __ movoop(rscratch2, (jobject)con);
2831 __ encode_klass_not_null(rscratch2);
2832 loadStore(_masm, &MacroAssembler::strw, rscratch2, $mem->opcode(),
2833 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
2834 %}
2835
2836 // This encoding class is generated automatically from ad_encode.m4.
2837 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
2838 enc_class aarch64_enc_strb0_ordered(memory4 mem) %{
2839 C2_MacroAssembler _masm(&cbuf);
2840 __ membar(Assembler::StoreStore);
2841 loadStore(_masm, &MacroAssembler::strb, zr, $mem->opcode(),
2842 as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 1);
2843 %}
2844
2845 // END Non-volatile memory access
2846
2847 // Vector loads and stores
2848 enc_class aarch64_enc_ldrvH(vecD dst, memory mem) %{
2849 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2850 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::H,
2851 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2852 %}
2853
2854 enc_class aarch64_enc_ldrvS(vecD dst, memory mem) %{
2855 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2856 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::S,
2857 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2858 %}
2859
2860 enc_class aarch64_enc_ldrvD(vecD dst, memory mem) %{
2861 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2862 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::D,
2863 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2864 %}
2865
2866 enc_class aarch64_enc_ldrvQ(vecX dst, memory mem) %{
2867 FloatRegister dst_reg = as_FloatRegister($dst$$reg);
2868 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::ldr, dst_reg, MacroAssembler::Q,
2869 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2870 %}
2871
2872 enc_class aarch64_enc_strvH(vecD src, memory mem) %{
2873 FloatRegister src_reg = as_FloatRegister($src$$reg);
2874 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::H,
2875 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2876 %}
2877
2878 enc_class aarch64_enc_strvS(vecD src, memory mem) %{
2879 FloatRegister src_reg = as_FloatRegister($src$$reg);
2880 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::S,
2881 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2882 %}
2883
2884 enc_class aarch64_enc_strvD(vecD src, memory mem) %{
2885 FloatRegister src_reg = as_FloatRegister($src$$reg);
2886 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::D,
2887 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2888 %}
2889
2890 enc_class aarch64_enc_strvQ(vecX src, memory mem) %{
2891 FloatRegister src_reg = as_FloatRegister($src$$reg);
2892 loadStore(C2_MacroAssembler(&cbuf), &MacroAssembler::str, src_reg, MacroAssembler::Q,
2893 $mem->opcode(), as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp);
2894 %}
2895
2896 // volatile loads and stores
2897
3942 operand immI_le_4()
3943 %{
3944 predicate(n->get_int() <= 4);
3945 match(ConI);
3946
3947 op_cost(0);
3948 format %{ %}
3949 interface(CONST_INTER);
3950 %}
3951
3952 operand immI_31()
3953 %{
3954 predicate(n->get_int() == 31);
3955 match(ConI);
3956
3957 op_cost(0);
3958 format %{ %}
3959 interface(CONST_INTER);
3960 %}
3961
3962 operand immI_2()
3963 %{
3964 predicate(n->get_int() == 2);
3965 match(ConI);
3966
3967 op_cost(0);
3968 format %{ %}
3969 interface(CONST_INTER);
3970 %}
3971
3972 operand immI_4()
3973 %{
3974 predicate(n->get_int() == 4);
3975 match(ConI);
3976
3977 op_cost(0);
3978 format %{ %}
3979 interface(CONST_INTER);
3980 %}
3981
3982 operand immI_8()
3983 %{
3984 predicate(n->get_int() == 8);
3985 match(ConI);
3986
3987 op_cost(0);
3988 format %{ %}
3989 interface(CONST_INTER);
3990 %}
3991
3992 operand immI_16()
3993 %{
3994 predicate(n->get_int() == 16);
3995 match(ConI);
3996
3997 op_cost(0);
3998 format %{ %}
3999 interface(CONST_INTER);
4000 %}
4001
10864 ins_pipe(ialu_reg_reg_vshift);
10865 %}
10866
10867 // Shift Right Arithmetic Immediate
10868 instruct rShiftL_reg_imm(iRegLNoSp dst, iRegL src1, immI src2) %{
10869 match(Set dst (RShiftL src1 src2));
10870
10871 ins_cost(INSN_COST);
10872 format %{ "asr $dst, $src1, ($src2 & 0x3f)" %}
10873
10874 ins_encode %{
10875 __ asr(as_Register($dst$$reg),
10876 as_Register($src1$$reg),
10877 $src2$$constant & 0x3f);
10878 %}
10879
10880 ins_pipe(ialu_reg_shift);
10881 %}
10882
10883 // BEGIN This section of the file is automatically generated. Do not edit --------------
10884 // This section is generated from aarch64_ad.m4
10885
10886 instruct regL_not_reg(iRegLNoSp dst,
10887 iRegL src1, immL_M1 m1,
10888 rFlagsReg cr) %{
10889 match(Set dst (XorL src1 m1));
10890 ins_cost(INSN_COST);
10891 format %{ "eon $dst, $src1, zr" %}
10892
10893 ins_encode %{
10894 __ eon(as_Register($dst$$reg),
10895 as_Register($src1$$reg),
10896 zr,
10897 Assembler::LSL, 0);
10898 %}
10899
10900 ins_pipe(ialu_reg);
10901 %}
10902 instruct regI_not_reg(iRegINoSp dst,
10903 iRegIorL2I src1, immI_M1 m1,
10904 rFlagsReg cr) %{
16021 ins_pipe(vdup_reg_freg128);
16022 %}
16023
16024 instruct replicate2D(vecX dst, vRegD src)
16025 %{
16026 predicate(n->as_Vector()->length() == 2);
16027 match(Set dst (ReplicateD src));
16028 ins_cost(INSN_COST);
16029 format %{ "dup $dst, $src\t# vector (2D)" %}
16030 ins_encode %{
16031 __ dup(as_FloatRegister($dst$$reg), __ T2D,
16032 as_FloatRegister($src$$reg));
16033 %}
16034 ins_pipe(vdup_reg_dreg128);
16035 %}
16036
16037 // ====================REDUCTION ARITHMETIC====================================
16038
16039 instruct reduce_add2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp, iRegINoSp tmp2)
16040 %{
16041 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
16042 match(Set dst (AddReductionVI isrc vsrc));
16043 ins_cost(INSN_COST);
16044 effect(TEMP tmp, TEMP tmp2);
16045 format %{ "umov $tmp, $vsrc, S, 0\n\t"
16046 "umov $tmp2, $vsrc, S, 1\n\t"
16047 "addw $tmp, $isrc, $tmp\n\t"
16048 "addw $dst, $tmp, $tmp2\t# add reduction2I"
16049 %}
16050 ins_encode %{
16051 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
16052 __ umov($tmp2$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
16053 __ addw($tmp$$Register, $isrc$$Register, $tmp$$Register);
16054 __ addw($dst$$Register, $tmp$$Register, $tmp2$$Register);
16055 %}
16056 ins_pipe(pipe_class_default);
16057 %}
16058
16059 instruct reduce_add4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp, iRegINoSp itmp)
16060 %{
16061 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
16062 match(Set dst (AddReductionVI isrc vsrc));
16063 ins_cost(INSN_COST);
16064 effect(TEMP vtmp, TEMP itmp);
16065 format %{ "addv $vtmp, T4S, $vsrc\n\t"
16066 "umov $itmp, $vtmp, S, 0\n\t"
16067 "addw $dst, $itmp, $isrc\t# add reduction4I"
16068 %}
16069 ins_encode %{
16070 __ addv(as_FloatRegister($vtmp$$reg), __ T4S,
16071 as_FloatRegister($vsrc$$reg));
16072 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
16073 __ addw($dst$$Register, $itmp$$Register, $isrc$$Register);
16074 %}
16075 ins_pipe(pipe_class_default);
16076 %}
16077
16078 instruct reduce_mul2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
16079 %{
16080 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
16081 match(Set dst (MulReductionVI isrc vsrc));
16082 ins_cost(INSN_COST);
16083 effect(TEMP tmp, TEMP dst);
16084 format %{ "umov $tmp, $vsrc, S, 0\n\t"
16085 "mul $dst, $tmp, $isrc\n\t"
16086 "umov $tmp, $vsrc, S, 1\n\t"
16087 "mul $dst, $tmp, $dst\t# mul reduction2I"
16088 %}
16089 ins_encode %{
16090 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
16091 __ mul($dst$$Register, $tmp$$Register, $isrc$$Register);
16092 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
16093 __ mul($dst$$Register, $tmp$$Register, $dst$$Register);
16094 %}
16095 ins_pipe(pipe_class_default);
16096 %}
16097
16098 instruct reduce_mul4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp, iRegINoSp itmp)
16099 %{
16100 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
16101 match(Set dst (MulReductionVI isrc vsrc));
16102 ins_cost(INSN_COST);
16103 effect(TEMP vtmp, TEMP itmp, TEMP dst);
16104 format %{ "ins $vtmp, D, $vsrc, 0, 1\n\t"
16105 "mulv $vtmp, T2S, $vtmp, $vsrc\n\t"
16106 "umov $itmp, $vtmp, S, 0\n\t"
16107 "mul $dst, $itmp, $isrc\n\t"
16108 "umov $itmp, $vtmp, S, 1\n\t"
16109 "mul $dst, $itmp, $dst\t# mul reduction4I"
16110 %}
16111 ins_encode %{
16112 __ ins(as_FloatRegister($vtmp$$reg), __ D,
16113 as_FloatRegister($vsrc$$reg), 0, 1);
16114 __ mulv(as_FloatRegister($vtmp$$reg), __ T2S,
16115 as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
16116 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 0);
16117 __ mul($dst$$Register, $itmp$$Register, $isrc$$Register);
16118 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ S, 1);
16119 __ mul($dst$$Register, $itmp$$Register, $dst$$Register);
16120 %}
17070 ins_encode %{
17071 __ fsqrt(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17072 %}
17073 ins_pipe(vsqrt_fp128);
17074 %}
17075
17076 instruct vsqrt2D(vecX dst, vecX src)
17077 %{
17078 predicate(n->as_Vector()->length() == 2);
17079 match(Set dst (SqrtVD src));
17080 format %{ "fsqrt $dst, $src\t# vector (2D)" %}
17081 ins_encode %{
17082 __ fsqrt(as_FloatRegister($dst$$reg), __ T2D,
17083 as_FloatRegister($src$$reg));
17084 %}
17085 ins_pipe(vsqrt_fp128);
17086 %}
17087
17088 // --------------------------------- ABS --------------------------------------
17089
17090 instruct vabs8B(vecD dst, vecD src)
17091 %{
17092 predicate(n->as_Vector()->length() == 4 ||
17093 n->as_Vector()->length() == 8);
17094 match(Set dst (AbsVB src));
17095 ins_cost(INSN_COST);
17096 format %{ "abs $dst, $src\t# vector (8B)" %}
17097 ins_encode %{
17098 __ absr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
17099 %}
17100 ins_pipe(vlogical64);
17101 %}
17102
17103 instruct vabs16B(vecX dst, vecX src)
17104 %{
17105 predicate(n->as_Vector()->length() == 16);
17106 match(Set dst (AbsVB src));
17107 ins_cost(INSN_COST);
17108 format %{ "abs $dst, $src\t# vector (16B)" %}
17109 ins_encode %{
17110 __ absr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
17111 %}
17112 ins_pipe(vlogical128);
17113 %}
17114
17115 instruct vabs4S(vecD dst, vecD src)
17116 %{
17117 predicate(n->as_Vector()->length() == 4);
17118 match(Set dst (AbsVS src));
17119 ins_cost(INSN_COST);
17120 format %{ "abs $dst, $src\t# vector (4H)" %}
17121 ins_encode %{
17122 __ absr(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg));
17123 %}
17124 ins_pipe(vlogical64);
17125 %}
17126
17127 instruct vabs8S(vecX dst, vecX src)
17128 %{
17129 predicate(n->as_Vector()->length() == 8);
17130 match(Set dst (AbsVS src));
17131 ins_cost(INSN_COST);
17132 format %{ "abs $dst, $src\t# vector (8H)" %}
17133 ins_encode %{
17134 __ absr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg));
17135 %}
17136 ins_pipe(vlogical128);
17137 %}
17138
17139 instruct vabs2I(vecD dst, vecD src)
17140 %{
17141 predicate(n->as_Vector()->length() == 2);
17142 match(Set dst (AbsVI src));
17143 ins_cost(INSN_COST);
17144 format %{ "abs $dst, $src\t# vector (2S)" %}
17145 ins_encode %{
17146 __ absr(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
17147 %}
17148 ins_pipe(vlogical64);
17149 %}
17150
17151 instruct vabs4I(vecX dst, vecX src)
17152 %{
17153 predicate(n->as_Vector()->length() == 4);
17154 match(Set dst (AbsVI src));
17155 ins_cost(INSN_COST);
17156 format %{ "abs $dst, $src\t# vector (4S)" %}
17157 ins_encode %{
17158 __ absr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17159 %}
17160 ins_pipe(vlogical128);
17161 %}
17162
17163 instruct vabs2L(vecX dst, vecX src)
17164 %{
17165 predicate(n->as_Vector()->length() == 2);
17166 match(Set dst (AbsVL src));
17167 ins_cost(INSN_COST);
17168 format %{ "abs $dst, $src\t# vector (2D)" %}
17169 ins_encode %{
17170 __ absr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
17171 %}
17172 ins_pipe(vlogical128);
17173 %}
17174
17175 instruct vabs2F(vecD dst, vecD src)
17176 %{
17177 predicate(n->as_Vector()->length() == 2);
17178 match(Set dst (AbsVF src));
17179 ins_cost(INSN_COST * 3);
17180 format %{ "fabs $dst,$src\t# vector (2S)" %}
17181 ins_encode %{
17182 __ fabs(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg));
17183 %}
17184 ins_pipe(vunop_fp64);
17185 %}
17186
17187 instruct vabs4F(vecX dst, vecX src)
17188 %{
17189 predicate(n->as_Vector()->length() == 4);
17190 match(Set dst (AbsVF src));
17191 ins_cost(INSN_COST * 3);
17192 format %{ "fabs $dst,$src\t# vector (4S)" %}
17193 ins_encode %{
17194 __ fabs(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg));
17195 %}
17196 ins_pipe(vunop_fp128);
17197 %}
17198
17199 instruct vabs2D(vecX dst, vecX src)
17200 %{
17201 predicate(n->as_Vector()->length() == 2);
17202 match(Set dst (AbsVD src));
17203 ins_cost(INSN_COST * 3);
17204 format %{ "fabs $dst,$src\t# vector (2D)" %}
17205 ins_encode %{
17206 __ fabs(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg));
17207 %}
17208 ins_pipe(vunop_fp128);
17209 %}
17210
17211 // --------------------------------- NEG --------------------------------------
17212
17213 instruct vneg2F(vecD dst, vecD src)
17214 %{
17215 predicate(n->as_Vector()->length() == 2);
17216 match(Set dst (NegVF src));
17217 ins_cost(INSN_COST * 3);
17218 format %{ "fneg $dst,$src\t# vector (2S)" %}
17219 ins_encode %{
17220 __ fneg(as_FloatRegister($dst$$reg), __ T2S,
17221 as_FloatRegister($src$$reg));
17222 %}
17223 ins_pipe(vunop_fp64);
17224 %}
17225
17226 instruct vneg4F(vecX dst, vecX src)
17327 %}
17328 ins_pipe(vlogical64);
17329 %}
17330
17331 instruct vxor16B(vecX dst, vecX src1, vecX src2)
17332 %{
17333 predicate(n->as_Vector()->length_in_bytes() == 16);
17334 match(Set dst (XorV src1 src2));
17335 ins_cost(INSN_COST);
17336 format %{ "xor $dst,$src1,$src2\t# vector (16B)" %}
17337 ins_encode %{
17338 __ eor(as_FloatRegister($dst$$reg), __ T16B,
17339 as_FloatRegister($src1$$reg),
17340 as_FloatRegister($src2$$reg));
17341 %}
17342 ins_pipe(vlogical128);
17343 %}
17344
17345 // ------------------------------ Shift ---------------------------------------
17346 instruct vshiftcnt8B(vecD dst, iRegIorL2I cnt) %{
17347 predicate(n->as_Vector()->length_in_bytes() == 4 ||
17348 n->as_Vector()->length_in_bytes() == 8);
17349 match(Set dst (LShiftCntV cnt));
17350 match(Set dst (RShiftCntV cnt));
17351 format %{ "dup $dst, $cnt\t# shift count vector (8B)" %}
17352 ins_encode %{
17353 __ dup(as_FloatRegister($dst$$reg), __ T8B, as_Register($cnt$$reg));
17354 %}
17355 ins_pipe(vdup_reg_reg64);
17356 %}
17357
17358 instruct vshiftcnt16B(vecX dst, iRegIorL2I cnt) %{
17359 predicate(n->as_Vector()->length_in_bytes() == 16);
17360 match(Set dst (LShiftCntV cnt));
17361 match(Set dst (RShiftCntV cnt));
17362 format %{ "dup $dst, $cnt\t# shift count vector (16B)" %}
17363 ins_encode %{
17364 __ dup(as_FloatRegister($dst$$reg), __ T16B, as_Register($cnt$$reg));
17365 %}
17366 ins_pipe(vdup_reg_reg128);
17367 %}
17368
18180 %}
18181
18182 instruct vpopcount2I(vecD dst, vecD src) %{
18183 predicate(UsePopCountInstruction && n->as_Vector()->length() == 2);
18184 match(Set dst (PopCountVI src));
18185 format %{
18186 "cnt $dst, $src\t# vector (8B)\n\t"
18187 "uaddlp $dst, $dst\t# vector (8B)\n\t"
18188 "uaddlp $dst, $dst\t# vector (4H)"
18189 %}
18190 ins_encode %{
18191 __ cnt(as_FloatRegister($dst$$reg), __ T8B,
18192 as_FloatRegister($src$$reg));
18193 __ uaddlp(as_FloatRegister($dst$$reg), __ T8B,
18194 as_FloatRegister($dst$$reg));
18195 __ uaddlp(as_FloatRegister($dst$$reg), __ T4H,
18196 as_FloatRegister($dst$$reg));
18197 %}
18198 ins_pipe(pipe_class_default);
18199 %}
18200
18201 // BEGIN This section of the file is automatically generated. Do not edit --------------
18202 // This section is generated from aarch64_neon_ad.m4
18203
18204 // ====================VECTOR INSTRUCTIONS==================================
18205
18206 // ------------------------------ Load/store/reinterpret -----------------------
18207
18208 // Load vector (16 bits)
18209 instruct loadV2(vecD dst, memory mem)
18210 %{
18211 predicate(n->as_LoadVector()->memory_size() == 2);
18212 match(Set dst (LoadVector mem));
18213 ins_cost(4 * INSN_COST);
18214 format %{ "ldrh $dst,$mem\t# vector (16 bits)" %}
18215 ins_encode( aarch64_enc_ldrvH(dst, mem) );
18216 ins_pipe(vload_reg_mem64);
18217 %}
18218
18219 // Store Vector (16 bits)
18220 instruct storeV2(vecD src, memory mem)
18221 %{
18222 predicate(n->as_StoreVector()->memory_size() == 2);
18223 match(Set mem (StoreVector mem src));
18224 ins_cost(4 * INSN_COST);
18225 format %{ "strh $mem,$src\t# vector (16 bits)" %}
18226 ins_encode( aarch64_enc_strvH(src, mem) );
18227 ins_pipe(vstore_reg_mem64);
18228 %}
18229
18230 instruct reinterpretD(vecD dst)
18231 %{
18232 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
18233 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
18234 match(Set dst (VectorReinterpret dst));
18235 ins_cost(0);
18236 format %{ " # reinterpret $dst" %}
18237 ins_encode %{
18238 // empty
18239 %}
18240 ins_pipe(pipe_class_empty);
18241 %}
18242
18243 instruct reinterpretX(vecX dst)
18244 %{
18245 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
18246 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
18247 match(Set dst (VectorReinterpret dst));
18248 ins_cost(0);
18249 format %{ " # reinterpret $dst" %}
18250 ins_encode %{
18251 // empty
18252 %}
18253 ins_pipe(pipe_class_empty);
18254 %}
18255
18256 instruct reinterpretD2X(vecX dst, vecD src)
18257 %{
18258 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 16 &&
18259 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 8);
18260 match(Set dst (VectorReinterpret src));
18261 ins_cost(INSN_COST);
18262 format %{ " # reinterpret $dst,$src" %}
18263 ins_encode %{
18264 // If register is the same, then move is not needed.
18265 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
18266 __ orr(as_FloatRegister($dst$$reg), __ T8B,
18267 as_FloatRegister($src$$reg),
18268 as_FloatRegister($src$$reg));
18269 }
18270 %}
18271 ins_pipe(vlogical64);
18272 %}
18273
18274 instruct reinterpretX2D(vecD dst, vecX src)
18275 %{
18276 predicate(n->bottom_type()->is_vect()->length_in_bytes() == 8 &&
18277 n->in(1)->bottom_type()->is_vect()->length_in_bytes() == 16);
18278 match(Set dst (VectorReinterpret src));
18279 ins_cost(INSN_COST);
18280 format %{ " # reinterpret $dst,$src" %}
18281 ins_encode %{
18282 // If register is the same, then move is not needed.
18283 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
18284 __ orr(as_FloatRegister($dst$$reg), __ T8B,
18285 as_FloatRegister($src$$reg),
18286 as_FloatRegister($src$$reg));
18287 }
18288 %}
18289 ins_pipe(vlogical64);
18290 %}
18291
18292 // ------------------------------ Vector cast -------------------------------
18293
18294 instruct vcvt4Bto4S(vecD dst, vecD src)
18295 %{
18296 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18297 match(Set dst (VectorCastB2X src));
18298 format %{ "sxtl $dst, T8H, $src, T8B\t# convert 4B to 4S vector" %}
18299 ins_encode %{
18300 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
18301 %}
18302 ins_pipe(pipe_class_default);
18303 %}
18304
18305 instruct vcvt8Bto8S(vecX dst, vecD src)
18306 %{
18307 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18308 match(Set dst (VectorCastB2X src));
18309 format %{ "sxtl $dst, T8H, $src, T8B\t# convert 8B to 8S vector" %}
18310 ins_encode %{
18311 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
18312 %}
18313 ins_pipe(pipe_class_default);
18314 %}
18315
18316 instruct vcvt4Sto4B(vecD dst, vecD src)
18317 %{
18318 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18319 match(Set dst (VectorCastS2X src));
18320 format %{ "xtn $dst, T8B, $src, T8H\t# convert 4S to 4B vector" %}
18321 ins_encode %{
18322 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
18323 %}
18324 ins_pipe(pipe_class_default);
18325 %}
18326
18327 instruct vcvt8Sto8B(vecD dst, vecX src)
18328 %{
18329 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18330 match(Set dst (VectorCastS2X src));
18331 format %{ "xtn $dst, T8B, $src, T8H\t# convert 8S to 8B vector" %}
18332 ins_encode %{
18333 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
18334 %}
18335 ins_pipe(pipe_class_default);
18336 %}
18337
18338 instruct vcvt4Sto4I(vecX dst, vecD src)
18339 %{
18340 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
18341 match(Set dst (VectorCastS2X src));
18342 format %{ "sxtl $dst, T4S, $src, T4H\t# convert 4S to 4I vector" %}
18343 ins_encode %{
18344 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
18345 %}
18346 ins_pipe(pipe_class_default);
18347 %}
18348
18349 instruct vcvt4Ito4S(vecD dst, vecX src)
18350 %{
18351 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18352 match(Set dst (VectorCastI2X src));
18353 format %{ "xtn $dst, T4H, $src, T4S\t# convert 4I to 4S vector" %}
18354 ins_encode %{
18355 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
18356 %}
18357 ins_pipe(pipe_class_default);
18358 %}
18359
18360 instruct vcvt2Ito2L(vecX dst, vecD src)
18361 %{
18362 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
18363 match(Set dst (VectorCastI2X src));
18364 format %{ "sxtl $dst, T2D, $src, T2S\t# convert 2I to 2L vector" %}
18365 ins_encode %{
18366 __ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
18367 %}
18368 ins_pipe(pipe_class_default);
18369 %}
18370
18371 instruct vcvt2Lto2I(vecD dst, vecX src)
18372 %{
18373 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
18374 match(Set dst (VectorCastL2X src));
18375 format %{ "xtn $dst, T2S, $src, T2D\t# convert 2L to 2I vector" %}
18376 ins_encode %{
18377 __ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
18378 %}
18379 ins_pipe(pipe_class_default);
18380 %}
18381
18382 instruct vcvt4Bto4I(vecX dst, vecD src)
18383 %{
18384 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
18385 match(Set dst (VectorCastB2X src));
18386 format %{ "sxtl $dst, T8H, $src, T8B\n\t"
18387 "sxtl $dst, T4S, $dst, T4H\t# convert 4B to 4I vector"
18388 %}
18389 ins_encode %{
18390 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
18391 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
18392 %}
18393 ins_pipe(pipe_slow);
18394 %}
18395
18396 instruct vcvt4Ito4B(vecD dst, vecX src)
18397 %{
18398 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18399 match(Set dst (VectorCastI2X src));
18400 format %{ "xtn $dst, T4H, $src, T4S\n\t"
18401 "xtn $dst, T8B, $dst, T8H\t# convert 4I to 4B vector"
18402 %}
18403 ins_encode %{
18404 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
18405 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
18406 %}
18407 ins_pipe(pipe_slow);
18408 %}
18409
18410 instruct vcvt4Bto4F(vecX dst, vecD src)
18411 %{
18412 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18413 match(Set dst (VectorCastB2X src));
18414 format %{ "sxtl $dst, T8H, $src, T8B\n\t"
18415 "sxtl $dst, T4S, $dst, T4H\n\t"
18416 "scvtfv T4S, $dst, $dst\t# convert 4B to 4F vector"
18417 %}
18418 ins_encode %{
18419 __ sxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
18420 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
18421 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
18422 %}
18423 ins_pipe(pipe_slow);
18424 %}
18425
18426 instruct vcvt4Sto4F(vecX dst, vecD src)
18427 %{
18428 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18429 match(Set dst (VectorCastS2X src));
18430 format %{ "sxtl $dst, T4S, $src, T4H\n\t"
18431 "scvtfv T4S, $dst, $dst\t# convert 4S to 4F vector"
18432 %}
18433 ins_encode %{
18434 __ sxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($src$$reg), __ T4H);
18435 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
18436 %}
18437 ins_pipe(pipe_slow);
18438 %}
18439
18440 instruct vcvt2Ito2D(vecX dst, vecD src)
18441 %{
18442 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
18443 match(Set dst (VectorCastI2X src));
18444 format %{ "sxtl $dst, T2D, $src, T2S\n\t"
18445 "scvtfv T2D, $dst, $dst\t# convert 2I to 2D vector"
18446 %}
18447 ins_encode %{
18448 __ sxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
18449 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($dst$$reg));
18450 %}
18451 ins_pipe(pipe_slow);
18452 %}
18453
18454 instruct vcvt2Ito2F(vecD dst, vecD src)
18455 %{
18456 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18457 match(Set dst (VectorCastI2X src));
18458 format %{ "scvtfv T2S, $dst, $src\t# convert 2I to 2F vector" %}
18459 ins_encode %{
18460 __ scvtfv(__ T2S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
18461 %}
18462 ins_pipe(pipe_class_default);
18463 %}
18464
18465 instruct vcvt4Ito4F(vecX dst, vecX src)
18466 %{
18467 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18468 match(Set dst (VectorCastI2X src));
18469 format %{ "scvtfv T4S, $dst, $src\t# convert 4I to 4F vector" %}
18470 ins_encode %{
18471 __ scvtfv(__ T4S, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
18472 %}
18473 ins_pipe(pipe_class_default);
18474 %}
18475
18476 instruct vcvt2Lto2D(vecX dst, vecX src)
18477 %{
18478 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
18479 match(Set dst (VectorCastL2X src));
18480 format %{ "scvtfv T2D, $dst, $src\t# convert 2L to 2D vector" %}
18481 ins_encode %{
18482 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
18483 %}
18484 ins_pipe(pipe_class_default);
18485 %}
18486
18487 instruct vcvt2Fto2D(vecX dst, vecD src)
18488 %{
18489 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
18490 match(Set dst (VectorCastF2X src));
18491 format %{ "fcvtl $dst, T2D, $src, T2S\t# convert 2F to 2D vector" %}
18492 ins_encode %{
18493 __ fcvtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($src$$reg), __ T2S);
18494 %}
18495 ins_pipe(pipe_class_default);
18496 %}
18497
18498 instruct vcvt2Dto2F(vecD dst, vecX src)
18499 %{
18500 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18501 match(Set dst (VectorCastD2X src));
18502 format %{ "fcvtn $dst, T2S, $src, T2D\t# convert 2D to 2F vector" %}
18503 ins_encode %{
18504 __ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
18505 %}
18506 ins_pipe(pipe_class_default);
18507 %}
18508
18509 instruct vcvt2Lto2F(vecD dst, vecX src)
18510 %{
18511 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
18512 match(Set dst (VectorCastL2X src));
18513 format %{ "scvtfv T2D, $dst, $src\n\t"
18514 "fcvtn $dst, T2S, $dst, T2D\t# convert 2L to 2F vector"
18515 %}
18516 ins_encode %{
18517 __ scvtfv(__ T2D, as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg));
18518 __ fcvtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($dst$$reg), __ T2D);
18519 %}
18520 ins_pipe(pipe_slow);
18521 %}
18522
18523 // ------------------------------ Reduction -------------------------------
18524
18525 instruct reduce_add8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
18526 %{
18527 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18528 match(Set dst (AddReductionVI isrc vsrc));
18529 ins_cost(INSN_COST);
18530 effect(TEMP_DEF dst, TEMP tmp);
18531 format %{ "addv $tmp, T8B, $vsrc\n\t"
18532 "smov $dst, $tmp, B, 0\n\t"
18533 "addw $dst, $dst, $isrc\n\t"
18534 "sxtb $dst, $dst\t# add reduction8B"
18535 %}
18536 ins_encode %{
18537 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
18538 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
18539 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
18540 __ sxtb($dst$$Register, $dst$$Register);
18541 %}
18542 ins_pipe(pipe_slow);
18543 %}
18544
18545 instruct reduce_add16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
18546 %{
18547 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18548 match(Set dst (AddReductionVI isrc vsrc));
18549 ins_cost(INSN_COST);
18550 effect(TEMP_DEF dst, TEMP tmp);
18551 format %{ "addv $tmp, T16B, $vsrc\n\t"
18552 "smov $dst, $tmp, B, 0\n\t"
18553 "addw $dst, $dst, $isrc\n\t"
18554 "sxtb $dst, $dst\t# add reduction16B"
18555 %}
18556 ins_encode %{
18557 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
18558 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
18559 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
18560 __ sxtb($dst$$Register, $dst$$Register);
18561 %}
18562 ins_pipe(pipe_slow);
18563 %}
18564
18565 instruct reduce_add4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp)
18566 %{
18567 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18568 match(Set dst (AddReductionVI isrc vsrc));
18569 ins_cost(INSN_COST);
18570 effect(TEMP_DEF dst, TEMP tmp);
18571 format %{ "addv $tmp, T4H, $vsrc\n\t"
18572 "smov $dst, $tmp, H, 0\n\t"
18573 "addw $dst, $dst, $isrc\n\t"
18574 "sxth $dst, $dst\t# add reduction4S"
18575 %}
18576 ins_encode %{
18577 __ addv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
18578 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
18579 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
18580 __ sxth($dst$$Register, $dst$$Register);
18581 %}
18582 ins_pipe(pipe_slow);
18583 %}
18584
18585 instruct reduce_add8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp)
18586 %{
18587 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18588 match(Set dst (AddReductionVI isrc vsrc));
18589 ins_cost(INSN_COST);
18590 effect(TEMP_DEF dst, TEMP tmp);
18591 format %{ "addv $tmp, T8H, $vsrc\n\t"
18592 "smov $dst, $tmp, H, 0\n\t"
18593 "addw $dst, $dst, $isrc\n\t"
18594 "sxth $dst, $dst\t# add reduction8S"
18595 %}
18596 ins_encode %{
18597 __ addv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
18598 __ smov($dst$$Register, as_FloatRegister($tmp$$reg), __ H, 0);
18599 __ addw($dst$$Register, $dst$$Register, $isrc$$Register);
18600 __ sxth($dst$$Register, $dst$$Register);
18601 %}
18602 ins_pipe(pipe_slow);
18603 %}
18604
18605 instruct reduce_add2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, vecX tmp)
18606 %{
18607 match(Set dst (AddReductionVL isrc vsrc));
18608 ins_cost(INSN_COST);
18609 effect(TEMP_DEF dst, TEMP tmp);
18610 format %{ "addpd $tmp, $vsrc\n\t"
18611 "umov $dst, $tmp, D, 0\n\t"
18612 "add $dst, $isrc, $dst\t# add reduction2L"
18613 %}
18614 ins_encode %{
18615 __ addpd(as_FloatRegister($tmp$$reg), as_FloatRegister($vsrc$$reg));
18616 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ D, 0);
18617 __ add($dst$$Register, $isrc$$Register, $dst$$Register);
18618 %}
18619 ins_pipe(pipe_slow);
18620 %}
18621
18622 instruct reduce_mul8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp1, vecD vtmp2, iRegINoSp itmp)
18623 %{
18624 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18625 match(Set dst (MulReductionVI isrc vsrc));
18626 ins_cost(INSN_COST);
18627 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
18628 format %{ "ins $vtmp1, S, $vsrc, 0, 1\n\t"
18629 "mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
18630 "ins $vtmp2, H, $vtmp1, 0, 1\n\t"
18631 "mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
18632 "umov $itmp, $vtmp2, B, 0\n\t"
18633 "mulw $dst, $itmp, $isrc\n\t"
18634 "sxtb $dst, $dst\n\t"
18635 "umov $itmp, $vtmp2, B, 1\n\t"
18636 "mulw $dst, $itmp, $dst\n\t"
18637 "sxtb $dst, $dst\t# mul reduction8B"
18638 %}
18639 ins_encode %{
18640 __ ins(as_FloatRegister($vtmp1$$reg), __ S,
18641 as_FloatRegister($vsrc$$reg), 0, 1);
18642 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
18643 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
18644 __ ins(as_FloatRegister($vtmp2$$reg), __ H,
18645 as_FloatRegister($vtmp1$$reg), 0, 1);
18646 __ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
18647 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
18648 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
18649 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
18650 __ sxtb($dst$$Register, $dst$$Register);
18651 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
18652 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
18653 __ sxtb($dst$$Register, $dst$$Register);
18654 %}
18655 ins_pipe(pipe_slow);
18656 %}
18657
18658 instruct reduce_mul16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
18659 %{
18660 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18661 match(Set dst (MulReductionVI isrc vsrc));
18662 ins_cost(INSN_COST);
18663 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
18664 format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
18665 "mulv $vtmp1, T8B, $vtmp1, $vsrc\n\t"
18666 "ins $vtmp2, S, $vtmp1, 0, 1\n\t"
18667 "mulv $vtmp1, T8B, $vtmp2, $vtmp1\n\t"
18668 "ins $vtmp2, H, $vtmp1, 0, 1\n\t"
18669 "mulv $vtmp2, T8B, $vtmp2, $vtmp1\n\t"
18670 "umov $itmp, $vtmp2, B, 0\n\t"
18671 "mulw $dst, $itmp, $isrc\n\t"
18672 "sxtb $dst, $dst\n\t"
18673 "umov $itmp, $vtmp2, B, 1\n\t"
18674 "mulw $dst, $itmp, $dst\n\t"
18675 "sxtb $dst, $dst\t# mul reduction16B"
18676 %}
18677 ins_encode %{
18678 __ ins(as_FloatRegister($vtmp1$$reg), __ D,
18679 as_FloatRegister($vsrc$$reg), 0, 1);
18680 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
18681 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
18682 __ ins(as_FloatRegister($vtmp2$$reg), __ S,
18683 as_FloatRegister($vtmp1$$reg), 0, 1);
18684 __ mulv(as_FloatRegister($vtmp1$$reg), __ T8B,
18685 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
18686 __ ins(as_FloatRegister($vtmp2$$reg), __ H,
18687 as_FloatRegister($vtmp1$$reg), 0, 1);
18688 __ mulv(as_FloatRegister($vtmp2$$reg), __ T8B,
18689 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
18690 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 0);
18691 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
18692 __ sxtb($dst$$Register, $dst$$Register);
18693 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ B, 1);
18694 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
18695 __ sxtb($dst$$Register, $dst$$Register);
18696 %}
18697 ins_pipe(pipe_slow);
18698 %}
18699
18700 instruct reduce_mul4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD vtmp, iRegINoSp itmp)
18701 %{
18702 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18703 match(Set dst (MulReductionVI isrc vsrc));
18704 ins_cost(INSN_COST);
18705 effect(TEMP_DEF dst, TEMP vtmp, TEMP itmp);
18706 format %{ "ins $vtmp, S, $vsrc, 0, 1\n\t"
18707 "mulv $vtmp, T4H, $vtmp, $vsrc\n\t"
18708 "umov $itmp, $vtmp, H, 0\n\t"
18709 "mulw $dst, $itmp, $isrc\n\t"
18710 "sxth $dst, $dst\n\t"
18711 "umov $itmp, $vtmp, H, 1\n\t"
18712 "mulw $dst, $itmp, $dst\n\t"
18713 "sxth $dst, $dst\t# mul reduction4S"
18714 %}
18715 ins_encode %{
18716 __ ins(as_FloatRegister($vtmp$$reg), __ S,
18717 as_FloatRegister($vsrc$$reg), 0, 1);
18718 __ mulv(as_FloatRegister($vtmp$$reg), __ T4H,
18719 as_FloatRegister($vtmp$$reg), as_FloatRegister($vsrc$$reg));
18720 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 0);
18721 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
18722 __ sxth($dst$$Register, $dst$$Register);
18723 __ umov($itmp$$Register, as_FloatRegister($vtmp$$reg), __ H, 1);
18724 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
18725 __ sxth($dst$$Register, $dst$$Register);
18726 %}
18727 ins_pipe(pipe_slow);
18728 %}
18729
18730 instruct reduce_mul8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX vtmp1, vecX vtmp2, iRegINoSp itmp)
18731 %{
18732 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18733 match(Set dst (MulReductionVI isrc vsrc));
18734 ins_cost(INSN_COST);
18735 effect(TEMP_DEF dst, TEMP vtmp1, TEMP vtmp2, TEMP itmp);
18736 format %{ "ins $vtmp1, D, $vsrc, 0, 1\n\t"
18737 "mulv $vtmp1, T4H, $vtmp1, $vsrc\n\t"
18738 "ins $vtmp2, S, $vtmp1, 0, 1\n\t"
18739 "mulv $vtmp2, T4H, $vtmp2, $vtmp1\n\t"
18740 "umov $itmp, $vtmp2, H, 0\n\t"
18741 "mulw $dst, $itmp, $isrc\n\t"
18742 "sxth $dst, $dst\n\t"
18743 "umov $itmp, $vtmp2, H, 1\n\t"
18744 "mulw $dst, $itmp, $dst\n\t"
18745 "sxth $dst, $dst\t# mul reduction8S"
18746 %}
18747 ins_encode %{
18748 __ ins(as_FloatRegister($vtmp1$$reg), __ D,
18749 as_FloatRegister($vsrc$$reg), 0, 1);
18750 __ mulv(as_FloatRegister($vtmp1$$reg), __ T4H,
18751 as_FloatRegister($vtmp1$$reg), as_FloatRegister($vsrc$$reg));
18752 __ ins(as_FloatRegister($vtmp2$$reg), __ S,
18753 as_FloatRegister($vtmp1$$reg), 0, 1);
18754 __ mulv(as_FloatRegister($vtmp2$$reg), __ T4H,
18755 as_FloatRegister($vtmp2$$reg), as_FloatRegister($vtmp1$$reg));
18756 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 0);
18757 __ mulw($dst$$Register, $itmp$$Register, $isrc$$Register);
18758 __ sxth($dst$$Register, $dst$$Register);
18759 __ umov($itmp$$Register, as_FloatRegister($vtmp2$$reg), __ H, 1);
18760 __ mulw($dst$$Register, $itmp$$Register, $dst$$Register);
18761 __ sxth($dst$$Register, $dst$$Register);
18762 %}
18763 ins_pipe(pipe_slow);
18764 %}
18765
18766 instruct reduce_mul2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
18767 %{
18768 match(Set dst (MulReductionVL isrc vsrc));
18769 ins_cost(INSN_COST);
18770 effect(TEMP_DEF dst, TEMP tmp);
18771 format %{ "umov $tmp, $vsrc, D, 0\n\t"
18772 "mul $dst, $isrc, $tmp\n\t"
18773 "umov $tmp, $vsrc, D, 1\n\t"
18774 "mul $dst, $dst, $tmp\t# mul reduction2L"
18775 %}
18776 ins_encode %{
18777 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
18778 __ mul($dst$$Register, $isrc$$Register, $tmp$$Register);
18779 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
18780 __ mul($dst$$Register, $dst$$Register, $tmp$$Register);
18781 %}
18782 ins_pipe(pipe_slow);
18783 %}
18784
18785 instruct reduce_max8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
18786 %{
18787 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18788 match(Set dst (MaxReductionV isrc vsrc));
18789 ins_cost(INSN_COST);
18790 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18791 format %{ "smaxv $tmp, T8B, $vsrc\n\t"
18792 "smov $dst, $tmp, B, 0\n\t"
18793 "cmpw $dst, $isrc\n\t"
18794 "cselw $dst, $dst, $isrc GT\t# max reduction8B"
18795 %}
18796 ins_encode %{
18797 __ smaxv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
18798 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
18799 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18800 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
18801 %}
18802 ins_pipe(pipe_slow);
18803 %}
18804
18805 instruct reduce_max16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18806 %{
18807 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18808 match(Set dst (MaxReductionV isrc vsrc));
18809 ins_cost(INSN_COST);
18810 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18811 format %{ "smaxv $tmp, T16B, $vsrc\n\t"
18812 "smov $dst, $tmp, B, 0\n\t"
18813 "cmpw $dst, $isrc\n\t"
18814 "cselw $dst, $dst, $isrc GT\t# max reduction16B"
18815 %}
18816 ins_encode %{
18817 __ smaxv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
18818 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
18819 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18820 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
18821 %}
18822 ins_pipe(pipe_slow);
18823 %}
18824
18825 instruct reduce_max4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
18826 %{
18827 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18828 match(Set dst (MaxReductionV isrc vsrc));
18829 ins_cost(INSN_COST);
18830 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18831 format %{ "smaxv $tmp, T4H, $vsrc\n\t"
18832 "smov $dst, $tmp, H, 0\n\t"
18833 "cmpw $dst, $isrc\n\t"
18834 "cselw $dst, $dst, $isrc GT\t# max reduction4S"
18835 %}
18836 ins_encode %{
18837 __ smaxv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
18838 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
18839 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18840 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
18841 %}
18842 ins_pipe(pipe_slow);
18843 %}
18844
18845 instruct reduce_max8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18846 %{
18847 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18848 match(Set dst (MaxReductionV isrc vsrc));
18849 ins_cost(INSN_COST);
18850 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18851 format %{ "smaxv $tmp, T8H, $vsrc\n\t"
18852 "smov $dst, $tmp, H, 0\n\t"
18853 "cmpw $dst, $isrc\n\t"
18854 "cselw $dst, $dst, $isrc GT\t# max reduction8S"
18855 %}
18856 ins_encode %{
18857 __ smaxv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
18858 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
18859 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18860 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
18861 %}
18862 ins_pipe(pipe_slow);
18863 %}
18864
18865 instruct reduce_max4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18866 %{
18867 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
18868 match(Set dst (MaxReductionV isrc vsrc));
18869 ins_cost(INSN_COST);
18870 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18871 format %{ "smaxv $tmp, T4S, $vsrc\n\t"
18872 "umov $dst, $tmp, S, 0\n\t"
18873 "cmpw $dst, $isrc\n\t"
18874 "cselw $dst, $dst, $isrc GT\t# max reduction4I"
18875 %}
18876 ins_encode %{
18877 __ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
18878 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
18879 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18880 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
18881 %}
18882 ins_pipe(pipe_slow);
18883 %}
18884
18885 instruct reduce_min8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
18886 %{
18887 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18888 match(Set dst (MinReductionV isrc vsrc));
18889 ins_cost(INSN_COST);
18890 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18891 format %{ "sminv $tmp, T8B, $vsrc\n\t"
18892 "smov $dst, $tmp, B, 0\n\t"
18893 "cmpw $dst, $isrc\n\t"
18894 "cselw $dst, $dst, $isrc LT\t# min reduction8B"
18895 %}
18896 ins_encode %{
18897 __ sminv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($vsrc$$reg));
18898 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
18899 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18900 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
18901 %}
18902 ins_pipe(pipe_slow);
18903 %}
18904
18905 instruct reduce_min16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18906 %{
18907 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
18908 match(Set dst (MinReductionV isrc vsrc));
18909 ins_cost(INSN_COST);
18910 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18911 format %{ "sminv $tmp, T16B, $vsrc\n\t"
18912 "smov $dst, $tmp, B, 0\n\t"
18913 "cmpw $dst, $isrc\n\t"
18914 "cselw $dst, $dst, $isrc LT\t# min reduction16B"
18915 %}
18916 ins_encode %{
18917 __ sminv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($vsrc$$reg));
18918 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ B, 0);
18919 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18920 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
18921 %}
18922 ins_pipe(pipe_slow);
18923 %}
18924
18925 instruct reduce_min4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecD tmp, rFlagsReg cr)
18926 %{
18927 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18928 match(Set dst (MinReductionV isrc vsrc));
18929 ins_cost(INSN_COST);
18930 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18931 format %{ "sminv $tmp, T4H, $vsrc\n\t"
18932 "smov $dst, $tmp, H, 0\n\t"
18933 "cmpw $dst, $isrc\n\t"
18934 "cselw $dst, $dst, $isrc LT\t# min reduction4S"
18935 %}
18936 ins_encode %{
18937 __ sminv(as_FloatRegister($tmp$$reg), __ T4H, as_FloatRegister($vsrc$$reg));
18938 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
18939 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18940 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
18941 %}
18942 ins_pipe(pipe_slow);
18943 %}
18944
18945 instruct reduce_min8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18946 %{
18947 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
18948 match(Set dst (MinReductionV isrc vsrc));
18949 ins_cost(INSN_COST);
18950 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18951 format %{ "sminv $tmp, T8H, $vsrc\n\t"
18952 "smov $dst, $tmp, H, 0\n\t"
18953 "cmpw $dst, $isrc\n\t"
18954 "cselw $dst, $dst, $isrc LT\t# min reduction8S"
18955 %}
18956 ins_encode %{
18957 __ sminv(as_FloatRegister($tmp$$reg), __ T8H, as_FloatRegister($vsrc$$reg));
18958 __ smov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ H, 0);
18959 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18960 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
18961 %}
18962 ins_pipe(pipe_slow);
18963 %}
18964
18965 instruct reduce_min4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, vecX tmp, rFlagsReg cr)
18966 %{
18967 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
18968 match(Set dst (MinReductionV isrc vsrc));
18969 ins_cost(INSN_COST);
18970 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18971 format %{ "sminv $tmp, T4S, $vsrc\n\t"
18972 "umov $dst, $tmp, S, 0\n\t"
18973 "cmpw $dst, $isrc\n\t"
18974 "cselw $dst, $dst, $isrc LT\t# min reduction4I"
18975 %}
18976 ins_encode %{
18977 __ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($vsrc$$reg));
18978 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
18979 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
18980 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
18981 %}
18982 ins_pipe(pipe_slow);
18983 %}
18984
18985 instruct reduce_max2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
18986 %{
18987 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
18988 match(Set dst (MaxReductionV isrc vsrc));
18989 ins_cost(INSN_COST);
18990 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
18991 format %{ "dup $tmp, T2D, $vsrc\n\t"
18992 "smaxv $tmp, T4S, $tmp\n\t"
18993 "umov $dst, $tmp, S, 0\n\t"
18994 "cmpw $dst, $isrc\n\t"
18995 "cselw $dst, $dst, $isrc GT\t# max reduction2I"
18996 %}
18997 ins_encode %{
18998 __ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
18999 __ smaxv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
19000 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
19001 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
19002 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::GT);
19003 %}
19004 ins_pipe(pipe_slow);
19005 %}
19006
19007 instruct reduce_min2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, vecX tmp, rFlagsReg cr)
19008 %{
19009 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19010 match(Set dst (MinReductionV isrc vsrc));
19011 ins_cost(INSN_COST);
19012 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
19013 format %{ "dup $tmp, T2D, $vsrc\n\t"
19014 "sminv $tmp, T4S, $tmp\n\t"
19015 "umov $dst, $tmp, S, 0\n\t"
19016 "cmpw $dst, $isrc\n\t"
19017 "cselw $dst, $dst, $isrc LT\t# min reduction2I"
19018 %}
19019 ins_encode %{
19020 __ dup(as_FloatRegister($tmp$$reg), __ T2D, as_FloatRegister($vsrc$$reg));
19021 __ sminv(as_FloatRegister($tmp$$reg), __ T4S, as_FloatRegister($tmp$$reg));
19022 __ umov(as_Register($dst$$reg), as_FloatRegister($tmp$$reg), __ S, 0);
19023 __ cmpw(as_Register($dst$$reg), as_Register($isrc$$reg));
19024 __ cselw(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($isrc$$reg), Assembler::LT);
19025 %}
19026 ins_pipe(pipe_slow);
19027 %}
19028
19029 instruct reduce_max2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
19030 %{
19031 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19032 match(Set dst (MaxReductionV isrc vsrc));
19033 ins_cost(INSN_COST);
19034 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
19035 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19036 "cmp $isrc,$tmp\n\t"
19037 "csel $dst, $isrc, $tmp GT\n\t"
19038 "umov $tmp, $vsrc, D, 1\n\t"
19039 "cmp $dst, $tmp\n\t"
19040 "csel $dst, $dst, $tmp GT\t# max reduction2L"
19041 %}
19042 ins_encode %{
19043 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
19044 __ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
19045 __ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::GT);
19046 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
19047 __ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
19048 __ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::GT);
19049 %}
19050 ins_pipe(pipe_slow);
19051 %}
19052
19053 instruct reduce_min2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp, rFlagsReg cr)
19054 %{
19055 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19056 match(Set dst (MinReductionV isrc vsrc));
19057 ins_cost(INSN_COST);
19058 effect(TEMP_DEF dst, TEMP tmp, KILL cr);
19059 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19060 "cmp $isrc,$tmp\n\t"
19061 "csel $dst, $isrc, $tmp LT\n\t"
19062 "umov $tmp, $vsrc, D, 1\n\t"
19063 "cmp $dst, $tmp\n\t"
19064 "csel $dst, $dst, $tmp LT\t# min reduction2L"
19065 %}
19066 ins_encode %{
19067 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 0);
19068 __ cmp(as_Register($isrc$$reg), as_Register($tmp$$reg));
19069 __ csel(as_Register($dst$$reg), as_Register($isrc$$reg), as_Register($tmp$$reg), Assembler::LT);
19070 __ umov(as_Register($tmp$$reg), as_FloatRegister($vsrc$$reg), __ D, 1);
19071 __ cmp(as_Register($dst$$reg), as_Register($tmp$$reg));
19072 __ csel(as_Register($dst$$reg), as_Register($dst$$reg), as_Register($tmp$$reg), Assembler::LT);
19073 %}
19074 ins_pipe(pipe_slow);
19075 %}
19076
19077 instruct reduce_and8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19078 %{
19079 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19080 match(Set dst (AndReductionV isrc vsrc));
19081 ins_cost(INSN_COST);
19082 effect(TEMP_DEF dst, TEMP tmp);
19083 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19084 "umov $dst, $vsrc, S, 1\n\t"
19085 "andw $dst, $dst, $tmp\n\t"
19086 "andw $dst, $dst, $dst, LSR #16\n\t"
19087 "andw $dst, $dst, $dst, LSR #8\n\t"
19088 "andw $dst, $isrc, $dst\n\t"
19089 "sxtb $dst, $dst\t# and reduction8B"
19090 %}
19091 ins_encode %{
19092 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19093 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19094 __ andw($dst$$Register, $dst$$Register, $tmp$$Register);
19095 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19096 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19097 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
19098 __ sxtb($dst$$Register, $dst$$Register);
19099 %}
19100 ins_pipe(pipe_slow);
19101 %}
19102
19103 instruct reduce_orr8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19104 %{
19105 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19106 match(Set dst (OrReductionV isrc vsrc));
19107 ins_cost(INSN_COST);
19108 effect(TEMP_DEF dst, TEMP tmp);
19109 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19110 "umov $dst, $vsrc, S, 1\n\t"
19111 "orrw $dst, $dst, $tmp\n\t"
19112 "orrw $dst, $dst, $dst, LSR #16\n\t"
19113 "orrw $dst, $dst, $dst, LSR #8\n\t"
19114 "orrw $dst, $isrc, $dst\n\t"
19115 "sxtb $dst, $dst\t# orr reduction8B"
19116 %}
19117 ins_encode %{
19118 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19119 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19120 __ orrw($dst$$Register, $dst$$Register, $tmp$$Register);
19121 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19122 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19123 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
19124 __ sxtb($dst$$Register, $dst$$Register);
19125 %}
19126 ins_pipe(pipe_slow);
19127 %}
19128
19129 instruct reduce_eor8B(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19130 %{
19131 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19132 match(Set dst (XorReductionV isrc vsrc));
19133 ins_cost(INSN_COST);
19134 effect(TEMP_DEF dst, TEMP tmp);
19135 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19136 "umov $dst, $vsrc, S, 1\n\t"
19137 "eorw $dst, $dst, $tmp\n\t"
19138 "eorw $dst, $dst, $dst, LSR #16\n\t"
19139 "eorw $dst, $dst, $dst, LSR #8\n\t"
19140 "eorw $dst, $isrc, $dst\n\t"
19141 "sxtb $dst, $dst\t# eor reduction8B"
19142 %}
19143 ins_encode %{
19144 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19145 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19146 __ eorw($dst$$Register, $dst$$Register, $tmp$$Register);
19147 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19148 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19149 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
19150 __ sxtb($dst$$Register, $dst$$Register);
19151 %}
19152 ins_pipe(pipe_slow);
19153 %}
19154
19155 instruct reduce_and16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19156 %{
19157 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19158 match(Set dst (AndReductionV isrc vsrc));
19159 ins_cost(INSN_COST);
19160 effect(TEMP_DEF dst, TEMP tmp);
19161 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19162 "umov $dst, $vsrc, D, 1\n\t"
19163 "andr $dst, $dst, $tmp\n\t"
19164 "andr $dst, $dst, $dst, LSR #32\n\t"
19165 "andw $dst, $dst, $dst, LSR #16\n\t"
19166 "andw $dst, $dst, $dst, LSR #8\n\t"
19167 "andw $dst, $isrc, $dst\n\t"
19168 "sxtb $dst, $dst\t# and reduction16B"
19169 %}
19170 ins_encode %{
19171 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19172 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19173 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
19174 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19175 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19176 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19177 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
19178 __ sxtb($dst$$Register, $dst$$Register);
19179 %}
19180 ins_pipe(pipe_slow);
19181 %}
19182
19183 instruct reduce_orr16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19184 %{
19185 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19186 match(Set dst (OrReductionV isrc vsrc));
19187 ins_cost(INSN_COST);
19188 effect(TEMP_DEF dst, TEMP tmp);
19189 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19190 "umov $dst, $vsrc, D, 1\n\t"
19191 "orr $dst, $dst, $tmp\n\t"
19192 "orr $dst, $dst, $dst, LSR #32\n\t"
19193 "orrw $dst, $dst, $dst, LSR #16\n\t"
19194 "orrw $dst, $dst, $dst, LSR #8\n\t"
19195 "orrw $dst, $isrc, $dst\n\t"
19196 "sxtb $dst, $dst\t# orr reduction16B"
19197 %}
19198 ins_encode %{
19199 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19200 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19201 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
19202 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19203 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19204 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19205 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
19206 __ sxtb($dst$$Register, $dst$$Register);
19207 %}
19208 ins_pipe(pipe_slow);
19209 %}
19210
19211 instruct reduce_eor16B(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19212 %{
19213 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19214 match(Set dst (XorReductionV isrc vsrc));
19215 ins_cost(INSN_COST);
19216 effect(TEMP_DEF dst, TEMP tmp);
19217 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19218 "umov $dst, $vsrc, D, 1\n\t"
19219 "eor $dst, $dst, $tmp\n\t"
19220 "eor $dst, $dst, $dst, LSR #32\n\t"
19221 "eorw $dst, $dst, $dst, LSR #16\n\t"
19222 "eorw $dst, $dst, $dst, LSR #8\n\t"
19223 "eorw $dst, $isrc, $dst\n\t"
19224 "sxtb $dst, $dst\t# eor reduction16B"
19225 %}
19226 ins_encode %{
19227 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19228 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19229 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
19230 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19231 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19232 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 8);
19233 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
19234 __ sxtb($dst$$Register, $dst$$Register);
19235 %}
19236 ins_pipe(pipe_slow);
19237 %}
19238
19239 instruct reduce_and4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19240 %{
19241 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19242 match(Set dst (AndReductionV isrc vsrc));
19243 ins_cost(INSN_COST);
19244 effect(TEMP_DEF dst, TEMP tmp);
19245 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19246 "umov $dst, $vsrc, S, 1\n\t"
19247 "andw $dst, $dst, $tmp\n\t"
19248 "andw $dst, $dst, $dst, LSR #16\n\t"
19249 "andw $dst, $isrc, $dst\n\t"
19250 "sxth $dst, $dst\t# and reduction4S"
19251 %}
19252 ins_encode %{
19253 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19254 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19255 __ andw($dst$$Register, $dst$$Register, $tmp$$Register);
19256 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19257 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
19258 __ sxth($dst$$Register, $dst$$Register);
19259 %}
19260 ins_pipe(pipe_slow);
19261 %}
19262
19263 instruct reduce_orr4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19264 %{
19265 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19266 match(Set dst (OrReductionV isrc vsrc));
19267 ins_cost(INSN_COST);
19268 effect(TEMP_DEF dst, TEMP tmp);
19269 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19270 "umov $dst, $vsrc, S, 1\n\t"
19271 "orrw $dst, $dst, $tmp\n\t"
19272 "orrw $dst, $dst, $dst, LSR #16\n\t"
19273 "orrw $dst, $isrc, $dst\n\t"
19274 "sxth $dst, $dst\t# orr reduction4S"
19275 %}
19276 ins_encode %{
19277 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19278 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19279 __ orrw($dst$$Register, $dst$$Register, $tmp$$Register);
19280 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19281 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
19282 __ sxth($dst$$Register, $dst$$Register);
19283 %}
19284 ins_pipe(pipe_slow);
19285 %}
19286
19287 instruct reduce_eor4S(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19288 %{
19289 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19290 match(Set dst (XorReductionV isrc vsrc));
19291 ins_cost(INSN_COST);
19292 effect(TEMP_DEF dst, TEMP tmp);
19293 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19294 "umov $dst, $vsrc, S, 1\n\t"
19295 "eorw $dst, $dst, $tmp\n\t"
19296 "eorw $dst, $dst, $dst, LSR #16\n\t"
19297 "eorw $dst, $isrc, $dst\n\t"
19298 "sxth $dst, $dst\t# eor reduction4S"
19299 %}
19300 ins_encode %{
19301 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19302 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19303 __ eorw($dst$$Register, $dst$$Register, $tmp$$Register);
19304 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19305 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
19306 __ sxth($dst$$Register, $dst$$Register);
19307 %}
19308 ins_pipe(pipe_slow);
19309 %}
19310
19311 instruct reduce_and8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19312 %{
19313 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19314 match(Set dst (AndReductionV isrc vsrc));
19315 ins_cost(INSN_COST);
19316 effect(TEMP_DEF dst, TEMP tmp);
19317 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19318 "umov $dst, $vsrc, D, 1\n\t"
19319 "andr $dst, $dst, $tmp\n\t"
19320 "andr $dst, $dst, $dst, LSR #32\n\t"
19321 "andw $dst, $dst, $dst, LSR #16\n\t"
19322 "andw $dst, $isrc, $dst\n\t"
19323 "sxth $dst, $dst\t# and reduction8S"
19324 %}
19325 ins_encode %{
19326 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19327 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19328 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
19329 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19330 __ andw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19331 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
19332 __ sxth($dst$$Register, $dst$$Register);
19333 %}
19334 ins_pipe(pipe_slow);
19335 %}
19336
19337 instruct reduce_orr8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19338 %{
19339 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19340 match(Set dst (OrReductionV isrc vsrc));
19341 ins_cost(INSN_COST);
19342 effect(TEMP_DEF dst, TEMP tmp);
19343 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19344 "umov $dst, $vsrc, D, 1\n\t"
19345 "orr $dst, $dst, $tmp\n\t"
19346 "orr $dst, $dst, $dst, LSR #32\n\t"
19347 "orrw $dst, $dst, $dst, LSR #16\n\t"
19348 "orrw $dst, $isrc, $dst\n\t"
19349 "sxth $dst, $dst\t# orr reduction8S"
19350 %}
19351 ins_encode %{
19352 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19353 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19354 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
19355 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19356 __ orrw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19357 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
19358 __ sxth($dst$$Register, $dst$$Register);
19359 %}
19360 ins_pipe(pipe_slow);
19361 %}
19362
19363 instruct reduce_eor8S(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19364 %{
19365 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19366 match(Set dst (XorReductionV isrc vsrc));
19367 ins_cost(INSN_COST);
19368 effect(TEMP_DEF dst, TEMP tmp);
19369 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19370 "umov $dst, $vsrc, D, 1\n\t"
19371 "eor $dst, $dst, $tmp\n\t"
19372 "eor $dst, $dst, $dst, LSR #32\n\t"
19373 "eorw $dst, $dst, $dst, LSR #16\n\t"
19374 "eorw $dst, $isrc, $dst\n\t"
19375 "sxth $dst, $dst\t# eor reduction8S"
19376 %}
19377 ins_encode %{
19378 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19379 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19380 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
19381 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19382 __ eorw($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 16);
19383 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
19384 __ sxth($dst$$Register, $dst$$Register);
19385 %}
19386 ins_pipe(pipe_slow);
19387 %}
19388
19389 instruct reduce_and2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19390 %{
19391 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19392 match(Set dst (AndReductionV isrc vsrc));
19393 ins_cost(INSN_COST);
19394 effect(TEMP_DEF dst, TEMP tmp);
19395 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19396 "andw $dst, $tmp, $isrc\n\t"
19397 "umov $tmp, $vsrc, S, 1\n\t"
19398 "andw $dst, $tmp, $dst\t# and reduction2I"
19399 %}
19400 ins_encode %{
19401 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19402 __ andw($dst$$Register, $tmp$$Register, $isrc$$Register);
19403 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19404 __ andw($dst$$Register, $tmp$$Register, $dst$$Register);
19405 %}
19406 ins_pipe(pipe_slow);
19407 %}
19408
19409 instruct reduce_orr2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19410 %{
19411 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19412 match(Set dst (OrReductionV isrc vsrc));
19413 ins_cost(INSN_COST);
19414 effect(TEMP_DEF dst, TEMP tmp);
19415 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19416 "orrw $dst, $tmp, $isrc\n\t"
19417 "umov $tmp, $vsrc, S, 1\n\t"
19418 "orrw $dst, $tmp, $dst\t# orr reduction2I"
19419 %}
19420 ins_encode %{
19421 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19422 __ orrw($dst$$Register, $tmp$$Register, $isrc$$Register);
19423 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19424 __ orrw($dst$$Register, $tmp$$Register, $dst$$Register);
19425 %}
19426 ins_pipe(pipe_slow);
19427 %}
19428
19429 instruct reduce_eor2I(iRegINoSp dst, iRegIorL2I isrc, vecD vsrc, iRegINoSp tmp)
19430 %{
19431 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19432 match(Set dst (XorReductionV isrc vsrc));
19433 ins_cost(INSN_COST);
19434 effect(TEMP_DEF dst, TEMP tmp);
19435 format %{ "umov $tmp, $vsrc, S, 0\n\t"
19436 "eorw $dst, $tmp, $isrc\n\t"
19437 "umov $tmp, $vsrc, S, 1\n\t"
19438 "eorw $dst, $tmp, $dst\t# eor reduction2I"
19439 %}
19440 ins_encode %{
19441 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 0);
19442 __ eorw($dst$$Register, $tmp$$Register, $isrc$$Register);
19443 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ S, 1);
19444 __ eorw($dst$$Register, $tmp$$Register, $dst$$Register);
19445 %}
19446 ins_pipe(pipe_slow);
19447 %}
19448
19449 instruct reduce_and4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19450 %{
19451 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19452 match(Set dst (AndReductionV isrc vsrc));
19453 ins_cost(INSN_COST);
19454 effect(TEMP_DEF dst, TEMP tmp);
19455 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19456 "umov $dst, $vsrc, D, 1\n\t"
19457 "andr $dst, $dst, $tmp\n\t"
19458 "andr $dst, $dst, $dst, LSR #32\n\t"
19459 "andw $dst, $isrc, $dst\t# and reduction4I"
19460 %}
19461 ins_encode %{
19462 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19463 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19464 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
19465 __ andr($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19466 __ andw($dst$$Register, $isrc$$Register, $dst$$Register);
19467 %}
19468 ins_pipe(pipe_slow);
19469 %}
19470
19471 instruct reduce_orr4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19472 %{
19473 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19474 match(Set dst (OrReductionV isrc vsrc));
19475 ins_cost(INSN_COST);
19476 effect(TEMP_DEF dst, TEMP tmp);
19477 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19478 "umov $dst, $vsrc, D, 1\n\t"
19479 "orr $dst, $dst, $tmp\n\t"
19480 "orr $dst, $dst, $dst, LSR #32\n\t"
19481 "orrw $dst, $isrc, $dst\t# orr reduction4I"
19482 %}
19483 ins_encode %{
19484 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19485 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19486 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
19487 __ orr ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19488 __ orrw($dst$$Register, $isrc$$Register, $dst$$Register);
19489 %}
19490 ins_pipe(pipe_slow);
19491 %}
19492
19493 instruct reduce_eor4I(iRegINoSp dst, iRegIorL2I isrc, vecX vsrc, iRegINoSp tmp)
19494 %{
19495 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19496 match(Set dst (XorReductionV isrc vsrc));
19497 ins_cost(INSN_COST);
19498 effect(TEMP_DEF dst, TEMP tmp);
19499 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19500 "umov $dst, $vsrc, D, 1\n\t"
19501 "eor $dst, $dst, $tmp\n\t"
19502 "eor $dst, $dst, $dst, LSR #32\n\t"
19503 "eorw $dst, $isrc, $dst\t# eor reduction4I"
19504 %}
19505 ins_encode %{
19506 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19507 __ umov($dst$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19508 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
19509 __ eor ($dst$$Register, $dst$$Register, $dst$$Register, Assembler::LSR, 32);
19510 __ eorw($dst$$Register, $isrc$$Register, $dst$$Register);
19511 %}
19512 ins_pipe(pipe_slow);
19513 %}
19514
19515 instruct reduce_and2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
19516 %{
19517 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19518 match(Set dst (AndReductionV isrc vsrc));
19519 ins_cost(INSN_COST);
19520 effect(TEMP_DEF dst, TEMP tmp);
19521 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19522 "andr $dst, $isrc, $tmp\n\t"
19523 "umov $tmp, $vsrc, D, 1\n\t"
19524 "andr $dst, $dst, $tmp\t# and reduction2L"
19525 %}
19526 ins_encode %{
19527 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19528 __ andr($dst$$Register, $isrc$$Register, $tmp$$Register);
19529 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19530 __ andr($dst$$Register, $dst$$Register, $tmp$$Register);
19531 %}
19532 ins_pipe(pipe_slow);
19533 %}
19534
19535 instruct reduce_orr2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
19536 %{
19537 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19538 match(Set dst (OrReductionV isrc vsrc));
19539 ins_cost(INSN_COST);
19540 effect(TEMP_DEF dst, TEMP tmp);
19541 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19542 "orr $dst, $isrc, $tmp\n\t"
19543 "umov $tmp, $vsrc, D, 1\n\t"
19544 "orr $dst, $dst, $tmp\t# orr reduction2L"
19545 %}
19546 ins_encode %{
19547 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19548 __ orr ($dst$$Register, $isrc$$Register, $tmp$$Register);
19549 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19550 __ orr ($dst$$Register, $dst$$Register, $tmp$$Register);
19551 %}
19552 ins_pipe(pipe_slow);
19553 %}
19554
19555 instruct reduce_eor2L(iRegLNoSp dst, iRegL isrc, vecX vsrc, iRegLNoSp tmp)
19556 %{
19557 predicate(n->in(2)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19558 match(Set dst (XorReductionV isrc vsrc));
19559 ins_cost(INSN_COST);
19560 effect(TEMP_DEF dst, TEMP tmp);
19561 format %{ "umov $tmp, $vsrc, D, 0\n\t"
19562 "eor $dst, $isrc, $tmp\n\t"
19563 "umov $tmp, $vsrc, D, 1\n\t"
19564 "eor $dst, $dst, $tmp\t# eor reduction2L"
19565 %}
19566 ins_encode %{
19567 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 0);
19568 __ eor ($dst$$Register, $isrc$$Register, $tmp$$Register);
19569 __ umov($tmp$$Register, as_FloatRegister($vsrc$$reg), __ D, 1);
19570 __ eor ($dst$$Register, $dst$$Register, $tmp$$Register);
19571 %}
19572 ins_pipe(pipe_slow);
19573 %}
19574
19575 // ------------------------------ Vector insert ---------------------------------
19576
19577 instruct insert8B(vecD dst, vecD src, iRegIorL2I val, immI idx)
19578 %{
19579 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19580 match(Set dst (VectorInsert (Binary src val) idx));
19581 ins_cost(INSN_COST);
19582 format %{ "orr $dst, T8B, $src, $src\n\t"
19583 "mov $dst, T8B, $idx, $val\t# insert into vector(8B)" %}
19584 ins_encode %{
19585 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19586 __ orr(as_FloatRegister($dst$$reg), __ T8B,
19587 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19588 }
19589 __ mov(as_FloatRegister($dst$$reg), __ T8B, $idx$$constant, $val$$Register);
19590 %}
19591 ins_pipe(pipe_slow);
19592 %}
19593
19594 instruct insert16B(vecX dst, vecX src, iRegIorL2I val, immI idx)
19595 %{
19596 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19597 match(Set dst (VectorInsert (Binary src val) idx));
19598 ins_cost(INSN_COST);
19599 format %{ "orr $dst, T16B, $src, $src\n\t"
19600 "mov $dst, T16B, $idx, $val\t# insert into vector(16B)" %}
19601 ins_encode %{
19602 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19603 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19604 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19605 }
19606 __ mov(as_FloatRegister($dst$$reg), __ T16B, $idx$$constant, $val$$Register);
19607 %}
19608 ins_pipe(pipe_slow);
19609 %}
19610
19611 instruct insert4S(vecD dst, vecD src, iRegIorL2I val, immI idx)
19612 %{
19613 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19614 match(Set dst (VectorInsert (Binary src val) idx));
19615 ins_cost(INSN_COST);
19616 format %{ "orr $dst, T8B, $src, $src\n\t"
19617 "mov $dst, T4H, $idx, $val\t# insert into vector(4S)" %}
19618 ins_encode %{
19619 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19620 __ orr(as_FloatRegister($dst$$reg), __ T8B,
19621 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19622 }
19623 __ mov(as_FloatRegister($dst$$reg), __ T4H, $idx$$constant, $val$$Register);
19624 %}
19625 ins_pipe(pipe_slow);
19626 %}
19627
19628 instruct insert8S(vecX dst, vecX src, iRegIorL2I val, immI idx)
19629 %{
19630 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19631 match(Set dst (VectorInsert (Binary src val) idx));
19632 ins_cost(INSN_COST);
19633 format %{ "orr $dst, T16B, $src, $src\n\t"
19634 "mov $dst, T8H, $idx, $val\t# insert into vector(8S)" %}
19635 ins_encode %{
19636 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19637 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19638 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19639 }
19640 __ mov(as_FloatRegister($dst$$reg), __ T8H, $idx$$constant, $val$$Register);
19641 %}
19642 ins_pipe(pipe_slow);
19643 %}
19644
19645 instruct insert2I(vecD dst, vecD src, iRegIorL2I val, immI idx)
19646 %{
19647 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_INT);
19648 match(Set dst (VectorInsert (Binary src val) idx));
19649 ins_cost(INSN_COST);
19650 format %{ "orr $dst, T8B, $src, $src\n\t"
19651 "mov $dst, T2S, $idx, $val\t# insert into vector(2I)" %}
19652 ins_encode %{
19653 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19654 __ orr(as_FloatRegister($dst$$reg), __ T8B,
19655 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19656 }
19657 __ mov(as_FloatRegister($dst$$reg), __ T2S, $idx$$constant, $val$$Register);
19658 %}
19659 ins_pipe(pipe_slow);
19660 %}
19661
19662 instruct insert4I(vecX dst, vecX src, iRegIorL2I val, immI idx)
19663 %{
19664 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_INT);
19665 match(Set dst (VectorInsert (Binary src val) idx));
19666 ins_cost(INSN_COST);
19667 format %{ "orr $dst, T16B, $src, $src\n\t"
19668 "mov $dst, T4S, $idx, $val\t# insert into vector(4I)" %}
19669 ins_encode %{
19670 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19671 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19672 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19673 }
19674 __ mov(as_FloatRegister($dst$$reg), __ T4S, $idx$$constant, $val$$Register);
19675 %}
19676 ins_pipe(pipe_slow);
19677 %}
19678
19679 instruct insert2L(vecX dst, vecX src, iRegL val, immI idx)
19680 %{
19681 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19682 match(Set dst (VectorInsert (Binary src val) idx));
19683 ins_cost(INSN_COST);
19684 format %{ "orr $dst, T16B, $src, $src\n\t"
19685 "mov $dst, T2D, $idx, $val\t# insert into vector(2L)" %}
19686 ins_encode %{
19687 if (as_FloatRegister($dst$$reg) != as_FloatRegister($src$$reg)) {
19688 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19689 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19690 }
19691 __ mov(as_FloatRegister($dst$$reg), __ T2D, $idx$$constant, $val$$Register);
19692 %}
19693 ins_pipe(pipe_slow);
19694 %}
19695
19696 instruct insert2F(vecD dst, vecD src, vRegF val, immI idx)
19697 %{
19698 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
19699 match(Set dst (VectorInsert (Binary src val) idx));
19700 ins_cost(INSN_COST);
19701 effect(TEMP_DEF dst);
19702 format %{ "orr $dst, T8B, $src, $src\n\t"
19703 "ins $dst, S, $val, $idx, 0\t# insert into vector(2F)" %}
19704 ins_encode %{
19705 __ orr(as_FloatRegister($dst$$reg), __ T8B,
19706 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19707 __ ins(as_FloatRegister($dst$$reg), __ S,
19708 as_FloatRegister($val$$reg), $idx$$constant, 0);
19709 %}
19710 ins_pipe(pipe_slow);
19711 %}
19712
19713 instruct insert4F(vecX dst, vecX src, vRegF val, immI idx)
19714 %{
19715 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
19716 match(Set dst (VectorInsert (Binary src val) idx));
19717 ins_cost(INSN_COST);
19718 effect(TEMP_DEF dst);
19719 format %{ "orr $dst, T16B, $src, $src\n\t"
19720 "ins $dst, S, $val, $idx, 0\t# insert into vector(4F)" %}
19721 ins_encode %{
19722 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19723 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19724 __ ins(as_FloatRegister($dst$$reg), __ S,
19725 as_FloatRegister($val$$reg), $idx$$constant, 0);
19726 %}
19727 ins_pipe(pipe_slow);
19728 %}
19729
19730 instruct insert2D(vecX dst, vecX src, vRegD val, immI idx)
19731 %{
19732 predicate(n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
19733 match(Set dst (VectorInsert (Binary src val) idx));
19734 ins_cost(INSN_COST);
19735 effect(TEMP_DEF dst);
19736 format %{ "orr $dst, T16B, $src, $src\n\t"
19737 "ins $dst, D, $val, $idx, 0\t# insert into vector(2D)" %}
19738 ins_encode %{
19739 __ orr(as_FloatRegister($dst$$reg), __ T16B,
19740 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
19741 __ ins(as_FloatRegister($dst$$reg), __ D,
19742 as_FloatRegister($val$$reg), $idx$$constant, 0);
19743 %}
19744 ins_pipe(pipe_slow);
19745 %}
19746
19747 // ------------------------------ Vector extract ---------------------------------
19748
19749 instruct extract8B(iRegINoSp dst, vecD src, immI idx)
19750 %{
19751 predicate(n->in(1)->bottom_type()->is_vect()->length() == 8);
19752 match(Set dst (ExtractB src idx));
19753 ins_cost(INSN_COST);
19754 format %{ "smov $dst, $src, B, $idx\t# extract from vector(8B)" %}
19755 ins_encode %{
19756 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ B, $idx$$constant);
19757 %}
19758 ins_pipe(pipe_class_default);
19759 %}
19760
19761 instruct extract16B(iRegINoSp dst, vecX src, immI idx)
19762 %{
19763 predicate(n->in(1)->bottom_type()->is_vect()->length() == 16);
19764 match(Set dst (ExtractB src idx));
19765 ins_cost(INSN_COST);
19766 format %{ "smov $dst, $src, B, $idx\t# extract from vector(16B)" %}
19767 ins_encode %{
19768 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ B, $idx$$constant);
19769 %}
19770 ins_pipe(pipe_class_default);
19771 %}
19772
19773 instruct extract4S(iRegINoSp dst, vecD src, immI idx)
19774 %{
19775 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
19776 match(Set dst (ExtractS src idx));
19777 ins_cost(INSN_COST);
19778 format %{ "smov $dst, $src, H, $idx\t# extract from vector(4S)" %}
19779 ins_encode %{
19780 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ H, $idx$$constant);
19781 %}
19782 ins_pipe(pipe_class_default);
19783 %}
19784
19785 instruct extract8S(iRegINoSp dst, vecX src, immI idx)
19786 %{
19787 predicate(n->in(1)->bottom_type()->is_vect()->length() == 8);
19788 match(Set dst (ExtractS src idx));
19789 ins_cost(INSN_COST);
19790 format %{ "smov $dst, $src, H, $idx\t# extract from vector(8S)" %}
19791 ins_encode %{
19792 __ smov($dst$$Register, as_FloatRegister($src$$reg), __ H, $idx$$constant);
19793 %}
19794 ins_pipe(pipe_class_default);
19795 %}
19796
19797 instruct extract2I(iRegINoSp dst, vecD src, immI idx)
19798 %{
19799 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
19800 match(Set dst (ExtractI src idx));
19801 ins_cost(INSN_COST);
19802 format %{ "umov $dst, $src, S, $idx\t# extract from vector(2I)" %}
19803 ins_encode %{
19804 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ S, $idx$$constant);
19805 %}
19806 ins_pipe(pipe_class_default);
19807 %}
19808
19809 instruct extract4I(iRegINoSp dst, vecX src, immI idx)
19810 %{
19811 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
19812 match(Set dst (ExtractI src idx));
19813 ins_cost(INSN_COST);
19814 format %{ "umov $dst, $src, S, $idx\t# extract from vector(4I)" %}
19815 ins_encode %{
19816 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ S, $idx$$constant);
19817 %}
19818 ins_pipe(pipe_class_default);
19819 %}
19820
19821 instruct extract2L(iRegLNoSp dst, vecX src, immI idx)
19822 %{
19823 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
19824 match(Set dst (ExtractL src idx));
19825 ins_cost(INSN_COST);
19826 format %{ "umov $dst, $src, D, $idx\t# extract from vector(2L)" %}
19827 ins_encode %{
19828 __ umov($dst$$Register, as_FloatRegister($src$$reg), __ D, $idx$$constant);
19829 %}
19830 ins_pipe(pipe_class_default);
19831 %}
19832
19833 instruct extract2F(vRegF dst, vecD src, immI idx)
19834 %{
19835 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
19836 match(Set dst (ExtractF src idx));
19837 ins_cost(INSN_COST);
19838 format %{ "ins $dst, S, $src, 0, $idx\t# extract from vector(2F)" %}
19839 ins_encode %{
19840 __ ins(as_FloatRegister($dst$$reg), __ S,
19841 as_FloatRegister($src$$reg), 0, $idx$$constant);
19842 %}
19843 ins_pipe(pipe_class_default);
19844 %}
19845
19846 instruct extract4F(vRegF dst, vecX src, immI idx)
19847 %{
19848 predicate(n->in(1)->bottom_type()->is_vect()->length() == 4);
19849 match(Set dst (ExtractF src idx));
19850 ins_cost(INSN_COST);
19851 format %{ "ins $dst, S, $src, 0, $idx\t# extract from vector(4F)" %}
19852 ins_encode %{
19853 __ ins(as_FloatRegister($dst$$reg), __ S,
19854 as_FloatRegister($src$$reg), 0, $idx$$constant);
19855 %}
19856 ins_pipe(pipe_class_default);
19857 %}
19858
19859 instruct extract2D(vRegD dst, vecX src, immI idx)
19860 %{
19861 predicate(n->in(1)->bottom_type()->is_vect()->length() == 2);
19862 match(Set dst (ExtractD src idx));
19863 ins_cost(INSN_COST);
19864 format %{ "ins $dst, D, $src, 0, $idx\t# extract from vector(2D)" %}
19865 ins_encode %{
19866 __ ins(as_FloatRegister($dst$$reg), __ D,
19867 as_FloatRegister($src$$reg), 0, $idx$$constant);
19868 %}
19869 ins_pipe(pipe_class_default);
19870 %}
19871
19872 // ------------------------------ Vector comparison ---------------------------------
19873
19874 instruct vcmeq8B(vecD dst, vecD src1, vecD src2, immI cond)
19875 %{
19876 predicate(n->as_Vector()->length() == 8 &&
19877 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19878 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19879 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19880 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (8B)" %}
19881 ins_cost(INSN_COST);
19882 ins_encode %{
19883 __ cmeq(as_FloatRegister($dst$$reg), __ T8B,
19884 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19885 %}
19886 ins_pipe(vdop64);
19887 %}
19888
19889 instruct vcmeq16B(vecX dst, vecX src1, vecX src2, immI cond)
19890 %{
19891 predicate(n->as_Vector()->length() == 16 &&
19892 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19893 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
19894 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19895 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (16B)" %}
19896 ins_cost(INSN_COST);
19897 ins_encode %{
19898 __ cmeq(as_FloatRegister($dst$$reg), __ T16B,
19899 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19900 %}
19901 ins_pipe(vdop128);
19902 %}
19903
19904 instruct vcmeq4S(vecD dst, vecD src1, vecD src2, immI cond)
19905 %{
19906 predicate(n->as_Vector()->length() == 4 &&
19907 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19908 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19909 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19910 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (4S)" %}
19911 ins_cost(INSN_COST);
19912 ins_encode %{
19913 __ cmeq(as_FloatRegister($dst$$reg), __ T4H,
19914 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19915 %}
19916 ins_pipe(vdop64);
19917 %}
19918
19919 instruct vcmeq8S(vecX dst, vecX src1, vecX src2, immI cond)
19920 %{
19921 predicate(n->as_Vector()->length() == 8 &&
19922 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19923 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
19924 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19925 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (8S)" %}
19926 ins_cost(INSN_COST);
19927 ins_encode %{
19928 __ cmeq(as_FloatRegister($dst$$reg), __ T8H,
19929 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19930 %}
19931 ins_pipe(vdop128);
19932 %}
19933
19934 instruct vcmeq2I(vecD dst, vecD src1, vecD src2, immI cond)
19935 %{
19936 predicate(n->as_Vector()->length() == 2 &&
19937 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19938 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19939 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19940 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (2I)" %}
19941 ins_cost(INSN_COST);
19942 ins_encode %{
19943 __ cmeq(as_FloatRegister($dst$$reg), __ T2S,
19944 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19945 %}
19946 ins_pipe(vdop64);
19947 %}
19948
19949 instruct vcmeq4I(vecX dst, vecX src1, vecX src2, immI cond)
19950 %{
19951 predicate(n->as_Vector()->length() == 4 &&
19952 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19953 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
19954 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19955 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (4I)" %}
19956 ins_cost(INSN_COST);
19957 ins_encode %{
19958 __ cmeq(as_FloatRegister($dst$$reg), __ T4S,
19959 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19960 %}
19961 ins_pipe(vdop128);
19962 %}
19963
19964 instruct vcmeq2L(vecX dst, vecX src1, vecX src2, immI cond)
19965 %{
19966 predicate(n->as_Vector()->length() == 2 &&
19967 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19968 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
19969 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19970 format %{ "cmeq $dst, $src1, $src2\t# vector cmp (2L)" %}
19971 ins_cost(INSN_COST);
19972 ins_encode %{
19973 __ cmeq(as_FloatRegister($dst$$reg), __ T2D,
19974 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19975 %}
19976 ins_pipe(vdop128);
19977 %}
19978
19979 instruct vcmeq2F(vecD dst, vecD src1, vecD src2, immI cond)
19980 %{
19981 predicate(n->as_Vector()->length() == 2 &&
19982 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19983 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
19984 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
19985 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (2F)" %}
19986 ins_cost(INSN_COST);
19987 ins_encode %{
19988 __ fcmeq(as_FloatRegister($dst$$reg), __ T2S,
19989 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
19990 %}
19991 ins_pipe(vdop64);
19992 %}
19993
19994 instruct vcmeq4F(vecX dst, vecX src1, vecX src2, immI cond)
19995 %{
19996 predicate(n->as_Vector()->length() == 4 &&
19997 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
19998 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
19999 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20000 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (4F)" %}
20001 ins_cost(INSN_COST);
20002 ins_encode %{
20003 __ fcmeq(as_FloatRegister($dst$$reg), __ T4S,
20004 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20005 %}
20006 ins_pipe(vdop128);
20007 %}
20008
20009 instruct vcmeq2D(vecX dst, vecX src1, vecX src2, immI cond)
20010 %{
20011 predicate(n->as_Vector()->length() == 2 &&
20012 n->as_VectorMaskCmp()->get_predicate() == BoolTest::eq &&
20013 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20014 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20015 format %{ "fcmeq $dst, $src1, $src2\t# vector cmp (2D)" %}
20016 ins_cost(INSN_COST);
20017 ins_encode %{
20018 __ fcmeq(as_FloatRegister($dst$$reg), __ T2D,
20019 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20020 %}
20021 ins_pipe(vdop128);
20022 %}
20023
20024 instruct vcmgt8B(vecD dst, vecD src1, vecD src2, immI cond)
20025 %{
20026 predicate(n->as_Vector()->length() == 8 &&
20027 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20028 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20029 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20030 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (8B)" %}
20031 ins_cost(INSN_COST);
20032 ins_encode %{
20033 __ cmgt(as_FloatRegister($dst$$reg), __ T8B,
20034 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20035 %}
20036 ins_pipe(vdop64);
20037 %}
20038
20039 instruct vcmgt16B(vecX dst, vecX src1, vecX src2, immI cond)
20040 %{
20041 predicate(n->as_Vector()->length() == 16 &&
20042 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20043 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20044 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20045 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (16B)" %}
20046 ins_cost(INSN_COST);
20047 ins_encode %{
20048 __ cmgt(as_FloatRegister($dst$$reg), __ T16B,
20049 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20050 %}
20051 ins_pipe(vdop128);
20052 %}
20053
20054 instruct vcmgt4S(vecD dst, vecD src1, vecD src2, immI cond)
20055 %{
20056 predicate(n->as_Vector()->length() == 4 &&
20057 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20058 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20059 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20060 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (4S)" %}
20061 ins_cost(INSN_COST);
20062 ins_encode %{
20063 __ cmgt(as_FloatRegister($dst$$reg), __ T4H,
20064 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20065 %}
20066 ins_pipe(vdop64);
20067 %}
20068
20069 instruct vcmgt8S(vecX dst, vecX src1, vecX src2, immI cond)
20070 %{
20071 predicate(n->as_Vector()->length() == 8 &&
20072 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20073 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20074 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20075 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (8S)" %}
20076 ins_cost(INSN_COST);
20077 ins_encode %{
20078 __ cmgt(as_FloatRegister($dst$$reg), __ T8H,
20079 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20080 %}
20081 ins_pipe(vdop128);
20082 %}
20083
20084 instruct vcmgt2I(vecD dst, vecD src1, vecD src2, immI cond)
20085 %{
20086 predicate(n->as_Vector()->length() == 2 &&
20087 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20088 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20089 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20090 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (2I)" %}
20091 ins_cost(INSN_COST);
20092 ins_encode %{
20093 __ cmgt(as_FloatRegister($dst$$reg), __ T2S,
20094 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20095 %}
20096 ins_pipe(vdop64);
20097 %}
20098
20099 instruct vcmgt4I(vecX dst, vecX src1, vecX src2, immI cond)
20100 %{
20101 predicate(n->as_Vector()->length() == 4 &&
20102 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20103 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20104 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20105 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (4I)" %}
20106 ins_cost(INSN_COST);
20107 ins_encode %{
20108 __ cmgt(as_FloatRegister($dst$$reg), __ T4S,
20109 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20110 %}
20111 ins_pipe(vdop128);
20112 %}
20113
20114 instruct vcmgt2L(vecX dst, vecX src1, vecX src2, immI cond)
20115 %{
20116 predicate(n->as_Vector()->length() == 2 &&
20117 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20118 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
20119 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20120 format %{ "cmgt $dst, $src1, $src2\t# vector cmp (2L)" %}
20121 ins_cost(INSN_COST);
20122 ins_encode %{
20123 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
20124 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20125 %}
20126 ins_pipe(vdop128);
20127 %}
20128
20129 instruct vcmgt2F(vecD dst, vecD src1, vecD src2, immI cond)
20130 %{
20131 predicate(n->as_Vector()->length() == 2 &&
20132 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20133 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20134 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20135 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (2F)" %}
20136 ins_cost(INSN_COST);
20137 ins_encode %{
20138 __ fcmgt(as_FloatRegister($dst$$reg), __ T2S,
20139 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20140 %}
20141 ins_pipe(vdop64);
20142 %}
20143
20144 instruct vcmgt4F(vecX dst, vecX src1, vecX src2, immI cond)
20145 %{
20146 predicate(n->as_Vector()->length() == 4 &&
20147 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20148 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20149 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20150 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (4F)" %}
20151 ins_cost(INSN_COST);
20152 ins_encode %{
20153 __ fcmgt(as_FloatRegister($dst$$reg), __ T4S,
20154 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20155 %}
20156 ins_pipe(vdop128);
20157 %}
20158
20159 instruct vcmgt2D(vecX dst, vecX src1, vecX src2, immI cond)
20160 %{
20161 predicate(n->as_Vector()->length() == 2 &&
20162 n->as_VectorMaskCmp()->get_predicate() == BoolTest::gt &&
20163 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20164 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20165 format %{ "fcmgt $dst, $src1, $src2\t# vector cmp (2D)" %}
20166 ins_cost(INSN_COST);
20167 ins_encode %{
20168 __ fcmgt(as_FloatRegister($dst$$reg), __ T2D,
20169 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20170 %}
20171 ins_pipe(vdop128);
20172 %}
20173
20174 instruct vcmge8B(vecD dst, vecD src1, vecD src2, immI cond)
20175 %{
20176 predicate(n->as_Vector()->length() == 8 &&
20177 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20178 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20179 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20180 format %{ "cmge $dst, $src1, $src2\t# vector cmp (8B)" %}
20181 ins_cost(INSN_COST);
20182 ins_encode %{
20183 __ cmge(as_FloatRegister($dst$$reg), __ T8B,
20184 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20185 %}
20186 ins_pipe(vdop64);
20187 %}
20188
20189 instruct vcmge16B(vecX dst, vecX src1, vecX src2, immI cond)
20190 %{
20191 predicate(n->as_Vector()->length() == 16 &&
20192 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20193 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20194 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20195 format %{ "cmge $dst, $src1, $src2\t# vector cmp (16B)" %}
20196 ins_cost(INSN_COST);
20197 ins_encode %{
20198 __ cmge(as_FloatRegister($dst$$reg), __ T16B,
20199 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20200 %}
20201 ins_pipe(vdop128);
20202 %}
20203
20204 instruct vcmge4S(vecD dst, vecD src1, vecD src2, immI cond)
20205 %{
20206 predicate(n->as_Vector()->length() == 4 &&
20207 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20208 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20209 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20210 format %{ "cmge $dst, $src1, $src2\t# vector cmp (4S)" %}
20211 ins_cost(INSN_COST);
20212 ins_encode %{
20213 __ cmge(as_FloatRegister($dst$$reg), __ T4H,
20214 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20215 %}
20216 ins_pipe(vdop64);
20217 %}
20218
20219 instruct vcmge8S(vecX dst, vecX src1, vecX src2, immI cond)
20220 %{
20221 predicate(n->as_Vector()->length() == 8 &&
20222 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20223 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20224 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20225 format %{ "cmge $dst, $src1, $src2\t# vector cmp (8S)" %}
20226 ins_cost(INSN_COST);
20227 ins_encode %{
20228 __ cmge(as_FloatRegister($dst$$reg), __ T8H,
20229 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20230 %}
20231 ins_pipe(vdop128);
20232 %}
20233
20234 instruct vcmge2I(vecD dst, vecD src1, vecD src2, immI cond)
20235 %{
20236 predicate(n->as_Vector()->length() == 2 &&
20237 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20238 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20239 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20240 format %{ "cmge $dst, $src1, $src2\t# vector cmp (2I)" %}
20241 ins_cost(INSN_COST);
20242 ins_encode %{
20243 __ cmge(as_FloatRegister($dst$$reg), __ T2S,
20244 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20245 %}
20246 ins_pipe(vdop64);
20247 %}
20248
20249 instruct vcmge4I(vecX dst, vecX src1, vecX src2, immI cond)
20250 %{
20251 predicate(n->as_Vector()->length() == 4 &&
20252 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20253 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20254 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20255 format %{ "cmge $dst, $src1, $src2\t# vector cmp (4I)" %}
20256 ins_cost(INSN_COST);
20257 ins_encode %{
20258 __ cmge(as_FloatRegister($dst$$reg), __ T4S,
20259 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20260 %}
20261 ins_pipe(vdop128);
20262 %}
20263
20264 instruct vcmge2L(vecX dst, vecX src1, vecX src2, immI cond)
20265 %{
20266 predicate(n->as_Vector()->length() == 2 &&
20267 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20268 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
20269 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20270 format %{ "cmge $dst, $src1, $src2\t# vector cmp (2L)" %}
20271 ins_cost(INSN_COST);
20272 ins_encode %{
20273 __ cmge(as_FloatRegister($dst$$reg), __ T2D,
20274 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20275 %}
20276 ins_pipe(vdop128);
20277 %}
20278
20279 instruct vcmge2F(vecD dst, vecD src1, vecD src2, immI cond)
20280 %{
20281 predicate(n->as_Vector()->length() == 2 &&
20282 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20283 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20284 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20285 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (2F)" %}
20286 ins_cost(INSN_COST);
20287 ins_encode %{
20288 __ fcmge(as_FloatRegister($dst$$reg), __ T2S,
20289 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20290 %}
20291 ins_pipe(vdop64);
20292 %}
20293
20294 instruct vcmge4F(vecX dst, vecX src1, vecX src2, immI cond)
20295 %{
20296 predicate(n->as_Vector()->length() == 4 &&
20297 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20298 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20299 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20300 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (4F)" %}
20301 ins_cost(INSN_COST);
20302 ins_encode %{
20303 __ fcmge(as_FloatRegister($dst$$reg), __ T4S,
20304 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20305 %}
20306 ins_pipe(vdop128);
20307 %}
20308
20309 instruct vcmge2D(vecX dst, vecX src1, vecX src2, immI cond)
20310 %{
20311 predicate(n->as_Vector()->length() == 2 &&
20312 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ge &&
20313 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20314 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20315 format %{ "fcmge $dst, $src1, $src2\t# vector cmp (2D)" %}
20316 ins_cost(INSN_COST);
20317 ins_encode %{
20318 __ fcmge(as_FloatRegister($dst$$reg), __ T2D,
20319 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20320 %}
20321 ins_pipe(vdop128);
20322 %}
20323
20324 instruct vcmne8B(vecD dst, vecD src1, vecD src2, immI cond)
20325 %{
20326 predicate(n->as_Vector()->length() == 8 &&
20327 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20328 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20329 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20330 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (8B)"
20331 "not $dst, $dst\t" %}
20332 ins_cost(INSN_COST);
20333 ins_encode %{
20334 __ cmeq(as_FloatRegister($dst$$reg), __ T8B,
20335 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20336 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
20337 %}
20338 ins_pipe(pipe_slow);
20339 %}
20340
20341 instruct vcmne16B(vecX dst, vecX src1, vecX src2, immI cond)
20342 %{
20343 predicate(n->as_Vector()->length() == 16 &&
20344 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20345 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20346 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20347 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (16B)"
20348 "not $dst, $dst\t" %}
20349 ins_cost(INSN_COST);
20350 ins_encode %{
20351 __ cmeq(as_FloatRegister($dst$$reg), __ T16B,
20352 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20353 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20354 %}
20355 ins_pipe(pipe_slow);
20356 %}
20357
20358 instruct vcmne4S(vecD dst, vecD src1, vecD src2, immI cond)
20359 %{
20360 predicate(n->as_Vector()->length() == 4 &&
20361 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20362 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20363 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20364 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (4S)"
20365 "not $dst, $dst\t" %}
20366 ins_cost(INSN_COST);
20367 ins_encode %{
20368 __ cmeq(as_FloatRegister($dst$$reg), __ T4H,
20369 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20370 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
20371 %}
20372 ins_pipe(pipe_slow);
20373 %}
20374
20375 instruct vcmne8S(vecX dst, vecX src1, vecX src2, immI cond)
20376 %{
20377 predicate(n->as_Vector()->length() == 8 &&
20378 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20379 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20380 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20381 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (8S)"
20382 "not $dst, $dst\t" %}
20383 ins_cost(INSN_COST);
20384 ins_encode %{
20385 __ cmeq(as_FloatRegister($dst$$reg), __ T8H,
20386 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20387 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20388 %}
20389 ins_pipe(pipe_slow);
20390 %}
20391
20392 instruct vcmne2I(vecD dst, vecD src1, vecD src2, immI cond)
20393 %{
20394 predicate(n->as_Vector()->length() == 2 &&
20395 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20396 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20397 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20398 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (2I)"
20399 "not $dst, $dst\t" %}
20400 ins_cost(INSN_COST);
20401 ins_encode %{
20402 __ cmeq(as_FloatRegister($dst$$reg), __ T2S,
20403 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20404 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
20405 %}
20406 ins_pipe(pipe_slow);
20407 %}
20408
20409 instruct vcmne4I(vecX dst, vecX src1, vecX src2, immI cond)
20410 %{
20411 predicate(n->as_Vector()->length() == 4 &&
20412 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20413 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20414 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20415 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (4I)"
20416 "not $dst, $dst\t" %}
20417 ins_cost(INSN_COST);
20418 ins_encode %{
20419 __ cmeq(as_FloatRegister($dst$$reg), __ T4S,
20420 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20421 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20422 %}
20423 ins_pipe(pipe_slow);
20424 %}
20425
20426 instruct vcmne2L(vecX dst, vecX src1, vecX src2, immI cond)
20427 %{
20428 predicate(n->as_Vector()->length() == 2 &&
20429 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20430 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
20431 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20432 format %{ "cmeq $dst, $src1, $src2\n\t# vector cmp (2L)"
20433 "not $dst, $dst\t" %}
20434 ins_cost(INSN_COST);
20435 ins_encode %{
20436 __ cmeq(as_FloatRegister($dst$$reg), __ T2D,
20437 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20438 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20439 %}
20440 ins_pipe(pipe_slow);
20441 %}
20442
20443 instruct vcmne2F(vecD dst, vecD src1, vecD src2, immI cond)
20444 %{
20445 predicate(n->as_Vector()->length() == 2 &&
20446 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20447 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20448 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20449 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (2F)"
20450 "not $dst, $dst\t" %}
20451 ins_cost(INSN_COST);
20452 ins_encode %{
20453 __ fcmeq(as_FloatRegister($dst$$reg), __ T2S,
20454 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20455 __ notr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
20456 %}
20457 ins_pipe(pipe_slow);
20458 %}
20459
20460 instruct vcmne4F(vecX dst, vecX src1, vecX src2, immI cond)
20461 %{
20462 predicate(n->as_Vector()->length() == 4 &&
20463 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20464 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20465 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20466 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (4F)"
20467 "not $dst, $dst\t" %}
20468 ins_cost(INSN_COST);
20469 ins_encode %{
20470 __ fcmeq(as_FloatRegister($dst$$reg), __ T4S,
20471 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20472 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20473 %}
20474 ins_pipe(pipe_slow);
20475 %}
20476
20477 instruct vcmne2D(vecX dst, vecX src1, vecX src2, immI cond)
20478 %{
20479 predicate(n->as_Vector()->length() == 2 &&
20480 n->as_VectorMaskCmp()->get_predicate() == BoolTest::ne &&
20481 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20482 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20483 format %{ "fcmeq $dst, $src1, $src2\n\t# vector cmp (2D)"
20484 "not $dst, $dst\t" %}
20485 ins_cost(INSN_COST);
20486 ins_encode %{
20487 __ fcmeq(as_FloatRegister($dst$$reg), __ T2D,
20488 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
20489 __ notr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($dst$$reg));
20490 %}
20491 ins_pipe(pipe_slow);
20492 %}
20493
20494 instruct vcmlt8B(vecD dst, vecD src1, vecD src2, immI cond)
20495 %{
20496 predicate(n->as_Vector()->length() == 8 &&
20497 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20498 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20499 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20500 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (8B)" %}
20501 ins_cost(INSN_COST);
20502 ins_encode %{
20503 __ cmgt(as_FloatRegister($dst$$reg), __ T8B,
20504 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20505 %}
20506 ins_pipe(vdop64);
20507 %}
20508
20509 instruct vcmlt16B(vecX dst, vecX src1, vecX src2, immI cond)
20510 %{
20511 predicate(n->as_Vector()->length() == 16 &&
20512 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20513 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20514 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20515 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (16B)" %}
20516 ins_cost(INSN_COST);
20517 ins_encode %{
20518 __ cmgt(as_FloatRegister($dst$$reg), __ T16B,
20519 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20520 %}
20521 ins_pipe(vdop128);
20522 %}
20523
20524 instruct vcmlt4S(vecD dst, vecD src1, vecD src2, immI cond)
20525 %{
20526 predicate(n->as_Vector()->length() == 4 &&
20527 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20528 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20529 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20530 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (4S)" %}
20531 ins_cost(INSN_COST);
20532 ins_encode %{
20533 __ cmgt(as_FloatRegister($dst$$reg), __ T4H,
20534 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20535 %}
20536 ins_pipe(vdop64);
20537 %}
20538
20539 instruct vcmlt8S(vecX dst, vecX src1, vecX src2, immI cond)
20540 %{
20541 predicate(n->as_Vector()->length() == 8 &&
20542 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20543 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20544 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20545 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (8S)" %}
20546 ins_cost(INSN_COST);
20547 ins_encode %{
20548 __ cmgt(as_FloatRegister($dst$$reg), __ T8H,
20549 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20550 %}
20551 ins_pipe(vdop128);
20552 %}
20553
20554 instruct vcmlt2I(vecD dst, vecD src1, vecD src2, immI cond)
20555 %{
20556 predicate(n->as_Vector()->length() == 2 &&
20557 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20558 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20559 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20560 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (2I)" %}
20561 ins_cost(INSN_COST);
20562 ins_encode %{
20563 __ cmgt(as_FloatRegister($dst$$reg), __ T2S,
20564 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20565 %}
20566 ins_pipe(vdop64);
20567 %}
20568
20569 instruct vcmlt4I(vecX dst, vecX src1, vecX src2, immI cond)
20570 %{
20571 predicate(n->as_Vector()->length() == 4 &&
20572 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20573 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20574 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20575 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (4I)" %}
20576 ins_cost(INSN_COST);
20577 ins_encode %{
20578 __ cmgt(as_FloatRegister($dst$$reg), __ T4S,
20579 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20580 %}
20581 ins_pipe(vdop128);
20582 %}
20583
20584 instruct vcmlt2L(vecX dst, vecX src1, vecX src2, immI cond)
20585 %{
20586 predicate(n->as_Vector()->length() == 2 &&
20587 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20588 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
20589 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20590 format %{ "cmgt $dst, $src2, $src1\t# vector cmp (2L)" %}
20591 ins_cost(INSN_COST);
20592 ins_encode %{
20593 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
20594 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20595 %}
20596 ins_pipe(vdop128);
20597 %}
20598
20599 instruct vcmlt2F(vecD dst, vecD src1, vecD src2, immI cond)
20600 %{
20601 predicate(n->as_Vector()->length() == 2 &&
20602 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20603 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20604 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20605 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (2F)" %}
20606 ins_cost(INSN_COST);
20607 ins_encode %{
20608 __ fcmgt(as_FloatRegister($dst$$reg), __ T2S,
20609 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20610 %}
20611 ins_pipe(vdop64);
20612 %}
20613
20614 instruct vcmlt4F(vecX dst, vecX src1, vecX src2, immI cond)
20615 %{
20616 predicate(n->as_Vector()->length() == 4 &&
20617 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20618 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20619 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20620 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (4F)" %}
20621 ins_cost(INSN_COST);
20622 ins_encode %{
20623 __ fcmgt(as_FloatRegister($dst$$reg), __ T4S,
20624 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20625 %}
20626 ins_pipe(vdop128);
20627 %}
20628
20629 instruct vcmlt2D(vecX dst, vecX src1, vecX src2, immI cond)
20630 %{
20631 predicate(n->as_Vector()->length() == 2 &&
20632 n->as_VectorMaskCmp()->get_predicate() == BoolTest::lt &&
20633 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20634 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20635 format %{ "fcmgt $dst, $src2, $src1\t# vector cmp (2D)" %}
20636 ins_cost(INSN_COST);
20637 ins_encode %{
20638 __ fcmgt(as_FloatRegister($dst$$reg), __ T2D,
20639 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20640 %}
20641 ins_pipe(vdop128);
20642 %}
20643
20644 instruct vcmle8B(vecD dst, vecD src1, vecD src2, immI cond)
20645 %{
20646 predicate(n->as_Vector()->length() == 8 &&
20647 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20648 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20649 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20650 format %{ "cmge $dst, $src2, $src1\t# vector cmp (8B)" %}
20651 ins_cost(INSN_COST);
20652 ins_encode %{
20653 __ cmge(as_FloatRegister($dst$$reg), __ T8B,
20654 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20655 %}
20656 ins_pipe(vdop64);
20657 %}
20658
20659 instruct vcmle16B(vecX dst, vecX src1, vecX src2, immI cond)
20660 %{
20661 predicate(n->as_Vector()->length() == 16 &&
20662 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20663 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20664 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20665 format %{ "cmge $dst, $src2, $src1\t# vector cmp (16B)" %}
20666 ins_cost(INSN_COST);
20667 ins_encode %{
20668 __ cmge(as_FloatRegister($dst$$reg), __ T16B,
20669 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20670 %}
20671 ins_pipe(vdop128);
20672 %}
20673
20674 instruct vcmle4S(vecD dst, vecD src1, vecD src2, immI cond)
20675 %{
20676 predicate(n->as_Vector()->length() == 4 &&
20677 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20678 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20679 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20680 format %{ "cmge $dst, $src2, $src1\t# vector cmp (4S)" %}
20681 ins_cost(INSN_COST);
20682 ins_encode %{
20683 __ cmge(as_FloatRegister($dst$$reg), __ T4H,
20684 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20685 %}
20686 ins_pipe(vdop64);
20687 %}
20688
20689 instruct vcmle8S(vecX dst, vecX src1, vecX src2, immI cond)
20690 %{
20691 predicate(n->as_Vector()->length() == 8 &&
20692 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20693 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20694 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20695 format %{ "cmge $dst, $src2, $src1\t# vector cmp (8S)" %}
20696 ins_cost(INSN_COST);
20697 ins_encode %{
20698 __ cmge(as_FloatRegister($dst$$reg), __ T8H,
20699 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20700 %}
20701 ins_pipe(vdop128);
20702 %}
20703
20704 instruct vcmle2I(vecD dst, vecD src1, vecD src2, immI cond)
20705 %{
20706 predicate(n->as_Vector()->length() == 2 &&
20707 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20708 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20709 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20710 format %{ "cmge $dst, $src2, $src1\t# vector cmp (2I)" %}
20711 ins_cost(INSN_COST);
20712 ins_encode %{
20713 __ cmge(as_FloatRegister($dst$$reg), __ T2S,
20714 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20715 %}
20716 ins_pipe(vdop64);
20717 %}
20718
20719 instruct vcmle4I(vecX dst, vecX src1, vecX src2, immI cond)
20720 %{
20721 predicate(n->as_Vector()->length() == 4 &&
20722 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20723 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_INT);
20724 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20725 format %{ "cmge $dst, $src2, $src1\t# vector cmp (4I)" %}
20726 ins_cost(INSN_COST);
20727 ins_encode %{
20728 __ cmge(as_FloatRegister($dst$$reg), __ T4S,
20729 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20730 %}
20731 ins_pipe(vdop128);
20732 %}
20733
20734 instruct vcmle2L(vecX dst, vecX src1, vecX src2, immI cond)
20735 %{
20736 predicate(n->as_Vector()->length() == 2 &&
20737 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20738 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_LONG);
20739 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20740 format %{ "cmge $dst, $src2, $src1\t# vector cmp (2L)" %}
20741 ins_cost(INSN_COST);
20742 ins_encode %{
20743 __ cmge(as_FloatRegister($dst$$reg), __ T2D,
20744 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20745 %}
20746 ins_pipe(vdop128);
20747 %}
20748
20749 instruct vcmle2F(vecD dst, vecD src1, vecD src2, immI cond)
20750 %{
20751 predicate(n->as_Vector()->length() == 2 &&
20752 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20753 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20754 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20755 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (2F)" %}
20756 ins_cost(INSN_COST);
20757 ins_encode %{
20758 __ fcmge(as_FloatRegister($dst$$reg), __ T2S,
20759 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20760 %}
20761 ins_pipe(vdop64);
20762 %}
20763
20764 instruct vcmle4F(vecX dst, vecX src1, vecX src2, immI cond)
20765 %{
20766 predicate(n->as_Vector()->length() == 4 &&
20767 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20768 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_FLOAT);
20769 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20770 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (4F)" %}
20771 ins_cost(INSN_COST);
20772 ins_encode %{
20773 __ fcmge(as_FloatRegister($dst$$reg), __ T4S,
20774 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20775 %}
20776 ins_pipe(vdop128);
20777 %}
20778
20779 instruct vcmle2D(vecX dst, vecX src1, vecX src2, immI cond)
20780 %{
20781 predicate(n->as_Vector()->length() == 2 &&
20782 n->as_VectorMaskCmp()->get_predicate() == BoolTest::le &&
20783 n->in(1)->in(1)->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE);
20784 match(Set dst (VectorMaskCmp (Binary src1 src2) cond));
20785 format %{ "fcmge $dst, $src2, $src1\t# vector cmp (2D)" %}
20786 ins_cost(INSN_COST);
20787 ins_encode %{
20788 __ fcmge(as_FloatRegister($dst$$reg), __ T2D,
20789 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
20790 %}
20791 ins_pipe(vdop128);
20792 %}
20793
20794 // ------------------------------ Vector mul -----------------------------------
20795
20796 instruct vmul2L(vecX dst, vecX src1, vecX src2, iRegLNoSp tmp1, iRegLNoSp tmp2)
20797 %{
20798 predicate(n->as_Vector()->length() == 2);
20799 match(Set dst (MulVL src1 src2));
20800 ins_cost(INSN_COST);
20801 effect(TEMP tmp1, TEMP tmp2);
20802 format %{ "umov $tmp1, $src1, D, 0\n\t"
20803 "umov $tmp2, $src2, D, 0\n\t"
20804 "mul $tmp2, $tmp2, $tmp1\n\t"
20805 "mov $dst, T2D, 0, $tmp2\t# insert into vector(2L)\n\t"
20806 "umov $tmp1, $src1, D, 1\n\t"
20807 "umov $tmp2, $src2, D, 1\n\t"
20808 "mul $tmp2, $tmp2, $tmp1\n\t"
20809 "mov $dst, T2D, 1, $tmp2\t# insert into vector(2L)\n\t"
20810 %}
20811 ins_encode %{
20812 __ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 0);
20813 __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 0);
20814 __ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
20815 __ mov(as_FloatRegister($dst$$reg), __ T2D, 0, $tmp2$$Register);
20816 __ umov($tmp1$$Register, as_FloatRegister($src1$$reg), __ D, 1);
20817 __ umov($tmp2$$Register, as_FloatRegister($src2$$reg), __ D, 1);
20818 __ mul(as_Register($tmp2$$reg), as_Register($tmp2$$reg), as_Register($tmp1$$reg));
20819 __ mov(as_FloatRegister($dst$$reg), __ T2D, 1, $tmp2$$Register);
20820 %}
20821 ins_pipe(pipe_slow);
20822 %}
20823
20824 // --------------------------------- Vector not --------------------------------
20825
20826 instruct vnot2I(vecD dst, vecD src, immI_M1 m1)
20827 %{
20828 predicate(n->as_Vector()->length_in_bytes() == 8);
20829 match(Set dst (XorV src (ReplicateB m1)));
20830 match(Set dst (XorV src (ReplicateS m1)));
20831 match(Set dst (XorV src (ReplicateI m1)));
20832 ins_cost(INSN_COST);
20833 format %{ "not $dst, $src\t# vector (8B)" %}
20834 ins_encode %{
20835 __ notr(as_FloatRegister($dst$$reg), __ T8B,
20836 as_FloatRegister($src$$reg));
20837 %}
20838 ins_pipe(pipe_class_default);
20839 %}
20840
20841 instruct vnot4I(vecX dst, vecX src, immI_M1 m1)
20842 %{
20843 predicate(n->as_Vector()->length_in_bytes() == 16);
20844 match(Set dst (XorV src (ReplicateB m1)));
20845 match(Set dst (XorV src (ReplicateS m1)));
20846 match(Set dst (XorV src (ReplicateI m1)));
20847 ins_cost(INSN_COST);
20848 format %{ "not $dst, $src\t# vector (16B)" %}
20849 ins_encode %{
20850 __ notr(as_FloatRegister($dst$$reg), __ T16B,
20851 as_FloatRegister($src$$reg));
20852 %}
20853 ins_pipe(pipe_class_default);
20854 %}
20855
20856 instruct vnot2L(vecX dst, vecX src, immL_M1 m1)
20857 %{
20858 predicate(n->as_Vector()->length_in_bytes() == 16);
20859 match(Set dst (XorV src (ReplicateL m1)));
20860 ins_cost(INSN_COST);
20861 format %{ "not $dst, $src\t# vector (16B)" %}
20862 ins_encode %{
20863 __ notr(as_FloatRegister($dst$$reg), __ T16B,
20864 as_FloatRegister($src$$reg));
20865 %}
20866 ins_pipe(pipe_class_default);
20867 %}
20868
20869 // ------------------------------ Vector max/min -------------------------------
20870
20871 instruct vmax8B(vecD dst, vecD src1, vecD src2)
20872 %{
20873 predicate((n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8) &&
20874 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20875 match(Set dst (MaxV src1 src2));
20876 ins_cost(INSN_COST);
20877 format %{ "maxv $dst, $src1, $src2\t# vector (8B)" %}
20878 ins_encode %{
20879 __ maxv(as_FloatRegister($dst$$reg), __ T8B,
20880 as_FloatRegister($src1$$reg),
20881 as_FloatRegister($src2$$reg));
20882 %}
20883 ins_pipe(vdop64);
20884 %}
20885
20886 instruct vmax16B(vecX dst, vecX src1, vecX src2)
20887 %{
20888 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20889 match(Set dst (MaxV src1 src2));
20890 ins_cost(INSN_COST);
20891 format %{ "maxv $dst, $src1, $src2\t# vector (16B)" %}
20892 ins_encode %{
20893 __ maxv(as_FloatRegister($dst$$reg), __ T16B,
20894 as_FloatRegister($src1$$reg),
20895 as_FloatRegister($src2$$reg));
20896 %}
20897 ins_pipe(vdop128);
20898 %}
20899
20900 instruct vmax4S(vecD dst, vecD src1, vecD src2)
20901 %{
20902 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20903 match(Set dst (MaxV src1 src2));
20904 ins_cost(INSN_COST);
20905 format %{ "maxv $dst, $src1, $src2\t# vector (4S)" %}
20906 ins_encode %{
20907 __ maxv(as_FloatRegister($dst$$reg), __ T4H,
20908 as_FloatRegister($src1$$reg),
20909 as_FloatRegister($src2$$reg));
20910 %}
20911 ins_pipe(vdop64);
20912 %}
20913
20914 instruct vmax8S(vecX dst, vecX src1, vecX src2)
20915 %{
20916 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20917 match(Set dst (MaxV src1 src2));
20918 ins_cost(INSN_COST);
20919 format %{ "maxv $dst, $src1, $src2\t# vector (8S)" %}
20920 ins_encode %{
20921 __ maxv(as_FloatRegister($dst$$reg), __ T8H,
20922 as_FloatRegister($src1$$reg),
20923 as_FloatRegister($src2$$reg));
20924 %}
20925 ins_pipe(vdop128);
20926 %}
20927
20928 instruct vmax2I(vecD dst, vecD src1, vecD src2)
20929 %{
20930 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
20931 match(Set dst (MaxV src1 src2));
20932 ins_cost(INSN_COST);
20933 format %{ "maxv $dst, $src1, $src2\t# vector (2I)" %}
20934 ins_encode %{
20935 __ maxv(as_FloatRegister($dst$$reg), __ T2S,
20936 as_FloatRegister($src1$$reg),
20937 as_FloatRegister($src2$$reg));
20938 %}
20939 ins_pipe(vdop64);
20940 %}
20941
20942 instruct vmax4I(vecX dst, vecX src1, vecX src2)
20943 %{
20944 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
20945 match(Set dst (MaxV src1 src2));
20946 ins_cost(INSN_COST);
20947 format %{ "maxv $dst, $src1, $src2\t# vector (4I)" %}
20948 ins_encode %{
20949 __ maxv(as_FloatRegister($dst$$reg), __ T4S,
20950 as_FloatRegister($src1$$reg),
20951 as_FloatRegister($src2$$reg));
20952 %}
20953 ins_pipe(vdop128);
20954 %}
20955
20956 instruct vmin8B(vecD dst, vecD src1, vecD src2)
20957 %{
20958 predicate((n->as_Vector()->length() == 4 || n->as_Vector()->length() == 8) &&
20959 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20960 match(Set dst (MinV src1 src2));
20961 ins_cost(INSN_COST);
20962 format %{ "minv $dst, $src1, $src2\t# vector (8B)" %}
20963 ins_encode %{
20964 __ minv(as_FloatRegister($dst$$reg), __ T8B,
20965 as_FloatRegister($src1$$reg),
20966 as_FloatRegister($src2$$reg));
20967 %}
20968 ins_pipe(vdop64);
20969 %}
20970
20971 instruct vmin16B(vecX dst, vecX src1, vecX src2)
20972 %{
20973 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
20974 match(Set dst (MinV src1 src2));
20975 ins_cost(INSN_COST);
20976 format %{ "minv $dst, $src1, $src2\t# vector (16B)" %}
20977 ins_encode %{
20978 __ minv(as_FloatRegister($dst$$reg), __ T16B,
20979 as_FloatRegister($src1$$reg),
20980 as_FloatRegister($src2$$reg));
20981 %}
20982 ins_pipe(vdop128);
20983 %}
20984
20985 instruct vmin4S(vecD dst, vecD src1, vecD src2)
20986 %{
20987 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
20988 match(Set dst (MinV src1 src2));
20989 ins_cost(INSN_COST);
20990 format %{ "minv $dst, $src1, $src2\t# vector (4S)" %}
20991 ins_encode %{
20992 __ minv(as_FloatRegister($dst$$reg), __ T4H,
20993 as_FloatRegister($src1$$reg),
20994 as_FloatRegister($src2$$reg));
20995 %}
20996 ins_pipe(vdop64);
20997 %}
20998
20999 instruct vmin8S(vecX dst, vecX src1, vecX src2)
21000 %{
21001 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21002 match(Set dst (MinV src1 src2));
21003 ins_cost(INSN_COST);
21004 format %{ "minv $dst, $src1, $src2\t# vector (8S)" %}
21005 ins_encode %{
21006 __ minv(as_FloatRegister($dst$$reg), __ T8H,
21007 as_FloatRegister($src1$$reg),
21008 as_FloatRegister($src2$$reg));
21009 %}
21010 ins_pipe(vdop128);
21011 %}
21012
21013 instruct vmin2I(vecD dst, vecD src1, vecD src2)
21014 %{
21015 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
21016 match(Set dst (MinV src1 src2));
21017 ins_cost(INSN_COST);
21018 format %{ "minv $dst, $src1, $src2\t# vector (2I)" %}
21019 ins_encode %{
21020 __ minv(as_FloatRegister($dst$$reg), __ T2S,
21021 as_FloatRegister($src1$$reg),
21022 as_FloatRegister($src2$$reg));
21023 %}
21024 ins_pipe(vdop64);
21025 %}
21026
21027 instruct vmin4I(vecX dst, vecX src1, vecX src2)
21028 %{
21029 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_INT);
21030 match(Set dst (MinV src1 src2));
21031 ins_cost(INSN_COST);
21032 format %{ "minv $dst, $src1, $src2\t# vector (4I)" %}
21033 ins_encode %{
21034 __ minv(as_FloatRegister($dst$$reg), __ T4S,
21035 as_FloatRegister($src1$$reg),
21036 as_FloatRegister($src2$$reg));
21037 %}
21038 ins_pipe(vdop128);
21039 %}
21040
21041
21042 instruct vmax2L(vecX dst, vecX src1, vecX src2)
21043 %{
21044 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
21045 match(Set dst (MaxV src1 src2));
21046 ins_cost(INSN_COST);
21047 effect(TEMP dst);
21048 format %{ "cmgt $dst, $src1, $src2\t# vector (2L)\n\t"
21049 "bsl $dst, $src1, $src2\t# vector (16B)" %}
21050 ins_encode %{
21051 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
21052 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
21053 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
21054 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
21055 %}
21056 ins_pipe(vdop128);
21057 %}
21058
21059 instruct vmin2L(vecX dst, vecX src1, vecX src2)
21060 %{
21061 predicate(n->as_Vector()->length() == 2 && n->bottom_type()->is_vect()->element_basic_type() == T_LONG);
21062 match(Set dst (MinV src1 src2));
21063 ins_cost(INSN_COST);
21064 effect(TEMP dst);
21065 format %{ "cmgt $dst, $src1, $src2\t# vector (2L)\n\t"
21066 "bsl $dst, $src2, $src1\t# vector (16B)" %}
21067 ins_encode %{
21068 __ cmgt(as_FloatRegister($dst$$reg), __ T2D,
21069 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
21070 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
21071 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
21072 %}
21073 ins_pipe(vdop128);
21074 %}
21075
21076 // --------------------------------- blend (bsl) ----------------------------
21077
21078 instruct vbsl8B(vecD dst, vecD src1, vecD src2)
21079 %{
21080 predicate(n->as_Vector()->length_in_bytes() == 8);
21081 match(Set dst (VectorBlend (Binary src1 src2) dst));
21082 ins_cost(INSN_COST);
21083 format %{ "bsl $dst, $src2, $src1\t# vector (8B)" %}
21084 ins_encode %{
21085 __ bsl(as_FloatRegister($dst$$reg), __ T8B,
21086 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
21087 %}
21088 ins_pipe(vlogical64);
21089 %}
21090
21091 instruct vbsl16B(vecX dst, vecX src1, vecX src2)
21092 %{
21093 predicate(n->as_Vector()->length_in_bytes() == 16);
21094 match(Set dst (VectorBlend (Binary src1 src2) dst));
21095 ins_cost(INSN_COST);
21096 format %{ "bsl $dst, $src2, $src1\t# vector (16B)" %}
21097 ins_encode %{
21098 __ bsl(as_FloatRegister($dst$$reg), __ T16B,
21099 as_FloatRegister($src2$$reg), as_FloatRegister($src1$$reg));
21100 %}
21101 ins_pipe(vlogical128);
21102 %}
21103
21104 // --------------------------------- Load/store Mask ----------------------------
21105
21106 instruct loadmask8B(vecD dst, vecD src )
21107 %{
21108 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21109 match(Set dst (VectorLoadMask src ));
21110 ins_cost(INSN_COST);
21111 format %{ "negr $dst, $src\t# load mask (8B to 8B)" %}
21112 ins_encode %{
21113 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
21114 %}
21115 ins_pipe(pipe_class_default);
21116 %}
21117
21118 instruct loadmask16B(vecX dst, vecX src )
21119 %{
21120 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21121 match(Set dst (VectorLoadMask src ));
21122 ins_cost(INSN_COST);
21123 format %{ "negr $dst, $src\t# load mask (16B to 16B)" %}
21124 ins_encode %{
21125 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
21126 %}
21127 ins_pipe(pipe_class_default);
21128 %}
21129
21130 instruct storemask8B(vecD dst, vecD src , immI_1 size)
21131 %{
21132 predicate(n->as_Vector()->length() == 8);
21133 match(Set dst (VectorStoreMask src size));
21134 ins_cost(INSN_COST);
21135 format %{ "negr $dst, $src\t# store mask (8B to 8B)" %}
21136 ins_encode %{
21137 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg));
21138 %}
21139 ins_pipe(pipe_class_default);
21140 %}
21141
21142 instruct storemask16B(vecX dst, vecX src , immI_1 size)
21143 %{
21144 predicate(n->as_Vector()->length() == 16);
21145 match(Set dst (VectorStoreMask src size));
21146 ins_cost(INSN_COST);
21147 format %{ "negr $dst, $src\t# store mask (16B to 16B)" %}
21148 ins_encode %{
21149 __ negr(as_FloatRegister($dst$$reg), __ T16B, as_FloatRegister($src$$reg));
21150 %}
21151 ins_pipe(pipe_class_default);
21152 %}
21153
21154 instruct loadmask4S(vecD dst, vecD src )
21155 %{
21156 predicate(n->as_Vector()->length() == 4 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21157 match(Set dst (VectorLoadMask src ));
21158 ins_cost(INSN_COST);
21159 format %{ "uxtl $dst, $src\n\t"
21160 "negr $dst, $dst\t# load mask (4B to 4H)" %}
21161 ins_encode %{
21162 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21163 __ negr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($dst$$reg));
21164 %}
21165 ins_pipe(pipe_slow);
21166 %}
21167
21168 instruct loadmask8S(vecX dst, vecD src )
21169 %{
21170 predicate(n->as_Vector()->length() == 8 && n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21171 match(Set dst (VectorLoadMask src ));
21172 ins_cost(INSN_COST);
21173 format %{ "uxtl $dst, $src\n\t"
21174 "negr $dst, $dst\t# load mask (8B to 8H)" %}
21175 ins_encode %{
21176 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21177 __ negr(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($dst$$reg));
21178 %}
21179 ins_pipe(pipe_slow);
21180 %}
21181
21182 instruct storemask4S(vecD dst, vecD src , immI_2 size)
21183 %{
21184 predicate(n->as_Vector()->length() == 4);
21185 match(Set dst (VectorStoreMask src size));
21186 ins_cost(INSN_COST);
21187 format %{ "xtn $dst, $src\n\t"
21188 "negr $dst, $dst\t# store mask (4H to 4B)" %}
21189 ins_encode %{
21190 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
21191 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
21192 %}
21193 ins_pipe(pipe_slow);
21194 %}
21195
21196 instruct storemask8S(vecD dst, vecX src , immI_2 size)
21197 %{
21198 predicate(n->as_Vector()->length() == 8);
21199 match(Set dst (VectorStoreMask src size));
21200 ins_cost(INSN_COST);
21201 format %{ "xtn $dst, $src\n\t"
21202 "negr $dst, $dst\t# store mask (8H to 8B)" %}
21203 ins_encode %{
21204 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($src$$reg), __ T8H);
21205 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
21206 %}
21207 ins_pipe(pipe_slow);
21208 %}
21209
21210 instruct loadmask2I(vecD dst, vecD src )
21211 %{
21212 predicate(n->as_Vector()->length() == 2 &&
21213 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
21214 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
21215 match(Set dst (VectorLoadMask src ));
21216 ins_cost(INSN_COST);
21217 format %{ "uxtl $dst, $src\t# 2B to 2H\n\t"
21218 "uxtl $dst, $dst\t# 2H to 2S\n\t"
21219 "negr $dst, $dst\t# load mask (2B to 2S)" %}
21220 ins_encode %{
21221 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21222 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
21223 __ negr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg));
21224 %}
21225 ins_pipe(pipe_slow);
21226 %}
21227
21228 instruct loadmask4I(vecX dst, vecD src )
21229 %{
21230 predicate(n->as_Vector()->length() == 4 &&
21231 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
21232 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
21233 match(Set dst (VectorLoadMask src ));
21234 ins_cost(INSN_COST);
21235 format %{ "uxtl $dst, $src\t# 4B to 4H\n\t"
21236 "uxtl $dst, $dst\t# 4H to 4S\n\t"
21237 "negr $dst, $dst\t# load mask (4B to 4S)" %}
21238 ins_encode %{
21239 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21240 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
21241 __ negr(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg));
21242 %}
21243 ins_pipe(pipe_slow);
21244 %}
21245
21246 instruct storemask2I(vecD dst, vecD src , immI_4 size)
21247 %{
21248 predicate(n->as_Vector()->length() == 2);
21249 match(Set dst (VectorStoreMask src size));
21250 ins_cost(INSN_COST);
21251 format %{ "xtn $dst, $src\t# 2S to 2H\n\t"
21252 "xtn $dst, $dst\t# 2H to 2B\n\t"
21253 "negr $dst, $dst\t# store mask (2S to 2B)" %}
21254 ins_encode %{
21255 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
21256 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
21257 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
21258 %}
21259 ins_pipe(pipe_slow);
21260 %}
21261
21262 instruct storemask4I(vecD dst, vecX src , immI_4 size)
21263 %{
21264 predicate(n->as_Vector()->length() == 4);
21265 match(Set dst (VectorStoreMask src size));
21266 ins_cost(INSN_COST);
21267 format %{ "xtn $dst, $src\t# 4S to 4H\n\t"
21268 "xtn $dst, $dst\t# 4H to 4B\n\t"
21269 "negr $dst, $dst\t# store mask (4S to 4B)" %}
21270 ins_encode %{
21271 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($src$$reg), __ T4S);
21272 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
21273 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
21274 %}
21275 ins_pipe(pipe_slow);
21276 %}
21277
21278 instruct loadmask2L(vecX dst, vecD src)
21279 %{
21280 predicate(n->as_Vector()->length() == 2 &&
21281 (n->bottom_type()->is_vect()->element_basic_type() == T_LONG ||
21282 n->bottom_type()->is_vect()->element_basic_type() == T_DOUBLE));
21283 match(Set dst (VectorLoadMask src));
21284 ins_cost(INSN_COST);
21285 format %{ "uxtl $dst, $src\t# 2B to 2S\n\t"
21286 "uxtl $dst, $dst\t# 2S to 2I\n\t"
21287 "uxtl $dst, $dst\t# 2I to 2L\n\t"
21288 "neg $dst, $dst\t# load mask (2B to 2L)" %}
21289 ins_encode %{
21290 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21291 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
21292 __ uxtl(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg), __ T2S);
21293 __ negr(as_FloatRegister($dst$$reg), __ T2D, as_FloatRegister($dst$$reg));
21294 %}
21295 ins_pipe(pipe_slow);
21296 %}
21297
21298 instruct storemask2L(vecD dst, vecX src, immI_8 size)
21299 %{
21300 predicate(n->as_Vector()->length() == 2);
21301 match(Set dst (VectorStoreMask src size));
21302 ins_cost(INSN_COST);
21303 format %{ "xtn $dst, $src\t# 2L to 2I\n\t"
21304 "xtn $dst, $dst\t# 2I to 2S\n\t"
21305 "xtn $dst, $dst\t# 2S to 2B\n\t"
21306 "neg $dst, $dst\t# store mask (2L to 2B)" %}
21307 ins_encode %{
21308 __ xtn(as_FloatRegister($dst$$reg), __ T2S, as_FloatRegister($src$$reg), __ T2D);
21309 __ xtn(as_FloatRegister($dst$$reg), __ T4H, as_FloatRegister($dst$$reg), __ T4S);
21310 __ xtn(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg), __ T8H);
21311 __ negr(as_FloatRegister($dst$$reg), __ T8B, as_FloatRegister($dst$$reg));
21312 %}
21313 ins_pipe(pipe_slow);
21314 %}
21315
21316 //-------------------------------- LOAD_IOTA_INDICES----------------------------------
21317
21318 instruct loadcon8B(vecD dst, immI0 src)
21319 %{
21320 predicate((n->as_Vector()->length() == 2 || n->as_Vector()->length() == 4 ||
21321 n->as_Vector()->length() == 8) &&
21322 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21323 match(Set dst (VectorLoadConst src));
21324 ins_cost(INSN_COST);
21325 format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
21326 ins_encode %{
21327 __ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
21328 __ ldrd(as_FloatRegister($dst$$reg), rscratch1);
21329 %}
21330 ins_pipe(pipe_class_memory);
21331 %}
21332
21333 instruct loadcon16B(vecX dst, immI0 src)
21334 %{
21335 predicate(n->as_Vector()->length() == 16 && n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21336 match(Set dst (VectorLoadConst src));
21337 ins_cost(INSN_COST);
21338 format %{ "ldr $dst, CONSTANT_MEMORY\t# load iota indices" %}
21339 ins_encode %{
21340 __ lea(rscratch1, ExternalAddress(StubRoutines::aarch64::vector_iota_indices()));
21341 __ ldrq(as_FloatRegister($dst$$reg), rscratch1);
21342 %}
21343 ins_pipe(pipe_class_memory);
21344 %}
21345
21346 //-------------------------------- LOAD_SHUFFLE ----------------------------------
21347
21348 instruct loadshuffle8B(vecD dst, vecD src)
21349 %{
21350 predicate(n->as_Vector()->length() == 8 &&
21351 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21352 match(Set dst (VectorLoadShuffle src));
21353 ins_cost(INSN_COST);
21354 format %{ "mov $dst, $src\t# get 8B shuffle" %}
21355 ins_encode %{
21356 __ orr(as_FloatRegister($dst$$reg), __ T8B,
21357 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
21358 %}
21359 ins_pipe(pipe_class_default);
21360 %}
21361
21362 instruct loadshuffle16B(vecX dst, vecX src)
21363 %{
21364 predicate(n->as_Vector()->length() == 16 &&
21365 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21366 match(Set dst (VectorLoadShuffle src));
21367 ins_cost(INSN_COST);
21368 format %{ "mov $dst, $src\t# get 16B shuffle" %}
21369 ins_encode %{
21370 __ orr(as_FloatRegister($dst$$reg), __ T16B,
21371 as_FloatRegister($src$$reg), as_FloatRegister($src$$reg));
21372 %}
21373 ins_pipe(pipe_class_default);
21374 %}
21375
21376 instruct loadshuffle4S(vecD dst, vecD src)
21377 %{
21378 predicate(n->as_Vector()->length() == 4 &&
21379 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21380 match(Set dst (VectorLoadShuffle src));
21381 ins_cost(INSN_COST);
21382 format %{ "uxtl $dst, $src\t# 4B to 4H" %}
21383 ins_encode %{
21384 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21385 %}
21386 ins_pipe(pipe_class_default);
21387 %}
21388
21389 instruct loadshuffle8S(vecX dst, vecD src)
21390 %{
21391 predicate(n->as_Vector()->length() == 8 &&
21392 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21393 match(Set dst (VectorLoadShuffle src));
21394 ins_cost(INSN_COST);
21395 format %{ "uxtl $dst, $src\t# 8B to 8H" %}
21396 ins_encode %{
21397 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21398 %}
21399 ins_pipe(pipe_class_default);
21400 %}
21401
21402 instruct loadshuffle4I(vecX dst, vecD src)
21403 %{
21404 predicate(n->as_Vector()->length() == 4 &&
21405 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
21406 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
21407 match(Set dst (VectorLoadShuffle src));
21408 ins_cost(INSN_COST);
21409 format %{ "uxtl $dst, $src\t# 4B to 4H \n\t"
21410 "uxtl $dst, $dst\t# 4H to 4S" %}
21411 ins_encode %{
21412 __ uxtl(as_FloatRegister($dst$$reg), __ T8H, as_FloatRegister($src$$reg), __ T8B);
21413 __ uxtl(as_FloatRegister($dst$$reg), __ T4S, as_FloatRegister($dst$$reg), __ T4H);
21414 %}
21415 ins_pipe(pipe_slow);
21416 %}
21417
21418 //-------------------------------- Rearrange -------------------------------------
21419 // Here is an example that rearranges a NEON vector with 4 ints:
21420 // Rearrange V1 int[a0, a1, a2, a3] to V2 int[a2, a3, a0, a1]
21421 // 1. Get the indices of V1 and store them as Vi byte[0, 1, 2, 3].
21422 // 2. Convert Vi byte[0, 1, 2, 3] to the indices of V2 and also store them as Vi byte[2, 3, 0, 1].
21423 // 3. Unsigned extend Long Vi from byte[2, 3, 0, 1] to int[2, 3, 0, 1].
21424 // 4. Multiply Vi int[2, 3, 0, 1] with constant int[0x04040404, 0x04040404, 0x04040404, 0x04040404]
21425 // and get tbl base Vm int[0x08080808, 0x0c0c0c0c, 0x00000000, 0x04040404].
21426 // 5. Add Vm with constant int[0x03020100, 0x03020100, 0x03020100, 0x03020100]
21427 // and get tbl index Vm int[0x0b0a0908, 0x0f0e0d0c, 0x03020100, 0x07060504]
21428 // 6. Use Vm as index register, and use V1 as table register.
21429 // Then get V2 as the result by tbl NEON instructions.
21430 // Notes:
21431 // Step 1 matches VectorLoadConst.
21432 // Step 3 matches VectorLoadShuffle.
21433 // Step 4, 5, 6 match VectorRearrange.
21434 // For VectorRearrange short/int, the reason why such complex calculation is
21435 // required is because NEON tbl supports bytes table only, so for short/int, we
21436 // need to lookup 2/4 bytes as a group. For VectorRearrange long, we use bsl
21437 // to implement rearrange.
21438
21439 instruct rearrange8B(vecD dst, vecD src, vecD shuffle)
21440 %{
21441 predicate(n->as_Vector()->length() == 8 &&
21442 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21443 match(Set dst (VectorRearrange src shuffle));
21444 ins_cost(INSN_COST);
21445 effect(TEMP_DEF dst);
21446 format %{ "tbl $dst, {$dst}, $shuffle\t# rearrange 8B" %}
21447 ins_encode %{
21448 __ tbl(as_FloatRegister($dst$$reg), __ T8B,
21449 as_FloatRegister($src$$reg), 1, as_FloatRegister($shuffle$$reg));
21450 %}
21451 ins_pipe(pipe_slow);
21452 %}
21453
21454 instruct rearrange16B(vecX dst, vecX src, vecX shuffle)
21455 %{
21456 predicate(n->as_Vector()->length() == 16 &&
21457 n->bottom_type()->is_vect()->element_basic_type() == T_BYTE);
21458 match(Set dst (VectorRearrange src shuffle));
21459 ins_cost(INSN_COST);
21460 effect(TEMP_DEF dst);
21461 format %{ "tbl $dst, {$dst}, $shuffle\t# rearrange 16B" %}
21462 ins_encode %{
21463 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
21464 as_FloatRegister($src$$reg), 1, as_FloatRegister($shuffle$$reg));
21465 %}
21466 ins_pipe(pipe_slow);
21467 %}
21468
21469 instruct rearrange4S(vecD dst, vecD src, vecD shuffle, vecD tmp0, vecD tmp1)
21470 %{
21471 predicate(n->as_Vector()->length() == 4 &&
21472 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21473 match(Set dst (VectorRearrange src shuffle));
21474 ins_cost(INSN_COST);
21475 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
21476 format %{ "mov $tmp0, CONSTANT\t# constant 0x0202020202020202\n\t"
21477 "mov $tmp1, CONSTANT\t# constant 0x0100010001000100\n\t"
21478 "mulv $dst, T4H, $shuffle, $tmp0\n\t"
21479 "addv $dst, T8B, $dst, $tmp1\n\t"
21480 "tbl $dst, {$src}, $dst\t# rearrange 4S" %}
21481 ins_encode %{
21482 __ mov(as_FloatRegister($tmp0$$reg), __ T8B, 0x02);
21483 __ mov(as_FloatRegister($tmp1$$reg), __ T4H, 0x0100);
21484 __ mulv(as_FloatRegister($dst$$reg), __ T4H,
21485 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
21486 __ addv(as_FloatRegister($dst$$reg), __ T8B,
21487 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
21488 __ tbl(as_FloatRegister($dst$$reg), __ T8B,
21489 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
21490 %}
21491 ins_pipe(pipe_slow);
21492 %}
21493
21494 instruct rearrange8S(vecX dst, vecX src, vecX shuffle, vecX tmp0, vecX tmp1)
21495 %{
21496 predicate(n->as_Vector()->length() == 8 &&
21497 n->bottom_type()->is_vect()->element_basic_type() == T_SHORT);
21498 match(Set dst (VectorRearrange src shuffle));
21499 ins_cost(INSN_COST);
21500 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
21501 format %{ "mov $tmp0, CONSTANT\t# constant 0x0202020202020202\n\t"
21502 "mov $tmp1, CONSTANT\t# constant 0x0100010001000100\n\t"
21503 "mulv $dst, T8H, $shuffle, $tmp0\n\t"
21504 "addv $dst, T16B, $dst, $tmp1\n\t"
21505 "tbl $dst, {$src}, $dst\t# rearrange 8S" %}
21506 ins_encode %{
21507 __ mov(as_FloatRegister($tmp0$$reg), __ T16B, 0x02);
21508 __ mov(as_FloatRegister($tmp1$$reg), __ T8H, 0x0100);
21509 __ mulv(as_FloatRegister($dst$$reg), __ T8H,
21510 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
21511 __ addv(as_FloatRegister($dst$$reg), __ T16B,
21512 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
21513 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
21514 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
21515 %}
21516 ins_pipe(pipe_slow);
21517 %}
21518
21519 instruct rearrange4I(vecX dst, vecX src, vecX shuffle, vecX tmp0, vecX tmp1)
21520 %{
21521 predicate(n->as_Vector()->length() == 4 &&
21522 (n->bottom_type()->is_vect()->element_basic_type() == T_INT ||
21523 n->bottom_type()->is_vect()->element_basic_type() == T_FLOAT));
21524 match(Set dst (VectorRearrange src shuffle));
21525 ins_cost(INSN_COST);
21526 effect(TEMP_DEF dst, TEMP tmp0, TEMP tmp1);
21527 format %{ "mov $tmp0, CONSTANT\t# constant 0x0404040404040404\n\t"
21528 "mov $tmp1, CONSTANT\t# constant 0x0302010003020100\n\t"
21529 "mulv $dst, T8H, $shuffle, $tmp0\n\t"
21530 "addv $dst, T16B, $dst, $tmp1\n\t"
21531 "tbl $dst, {$src}, $dst\t# rearrange 4I" %}
21532 ins_encode %{
21533 __ mov(as_FloatRegister($tmp0$$reg), __ T16B, 0x04);
21534 __ mov(as_FloatRegister($tmp1$$reg), __ T4S, 0x03020100);
21535 __ mulv(as_FloatRegister($dst$$reg), __ T4S,
21536 as_FloatRegister($shuffle$$reg), as_FloatRegister($tmp0$$reg));
21537 __ addv(as_FloatRegister($dst$$reg), __ T16B,
21538 as_FloatRegister($dst$$reg), as_FloatRegister($tmp1$$reg));
21539 __ tbl(as_FloatRegister($dst$$reg), __ T16B,
21540 as_FloatRegister($src$$reg), 1, as_FloatRegister($dst$$reg));
21541 %}
21542 ins_pipe(pipe_slow);
21543 %}
21544
21545 //-------------------------------- Anytrue/alltrue -----------------------------
21546
21547 instruct anytrue_in_mask8B(iRegINoSp dst, vecD src1, vecD src2, vecD tmp, rFlagsReg cr)
21548 %{
21549 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
21550 match(Set dst (VectorTest src1 src2 ));
21551 ins_cost(INSN_COST);
21552 effect(TEMP tmp, KILL cr);
21553 format %{ "addv $tmp, T8B, $src1\t# src1 and src2 are the same\n\t"
21554 "umov $dst, $tmp, B, 0\n\t"
21555 "cmp $dst, 0\n\t"
21556 "cset $dst" %}
21557 ins_encode %{
21558 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($src1$$reg));
21559 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
21560 __ cmpw($dst$$Register, zr);
21561 __ csetw($dst$$Register, Assembler::NE);
21562 %}
21563 ins_pipe(pipe_slow);
21564 %}
21565
21566 instruct anytrue_in_mask16B(iRegINoSp dst, vecX src1, vecX src2, vecX tmp, rFlagsReg cr)
21567 %{
21568 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::ne);
21569 match(Set dst (VectorTest src1 src2 ));
21570 ins_cost(INSN_COST);
21571 effect(TEMP tmp, KILL cr);
21572 format %{ "addv $tmp, T16B, $src1\t# src1 and src2 are the same\n\t"
21573 "umov $dst, $tmp, B, 0\n\t"
21574 "cmp $dst, 0\n\t"
21575 "cset $dst" %}
21576 ins_encode %{
21577 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($src1$$reg));
21578 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
21579 __ cmpw($dst$$Register, zr);
21580 __ csetw($dst$$Register, Assembler::NE);
21581 %}
21582 ins_pipe(pipe_slow);
21583 %}
21584
21585 instruct alltrue_in_mask8B(iRegINoSp dst, vecD src1, vecD src2, vecD tmp, rFlagsReg cr)
21586 %{
21587 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
21588 match(Set dst (VectorTest src1 src2 ));
21589 ins_cost(INSN_COST);
21590 effect(TEMP tmp, KILL cr);
21591 format %{ "andr $tmp, T8B, $src1, $src2\t# src2 is maskAllTrue\n\t"
21592 "notr $tmp, T8B, $tmp\n\t"
21593 "addv $tmp, T8B, $tmp\n\t"
21594 "umov $dst, $tmp, B, 0\n\t"
21595 "cmp $dst, 0\n\t"
21596 "cset $dst" %}
21597 ins_encode %{
21598 __ andr(as_FloatRegister($tmp$$reg), __ T8B,
21599 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
21600 __ notr(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($tmp$$reg));
21601 __ addv(as_FloatRegister($tmp$$reg), __ T8B, as_FloatRegister($tmp$$reg));
21602 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
21603 __ cmpw($dst$$Register, zr);
21604 __ csetw($dst$$Register, Assembler::EQ);
21605 %}
21606 ins_pipe(pipe_slow);
21607 %}
21608
21609 instruct alltrue_in_mask16B(iRegINoSp dst, vecX src1, vecX src2, vecX tmp, rFlagsReg cr)
21610 %{
21611 predicate(static_cast<const VectorTestNode*>(n)->get_predicate() == BoolTest::overflow);
21612 match(Set dst (VectorTest src1 src2 ));
21613 ins_cost(INSN_COST);
21614 effect(TEMP tmp, KILL cr);
21615 format %{ "andr $tmp, T16B, $src1, $src2\t# src2 is maskAllTrue\n\t"
21616 "notr $tmp, T16B, $tmp\n\t"
21617 "addv $tmp, T16B, $tmp\n\t"
21618 "umov $dst, $tmp, B, 0\n\t"
21619 "cmp $dst, 0\n\t"
21620 "cset $dst" %}
21621 ins_encode %{
21622 __ andr(as_FloatRegister($tmp$$reg), __ T16B,
21623 as_FloatRegister($src1$$reg), as_FloatRegister($src2$$reg));
21624 __ notr(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($tmp$$reg));
21625 __ addv(as_FloatRegister($tmp$$reg), __ T16B, as_FloatRegister($tmp$$reg));
21626 __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
21627 __ cmpw($dst$$Register, zr);
21628 __ csetw($dst$$Register, Assembler::EQ);
21629 %}
21630 ins_pipe(pipe_slow);
21631 %}
21632 // END This section of the file is automatically generated. Do not edit --------------
21633
21634 //----------PEEPHOLE RULES-----------------------------------------------------
21635 // These must follow all instruction definitions as they use the names
21636 // defined in the instructions definitions.
21637 //
21638 // peepmatch ( root_instr_name [preceding_instruction]* );
21639 //
21640 // peepconstraint %{
21641 // (instruction_number.operand_name relational_op instruction_number.operand_name
21642 // [, ...] );
21643 // // instruction numbers are zero-based using left to right order in peepmatch
21644 //
21645 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
21646 // // provide an instruction_number.operand_name for each operand that appears
21647 // // in the replacement instruction's match rule
21648 //
21649 // ---------VM FLAGS---------------------------------------------------------
21650 //
21651 // All peephole optimizations can be turned off using -XX:-OptoPeephole
21652 //
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