1 /*
2 * Copyright (c) 2003, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #ifndef _WINDOWS
27 #include "alloca.h"
28 #endif
29 #include "asm/macroAssembler.hpp"
30 #include "asm/macroAssembler.inline.hpp"
31 #include "code/debugInfoRec.hpp"
32 #include "code/icBuffer.hpp"
33 #include "code/nativeInst.hpp"
34 #include "code/vtableStubs.hpp"
35 #include "gc/shared/gcLocker.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "logging/log.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "oops/compiledICHolder.hpp"
40 #include "runtime/safepointMechanism.hpp"
41 #include "runtime/sharedRuntime.hpp"
42 #include "runtime/vframeArray.hpp"
43 #include "utilities/align.hpp"
44 #include "utilities/formatBuffer.hpp"
45 #include "vm_version_x86.hpp"
46 #include "vmreg_x86.inline.hpp"
47 #ifdef COMPILER1
48 #include "c1/c1_Runtime1.hpp"
49 #endif
50 #ifdef COMPILER2
51 #include "opto/runtime.hpp"
52 #endif
53 #if INCLUDE_JVMCI
54 #include "jvmci/jvmciJavaClasses.hpp"
55 #endif
56
57 #define __ masm->
58
59 const int StackAlignmentInSlots = StackAlignmentInBytes / VMRegImpl::stack_slot_size;
60
61 class SimpleRuntimeFrame {
62
63 public:
64
65 // Most of the runtime stubs have this simple frame layout.
66 // This class exists to make the layout shared in one place.
67 // Offsets are for compiler stack slots, which are jints.
68 enum layout {
69 // The frame sender code expects that rbp will be in the "natural" place and
70 // will override any oopMap setting for it. We must therefore force the layout
71 // so that it agrees with the frame sender code.
72 rbp_off = frame::arg_reg_save_area_bytes/BytesPerInt,
73 rbp_off2,
74 return_off, return_off2,
75 framesize
76 };
77 };
78
79 class RegisterSaver {
80 // Capture info about frame layout. Layout offsets are in jint
81 // units because compiler frame slots are jints.
82 #define XSAVE_AREA_BEGIN 160
83 #define XSAVE_AREA_YMM_BEGIN 576
84 #define XSAVE_AREA_ZMM_BEGIN 1152
85 #define XSAVE_AREA_UPPERBANK 1664
86 #define DEF_XMM_OFFS(regnum) xmm ## regnum ## _off = xmm_off + (regnum)*16/BytesPerInt, xmm ## regnum ## H_off
87 #define DEF_YMM_OFFS(regnum) ymm ## regnum ## _off = ymm_off + (regnum)*16/BytesPerInt, ymm ## regnum ## H_off
88 #define DEF_ZMM_OFFS(regnum) zmm ## regnum ## _off = zmm_off + (regnum-16)*64/BytesPerInt, zmm ## regnum ## H_off
89 enum layout {
90 fpu_state_off = frame::arg_reg_save_area_bytes/BytesPerInt, // fxsave save area
91 xmm_off = fpu_state_off + XSAVE_AREA_BEGIN/BytesPerInt, // offset in fxsave save area
92 DEF_XMM_OFFS(0),
93 DEF_XMM_OFFS(1),
94 // 2..15 are implied in range usage
95 ymm_off = xmm_off + (XSAVE_AREA_YMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
96 DEF_YMM_OFFS(0),
97 DEF_YMM_OFFS(1),
98 // 2..15 are implied in range usage
99 zmm_high = xmm_off + (XSAVE_AREA_ZMM_BEGIN - XSAVE_AREA_BEGIN)/BytesPerInt,
100 zmm_off = xmm_off + (XSAVE_AREA_UPPERBANK - XSAVE_AREA_BEGIN)/BytesPerInt,
101 DEF_ZMM_OFFS(16),
102 DEF_ZMM_OFFS(17),
103 // 18..31 are implied in range usage
104 fpu_state_end = fpu_state_off + ((FPUStateSizeInWords-1)*wordSize / BytesPerInt),
105 fpu_stateH_end,
106 r15_off, r15H_off,
107 r14_off, r14H_off,
108 r13_off, r13H_off,
109 r12_off, r12H_off,
110 r11_off, r11H_off,
111 r10_off, r10H_off,
112 r9_off, r9H_off,
113 r8_off, r8H_off,
114 rdi_off, rdiH_off,
115 rsi_off, rsiH_off,
116 ignore_off, ignoreH_off, // extra copy of rbp
117 rsp_off, rspH_off,
118 rbx_off, rbxH_off,
119 rdx_off, rdxH_off,
120 rcx_off, rcxH_off,
121 rax_off, raxH_off,
122 // 16-byte stack alignment fill word: see MacroAssembler::push/pop_IU_state
123 align_off, alignH_off,
124 flags_off, flagsH_off,
125 // The frame sender code expects that rbp will be in the "natural" place and
126 // will override any oopMap setting for it. We must therefore force the layout
127 // so that it agrees with the frame sender code.
128 rbp_off, rbpH_off, // copy of rbp we will restore
129 return_off, returnH_off, // slot for return address
130 reg_save_size // size in compiler stack slots
131 };
132
133 public:
134 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors = false);
135 static void restore_live_registers(MacroAssembler* masm, bool restore_vectors = false);
136
137 // Offsets into the register save area
138 // Used by deoptimization when it is managing result register
139 // values on its own
140
141 static int rax_offset_in_bytes(void) { return BytesPerInt * rax_off; }
142 static int rdx_offset_in_bytes(void) { return BytesPerInt * rdx_off; }
143 static int rbx_offset_in_bytes(void) { return BytesPerInt * rbx_off; }
144 static int xmm0_offset_in_bytes(void) { return BytesPerInt * xmm0_off; }
145 static int return_offset_in_bytes(void) { return BytesPerInt * return_off; }
146
147 // During deoptimization only the result registers need to be restored,
148 // all the other values have already been extracted.
149 static void restore_result_registers(MacroAssembler* masm);
150 };
151
152 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words, bool save_vectors) {
153 int off = 0;
154 int num_xmm_regs = XMMRegisterImpl::number_of_registers;
155 if (UseAVX < 3) {
156 num_xmm_regs = num_xmm_regs/2;
157 }
158 #if COMPILER2_OR_JVMCI
159 if (save_vectors) {
160 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
161 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
162 }
163 #else
164 assert(!save_vectors, "vectors are generated only by C2 and JVMCI");
165 #endif
166
167 // Always make the frame size 16-byte aligned, both vector and non vector stacks are always allocated
168 int frame_size_in_bytes = align_up(reg_save_size*BytesPerInt, num_xmm_regs);
169 // OopMap frame size is in compiler stack slots (jint's) not bytes or words
170 int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
171 // CodeBlob frame size is in words.
172 int frame_size_in_words = frame_size_in_bytes / wordSize;
173 *total_frame_words = frame_size_in_words;
174
175 // Save registers, fpu state, and flags.
176 // We assume caller has already pushed the return address onto the
177 // stack, so rsp is 8-byte aligned here.
178 // We push rpb twice in this sequence because we want the real rbp
179 // to be under the return like a normal enter.
180
181 __ enter(); // rsp becomes 16-byte aligned here
182 __ push_CPU_state(); // Push a multiple of 16 bytes
183
184 // push cpu state handles this on EVEX enabled targets
185 if (save_vectors) {
186 // Save upper half of YMM registers(0..15)
187 int base_addr = XSAVE_AREA_YMM_BEGIN;
188 for (int n = 0; n < 16; n++) {
189 __ vextractf128_high(Address(rsp, base_addr+n*16), as_XMMRegister(n));
190 }
191 if (VM_Version::supports_evex()) {
192 // Save upper half of ZMM registers(0..15)
193 base_addr = XSAVE_AREA_ZMM_BEGIN;
194 for (int n = 0; n < 16; n++) {
195 __ vextractf64x4_high(Address(rsp, base_addr+n*32), as_XMMRegister(n));
196 }
197 // Save full ZMM registers(16..num_xmm_regs)
198 base_addr = XSAVE_AREA_UPPERBANK;
199 off = 0;
200 int vector_len = Assembler::AVX_512bit;
201 for (int n = 16; n < num_xmm_regs; n++) {
202 __ evmovdqul(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n), vector_len);
203 }
204 }
205 } else {
206 if (VM_Version::supports_evex()) {
207 // Save upper bank of ZMM registers(16..31) for double/float usage
208 int base_addr = XSAVE_AREA_UPPERBANK;
209 off = 0;
210 for (int n = 16; n < num_xmm_regs; n++) {
211 __ movsd(Address(rsp, base_addr+(off++*64)), as_XMMRegister(n));
212 }
213 }
214 }
215 __ vzeroupper();
216 if (frame::arg_reg_save_area_bytes != 0) {
217 // Allocate argument register save area
218 __ subptr(rsp, frame::arg_reg_save_area_bytes);
219 }
220
221 // Set an oopmap for the call site. This oopmap will map all
222 // oop-registers and debug-info registers as callee-saved. This
223 // will allow deoptimization at this safepoint to find all possible
224 // debug-info recordings, as well as let GC find all oops.
225
226 OopMapSet *oop_maps = new OopMapSet();
227 OopMap* map = new OopMap(frame_size_in_slots, 0);
228
229 #define STACK_OFFSET(x) VMRegImpl::stack2reg((x))
230
231 map->set_callee_saved(STACK_OFFSET( rax_off ), rax->as_VMReg());
232 map->set_callee_saved(STACK_OFFSET( rcx_off ), rcx->as_VMReg());
233 map->set_callee_saved(STACK_OFFSET( rdx_off ), rdx->as_VMReg());
234 map->set_callee_saved(STACK_OFFSET( rbx_off ), rbx->as_VMReg());
235 // rbp location is known implicitly by the frame sender code, needs no oopmap
236 // and the location where rbp was saved by is ignored
237 map->set_callee_saved(STACK_OFFSET( rsi_off ), rsi->as_VMReg());
238 map->set_callee_saved(STACK_OFFSET( rdi_off ), rdi->as_VMReg());
239 map->set_callee_saved(STACK_OFFSET( r8_off ), r8->as_VMReg());
240 map->set_callee_saved(STACK_OFFSET( r9_off ), r9->as_VMReg());
241 map->set_callee_saved(STACK_OFFSET( r10_off ), r10->as_VMReg());
242 map->set_callee_saved(STACK_OFFSET( r11_off ), r11->as_VMReg());
243 map->set_callee_saved(STACK_OFFSET( r12_off ), r12->as_VMReg());
244 map->set_callee_saved(STACK_OFFSET( r13_off ), r13->as_VMReg());
245 map->set_callee_saved(STACK_OFFSET( r14_off ), r14->as_VMReg());
246 map->set_callee_saved(STACK_OFFSET( r15_off ), r15->as_VMReg());
247 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
248 // on EVEX enabled targets, we get it included in the xsave area
249 off = xmm0_off;
250 int delta = xmm1_off - off;
251 for (int n = 0; n < 16; n++) {
252 XMMRegister xmm_name = as_XMMRegister(n);
253 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg());
254 off += delta;
255 }
256 if(UseAVX > 2) {
257 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
258 off = zmm16_off;
259 delta = zmm17_off - off;
260 for (int n = 16; n < num_xmm_regs; n++) {
261 XMMRegister zmm_name = as_XMMRegister(n);
262 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg());
263 off += delta;
264 }
265 }
266
267 #if COMPILER2_OR_JVMCI
268 if (save_vectors) {
269 off = ymm0_off;
270 int delta = ymm1_off - off;
271 for (int n = 0; n < 16; n++) {
272 XMMRegister ymm_name = as_XMMRegister(n);
273 map->set_callee_saved(STACK_OFFSET(off), ymm_name->as_VMReg()->next(4));
274 off += delta;
275 }
276 }
277 #endif // COMPILER2_OR_JVMCI
278
279 // %%% These should all be a waste but we'll keep things as they were for now
280 if (true) {
281 map->set_callee_saved(STACK_OFFSET( raxH_off ), rax->as_VMReg()->next());
282 map->set_callee_saved(STACK_OFFSET( rcxH_off ), rcx->as_VMReg()->next());
283 map->set_callee_saved(STACK_OFFSET( rdxH_off ), rdx->as_VMReg()->next());
284 map->set_callee_saved(STACK_OFFSET( rbxH_off ), rbx->as_VMReg()->next());
285 // rbp location is known implicitly by the frame sender code, needs no oopmap
286 map->set_callee_saved(STACK_OFFSET( rsiH_off ), rsi->as_VMReg()->next());
287 map->set_callee_saved(STACK_OFFSET( rdiH_off ), rdi->as_VMReg()->next());
288 map->set_callee_saved(STACK_OFFSET( r8H_off ), r8->as_VMReg()->next());
289 map->set_callee_saved(STACK_OFFSET( r9H_off ), r9->as_VMReg()->next());
290 map->set_callee_saved(STACK_OFFSET( r10H_off ), r10->as_VMReg()->next());
291 map->set_callee_saved(STACK_OFFSET( r11H_off ), r11->as_VMReg()->next());
292 map->set_callee_saved(STACK_OFFSET( r12H_off ), r12->as_VMReg()->next());
293 map->set_callee_saved(STACK_OFFSET( r13H_off ), r13->as_VMReg()->next());
294 map->set_callee_saved(STACK_OFFSET( r14H_off ), r14->as_VMReg()->next());
295 map->set_callee_saved(STACK_OFFSET( r15H_off ), r15->as_VMReg()->next());
296 // For both AVX and EVEX we will use the legacy FXSAVE area for xmm0..xmm15,
297 // on EVEX enabled targets, we get it included in the xsave area
298 off = xmm0H_off;
299 delta = xmm1H_off - off;
300 for (int n = 0; n < 16; n++) {
301 XMMRegister xmm_name = as_XMMRegister(n);
302 map->set_callee_saved(STACK_OFFSET(off), xmm_name->as_VMReg()->next());
303 off += delta;
304 }
305 if (UseAVX > 2) {
306 // Obtain xmm16..xmm31 from the XSAVE area on EVEX enabled targets
307 off = zmm16H_off;
308 delta = zmm17H_off - off;
309 for (int n = 16; n < num_xmm_regs; n++) {
310 XMMRegister zmm_name = as_XMMRegister(n);
311 map->set_callee_saved(STACK_OFFSET(off), zmm_name->as_VMReg()->next());
312 off += delta;
313 }
314 }
315 }
316
317 return map;
318 }
319
320 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_vectors) {
321 int num_xmm_regs = XMMRegisterImpl::number_of_registers;
322 if (UseAVX < 3) {
323 num_xmm_regs = num_xmm_regs/2;
324 }
325 if (frame::arg_reg_save_area_bytes != 0) {
326 // Pop arg register save area
327 __ addptr(rsp, frame::arg_reg_save_area_bytes);
328 }
329
330 #if COMPILER2_OR_JVMCI
331 if (restore_vectors) {
332 assert(UseAVX > 0, "Vectors larger than 16 byte long are supported only with AVX");
333 assert(MaxVectorSize <= 64, "Only up to 64 byte long vectors are supported");
334 }
335 #else
336 assert(!restore_vectors, "vectors are generated only by C2");
337 #endif
338
339 __ vzeroupper();
340
341 // On EVEX enabled targets everything is handled in pop fpu state
342 if (restore_vectors) {
343 // Restore upper half of YMM registers (0..15)
344 int base_addr = XSAVE_AREA_YMM_BEGIN;
345 for (int n = 0; n < 16; n++) {
346 __ vinsertf128_high(as_XMMRegister(n), Address(rsp, base_addr+n*16));
347 }
348 if (VM_Version::supports_evex()) {
349 // Restore upper half of ZMM registers (0..15)
350 base_addr = XSAVE_AREA_ZMM_BEGIN;
351 for (int n = 0; n < 16; n++) {
352 __ vinsertf64x4_high(as_XMMRegister(n), Address(rsp, base_addr+n*32));
353 }
354 // Restore full ZMM registers(16..num_xmm_regs)
355 base_addr = XSAVE_AREA_UPPERBANK;
356 int vector_len = Assembler::AVX_512bit;
357 int off = 0;
358 for (int n = 16; n < num_xmm_regs; n++) {
359 __ evmovdqul(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)), vector_len);
360 }
361 }
362 } else {
363 if (VM_Version::supports_evex()) {
364 // Restore upper bank of ZMM registers(16..31) for double/float usage
365 int base_addr = XSAVE_AREA_UPPERBANK;
366 int off = 0;
367 for (int n = 16; n < num_xmm_regs; n++) {
368 __ movsd(as_XMMRegister(n), Address(rsp, base_addr+(off++*64)));
369 }
370 }
371 }
372
373 // Recover CPU state
374 __ pop_CPU_state();
375 // Get the rbp described implicitly by the calling convention (no oopMap)
376 __ pop(rbp);
377 }
378
379 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
380
381 // Just restore result register. Only used by deoptimization. By
382 // now any callee save register that needs to be restored to a c2
383 // caller of the deoptee has been extracted into the vframeArray
384 // and will be stuffed into the c2i adapter we create for later
385 // restoration so only result registers need to be restored here.
386
387 // Restore fp result register
388 __ movdbl(xmm0, Address(rsp, xmm0_offset_in_bytes()));
389 // Restore integer result register
390 __ movptr(rax, Address(rsp, rax_offset_in_bytes()));
391 __ movptr(rdx, Address(rsp, rdx_offset_in_bytes()));
392
393 // Pop all of the register save are off the stack except the return address
394 __ addptr(rsp, return_offset_in_bytes());
395 }
396
397 // Is vector's size (in bytes) bigger than a size saved by default?
398 // 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
399 bool SharedRuntime::is_wide_vector(int size) {
400 return size > 16;
401 }
402
403 size_t SharedRuntime::trampoline_size() {
404 return 16;
405 }
406
407 void SharedRuntime::generate_trampoline(MacroAssembler *masm, address destination) {
408 __ jump(RuntimeAddress(destination));
409 }
410
411 // The java_calling_convention describes stack locations as ideal slots on
412 // a frame with no abi restrictions. Since we must observe abi restrictions
413 // (like the placement of the register window) the slots must be biased by
414 // the following value.
415 static int reg2offset_in(VMReg r) {
416 // Account for saved rbp and return address
417 // This should really be in_preserve_stack_slots
418 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
419 }
420
421 static int reg2offset_out(VMReg r) {
422 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
423 }
424
425 // ---------------------------------------------------------------------------
426 // Read the array of BasicTypes from a signature, and compute where the
427 // arguments should go. Values in the VMRegPair regs array refer to 4-byte
428 // quantities. Values less than VMRegImpl::stack0 are registers, those above
429 // refer to 4-byte stack slots. All stack slots are based off of the stack pointer
430 // as framesizes are fixed.
431 // VMRegImpl::stack0 refers to the first slot 0(sp).
432 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
433 // up to RegisterImpl::number_of_registers) are the 64-bit
434 // integer registers.
435
436 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
437 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
438 // units regardless of build. Of course for i486 there is no 64 bit build
439
440 // The Java calling convention is a "shifted" version of the C ABI.
441 // By skipping the first C ABI register we can call non-static jni methods
442 // with small numbers of arguments without having to shuffle the arguments
443 // at all. Since we control the java ABI we ought to at least get some
444 // advantage out of it.
445
446 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
447 VMRegPair *regs,
448 int total_args_passed,
449 int is_outgoing) {
450
451 // Create the mapping between argument positions and
452 // registers.
453 static const Register INT_ArgReg[Argument::n_int_register_parameters_j] = {
454 j_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4, j_rarg5
455 };
456 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_j] = {
457 j_farg0, j_farg1, j_farg2, j_farg3,
458 j_farg4, j_farg5, j_farg6, j_farg7
459 };
460
461
462 uint int_args = 0;
463 uint fp_args = 0;
464 uint stk_args = 0; // inc by 2 each time
465
466 for (int i = 0; i < total_args_passed; i++) {
467 switch (sig_bt[i]) {
468 case T_BOOLEAN:
469 case T_CHAR:
470 case T_BYTE:
471 case T_SHORT:
472 case T_INT:
473 if (int_args < Argument::n_int_register_parameters_j) {
474 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
475 } else {
476 regs[i].set1(VMRegImpl::stack2reg(stk_args));
477 stk_args += 2;
478 }
479 break;
480 case T_VOID:
481 // halves of T_LONG or T_DOUBLE
482 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
483 regs[i].set_bad();
484 break;
485 case T_LONG:
486 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
487 // fall through
488 case T_OBJECT:
489 case T_ARRAY:
490 case T_ADDRESS:
491 if (int_args < Argument::n_int_register_parameters_j) {
492 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
493 } else {
494 regs[i].set2(VMRegImpl::stack2reg(stk_args));
495 stk_args += 2;
496 }
497 break;
498 case T_FLOAT:
499 if (fp_args < Argument::n_float_register_parameters_j) {
500 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
501 } else {
502 regs[i].set1(VMRegImpl::stack2reg(stk_args));
503 stk_args += 2;
504 }
505 break;
506 case T_DOUBLE:
507 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
508 if (fp_args < Argument::n_float_register_parameters_j) {
509 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
510 } else {
511 regs[i].set2(VMRegImpl::stack2reg(stk_args));
512 stk_args += 2;
513 }
514 break;
515 default:
516 ShouldNotReachHere();
517 break;
518 }
519 }
520
521 return align_up(stk_args, 2);
522 }
523
524 // Patch the callers callsite with entry to compiled code if it exists.
525 static void patch_callers_callsite(MacroAssembler *masm) {
526 Label L;
527 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
528 __ jcc(Assembler::equal, L);
529
530 // Save the current stack pointer
531 __ mov(r13, rsp);
532 // Schedule the branch target address early.
533 // Call into the VM to patch the caller, then jump to compiled callee
534 // rax isn't live so capture return address while we easily can
535 __ movptr(rax, Address(rsp, 0));
536
537 // align stack so push_CPU_state doesn't fault
538 __ andptr(rsp, -(StackAlignmentInBytes));
539 __ push_CPU_state();
540 __ vzeroupper();
541 // VM needs caller's callsite
542 // VM needs target method
543 // This needs to be a long call since we will relocate this adapter to
544 // the codeBuffer and it may not reach
545
546 // Allocate argument register save area
547 if (frame::arg_reg_save_area_bytes != 0) {
548 __ subptr(rsp, frame::arg_reg_save_area_bytes);
549 }
550 __ mov(c_rarg0, rbx);
551 __ mov(c_rarg1, rax);
552 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
553
554 // De-allocate argument register save area
555 if (frame::arg_reg_save_area_bytes != 0) {
556 __ addptr(rsp, frame::arg_reg_save_area_bytes);
557 }
558
559 __ vzeroupper();
560 __ pop_CPU_state();
561 // restore sp
562 __ mov(rsp, r13);
563 __ bind(L);
564 }
565
566
567 static void gen_c2i_adapter(MacroAssembler *masm,
568 int total_args_passed,
569 int comp_args_on_stack,
570 const BasicType *sig_bt,
571 const VMRegPair *regs,
572 Label& skip_fixup) {
573 // Before we get into the guts of the C2I adapter, see if we should be here
574 // at all. We've come from compiled code and are attempting to jump to the
575 // interpreter, which means the caller made a static call to get here
576 // (vcalls always get a compiled target if there is one). Check for a
577 // compiled target. If there is one, we need to patch the caller's call.
578 patch_callers_callsite(masm);
579
580 __ bind(skip_fixup);
581
582 // Since all args are passed on the stack, total_args_passed *
583 // Interpreter::stackElementSize is the space we need. Plus 1 because
584 // we also account for the return address location since
585 // we store it first rather than hold it in rax across all the shuffling
586
587 int extraspace = (total_args_passed * Interpreter::stackElementSize) + wordSize;
588
589 // stack is aligned, keep it that way
590 extraspace = align_up(extraspace, 2*wordSize);
591
592 // Get return address
593 __ pop(rax);
594
595 // set senderSP value
596 __ mov(r13, rsp);
597
598 __ subptr(rsp, extraspace);
599
600 // Store the return address in the expected location
601 __ movptr(Address(rsp, 0), rax);
602
603 // Now write the args into the outgoing interpreter space
604 for (int i = 0; i < total_args_passed; i++) {
605 if (sig_bt[i] == T_VOID) {
606 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
607 continue;
608 }
609
610 // offset to start parameters
611 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
612 int next_off = st_off - Interpreter::stackElementSize;
613
614 // Say 4 args:
615 // i st_off
616 // 0 32 T_LONG
617 // 1 24 T_VOID
618 // 2 16 T_OBJECT
619 // 3 8 T_BOOL
620 // - 0 return address
621 //
622 // However to make thing extra confusing. Because we can fit a long/double in
623 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
624 // leaves one slot empty and only stores to a single slot. In this case the
625 // slot that is occupied is the T_VOID slot. See I said it was confusing.
626
627 VMReg r_1 = regs[i].first();
628 VMReg r_2 = regs[i].second();
629 if (!r_1->is_valid()) {
630 assert(!r_2->is_valid(), "");
631 continue;
632 }
633 if (r_1->is_stack()) {
634 // memory to memory use rax
635 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
636 if (!r_2->is_valid()) {
637 // sign extend??
638 __ movl(rax, Address(rsp, ld_off));
639 __ movptr(Address(rsp, st_off), rax);
640
641 } else {
642
643 __ movq(rax, Address(rsp, ld_off));
644
645 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
646 // T_DOUBLE and T_LONG use two slots in the interpreter
647 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
648 // ld_off == LSW, ld_off+wordSize == MSW
649 // st_off == MSW, next_off == LSW
650 __ movq(Address(rsp, next_off), rax);
651 #ifdef ASSERT
652 // Overwrite the unused slot with known junk
653 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
654 __ movptr(Address(rsp, st_off), rax);
655 #endif /* ASSERT */
656 } else {
657 __ movq(Address(rsp, st_off), rax);
658 }
659 }
660 } else if (r_1->is_Register()) {
661 Register r = r_1->as_Register();
662 if (!r_2->is_valid()) {
663 // must be only an int (or less ) so move only 32bits to slot
664 // why not sign extend??
665 __ movl(Address(rsp, st_off), r);
666 } else {
667 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
668 // T_DOUBLE and T_LONG use two slots in the interpreter
669 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
670 // long/double in gpr
671 #ifdef ASSERT
672 // Overwrite the unused slot with known junk
673 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
674 __ movptr(Address(rsp, st_off), rax);
675 #endif /* ASSERT */
676 __ movq(Address(rsp, next_off), r);
677 } else {
678 __ movptr(Address(rsp, st_off), r);
679 }
680 }
681 } else {
682 assert(r_1->is_XMMRegister(), "");
683 if (!r_2->is_valid()) {
684 // only a float use just part of the slot
685 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
686 } else {
687 #ifdef ASSERT
688 // Overwrite the unused slot with known junk
689 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
690 __ movptr(Address(rsp, st_off), rax);
691 #endif /* ASSERT */
692 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
693 }
694 }
695 }
696
697 // Schedule the branch target address early.
698 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
699 __ jmp(rcx);
700 }
701
702 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
703 address code_start, address code_end,
704 Label& L_ok) {
705 Label L_fail;
706 __ lea(temp_reg, ExternalAddress(code_start));
707 __ cmpptr(pc_reg, temp_reg);
708 __ jcc(Assembler::belowEqual, L_fail);
709 __ lea(temp_reg, ExternalAddress(code_end));
710 __ cmpptr(pc_reg, temp_reg);
711 __ jcc(Assembler::below, L_ok);
712 __ bind(L_fail);
713 }
714
715 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
716 int total_args_passed,
717 int comp_args_on_stack,
718 const BasicType *sig_bt,
719 const VMRegPair *regs) {
720
721 // Note: r13 contains the senderSP on entry. We must preserve it since
722 // we may do a i2c -> c2i transition if we lose a race where compiled
723 // code goes non-entrant while we get args ready.
724 // In addition we use r13 to locate all the interpreter args as
725 // we must align the stack to 16 bytes on an i2c entry else we
726 // lose alignment we expect in all compiled code and register
727 // save code can segv when fxsave instructions find improperly
728 // aligned stack pointer.
729
730 // Adapters can be frameless because they do not require the caller
731 // to perform additional cleanup work, such as correcting the stack pointer.
732 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
733 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
734 // even if a callee has modified the stack pointer.
735 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
736 // routinely repairs its caller's stack pointer (from sender_sp, which is set
737 // up via the senderSP register).
738 // In other words, if *either* the caller or callee is interpreted, we can
739 // get the stack pointer repaired after a call.
740 // This is why c2i and i2c adapters cannot be indefinitely composed.
741 // In particular, if a c2i adapter were to somehow call an i2c adapter,
742 // both caller and callee would be compiled methods, and neither would
743 // clean up the stack pointer changes performed by the two adapters.
744 // If this happens, control eventually transfers back to the compiled
745 // caller, but with an uncorrected stack, causing delayed havoc.
746
747 // Pick up the return address
748 __ movptr(rax, Address(rsp, 0));
749
750 if (VerifyAdapterCalls &&
751 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) {
752 // So, let's test for cascading c2i/i2c adapters right now.
753 // assert(Interpreter::contains($return_addr) ||
754 // StubRoutines::contains($return_addr),
755 // "i2c adapter must return to an interpreter frame");
756 __ block_comment("verify_i2c { ");
757 Label L_ok;
758 if (Interpreter::code() != NULL)
759 range_check(masm, rax, r11,
760 Interpreter::code()->code_start(), Interpreter::code()->code_end(),
761 L_ok);
762 if (StubRoutines::code1() != NULL)
763 range_check(masm, rax, r11,
764 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(),
765 L_ok);
766 if (StubRoutines::code2() != NULL)
767 range_check(masm, rax, r11,
768 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(),
769 L_ok);
770 const char* msg = "i2c adapter must return to an interpreter frame";
771 __ block_comment(msg);
772 __ stop(msg);
773 __ bind(L_ok);
774 __ block_comment("} verify_i2ce ");
775 }
776
777 // Must preserve original SP for loading incoming arguments because
778 // we need to align the outgoing SP for compiled code.
779 __ movptr(r11, rsp);
780
781 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
782 // in registers, we will occasionally have no stack args.
783 int comp_words_on_stack = 0;
784 if (comp_args_on_stack) {
785 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
786 // registers are below. By subtracting stack0, we either get a negative
787 // number (all values in registers) or the maximum stack slot accessed.
788
789 // Convert 4-byte c2 stack slots to words.
790 comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
791 // Round up to miminum stack alignment, in wordSize
792 comp_words_on_stack = align_up(comp_words_on_stack, 2);
793 __ subptr(rsp, comp_words_on_stack * wordSize);
794 }
795
796
797 // Ensure compiled code always sees stack at proper alignment
798 __ andptr(rsp, -16);
799
800 // push the return address and misalign the stack that youngest frame always sees
801 // as far as the placement of the call instruction
802 __ push(rax);
803
804 // Put saved SP in another register
805 const Register saved_sp = rax;
806 __ movptr(saved_sp, r11);
807
808 // Will jump to the compiled code just as if compiled code was doing it.
809 // Pre-load the register-jump target early, to schedule it better.
810 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
811
812 #if INCLUDE_JVMCI
813 if (EnableJVMCI || UseAOT) {
814 // check if this call should be routed towards a specific entry point
815 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
816 Label no_alternative_target;
817 __ jcc(Assembler::equal, no_alternative_target);
818 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
819 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
820 __ bind(no_alternative_target);
821 }
822 #endif // INCLUDE_JVMCI
823
824 // Now generate the shuffle code. Pick up all register args and move the
825 // rest through the floating point stack top.
826 for (int i = 0; i < total_args_passed; i++) {
827 if (sig_bt[i] == T_VOID) {
828 // Longs and doubles are passed in native word order, but misaligned
829 // in the 32-bit build.
830 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
831 continue;
832 }
833
834 // Pick up 0, 1 or 2 words from SP+offset.
835
836 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
837 "scrambled load targets?");
838 // Load in argument order going down.
839 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
840 // Point to interpreter value (vs. tag)
841 int next_off = ld_off - Interpreter::stackElementSize;
842 //
843 //
844 //
845 VMReg r_1 = regs[i].first();
846 VMReg r_2 = regs[i].second();
847 if (!r_1->is_valid()) {
848 assert(!r_2->is_valid(), "");
849 continue;
850 }
851 if (r_1->is_stack()) {
852 // Convert stack slot to an SP offset (+ wordSize to account for return address )
853 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
854
855 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
856 // and if we end up going thru a c2i because of a miss a reasonable value of r13
857 // will be generated.
858 if (!r_2->is_valid()) {
859 // sign extend???
860 __ movl(r13, Address(saved_sp, ld_off));
861 __ movptr(Address(rsp, st_off), r13);
862 } else {
863 //
864 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
865 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
866 // So we must adjust where to pick up the data to match the interpreter.
867 //
868 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
869 // are accessed as negative so LSW is at LOW address
870
871 // ld_off is MSW so get LSW
872 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
873 next_off : ld_off;
874 __ movq(r13, Address(saved_sp, offset));
875 // st_off is LSW (i.e. reg.first())
876 __ movq(Address(rsp, st_off), r13);
877 }
878 } else if (r_1->is_Register()) { // Register argument
879 Register r = r_1->as_Register();
880 assert(r != rax, "must be different");
881 if (r_2->is_valid()) {
882 //
883 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
884 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
885 // So we must adjust where to pick up the data to match the interpreter.
886
887 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
888 next_off : ld_off;
889
890 // this can be a misaligned move
891 __ movq(r, Address(saved_sp, offset));
892 } else {
893 // sign extend and use a full word?
894 __ movl(r, Address(saved_sp, ld_off));
895 }
896 } else {
897 if (!r_2->is_valid()) {
898 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
899 } else {
900 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
901 }
902 }
903 }
904
905 // 6243940 We might end up in handle_wrong_method if
906 // the callee is deoptimized as we race thru here. If that
907 // happens we don't want to take a safepoint because the
908 // caller frame will look interpreted and arguments are now
909 // "compiled" so it is much better to make this transition
910 // invisible to the stack walking code. Unfortunately if
911 // we try and find the callee by normal means a safepoint
912 // is possible. So we stash the desired callee in the thread
913 // and the vm will find there should this case occur.
914
915 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
916
917 // put Method* where a c2i would expect should we end up there
918 // only needed becaus eof c2 resolve stubs return Method* as a result in
919 // rax
920 __ mov(rax, rbx);
921 __ jmp(r11);
922 }
923
924 // ---------------------------------------------------------------
925 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
926 int total_args_passed,
927 int comp_args_on_stack,
928 const BasicType *sig_bt,
929 const VMRegPair *regs,
930 AdapterFingerPrint* fingerprint) {
931 address i2c_entry = __ pc();
932
933 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
934
935 // -------------------------------------------------------------------------
936 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
937 // to the interpreter. The args start out packed in the compiled layout. They
938 // need to be unpacked into the interpreter layout. This will almost always
939 // require some stack space. We grow the current (compiled) stack, then repack
940 // the args. We finally end in a jump to the generic interpreter entry point.
941 // On exit from the interpreter, the interpreter will restore our SP (lest the
942 // compiled code, which relys solely on SP and not RBP, get sick).
943
944 address c2i_unverified_entry = __ pc();
945 Label skip_fixup;
946 Label ok;
947
948 Register holder = rax;
949 Register receiver = j_rarg0;
950 Register temp = rbx;
951
952 {
953 __ load_klass(temp, receiver);
954 __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
955 __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
956 __ jcc(Assembler::equal, ok);
957 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
958
959 __ bind(ok);
960 // Method might have been compiled since the call site was patched to
961 // interpreted if that is the case treat it as a miss so we can get
962 // the call site corrected.
963 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
964 __ jcc(Assembler::equal, skip_fixup);
965 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
966 }
967
968 address c2i_entry = __ pc();
969
970 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
971
972 __ flush();
973 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
974 }
975
976 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
977 VMRegPair *regs,
978 VMRegPair *regs2,
979 int total_args_passed) {
980 assert(regs2 == NULL, "not needed on x86");
981 // We return the amount of VMRegImpl stack slots we need to reserve for all
982 // the arguments NOT counting out_preserve_stack_slots.
983
984 // NOTE: These arrays will have to change when c1 is ported
985 #ifdef _WIN64
986 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
987 c_rarg0, c_rarg1, c_rarg2, c_rarg3
988 };
989 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
990 c_farg0, c_farg1, c_farg2, c_farg3
991 };
992 #else
993 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
994 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
995 };
996 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
997 c_farg0, c_farg1, c_farg2, c_farg3,
998 c_farg4, c_farg5, c_farg6, c_farg7
999 };
1000 #endif // _WIN64
1001
1002
1003 uint int_args = 0;
1004 uint fp_args = 0;
1005 uint stk_args = 0; // inc by 2 each time
1006
1007 for (int i = 0; i < total_args_passed; i++) {
1008 switch (sig_bt[i]) {
1009 case T_BOOLEAN:
1010 case T_CHAR:
1011 case T_BYTE:
1012 case T_SHORT:
1013 case T_INT:
1014 if (int_args < Argument::n_int_register_parameters_c) {
1015 regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
1016 #ifdef _WIN64
1017 fp_args++;
1018 // Allocate slots for callee to stuff register args the stack.
1019 stk_args += 2;
1020 #endif
1021 } else {
1022 regs[i].set1(VMRegImpl::stack2reg(stk_args));
1023 stk_args += 2;
1024 }
1025 break;
1026 case T_LONG:
1027 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1028 // fall through
1029 case T_OBJECT:
1030 case T_ARRAY:
1031 case T_ADDRESS:
1032 case T_METADATA:
1033 if (int_args < Argument::n_int_register_parameters_c) {
1034 regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
1035 #ifdef _WIN64
1036 fp_args++;
1037 stk_args += 2;
1038 #endif
1039 } else {
1040 regs[i].set2(VMRegImpl::stack2reg(stk_args));
1041 stk_args += 2;
1042 }
1043 break;
1044 case T_FLOAT:
1045 if (fp_args < Argument::n_float_register_parameters_c) {
1046 regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
1047 #ifdef _WIN64
1048 int_args++;
1049 // Allocate slots for callee to stuff register args the stack.
1050 stk_args += 2;
1051 #endif
1052 } else {
1053 regs[i].set1(VMRegImpl::stack2reg(stk_args));
1054 stk_args += 2;
1055 }
1056 break;
1057 case T_DOUBLE:
1058 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1059 if (fp_args < Argument::n_float_register_parameters_c) {
1060 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
1061 #ifdef _WIN64
1062 int_args++;
1063 // Allocate slots for callee to stuff register args the stack.
1064 stk_args += 2;
1065 #endif
1066 } else {
1067 regs[i].set2(VMRegImpl::stack2reg(stk_args));
1068 stk_args += 2;
1069 }
1070 break;
1071 case T_VOID: // Halves of longs and doubles
1072 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
1073 regs[i].set_bad();
1074 break;
1075 default:
1076 ShouldNotReachHere();
1077 break;
1078 }
1079 }
1080 #ifdef _WIN64
1081 // windows abi requires that we always allocate enough stack space
1082 // for 4 64bit registers to be stored down.
1083 if (stk_args < 8) {
1084 stk_args = 8;
1085 }
1086 #endif // _WIN64
1087
1088 return stk_args;
1089 }
1090
1091 // On 64 bit we will store integer like items to the stack as
1092 // 64 bits items (sparc abi) even though java would only store
1093 // 32bits for a parameter. On 32bit it will simply be 32 bits
1094 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1095 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1096 if (src.first()->is_stack()) {
1097 if (dst.first()->is_stack()) {
1098 // stack to stack
1099 __ movslq(rax, Address(rbp, reg2offset_in(src.first())));
1100 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1101 } else {
1102 // stack to reg
1103 __ movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1104 }
1105 } else if (dst.first()->is_stack()) {
1106 // reg to stack
1107 // Do we really have to sign extend???
1108 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1109 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1110 } else {
1111 // Do we really have to sign extend???
1112 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1113 if (dst.first() != src.first()) {
1114 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1115 }
1116 }
1117 }
1118
1119 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1120 if (src.first()->is_stack()) {
1121 if (dst.first()->is_stack()) {
1122 // stack to stack
1123 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1124 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1125 } else {
1126 // stack to reg
1127 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1128 }
1129 } else if (dst.first()->is_stack()) {
1130 // reg to stack
1131 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1132 } else {
1133 if (dst.first() != src.first()) {
1134 __ movq(dst.first()->as_Register(), src.first()->as_Register());
1135 }
1136 }
1137 }
1138
1139 // An oop arg. Must pass a handle not the oop itself
1140 static void object_move(MacroAssembler* masm,
1141 OopMap* map,
1142 int oop_handle_offset,
1143 int framesize_in_slots,
1144 VMRegPair src,
1145 VMRegPair dst,
1146 bool is_receiver,
1147 int* receiver_offset) {
1148
1149 // must pass a handle. First figure out the location we use as a handle
1150
1151 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1152
1153 // See if oop is NULL if it is we need no handle
1154
1155 if (src.first()->is_stack()) {
1156
1157 // Oop is already on the stack as an argument
1158 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1159 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1160 if (is_receiver) {
1161 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1162 }
1163
1164 __ cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1165 __ lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1166 // conditionally move a NULL
1167 __ cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1168 } else {
1169
1170 // Oop is in an a register we must store it to the space we reserve
1171 // on the stack for oop_handles and pass a handle if oop is non-NULL
1172
1173 const Register rOop = src.first()->as_Register();
1174 int oop_slot;
1175 if (rOop == j_rarg0)
1176 oop_slot = 0;
1177 else if (rOop == j_rarg1)
1178 oop_slot = 1;
1179 else if (rOop == j_rarg2)
1180 oop_slot = 2;
1181 else if (rOop == j_rarg3)
1182 oop_slot = 3;
1183 else if (rOop == j_rarg4)
1184 oop_slot = 4;
1185 else {
1186 assert(rOop == j_rarg5, "wrong register");
1187 oop_slot = 5;
1188 }
1189
1190 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1191 int offset = oop_slot*VMRegImpl::stack_slot_size;
1192
1193 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1194 // Store oop in handle area, may be NULL
1195 __ movptr(Address(rsp, offset), rOop);
1196 if (is_receiver) {
1197 *receiver_offset = offset;
1198 }
1199
1200 __ cmpptr(rOop, (int32_t)NULL_WORD);
1201 __ lea(rHandle, Address(rsp, offset));
1202 // conditionally move a NULL from the handle area where it was just stored
1203 __ cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1204 }
1205
1206 // If arg is on the stack then place it otherwise it is already in correct reg.
1207 if (dst.first()->is_stack()) {
1208 __ movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1209 }
1210 }
1211
1212 // A float arg may have to do float reg int reg conversion
1213 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1214 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1215
1216 // The calling conventions assures us that each VMregpair is either
1217 // all really one physical register or adjacent stack slots.
1218 // This greatly simplifies the cases here compared to sparc.
1219
1220 if (src.first()->is_stack()) {
1221 if (dst.first()->is_stack()) {
1222 __ movl(rax, Address(rbp, reg2offset_in(src.first())));
1223 __ movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1224 } else {
1225 // stack to reg
1226 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1227 __ movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1228 }
1229 } else if (dst.first()->is_stack()) {
1230 // reg to stack
1231 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1232 __ movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1233 } else {
1234 // reg to reg
1235 // In theory these overlap but the ordering is such that this is likely a nop
1236 if ( src.first() != dst.first()) {
1237 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1238 }
1239 }
1240 }
1241
1242 // A long move
1243 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1244
1245 // The calling conventions assures us that each VMregpair is either
1246 // all really one physical register or adjacent stack slots.
1247 // This greatly simplifies the cases here compared to sparc.
1248
1249 if (src.is_single_phys_reg() ) {
1250 if (dst.is_single_phys_reg()) {
1251 if (dst.first() != src.first()) {
1252 __ mov(dst.first()->as_Register(), src.first()->as_Register());
1253 }
1254 } else {
1255 assert(dst.is_single_reg(), "not a stack pair");
1256 __ movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1257 }
1258 } else if (dst.is_single_phys_reg()) {
1259 assert(src.is_single_reg(), "not a stack pair");
1260 __ movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
1261 } else {
1262 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1263 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1264 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1265 }
1266 }
1267
1268 // A double move
1269 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1270
1271 // The calling conventions assures us that each VMregpair is either
1272 // all really one physical register or adjacent stack slots.
1273 // This greatly simplifies the cases here compared to sparc.
1274
1275 if (src.is_single_phys_reg() ) {
1276 if (dst.is_single_phys_reg()) {
1277 // In theory these overlap but the ordering is such that this is likely a nop
1278 if ( src.first() != dst.first()) {
1279 __ movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1280 }
1281 } else {
1282 assert(dst.is_single_reg(), "not a stack pair");
1283 __ movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1284 }
1285 } else if (dst.is_single_phys_reg()) {
1286 assert(src.is_single_reg(), "not a stack pair");
1287 __ movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
1288 } else {
1289 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
1290 __ movq(rax, Address(rbp, reg2offset_in(src.first())));
1291 __ movq(Address(rsp, reg2offset_out(dst.first())), rax);
1292 }
1293 }
1294
1295
1296 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1297 // We always ignore the frame_slots arg and just use the space just below frame pointer
1298 // which by this time is free to use
1299 switch (ret_type) {
1300 case T_FLOAT:
1301 __ movflt(Address(rbp, -wordSize), xmm0);
1302 break;
1303 case T_DOUBLE:
1304 __ movdbl(Address(rbp, -wordSize), xmm0);
1305 break;
1306 case T_VOID: break;
1307 default: {
1308 __ movptr(Address(rbp, -wordSize), rax);
1309 }
1310 }
1311 }
1312
1313 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1314 // We always ignore the frame_slots arg and just use the space just below frame pointer
1315 // which by this time is free to use
1316 switch (ret_type) {
1317 case T_FLOAT:
1318 __ movflt(xmm0, Address(rbp, -wordSize));
1319 break;
1320 case T_DOUBLE:
1321 __ movdbl(xmm0, Address(rbp, -wordSize));
1322 break;
1323 case T_VOID: break;
1324 default: {
1325 __ movptr(rax, Address(rbp, -wordSize));
1326 }
1327 }
1328 }
1329
1330 static void save_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1331 for ( int i = first_arg ; i < arg_count ; i++ ) {
1332 if (args[i].first()->is_Register()) {
1333 __ push(args[i].first()->as_Register());
1334 } else if (args[i].first()->is_XMMRegister()) {
1335 __ subptr(rsp, 2*wordSize);
1336 __ movdbl(Address(rsp, 0), args[i].first()->as_XMMRegister());
1337 }
1338 }
1339 }
1340
1341 static void restore_args(MacroAssembler *masm, int arg_count, int first_arg, VMRegPair *args) {
1342 for ( int i = arg_count - 1 ; i >= first_arg ; i-- ) {
1343 if (args[i].first()->is_Register()) {
1344 __ pop(args[i].first()->as_Register());
1345 } else if (args[i].first()->is_XMMRegister()) {
1346 __ movdbl(args[i].first()->as_XMMRegister(), Address(rsp, 0));
1347 __ addptr(rsp, 2*wordSize);
1348 }
1349 }
1350 }
1351
1352
1353 static void save_or_restore_arguments(MacroAssembler* masm,
1354 const int stack_slots,
1355 const int total_in_args,
1356 const int arg_save_area,
1357 OopMap* map,
1358 VMRegPair* in_regs,
1359 BasicType* in_sig_bt) {
1360 // if map is non-NULL then the code should store the values,
1361 // otherwise it should load them.
1362 int slot = arg_save_area;
1363 // Save down double word first
1364 for ( int i = 0; i < total_in_args; i++) {
1365 if (in_regs[i].first()->is_XMMRegister() && in_sig_bt[i] == T_DOUBLE) {
1366 int offset = slot * VMRegImpl::stack_slot_size;
1367 slot += VMRegImpl::slots_per_word;
1368 assert(slot <= stack_slots, "overflow");
1369 if (map != NULL) {
1370 __ movdbl(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1371 } else {
1372 __ movdbl(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1373 }
1374 }
1375 if (in_regs[i].first()->is_Register() &&
1376 (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_ARRAY)) {
1377 int offset = slot * VMRegImpl::stack_slot_size;
1378 if (map != NULL) {
1379 __ movq(Address(rsp, offset), in_regs[i].first()->as_Register());
1380 if (in_sig_bt[i] == T_ARRAY) {
1381 map->set_oop(VMRegImpl::stack2reg(slot));;
1382 }
1383 } else {
1384 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
1385 }
1386 slot += VMRegImpl::slots_per_word;
1387 }
1388 }
1389 // Save or restore single word registers
1390 for ( int i = 0; i < total_in_args; i++) {
1391 if (in_regs[i].first()->is_Register()) {
1392 int offset = slot * VMRegImpl::stack_slot_size;
1393 slot++;
1394 assert(slot <= stack_slots, "overflow");
1395
1396 // Value is in an input register pass we must flush it to the stack
1397 const Register reg = in_regs[i].first()->as_Register();
1398 switch (in_sig_bt[i]) {
1399 case T_BOOLEAN:
1400 case T_CHAR:
1401 case T_BYTE:
1402 case T_SHORT:
1403 case T_INT:
1404 if (map != NULL) {
1405 __ movl(Address(rsp, offset), reg);
1406 } else {
1407 __ movl(reg, Address(rsp, offset));
1408 }
1409 break;
1410 case T_ARRAY:
1411 case T_LONG:
1412 // handled above
1413 break;
1414 case T_OBJECT:
1415 default: ShouldNotReachHere();
1416 }
1417 } else if (in_regs[i].first()->is_XMMRegister()) {
1418 if (in_sig_bt[i] == T_FLOAT) {
1419 int offset = slot * VMRegImpl::stack_slot_size;
1420 slot++;
1421 assert(slot <= stack_slots, "overflow");
1422 if (map != NULL) {
1423 __ movflt(Address(rsp, offset), in_regs[i].first()->as_XMMRegister());
1424 } else {
1425 __ movflt(in_regs[i].first()->as_XMMRegister(), Address(rsp, offset));
1426 }
1427 }
1428 } else if (in_regs[i].first()->is_stack()) {
1429 if (in_sig_bt[i] == T_ARRAY && map != NULL) {
1430 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1431 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
1432 }
1433 }
1434 }
1435 }
1436
1437 // Pin object, return pinned object or null in rax
1438 static void gen_pin_object(MacroAssembler* masm,
1439 VMRegPair reg) {
1440 __ block_comment("gen_pin_object {");
1441
1442 // rax always contains oop, either incoming or
1443 // pinned.
1444 Register tmp_reg = rax;
1445
1446 Label is_null;
1447 VMRegPair tmp;
1448 VMRegPair in_reg = reg;
1449
1450 tmp.set_ptr(tmp_reg->as_VMReg());
1451 if (reg.first()->is_stack()) {
1452 // Load the arg up from the stack
1453 move_ptr(masm, reg, tmp);
1454 reg = tmp;
1455 } else {
1456 __ movptr(rax, reg.first()->as_Register());
1457 }
1458 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1459 __ jccb(Assembler::equal, is_null);
1460
1461 if (reg.first()->as_Register() != c_rarg1) {
1462 __ movptr(c_rarg1, reg.first()->as_Register());
1463 }
1464
1465 __ call_VM_leaf(
1466 CAST_FROM_FN_PTR(address, SharedRuntime::pin_object),
1467 r15_thread, c_rarg1);
1468
1469 __ bind(is_null);
1470 __ block_comment("} gen_pin_object");
1471 }
1472
1473 // Unpin object
1474 static void gen_unpin_object(MacroAssembler* masm,
1475 VMRegPair reg) {
1476 __ block_comment("gen_unpin_object {");
1477 Label is_null;
1478
1479 if (reg.first()->is_stack()) {
1480 __ movptr(c_rarg1, Address(rbp, reg2offset_in(reg.first())));
1481 } else if (reg.first()->as_Register() != c_rarg1) {
1482 __ movptr(c_rarg1, reg.first()->as_Register());
1483 }
1484
1485 __ testptr(c_rarg1, c_rarg1);
1486 __ jccb(Assembler::equal, is_null);
1487
1488 __ call_VM_leaf(
1489 CAST_FROM_FN_PTR(address, SharedRuntime::unpin_object),
1490 r15_thread, c_rarg1);
1491
1492 __ bind(is_null);
1493 __ block_comment("} gen_unpin_object");
1494 }
1495
1496 // Check GCLocker::needs_gc and enter the runtime if it's true. This
1497 // keeps a new JNI critical region from starting until a GC has been
1498 // forced. Save down any oops in registers and describe them in an
1499 // OopMap.
1500 static void check_needs_gc_for_critical_native(MacroAssembler* masm,
1501 int stack_slots,
1502 int total_c_args,
1503 int total_in_args,
1504 int arg_save_area,
1505 OopMapSet* oop_maps,
1506 VMRegPair* in_regs,
1507 BasicType* in_sig_bt) {
1508 __ block_comment("check GCLocker::needs_gc");
1509 Label cont;
1510 __ cmp8(ExternalAddress((address)GCLocker::needs_gc_address()), false);
1511 __ jcc(Assembler::equal, cont);
1512
1513 // Save down any incoming oops and call into the runtime to halt for a GC
1514
1515 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1516 save_or_restore_arguments(masm, stack_slots, total_in_args,
1517 arg_save_area, map, in_regs, in_sig_bt);
1518
1519 address the_pc = __ pc();
1520 oop_maps->add_gc_map( __ offset(), map);
1521 __ set_last_Java_frame(rsp, noreg, the_pc);
1522
1523 __ block_comment("block_for_jni_critical");
1524 __ movptr(c_rarg0, r15_thread);
1525 __ mov(r12, rsp); // remember sp
1526 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
1527 __ andptr(rsp, -16); // align stack as required by ABI
1528 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical)));
1529 __ mov(rsp, r12); // restore sp
1530 __ reinit_heapbase();
1531
1532 __ reset_last_Java_frame(false);
1533
1534 save_or_restore_arguments(masm, stack_slots, total_in_args,
1535 arg_save_area, NULL, in_regs, in_sig_bt);
1536 __ bind(cont);
1537 #ifdef ASSERT
1538 if (StressCriticalJNINatives) {
1539 // Stress register saving
1540 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1541 save_or_restore_arguments(masm, stack_slots, total_in_args,
1542 arg_save_area, map, in_regs, in_sig_bt);
1543 // Destroy argument registers
1544 for (int i = 0; i < total_in_args - 1; i++) {
1545 if (in_regs[i].first()->is_Register()) {
1546 const Register reg = in_regs[i].first()->as_Register();
1547 __ xorptr(reg, reg);
1548 } else if (in_regs[i].first()->is_XMMRegister()) {
1549 __ xorpd(in_regs[i].first()->as_XMMRegister(), in_regs[i].first()->as_XMMRegister());
1550 } else if (in_regs[i].first()->is_FloatRegister()) {
1551 ShouldNotReachHere();
1552 } else if (in_regs[i].first()->is_stack()) {
1553 // Nothing to do
1554 } else {
1555 ShouldNotReachHere();
1556 }
1557 if (in_sig_bt[i] == T_LONG || in_sig_bt[i] == T_DOUBLE) {
1558 i++;
1559 }
1560 }
1561
1562 save_or_restore_arguments(masm, stack_slots, total_in_args,
1563 arg_save_area, NULL, in_regs, in_sig_bt);
1564 }
1565 #endif
1566 }
1567
1568 // Unpack an array argument into a pointer to the body and the length
1569 // if the array is non-null, otherwise pass 0 for both.
1570 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) {
1571 Register tmp_reg = rax;
1572 assert(!body_arg.first()->is_Register() || body_arg.first()->as_Register() != tmp_reg,
1573 "possible collision");
1574 assert(!length_arg.first()->is_Register() || length_arg.first()->as_Register() != tmp_reg,
1575 "possible collision");
1576
1577 __ block_comment("unpack_array_argument {");
1578
1579 // Pass the length, ptr pair
1580 Label is_null, done;
1581 VMRegPair tmp;
1582 tmp.set_ptr(tmp_reg->as_VMReg());
1583 if (reg.first()->is_stack()) {
1584 // Load the arg up from the stack
1585 move_ptr(masm, reg, tmp);
1586 reg = tmp;
1587 }
1588 __ testptr(reg.first()->as_Register(), reg.first()->as_Register());
1589 __ jccb(Assembler::equal, is_null);
1590 __ lea(tmp_reg, Address(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1591 move_ptr(masm, tmp, body_arg);
1592 // load the length relative to the body.
1593 __ movl(tmp_reg, Address(tmp_reg, arrayOopDesc::length_offset_in_bytes() -
1594 arrayOopDesc::base_offset_in_bytes(in_elem_type)));
1595 move32_64(masm, tmp, length_arg);
1596 __ jmpb(done);
1597 __ bind(is_null);
1598 // Pass zeros
1599 __ xorptr(tmp_reg, tmp_reg);
1600 move_ptr(masm, tmp, body_arg);
1601 move32_64(masm, tmp, length_arg);
1602 __ bind(done);
1603
1604 __ block_comment("} unpack_array_argument");
1605 }
1606
1607
1608 // Different signatures may require very different orders for the move
1609 // to avoid clobbering other arguments. There's no simple way to
1610 // order them safely. Compute a safe order for issuing stores and
1611 // break any cycles in those stores. This code is fairly general but
1612 // it's not necessary on the other platforms so we keep it in the
1613 // platform dependent code instead of moving it into a shared file.
1614 // (See bugs 7013347 & 7145024.)
1615 // Note that this code is specific to LP64.
1616 class ComputeMoveOrder: public StackObj {
1617 class MoveOperation: public ResourceObj {
1618 friend class ComputeMoveOrder;
1619 private:
1620 VMRegPair _src;
1621 VMRegPair _dst;
1622 int _src_index;
1623 int _dst_index;
1624 bool _processed;
1625 MoveOperation* _next;
1626 MoveOperation* _prev;
1627
1628 static int get_id(VMRegPair r) {
1629 return r.first()->value();
1630 }
1631
1632 public:
1633 MoveOperation(int src_index, VMRegPair src, int dst_index, VMRegPair dst):
1634 _src(src)
1635 , _src_index(src_index)
1636 , _dst(dst)
1637 , _dst_index(dst_index)
1638 , _next(NULL)
1639 , _prev(NULL)
1640 , _processed(false) {
1641 }
1642
1643 VMRegPair src() const { return _src; }
1644 int src_id() const { return get_id(src()); }
1645 int src_index() const { return _src_index; }
1646 VMRegPair dst() const { return _dst; }
1647 void set_dst(int i, VMRegPair dst) { _dst_index = i, _dst = dst; }
1648 int dst_index() const { return _dst_index; }
1649 int dst_id() const { return get_id(dst()); }
1650 MoveOperation* next() const { return _next; }
1651 MoveOperation* prev() const { return _prev; }
1652 void set_processed() { _processed = true; }
1653 bool is_processed() const { return _processed; }
1654
1655 // insert
1656 void break_cycle(VMRegPair temp_register) {
1657 // create a new store following the last store
1658 // to move from the temp_register to the original
1659 MoveOperation* new_store = new MoveOperation(-1, temp_register, dst_index(), dst());
1660
1661 // break the cycle of links and insert new_store at the end
1662 // break the reverse link.
1663 MoveOperation* p = prev();
1664 assert(p->next() == this, "must be");
1665 _prev = NULL;
1666 p->_next = new_store;
1667 new_store->_prev = p;
1668
1669 // change the original store to save it's value in the temp.
1670 set_dst(-1, temp_register);
1671 }
1672
1673 void link(GrowableArray<MoveOperation*>& killer) {
1674 // link this store in front the store that it depends on
1675 MoveOperation* n = killer.at_grow(src_id(), NULL);
1676 if (n != NULL) {
1677 assert(_next == NULL && n->_prev == NULL, "shouldn't have been set yet");
1678 _next = n;
1679 n->_prev = this;
1680 }
1681 }
1682 };
1683
1684 private:
1685 GrowableArray<MoveOperation*> edges;
1686
1687 public:
1688 ComputeMoveOrder(int total_in_args, VMRegPair* in_regs, int total_c_args, VMRegPair* out_regs,
1689 BasicType* in_sig_bt, GrowableArray<int>& arg_order, VMRegPair tmp_vmreg) {
1690 // Move operations where the dest is the stack can all be
1691 // scheduled first since they can't interfere with the other moves.
1692 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
1693 if (in_sig_bt[i] == T_ARRAY) {
1694 c_arg--;
1695 if (out_regs[c_arg].first()->is_stack() &&
1696 out_regs[c_arg + 1].first()->is_stack()) {
1697 arg_order.push(i);
1698 arg_order.push(c_arg);
1699 } else {
1700 if (out_regs[c_arg].first()->is_stack() ||
1701 in_regs[i].first() == out_regs[c_arg].first()) {
1702 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg + 1]);
1703 } else {
1704 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1705 }
1706 }
1707 } else if (in_sig_bt[i] == T_VOID) {
1708 arg_order.push(i);
1709 arg_order.push(c_arg);
1710 } else {
1711 if (out_regs[c_arg].first()->is_stack() ||
1712 in_regs[i].first() == out_regs[c_arg].first()) {
1713 arg_order.push(i);
1714 arg_order.push(c_arg);
1715 } else {
1716 add_edge(i, in_regs[i].first(), c_arg, out_regs[c_arg]);
1717 }
1718 }
1719 }
1720 // Break any cycles in the register moves and emit the in the
1721 // proper order.
1722 GrowableArray<MoveOperation*>* stores = get_store_order(tmp_vmreg);
1723 for (int i = 0; i < stores->length(); i++) {
1724 arg_order.push(stores->at(i)->src_index());
1725 arg_order.push(stores->at(i)->dst_index());
1726 }
1727 }
1728
1729 // Collected all the move operations
1730 void add_edge(int src_index, VMRegPair src, int dst_index, VMRegPair dst) {
1731 if (src.first() == dst.first()) return;
1732 edges.append(new MoveOperation(src_index, src, dst_index, dst));
1733 }
1734
1735 // Walk the edges breaking cycles between moves. The result list
1736 // can be walked in order to produce the proper set of loads
1737 GrowableArray<MoveOperation*>* get_store_order(VMRegPair temp_register) {
1738 // Record which moves kill which values
1739 GrowableArray<MoveOperation*> killer;
1740 for (int i = 0; i < edges.length(); i++) {
1741 MoveOperation* s = edges.at(i);
1742 assert(killer.at_grow(s->dst_id(), NULL) == NULL, "only one killer");
1743 killer.at_put_grow(s->dst_id(), s, NULL);
1744 }
1745 assert(killer.at_grow(MoveOperation::get_id(temp_register), NULL) == NULL,
1746 "make sure temp isn't in the registers that are killed");
1747
1748 // create links between loads and stores
1749 for (int i = 0; i < edges.length(); i++) {
1750 edges.at(i)->link(killer);
1751 }
1752
1753 // at this point, all the move operations are chained together
1754 // in a doubly linked list. Processing it backwards finds
1755 // the beginning of the chain, forwards finds the end. If there's
1756 // a cycle it can be broken at any point, so pick an edge and walk
1757 // backward until the list ends or we end where we started.
1758 GrowableArray<MoveOperation*>* stores = new GrowableArray<MoveOperation*>();
1759 for (int e = 0; e < edges.length(); e++) {
1760 MoveOperation* s = edges.at(e);
1761 if (!s->is_processed()) {
1762 MoveOperation* start = s;
1763 // search for the beginning of the chain or cycle
1764 while (start->prev() != NULL && start->prev() != s) {
1765 start = start->prev();
1766 }
1767 if (start->prev() == s) {
1768 start->break_cycle(temp_register);
1769 }
1770 // walk the chain forward inserting to store list
1771 while (start != NULL) {
1772 stores->append(start);
1773 start->set_processed();
1774 start = start->next();
1775 }
1776 }
1777 }
1778 return stores;
1779 }
1780 };
1781
1782 static void verify_oop_args(MacroAssembler* masm,
1783 const methodHandle& method,
1784 const BasicType* sig_bt,
1785 const VMRegPair* regs) {
1786 Register temp_reg = rbx; // not part of any compiled calling seq
1787 if (VerifyOops) {
1788 for (int i = 0; i < method->size_of_parameters(); i++) {
1789 if (sig_bt[i] == T_OBJECT ||
1790 sig_bt[i] == T_ARRAY) {
1791 VMReg r = regs[i].first();
1792 assert(r->is_valid(), "bad oop arg");
1793 if (r->is_stack()) {
1794 __ movptr(temp_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1795 __ verify_oop(temp_reg);
1796 } else {
1797 __ verify_oop(r->as_Register());
1798 }
1799 }
1800 }
1801 }
1802 }
1803
1804 static void gen_special_dispatch(MacroAssembler* masm,
1805 const methodHandle& method,
1806 const BasicType* sig_bt,
1807 const VMRegPair* regs) {
1808 verify_oop_args(masm, method, sig_bt, regs);
1809 vmIntrinsics::ID iid = method->intrinsic_id();
1810
1811 // Now write the args into the outgoing interpreter space
1812 bool has_receiver = false;
1813 Register receiver_reg = noreg;
1814 int member_arg_pos = -1;
1815 Register member_reg = noreg;
1816 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
1817 if (ref_kind != 0) {
1818 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument
1819 member_reg = rbx; // known to be free at this point
1820 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
1821 } else if (iid == vmIntrinsics::_invokeBasic) {
1822 has_receiver = true;
1823 } else {
1824 fatal("unexpected intrinsic id %d", iid);
1825 }
1826
1827 if (member_reg != noreg) {
1828 // Load the member_arg into register, if necessary.
1829 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
1830 VMReg r = regs[member_arg_pos].first();
1831 if (r->is_stack()) {
1832 __ movptr(member_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1833 } else {
1834 // no data motion is needed
1835 member_reg = r->as_Register();
1836 }
1837 }
1838
1839 if (has_receiver) {
1840 // Make sure the receiver is loaded into a register.
1841 assert(method->size_of_parameters() > 0, "oob");
1842 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
1843 VMReg r = regs[0].first();
1844 assert(r->is_valid(), "bad receiver arg");
1845 if (r->is_stack()) {
1846 // Porting note: This assumes that compiled calling conventions always
1847 // pass the receiver oop in a register. If this is not true on some
1848 // platform, pick a temp and load the receiver from stack.
1849 fatal("receiver always in a register");
1850 receiver_reg = j_rarg0; // known to be free at this point
1851 __ movptr(receiver_reg, Address(rsp, r->reg2stack() * VMRegImpl::stack_slot_size + wordSize));
1852 } else {
1853 // no data motion is needed
1854 receiver_reg = r->as_Register();
1855 }
1856 }
1857
1858 // Figure out which address we are really jumping to:
1859 MethodHandles::generate_method_handle_dispatch(masm, iid,
1860 receiver_reg, member_reg, /*for_compiler_entry:*/ true);
1861 }
1862
1863 // ---------------------------------------------------------------------------
1864 // Generate a native wrapper for a given method. The method takes arguments
1865 // in the Java compiled code convention, marshals them to the native
1866 // convention (handlizes oops, etc), transitions to native, makes the call,
1867 // returns to java state (possibly blocking), unhandlizes any result and
1868 // returns.
1869 //
1870 // Critical native functions are a shorthand for the use of
1871 // GetPrimtiveArrayCritical and disallow the use of any other JNI
1872 // functions. The wrapper is expected to unpack the arguments before
1873 // passing them to the callee and perform checks before and after the
1874 // native call to ensure that they GCLocker
1875 // lock_critical/unlock_critical semantics are followed. Some other
1876 // parts of JNI setup are skipped like the tear down of the JNI handle
1877 // block and the check for pending exceptions it's impossible for them
1878 // to be thrown.
1879 //
1880 // They are roughly structured like this:
1881 // if (GCLocker::needs_gc())
1882 // SharedRuntime::block_for_jni_critical();
1883 // tranistion to thread_in_native
1884 // unpack arrray arguments and call native entry point
1885 // check for safepoint in progress
1886 // check if any thread suspend flags are set
1887 // call into JVM and possible unlock the JNI critical
1888 // if a GC was suppressed while in the critical native.
1889 // transition back to thread_in_Java
1890 // return to caller
1891 //
1892 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1893 const methodHandle& method,
1894 int compile_id,
1895 BasicType* in_sig_bt,
1896 VMRegPair* in_regs,
1897 BasicType ret_type) {
1898 if (method->is_method_handle_intrinsic()) {
1899 vmIntrinsics::ID iid = method->intrinsic_id();
1900 intptr_t start = (intptr_t)__ pc();
1901 int vep_offset = ((intptr_t)__ pc()) - start;
1902 gen_special_dispatch(masm,
1903 method,
1904 in_sig_bt,
1905 in_regs);
1906 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period
1907 __ flush();
1908 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually
1909 return nmethod::new_native_nmethod(method,
1910 compile_id,
1911 masm->code(),
1912 vep_offset,
1913 frame_complete,
1914 stack_slots / VMRegImpl::slots_per_word,
1915 in_ByteSize(-1),
1916 in_ByteSize(-1),
1917 (OopMapSet*)NULL);
1918 }
1919 bool is_critical_native = true;
1920 address native_func = method->critical_native_function();
1921 if (native_func == NULL) {
1922 native_func = method->native_function();
1923 is_critical_native = false;
1924 }
1925 assert(native_func != NULL, "must have function");
1926
1927 // An OopMap for lock (and class if static)
1928 OopMapSet *oop_maps = new OopMapSet();
1929 intptr_t start = (intptr_t)__ pc();
1930
1931 // We have received a description of where all the java arg are located
1932 // on entry to the wrapper. We need to convert these args to where
1933 // the jni function will expect them. To figure out where they go
1934 // we convert the java signature to a C signature by inserting
1935 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1936
1937 const int total_in_args = method->size_of_parameters();
1938 int total_c_args = total_in_args;
1939 if (!is_critical_native) {
1940 total_c_args += 1;
1941 if (method->is_static()) {
1942 total_c_args++;
1943 }
1944 } else {
1945 for (int i = 0; i < total_in_args; i++) {
1946 if (in_sig_bt[i] == T_ARRAY) {
1947 total_c_args++;
1948 }
1949 }
1950 }
1951
1952 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1953 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1954 BasicType* in_elem_bt = NULL;
1955
1956 int argc = 0;
1957 if (!is_critical_native) {
1958 out_sig_bt[argc++] = T_ADDRESS;
1959 if (method->is_static()) {
1960 out_sig_bt[argc++] = T_OBJECT;
1961 }
1962
1963 for (int i = 0; i < total_in_args ; i++ ) {
1964 out_sig_bt[argc++] = in_sig_bt[i];
1965 }
1966 } else {
1967 Thread* THREAD = Thread::current();
1968 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args);
1969 SignatureStream ss(method->signature());
1970 for (int i = 0; i < total_in_args ; i++ ) {
1971 if (in_sig_bt[i] == T_ARRAY) {
1972 // Arrays are passed as int, elem* pair
1973 out_sig_bt[argc++] = T_INT;
1974 out_sig_bt[argc++] = T_ADDRESS;
1975 Symbol* atype = ss.as_symbol(CHECK_NULL);
1976 const char* at = atype->as_C_string();
1977 if (strlen(at) == 2) {
1978 assert(at[0] == '[', "must be");
1979 switch (at[1]) {
1980 case 'B': in_elem_bt[i] = T_BYTE; break;
1981 case 'C': in_elem_bt[i] = T_CHAR; break;
1982 case 'D': in_elem_bt[i] = T_DOUBLE; break;
1983 case 'F': in_elem_bt[i] = T_FLOAT; break;
1984 case 'I': in_elem_bt[i] = T_INT; break;
1985 case 'J': in_elem_bt[i] = T_LONG; break;
1986 case 'S': in_elem_bt[i] = T_SHORT; break;
1987 case 'Z': in_elem_bt[i] = T_BOOLEAN; break;
1988 default: ShouldNotReachHere();
1989 }
1990 }
1991 } else {
1992 out_sig_bt[argc++] = in_sig_bt[i];
1993 in_elem_bt[i] = T_VOID;
1994 }
1995 if (in_sig_bt[i] != T_VOID) {
1996 assert(in_sig_bt[i] == ss.type(), "must match");
1997 ss.next();
1998 }
1999 }
2000 }
2001
2002 // Now figure out where the args must be stored and how much stack space
2003 // they require.
2004 int out_arg_slots;
2005 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
2006
2007 // Compute framesize for the wrapper. We need to handlize all oops in
2008 // incoming registers
2009
2010 // Calculate the total number of stack slots we will need.
2011
2012 // First count the abi requirement plus all of the outgoing args
2013 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2014
2015 // Now the space for the inbound oop handle area
2016 int total_save_slots = 6 * VMRegImpl::slots_per_word; // 6 arguments passed in registers
2017 if (is_critical_native) {
2018 // Critical natives may have to call out so they need a save area
2019 // for register arguments.
2020 int double_slots = 0;
2021 int single_slots = 0;
2022 for ( int i = 0; i < total_in_args; i++) {
2023 if (in_regs[i].first()->is_Register()) {
2024 const Register reg = in_regs[i].first()->as_Register();
2025 switch (in_sig_bt[i]) {
2026 case T_BOOLEAN:
2027 case T_BYTE:
2028 case T_SHORT:
2029 case T_CHAR:
2030 case T_INT: single_slots++; break;
2031 case T_ARRAY: // specific to LP64 (7145024)
2032 case T_LONG: double_slots++; break;
2033 default: ShouldNotReachHere();
2034 }
2035 } else if (in_regs[i].first()->is_XMMRegister()) {
2036 switch (in_sig_bt[i]) {
2037 case T_FLOAT: single_slots++; break;
2038 case T_DOUBLE: double_slots++; break;
2039 default: ShouldNotReachHere();
2040 }
2041 } else if (in_regs[i].first()->is_FloatRegister()) {
2042 ShouldNotReachHere();
2043 }
2044 }
2045 total_save_slots = double_slots * 2 + single_slots;
2046 // align the save area
2047 if (double_slots != 0) {
2048 stack_slots = align_up(stack_slots, 2);
2049 }
2050 }
2051
2052 int oop_handle_offset = stack_slots;
2053 stack_slots += total_save_slots;
2054
2055 // Now any space we need for handlizing a klass if static method
2056
2057 int klass_slot_offset = 0;
2058 int klass_offset = -1;
2059 int lock_slot_offset = 0;
2060 bool is_static = false;
2061
2062 if (method->is_static()) {
2063 klass_slot_offset = stack_slots;
2064 stack_slots += VMRegImpl::slots_per_word;
2065 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
2066 is_static = true;
2067 }
2068
2069 // Plus a lock if needed
2070
2071 if (method->is_synchronized()) {
2072 lock_slot_offset = stack_slots;
2073 stack_slots += VMRegImpl::slots_per_word;
2074 }
2075
2076 // Now a place (+2) to save return values or temp during shuffling
2077 // + 4 for return address (which we own) and saved rbp
2078 stack_slots += 6;
2079
2080 // Ok The space we have allocated will look like:
2081 //
2082 //
2083 // FP-> | |
2084 // |---------------------|
2085 // | 2 slots for moves |
2086 // |---------------------|
2087 // | lock box (if sync) |
2088 // |---------------------| <- lock_slot_offset
2089 // | klass (if static) |
2090 // |---------------------| <- klass_slot_offset
2091 // | oopHandle area |
2092 // |---------------------| <- oop_handle_offset (6 java arg registers)
2093 // | outbound memory |
2094 // | based arguments |
2095 // | |
2096 // |---------------------|
2097 // | |
2098 // SP-> | out_preserved_slots |
2099 //
2100 //
2101
2102
2103 // Now compute actual number of stack words we need rounding to make
2104 // stack properly aligned.
2105 stack_slots = align_up(stack_slots, StackAlignmentInSlots);
2106
2107 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2108
2109 // First thing make an ic check to see if we should even be here
2110
2111 // We are free to use all registers as temps without saving them and
2112 // restoring them except rbp. rbp is the only callee save register
2113 // as far as the interpreter and the compiler(s) are concerned.
2114
2115
2116 const Register ic_reg = rax;
2117 const Register receiver = j_rarg0;
2118
2119 Label hit;
2120 Label exception_pending;
2121
2122 assert_different_registers(ic_reg, receiver, rscratch1);
2123 __ verify_oop(receiver);
2124 __ load_klass(rscratch1, receiver);
2125 __ cmpq(ic_reg, rscratch1);
2126 __ jcc(Assembler::equal, hit);
2127
2128 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
2129
2130 // Verified entry point must be aligned
2131 __ align(8);
2132
2133 __ bind(hit);
2134
2135 int vep_offset = ((intptr_t)__ pc()) - start;
2136
2137 #ifdef COMPILER1
2138 // For Object.hashCode, System.identityHashCode try to pull hashCode from object header if available.
2139 if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
2140 inline_check_hashcode_from_object_header(masm, method, j_rarg0 /*obj_reg*/, rax /*result*/);
2141 }
2142 #endif // COMPILER1
2143
2144 // The instruction at the verified entry point must be 5 bytes or longer
2145 // because it can be patched on the fly by make_non_entrant. The stack bang
2146 // instruction fits that requirement.
2147
2148 // Generate stack overflow check
2149
2150 if (UseStackBanging) {
2151 __ bang_stack_with_offset((int)JavaThread::stack_shadow_zone_size());
2152 } else {
2153 // need a 5 byte instruction to allow MT safe patching to non-entrant
2154 __ fat_nop();
2155 }
2156
2157 // Generate a new frame for the wrapper.
2158 __ enter();
2159 // -2 because return address is already present and so is saved rbp
2160 __ subptr(rsp, stack_size - 2*wordSize);
2161
2162 // Frame is now completed as far as size and linkage.
2163 int frame_complete = ((intptr_t)__ pc()) - start;
2164
2165 if (UseRTMLocking) {
2166 // Abort RTM transaction before calling JNI
2167 // because critical section will be large and will be
2168 // aborted anyway. Also nmethod could be deoptimized.
2169 __ xabort(0);
2170 }
2171
2172 #ifdef ASSERT
2173 {
2174 Label L;
2175 __ mov(rax, rsp);
2176 __ andptr(rax, -16); // must be 16 byte boundary (see amd64 ABI)
2177 __ cmpptr(rax, rsp);
2178 __ jcc(Assembler::equal, L);
2179 __ stop("improperly aligned stack");
2180 __ bind(L);
2181 }
2182 #endif /* ASSERT */
2183
2184
2185 // We use r14 as the oop handle for the receiver/klass
2186 // It is callee save so it survives the call to native
2187
2188 const Register oop_handle_reg = r14;
2189
2190 if (is_critical_native && !Universe::heap()->supports_object_pinning()) {
2191 check_needs_gc_for_critical_native(masm, stack_slots, total_c_args, total_in_args,
2192 oop_handle_offset, oop_maps, in_regs, in_sig_bt);
2193 }
2194
2195 //
2196 // We immediately shuffle the arguments so that any vm call we have to
2197 // make from here on out (sync slow path, jvmti, etc.) we will have
2198 // captured the oops from our caller and have a valid oopMap for
2199 // them.
2200
2201 // -----------------
2202 // The Grand Shuffle
2203
2204 // The Java calling convention is either equal (linux) or denser (win64) than the
2205 // c calling convention. However the because of the jni_env argument the c calling
2206 // convention always has at least one more (and two for static) arguments than Java.
2207 // Therefore if we move the args from java -> c backwards then we will never have
2208 // a register->register conflict and we don't have to build a dependency graph
2209 // and figure out how to break any cycles.
2210 //
2211
2212 // Record esp-based slot for receiver on stack for non-static methods
2213 int receiver_offset = -1;
2214
2215 // This is a trick. We double the stack slots so we can claim
2216 // the oops in the caller's frame. Since we are sure to have
2217 // more args than the caller doubling is enough to make
2218 // sure we can capture all the incoming oop args from the
2219 // caller.
2220 //
2221 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
2222
2223 // Mark location of rbp (someday)
2224 // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, vmreg(rbp));
2225
2226 // Use eax, ebx as temporaries during any memory-memory moves we have to do
2227 // All inbound args are referenced based on rbp and all outbound args via rsp.
2228
2229
2230 #ifdef ASSERT
2231 bool reg_destroyed[RegisterImpl::number_of_registers];
2232 bool freg_destroyed[XMMRegisterImpl::number_of_registers];
2233 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2234 reg_destroyed[r] = false;
2235 }
2236 for ( int f = 0 ; f < XMMRegisterImpl::number_of_registers ; f++ ) {
2237 freg_destroyed[f] = false;
2238 }
2239
2240 #endif /* ASSERT */
2241
2242 // This may iterate in two different directions depending on the
2243 // kind of native it is. The reason is that for regular JNI natives
2244 // the incoming and outgoing registers are offset upwards and for
2245 // critical natives they are offset down.
2246 GrowableArray<int> arg_order(2 * total_in_args);
2247 // Inbound arguments that need to be pinned for critical natives
2248 GrowableArray<int> pinned_args(total_in_args);
2249 // Current stack slot for storing register based array argument
2250 int pinned_slot = oop_handle_offset;
2251
2252 VMRegPair tmp_vmreg;
2253 tmp_vmreg.set2(rbx->as_VMReg());
2254
2255 if (!is_critical_native) {
2256 for (int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0; i--, c_arg--) {
2257 arg_order.push(i);
2258 arg_order.push(c_arg);
2259 }
2260 } else {
2261 // Compute a valid move order, using tmp_vmreg to break any cycles
2262 ComputeMoveOrder cmo(total_in_args, in_regs, total_c_args, out_regs, in_sig_bt, arg_order, tmp_vmreg);
2263 }
2264
2265 int temploc = -1;
2266 for (int ai = 0; ai < arg_order.length(); ai += 2) {
2267 int i = arg_order.at(ai);
2268 int c_arg = arg_order.at(ai + 1);
2269 __ block_comment(err_msg("move %d -> %d", i, c_arg));
2270 if (c_arg == -1) {
2271 assert(is_critical_native, "should only be required for critical natives");
2272 // This arg needs to be moved to a temporary
2273 __ mov(tmp_vmreg.first()->as_Register(), in_regs[i].first()->as_Register());
2274 in_regs[i] = tmp_vmreg;
2275 temploc = i;
2276 continue;
2277 } else if (i == -1) {
2278 assert(is_critical_native, "should only be required for critical natives");
2279 // Read from the temporary location
2280 assert(temploc != -1, "must be valid");
2281 i = temploc;
2282 temploc = -1;
2283 }
2284 #ifdef ASSERT
2285 if (in_regs[i].first()->is_Register()) {
2286 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2287 } else if (in_regs[i].first()->is_XMMRegister()) {
2288 assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2289 }
2290 if (out_regs[c_arg].first()->is_Register()) {
2291 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2292 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2293 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2294 }
2295 #endif /* ASSERT */
2296 switch (in_sig_bt[i]) {
2297 case T_ARRAY:
2298 if (is_critical_native) {
2299 // pin before unpack
2300 if (Universe::heap()->supports_object_pinning()) {
2301 save_args(masm, total_c_args, 0, out_regs);
2302 gen_pin_object(masm, in_regs[i]);
2303 pinned_args.append(i);
2304 restore_args(masm, total_c_args, 0, out_regs);
2305
2306 // rax has pinned array
2307 VMRegPair result_reg;
2308 result_reg.set_ptr(rax->as_VMReg());
2309 move_ptr(masm, result_reg, in_regs[i]);
2310 if (!in_regs[i].first()->is_stack()) {
2311 assert(pinned_slot <= stack_slots, "overflow");
2312 move_ptr(masm, result_reg, VMRegImpl::stack2reg(pinned_slot));
2313 pinned_slot += VMRegImpl::slots_per_word;
2314 }
2315 }
2316 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
2317 c_arg++;
2318 #ifdef ASSERT
2319 if (out_regs[c_arg].first()->is_Register()) {
2320 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2321 } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2322 freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2323 }
2324 #endif
2325 break;
2326 }
2327 case T_OBJECT:
2328 assert(!is_critical_native, "no oop arguments");
2329 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2330 ((i == 0) && (!is_static)),
2331 &receiver_offset);
2332 break;
2333 case T_VOID:
2334 break;
2335
2336 case T_FLOAT:
2337 float_move(masm, in_regs[i], out_regs[c_arg]);
2338 break;
2339
2340 case T_DOUBLE:
2341 assert( i + 1 < total_in_args &&
2342 in_sig_bt[i + 1] == T_VOID &&
2343 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2344 double_move(masm, in_regs[i], out_regs[c_arg]);
2345 break;
2346
2347 case T_LONG :
2348 long_move(masm, in_regs[i], out_regs[c_arg]);
2349 break;
2350
2351 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2352
2353 default:
2354 move32_64(masm, in_regs[i], out_regs[c_arg]);
2355 }
2356 }
2357
2358 int c_arg;
2359
2360 // Pre-load a static method's oop into r14. Used both by locking code and
2361 // the normal JNI call code.
2362 if (!is_critical_native) {
2363 // point c_arg at the first arg that is already loaded in case we
2364 // need to spill before we call out
2365 c_arg = total_c_args - total_in_args;
2366
2367 if (method->is_static()) {
2368
2369 // load oop into a register
2370 __ movoop(oop_handle_reg, JNIHandles::make_local(method->method_holder()->java_mirror()));
2371
2372 // Now handlize the static class mirror it's known not-null.
2373 __ movptr(Address(rsp, klass_offset), oop_handle_reg);
2374 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2375
2376 // Now get the handle
2377 __ lea(oop_handle_reg, Address(rsp, klass_offset));
2378 // store the klass handle as second argument
2379 __ movptr(c_rarg1, oop_handle_reg);
2380 // and protect the arg if we must spill
2381 c_arg--;
2382 }
2383 } else {
2384 // For JNI critical methods we need to save all registers in save_args.
2385 c_arg = 0;
2386 }
2387
2388 // Change state to native (we save the return address in the thread, since it might not
2389 // be pushed on the stack when we do a a stack traversal). It is enough that the pc()
2390 // points into the right code segment. It does not have to be the correct return pc.
2391 // We use the same pc/oopMap repeatedly when we call out
2392
2393 intptr_t the_pc = (intptr_t) __ pc();
2394 oop_maps->add_gc_map(the_pc - start, map);
2395
2396 __ set_last_Java_frame(rsp, noreg, (address)the_pc);
2397
2398
2399 // We have all of the arguments setup at this point. We must not touch any register
2400 // argument registers at this point (what if we save/restore them there are no oop?
2401
2402 {
2403 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2404 // protect the args we've loaded
2405 save_args(masm, total_c_args, c_arg, out_regs);
2406 __ mov_metadata(c_rarg1, method());
2407 __ call_VM_leaf(
2408 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2409 r15_thread, c_rarg1);
2410 restore_args(masm, total_c_args, c_arg, out_regs);
2411 }
2412
2413 // RedefineClasses() tracing support for obsolete method entry
2414 if (log_is_enabled(Trace, redefine, class, obsolete)) {
2415 // protect the args we've loaded
2416 save_args(masm, total_c_args, c_arg, out_regs);
2417 __ mov_metadata(c_rarg1, method());
2418 __ call_VM_leaf(
2419 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2420 r15_thread, c_rarg1);
2421 restore_args(masm, total_c_args, c_arg, out_regs);
2422 }
2423
2424 // Lock a synchronized method
2425
2426 // Register definitions used by locking and unlocking
2427
2428 const Register swap_reg = rax; // Must use rax for cmpxchg instruction
2429 const Register obj_reg = rbx; // Will contain the oop
2430 const Register lock_reg = r13; // Address of compiler lock object (BasicLock)
2431 const Register old_hdr = r13; // value of old header at unlock time
2432
2433 Label slow_path_lock;
2434 Label lock_done;
2435
2436 if (method->is_synchronized()) {
2437 assert(!is_critical_native, "unhandled");
2438
2439
2440 const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2441
2442 // Get the handle (the 2nd argument)
2443 __ mov(oop_handle_reg, c_rarg1);
2444
2445 // Get address of the box
2446
2447 __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2448
2449 // Load the oop from the handle
2450 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2451
2452 if (UseBiasedLocking) {
2453 __ biased_locking_enter(lock_reg, obj_reg, swap_reg, rscratch1, false, lock_done, &slow_path_lock);
2454 }
2455
2456 // Load immediate 1 into swap_reg %rax
2457 __ movl(swap_reg, 1);
2458
2459 // Load (object->mark() | 1) into swap_reg %rax
2460 __ orptr(swap_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2461
2462 // Save (object->mark() | 1) into BasicLock's displaced header
2463 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2464
2465 if (os::is_MP()) {
2466 __ lock();
2467 }
2468
2469 // src -> dest iff dest == rax else rax <- dest
2470 __ cmpxchgptr(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2471 __ jcc(Assembler::equal, lock_done);
2472
2473 // Hmm should this move to the slow path code area???
2474
2475 // Test if the oopMark is an obvious stack pointer, i.e.,
2476 // 1) (mark & 3) == 0, and
2477 // 2) rsp <= mark < mark + os::pagesize()
2478 // These 3 tests can be done by evaluating the following
2479 // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2480 // assuming both stack pointer and pagesize have their
2481 // least significant 2 bits clear.
2482 // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2483
2484 __ subptr(swap_reg, rsp);
2485 __ andptr(swap_reg, 3 - os::vm_page_size());
2486
2487 // Save the test result, for recursive case, the result is zero
2488 __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2489 __ jcc(Assembler::notEqual, slow_path_lock);
2490
2491 // Slow path will re-enter here
2492
2493 __ bind(lock_done);
2494 }
2495
2496
2497 // Finally just about ready to make the JNI call
2498
2499
2500 // get JNIEnv* which is first argument to native
2501 if (!is_critical_native) {
2502 __ lea(c_rarg0, Address(r15_thread, in_bytes(JavaThread::jni_environment_offset())));
2503 }
2504
2505 // Now set thread in native
2506 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2507
2508 __ call(RuntimeAddress(native_func));
2509
2510 // Verify or restore cpu control state after JNI call
2511 __ restore_cpu_control_state_after_jni();
2512
2513 // Unpack native results.
2514 switch (ret_type) {
2515 case T_BOOLEAN: __ c2bool(rax); break;
2516 case T_CHAR : __ movzwl(rax, rax); break;
2517 case T_BYTE : __ sign_extend_byte (rax); break;
2518 case T_SHORT : __ sign_extend_short(rax); break;
2519 case T_INT : /* nothing to do */ break;
2520 case T_DOUBLE :
2521 case T_FLOAT :
2522 // Result is in xmm0 we'll save as needed
2523 break;
2524 case T_ARRAY: // Really a handle
2525 case T_OBJECT: // Really a handle
2526 break; // can't de-handlize until after safepoint check
2527 case T_VOID: break;
2528 case T_LONG: break;
2529 default : ShouldNotReachHere();
2530 }
2531
2532 // unpin pinned arguments
2533 pinned_slot = oop_handle_offset;
2534 if (pinned_args.length() > 0) {
2535 // save return value that may be overwritten otherwise.
2536 save_native_result(masm, ret_type, stack_slots);
2537 for (int index = 0; index < pinned_args.length(); index ++) {
2538 int i = pinned_args.at(index);
2539 assert(pinned_slot <= stack_slots, "overflow");
2540 if (!in_regs[i].first()->is_stack()) {
2541 int offset = pinned_slot * VMRegImpl::stack_slot_size;
2542 __ movq(in_regs[i].first()->as_Register(), Address(rsp, offset));
2543 pinned_slot += VMRegImpl::slots_per_word;
2544 }
2545 gen_unpin_object(masm, in_regs[i]);
2546 }
2547 restore_native_result(masm, ret_type, stack_slots);
2548 }
2549
2550 // Switch thread to "native transition" state before reading the synchronization state.
2551 // This additional state is necessary because reading and testing the synchronization
2552 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2553 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2554 // VM thread changes sync state to synchronizing and suspends threads for GC.
2555 // Thread A is resumed to finish this native method, but doesn't block here since it
2556 // didn't see any synchronization is progress, and escapes.
2557 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2558
2559 if(os::is_MP()) {
2560 if (UseMembar) {
2561 // Force this write out before the read below
2562 __ membar(Assembler::Membar_mask_bits(
2563 Assembler::LoadLoad | Assembler::LoadStore |
2564 Assembler::StoreLoad | Assembler::StoreStore));
2565 } else {
2566 // Write serialization page so VM thread can do a pseudo remote membar.
2567 // We use the current thread pointer to calculate a thread specific
2568 // offset to write to within the page. This minimizes bus traffic
2569 // due to cache line collision.
2570 __ serialize_memory(r15_thread, rcx);
2571 }
2572 }
2573
2574 Label after_transition;
2575
2576 // check for safepoint operation in progress and/or pending suspend requests
2577 {
2578 Label Continue;
2579 Label slow_path;
2580
2581 __ safepoint_poll(slow_path, r15_thread, rscratch1);
2582
2583 __ cmpl(Address(r15_thread, JavaThread::suspend_flags_offset()), 0);
2584 __ jcc(Assembler::equal, Continue);
2585 __ bind(slow_path);
2586
2587 // Don't use call_VM as it will see a possible pending exception and forward it
2588 // and never return here preventing us from clearing _last_native_pc down below.
2589 // Also can't use call_VM_leaf either as it will check to see if rsi & rdi are
2590 // preserved and correspond to the bcp/locals pointers. So we do a runtime call
2591 // by hand.
2592 //
2593 __ vzeroupper();
2594 save_native_result(masm, ret_type, stack_slots);
2595 __ mov(c_rarg0, r15_thread);
2596 __ mov(r12, rsp); // remember sp
2597 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2598 __ andptr(rsp, -16); // align stack as required by ABI
2599 if (!is_critical_native) {
2600 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans)));
2601 } else {
2602 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition)));
2603 }
2604 __ mov(rsp, r12); // restore sp
2605 __ reinit_heapbase();
2606 // Restore any method result value
2607 restore_native_result(masm, ret_type, stack_slots);
2608
2609 if (is_critical_native) {
2610 // The call above performed the transition to thread_in_Java so
2611 // skip the transition logic below.
2612 __ jmpb(after_transition);
2613 }
2614
2615 __ bind(Continue);
2616 }
2617
2618 // change thread state
2619 __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_Java);
2620 __ bind(after_transition);
2621
2622 Label reguard;
2623 Label reguard_done;
2624 __ cmpl(Address(r15_thread, JavaThread::stack_guard_state_offset()), JavaThread::stack_guard_yellow_reserved_disabled);
2625 __ jcc(Assembler::equal, reguard);
2626 __ bind(reguard_done);
2627
2628 // native result if any is live
2629
2630 // Unlock
2631 Label unlock_done;
2632 Label slow_path_unlock;
2633 if (method->is_synchronized()) {
2634
2635 // Get locked oop from the handle we passed to jni
2636 __ movptr(obj_reg, Address(oop_handle_reg, 0));
2637
2638 Label done;
2639
2640 if (UseBiasedLocking) {
2641 __ biased_locking_exit(obj_reg, old_hdr, done);
2642 }
2643
2644 // Simple recursive lock?
2645
2646 __ cmpptr(Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size), (int32_t)NULL_WORD);
2647 __ jcc(Assembler::equal, done);
2648
2649 // Must save rax if if it is live now because cmpxchg must use it
2650 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2651 save_native_result(masm, ret_type, stack_slots);
2652 }
2653
2654
2655 // get address of the stack lock
2656 __ lea(rax, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2657 // get old displaced header
2658 __ movptr(old_hdr, Address(rax, 0));
2659
2660 // Atomic swap old header if oop still contains the stack lock
2661 if (os::is_MP()) {
2662 __ lock();
2663 }
2664 __ cmpxchgptr(old_hdr, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2665 __ jcc(Assembler::notEqual, slow_path_unlock);
2666
2667 // slow path re-enters here
2668 __ bind(unlock_done);
2669 if (ret_type != T_FLOAT && ret_type != T_DOUBLE && ret_type != T_VOID) {
2670 restore_native_result(masm, ret_type, stack_slots);
2671 }
2672
2673 __ bind(done);
2674
2675 }
2676 {
2677 SkipIfEqual skip(masm, &DTraceMethodProbes, false);
2678 save_native_result(masm, ret_type, stack_slots);
2679 __ mov_metadata(c_rarg1, method());
2680 __ call_VM_leaf(
2681 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2682 r15_thread, c_rarg1);
2683 restore_native_result(masm, ret_type, stack_slots);
2684 }
2685
2686 __ reset_last_Java_frame(false);
2687
2688 // Unbox oop result, e.g. JNIHandles::resolve value.
2689 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2690 __ resolve_jobject(rax /* value */,
2691 r15_thread /* thread */,
2692 rcx /* tmp */);
2693 }
2694
2695 if (CheckJNICalls) {
2696 // clear_pending_jni_exception_check
2697 __ movptr(Address(r15_thread, JavaThread::pending_jni_exception_check_fn_offset()), NULL_WORD);
2698 }
2699
2700 if (!is_critical_native) {
2701 // reset handle block
2702 __ movptr(rcx, Address(r15_thread, JavaThread::active_handles_offset()));
2703 __ movl(Address(rcx, JNIHandleBlock::top_offset_in_bytes()), (int32_t)NULL_WORD);
2704 }
2705
2706 // pop our frame
2707
2708 __ leave();
2709
2710 if (!is_critical_native) {
2711 // Any exception pending?
2712 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2713 __ jcc(Assembler::notEqual, exception_pending);
2714 }
2715
2716 // Return
2717
2718 __ ret(0);
2719
2720 // Unexpected paths are out of line and go here
2721
2722 if (!is_critical_native) {
2723 // forward the exception
2724 __ bind(exception_pending);
2725
2726 // and forward the exception
2727 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2728 }
2729
2730 // Slow path locking & unlocking
2731 if (method->is_synchronized()) {
2732
2733 // BEGIN Slow path lock
2734 __ bind(slow_path_lock);
2735
2736 // has last_Java_frame setup. No exceptions so do vanilla call not call_VM
2737 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2738
2739 // protect the args we've loaded
2740 save_args(masm, total_c_args, c_arg, out_regs);
2741
2742 __ mov(c_rarg0, obj_reg);
2743 __ mov(c_rarg1, lock_reg);
2744 __ mov(c_rarg2, r15_thread);
2745
2746 // Not a leaf but we have last_Java_frame setup as we want
2747 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), 3);
2748 restore_args(masm, total_c_args, c_arg, out_regs);
2749
2750 #ifdef ASSERT
2751 { Label L;
2752 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2753 __ jcc(Assembler::equal, L);
2754 __ stop("no pending exception allowed on exit from monitorenter");
2755 __ bind(L);
2756 }
2757 #endif
2758 __ jmp(lock_done);
2759
2760 // END Slow path lock
2761
2762 // BEGIN Slow path unlock
2763 __ bind(slow_path_unlock);
2764
2765 // If we haven't already saved the native result we must save it now as xmm registers
2766 // are still exposed.
2767 __ vzeroupper();
2768 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2769 save_native_result(masm, ret_type, stack_slots);
2770 }
2771
2772 __ lea(c_rarg1, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2773
2774 __ mov(c_rarg0, obj_reg);
2775 __ mov(c_rarg2, r15_thread);
2776 __ mov(r12, rsp); // remember sp
2777 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2778 __ andptr(rsp, -16); // align stack as required by ABI
2779
2780 // Save pending exception around call to VM (which contains an EXCEPTION_MARK)
2781 // NOTE that obj_reg == rbx currently
2782 __ movptr(rbx, Address(r15_thread, in_bytes(Thread::pending_exception_offset())));
2783 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int32_t)NULL_WORD);
2784
2785 // args are (oop obj, BasicLock* lock, JavaThread* thread)
2786 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C)));
2787 __ mov(rsp, r12); // restore sp
2788 __ reinit_heapbase();
2789 #ifdef ASSERT
2790 {
2791 Label L;
2792 __ cmpptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), (int)NULL_WORD);
2793 __ jcc(Assembler::equal, L);
2794 __ stop("no pending exception allowed on exit complete_monitor_unlocking_C");
2795 __ bind(L);
2796 }
2797 #endif /* ASSERT */
2798
2799 __ movptr(Address(r15_thread, in_bytes(Thread::pending_exception_offset())), rbx);
2800
2801 if (ret_type == T_FLOAT || ret_type == T_DOUBLE ) {
2802 restore_native_result(masm, ret_type, stack_slots);
2803 }
2804 __ jmp(unlock_done);
2805
2806 // END Slow path unlock
2807
2808 } // synchronized
2809
2810 // SLOW PATH Reguard the stack if needed
2811
2812 __ bind(reguard);
2813 __ vzeroupper();
2814 save_native_result(masm, ret_type, stack_slots);
2815 __ mov(r12, rsp); // remember sp
2816 __ subptr(rsp, frame::arg_reg_save_area_bytes); // windows
2817 __ andptr(rsp, -16); // align stack as required by ABI
2818 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)));
2819 __ mov(rsp, r12); // restore sp
2820 __ reinit_heapbase();
2821 restore_native_result(masm, ret_type, stack_slots);
2822 // and continue
2823 __ jmp(reguard_done);
2824
2825
2826
2827 __ flush();
2828
2829 nmethod *nm = nmethod::new_native_nmethod(method,
2830 compile_id,
2831 masm->code(),
2832 vep_offset,
2833 frame_complete,
2834 stack_slots / VMRegImpl::slots_per_word,
2835 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2836 in_ByteSize(lock_slot_offset*VMRegImpl::stack_slot_size),
2837 oop_maps);
2838
2839 if (is_critical_native) {
2840 nm->set_lazy_critical_native(true);
2841 }
2842
2843 return nm;
2844
2845 }
2846
2847 // this function returns the adjust size (in number of words) to a c2i adapter
2848 // activation for use during deoptimization
2849 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals ) {
2850 return (callee_locals - callee_parameters) * Interpreter::stackElementWords;
2851 }
2852
2853
2854 uint SharedRuntime::out_preserve_stack_slots() {
2855 return 0;
2856 }
2857
2858 //------------------------------generate_deopt_blob----------------------------
2859 void SharedRuntime::generate_deopt_blob() {
2860 // Allocate space for the code
2861 ResourceMark rm;
2862 // Setup code generation tools
2863 int pad = 0;
2864 #if INCLUDE_JVMCI
2865 if (EnableJVMCI || UseAOT) {
2866 pad += 512; // Increase the buffer size when compiling for JVMCI
2867 }
2868 #endif
2869 CodeBuffer buffer("deopt_blob", 2048+pad, 1024);
2870 MacroAssembler* masm = new MacroAssembler(&buffer);
2871 int frame_size_in_words;
2872 OopMap* map = NULL;
2873 OopMapSet *oop_maps = new OopMapSet();
2874
2875 // -------------
2876 // This code enters when returning to a de-optimized nmethod. A return
2877 // address has been pushed on the the stack, and return values are in
2878 // registers.
2879 // If we are doing a normal deopt then we were called from the patched
2880 // nmethod from the point we returned to the nmethod. So the return
2881 // address on the stack is wrong by NativeCall::instruction_size
2882 // We will adjust the value so it looks like we have the original return
2883 // address on the stack (like when we eagerly deoptimized).
2884 // In the case of an exception pending when deoptimizing, we enter
2885 // with a return address on the stack that points after the call we patched
2886 // into the exception handler. We have the following register state from,
2887 // e.g., the forward exception stub (see stubGenerator_x86_64.cpp).
2888 // rax: exception oop
2889 // rbx: exception handler
2890 // rdx: throwing pc
2891 // So in this case we simply jam rdx into the useless return address and
2892 // the stack looks just like we want.
2893 //
2894 // At this point we need to de-opt. We save the argument return
2895 // registers. We call the first C routine, fetch_unroll_info(). This
2896 // routine captures the return values and returns a structure which
2897 // describes the current frame size and the sizes of all replacement frames.
2898 // The current frame is compiled code and may contain many inlined
2899 // functions, each with their own JVM state. We pop the current frame, then
2900 // push all the new frames. Then we call the C routine unpack_frames() to
2901 // populate these frames. Finally unpack_frames() returns us the new target
2902 // address. Notice that callee-save registers are BLOWN here; they have
2903 // already been captured in the vframeArray at the time the return PC was
2904 // patched.
2905 address start = __ pc();
2906 Label cont;
2907
2908 // Prolog for non exception case!
2909
2910 // Save everything in sight.
2911 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2912
2913 // Normal deoptimization. Save exec mode for unpack_frames.
2914 __ movl(r14, Deoptimization::Unpack_deopt); // callee-saved
2915 __ jmp(cont);
2916
2917 int reexecute_offset = __ pc() - start;
2918 #if INCLUDE_JVMCI && !defined(COMPILER1)
2919 if (EnableJVMCI && UseJVMCICompiler) {
2920 // JVMCI does not use this kind of deoptimization
2921 __ should_not_reach_here();
2922 }
2923 #endif
2924
2925 // Reexecute case
2926 // return address is the pc describes what bci to do re-execute at
2927
2928 // No need to update map as each call to save_live_registers will produce identical oopmap
2929 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2930
2931 __ movl(r14, Deoptimization::Unpack_reexecute); // callee-saved
2932 __ jmp(cont);
2933
2934 #if INCLUDE_JVMCI
2935 Label after_fetch_unroll_info_call;
2936 int implicit_exception_uncommon_trap_offset = 0;
2937 int uncommon_trap_offset = 0;
2938
2939 if (EnableJVMCI || UseAOT) {
2940 implicit_exception_uncommon_trap_offset = __ pc() - start;
2941
2942 __ pushptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())));
2943 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_implicit_exception_pc_offset())), (int32_t)NULL_WORD);
2944
2945 uncommon_trap_offset = __ pc() - start;
2946
2947 // Save everything in sight.
2948 RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2949 // fetch_unroll_info needs to call last_java_frame()
2950 __ set_last_Java_frame(noreg, noreg, NULL);
2951
2952 __ movl(c_rarg1, Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset())));
2953 __ movl(Address(r15_thread, in_bytes(JavaThread::pending_deoptimization_offset())), -1);
2954
2955 __ movl(r14, (int32_t)Deoptimization::Unpack_reexecute);
2956 __ mov(c_rarg0, r15_thread);
2957 __ movl(c_rarg2, r14); // exec mode
2958 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
2959 oop_maps->add_gc_map( __ pc()-start, map->deep_copy());
2960
2961 __ reset_last_Java_frame(false);
2962
2963 __ jmp(after_fetch_unroll_info_call);
2964 } // EnableJVMCI
2965 #endif // INCLUDE_JVMCI
2966
2967 int exception_offset = __ pc() - start;
2968
2969 // Prolog for exception case
2970
2971 // all registers are dead at this entry point, except for rax, and
2972 // rdx which contain the exception oop and exception pc
2973 // respectively. Set them in TLS and fall thru to the
2974 // unpack_with_exception_in_tls entry point.
2975
2976 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
2977 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), rax);
2978
2979 int exception_in_tls_offset = __ pc() - start;
2980
2981 // new implementation because exception oop is now passed in JavaThread
2982
2983 // Prolog for exception case
2984 // All registers must be preserved because they might be used by LinearScan
2985 // Exceptiop oop and throwing PC are passed in JavaThread
2986 // tos: stack at point of call to method that threw the exception (i.e. only
2987 // args are on the stack, no return address)
2988
2989 // make room on stack for the return address
2990 // It will be patched later with the throwing pc. The correct value is not
2991 // available now because loading it from memory would destroy registers.
2992 __ push(0);
2993
2994 // Save everything in sight.
2995 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
2996
2997 // Now it is safe to overwrite any register
2998
2999 // Deopt during an exception. Save exec mode for unpack_frames.
3000 __ movl(r14, Deoptimization::Unpack_exception); // callee-saved
3001
3002 // load throwing pc from JavaThread and patch it as the return address
3003 // of the current frame. Then clear the field in JavaThread
3004
3005 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3006 __ movptr(Address(rbp, wordSize), rdx);
3007 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3008
3009 #ifdef ASSERT
3010 // verify that there is really an exception oop in JavaThread
3011 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3012 __ verify_oop(rax);
3013
3014 // verify that there is no pending exception
3015 Label no_pending_exception;
3016 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3017 __ testptr(rax, rax);
3018 __ jcc(Assembler::zero, no_pending_exception);
3019 __ stop("must not have pending exception here");
3020 __ bind(no_pending_exception);
3021 #endif
3022
3023 __ bind(cont);
3024
3025 // Call C code. Need thread and this frame, but NOT official VM entry
3026 // crud. We cannot block on this call, no GC can happen.
3027 //
3028 // UnrollBlock* fetch_unroll_info(JavaThread* thread)
3029
3030 // fetch_unroll_info needs to call last_java_frame().
3031
3032 __ set_last_Java_frame(noreg, noreg, NULL);
3033 #ifdef ASSERT
3034 { Label L;
3035 __ cmpptr(Address(r15_thread,
3036 JavaThread::last_Java_fp_offset()),
3037 (int32_t)0);
3038 __ jcc(Assembler::equal, L);
3039 __ stop("SharedRuntime::generate_deopt_blob: last_Java_fp not cleared");
3040 __ bind(L);
3041 }
3042 #endif // ASSERT
3043 __ mov(c_rarg0, r15_thread);
3044 __ movl(c_rarg1, r14); // exec_mode
3045 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info)));
3046
3047 // Need to have an oopmap that tells fetch_unroll_info where to
3048 // find any register it might need.
3049 oop_maps->add_gc_map(__ pc() - start, map);
3050
3051 __ reset_last_Java_frame(false);
3052
3053 #if INCLUDE_JVMCI
3054 if (EnableJVMCI || UseAOT) {
3055 __ bind(after_fetch_unroll_info_call);
3056 }
3057 #endif
3058
3059 // Load UnrollBlock* into rdi
3060 __ mov(rdi, rax);
3061
3062 __ movl(r14, Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()));
3063 Label noException;
3064 __ cmpl(r14, Deoptimization::Unpack_exception); // Was exception pending?
3065 __ jcc(Assembler::notEqual, noException);
3066 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
3067 // QQQ this is useless it was NULL above
3068 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
3069 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
3070 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
3071
3072 __ verify_oop(rax);
3073
3074 // Overwrite the result registers with the exception results.
3075 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3076 // I think this is useless
3077 __ movptr(Address(rsp, RegisterSaver::rdx_offset_in_bytes()), rdx);
3078
3079 __ bind(noException);
3080
3081 // Only register save data is on the stack.
3082 // Now restore the result registers. Everything else is either dead
3083 // or captured in the vframeArray.
3084 RegisterSaver::restore_result_registers(masm);
3085
3086 // All of the register save area has been popped of the stack. Only the
3087 // return address remains.
3088
3089 // Pop all the frames we must move/replace.
3090 //
3091 // Frame picture (youngest to oldest)
3092 // 1: self-frame (no frame link)
3093 // 2: deopting frame (no frame link)
3094 // 3: caller of deopting frame (could be compiled/interpreted).
3095 //
3096 // Note: by leaving the return address of self-frame on the stack
3097 // and using the size of frame 2 to adjust the stack
3098 // when we are done the return to frame 3 will still be on the stack.
3099
3100 // Pop deoptimized frame
3101 __ movl(rcx, Address(rdi, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
3102 __ addptr(rsp, rcx);
3103
3104 // rsp should be pointing at the return address to the caller (3)
3105
3106 // Pick up the initial fp we should save
3107 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3108 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3109
3110 #ifdef ASSERT
3111 // Compilers generate code that bang the stack by as much as the
3112 // interpreter would need. So this stack banging should never
3113 // trigger a fault. Verify that it does not on non product builds.
3114 if (UseStackBanging) {
3115 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3116 __ bang_stack_size(rbx, rcx);
3117 }
3118 #endif
3119
3120 // Load address of array of frame pcs into rcx
3121 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3122
3123 // Trash the old pc
3124 __ addptr(rsp, wordSize);
3125
3126 // Load address of array of frame sizes into rsi
3127 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
3128
3129 // Load counter into rdx
3130 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
3131
3132 // Now adjust the caller's stack to make up for the extra locals
3133 // but record the original sp so that we can save it in the skeletal interpreter
3134 // frame and the stack walking of interpreter_sender will get the unextended sp
3135 // value and not the "real" sp value.
3136
3137 const Register sender_sp = r8;
3138
3139 __ mov(sender_sp, rsp);
3140 __ movl(rbx, Address(rdi,
3141 Deoptimization::UnrollBlock::
3142 caller_adjustment_offset_in_bytes()));
3143 __ subptr(rsp, rbx);
3144
3145 // Push interpreter frames in a loop
3146 Label loop;
3147 __ bind(loop);
3148 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3149 __ subptr(rbx, 2*wordSize); // We'll push pc and ebp by hand
3150 __ pushptr(Address(rcx, 0)); // Save return address
3151 __ enter(); // Save old & set new ebp
3152 __ subptr(rsp, rbx); // Prolog
3153 // This value is corrected by layout_activation_impl
3154 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3155 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize), sender_sp); // Make it walkable
3156 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3157 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3158 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3159 __ decrementl(rdx); // Decrement counter
3160 __ jcc(Assembler::notZero, loop);
3161 __ pushptr(Address(rcx, 0)); // Save final return address
3162
3163 // Re-push self-frame
3164 __ enter(); // Save old & set new ebp
3165
3166 // Allocate a full sized register save area.
3167 // Return address and rbp are in place, so we allocate two less words.
3168 __ subptr(rsp, (frame_size_in_words - 2) * wordSize);
3169
3170 // Restore frame locals after moving the frame
3171 __ movdbl(Address(rsp, RegisterSaver::xmm0_offset_in_bytes()), xmm0);
3172 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3173
3174 // Call C code. Need thread but NOT official VM entry
3175 // crud. We cannot block on this call, no GC can happen. Call should
3176 // restore return values to their stack-slots with the new SP.
3177 //
3178 // void Deoptimization::unpack_frames(JavaThread* thread, int exec_mode)
3179
3180 // Use rbp because the frames look interpreted now
3181 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3182 // Don't need the precise return PC here, just precise enough to point into this code blob.
3183 address the_pc = __ pc();
3184 __ set_last_Java_frame(noreg, rbp, the_pc);
3185
3186 __ andptr(rsp, -(StackAlignmentInBytes)); // Fix stack alignment as required by ABI
3187 __ mov(c_rarg0, r15_thread);
3188 __ movl(c_rarg1, r14); // second arg: exec_mode
3189 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3190 // Revert SP alignment after call since we're going to do some SP relative addressing below
3191 __ movptr(rsp, Address(r15_thread, JavaThread::last_Java_sp_offset()));
3192
3193 // Set an oopmap for the call site
3194 // Use the same PC we used for the last java frame
3195 oop_maps->add_gc_map(the_pc - start,
3196 new OopMap( frame_size_in_words, 0 ));
3197
3198 // Clear fp AND pc
3199 __ reset_last_Java_frame(true);
3200
3201 // Collect return values
3202 __ movdbl(xmm0, Address(rsp, RegisterSaver::xmm0_offset_in_bytes()));
3203 __ movptr(rax, Address(rsp, RegisterSaver::rax_offset_in_bytes()));
3204 // I think this is useless (throwing pc?)
3205 __ movptr(rdx, Address(rsp, RegisterSaver::rdx_offset_in_bytes()));
3206
3207 // Pop self-frame.
3208 __ leave(); // Epilog
3209
3210 // Jump to interpreter
3211 __ ret(0);
3212
3213 // Make sure all code is generated
3214 masm->flush();
3215
3216 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_in_words);
3217 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3218 #if INCLUDE_JVMCI
3219 if (EnableJVMCI || UseAOT) {
3220 _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
3221 _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
3222 }
3223 #endif
3224 }
3225
3226 #ifdef COMPILER2
3227 //------------------------------generate_uncommon_trap_blob--------------------
3228 void SharedRuntime::generate_uncommon_trap_blob() {
3229 // Allocate space for the code
3230 ResourceMark rm;
3231 // Setup code generation tools
3232 CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
3233 MacroAssembler* masm = new MacroAssembler(&buffer);
3234
3235 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3236
3237 address start = __ pc();
3238
3239 if (UseRTMLocking) {
3240 // Abort RTM transaction before possible nmethod deoptimization.
3241 __ xabort(0);
3242 }
3243
3244 // Push self-frame. We get here with a return address on the
3245 // stack, so rsp is 8-byte aligned until we allocate our frame.
3246 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog!
3247
3248 // No callee saved registers. rbp is assumed implicitly saved
3249 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3250
3251 // compiler left unloaded_class_index in j_rarg0 move to where the
3252 // runtime expects it.
3253 __ movl(c_rarg1, j_rarg0);
3254
3255 __ set_last_Java_frame(noreg, noreg, NULL);
3256
3257 // Call C code. Need thread but NOT official VM entry
3258 // crud. We cannot block on this call, no GC can happen. Call should
3259 // capture callee-saved registers as well as return values.
3260 // Thread is in rdi already.
3261 //
3262 // UnrollBlock* uncommon_trap(JavaThread* thread, jint unloaded_class_index);
3263
3264 __ mov(c_rarg0, r15_thread);
3265 __ movl(c_rarg2, Deoptimization::Unpack_uncommon_trap);
3266 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap)));
3267
3268 // Set an oopmap for the call site
3269 OopMapSet* oop_maps = new OopMapSet();
3270 OopMap* map = new OopMap(SimpleRuntimeFrame::framesize, 0);
3271
3272 // location of rbp is known implicitly by the frame sender code
3273
3274 oop_maps->add_gc_map(__ pc() - start, map);
3275
3276 __ reset_last_Java_frame(false);
3277
3278 // Load UnrollBlock* into rdi
3279 __ mov(rdi, rax);
3280
3281 #ifdef ASSERT
3282 { Label L;
3283 __ cmpptr(Address(rdi, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()),
3284 (int32_t)Deoptimization::Unpack_uncommon_trap);
3285 __ jcc(Assembler::equal, L);
3286 __ stop("SharedRuntime::generate_deopt_blob: expected Unpack_uncommon_trap");
3287 __ bind(L);
3288 }
3289 #endif
3290
3291 // Pop all the frames we must move/replace.
3292 //
3293 // Frame picture (youngest to oldest)
3294 // 1: self-frame (no frame link)
3295 // 2: deopting frame (no frame link)
3296 // 3: caller of deopting frame (could be compiled/interpreted).
3297
3298 // Pop self-frame. We have no frame, and must rely only on rax and rsp.
3299 __ addptr(rsp, (SimpleRuntimeFrame::framesize - 2) << LogBytesPerInt); // Epilog!
3300
3301 // Pop deoptimized frame (int)
3302 __ movl(rcx, Address(rdi,
3303 Deoptimization::UnrollBlock::
3304 size_of_deoptimized_frame_offset_in_bytes()));
3305 __ addptr(rsp, rcx);
3306
3307 // rsp should be pointing at the return address to the caller (3)
3308
3309 // Pick up the initial fp we should save
3310 // restore rbp before stack bang because if stack overflow is thrown it needs to be pushed (and preserved)
3311 __ movptr(rbp, Address(rdi, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
3312
3313 #ifdef ASSERT
3314 // Compilers generate code that bang the stack by as much as the
3315 // interpreter would need. So this stack banging should never
3316 // trigger a fault. Verify that it does not on non product builds.
3317 if (UseStackBanging) {
3318 __ movl(rbx, Address(rdi ,Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
3319 __ bang_stack_size(rbx, rcx);
3320 }
3321 #endif
3322
3323 // Load address of array of frame pcs into rcx (address*)
3324 __ movptr(rcx, Address(rdi, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
3325
3326 // Trash the return pc
3327 __ addptr(rsp, wordSize);
3328
3329 // Load address of array of frame sizes into rsi (intptr_t*)
3330 __ movptr(rsi, Address(rdi, Deoptimization::UnrollBlock:: frame_sizes_offset_in_bytes()));
3331
3332 // Counter
3333 __ movl(rdx, Address(rdi, Deoptimization::UnrollBlock:: number_of_frames_offset_in_bytes())); // (int)
3334
3335 // Now adjust the caller's stack to make up for the extra locals but
3336 // record the original sp so that we can save it in the skeletal
3337 // interpreter frame and the stack walking of interpreter_sender
3338 // will get the unextended sp value and not the "real" sp value.
3339
3340 const Register sender_sp = r8;
3341
3342 __ mov(sender_sp, rsp);
3343 __ movl(rbx, Address(rdi, Deoptimization::UnrollBlock:: caller_adjustment_offset_in_bytes())); // (int)
3344 __ subptr(rsp, rbx);
3345
3346 // Push interpreter frames in a loop
3347 Label loop;
3348 __ bind(loop);
3349 __ movptr(rbx, Address(rsi, 0)); // Load frame size
3350 __ subptr(rbx, 2 * wordSize); // We'll push pc and rbp by hand
3351 __ pushptr(Address(rcx, 0)); // Save return address
3352 __ enter(); // Save old & set new rbp
3353 __ subptr(rsp, rbx); // Prolog
3354 __ movptr(Address(rbp, frame::interpreter_frame_sender_sp_offset * wordSize),
3355 sender_sp); // Make it walkable
3356 // This value is corrected by layout_activation_impl
3357 __ movptr(Address(rbp, frame::interpreter_frame_last_sp_offset * wordSize), (int32_t)NULL_WORD );
3358 __ mov(sender_sp, rsp); // Pass sender_sp to next frame
3359 __ addptr(rsi, wordSize); // Bump array pointer (sizes)
3360 __ addptr(rcx, wordSize); // Bump array pointer (pcs)
3361 __ decrementl(rdx); // Decrement counter
3362 __ jcc(Assembler::notZero, loop);
3363 __ pushptr(Address(rcx, 0)); // Save final return address
3364
3365 // Re-push self-frame
3366 __ enter(); // Save old & set new rbp
3367 __ subptr(rsp, (SimpleRuntimeFrame::framesize - 4) << LogBytesPerInt);
3368 // Prolog
3369
3370 // Use rbp because the frames look interpreted now
3371 // Save "the_pc" since it cannot easily be retrieved using the last_java_SP after we aligned SP.
3372 // Don't need the precise return PC here, just precise enough to point into this code blob.
3373 address the_pc = __ pc();
3374 __ set_last_Java_frame(noreg, rbp, the_pc);
3375
3376 // Call C code. Need thread but NOT official VM entry
3377 // crud. We cannot block on this call, no GC can happen. Call should
3378 // restore return values to their stack-slots with the new SP.
3379 // Thread is in rdi already.
3380 //
3381 // BasicType unpack_frames(JavaThread* thread, int exec_mode);
3382
3383 __ andptr(rsp, -(StackAlignmentInBytes)); // Align SP as required by ABI
3384 __ mov(c_rarg0, r15_thread);
3385 __ movl(c_rarg1, Deoptimization::Unpack_uncommon_trap);
3386 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames)));
3387
3388 // Set an oopmap for the call site
3389 // Use the same PC we used for the last java frame
3390 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3391
3392 // Clear fp AND pc
3393 __ reset_last_Java_frame(true);
3394
3395 // Pop self-frame.
3396 __ leave(); // Epilog
3397
3398 // Jump to interpreter
3399 __ ret(0);
3400
3401 // Make sure all code is generated
3402 masm->flush();
3403
3404 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, oop_maps,
3405 SimpleRuntimeFrame::framesize >> 1);
3406 }
3407 #endif // COMPILER2
3408
3409
3410 //------------------------------generate_handler_blob------
3411 //
3412 // Generate a special Compile2Runtime blob that saves all registers,
3413 // and setup oopmap.
3414 //
3415 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
3416 assert(StubRoutines::forward_exception_entry() != NULL,
3417 "must be generated before");
3418
3419 ResourceMark rm;
3420 OopMapSet *oop_maps = new OopMapSet();
3421 OopMap* map;
3422
3423 // Allocate space for the code. Setup code generation tools.
3424 CodeBuffer buffer("handler_blob", 2048, 1024);
3425 MacroAssembler* masm = new MacroAssembler(&buffer);
3426
3427 address start = __ pc();
3428 address call_pc = NULL;
3429 int frame_size_in_words;
3430 bool cause_return = (poll_type == POLL_AT_RETURN);
3431 bool save_vectors = (poll_type == POLL_AT_VECTOR_LOOP);
3432
3433 if (UseRTMLocking) {
3434 // Abort RTM transaction before calling runtime
3435 // because critical section will be large and will be
3436 // aborted anyway. Also nmethod could be deoptimized.
3437 __ xabort(0);
3438 }
3439
3440 // Make room for return address (or push it again)
3441 if (!cause_return) {
3442 __ push(rbx);
3443 }
3444
3445 // Save registers, fpu state, and flags
3446 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, save_vectors);
3447
3448 // The following is basically a call_VM. However, we need the precise
3449 // address of the call in order to generate an oopmap. Hence, we do all the
3450 // work outselves.
3451
3452 __ set_last_Java_frame(noreg, noreg, NULL);
3453
3454 // The return address must always be correct so that frame constructor never
3455 // sees an invalid pc.
3456
3457 if (!cause_return) {
3458 // Get the return pc saved by the signal handler and stash it in its appropriate place on the stack.
3459 // Additionally, rbx is a callee saved register and we can look at it later to determine
3460 // if someone changed the return address for us!
3461 __ movptr(rbx, Address(r15_thread, JavaThread::saved_exception_pc_offset()));
3462 __ movptr(Address(rbp, wordSize), rbx);
3463 }
3464
3465 // Do the call
3466 __ mov(c_rarg0, r15_thread);
3467 __ call(RuntimeAddress(call_ptr));
3468
3469 // Set an oopmap for the call site. This oopmap will map all
3470 // oop-registers and debug-info registers as callee-saved. This
3471 // will allow deoptimization at this safepoint to find all possible
3472 // debug-info recordings, as well as let GC find all oops.
3473
3474 oop_maps->add_gc_map( __ pc() - start, map);
3475
3476 Label noException;
3477
3478 __ reset_last_Java_frame(false);
3479
3480 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3481 __ jcc(Assembler::equal, noException);
3482
3483 // Exception pending
3484
3485 RegisterSaver::restore_live_registers(masm, save_vectors);
3486
3487 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3488
3489 // No exception case
3490 __ bind(noException);
3491
3492 Label no_adjust, bail, no_prefix, not_special;
3493 if (SafepointMechanism::uses_thread_local_poll() && !cause_return) {
3494 // If our stashed return pc was modified by the runtime we avoid touching it
3495 __ cmpptr(rbx, Address(rbp, wordSize));
3496 __ jccb(Assembler::notEqual, no_adjust);
3497
3498 // Skip over the poll instruction.
3499 // See NativeInstruction::is_safepoint_poll()
3500 // Possible encodings:
3501 // 85 00 test %eax,(%rax)
3502 // 85 01 test %eax,(%rcx)
3503 // 85 02 test %eax,(%rdx)
3504 // 85 03 test %eax,(%rbx)
3505 // 85 06 test %eax,(%rsi)
3506 // 85 07 test %eax,(%rdi)
3507 //
3508 // 41 85 00 test %eax,(%r8)
3509 // 41 85 01 test %eax,(%r9)
3510 // 41 85 02 test %eax,(%r10)
3511 // 41 85 03 test %eax,(%r11)
3512 // 41 85 06 test %eax,(%r14)
3513 // 41 85 07 test %eax,(%r15)
3514 //
3515 // 85 04 24 test %eax,(%rsp)
3516 // 41 85 04 24 test %eax,(%r12)
3517 // 85 45 00 test %eax,0x0(%rbp)
3518 // 41 85 45 00 test %eax,0x0(%r13)
3519
3520 __ cmpb(Address(rbx, 0), NativeTstRegMem::instruction_rex_b_prefix);
3521 __ jcc(Assembler::notEqual, no_prefix);
3522 __ addptr(rbx, 1);
3523 __ bind(no_prefix);
3524 #ifdef ASSERT
3525 __ movptr(rax, rbx); // remember where 0x85 should be, for verification below
3526 #endif
3527 // r12/r13/rsp/rbp base encoding takes 3 bytes with the following register values:
3528 // r12/rsp 0x04
3529 // r13/rbp 0x05
3530 __ movzbq(rcx, Address(rbx, 1));
3531 __ andptr(rcx, 0x07); // looking for 0x04 .. 0x05
3532 __ subptr(rcx, 4); // looking for 0x00 .. 0x01
3533 __ cmpptr(rcx, 1);
3534 __ jcc(Assembler::above, not_special);
3535 __ addptr(rbx, 1);
3536 __ bind(not_special);
3537 #ifdef ASSERT
3538 // Verify the correct encoding of the poll we're about to skip.
3539 __ cmpb(Address(rax, 0), NativeTstRegMem::instruction_code_memXregl);
3540 __ jcc(Assembler::notEqual, bail);
3541 // Mask out the modrm bits
3542 __ testb(Address(rax, 1), NativeTstRegMem::modrm_mask);
3543 // rax encodes to 0, so if the bits are nonzero it's incorrect
3544 __ jcc(Assembler::notZero, bail);
3545 #endif
3546 // Adjust return pc forward to step over the safepoint poll instruction
3547 __ addptr(rbx, 2);
3548 __ movptr(Address(rbp, wordSize), rbx);
3549 }
3550
3551 __ bind(no_adjust);
3552 // Normal exit, restore registers and exit.
3553 RegisterSaver::restore_live_registers(masm, save_vectors);
3554 __ ret(0);
3555
3556 #ifdef ASSERT
3557 __ bind(bail);
3558 __ stop("Attempting to adjust pc to skip safepoint poll but the return point is not what we expected");
3559 #endif
3560
3561 // Make sure all code is generated
3562 masm->flush();
3563
3564 // Fill-out other meta info
3565 return SafepointBlob::create(&buffer, oop_maps, frame_size_in_words);
3566 }
3567
3568 //
3569 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3570 //
3571 // Generate a stub that calls into vm to find out the proper destination
3572 // of a java call. All the argument registers are live at this point
3573 // but since this is generic code we don't know what they are and the caller
3574 // must do any gc of the args.
3575 //
3576 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
3577 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3578
3579 // allocate space for the code
3580 ResourceMark rm;
3581
3582 CodeBuffer buffer(name, 1000, 512);
3583 MacroAssembler* masm = new MacroAssembler(&buffer);
3584
3585 int frame_size_in_words;
3586
3587 OopMapSet *oop_maps = new OopMapSet();
3588 OopMap* map = NULL;
3589
3590 int start = __ offset();
3591
3592 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words);
3593
3594 int frame_complete = __ offset();
3595
3596 __ set_last_Java_frame(noreg, noreg, NULL);
3597
3598 __ mov(c_rarg0, r15_thread);
3599
3600 __ call(RuntimeAddress(destination));
3601
3602
3603 // Set an oopmap for the call site.
3604 // We need this not only for callee-saved registers, but also for volatile
3605 // registers that the compiler might be keeping live across a safepoint.
3606
3607 oop_maps->add_gc_map( __ offset() - start, map);
3608
3609 // rax contains the address we are going to jump to assuming no exception got installed
3610
3611 // clear last_Java_sp
3612 __ reset_last_Java_frame(false);
3613 // check for pending exceptions
3614 Label pending;
3615 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
3616 __ jcc(Assembler::notEqual, pending);
3617
3618 // get the returned Method*
3619 __ get_vm_result_2(rbx, r15_thread);
3620 __ movptr(Address(rsp, RegisterSaver::rbx_offset_in_bytes()), rbx);
3621
3622 __ movptr(Address(rsp, RegisterSaver::rax_offset_in_bytes()), rax);
3623
3624 RegisterSaver::restore_live_registers(masm);
3625
3626 // We are back the the original state on entry and ready to go.
3627
3628 __ jmp(rax);
3629
3630 // Pending exception after the safepoint
3631
3632 __ bind(pending);
3633
3634 RegisterSaver::restore_live_registers(masm);
3635
3636 // exception pending => remove activation and forward to exception handler
3637
3638 __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), (int)NULL_WORD);
3639
3640 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
3641 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
3642
3643 // -------------
3644 // make sure all code is generated
3645 masm->flush();
3646
3647 // return the blob
3648 // frame_size_words or bytes??
3649 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_in_words, oop_maps, true);
3650 }
3651
3652
3653 //------------------------------Montgomery multiplication------------------------
3654 //
3655
3656 #ifndef _WINDOWS
3657
3658 #define ASM_SUBTRACT
3659
3660 #ifdef ASM_SUBTRACT
3661 // Subtract 0:b from carry:a. Return carry.
3662 static unsigned long
3663 sub(unsigned long a[], unsigned long b[], unsigned long carry, long len) {
3664 long i = 0, cnt = len;
3665 unsigned long tmp;
3666 asm volatile("clc; "
3667 "0: ; "
3668 "mov (%[b], %[i], 8), %[tmp]; "
3669 "sbb %[tmp], (%[a], %[i], 8); "
3670 "inc %[i]; dec %[cnt]; "
3671 "jne 0b; "
3672 "mov %[carry], %[tmp]; sbb $0, %[tmp]; "
3673 : [i]"+r"(i), [cnt]"+r"(cnt), [tmp]"=&r"(tmp)
3674 : [a]"r"(a), [b]"r"(b), [carry]"r"(carry)
3675 : "memory");
3676 return tmp;
3677 }
3678 #else // ASM_SUBTRACT
3679 typedef int __attribute__((mode(TI))) int128;
3680
3681 // Subtract 0:b from carry:a. Return carry.
3682 static unsigned long
3683 sub(unsigned long a[], unsigned long b[], unsigned long carry, int len) {
3684 int128 tmp = 0;
3685 int i;
3686 for (i = 0; i < len; i++) {
3687 tmp += a[i];
3688 tmp -= b[i];
3689 a[i] = tmp;
3690 tmp >>= 64;
3691 assert(-1 <= tmp && tmp <= 0, "invariant");
3692 }
3693 return tmp + carry;
3694 }
3695 #endif // ! ASM_SUBTRACT
3696
3697 // Multiply (unsigned) Long A by Long B, accumulating the double-
3698 // length result into the accumulator formed of T0, T1, and T2.
3699 #define MACC(A, B, T0, T1, T2) \
3700 do { \
3701 unsigned long hi, lo; \
3702 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4" \
3703 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \
3704 : "r"(A), "a"(B) : "cc"); \
3705 } while(0)
3706
3707 // As above, but add twice the double-length result into the
3708 // accumulator.
3709 #define MACC2(A, B, T0, T1, T2) \
3710 do { \
3711 unsigned long hi, lo; \
3712 __asm__ ("mul %5; add %%rax, %2; adc %%rdx, %3; adc $0, %4; " \
3713 "add %%rax, %2; adc %%rdx, %3; adc $0, %4" \
3714 : "=&d"(hi), "=a"(lo), "+r"(T0), "+r"(T1), "+g"(T2) \
3715 : "r"(A), "a"(B) : "cc"); \
3716 } while(0)
3717
3718 // Fast Montgomery multiplication. The derivation of the algorithm is
3719 // in A Cryptographic Library for the Motorola DSP56000,
3720 // Dusse and Kaliski, Proc. EUROCRYPT 90, pp. 230-237.
3721
3722 static void __attribute__((noinline))
3723 montgomery_multiply(unsigned long a[], unsigned long b[], unsigned long n[],
3724 unsigned long m[], unsigned long inv, int len) {
3725 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
3726 int i;
3727
3728 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply");
3729
3730 for (i = 0; i < len; i++) {
3731 int j;
3732 for (j = 0; j < i; j++) {
3733 MACC(a[j], b[i-j], t0, t1, t2);
3734 MACC(m[j], n[i-j], t0, t1, t2);
3735 }
3736 MACC(a[i], b[0], t0, t1, t2);
3737 m[i] = t0 * inv;
3738 MACC(m[i], n[0], t0, t1, t2);
3739
3740 assert(t0 == 0, "broken Montgomery multiply");
3741
3742 t0 = t1; t1 = t2; t2 = 0;
3743 }
3744
3745 for (i = len; i < 2*len; i++) {
3746 int j;
3747 for (j = i-len+1; j < len; j++) {
3748 MACC(a[j], b[i-j], t0, t1, t2);
3749 MACC(m[j], n[i-j], t0, t1, t2);
3750 }
3751 m[i-len] = t0;
3752 t0 = t1; t1 = t2; t2 = 0;
3753 }
3754
3755 while (t0)
3756 t0 = sub(m, n, t0, len);
3757 }
3758
3759 // Fast Montgomery squaring. This uses asymptotically 25% fewer
3760 // multiplies so it should be up to 25% faster than Montgomery
3761 // multiplication. However, its loop control is more complex and it
3762 // may actually run slower on some machines.
3763
3764 static void __attribute__((noinline))
3765 montgomery_square(unsigned long a[], unsigned long n[],
3766 unsigned long m[], unsigned long inv, int len) {
3767 unsigned long t0 = 0, t1 = 0, t2 = 0; // Triple-precision accumulator
3768 int i;
3769
3770 assert(inv * n[0] == -1UL, "broken inverse in Montgomery multiply");
3771
3772 for (i = 0; i < len; i++) {
3773 int j;
3774 int end = (i+1)/2;
3775 for (j = 0; j < end; j++) {
3776 MACC2(a[j], a[i-j], t0, t1, t2);
3777 MACC(m[j], n[i-j], t0, t1, t2);
3778 }
3779 if ((i & 1) == 0) {
3780 MACC(a[j], a[j], t0, t1, t2);
3781 }
3782 for (; j < i; j++) {
3783 MACC(m[j], n[i-j], t0, t1, t2);
3784 }
3785 m[i] = t0 * inv;
3786 MACC(m[i], n[0], t0, t1, t2);
3787
3788 assert(t0 == 0, "broken Montgomery square");
3789
3790 t0 = t1; t1 = t2; t2 = 0;
3791 }
3792
3793 for (i = len; i < 2*len; i++) {
3794 int start = i-len+1;
3795 int end = start + (len - start)/2;
3796 int j;
3797 for (j = start; j < end; j++) {
3798 MACC2(a[j], a[i-j], t0, t1, t2);
3799 MACC(m[j], n[i-j], t0, t1, t2);
3800 }
3801 if ((i & 1) == 0) {
3802 MACC(a[j], a[j], t0, t1, t2);
3803 }
3804 for (; j < len; j++) {
3805 MACC(m[j], n[i-j], t0, t1, t2);
3806 }
3807 m[i-len] = t0;
3808 t0 = t1; t1 = t2; t2 = 0;
3809 }
3810
3811 while (t0)
3812 t0 = sub(m, n, t0, len);
3813 }
3814
3815 // Swap words in a longword.
3816 static unsigned long swap(unsigned long x) {
3817 return (x << 32) | (x >> 32);
3818 }
3819
3820 // Copy len longwords from s to d, word-swapping as we go. The
3821 // destination array is reversed.
3822 static void reverse_words(unsigned long *s, unsigned long *d, int len) {
3823 d += len;
3824 while(len-- > 0) {
3825 d--;
3826 *d = swap(*s);
3827 s++;
3828 }
3829 }
3830
3831 // The threshold at which squaring is advantageous was determined
3832 // experimentally on an i7-3930K (Ivy Bridge) CPU @ 3.5GHz.
3833 #define MONTGOMERY_SQUARING_THRESHOLD 64
3834
3835 void SharedRuntime::montgomery_multiply(jint *a_ints, jint *b_ints, jint *n_ints,
3836 jint len, jlong inv,
3837 jint *m_ints) {
3838 assert(len % 2 == 0, "array length in montgomery_multiply must be even");
3839 int longwords = len/2;
3840
3841 // Make very sure we don't use so much space that the stack might
3842 // overflow. 512 jints corresponds to an 16384-bit integer and
3843 // will use here a total of 8k bytes of stack space.
3844 int total_allocation = longwords * sizeof (unsigned long) * 4;
3845 guarantee(total_allocation <= 8192, "must be");
3846 unsigned long *scratch = (unsigned long *)alloca(total_allocation);
3847
3848 // Local scratch arrays
3849 unsigned long
3850 *a = scratch + 0 * longwords,
3851 *b = scratch + 1 * longwords,
3852 *n = scratch + 2 * longwords,
3853 *m = scratch + 3 * longwords;
3854
3855 reverse_words((unsigned long *)a_ints, a, longwords);
3856 reverse_words((unsigned long *)b_ints, b, longwords);
3857 reverse_words((unsigned long *)n_ints, n, longwords);
3858
3859 ::montgomery_multiply(a, b, n, m, (unsigned long)inv, longwords);
3860
3861 reverse_words(m, (unsigned long *)m_ints, longwords);
3862 }
3863
3864 void SharedRuntime::montgomery_square(jint *a_ints, jint *n_ints,
3865 jint len, jlong inv,
3866 jint *m_ints) {
3867 assert(len % 2 == 0, "array length in montgomery_square must be even");
3868 int longwords = len/2;
3869
3870 // Make very sure we don't use so much space that the stack might
3871 // overflow. 512 jints corresponds to an 16384-bit integer and
3872 // will use here a total of 6k bytes of stack space.
3873 int total_allocation = longwords * sizeof (unsigned long) * 3;
3874 guarantee(total_allocation <= 8192, "must be");
3875 unsigned long *scratch = (unsigned long *)alloca(total_allocation);
3876
3877 // Local scratch arrays
3878 unsigned long
3879 *a = scratch + 0 * longwords,
3880 *n = scratch + 1 * longwords,
3881 *m = scratch + 2 * longwords;
3882
3883 reverse_words((unsigned long *)a_ints, a, longwords);
3884 reverse_words((unsigned long *)n_ints, n, longwords);
3885
3886 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3887 ::montgomery_square(a, n, m, (unsigned long)inv, longwords);
3888 } else {
3889 ::montgomery_multiply(a, a, n, m, (unsigned long)inv, longwords);
3890 }
3891
3892 reverse_words(m, (unsigned long *)m_ints, longwords);
3893 }
3894
3895 #endif // WINDOWS
3896
3897 #ifdef COMPILER2
3898 // This is here instead of runtime_x86_64.cpp because it uses SimpleRuntimeFrame
3899 //
3900 //------------------------------generate_exception_blob---------------------------
3901 // creates exception blob at the end
3902 // Using exception blob, this code is jumped from a compiled method.
3903 // (see emit_exception_handler in x86_64.ad file)
3904 //
3905 // Given an exception pc at a call we call into the runtime for the
3906 // handler in this method. This handler might merely restore state
3907 // (i.e. callee save registers) unwind the frame and jump to the
3908 // exception handler for the nmethod if there is no Java level handler
3909 // for the nmethod.
3910 //
3911 // This code is entered with a jmp.
3912 //
3913 // Arguments:
3914 // rax: exception oop
3915 // rdx: exception pc
3916 //
3917 // Results:
3918 // rax: exception oop
3919 // rdx: exception pc in caller or ???
3920 // destination: exception handler of caller
3921 //
3922 // Note: the exception pc MUST be at a call (precise debug information)
3923 // Registers rax, rdx, rcx, rsi, rdi, r8-r11 are not callee saved.
3924 //
3925
3926 void OptoRuntime::generate_exception_blob() {
3927 assert(!OptoRuntime::is_callee_saved_register(RDX_num), "");
3928 assert(!OptoRuntime::is_callee_saved_register(RAX_num), "");
3929 assert(!OptoRuntime::is_callee_saved_register(RCX_num), "");
3930
3931 assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
3932
3933 // Allocate space for the code
3934 ResourceMark rm;
3935 // Setup code generation tools
3936 CodeBuffer buffer("exception_blob", 2048, 1024);
3937 MacroAssembler* masm = new MacroAssembler(&buffer);
3938
3939
3940 address start = __ pc();
3941
3942 // Exception pc is 'return address' for stack walker
3943 __ push(rdx);
3944 __ subptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Prolog
3945
3946 // Save callee-saved registers. See x86_64.ad.
3947
3948 // rbp is an implicitly saved callee saved register (i.e., the calling
3949 // convention will save/restore it in the prolog/epilog). Other than that
3950 // there are no callee save registers now that adapter frames are gone.
3951
3952 __ movptr(Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt), rbp);
3953
3954 // Store exception in Thread object. We cannot pass any arguments to the
3955 // handle_exception call, since we do not want to make any assumption
3956 // about the size of the frame where the exception happened in.
3957 // c_rarg0 is either rdi (Linux) or rcx (Windows).
3958 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()),rax);
3959 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), rdx);
3960
3961 // This call does all the hard work. It checks if an exception handler
3962 // exists in the method.
3963 // If so, it returns the handler address.
3964 // If not, it prepares for stack-unwinding, restoring the callee-save
3965 // registers of the frame being removed.
3966 //
3967 // address OptoRuntime::handle_exception_C(JavaThread* thread)
3968
3969 // At a method handle call, the stack may not be properly aligned
3970 // when returning with an exception.
3971 address the_pc = __ pc();
3972 __ set_last_Java_frame(noreg, noreg, the_pc);
3973 __ mov(c_rarg0, r15_thread);
3974 __ andptr(rsp, -(StackAlignmentInBytes)); // Align stack
3975 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, OptoRuntime::handle_exception_C)));
3976
3977 // Set an oopmap for the call site. This oopmap will only be used if we
3978 // are unwinding the stack. Hence, all locations will be dead.
3979 // Callee-saved registers will be the same as the frame above (i.e.,
3980 // handle_exception_stub), since they were restored when we got the
3981 // exception.
3982
3983 OopMapSet* oop_maps = new OopMapSet();
3984
3985 oop_maps->add_gc_map(the_pc - start, new OopMap(SimpleRuntimeFrame::framesize, 0));
3986
3987 __ reset_last_Java_frame(false);
3988
3989 // Restore callee-saved registers
3990
3991 // rbp is an implicitly saved callee-saved register (i.e., the calling
3992 // convention will save restore it in prolog/epilog) Other than that
3993 // there are no callee save registers now that adapter frames are gone.
3994
3995 __ movptr(rbp, Address(rsp, SimpleRuntimeFrame::rbp_off << LogBytesPerInt));
3996
3997 __ addptr(rsp, SimpleRuntimeFrame::return_off << LogBytesPerInt); // Epilog
3998 __ pop(rdx); // No need for exception pc anymore
3999
4000 // rax: exception handler
4001
4002 // We have a handler in rax (could be deopt blob).
4003 __ mov(r8, rax);
4004
4005 // Get the exception oop
4006 __ movptr(rax, Address(r15_thread, JavaThread::exception_oop_offset()));
4007 // Get the exception pc in case we are deoptimized
4008 __ movptr(rdx, Address(r15_thread, JavaThread::exception_pc_offset()));
4009 #ifdef ASSERT
4010 __ movptr(Address(r15_thread, JavaThread::exception_handler_pc_offset()), (int)NULL_WORD);
4011 __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), (int)NULL_WORD);
4012 #endif
4013 // Clear the exception oop so GC no longer processes it as a root.
4014 __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), (int)NULL_WORD);
4015
4016 // rax: exception oop
4017 // r8: exception handler
4018 // rdx: exception pc
4019 // Jump to handler
4020
4021 __ jmp(r8);
4022
4023 // Make sure all code is generated
4024 masm->flush();
4025
4026 // Set exception blob
4027 _exception_blob = ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
4028 }
4029 #endif // COMPILER2