1 /*
2 * Copyright (c) 1999, 2013, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_MacroAssembler.hpp"
29 #include "c1/c1_Runtime1.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "nativeInst_x86.hpp"
32 #include "oops/compiledICHolder.hpp"
33 #include "oops/oop.inline.hpp"
34 #include "prims/jvmtiExport.hpp"
35 #include "register_x86.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/signature.hpp"
38 #include "runtime/vframeArray.hpp"
39 #include "utilities/macros.hpp"
40 #include "vmreg_x86.inline.hpp"
41 #if INCLUDE_ALL_GCS
42 #include "gc_implementation/g1/g1SATBCardTableModRefBS.hpp"
43 #endif
44
45
46 // Implementation of StubAssembler
47
48 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
49 // setup registers
50 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions)
51 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different");
52 assert(oop_result1 != thread && metadata_result != thread, "registers must be different");
53 assert(args_size >= 0, "illegal args_size");
54 bool align_stack = false;
55 #ifdef _LP64
56 // At a method handle call, the stack may not be properly aligned
57 // when returning with an exception.
58 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id);
59 #endif
60
61 #ifdef _LP64
62 mov(c_rarg0, thread);
63 set_num_rt_args(0); // Nothing on stack
64 #else
65 set_num_rt_args(1 + args_size);
66
67 // push java thread (becomes first argument of C function)
68 get_thread(thread);
69 push(thread);
70 #endif // _LP64
71
72 int call_offset;
73 if (!align_stack) {
74 set_last_Java_frame(thread, noreg, rbp, NULL);
75 } else {
76 address the_pc = pc();
77 call_offset = offset();
78 set_last_Java_frame(thread, noreg, rbp, the_pc);
79 andptr(rsp, -(StackAlignmentInBytes)); // Align stack
80 }
81
82 // do the call
83 call(RuntimeAddress(entry));
84 if (!align_stack) {
85 call_offset = offset();
86 }
87 // verify callee-saved register
88 #ifdef ASSERT
89 guarantee(thread != rax, "change this code");
90 push(rax);
91 { Label L;
92 get_thread(rax);
93 cmpptr(thread, rax);
94 jcc(Assembler::equal, L);
95 int3();
96 stop("StubAssembler::call_RT: rdi not callee saved?");
97 bind(L);
98 }
99 pop(rax);
100 #endif
101 reset_last_Java_frame(thread, true, align_stack);
102
103 // discard thread and arguments
104 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord));
105
106 // check for pending exceptions
107 { Label L;
108 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
109 jcc(Assembler::equal, L);
110 // exception pending => remove activation and forward to exception handler
111 movptr(rax, Address(thread, Thread::pending_exception_offset()));
112 // make sure that the vm_results are cleared
113 if (oop_result1->is_valid()) {
114 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
115 }
116 if (metadata_result->is_valid()) {
117 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
118 }
119 if (frame_size() == no_frame_size) {
120 leave();
121 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
122 } else if (_stub_id == Runtime1::forward_exception_id) {
123 should_not_reach_here();
124 } else {
125 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
126 }
127 bind(L);
128 }
129 // get oop results if there are any and reset the values in the thread
130 if (oop_result1->is_valid()) {
131 get_vm_result(oop_result1, thread);
132 }
133 if (metadata_result->is_valid()) {
134 get_vm_result_2(metadata_result, thread);
135 }
136 return call_offset;
137 }
138
139
140 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
141 #ifdef _LP64
142 mov(c_rarg1, arg1);
143 #else
144 push(arg1);
145 #endif // _LP64
146 return call_RT(oop_result1, metadata_result, entry, 1);
147 }
148
149
150 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
151 #ifdef _LP64
152 if (c_rarg1 == arg2) {
153 if (c_rarg2 == arg1) {
154 xchgq(arg1, arg2);
155 } else {
156 mov(c_rarg2, arg2);
157 mov(c_rarg1, arg1);
158 }
159 } else {
160 mov(c_rarg1, arg1);
161 mov(c_rarg2, arg2);
162 }
163 #else
164 push(arg2);
165 push(arg1);
166 #endif // _LP64
167 return call_RT(oop_result1, metadata_result, entry, 2);
168 }
169
170
171 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
172 #ifdef _LP64
173 // if there is any conflict use the stack
174 if (arg1 == c_rarg2 || arg1 == c_rarg3 ||
175 arg2 == c_rarg1 || arg1 == c_rarg3 ||
176 arg3 == c_rarg1 || arg1 == c_rarg2) {
177 push(arg3);
178 push(arg2);
179 push(arg1);
180 pop(c_rarg1);
181 pop(c_rarg2);
182 pop(c_rarg3);
183 } else {
184 mov(c_rarg1, arg1);
185 mov(c_rarg2, arg2);
186 mov(c_rarg3, arg3);
187 }
188 #else
189 push(arg3);
190 push(arg2);
191 push(arg1);
192 #endif // _LP64
193 return call_RT(oop_result1, metadata_result, entry, 3);
194 }
195
196
197 // Implementation of StubFrame
198
199 class StubFrame: public StackObj {
200 private:
201 StubAssembler* _sasm;
202
203 public:
204 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments);
205 void load_argument(int offset_in_words, Register reg);
206
207 ~StubFrame();
208 };
209
210
211 #define __ _sasm->
212
213 StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) {
214 _sasm = sasm;
215 __ set_info(name, must_gc_arguments);
216 __ enter();
217 }
218
219 // load parameters that were stored with LIR_Assembler::store_parameter
220 // Note: offsets for store_parameter and load_argument must match
221 void StubFrame::load_argument(int offset_in_words, Register reg) {
222 // rbp, + 0: link
223 // + 1: return address
224 // + 2: argument with offset 0
225 // + 3: argument with offset 1
226 // + 4: ...
227
228 __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord));
229 }
230
231
232 StubFrame::~StubFrame() {
233 __ leave();
234 __ ret(0);
235 }
236
237 #undef __
238
239
240 // Implementation of Runtime1
241
242 #define __ sasm->
243
244 const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2;
245 const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2;
246
247 // Stack layout for saving/restoring all the registers needed during a runtime
248 // call (this includes deoptimization)
249 // Note: note that users of this frame may well have arguments to some runtime
250 // while these values are on the stack. These positions neglect those arguments
251 // but the code in save_live_registers will take the argument count into
252 // account.
253 //
254 #ifdef _LP64
255 #define SLOT2(x) x,
256 #define SLOT_PER_WORD 2
257 #else
258 #define SLOT2(x)
259 #define SLOT_PER_WORD 1
260 #endif // _LP64
261
262 enum reg_save_layout {
263 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that
264 // happen and will assert if the stack size we create is misaligned
265 #ifdef _LP64
266 align_dummy_0, align_dummy_1,
267 #endif // _LP64
268 #ifdef _WIN64
269 // Windows always allocates space for it's argument registers (see
270 // frame::arg_reg_save_area_bytes).
271 arg_reg_save_1, arg_reg_save_1H, // 0, 4
272 arg_reg_save_2, arg_reg_save_2H, // 8, 12
273 arg_reg_save_3, arg_reg_save_3H, // 16, 20
274 arg_reg_save_4, arg_reg_save_4H, // 24, 28
275 #endif // _WIN64
276 xmm_regs_as_doubles_off, // 32
277 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160
278 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224
279 // fpu_state_end_off is exclusive
280 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352
281 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356
282 extra_space_offset, // 360
283 #ifdef _LP64
284 r15_off = extra_space_offset, r15H_off, // 360, 364
285 r14_off, r14H_off, // 368, 372
286 r13_off, r13H_off, // 376, 380
287 r12_off, r12H_off, // 384, 388
288 r11_off, r11H_off, // 392, 396
289 r10_off, r10H_off, // 400, 404
290 r9_off, r9H_off, // 408, 412
291 r8_off, r8H_off, // 416, 420
292 rdi_off, rdiH_off, // 424, 428
293 #else
294 rdi_off = extra_space_offset,
295 #endif // _LP64
296 rsi_off, SLOT2(rsiH_off) // 432, 436
297 rbp_off, SLOT2(rbpH_off) // 440, 444
298 rsp_off, SLOT2(rspH_off) // 448, 452
299 rbx_off, SLOT2(rbxH_off) // 456, 460
300 rdx_off, SLOT2(rdxH_off) // 464, 468
301 rcx_off, SLOT2(rcxH_off) // 472, 476
302 rax_off, SLOT2(raxH_off) // 480, 484
303 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492
304 return_off, SLOT2(returnH_off) // 496, 500
305 reg_save_frame_size // As noted: neglects any parameters to runtime // 504
306 };
307
308
309
310 // Save off registers which might be killed by calls into the runtime.
311 // Tries to smart of about FP registers. In particular we separate
312 // saving and describing the FPU registers for deoptimization since we
313 // have to save the FPU registers twice if we describe them and on P4
314 // saving FPU registers which don't contain anything appears
315 // expensive. The deopt blob is the only thing which needs to
316 // describe FPU registers. In all other cases it should be sufficient
317 // to simply save their current value.
318
319 static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args,
320 bool save_fpu_registers = true) {
321
322 // In 64bit all the args are in regs so there are no additional stack slots
323 LP64_ONLY(num_rt_args = 0);
324 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");)
325 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread
326 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word );
327
328 // record saved value locations in an OopMap
329 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread
330 OopMap* map = new OopMap(frame_size_in_slots, 0);
331 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg());
332 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg());
333 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg());
334 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg());
335 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg());
336 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg());
337 #ifdef _LP64
338 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg());
339 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg());
340 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg());
341 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg());
342 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg());
343 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg());
344 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg());
345 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg());
346
347 // This is stupid but needed.
348 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next());
349 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next());
350 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next());
351 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next());
352 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next());
353 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next());
354
355 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next());
356 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next());
357 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next());
358 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next());
359 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next());
360 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next());
361 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next());
362 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next());
363 #endif // _LP64
364
365 if (save_fpu_registers) {
366 if (UseSSE < 2) {
367 int fpu_off = float_regs_as_doubles_off;
368 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) {
369 VMReg fpu_name_0 = FrameMap::fpu_regname(n);
370 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0);
371 // %%% This is really a waste but we'll keep things as they were for now
372 if (true) {
373 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next());
374 }
375 fpu_off += 2;
376 }
377 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots");
378 }
379
380 if (UseSSE >= 2) {
381 int xmm_off = xmm_regs_as_doubles_off;
382 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
383 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
384 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
385 // %%% This is really a waste but we'll keep things as they were for now
386 if (true) {
387 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next());
388 }
389 xmm_off += 2;
390 }
391 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
392
393 } else if (UseSSE == 1) {
394 int xmm_off = xmm_regs_as_doubles_off;
395 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) {
396 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg();
397 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0);
398 xmm_off += 2;
399 }
400 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers");
401 }
402 }
403
404 return map;
405 }
406
407 static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args,
408 bool save_fpu_registers = true) {
409 __ block_comment("save_live_registers");
410
411 __ pusha(); // integer registers
412
413 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset");
414 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset");
415
416 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
417
418 #ifdef ASSERT
419 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
420 #endif
421
422 if (save_fpu_registers) {
423 if (UseSSE < 2) {
424 // save FPU stack
425 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
426 __ fwait();
427
428 #ifdef ASSERT
429 Label ok;
430 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
431 __ jccb(Assembler::equal, ok);
432 __ stop("corrupted control word detected");
433 __ bind(ok);
434 #endif
435
436 // Reset the control word to guard against exceptions being unmasked
437 // since fstp_d can cause FPU stack underflow exceptions. Write it
438 // into the on stack copy and then reload that to make sure that the
439 // current and future values are correct.
440 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std());
441 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
442
443 // Save the FPU registers in de-opt-able form
444 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
445 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
446 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
447 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
448 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
449 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
450 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
451 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
452 }
453
454 if (UseSSE >= 2) {
455 // save XMM registers
456 // XMM registers can contain float or double values, but this is not known here,
457 // so always save them as doubles.
458 // note that float values are _not_ converted automatically, so for float values
459 // the second word contains only garbage data.
460 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
461 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
462 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
463 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
464 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
465 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
466 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
467 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
468 #ifdef _LP64
469 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64), xmm8);
470 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72), xmm9);
471 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80), xmm10);
472 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88), xmm11);
473 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96), xmm12);
474 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104), xmm13);
475 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112), xmm14);
476 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120), xmm15);
477 #endif // _LP64
478 } else if (UseSSE == 1) {
479 // save XMM registers as float because double not supported without SSE2
480 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0), xmm0);
481 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8), xmm1);
482 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16), xmm2);
483 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24), xmm3);
484 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32), xmm4);
485 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40), xmm5);
486 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48), xmm6);
487 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56), xmm7);
488 }
489 }
490
491 // FPU stack must be empty now
492 __ verify_FPU(0, "save_live_registers");
493
494 return generate_oop_map(sasm, num_rt_args, save_fpu_registers);
495 }
496
497
498 static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) {
499 if (restore_fpu_registers) {
500 if (UseSSE >= 2) {
501 // restore XMM registers
502 __ movdbl(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
503 __ movdbl(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
504 __ movdbl(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
505 __ movdbl(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
506 __ movdbl(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
507 __ movdbl(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
508 __ movdbl(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
509 __ movdbl(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
510 #ifdef _LP64
511 __ movdbl(xmm8, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 64));
512 __ movdbl(xmm9, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 72));
513 __ movdbl(xmm10, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 80));
514 __ movdbl(xmm11, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 88));
515 __ movdbl(xmm12, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 96));
516 __ movdbl(xmm13, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 104));
517 __ movdbl(xmm14, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 112));
518 __ movdbl(xmm15, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 120));
519 #endif // _LP64
520 } else if (UseSSE == 1) {
521 // restore XMM registers
522 __ movflt(xmm0, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 0));
523 __ movflt(xmm1, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 8));
524 __ movflt(xmm2, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 16));
525 __ movflt(xmm3, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 24));
526 __ movflt(xmm4, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 32));
527 __ movflt(xmm5, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 40));
528 __ movflt(xmm6, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 48));
529 __ movflt(xmm7, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + 56));
530 }
531
532 if (UseSSE < 2) {
533 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size));
534 } else {
535 // check that FPU stack is really empty
536 __ verify_FPU(0, "restore_live_registers");
537 }
538
539 } else {
540 // check that FPU stack is really empty
541 __ verify_FPU(0, "restore_live_registers");
542 }
543
544 #ifdef ASSERT
545 {
546 Label ok;
547 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef);
548 __ jcc(Assembler::equal, ok);
549 __ stop("bad offsets in frame");
550 __ bind(ok);
551 }
552 #endif // ASSERT
553
554 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size);
555 }
556
557
558 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) {
559 __ block_comment("restore_live_registers");
560
561 restore_fpu(sasm, restore_fpu_registers);
562 __ popa();
563 }
564
565
566 static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) {
567 __ block_comment("restore_live_registers_except_rax");
568
569 restore_fpu(sasm, restore_fpu_registers);
570
571 #ifdef _LP64
572 __ movptr(r15, Address(rsp, 0));
573 __ movptr(r14, Address(rsp, wordSize));
574 __ movptr(r13, Address(rsp, 2 * wordSize));
575 __ movptr(r12, Address(rsp, 3 * wordSize));
576 __ movptr(r11, Address(rsp, 4 * wordSize));
577 __ movptr(r10, Address(rsp, 5 * wordSize));
578 __ movptr(r9, Address(rsp, 6 * wordSize));
579 __ movptr(r8, Address(rsp, 7 * wordSize));
580 __ movptr(rdi, Address(rsp, 8 * wordSize));
581 __ movptr(rsi, Address(rsp, 9 * wordSize));
582 __ movptr(rbp, Address(rsp, 10 * wordSize));
583 // skip rsp
584 __ movptr(rbx, Address(rsp, 12 * wordSize));
585 __ movptr(rdx, Address(rsp, 13 * wordSize));
586 __ movptr(rcx, Address(rsp, 14 * wordSize));
587
588 __ addptr(rsp, 16 * wordSize);
589 #else
590
591 __ pop(rdi);
592 __ pop(rsi);
593 __ pop(rbp);
594 __ pop(rbx); // skip this value
595 __ pop(rbx);
596 __ pop(rdx);
597 __ pop(rcx);
598 __ addptr(rsp, BytesPerWord);
599 #endif // _LP64
600 }
601
602
603 void Runtime1::initialize_pd() {
604 // nothing to do
605 }
606
607
608 // target: the entry point of the method that creates and posts the exception oop
609 // has_argument: true if the exception needs an argument (passed on stack because registers must be preserved)
610
611 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
612 // preserve all registers
613 int num_rt_args = has_argument ? 2 : 1;
614 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
615
616 // now all registers are saved and can be used freely
617 // verify that no old value is used accidentally
618 __ invalidate_registers(true, true, true, true, true, true);
619
620 // registers used by this stub
621 const Register temp_reg = rbx;
622
623 // load argument for exception that is passed as an argument into the stub
624 if (has_argument) {
625 #ifdef _LP64
626 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord));
627 #else
628 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord));
629 __ push(temp_reg);
630 #endif // _LP64
631 }
632 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1);
633
634 OopMapSet* oop_maps = new OopMapSet();
635 oop_maps->add_gc_map(call_offset, oop_map);
636
637 __ stop("should not reach here");
638
639 return oop_maps;
640 }
641
642
643 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) {
644 __ block_comment("generate_handle_exception");
645
646 // incoming parameters
647 const Register exception_oop = rax;
648 const Register exception_pc = rdx;
649 // other registers used in this stub
650 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
651
652 // Save registers, if required.
653 OopMapSet* oop_maps = new OopMapSet();
654 OopMap* oop_map = NULL;
655 switch (id) {
656 case forward_exception_id:
657 // We're handling an exception in the context of a compiled frame.
658 // The registers have been saved in the standard places. Perform
659 // an exception lookup in the caller and dispatch to the handler
660 // if found. Otherwise unwind and dispatch to the callers
661 // exception handler.
662 oop_map = generate_oop_map(sasm, 1 /*thread*/);
663
664 // load and clear pending exception oop into RAX
665 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset()));
666 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
667
668 // load issuing PC (the return address for this stub) into rdx
669 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord));
670
671 // make sure that the vm_results are cleared (may be unnecessary)
672 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
673 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD);
674 break;
675 case handle_exception_nofpu_id:
676 case handle_exception_id:
677 // At this point all registers MAY be live.
678 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id);
679 break;
680 case handle_exception_from_callee_id: {
681 // At this point all registers except exception oop (RAX) and
682 // exception pc (RDX) are dead.
683 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord);
684 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0);
685 sasm->set_frame_size(frame_size);
686 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes));
687 break;
688 }
689 default: ShouldNotReachHere();
690 }
691
692 #ifdef TIERED
693 // C2 can leave the fpu stack dirty
694 if (UseSSE < 2) {
695 __ empty_FPU_stack();
696 }
697 #endif // TIERED
698
699 // verify that only rax, and rdx is valid at this time
700 __ invalidate_registers(false, true, true, false, true, true);
701 // verify that rax, contains a valid exception
702 __ verify_not_null_oop(exception_oop);
703
704 // load address of JavaThread object for thread-local data
705 NOT_LP64(__ get_thread(thread);)
706
707 #ifdef ASSERT
708 // check that fields in JavaThread for exception oop and issuing pc are
709 // empty before writing to them
710 Label oop_empty;
711 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD);
712 __ jcc(Assembler::equal, oop_empty);
713 __ stop("exception oop already set");
714 __ bind(oop_empty);
715
716 Label pc_empty;
717 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
718 __ jcc(Assembler::equal, pc_empty);
719 __ stop("exception pc already set");
720 __ bind(pc_empty);
721 #endif
722
723 // save exception oop and issuing pc into JavaThread
724 // (exception handler will load it from here)
725 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop);
726 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc);
727
728 // patch throwing pc into return address (has bci & oop map)
729 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc);
730
731 // compute the exception handler.
732 // the exception oop and the throwing pc are read from the fields in JavaThread
733 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
734 oop_maps->add_gc_map(call_offset, oop_map);
735
736 // rax: handler address
737 // will be the deopt blob if nmethod was deoptimized while we looked up
738 // handler regardless of whether handler existed in the nmethod.
739
740 // only rax, is valid at this time, all other registers have been destroyed by the runtime call
741 __ invalidate_registers(false, true, true, true, true, true);
742
743 // patch the return address, this stub will directly return to the exception handler
744 __ movptr(Address(rbp, 1*BytesPerWord), rax);
745
746 switch (id) {
747 case forward_exception_id:
748 case handle_exception_nofpu_id:
749 case handle_exception_id:
750 // Restore the registers that were saved at the beginning.
751 restore_live_registers(sasm, id != handle_exception_nofpu_id);
752 break;
753 case handle_exception_from_callee_id:
754 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP
755 // since we do a leave anyway.
756
757 // Pop the return address.
758 __ leave();
759 __ pop(rcx);
760 __ jmp(rcx); // jump to exception handler
761 break;
762 default: ShouldNotReachHere();
763 }
764
765 return oop_maps;
766 }
767
768
769 void Runtime1::generate_unwind_exception(StubAssembler *sasm) {
770 // incoming parameters
771 const Register exception_oop = rax;
772 // callee-saved copy of exception_oop during runtime call
773 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14);
774 // other registers used in this stub
775 const Register exception_pc = rdx;
776 const Register handler_addr = rbx;
777 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread);
778
779 // verify that only rax, is valid at this time
780 __ invalidate_registers(false, true, true, true, true, true);
781
782 #ifdef ASSERT
783 // check that fields in JavaThread for exception oop and issuing pc are empty
784 NOT_LP64(__ get_thread(thread);)
785 Label oop_empty;
786 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0);
787 __ jcc(Assembler::equal, oop_empty);
788 __ stop("exception oop must be empty");
789 __ bind(oop_empty);
790
791 Label pc_empty;
792 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0);
793 __ jcc(Assembler::equal, pc_empty);
794 __ stop("exception pc must be empty");
795 __ bind(pc_empty);
796 #endif
797
798 // clear the FPU stack in case any FPU results are left behind
799 __ empty_FPU_stack();
800
801 // save exception_oop in callee-saved register to preserve it during runtime calls
802 __ verify_not_null_oop(exception_oop);
803 __ movptr(exception_oop_callee_saved, exception_oop);
804
805 NOT_LP64(__ get_thread(thread);)
806 // Get return address (is on top of stack after leave).
807 __ movptr(exception_pc, Address(rsp, 0));
808
809 // search the exception handler address of the caller (using the return address)
810 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc);
811 // rax: exception handler address of the caller
812
813 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call.
814 __ invalidate_registers(false, true, true, true, false, true);
815
816 // move result of call into correct register
817 __ movptr(handler_addr, rax);
818
819 // Restore exception oop to RAX (required convention of exception handler).
820 __ movptr(exception_oop, exception_oop_callee_saved);
821
822 // verify that there is really a valid exception in rax
823 __ verify_not_null_oop(exception_oop);
824
825 // get throwing pc (= return address).
826 // rdx has been destroyed by the call, so it must be set again
827 // the pop is also necessary to simulate the effect of a ret(0)
828 __ pop(exception_pc);
829
830 // continue at exception handler (return address removed)
831 // note: do *not* remove arguments when unwinding the
832 // activation since the caller assumes having
833 // all arguments on the stack when entering the
834 // runtime to determine the exception handler
835 // (GC happens at call site with arguments!)
836 // rax: exception oop
837 // rdx: throwing pc
838 // rbx: exception handler
839 __ jmp(handler_addr);
840 }
841
842
843 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
844 // use the maximum number of runtime-arguments here because it is difficult to
845 // distinguish each RT-Call.
846 // Note: This number affects also the RT-Call in generate_handle_exception because
847 // the oop-map is shared for all calls.
848 const int num_rt_args = 2; // thread + dummy
849
850 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
851 assert(deopt_blob != NULL, "deoptimization blob must have been created");
852
853 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
854
855 #ifdef _LP64
856 const Register thread = r15_thread;
857 // No need to worry about dummy
858 __ mov(c_rarg0, thread);
859 #else
860 __ push(rax); // push dummy
861
862 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions)
863 // push java thread (becomes first argument of C function)
864 __ get_thread(thread);
865 __ push(thread);
866 #endif // _LP64
867 __ set_last_Java_frame(thread, noreg, rbp, NULL);
868 // do the call
869 __ call(RuntimeAddress(target));
870 OopMapSet* oop_maps = new OopMapSet();
871 oop_maps->add_gc_map(__ offset(), oop_map);
872 // verify callee-saved register
873 #ifdef ASSERT
874 guarantee(thread != rax, "change this code");
875 __ push(rax);
876 { Label L;
877 __ get_thread(rax);
878 __ cmpptr(thread, rax);
879 __ jcc(Assembler::equal, L);
880 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?");
881 __ bind(L);
882 }
883 __ pop(rax);
884 #endif
885 __ reset_last_Java_frame(thread, true, false);
886 #ifndef _LP64
887 __ pop(rcx); // discard thread arg
888 __ pop(rcx); // discard dummy
889 #endif // _LP64
890
891 // check for pending exceptions
892 { Label L;
893 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD);
894 __ jcc(Assembler::equal, L);
895 // exception pending => remove activation and forward to exception handler
896
897 __ testptr(rax, rax); // have we deoptimized?
898 __ jump_cc(Assembler::equal,
899 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id)));
900
901 // the deopt blob expects exceptions in the special fields of
902 // JavaThread, so copy and clear pending exception.
903
904 // load and clear pending exception
905 __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
906 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD);
907
908 // check that there is really a valid exception
909 __ verify_not_null_oop(rax);
910
911 // load throwing pc: this is the return address of the stub
912 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size));
913
914 #ifdef ASSERT
915 // check that fields in JavaThread for exception oop and issuing pc are empty
916 Label oop_empty;
917 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD);
918 __ jcc(Assembler::equal, oop_empty);
919 __ stop("exception oop must be empty");
920 __ bind(oop_empty);
921
922 Label pc_empty;
923 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD);
924 __ jcc(Assembler::equal, pc_empty);
925 __ stop("exception pc must be empty");
926 __ bind(pc_empty);
927 #endif
928
929 // store exception oop and throwing pc to JavaThread
930 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax);
931 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx);
932
933 restore_live_registers(sasm);
934
935 __ leave();
936 __ addptr(rsp, BytesPerWord); // remove return address from stack
937
938 // Forward the exception directly to deopt blob. We can blow no
939 // registers and must leave throwing pc on the stack. A patch may
940 // have values live in registers so the entry point with the
941 // exception in tls.
942 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls()));
943
944 __ bind(L);
945 }
946
947
948 // Runtime will return true if the nmethod has been deoptimized during
949 // the patching process. In that case we must do a deopt reexecute instead.
950
951 Label reexecuteEntry, cont;
952
953 __ testptr(rax, rax); // have we deoptimized?
954 __ jcc(Assembler::equal, cont); // no
955
956 // Will reexecute. Proper return address is already on the stack we just restore
957 // registers, pop all of our frame but the return address and jump to the deopt blob
958 restore_live_registers(sasm);
959 __ leave();
960 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
961
962 __ bind(cont);
963 restore_live_registers(sasm);
964 __ leave();
965 __ ret(0);
966
967 return oop_maps;
968 }
969
970
971 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
972
973 // for better readability
974 const bool must_gc_arguments = true;
975 const bool dont_gc_arguments = false;
976
977 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu
978 bool save_fpu_registers = true;
979
980 // stub code & info for the different stubs
981 OopMapSet* oop_maps = NULL;
982 switch (id) {
983 case forward_exception_id:
984 {
985 oop_maps = generate_handle_exception(id, sasm);
986 __ leave();
987 __ ret(0);
988 }
989 break;
990
991 case new_instance_id:
992 case fast_new_instance_id:
993 case fast_new_instance_init_check_id:
994 {
995 Register klass = rdx; // Incoming
996 Register obj = rax; // Result
997
998 if (id == new_instance_id) {
999 __ set_info("new_instance", dont_gc_arguments);
1000 } else if (id == fast_new_instance_id) {
1001 __ set_info("fast new_instance", dont_gc_arguments);
1002 } else {
1003 assert(id == fast_new_instance_init_check_id, "bad StubID");
1004 __ set_info("fast new_instance init check", dont_gc_arguments);
1005 }
1006
1007 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) &&
1008 UseTLAB && FastTLABRefill) {
1009 Label slow_path;
1010 Register obj_size = rcx;
1011 Register t1 = rbx;
1012 Register t2 = rsi;
1013 assert_different_registers(klass, obj, obj_size, t1, t2);
1014
1015 __ push(rdi);
1016 __ push(rbx);
1017
1018 if (id == fast_new_instance_init_check_id) {
1019 // make sure the klass is initialized
1020 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
1021 __ jcc(Assembler::notEqual, slow_path);
1022 }
1023
1024 #ifdef ASSERT
1025 // assert object can be fast path allocated
1026 {
1027 Label ok, not_ok;
1028 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1029 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0)
1030 __ jcc(Assembler::lessEqual, not_ok);
1031 __ testl(obj_size, Klass::_lh_instance_slow_path_bit);
1032 __ jcc(Assembler::zero, ok);
1033 __ bind(not_ok);
1034 __ stop("assert(can be fast path allocated)");
1035 __ should_not_reach_here();
1036 __ bind(ok);
1037 }
1038 #endif // ASSERT
1039
1040 // if we got here then the TLAB allocation failed, so try
1041 // refilling the TLAB or allocating directly from eden.
1042 Label retry_tlab, try_eden;
1043 const Register thread =
1044 __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy rdx (klass), returns rdi
1045
1046 __ bind(retry_tlab);
1047
1048 // get the instance size (size is postive so movl is fine for 64bit)
1049 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1050
1051 __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path);
1052
1053 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1054 __ verify_oop(obj);
1055 __ pop(rbx);
1056 __ pop(rdi);
1057 __ ret(0);
1058
1059 __ bind(try_eden);
1060 // get the instance size (size is postive so movl is fine for 64bit)
1061 __ movl(obj_size, Address(klass, Klass::layout_helper_offset()));
1062
1063 __ eden_allocate(obj, obj_size, 0, t1, slow_path);
1064 __ incr_allocated_bytes(thread, obj_size, 0);
1065
1066 __ initialize_object(obj, klass, obj_size, 0, t1, t2);
1067 __ verify_oop(obj);
1068 __ pop(rbx);
1069 __ pop(rdi);
1070 __ ret(0);
1071
1072 __ bind(slow_path);
1073 __ pop(rbx);
1074 __ pop(rdi);
1075 }
1076
1077 __ enter();
1078 OopMap* map = save_live_registers(sasm, 2);
1079 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
1080 oop_maps = new OopMapSet();
1081 oop_maps->add_gc_map(call_offset, map);
1082 restore_live_registers_except_rax(sasm);
1083 __ verify_oop(obj);
1084 __ leave();
1085 __ ret(0);
1086
1087 // rax,: new instance
1088 }
1089
1090 break;
1091
1092 case counter_overflow_id:
1093 {
1094 Register bci = rax, method = rbx;
1095 __ enter();
1096 OopMap* map = save_live_registers(sasm, 3);
1097 // Retrieve bci
1098 __ movl(bci, Address(rbp, 2*BytesPerWord));
1099 // And a pointer to the Method*
1100 __ movptr(method, Address(rbp, 3*BytesPerWord));
1101 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method);
1102 oop_maps = new OopMapSet();
1103 oop_maps->add_gc_map(call_offset, map);
1104 restore_live_registers(sasm);
1105 __ leave();
1106 __ ret(0);
1107 }
1108 break;
1109
1110 case new_type_array_id:
1111 case new_object_array_id:
1112 {
1113 Register length = rbx; // Incoming
1114 Register klass = rdx; // Incoming
1115 Register obj = rax; // Result
1116
1117 if (id == new_type_array_id) {
1118 __ set_info("new_type_array", dont_gc_arguments);
1119 } else {
1120 __ set_info("new_object_array", dont_gc_arguments);
1121 }
1122
1123 #ifdef ASSERT
1124 // assert object type is really an array of the proper kind
1125 {
1126 Label ok;
1127 Register t0 = obj;
1128 __ movl(t0, Address(klass, Klass::layout_helper_offset()));
1129 __ sarl(t0, Klass::_lh_array_tag_shift);
1130 int tag = ((id == new_type_array_id)
1131 ? Klass::_lh_array_tag_type_value
1132 : Klass::_lh_array_tag_obj_value);
1133 __ cmpl(t0, tag);
1134 __ jcc(Assembler::equal, ok);
1135 __ stop("assert(is an array klass)");
1136 __ should_not_reach_here();
1137 __ bind(ok);
1138 }
1139 #endif // ASSERT
1140
1141 if (UseTLAB && FastTLABRefill) {
1142 Register arr_size = rsi;
1143 Register t1 = rcx; // must be rcx for use as shift count
1144 Register t2 = rdi;
1145 Label slow_path;
1146 assert_different_registers(length, klass, obj, arr_size, t1, t2);
1147
1148 // check that array length is small enough for fast path.
1149 __ cmpl(length, C1_MacroAssembler::max_array_allocation_length);
1150 __ jcc(Assembler::above, slow_path);
1151
1152 // if we got here then the TLAB allocation failed, so try
1153 // refilling the TLAB or allocating directly from eden.
1154 Label retry_tlab, try_eden;
1155 const Register thread =
1156 __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves rbx & rdx, returns rdi
1157
1158 __ bind(retry_tlab);
1159
1160 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1161 // since size is positive movl does right thing on 64bit
1162 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1163 // since size is postive movl does right thing on 64bit
1164 __ movl(arr_size, length);
1165 assert(t1 == rcx, "fixed register usage");
1166 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1167 __ shrptr(t1, Klass::_lh_header_size_shift);
1168 __ andptr(t1, Klass::_lh_header_size_mask);
1169 __ addptr(arr_size, t1);
1170 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1171 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1172
1173 __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size
1174
1175 __ initialize_header(obj, klass, length, t1, t2);
1176 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1177 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1178 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1179 __ andptr(t1, Klass::_lh_header_size_mask);
1180 __ subptr(arr_size, t1); // body length
1181 __ addptr(t1, obj); // body start
1182 __ initialize_body(t1, arr_size, 0, t2);
1183 __ verify_oop(obj);
1184 __ ret(0);
1185
1186 __ bind(try_eden);
1187 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F))
1188 // since size is positive movl does right thing on 64bit
1189 __ movl(t1, Address(klass, Klass::layout_helper_offset()));
1190 // since size is postive movl does right thing on 64bit
1191 __ movl(arr_size, length);
1192 assert(t1 == rcx, "fixed register usage");
1193 __ shlptr(arr_size /* by t1=rcx, mod 32 */);
1194 __ shrptr(t1, Klass::_lh_header_size_shift);
1195 __ andptr(t1, Klass::_lh_header_size_mask);
1196 __ addptr(arr_size, t1);
1197 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up
1198 __ andptr(arr_size, ~MinObjAlignmentInBytesMask);
1199
1200 __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size
1201 __ incr_allocated_bytes(thread, arr_size, 0);
1202
1203 __ initialize_header(obj, klass, length, t1, t2);
1204 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte)));
1205 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise");
1206 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise");
1207 __ andptr(t1, Klass::_lh_header_size_mask);
1208 __ subptr(arr_size, t1); // body length
1209 __ addptr(t1, obj); // body start
1210 __ initialize_body(t1, arr_size, 0, t2);
1211 __ verify_oop(obj);
1212 __ ret(0);
1213
1214 __ bind(slow_path);
1215 }
1216
1217 __ enter();
1218 OopMap* map = save_live_registers(sasm, 3);
1219 int call_offset;
1220 if (id == new_type_array_id) {
1221 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
1222 } else {
1223 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
1224 }
1225
1226 oop_maps = new OopMapSet();
1227 oop_maps->add_gc_map(call_offset, map);
1228 restore_live_registers_except_rax(sasm);
1229
1230 __ verify_oop(obj);
1231 __ leave();
1232 __ ret(0);
1233
1234 // rax,: new array
1235 }
1236 break;
1237
1238 case new_multi_array_id:
1239 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments);
1240 // rax,: klass
1241 // rbx,: rank
1242 // rcx: address of 1st dimension
1243 OopMap* map = save_live_registers(sasm, 4);
1244 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx);
1245
1246 oop_maps = new OopMapSet();
1247 oop_maps->add_gc_map(call_offset, map);
1248 restore_live_registers_except_rax(sasm);
1249
1250 // rax,: new multi array
1251 __ verify_oop(rax);
1252 }
1253 break;
1254
1255 case register_finalizer_id:
1256 {
1257 __ set_info("register_finalizer", dont_gc_arguments);
1258
1259 // This is called via call_runtime so the arguments
1260 // will be place in C abi locations
1261
1262 #ifdef _LP64
1263 __ verify_oop(c_rarg0);
1264 __ mov(rax, c_rarg0);
1265 #else
1266 // The object is passed on the stack and we haven't pushed a
1267 // frame yet so it's one work away from top of stack.
1268 __ movptr(rax, Address(rsp, 1 * BytesPerWord));
1269 __ verify_oop(rax);
1270 #endif // _LP64
1271
1272 // load the klass and check the has finalizer flag
1273 Label register_finalizer;
1274 Register t = rsi;
1275 __ load_klass(t, rax);
1276 __ movl(t, Address(t, Klass::access_flags_offset()));
1277 __ testl(t, JVM_ACC_HAS_FINALIZER);
1278 __ jcc(Assembler::notZero, register_finalizer);
1279 __ ret(0);
1280
1281 __ bind(register_finalizer);
1282 __ enter();
1283 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */);
1284 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax);
1285 oop_maps = new OopMapSet();
1286 oop_maps->add_gc_map(call_offset, oop_map);
1287
1288 // Now restore all the live registers
1289 restore_live_registers(sasm);
1290
1291 __ leave();
1292 __ ret(0);
1293 }
1294 break;
1295
1296 case throw_range_check_failed_id:
1297 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments);
1298 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
1299 }
1300 break;
1301
1302 case throw_index_exception_id:
1303 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments);
1304 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
1305 }
1306 break;
1307
1308 case throw_div0_exception_id:
1309 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments);
1310 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
1311 }
1312 break;
1313
1314 case throw_null_pointer_exception_id:
1315 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments);
1316 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
1317 }
1318 break;
1319
1320 case handle_exception_nofpu_id:
1321 case handle_exception_id:
1322 { StubFrame f(sasm, "handle_exception", dont_gc_arguments);
1323 oop_maps = generate_handle_exception(id, sasm);
1324 }
1325 break;
1326
1327 case handle_exception_from_callee_id:
1328 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments);
1329 oop_maps = generate_handle_exception(id, sasm);
1330 }
1331 break;
1332
1333 case unwind_exception_id:
1334 { __ set_info("unwind_exception", dont_gc_arguments);
1335 // note: no stubframe since we are about to leave the current
1336 // activation and we are calling a leaf VM function only.
1337 generate_unwind_exception(sasm);
1338 }
1339 break;
1340
1341 case throw_array_store_exception_id:
1342 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments);
1343 // tos + 0: link
1344 // + 1: return address
1345 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1346 }
1347 break;
1348
1349 case throw_class_cast_exception_id:
1350 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments);
1351 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1352 }
1353 break;
1354
1355 case throw_incompatible_class_change_error_id:
1356 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments);
1357 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1358 }
1359 break;
1360
1361 case slow_subtype_check_id:
1362 {
1363 // Typical calling sequence:
1364 // __ push(klass_RInfo); // object klass or other subclass
1365 // __ push(sup_k_RInfo); // array element klass or other superclass
1366 // __ call(slow_subtype_check);
1367 // Note that the subclass is pushed first, and is therefore deepest.
1368 // Previous versions of this code reversed the names 'sub' and 'super'.
1369 // This was operationally harmless but made the code unreadable.
1370 enum layout {
1371 rax_off, SLOT2(raxH_off)
1372 rcx_off, SLOT2(rcxH_off)
1373 rsi_off, SLOT2(rsiH_off)
1374 rdi_off, SLOT2(rdiH_off)
1375 // saved_rbp_off, SLOT2(saved_rbpH_off)
1376 return_off, SLOT2(returnH_off)
1377 sup_k_off, SLOT2(sup_kH_off)
1378 klass_off, SLOT2(superH_off)
1379 framesize,
1380 result_off = klass_off // deepest argument is also the return value
1381 };
1382
1383 __ set_info("slow_subtype_check", dont_gc_arguments);
1384 __ push(rdi);
1385 __ push(rsi);
1386 __ push(rcx);
1387 __ push(rax);
1388
1389 // This is called by pushing args and not with C abi
1390 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass
1391 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass
1392
1393 Label miss;
1394 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss);
1395
1396 // fallthrough on success:
1397 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result
1398 __ pop(rax);
1399 __ pop(rcx);
1400 __ pop(rsi);
1401 __ pop(rdi);
1402 __ ret(0);
1403
1404 __ bind(miss);
1405 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result
1406 __ pop(rax);
1407 __ pop(rcx);
1408 __ pop(rsi);
1409 __ pop(rdi);
1410 __ ret(0);
1411 }
1412 break;
1413
1414 case monitorenter_nofpu_id:
1415 save_fpu_registers = false;
1416 // fall through
1417 case monitorenter_id:
1418 {
1419 StubFrame f(sasm, "monitorenter", dont_gc_arguments);
1420 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers);
1421
1422 // Called with store_parameter and not C abi
1423
1424 f.load_argument(1, rax); // rax,: object
1425 f.load_argument(0, rbx); // rbx,: lock address
1426
1427 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx);
1428
1429 oop_maps = new OopMapSet();
1430 oop_maps->add_gc_map(call_offset, map);
1431 restore_live_registers(sasm, save_fpu_registers);
1432 }
1433 break;
1434
1435 case monitorexit_nofpu_id:
1436 save_fpu_registers = false;
1437 // fall through
1438 case monitorexit_id:
1439 {
1440 StubFrame f(sasm, "monitorexit", dont_gc_arguments);
1441 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers);
1442
1443 // Called with store_parameter and not C abi
1444
1445 f.load_argument(0, rax); // rax,: lock address
1446
1447 // note: really a leaf routine but must setup last java sp
1448 // => use call_RT for now (speed can be improved by
1449 // doing last java sp setup manually)
1450 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax);
1451
1452 oop_maps = new OopMapSet();
1453 oop_maps->add_gc_map(call_offset, map);
1454 restore_live_registers(sasm, save_fpu_registers);
1455 }
1456 break;
1457
1458 case deoptimize_id:
1459 {
1460 StubFrame f(sasm, "deoptimize", dont_gc_arguments);
1461 const int num_rt_args = 1; // thread
1462 OopMap* oop_map = save_live_registers(sasm, num_rt_args);
1463 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize));
1464 oop_maps = new OopMapSet();
1465 oop_maps->add_gc_map(call_offset, oop_map);
1466 restore_live_registers(sasm);
1467 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1468 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1469 __ leave();
1470 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1471 }
1472 break;
1473
1474 case access_field_patching_id:
1475 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments);
1476 // we should set up register map
1477 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1478 }
1479 break;
1480
1481 case load_klass_patching_id:
1482 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments);
1483 // we should set up register map
1484 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1485 }
1486 break;
1487
1488 case load_mirror_patching_id:
1489 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments);
1490 // we should set up register map
1491 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1492 }
1493 break;
1494
1495 case load_appendix_patching_id:
1496 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments);
1497 // we should set up register map
1498 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1499 }
1500 break;
1501
1502 case dtrace_object_alloc_id:
1503 { // rax,: object
1504 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments);
1505 // we can't gc here so skip the oopmap but make sure that all
1506 // the live registers get saved.
1507 save_live_registers(sasm, 1);
1508
1509 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax));
1510 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc)));
1511 NOT_LP64(__ pop(rax));
1512
1513 restore_live_registers(sasm);
1514 }
1515 break;
1516
1517 case fpu2long_stub_id:
1518 {
1519 // rax, and rdx are destroyed, but should be free since the result is returned there
1520 // preserve rsi,ecx
1521 __ push(rsi);
1522 __ push(rcx);
1523 LP64_ONLY(__ push(rdx);)
1524
1525 // check for NaN
1526 Label return0, do_return, return_min_jlong, do_convert;
1527
1528 Address value_high_word(rsp, wordSize + 4);
1529 Address value_low_word(rsp, wordSize);
1530 Address result_high_word(rsp, 3*wordSize + 4);
1531 Address result_low_word(rsp, 3*wordSize);
1532
1533 __ subptr(rsp, 32); // more than enough on 32bit
1534 __ fst_d(value_low_word);
1535 __ movl(rax, value_high_word);
1536 __ andl(rax, 0x7ff00000);
1537 __ cmpl(rax, 0x7ff00000);
1538 __ jcc(Assembler::notEqual, do_convert);
1539 __ movl(rax, value_high_word);
1540 __ andl(rax, 0xfffff);
1541 __ orl(rax, value_low_word);
1542 __ jcc(Assembler::notZero, return0);
1543
1544 __ bind(do_convert);
1545 __ fnstcw(Address(rsp, 0));
1546 __ movzwl(rax, Address(rsp, 0));
1547 __ orl(rax, 0xc00);
1548 __ movw(Address(rsp, 2), rax);
1549 __ fldcw(Address(rsp, 2));
1550 __ fwait();
1551 __ fistp_d(result_low_word);
1552 __ fldcw(Address(rsp, 0));
1553 __ fwait();
1554 // This gets the entire long in rax on 64bit
1555 __ movptr(rax, result_low_word);
1556 // testing of high bits
1557 __ movl(rdx, result_high_word);
1558 __ mov(rcx, rax);
1559 // What the heck is the point of the next instruction???
1560 __ xorl(rcx, 0x0);
1561 __ movl(rsi, 0x80000000);
1562 __ xorl(rsi, rdx);
1563 __ orl(rcx, rsi);
1564 __ jcc(Assembler::notEqual, do_return);
1565 __ fldz();
1566 __ fcomp_d(value_low_word);
1567 __ fnstsw_ax();
1568 #ifdef _LP64
1569 __ testl(rax, 0x4100); // ZF & CF == 0
1570 __ jcc(Assembler::equal, return_min_jlong);
1571 #else
1572 __ sahf();
1573 __ jcc(Assembler::above, return_min_jlong);
1574 #endif // _LP64
1575 // return max_jlong
1576 #ifndef _LP64
1577 __ movl(rdx, 0x7fffffff);
1578 __ movl(rax, 0xffffffff);
1579 #else
1580 __ mov64(rax, CONST64(0x7fffffffffffffff));
1581 #endif // _LP64
1582 __ jmp(do_return);
1583
1584 __ bind(return_min_jlong);
1585 #ifndef _LP64
1586 __ movl(rdx, 0x80000000);
1587 __ xorl(rax, rax);
1588 #else
1589 __ mov64(rax, CONST64(0x8000000000000000));
1590 #endif // _LP64
1591 __ jmp(do_return);
1592
1593 __ bind(return0);
1594 __ fpop();
1595 #ifndef _LP64
1596 __ xorptr(rdx,rdx);
1597 __ xorptr(rax,rax);
1598 #else
1599 __ xorptr(rax, rax);
1600 #endif // _LP64
1601
1602 __ bind(do_return);
1603 __ addptr(rsp, 32);
1604 LP64_ONLY(__ pop(rdx);)
1605 __ pop(rcx);
1606 __ pop(rsi);
1607 __ ret(0);
1608 }
1609 break;
1610
1611 #if INCLUDE_ALL_GCS
1612 case g1_pre_barrier_slow_id:
1613 {
1614 StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments);
1615 // arg0 : previous value of memory
1616
1617 BarrierSet* bs = Universe::heap()->barrier_set();
1618 if (bs->kind() != BarrierSet::G1SATBCTLogging) {
1619 __ movptr(rax, (int)id);
1620 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1621 __ should_not_reach_here();
1622 break;
1623 }
1624 __ push(rax);
1625 __ push(rdx);
1626
1627 const Register pre_val = rax;
1628 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1629 const Register tmp = rdx;
1630
1631 NOT_LP64(__ get_thread(thread);)
1632
1633 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1634 PtrQueue::byte_offset_of_active()));
1635
1636 Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1637 PtrQueue::byte_offset_of_index()));
1638 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
1639 PtrQueue::byte_offset_of_buf()));
1640
1641
1642 Label done;
1643 Label runtime;
1644
1645 // Can we store original value in the thread's buffer?
1646
1647 #ifdef _LP64
1648 __ movslq(tmp, queue_index);
1649 __ cmpq(tmp, 0);
1650 #else
1651 __ cmpl(queue_index, 0);
1652 #endif
1653 __ jcc(Assembler::equal, runtime);
1654 #ifdef _LP64
1655 __ subq(tmp, wordSize);
1656 __ movl(queue_index, tmp);
1657 __ addq(tmp, buffer);
1658 #else
1659 __ subl(queue_index, wordSize);
1660 __ movl(tmp, buffer);
1661 __ addl(tmp, queue_index);
1662 #endif
1663
1664 // prev_val (rax)
1665 f.load_argument(0, pre_val);
1666 __ movptr(Address(tmp, 0), pre_val);
1667 __ jmp(done);
1668
1669 __ bind(runtime);
1670 __ push(rcx);
1671 #ifdef _LP64
1672 __ push(r8);
1673 __ push(r9);
1674 __ push(r10);
1675 __ push(r11);
1676 # ifndef _WIN64
1677 __ push(rdi);
1678 __ push(rsi);
1679 # endif
1680 #endif
1681 // load the pre-value
1682 f.load_argument(0, rcx);
1683 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread);
1684 #ifdef _LP64
1685 # ifndef _WIN64
1686 __ pop(rsi);
1687 __ pop(rdi);
1688 # endif
1689 __ pop(r11);
1690 __ pop(r10);
1691 __ pop(r9);
1692 __ pop(r8);
1693 #endif
1694 __ pop(rcx);
1695 __ bind(done);
1696
1697 __ pop(rdx);
1698 __ pop(rax);
1699 }
1700 break;
1701
1702 case g1_post_barrier_slow_id:
1703 {
1704 StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments);
1705
1706
1707 // arg0: store_address
1708 Address store_addr(rbp, 2*BytesPerWord);
1709
1710 BarrierSet* bs = Universe::heap()->barrier_set();
1711 CardTableModRefBS* ct = (CardTableModRefBS*)bs;
1712 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
1713
1714 Label done;
1715 Label runtime;
1716
1717 // At this point we know new_value is non-NULL and the new_value crosses regions.
1718 // Must check to see if card is already dirty
1719
1720 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread);
1721
1722 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1723 PtrQueue::byte_offset_of_index()));
1724 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
1725 PtrQueue::byte_offset_of_buf()));
1726
1727 __ push(rax);
1728 __ push(rcx);
1729
1730 const Register cardtable = rax;
1731 const Register card_addr = rcx;
1732
1733 f.load_argument(0, card_addr);
1734 __ shrptr(card_addr, CardTableModRefBS::card_shift);
1735 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
1736 // a valid address and therefore is not properly handled by the relocation code.
1737 __ movptr(cardtable, (intptr_t)ct->byte_map_base);
1738 __ addptr(card_addr, cardtable);
1739
1740 NOT_LP64(__ get_thread(thread);)
1741
1742 __ cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
1743 __ jcc(Assembler::equal, done);
1744
1745 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
1746 __ cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1747 __ jcc(Assembler::equal, done);
1748
1749 // storing region crossing non-NULL, card is clean.
1750 // dirty card and log.
1751
1752 __ movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
1753
1754 __ cmpl(queue_index, 0);
1755 __ jcc(Assembler::equal, runtime);
1756 __ subl(queue_index, wordSize);
1757
1758 const Register buffer_addr = rbx;
1759 __ push(rbx);
1760
1761 __ movptr(buffer_addr, buffer);
1762
1763 #ifdef _LP64
1764 __ movslq(rscratch1, queue_index);
1765 __ addptr(buffer_addr, rscratch1);
1766 #else
1767 __ addptr(buffer_addr, queue_index);
1768 #endif
1769 __ movptr(Address(buffer_addr, 0), card_addr);
1770
1771 __ pop(rbx);
1772 __ jmp(done);
1773
1774 __ bind(runtime);
1775 __ push(rdx);
1776 #ifdef _LP64
1777 __ push(r8);
1778 __ push(r9);
1779 __ push(r10);
1780 __ push(r11);
1781 # ifndef _WIN64
1782 __ push(rdi);
1783 __ push(rsi);
1784 # endif
1785 #endif
1786 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
1787 #ifdef _LP64
1788 # ifndef _WIN64
1789 __ pop(rsi);
1790 __ pop(rdi);
1791 # endif
1792 __ pop(r11);
1793 __ pop(r10);
1794 __ pop(r9);
1795 __ pop(r8);
1796 #endif
1797 __ pop(rdx);
1798 __ bind(done);
1799
1800 __ pop(rcx);
1801 __ pop(rax);
1802
1803 }
1804 break;
1805 #endif // INCLUDE_ALL_GCS
1806
1807 case predicate_failed_trap_id:
1808 {
1809 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments);
1810
1811 OopMap* map = save_live_registers(sasm, 1);
1812
1813 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1814 oop_maps = new OopMapSet();
1815 oop_maps->add_gc_map(call_offset, map);
1816 restore_live_registers(sasm);
1817 __ leave();
1818 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1819 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1820
1821 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution()));
1822 }
1823 break;
1824
1825 default:
1826 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments);
1827 __ movptr(rax, (int)id);
1828 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax);
1829 __ should_not_reach_here();
1830 }
1831 break;
1832 }
1833 return oop_maps;
1834 }
1835
1836 #undef __
1837
1838 const char *Runtime1::pd_name_for_address(address entry) {
1839 return "<unknown function>";
1840 }