1 //
2 // Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, [rsp + #%d]\t# Save the caller's SP into rbp", (framesize + wordSize));
867 }
868 }
869
870 if (VerifyStackAtCalls) {
871 st->print("\n\t");
872 framesize -= wordSize;
873 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
874 #ifdef ASSERT
875 st->print("\n\t");
876 st->print("# stack alignment check");
877 #endif
878 }
879 st->cr();
880 }
881 #endif
882
883 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
884 Compile* C = ra_->C;
885 MacroAssembler _masm(&cbuf);
886
887 int framesize = C->frame_size_in_bytes();
888 int bangsize = C->bang_size_in_bytes();
889
890 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
891
892 C->set_frame_complete(cbuf.insts_size());
893
894 if (C->has_mach_constant_base_node()) {
895 // NOTE: We set the table base offset here because users might be
896 // emitted before MachConstantBaseNode.
897 Compile::ConstantTable& constant_table = C->constant_table();
898 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
899 }
900 }
901
902 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
903 {
904 return MachNode::size(ra_); // too many variables; just compute it
905 // the hard way
906 }
907
908 int MachPrologNode::reloc() const
909 {
910 return 0; // a large enough number
911 }
912
913 //=============================================================================
914 #ifndef PRODUCT
915 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
916 {
917 Compile* C = ra_->C;
918 if (C->max_vector_size() > 16) {
919 st->print("vzeroupper");
920 st->cr(); st->print("\t");
921 }
922
923 int framesize = C->frame_size_in_bytes();
924 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
925 // Remove word for return adr already pushed
926 // and RBP
927 framesize -= 2*wordSize;
928
929 if (framesize) {
930 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
931 st->print("\t");
932 }
933
934 st->print_cr("popq rbp");
935 if (do_polling() && C->is_method_compilation()) {
936 st->print("\t");
937 if (Assembler::is_polling_page_far()) {
938 st->print_cr("movq rscratch1, #polling_page_address\n\t"
939 "testl rax, [rscratch1]\t"
940 "# Safepoint: poll for GC");
941 } else {
942 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
943 "# Safepoint: poll for GC");
944 }
945 }
946 }
947 #endif
948
949 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
950 {
951 Compile* C = ra_->C;
952 if (C->max_vector_size() > 16) {
953 // Clear upper bits of YMM registers when current compiled code uses
954 // wide vectors to avoid AVX <-> SSE transition penalty during call.
955 MacroAssembler _masm(&cbuf);
956 __ vzeroupper();
957 }
958
959 int framesize = C->frame_size_in_bytes();
960 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
961 // Remove word for return adr already pushed
962 // and RBP
963 framesize -= 2*wordSize;
964
965 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
966
967 if (framesize) {
968 emit_opcode(cbuf, Assembler::REX_W);
969 if (framesize < 0x80) {
970 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
971 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
972 emit_d8(cbuf, framesize);
973 } else {
974 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
975 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
976 emit_d32(cbuf, framesize);
977 }
978 }
979
980 // popq rbp
981 emit_opcode(cbuf, 0x58 | RBP_enc);
982
983 if (do_polling() && C->is_method_compilation()) {
984 MacroAssembler _masm(&cbuf);
985 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
986 if (Assembler::is_polling_page_far()) {
987 __ lea(rscratch1, polling_page);
988 __ relocate(relocInfo::poll_return_type);
989 __ testl(rax, Address(rscratch1, 0));
990 } else {
991 __ testl(rax, polling_page);
992 }
993 }
994 }
995
996 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
997 {
998 return MachNode::size(ra_); // too many variables; just compute it
999 // the hard way
1000 }
1001
1002 int MachEpilogNode::reloc() const
1003 {
1004 return 2; // a large enough number
1005 }
1006
1007 const Pipeline* MachEpilogNode::pipeline() const
1008 {
1009 return MachNode::pipeline_class();
1010 }
1011
1012 int MachEpilogNode::safepoint_offset() const
1013 {
1014 return 0;
1015 }
1016
1017 //=============================================================================
1018
1019 enum RC {
1020 rc_bad,
1021 rc_int,
1022 rc_float,
1023 rc_stack
1024 };
1025
1026 static enum RC rc_class(OptoReg::Name reg)
1027 {
1028 if( !OptoReg::is_valid(reg) ) return rc_bad;
1029
1030 if (OptoReg::is_stack(reg)) return rc_stack;
1031
1032 VMReg r = OptoReg::as_VMReg(reg);
1033
1034 if (r->is_Register()) return rc_int;
1035
1036 assert(r->is_XMMRegister(), "must be");
1037 return rc_float;
1038 }
1039
1040 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1041 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1042 int src_hi, int dst_hi, uint ireg, outputStream* st);
1043
1044 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1045 int stack_offset, int reg, uint ireg, outputStream* st);
1046
1047 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1048 int dst_offset, uint ireg, outputStream* st) {
1049 if (cbuf) {
1050 MacroAssembler _masm(cbuf);
1051 switch (ireg) {
1052 case Op_VecS:
1053 __ movq(Address(rsp, -8), rax);
1054 __ movl(rax, Address(rsp, src_offset));
1055 __ movl(Address(rsp, dst_offset), rax);
1056 __ movq(rax, Address(rsp, -8));
1057 break;
1058 case Op_VecD:
1059 __ pushq(Address(rsp, src_offset));
1060 __ popq (Address(rsp, dst_offset));
1061 break;
1062 case Op_VecX:
1063 __ pushq(Address(rsp, src_offset));
1064 __ popq (Address(rsp, dst_offset));
1065 __ pushq(Address(rsp, src_offset+8));
1066 __ popq (Address(rsp, dst_offset+8));
1067 break;
1068 case Op_VecY:
1069 __ vmovdqu(Address(rsp, -32), xmm0);
1070 __ vmovdqu(xmm0, Address(rsp, src_offset));
1071 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1072 __ vmovdqu(xmm0, Address(rsp, -32));
1073 break;
1074 default:
1075 ShouldNotReachHere();
1076 }
1077 #ifndef PRODUCT
1078 } else {
1079 switch (ireg) {
1080 case Op_VecS:
1081 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1082 "movl rax, [rsp + #%d]\n\t"
1083 "movl [rsp + #%d], rax\n\t"
1084 "movq rax, [rsp - #8]",
1085 src_offset, dst_offset);
1086 break;
1087 case Op_VecD:
1088 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1089 "popq [rsp + #%d]",
1090 src_offset, dst_offset);
1091 break;
1092 case Op_VecX:
1093 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1094 "popq [rsp + #%d]\n\t"
1095 "pushq [rsp + #%d]\n\t"
1096 "popq [rsp + #%d]",
1097 src_offset, dst_offset, src_offset+8, dst_offset+8);
1098 break;
1099 case Op_VecY:
1100 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1101 "vmovdqu xmm0, [rsp + #%d]\n\t"
1102 "vmovdqu [rsp + #%d], xmm0\n\t"
1103 "vmovdqu xmm0, [rsp - #32]",
1104 src_offset, dst_offset);
1105 break;
1106 default:
1107 ShouldNotReachHere();
1108 }
1109 #endif
1110 }
1111 }
1112
1113 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1114 PhaseRegAlloc* ra_,
1115 bool do_size,
1116 outputStream* st) const {
1117 assert(cbuf != NULL || st != NULL, "sanity");
1118 // Get registers to move
1119 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1120 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1121 OptoReg::Name dst_second = ra_->get_reg_second(this);
1122 OptoReg::Name dst_first = ra_->get_reg_first(this);
1123
1124 enum RC src_second_rc = rc_class(src_second);
1125 enum RC src_first_rc = rc_class(src_first);
1126 enum RC dst_second_rc = rc_class(dst_second);
1127 enum RC dst_first_rc = rc_class(dst_first);
1128
1129 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1130 "must move at least 1 register" );
1131
1132 if (src_first == dst_first && src_second == dst_second) {
1133 // Self copy, no move
1134 return 0;
1135 }
1136 if (bottom_type()->isa_vect() != NULL) {
1137 uint ireg = ideal_reg();
1138 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1139 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY), "sanity");
1140 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1141 // mem -> mem
1142 int src_offset = ra_->reg2offset(src_first);
1143 int dst_offset = ra_->reg2offset(dst_first);
1144 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1145 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1146 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1147 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1148 int stack_offset = ra_->reg2offset(dst_first);
1149 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1150 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1151 int stack_offset = ra_->reg2offset(src_first);
1152 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1153 } else {
1154 ShouldNotReachHere();
1155 }
1156 return 0;
1157 }
1158 if (src_first_rc == rc_stack) {
1159 // mem ->
1160 if (dst_first_rc == rc_stack) {
1161 // mem -> mem
1162 assert(src_second != dst_first, "overlap");
1163 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1164 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1165 // 64-bit
1166 int src_offset = ra_->reg2offset(src_first);
1167 int dst_offset = ra_->reg2offset(dst_first);
1168 if (cbuf) {
1169 MacroAssembler _masm(cbuf);
1170 __ pushq(Address(rsp, src_offset));
1171 __ popq (Address(rsp, dst_offset));
1172 #ifndef PRODUCT
1173 } else {
1174 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1175 "popq [rsp + #%d]",
1176 src_offset, dst_offset);
1177 #endif
1178 }
1179 } else {
1180 // 32-bit
1181 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1182 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1183 // No pushl/popl, so:
1184 int src_offset = ra_->reg2offset(src_first);
1185 int dst_offset = ra_->reg2offset(dst_first);
1186 if (cbuf) {
1187 MacroAssembler _masm(cbuf);
1188 __ movq(Address(rsp, -8), rax);
1189 __ movl(rax, Address(rsp, src_offset));
1190 __ movl(Address(rsp, dst_offset), rax);
1191 __ movq(rax, Address(rsp, -8));
1192 #ifndef PRODUCT
1193 } else {
1194 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1195 "movl rax, [rsp + #%d]\n\t"
1196 "movl [rsp + #%d], rax\n\t"
1197 "movq rax, [rsp - #8]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 }
1202 return 0;
1203 } else if (dst_first_rc == rc_int) {
1204 // mem -> gpr
1205 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1206 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1207 // 64-bit
1208 int offset = ra_->reg2offset(src_first);
1209 if (cbuf) {
1210 MacroAssembler _masm(cbuf);
1211 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1212 #ifndef PRODUCT
1213 } else {
1214 st->print("movq %s, [rsp + #%d]\t# spill",
1215 Matcher::regName[dst_first],
1216 offset);
1217 #endif
1218 }
1219 } else {
1220 // 32-bit
1221 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1222 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1223 int offset = ra_->reg2offset(src_first);
1224 if (cbuf) {
1225 MacroAssembler _masm(cbuf);
1226 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1227 #ifndef PRODUCT
1228 } else {
1229 st->print("movl %s, [rsp + #%d]\t# spill",
1230 Matcher::regName[dst_first],
1231 offset);
1232 #endif
1233 }
1234 }
1235 return 0;
1236 } else if (dst_first_rc == rc_float) {
1237 // mem-> xmm
1238 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1239 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1240 // 64-bit
1241 int offset = ra_->reg2offset(src_first);
1242 if (cbuf) {
1243 MacroAssembler _masm(cbuf);
1244 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1245 #ifndef PRODUCT
1246 } else {
1247 st->print("%s %s, [rsp + #%d]\t# spill",
1248 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1249 Matcher::regName[dst_first],
1250 offset);
1251 #endif
1252 }
1253 } else {
1254 // 32-bit
1255 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1256 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1257 int offset = ra_->reg2offset(src_first);
1258 if (cbuf) {
1259 MacroAssembler _masm(cbuf);
1260 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1261 #ifndef PRODUCT
1262 } else {
1263 st->print("movss %s, [rsp + #%d]\t# spill",
1264 Matcher::regName[dst_first],
1265 offset);
1266 #endif
1267 }
1268 }
1269 return 0;
1270 }
1271 } else if (src_first_rc == rc_int) {
1272 // gpr ->
1273 if (dst_first_rc == rc_stack) {
1274 // gpr -> mem
1275 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1276 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1277 // 64-bit
1278 int offset = ra_->reg2offset(dst_first);
1279 if (cbuf) {
1280 MacroAssembler _masm(cbuf);
1281 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1282 #ifndef PRODUCT
1283 } else {
1284 st->print("movq [rsp + #%d], %s\t# spill",
1285 offset,
1286 Matcher::regName[src_first]);
1287 #endif
1288 }
1289 } else {
1290 // 32-bit
1291 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1292 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1293 int offset = ra_->reg2offset(dst_first);
1294 if (cbuf) {
1295 MacroAssembler _masm(cbuf);
1296 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1297 #ifndef PRODUCT
1298 } else {
1299 st->print("movl [rsp + #%d], %s\t# spill",
1300 offset,
1301 Matcher::regName[src_first]);
1302 #endif
1303 }
1304 }
1305 return 0;
1306 } else if (dst_first_rc == rc_int) {
1307 // gpr -> gpr
1308 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1309 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1310 // 64-bit
1311 if (cbuf) {
1312 MacroAssembler _masm(cbuf);
1313 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1314 as_Register(Matcher::_regEncode[src_first]));
1315 #ifndef PRODUCT
1316 } else {
1317 st->print("movq %s, %s\t# spill",
1318 Matcher::regName[dst_first],
1319 Matcher::regName[src_first]);
1320 #endif
1321 }
1322 return 0;
1323 } else {
1324 // 32-bit
1325 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1326 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1327 if (cbuf) {
1328 MacroAssembler _masm(cbuf);
1329 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1330 as_Register(Matcher::_regEncode[src_first]));
1331 #ifndef PRODUCT
1332 } else {
1333 st->print("movl %s, %s\t# spill",
1334 Matcher::regName[dst_first],
1335 Matcher::regName[src_first]);
1336 #endif
1337 }
1338 return 0;
1339 }
1340 } else if (dst_first_rc == rc_float) {
1341 // gpr -> xmm
1342 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1343 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1344 // 64-bit
1345 if (cbuf) {
1346 MacroAssembler _masm(cbuf);
1347 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1348 #ifndef PRODUCT
1349 } else {
1350 st->print("movdq %s, %s\t# spill",
1351 Matcher::regName[dst_first],
1352 Matcher::regName[src_first]);
1353 #endif
1354 }
1355 } else {
1356 // 32-bit
1357 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1358 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1359 if (cbuf) {
1360 MacroAssembler _masm(cbuf);
1361 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1362 #ifndef PRODUCT
1363 } else {
1364 st->print("movdl %s, %s\t# spill",
1365 Matcher::regName[dst_first],
1366 Matcher::regName[src_first]);
1367 #endif
1368 }
1369 }
1370 return 0;
1371 }
1372 } else if (src_first_rc == rc_float) {
1373 // xmm ->
1374 if (dst_first_rc == rc_stack) {
1375 // xmm -> mem
1376 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1377 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1378 // 64-bit
1379 int offset = ra_->reg2offset(dst_first);
1380 if (cbuf) {
1381 MacroAssembler _masm(cbuf);
1382 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1383 #ifndef PRODUCT
1384 } else {
1385 st->print("movsd [rsp + #%d], %s\t# spill",
1386 offset,
1387 Matcher::regName[src_first]);
1388 #endif
1389 }
1390 } else {
1391 // 32-bit
1392 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1393 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1394 int offset = ra_->reg2offset(dst_first);
1395 if (cbuf) {
1396 MacroAssembler _masm(cbuf);
1397 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1398 #ifndef PRODUCT
1399 } else {
1400 st->print("movss [rsp + #%d], %s\t# spill",
1401 offset,
1402 Matcher::regName[src_first]);
1403 #endif
1404 }
1405 }
1406 return 0;
1407 } else if (dst_first_rc == rc_int) {
1408 // xmm -> gpr
1409 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1410 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1411 // 64-bit
1412 if (cbuf) {
1413 MacroAssembler _masm(cbuf);
1414 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1415 #ifndef PRODUCT
1416 } else {
1417 st->print("movdq %s, %s\t# spill",
1418 Matcher::regName[dst_first],
1419 Matcher::regName[src_first]);
1420 #endif
1421 }
1422 } else {
1423 // 32-bit
1424 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1425 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1426 if (cbuf) {
1427 MacroAssembler _masm(cbuf);
1428 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1429 #ifndef PRODUCT
1430 } else {
1431 st->print("movdl %s, %s\t# spill",
1432 Matcher::regName[dst_first],
1433 Matcher::regName[src_first]);
1434 #endif
1435 }
1436 }
1437 return 0;
1438 } else if (dst_first_rc == rc_float) {
1439 // xmm -> xmm
1440 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1441 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1442 // 64-bit
1443 if (cbuf) {
1444 MacroAssembler _masm(cbuf);
1445 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1446 #ifndef PRODUCT
1447 } else {
1448 st->print("%s %s, %s\t# spill",
1449 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1450 Matcher::regName[dst_first],
1451 Matcher::regName[src_first]);
1452 #endif
1453 }
1454 } else {
1455 // 32-bit
1456 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1457 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1458 if (cbuf) {
1459 MacroAssembler _masm(cbuf);
1460 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1461 #ifndef PRODUCT
1462 } else {
1463 st->print("%s %s, %s\t# spill",
1464 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1465 Matcher::regName[dst_first],
1466 Matcher::regName[src_first]);
1467 #endif
1468 }
1469 }
1470 return 0;
1471 }
1472 }
1473
1474 assert(0," foo ");
1475 Unimplemented();
1476 return 0;
1477 }
1478
1479 #ifndef PRODUCT
1480 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1481 implementation(NULL, ra_, false, st);
1482 }
1483 #endif
1484
1485 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1486 implementation(&cbuf, ra_, false, NULL);
1487 }
1488
1489 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1490 return MachNode::size(ra_);
1491 }
1492
1493 //=============================================================================
1494 #ifndef PRODUCT
1495 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1496 {
1497 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1498 int reg = ra_->get_reg_first(this);
1499 st->print("leaq %s, [rsp + #%d]\t# box lock",
1500 Matcher::regName[reg], offset);
1501 }
1502 #endif
1503
1504 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1505 {
1506 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1507 int reg = ra_->get_encode(this);
1508 if (offset >= 0x80) {
1509 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1510 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1511 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1512 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1513 emit_d32(cbuf, offset);
1514 } else {
1515 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1516 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1517 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1518 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1519 emit_d8(cbuf, offset);
1520 }
1521 }
1522
1523 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1524 {
1525 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1526 return (offset < 0x80) ? 5 : 8; // REX
1527 }
1528
1529 //=============================================================================
1530 #ifndef PRODUCT
1531 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1532 {
1533 if (UseCompressedClassPointers) {
1534 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1535 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1536 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1537 } else {
1538 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1539 "# Inline cache check");
1540 }
1541 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1542 st->print_cr("\tnop\t# nops to align entry point");
1543 }
1544 #endif
1545
1546 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1547 {
1548 MacroAssembler masm(&cbuf);
1549 uint insts_size = cbuf.insts_size();
1550 if (UseCompressedClassPointers) {
1551 masm.load_klass(rscratch1, j_rarg0);
1552 masm.cmpptr(rax, rscratch1);
1553 } else {
1554 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1555 }
1556
1557 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1558
1559 /* WARNING these NOPs are critical so that verified entry point is properly
1560 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1561 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1562 if (OptoBreakpoint) {
1563 // Leave space for int3
1564 nops_cnt -= 1;
1565 }
1566 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1567 if (nops_cnt > 0)
1568 masm.nop(nops_cnt);
1569 }
1570
1571 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1572 {
1573 return MachNode::size(ra_); // too many variables; just compute it
1574 // the hard way
1575 }
1576
1577
1578 //=============================================================================
1579
1580 int Matcher::regnum_to_fpu_offset(int regnum)
1581 {
1582 return regnum - 32; // The FP registers are in the second chunk
1583 }
1584
1585 // This is UltraSparc specific, true just means we have fast l2f conversion
1586 const bool Matcher::convL2FSupported(void) {
1587 return true;
1588 }
1589
1590 // Is this branch offset short enough that a short branch can be used?
1591 //
1592 // NOTE: If the platform does not provide any short branch variants, then
1593 // this method should return false for offset 0.
1594 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1595 // The passed offset is relative to address of the branch.
1596 // On 86 a branch displacement is calculated relative to address
1597 // of a next instruction.
1598 offset -= br_size;
1599
1600 // the short version of jmpConUCF2 contains multiple branches,
1601 // making the reach slightly less
1602 if (rule == jmpConUCF2_rule)
1603 return (-126 <= offset && offset <= 125);
1604 return (-128 <= offset && offset <= 127);
1605 }
1606
1607 const bool Matcher::isSimpleConstant64(jlong value) {
1608 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1609 //return value == (int) value; // Cf. storeImmL and immL32.
1610
1611 // Probably always true, even if a temp register is required.
1612 return true;
1613 }
1614
1615 // The ecx parameter to rep stosq for the ClearArray node is in words.
1616 const bool Matcher::init_array_count_is_in_bytes = false;
1617
1618 // Threshold size for cleararray.
1619 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1620
1621 // No additional cost for CMOVL.
1622 const int Matcher::long_cmove_cost() { return 0; }
1623
1624 // No CMOVF/CMOVD with SSE2
1625 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1626
1627 // Does the CPU require late expand (see block.cpp for description of late expand)?
1628 const bool Matcher::require_postalloc_expand = false;
1629
1630 // Should the Matcher clone shifts on addressing modes, expecting them
1631 // to be subsumed into complex addressing expressions or compute them
1632 // into registers? True for Intel but false for most RISCs
1633 const bool Matcher::clone_shift_expressions = true;
1634
1635 // Do we need to mask the count passed to shift instructions or does
1636 // the cpu only look at the lower 5/6 bits anyway?
1637 const bool Matcher::need_masked_shift_count = false;
1638
1639 bool Matcher::narrow_oop_use_complex_address() {
1640 assert(UseCompressedOops, "only for compressed oops code");
1641 return (LogMinObjAlignmentInBytes <= 3);
1642 }
1643
1644 bool Matcher::narrow_klass_use_complex_address() {
1645 assert(UseCompressedClassPointers, "only for compressed klass code");
1646 return (LogKlassAlignmentInBytes <= 3);
1647 }
1648
1649 // Is it better to copy float constants, or load them directly from
1650 // memory? Intel can load a float constant from a direct address,
1651 // requiring no extra registers. Most RISCs will have to materialize
1652 // an address into a register first, so they would do better to copy
1653 // the constant from stack.
1654 const bool Matcher::rematerialize_float_constants = true; // XXX
1655
1656 // If CPU can load and store mis-aligned doubles directly then no
1657 // fixup is needed. Else we split the double into 2 integer pieces
1658 // and move it piece-by-piece. Only happens when passing doubles into
1659 // C code as the Java calling convention forces doubles to be aligned.
1660 const bool Matcher::misaligned_doubles_ok = true;
1661
1662 // No-op on amd64
1663 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1664
1665 // Advertise here if the CPU requires explicit rounding operations to
1666 // implement the UseStrictFP mode.
1667 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1668
1669 // Are floats conerted to double when stored to stack during deoptimization?
1670 // On x64 it is stored without convertion so we can use normal access.
1671 bool Matcher::float_in_double() { return false; }
1672
1673 // Do ints take an entire long register or just half?
1674 const bool Matcher::int_in_long = true;
1675
1676 // Return whether or not this register is ever used as an argument.
1677 // This function is used on startup to build the trampoline stubs in
1678 // generateOptoStub. Registers not mentioned will be killed by the VM
1679 // call in the trampoline, and arguments in those registers not be
1680 // available to the callee.
1681 bool Matcher::can_be_java_arg(int reg)
1682 {
1683 return
1684 reg == RDI_num || reg == RDI_H_num ||
1685 reg == RSI_num || reg == RSI_H_num ||
1686 reg == RDX_num || reg == RDX_H_num ||
1687 reg == RCX_num || reg == RCX_H_num ||
1688 reg == R8_num || reg == R8_H_num ||
1689 reg == R9_num || reg == R9_H_num ||
1690 reg == R12_num || reg == R12_H_num ||
1691 reg == XMM0_num || reg == XMM0b_num ||
1692 reg == XMM1_num || reg == XMM1b_num ||
1693 reg == XMM2_num || reg == XMM2b_num ||
1694 reg == XMM3_num || reg == XMM3b_num ||
1695 reg == XMM4_num || reg == XMM4b_num ||
1696 reg == XMM5_num || reg == XMM5b_num ||
1697 reg == XMM6_num || reg == XMM6b_num ||
1698 reg == XMM7_num || reg == XMM7b_num;
1699 }
1700
1701 bool Matcher::is_spillable_arg(int reg)
1702 {
1703 return can_be_java_arg(reg);
1704 }
1705
1706 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1707 // In 64 bit mode a code which use multiply when
1708 // devisor is constant is faster than hardware
1709 // DIV instruction (it uses MulHiL).
1710 return false;
1711 }
1712
1713 // Register for DIVI projection of divmodI
1714 RegMask Matcher::divI_proj_mask() {
1715 return INT_RAX_REG_mask();
1716 }
1717
1718 // Register for MODI projection of divmodI
1719 RegMask Matcher::modI_proj_mask() {
1720 return INT_RDX_REG_mask();
1721 }
1722
1723 // Register for DIVL projection of divmodL
1724 RegMask Matcher::divL_proj_mask() {
1725 return LONG_RAX_REG_mask();
1726 }
1727
1728 // Register for MODL projection of divmodL
1729 RegMask Matcher::modL_proj_mask() {
1730 return LONG_RDX_REG_mask();
1731 }
1732
1733 // Register for saving SP into on method handle invokes. Not used on x86_64.
1734 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1735 return NO_REG_mask();
1736 }
1737
1738 %}
1739
1740 //----------ENCODING BLOCK-----------------------------------------------------
1741 // This block specifies the encoding classes used by the compiler to
1742 // output byte streams. Encoding classes are parameterized macros
1743 // used by Machine Instruction Nodes in order to generate the bit
1744 // encoding of the instruction. Operands specify their base encoding
1745 // interface with the interface keyword. There are currently
1746 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1747 // COND_INTER. REG_INTER causes an operand to generate a function
1748 // which returns its register number when queried. CONST_INTER causes
1749 // an operand to generate a function which returns the value of the
1750 // constant when queried. MEMORY_INTER causes an operand to generate
1751 // four functions which return the Base Register, the Index Register,
1752 // the Scale Value, and the Offset Value of the operand when queried.
1753 // COND_INTER causes an operand to generate six functions which return
1754 // the encoding code (ie - encoding bits for the instruction)
1755 // associated with each basic boolean condition for a conditional
1756 // instruction.
1757 //
1758 // Instructions specify two basic values for encoding. Again, a
1759 // function is available to check if the constant displacement is an
1760 // oop. They use the ins_encode keyword to specify their encoding
1761 // classes (which must be a sequence of enc_class names, and their
1762 // parameters, specified in the encoding block), and they use the
1763 // opcode keyword to specify, in order, their primary, secondary, and
1764 // tertiary opcode. Only the opcode sections which a particular
1765 // instruction needs for encoding need to be specified.
1766 encode %{
1767 // Build emit functions for each basic byte or larger field in the
1768 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1769 // from C++ code in the enc_class source block. Emit functions will
1770 // live in the main source block for now. In future, we can
1771 // generalize this by adding a syntax that specifies the sizes of
1772 // fields in an order, so that the adlc can build the emit functions
1773 // automagically
1774
1775 // Emit primary opcode
1776 enc_class OpcP
1777 %{
1778 emit_opcode(cbuf, $primary);
1779 %}
1780
1781 // Emit secondary opcode
1782 enc_class OpcS
1783 %{
1784 emit_opcode(cbuf, $secondary);
1785 %}
1786
1787 // Emit tertiary opcode
1788 enc_class OpcT
1789 %{
1790 emit_opcode(cbuf, $tertiary);
1791 %}
1792
1793 // Emit opcode directly
1794 enc_class Opcode(immI d8)
1795 %{
1796 emit_opcode(cbuf, $d8$$constant);
1797 %}
1798
1799 // Emit size prefix
1800 enc_class SizePrefix
1801 %{
1802 emit_opcode(cbuf, 0x66);
1803 %}
1804
1805 enc_class reg(rRegI reg)
1806 %{
1807 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1808 %}
1809
1810 enc_class reg_reg(rRegI dst, rRegI src)
1811 %{
1812 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1813 %}
1814
1815 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1816 %{
1817 emit_opcode(cbuf, $opcode$$constant);
1818 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1819 %}
1820
1821 enc_class cdql_enc(no_rax_rdx_RegI div)
1822 %{
1823 // Full implementation of Java idiv and irem; checks for
1824 // special case as described in JVM spec., p.243 & p.271.
1825 //
1826 // normal case special case
1827 //
1828 // input : rax: dividend min_int
1829 // reg: divisor -1
1830 //
1831 // output: rax: quotient (= rax idiv reg) min_int
1832 // rdx: remainder (= rax irem reg) 0
1833 //
1834 // Code sequnce:
1835 //
1836 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1837 // 5: 75 07/08 jne e <normal>
1838 // 7: 33 d2 xor %edx,%edx
1839 // [div >= 8 -> offset + 1]
1840 // [REX_B]
1841 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1842 // c: 74 03/04 je 11 <done>
1843 // 000000000000000e <normal>:
1844 // e: 99 cltd
1845 // [div >= 8 -> offset + 1]
1846 // [REX_B]
1847 // f: f7 f9 idiv $div
1848 // 0000000000000011 <done>:
1849
1850 // cmp $0x80000000,%eax
1851 emit_opcode(cbuf, 0x3d);
1852 emit_d8(cbuf, 0x00);
1853 emit_d8(cbuf, 0x00);
1854 emit_d8(cbuf, 0x00);
1855 emit_d8(cbuf, 0x80);
1856
1857 // jne e <normal>
1858 emit_opcode(cbuf, 0x75);
1859 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1860
1861 // xor %edx,%edx
1862 emit_opcode(cbuf, 0x33);
1863 emit_d8(cbuf, 0xD2);
1864
1865 // cmp $0xffffffffffffffff,%ecx
1866 if ($div$$reg >= 8) {
1867 emit_opcode(cbuf, Assembler::REX_B);
1868 }
1869 emit_opcode(cbuf, 0x83);
1870 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1871 emit_d8(cbuf, 0xFF);
1872
1873 // je 11 <done>
1874 emit_opcode(cbuf, 0x74);
1875 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1876
1877 // <normal>
1878 // cltd
1879 emit_opcode(cbuf, 0x99);
1880
1881 // idivl (note: must be emitted by the user of this rule)
1882 // <done>
1883 %}
1884
1885 enc_class cdqq_enc(no_rax_rdx_RegL div)
1886 %{
1887 // Full implementation of Java ldiv and lrem; checks for
1888 // special case as described in JVM spec., p.243 & p.271.
1889 //
1890 // normal case special case
1891 //
1892 // input : rax: dividend min_long
1893 // reg: divisor -1
1894 //
1895 // output: rax: quotient (= rax idiv reg) min_long
1896 // rdx: remainder (= rax irem reg) 0
1897 //
1898 // Code sequnce:
1899 //
1900 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1901 // 7: 00 00 80
1902 // a: 48 39 d0 cmp %rdx,%rax
1903 // d: 75 08 jne 17 <normal>
1904 // f: 33 d2 xor %edx,%edx
1905 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1906 // 15: 74 05 je 1c <done>
1907 // 0000000000000017 <normal>:
1908 // 17: 48 99 cqto
1909 // 19: 48 f7 f9 idiv $div
1910 // 000000000000001c <done>:
1911
1912 // mov $0x8000000000000000,%rdx
1913 emit_opcode(cbuf, Assembler::REX_W);
1914 emit_opcode(cbuf, 0xBA);
1915 emit_d8(cbuf, 0x00);
1916 emit_d8(cbuf, 0x00);
1917 emit_d8(cbuf, 0x00);
1918 emit_d8(cbuf, 0x00);
1919 emit_d8(cbuf, 0x00);
1920 emit_d8(cbuf, 0x00);
1921 emit_d8(cbuf, 0x00);
1922 emit_d8(cbuf, 0x80);
1923
1924 // cmp %rdx,%rax
1925 emit_opcode(cbuf, Assembler::REX_W);
1926 emit_opcode(cbuf, 0x39);
1927 emit_d8(cbuf, 0xD0);
1928
1929 // jne 17 <normal>
1930 emit_opcode(cbuf, 0x75);
1931 emit_d8(cbuf, 0x08);
1932
1933 // xor %edx,%edx
1934 emit_opcode(cbuf, 0x33);
1935 emit_d8(cbuf, 0xD2);
1936
1937 // cmp $0xffffffffffffffff,$div
1938 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1939 emit_opcode(cbuf, 0x83);
1940 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1941 emit_d8(cbuf, 0xFF);
1942
1943 // je 1e <done>
1944 emit_opcode(cbuf, 0x74);
1945 emit_d8(cbuf, 0x05);
1946
1947 // <normal>
1948 // cqto
1949 emit_opcode(cbuf, Assembler::REX_W);
1950 emit_opcode(cbuf, 0x99);
1951
1952 // idivq (note: must be emitted by the user of this rule)
1953 // <done>
1954 %}
1955
1956 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1957 enc_class OpcSE(immI imm)
1958 %{
1959 // Emit primary opcode and set sign-extend bit
1960 // Check for 8-bit immediate, and set sign extend bit in opcode
1961 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1962 emit_opcode(cbuf, $primary | 0x02);
1963 } else {
1964 // 32-bit immediate
1965 emit_opcode(cbuf, $primary);
1966 }
1967 %}
1968
1969 enc_class OpcSErm(rRegI dst, immI imm)
1970 %{
1971 // OpcSEr/m
1972 int dstenc = $dst$$reg;
1973 if (dstenc >= 8) {
1974 emit_opcode(cbuf, Assembler::REX_B);
1975 dstenc -= 8;
1976 }
1977 // Emit primary opcode and set sign-extend bit
1978 // Check for 8-bit immediate, and set sign extend bit in opcode
1979 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1980 emit_opcode(cbuf, $primary | 0x02);
1981 } else {
1982 // 32-bit immediate
1983 emit_opcode(cbuf, $primary);
1984 }
1985 // Emit r/m byte with secondary opcode, after primary opcode.
1986 emit_rm(cbuf, 0x3, $secondary, dstenc);
1987 %}
1988
1989 enc_class OpcSErm_wide(rRegL dst, immI imm)
1990 %{
1991 // OpcSEr/m
1992 int dstenc = $dst$$reg;
1993 if (dstenc < 8) {
1994 emit_opcode(cbuf, Assembler::REX_W);
1995 } else {
1996 emit_opcode(cbuf, Assembler::REX_WB);
1997 dstenc -= 8;
1998 }
1999 // Emit primary opcode and set sign-extend bit
2000 // Check for 8-bit immediate, and set sign extend bit in opcode
2001 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2002 emit_opcode(cbuf, $primary | 0x02);
2003 } else {
2004 // 32-bit immediate
2005 emit_opcode(cbuf, $primary);
2006 }
2007 // Emit r/m byte with secondary opcode, after primary opcode.
2008 emit_rm(cbuf, 0x3, $secondary, dstenc);
2009 %}
2010
2011 enc_class Con8or32(immI imm)
2012 %{
2013 // Check for 8-bit immediate, and set sign extend bit in opcode
2014 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2015 $$$emit8$imm$$constant;
2016 } else {
2017 // 32-bit immediate
2018 $$$emit32$imm$$constant;
2019 }
2020 %}
2021
2022 enc_class opc2_reg(rRegI dst)
2023 %{
2024 // BSWAP
2025 emit_cc(cbuf, $secondary, $dst$$reg);
2026 %}
2027
2028 enc_class opc3_reg(rRegI dst)
2029 %{
2030 // BSWAP
2031 emit_cc(cbuf, $tertiary, $dst$$reg);
2032 %}
2033
2034 enc_class reg_opc(rRegI div)
2035 %{
2036 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2037 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2038 %}
2039
2040 enc_class enc_cmov(cmpOp cop)
2041 %{
2042 // CMOV
2043 $$$emit8$primary;
2044 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2045 %}
2046
2047 enc_class enc_PartialSubtypeCheck()
2048 %{
2049 Register Rrdi = as_Register(RDI_enc); // result register
2050 Register Rrax = as_Register(RAX_enc); // super class
2051 Register Rrcx = as_Register(RCX_enc); // killed
2052 Register Rrsi = as_Register(RSI_enc); // sub class
2053 Label miss;
2054 const bool set_cond_codes = true;
2055
2056 MacroAssembler _masm(&cbuf);
2057 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2058 NULL, &miss,
2059 /*set_cond_codes:*/ true);
2060 if ($primary) {
2061 __ xorptr(Rrdi, Rrdi);
2062 }
2063 __ bind(miss);
2064 %}
2065
2066 enc_class clear_avx %{
2067 debug_only(int off0 = cbuf.insts_size());
2068 if (ra_->C->max_vector_size() > 16) {
2069 // Clear upper bits of YMM registers when current compiled code uses
2070 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2071 MacroAssembler _masm(&cbuf);
2072 __ vzeroupper();
2073 }
2074 debug_only(int off1 = cbuf.insts_size());
2075 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2076 %}
2077
2078 enc_class Java_To_Runtime(method meth) %{
2079 // No relocation needed
2080 MacroAssembler _masm(&cbuf);
2081 __ mov64(r10, (int64_t) $meth$$method);
2082 __ call(r10);
2083 %}
2084
2085 enc_class Java_To_Interpreter(method meth)
2086 %{
2087 // CALL Java_To_Interpreter
2088 // This is the instruction starting address for relocation info.
2089 cbuf.set_insts_mark();
2090 $$$emit8$primary;
2091 // CALL directly to the runtime
2092 emit_d32_reloc(cbuf,
2093 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2094 runtime_call_Relocation::spec(),
2095 RELOC_DISP32);
2096 %}
2097
2098 enc_class Java_Static_Call(method meth)
2099 %{
2100 // JAVA STATIC CALL
2101 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2102 // determine who we intended to call.
2103 cbuf.set_insts_mark();
2104 $$$emit8$primary;
2105
2106 if (!_method) {
2107 emit_d32_reloc(cbuf,
2108 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2109 runtime_call_Relocation::spec(),
2110 RELOC_DISP32);
2111 } else if (_optimized_virtual) {
2112 emit_d32_reloc(cbuf,
2113 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2114 opt_virtual_call_Relocation::spec(),
2115 RELOC_DISP32);
2116 } else {
2117 emit_d32_reloc(cbuf,
2118 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2119 static_call_Relocation::spec(),
2120 RELOC_DISP32);
2121 }
2122 if (_method) {
2123 // Emit stub for static call.
2124 CompiledStaticCall::emit_to_interp_stub(cbuf);
2125 }
2126 %}
2127
2128 enc_class Java_Dynamic_Call(method meth) %{
2129 MacroAssembler _masm(&cbuf);
2130 __ ic_call((address)$meth$$method);
2131 %}
2132
2133 enc_class Java_Compiled_Call(method meth)
2134 %{
2135 // JAVA COMPILED CALL
2136 int disp = in_bytes(Method:: from_compiled_offset());
2137
2138 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2139 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2140
2141 // callq *disp(%rax)
2142 cbuf.set_insts_mark();
2143 $$$emit8$primary;
2144 if (disp < 0x80) {
2145 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2146 emit_d8(cbuf, disp); // Displacement
2147 } else {
2148 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2149 emit_d32(cbuf, disp); // Displacement
2150 }
2151 %}
2152
2153 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2154 %{
2155 // SAL, SAR, SHR
2156 int dstenc = $dst$$reg;
2157 if (dstenc >= 8) {
2158 emit_opcode(cbuf, Assembler::REX_B);
2159 dstenc -= 8;
2160 }
2161 $$$emit8$primary;
2162 emit_rm(cbuf, 0x3, $secondary, dstenc);
2163 $$$emit8$shift$$constant;
2164 %}
2165
2166 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2167 %{
2168 // SAL, SAR, SHR
2169 int dstenc = $dst$$reg;
2170 if (dstenc < 8) {
2171 emit_opcode(cbuf, Assembler::REX_W);
2172 } else {
2173 emit_opcode(cbuf, Assembler::REX_WB);
2174 dstenc -= 8;
2175 }
2176 $$$emit8$primary;
2177 emit_rm(cbuf, 0x3, $secondary, dstenc);
2178 $$$emit8$shift$$constant;
2179 %}
2180
2181 enc_class load_immI(rRegI dst, immI src)
2182 %{
2183 int dstenc = $dst$$reg;
2184 if (dstenc >= 8) {
2185 emit_opcode(cbuf, Assembler::REX_B);
2186 dstenc -= 8;
2187 }
2188 emit_opcode(cbuf, 0xB8 | dstenc);
2189 $$$emit32$src$$constant;
2190 %}
2191
2192 enc_class load_immL(rRegL dst, immL src)
2193 %{
2194 int dstenc = $dst$$reg;
2195 if (dstenc < 8) {
2196 emit_opcode(cbuf, Assembler::REX_W);
2197 } else {
2198 emit_opcode(cbuf, Assembler::REX_WB);
2199 dstenc -= 8;
2200 }
2201 emit_opcode(cbuf, 0xB8 | dstenc);
2202 emit_d64(cbuf, $src$$constant);
2203 %}
2204
2205 enc_class load_immUL32(rRegL dst, immUL32 src)
2206 %{
2207 // same as load_immI, but this time we care about zeroes in the high word
2208 int dstenc = $dst$$reg;
2209 if (dstenc >= 8) {
2210 emit_opcode(cbuf, Assembler::REX_B);
2211 dstenc -= 8;
2212 }
2213 emit_opcode(cbuf, 0xB8 | dstenc);
2214 $$$emit32$src$$constant;
2215 %}
2216
2217 enc_class load_immL32(rRegL dst, immL32 src)
2218 %{
2219 int dstenc = $dst$$reg;
2220 if (dstenc < 8) {
2221 emit_opcode(cbuf, Assembler::REX_W);
2222 } else {
2223 emit_opcode(cbuf, Assembler::REX_WB);
2224 dstenc -= 8;
2225 }
2226 emit_opcode(cbuf, 0xC7);
2227 emit_rm(cbuf, 0x03, 0x00, dstenc);
2228 $$$emit32$src$$constant;
2229 %}
2230
2231 enc_class load_immP31(rRegP dst, immP32 src)
2232 %{
2233 // same as load_immI, but this time we care about zeroes in the high word
2234 int dstenc = $dst$$reg;
2235 if (dstenc >= 8) {
2236 emit_opcode(cbuf, Assembler::REX_B);
2237 dstenc -= 8;
2238 }
2239 emit_opcode(cbuf, 0xB8 | dstenc);
2240 $$$emit32$src$$constant;
2241 %}
2242
2243 enc_class load_immP(rRegP dst, immP src)
2244 %{
2245 int dstenc = $dst$$reg;
2246 if (dstenc < 8) {
2247 emit_opcode(cbuf, Assembler::REX_W);
2248 } else {
2249 emit_opcode(cbuf, Assembler::REX_WB);
2250 dstenc -= 8;
2251 }
2252 emit_opcode(cbuf, 0xB8 | dstenc);
2253 // This next line should be generated from ADLC
2254 if ($src->constant_reloc() != relocInfo::none) {
2255 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2256 } else {
2257 emit_d64(cbuf, $src$$constant);
2258 }
2259 %}
2260
2261 enc_class Con32(immI src)
2262 %{
2263 // Output immediate
2264 $$$emit32$src$$constant;
2265 %}
2266
2267 enc_class Con32F_as_bits(immF src)
2268 %{
2269 // Output Float immediate bits
2270 jfloat jf = $src$$constant;
2271 jint jf_as_bits = jint_cast(jf);
2272 emit_d32(cbuf, jf_as_bits);
2273 %}
2274
2275 enc_class Con16(immI src)
2276 %{
2277 // Output immediate
2278 $$$emit16$src$$constant;
2279 %}
2280
2281 // How is this different from Con32??? XXX
2282 enc_class Con_d32(immI src)
2283 %{
2284 emit_d32(cbuf,$src$$constant);
2285 %}
2286
2287 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2288 // Output immediate memory reference
2289 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2290 emit_d32(cbuf, 0x00);
2291 %}
2292
2293 enc_class lock_prefix()
2294 %{
2295 if (os::is_MP()) {
2296 emit_opcode(cbuf, 0xF0); // lock
2297 }
2298 %}
2299
2300 enc_class REX_mem(memory mem)
2301 %{
2302 if ($mem$$base >= 8) {
2303 if ($mem$$index < 8) {
2304 emit_opcode(cbuf, Assembler::REX_B);
2305 } else {
2306 emit_opcode(cbuf, Assembler::REX_XB);
2307 }
2308 } else {
2309 if ($mem$$index >= 8) {
2310 emit_opcode(cbuf, Assembler::REX_X);
2311 }
2312 }
2313 %}
2314
2315 enc_class REX_mem_wide(memory mem)
2316 %{
2317 if ($mem$$base >= 8) {
2318 if ($mem$$index < 8) {
2319 emit_opcode(cbuf, Assembler::REX_WB);
2320 } else {
2321 emit_opcode(cbuf, Assembler::REX_WXB);
2322 }
2323 } else {
2324 if ($mem$$index < 8) {
2325 emit_opcode(cbuf, Assembler::REX_W);
2326 } else {
2327 emit_opcode(cbuf, Assembler::REX_WX);
2328 }
2329 }
2330 %}
2331
2332 // for byte regs
2333 enc_class REX_breg(rRegI reg)
2334 %{
2335 if ($reg$$reg >= 4) {
2336 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2337 }
2338 %}
2339
2340 // for byte regs
2341 enc_class REX_reg_breg(rRegI dst, rRegI src)
2342 %{
2343 if ($dst$$reg < 8) {
2344 if ($src$$reg >= 4) {
2345 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2346 }
2347 } else {
2348 if ($src$$reg < 8) {
2349 emit_opcode(cbuf, Assembler::REX_R);
2350 } else {
2351 emit_opcode(cbuf, Assembler::REX_RB);
2352 }
2353 }
2354 %}
2355
2356 // for byte regs
2357 enc_class REX_breg_mem(rRegI reg, memory mem)
2358 %{
2359 if ($reg$$reg < 8) {
2360 if ($mem$$base < 8) {
2361 if ($mem$$index >= 8) {
2362 emit_opcode(cbuf, Assembler::REX_X);
2363 } else if ($reg$$reg >= 4) {
2364 emit_opcode(cbuf, Assembler::REX);
2365 }
2366 } else {
2367 if ($mem$$index < 8) {
2368 emit_opcode(cbuf, Assembler::REX_B);
2369 } else {
2370 emit_opcode(cbuf, Assembler::REX_XB);
2371 }
2372 }
2373 } else {
2374 if ($mem$$base < 8) {
2375 if ($mem$$index < 8) {
2376 emit_opcode(cbuf, Assembler::REX_R);
2377 } else {
2378 emit_opcode(cbuf, Assembler::REX_RX);
2379 }
2380 } else {
2381 if ($mem$$index < 8) {
2382 emit_opcode(cbuf, Assembler::REX_RB);
2383 } else {
2384 emit_opcode(cbuf, Assembler::REX_RXB);
2385 }
2386 }
2387 }
2388 %}
2389
2390 enc_class REX_reg(rRegI reg)
2391 %{
2392 if ($reg$$reg >= 8) {
2393 emit_opcode(cbuf, Assembler::REX_B);
2394 }
2395 %}
2396
2397 enc_class REX_reg_wide(rRegI reg)
2398 %{
2399 if ($reg$$reg < 8) {
2400 emit_opcode(cbuf, Assembler::REX_W);
2401 } else {
2402 emit_opcode(cbuf, Assembler::REX_WB);
2403 }
2404 %}
2405
2406 enc_class REX_reg_reg(rRegI dst, rRegI src)
2407 %{
2408 if ($dst$$reg < 8) {
2409 if ($src$$reg >= 8) {
2410 emit_opcode(cbuf, Assembler::REX_B);
2411 }
2412 } else {
2413 if ($src$$reg < 8) {
2414 emit_opcode(cbuf, Assembler::REX_R);
2415 } else {
2416 emit_opcode(cbuf, Assembler::REX_RB);
2417 }
2418 }
2419 %}
2420
2421 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2422 %{
2423 if ($dst$$reg < 8) {
2424 if ($src$$reg < 8) {
2425 emit_opcode(cbuf, Assembler::REX_W);
2426 } else {
2427 emit_opcode(cbuf, Assembler::REX_WB);
2428 }
2429 } else {
2430 if ($src$$reg < 8) {
2431 emit_opcode(cbuf, Assembler::REX_WR);
2432 } else {
2433 emit_opcode(cbuf, Assembler::REX_WRB);
2434 }
2435 }
2436 %}
2437
2438 enc_class REX_reg_mem(rRegI reg, memory mem)
2439 %{
2440 if ($reg$$reg < 8) {
2441 if ($mem$$base < 8) {
2442 if ($mem$$index >= 8) {
2443 emit_opcode(cbuf, Assembler::REX_X);
2444 }
2445 } else {
2446 if ($mem$$index < 8) {
2447 emit_opcode(cbuf, Assembler::REX_B);
2448 } else {
2449 emit_opcode(cbuf, Assembler::REX_XB);
2450 }
2451 }
2452 } else {
2453 if ($mem$$base < 8) {
2454 if ($mem$$index < 8) {
2455 emit_opcode(cbuf, Assembler::REX_R);
2456 } else {
2457 emit_opcode(cbuf, Assembler::REX_RX);
2458 }
2459 } else {
2460 if ($mem$$index < 8) {
2461 emit_opcode(cbuf, Assembler::REX_RB);
2462 } else {
2463 emit_opcode(cbuf, Assembler::REX_RXB);
2464 }
2465 }
2466 }
2467 %}
2468
2469 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2470 %{
2471 if ($reg$$reg < 8) {
2472 if ($mem$$base < 8) {
2473 if ($mem$$index < 8) {
2474 emit_opcode(cbuf, Assembler::REX_W);
2475 } else {
2476 emit_opcode(cbuf, Assembler::REX_WX);
2477 }
2478 } else {
2479 if ($mem$$index < 8) {
2480 emit_opcode(cbuf, Assembler::REX_WB);
2481 } else {
2482 emit_opcode(cbuf, Assembler::REX_WXB);
2483 }
2484 }
2485 } else {
2486 if ($mem$$base < 8) {
2487 if ($mem$$index < 8) {
2488 emit_opcode(cbuf, Assembler::REX_WR);
2489 } else {
2490 emit_opcode(cbuf, Assembler::REX_WRX);
2491 }
2492 } else {
2493 if ($mem$$index < 8) {
2494 emit_opcode(cbuf, Assembler::REX_WRB);
2495 } else {
2496 emit_opcode(cbuf, Assembler::REX_WRXB);
2497 }
2498 }
2499 }
2500 %}
2501
2502 enc_class reg_mem(rRegI ereg, memory mem)
2503 %{
2504 // High registers handle in encode_RegMem
2505 int reg = $ereg$$reg;
2506 int base = $mem$$base;
2507 int index = $mem$$index;
2508 int scale = $mem$$scale;
2509 int disp = $mem$$disp;
2510 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2511
2512 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2513 %}
2514
2515 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2516 %{
2517 int rm_byte_opcode = $rm_opcode$$constant;
2518
2519 // High registers handle in encode_RegMem
2520 int base = $mem$$base;
2521 int index = $mem$$index;
2522 int scale = $mem$$scale;
2523 int displace = $mem$$disp;
2524
2525 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2526 // working with static
2527 // globals
2528 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2529 disp_reloc);
2530 %}
2531
2532 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2533 %{
2534 int reg_encoding = $dst$$reg;
2535 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2536 int index = 0x04; // 0x04 indicates no index
2537 int scale = 0x00; // 0x00 indicates no scale
2538 int displace = $src1$$constant; // 0x00 indicates no displacement
2539 relocInfo::relocType disp_reloc = relocInfo::none;
2540 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2541 disp_reloc);
2542 %}
2543
2544 enc_class neg_reg(rRegI dst)
2545 %{
2546 int dstenc = $dst$$reg;
2547 if (dstenc >= 8) {
2548 emit_opcode(cbuf, Assembler::REX_B);
2549 dstenc -= 8;
2550 }
2551 // NEG $dst
2552 emit_opcode(cbuf, 0xF7);
2553 emit_rm(cbuf, 0x3, 0x03, dstenc);
2554 %}
2555
2556 enc_class neg_reg_wide(rRegI dst)
2557 %{
2558 int dstenc = $dst$$reg;
2559 if (dstenc < 8) {
2560 emit_opcode(cbuf, Assembler::REX_W);
2561 } else {
2562 emit_opcode(cbuf, Assembler::REX_WB);
2563 dstenc -= 8;
2564 }
2565 // NEG $dst
2566 emit_opcode(cbuf, 0xF7);
2567 emit_rm(cbuf, 0x3, 0x03, dstenc);
2568 %}
2569
2570 enc_class setLT_reg(rRegI dst)
2571 %{
2572 int dstenc = $dst$$reg;
2573 if (dstenc >= 8) {
2574 emit_opcode(cbuf, Assembler::REX_B);
2575 dstenc -= 8;
2576 } else if (dstenc >= 4) {
2577 emit_opcode(cbuf, Assembler::REX);
2578 }
2579 // SETLT $dst
2580 emit_opcode(cbuf, 0x0F);
2581 emit_opcode(cbuf, 0x9C);
2582 emit_rm(cbuf, 0x3, 0x0, dstenc);
2583 %}
2584
2585 enc_class setNZ_reg(rRegI dst)
2586 %{
2587 int dstenc = $dst$$reg;
2588 if (dstenc >= 8) {
2589 emit_opcode(cbuf, Assembler::REX_B);
2590 dstenc -= 8;
2591 } else if (dstenc >= 4) {
2592 emit_opcode(cbuf, Assembler::REX);
2593 }
2594 // SETNZ $dst
2595 emit_opcode(cbuf, 0x0F);
2596 emit_opcode(cbuf, 0x95);
2597 emit_rm(cbuf, 0x3, 0x0, dstenc);
2598 %}
2599
2600
2601 // Compare the lonogs and set -1, 0, or 1 into dst
2602 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2603 %{
2604 int src1enc = $src1$$reg;
2605 int src2enc = $src2$$reg;
2606 int dstenc = $dst$$reg;
2607
2608 // cmpq $src1, $src2
2609 if (src1enc < 8) {
2610 if (src2enc < 8) {
2611 emit_opcode(cbuf, Assembler::REX_W);
2612 } else {
2613 emit_opcode(cbuf, Assembler::REX_WB);
2614 }
2615 } else {
2616 if (src2enc < 8) {
2617 emit_opcode(cbuf, Assembler::REX_WR);
2618 } else {
2619 emit_opcode(cbuf, Assembler::REX_WRB);
2620 }
2621 }
2622 emit_opcode(cbuf, 0x3B);
2623 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2624
2625 // movl $dst, -1
2626 if (dstenc >= 8) {
2627 emit_opcode(cbuf, Assembler::REX_B);
2628 }
2629 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2630 emit_d32(cbuf, -1);
2631
2632 // jl,s done
2633 emit_opcode(cbuf, 0x7C);
2634 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2635
2636 // setne $dst
2637 if (dstenc >= 4) {
2638 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2639 }
2640 emit_opcode(cbuf, 0x0F);
2641 emit_opcode(cbuf, 0x95);
2642 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2643
2644 // movzbl $dst, $dst
2645 if (dstenc >= 4) {
2646 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2647 }
2648 emit_opcode(cbuf, 0x0F);
2649 emit_opcode(cbuf, 0xB6);
2650 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2651 %}
2652
2653 enc_class Push_ResultXD(regD dst) %{
2654 MacroAssembler _masm(&cbuf);
2655 __ fstp_d(Address(rsp, 0));
2656 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2657 __ addptr(rsp, 8);
2658 %}
2659
2660 enc_class Push_SrcXD(regD src) %{
2661 MacroAssembler _masm(&cbuf);
2662 __ subptr(rsp, 8);
2663 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2664 __ fld_d(Address(rsp, 0));
2665 %}
2666
2667
2668 enc_class enc_rethrow()
2669 %{
2670 cbuf.set_insts_mark();
2671 emit_opcode(cbuf, 0xE9); // jmp entry
2672 emit_d32_reloc(cbuf,
2673 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2674 runtime_call_Relocation::spec(),
2675 RELOC_DISP32);
2676 %}
2677
2678 %}
2679
2680
2681
2682 //----------FRAME--------------------------------------------------------------
2683 // Definition of frame structure and management information.
2684 //
2685 // S T A C K L A Y O U T Allocators stack-slot number
2686 // | (to get allocators register number
2687 // G Owned by | | v add OptoReg::stack0())
2688 // r CALLER | |
2689 // o | +--------+ pad to even-align allocators stack-slot
2690 // w V | pad0 | numbers; owned by CALLER
2691 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2692 // h ^ | in | 5
2693 // | | args | 4 Holes in incoming args owned by SELF
2694 // | | | | 3
2695 // | | +--------+
2696 // V | | old out| Empty on Intel, window on Sparc
2697 // | old |preserve| Must be even aligned.
2698 // | SP-+--------+----> Matcher::_old_SP, even aligned
2699 // | | in | 3 area for Intel ret address
2700 // Owned by |preserve| Empty on Sparc.
2701 // SELF +--------+
2702 // | | pad2 | 2 pad to align old SP
2703 // | +--------+ 1
2704 // | | locks | 0
2705 // | +--------+----> OptoReg::stack0(), even aligned
2706 // | | pad1 | 11 pad to align new SP
2707 // | +--------+
2708 // | | | 10
2709 // | | spills | 9 spills
2710 // V | | 8 (pad0 slot for callee)
2711 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2712 // ^ | out | 7
2713 // | | args | 6 Holes in outgoing args owned by CALLEE
2714 // Owned by +--------+
2715 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2716 // | new |preserve| Must be even-aligned.
2717 // | SP-+--------+----> Matcher::_new_SP, even aligned
2718 // | | |
2719 //
2720 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2721 // known from SELF's arguments and the Java calling convention.
2722 // Region 6-7 is determined per call site.
2723 // Note 2: If the calling convention leaves holes in the incoming argument
2724 // area, those holes are owned by SELF. Holes in the outgoing area
2725 // are owned by the CALLEE. Holes should not be nessecary in the
2726 // incoming area, as the Java calling convention is completely under
2727 // the control of the AD file. Doubles can be sorted and packed to
2728 // avoid holes. Holes in the outgoing arguments may be nessecary for
2729 // varargs C calling conventions.
2730 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2731 // even aligned with pad0 as needed.
2732 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2733 // region 6-11 is even aligned; it may be padded out more so that
2734 // the region from SP to FP meets the minimum stack alignment.
2735 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2736 // alignment. Region 11, pad1, may be dynamically extended so that
2737 // SP meets the minimum alignment.
2738
2739 frame
2740 %{
2741 // What direction does stack grow in (assumed to be same for C & Java)
2742 stack_direction(TOWARDS_LOW);
2743
2744 // These three registers define part of the calling convention
2745 // between compiled code and the interpreter.
2746 inline_cache_reg(RAX); // Inline Cache Register
2747 interpreter_method_oop_reg(RBX); // Method Oop Register when
2748 // calling interpreter
2749
2750 // Optional: name the operand used by cisc-spilling to access
2751 // [stack_pointer + offset]
2752 cisc_spilling_operand_name(indOffset32);
2753
2754 // Number of stack slots consumed by locking an object
2755 sync_stack_slots(2);
2756
2757 // Compiled code's Frame Pointer
2758 frame_pointer(RSP);
2759
2760 // Interpreter stores its frame pointer in a register which is
2761 // stored to the stack by I2CAdaptors.
2762 // I2CAdaptors convert from interpreted java to compiled java.
2763 interpreter_frame_pointer(RBP);
2764
2765 // Stack alignment requirement
2766 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2767
2768 // Number of stack slots between incoming argument block and the start of
2769 // a new frame. The PROLOG must add this many slots to the stack. The
2770 // EPILOG must remove this many slots. amd64 needs two slots for
2771 // return address.
2772 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2773
2774 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2775 // for calls to C. Supports the var-args backing area for register parms.
2776 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2777
2778 // The after-PROLOG location of the return address. Location of
2779 // return address specifies a type (REG or STACK) and a number
2780 // representing the register number (i.e. - use a register name) or
2781 // stack slot.
2782 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2783 // Otherwise, it is above the locks and verification slot and alignment word
2784 return_addr(STACK - 2 +
2785 round_to((Compile::current()->in_preserve_stack_slots() +
2786 Compile::current()->fixed_slots()),
2787 stack_alignment_in_slots()));
2788
2789 // Body of function which returns an integer array locating
2790 // arguments either in registers or in stack slots. Passed an array
2791 // of ideal registers called "sig" and a "length" count. Stack-slot
2792 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2793 // arguments for a CALLEE. Incoming stack arguments are
2794 // automatically biased by the preserve_stack_slots field above.
2795
2796 calling_convention
2797 %{
2798 // No difference between ingoing/outgoing just pass false
2799 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2800 %}
2801
2802 c_calling_convention
2803 %{
2804 // This is obviously always outgoing
2805 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2806 %}
2807
2808 // Location of compiled Java return values. Same as C for now.
2809 return_value
2810 %{
2811 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2812 "only return normal values");
2813
2814 static const int lo[Op_RegL + 1] = {
2815 0,
2816 0,
2817 RAX_num, // Op_RegN
2818 RAX_num, // Op_RegI
2819 RAX_num, // Op_RegP
2820 XMM0_num, // Op_RegF
2821 XMM0_num, // Op_RegD
2822 RAX_num // Op_RegL
2823 };
2824 static const int hi[Op_RegL + 1] = {
2825 0,
2826 0,
2827 OptoReg::Bad, // Op_RegN
2828 OptoReg::Bad, // Op_RegI
2829 RAX_H_num, // Op_RegP
2830 OptoReg::Bad, // Op_RegF
2831 XMM0b_num, // Op_RegD
2832 RAX_H_num // Op_RegL
2833 };
2834 // Excluded flags and vector registers.
2835 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 5, "missing type");
2836 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2837 %}
2838 %}
2839
2840 //----------ATTRIBUTES---------------------------------------------------------
2841 //----------Operand Attributes-------------------------------------------------
2842 op_attrib op_cost(0); // Required cost attribute
2843
2844 //----------Instruction Attributes---------------------------------------------
2845 ins_attrib ins_cost(100); // Required cost attribute
2846 ins_attrib ins_size(8); // Required size attribute (in bits)
2847 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2848 // a non-matching short branch variant
2849 // of some long branch?
2850 ins_attrib ins_alignment(1); // Required alignment attribute (must
2851 // be a power of 2) specifies the
2852 // alignment that some part of the
2853 // instruction (not necessarily the
2854 // start) requires. If > 1, a
2855 // compute_padding() function must be
2856 // provided for the instruction
2857
2858 //----------OPERANDS-----------------------------------------------------------
2859 // Operand definitions must precede instruction definitions for correct parsing
2860 // in the ADLC because operands constitute user defined types which are used in
2861 // instruction definitions.
2862
2863 //----------Simple Operands----------------------------------------------------
2864 // Immediate Operands
2865 // Integer Immediate
2866 operand immI()
2867 %{
2868 match(ConI);
2869
2870 op_cost(10);
2871 format %{ %}
2872 interface(CONST_INTER);
2873 %}
2874
2875 // Constant for test vs zero
2876 operand immI0()
2877 %{
2878 predicate(n->get_int() == 0);
2879 match(ConI);
2880
2881 op_cost(0);
2882 format %{ %}
2883 interface(CONST_INTER);
2884 %}
2885
2886 // Constant for increment
2887 operand immI1()
2888 %{
2889 predicate(n->get_int() == 1);
2890 match(ConI);
2891
2892 op_cost(0);
2893 format %{ %}
2894 interface(CONST_INTER);
2895 %}
2896
2897 // Constant for decrement
2898 operand immI_M1()
2899 %{
2900 predicate(n->get_int() == -1);
2901 match(ConI);
2902
2903 op_cost(0);
2904 format %{ %}
2905 interface(CONST_INTER);
2906 %}
2907
2908 // Valid scale values for addressing modes
2909 operand immI2()
2910 %{
2911 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2912 match(ConI);
2913
2914 format %{ %}
2915 interface(CONST_INTER);
2916 %}
2917
2918 operand immI8()
2919 %{
2920 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2921 match(ConI);
2922
2923 op_cost(5);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 operand immI16()
2929 %{
2930 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2931 match(ConI);
2932
2933 op_cost(10);
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 // Int Immediate non-negative
2939 operand immU31()
2940 %{
2941 predicate(n->get_int() >= 0);
2942 match(ConI);
2943
2944 op_cost(0);
2945 format %{ %}
2946 interface(CONST_INTER);
2947 %}
2948
2949 // Constant for long shifts
2950 operand immI_32()
2951 %{
2952 predicate( n->get_int() == 32 );
2953 match(ConI);
2954
2955 op_cost(0);
2956 format %{ %}
2957 interface(CONST_INTER);
2958 %}
2959
2960 // Constant for long shifts
2961 operand immI_64()
2962 %{
2963 predicate( n->get_int() == 64 );
2964 match(ConI);
2965
2966 op_cost(0);
2967 format %{ %}
2968 interface(CONST_INTER);
2969 %}
2970
2971 // Pointer Immediate
2972 operand immP()
2973 %{
2974 match(ConP);
2975
2976 op_cost(10);
2977 format %{ %}
2978 interface(CONST_INTER);
2979 %}
2980
2981 // NULL Pointer Immediate
2982 operand immP0()
2983 %{
2984 predicate(n->get_ptr() == 0);
2985 match(ConP);
2986
2987 op_cost(5);
2988 format %{ %}
2989 interface(CONST_INTER);
2990 %}
2991
2992 // Pointer Immediate
2993 operand immN() %{
2994 match(ConN);
2995
2996 op_cost(10);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 operand immNKlass() %{
3002 match(ConNKlass);
3003
3004 op_cost(10);
3005 format %{ %}
3006 interface(CONST_INTER);
3007 %}
3008
3009 // NULL Pointer Immediate
3010 operand immN0() %{
3011 predicate(n->get_narrowcon() == 0);
3012 match(ConN);
3013
3014 op_cost(5);
3015 format %{ %}
3016 interface(CONST_INTER);
3017 %}
3018
3019 operand immP31()
3020 %{
3021 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3022 && (n->get_ptr() >> 31) == 0);
3023 match(ConP);
3024
3025 op_cost(5);
3026 format %{ %}
3027 interface(CONST_INTER);
3028 %}
3029
3030
3031 // Long Immediate
3032 operand immL()
3033 %{
3034 match(ConL);
3035
3036 op_cost(20);
3037 format %{ %}
3038 interface(CONST_INTER);
3039 %}
3040
3041 // Long Immediate 8-bit
3042 operand immL8()
3043 %{
3044 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3045 match(ConL);
3046
3047 op_cost(5);
3048 format %{ %}
3049 interface(CONST_INTER);
3050 %}
3051
3052 // Long Immediate 32-bit unsigned
3053 operand immUL32()
3054 %{
3055 predicate(n->get_long() == (unsigned int) (n->get_long()));
3056 match(ConL);
3057
3058 op_cost(10);
3059 format %{ %}
3060 interface(CONST_INTER);
3061 %}
3062
3063 // Long Immediate 32-bit signed
3064 operand immL32()
3065 %{
3066 predicate(n->get_long() == (int) (n->get_long()));
3067 match(ConL);
3068
3069 op_cost(15);
3070 format %{ %}
3071 interface(CONST_INTER);
3072 %}
3073
3074 // Long Immediate zero
3075 operand immL0()
3076 %{
3077 predicate(n->get_long() == 0L);
3078 match(ConL);
3079
3080 op_cost(10);
3081 format %{ %}
3082 interface(CONST_INTER);
3083 %}
3084
3085 // Constant for increment
3086 operand immL1()
3087 %{
3088 predicate(n->get_long() == 1);
3089 match(ConL);
3090
3091 format %{ %}
3092 interface(CONST_INTER);
3093 %}
3094
3095 // Constant for decrement
3096 operand immL_M1()
3097 %{
3098 predicate(n->get_long() == -1);
3099 match(ConL);
3100
3101 format %{ %}
3102 interface(CONST_INTER);
3103 %}
3104
3105 // Long Immediate: the value 10
3106 operand immL10()
3107 %{
3108 predicate(n->get_long() == 10);
3109 match(ConL);
3110
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Long immediate from 0 to 127.
3116 // Used for a shorter form of long mul by 10.
3117 operand immL_127()
3118 %{
3119 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3120 match(ConL);
3121
3122 op_cost(10);
3123 format %{ %}
3124 interface(CONST_INTER);
3125 %}
3126
3127 // Long Immediate: low 32-bit mask
3128 operand immL_32bits()
3129 %{
3130 predicate(n->get_long() == 0xFFFFFFFFL);
3131 match(ConL);
3132 op_cost(20);
3133
3134 format %{ %}
3135 interface(CONST_INTER);
3136 %}
3137
3138 // Float Immediate zero
3139 operand immF0()
3140 %{
3141 predicate(jint_cast(n->getf()) == 0);
3142 match(ConF);
3143
3144 op_cost(5);
3145 format %{ %}
3146 interface(CONST_INTER);
3147 %}
3148
3149 // Float Immediate
3150 operand immF()
3151 %{
3152 match(ConF);
3153
3154 op_cost(15);
3155 format %{ %}
3156 interface(CONST_INTER);
3157 %}
3158
3159 // Double Immediate zero
3160 operand immD0()
3161 %{
3162 predicate(jlong_cast(n->getd()) == 0);
3163 match(ConD);
3164
3165 op_cost(5);
3166 format %{ %}
3167 interface(CONST_INTER);
3168 %}
3169
3170 // Double Immediate
3171 operand immD()
3172 %{
3173 match(ConD);
3174
3175 op_cost(15);
3176 format %{ %}
3177 interface(CONST_INTER);
3178 %}
3179
3180 // Immediates for special shifts (sign extend)
3181
3182 // Constants for increment
3183 operand immI_16()
3184 %{
3185 predicate(n->get_int() == 16);
3186 match(ConI);
3187
3188 format %{ %}
3189 interface(CONST_INTER);
3190 %}
3191
3192 operand immI_24()
3193 %{
3194 predicate(n->get_int() == 24);
3195 match(ConI);
3196
3197 format %{ %}
3198 interface(CONST_INTER);
3199 %}
3200
3201 // Constant for byte-wide masking
3202 operand immI_255()
3203 %{
3204 predicate(n->get_int() == 255);
3205 match(ConI);
3206
3207 format %{ %}
3208 interface(CONST_INTER);
3209 %}
3210
3211 // Constant for short-wide masking
3212 operand immI_65535()
3213 %{
3214 predicate(n->get_int() == 65535);
3215 match(ConI);
3216
3217 format %{ %}
3218 interface(CONST_INTER);
3219 %}
3220
3221 // Constant for byte-wide masking
3222 operand immL_255()
3223 %{
3224 predicate(n->get_long() == 255);
3225 match(ConL);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Constant for short-wide masking
3232 operand immL_65535()
3233 %{
3234 predicate(n->get_long() == 65535);
3235 match(ConL);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Register Operands
3242 // Integer Register
3243 operand rRegI()
3244 %{
3245 constraint(ALLOC_IN_RC(int_reg));
3246 match(RegI);
3247
3248 match(rax_RegI);
3249 match(rbx_RegI);
3250 match(rcx_RegI);
3251 match(rdx_RegI);
3252 match(rdi_RegI);
3253
3254 format %{ %}
3255 interface(REG_INTER);
3256 %}
3257
3258 // Special Registers
3259 operand rax_RegI()
3260 %{
3261 constraint(ALLOC_IN_RC(int_rax_reg));
3262 match(RegI);
3263 match(rRegI);
3264
3265 format %{ "RAX" %}
3266 interface(REG_INTER);
3267 %}
3268
3269 // Special Registers
3270 operand rbx_RegI()
3271 %{
3272 constraint(ALLOC_IN_RC(int_rbx_reg));
3273 match(RegI);
3274 match(rRegI);
3275
3276 format %{ "RBX" %}
3277 interface(REG_INTER);
3278 %}
3279
3280 operand rcx_RegI()
3281 %{
3282 constraint(ALLOC_IN_RC(int_rcx_reg));
3283 match(RegI);
3284 match(rRegI);
3285
3286 format %{ "RCX" %}
3287 interface(REG_INTER);
3288 %}
3289
3290 operand rdx_RegI()
3291 %{
3292 constraint(ALLOC_IN_RC(int_rdx_reg));
3293 match(RegI);
3294 match(rRegI);
3295
3296 format %{ "RDX" %}
3297 interface(REG_INTER);
3298 %}
3299
3300 operand rdi_RegI()
3301 %{
3302 constraint(ALLOC_IN_RC(int_rdi_reg));
3303 match(RegI);
3304 match(rRegI);
3305
3306 format %{ "RDI" %}
3307 interface(REG_INTER);
3308 %}
3309
3310 operand no_rcx_RegI()
3311 %{
3312 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3313 match(RegI);
3314 match(rax_RegI);
3315 match(rbx_RegI);
3316 match(rdx_RegI);
3317 match(rdi_RegI);
3318
3319 format %{ %}
3320 interface(REG_INTER);
3321 %}
3322
3323 operand no_rax_rdx_RegI()
3324 %{
3325 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3326 match(RegI);
3327 match(rbx_RegI);
3328 match(rcx_RegI);
3329 match(rdi_RegI);
3330
3331 format %{ %}
3332 interface(REG_INTER);
3333 %}
3334
3335 // Pointer Register
3336 operand any_RegP()
3337 %{
3338 constraint(ALLOC_IN_RC(any_reg));
3339 match(RegP);
3340 match(rax_RegP);
3341 match(rbx_RegP);
3342 match(rdi_RegP);
3343 match(rsi_RegP);
3344 match(rbp_RegP);
3345 match(r15_RegP);
3346 match(rRegP);
3347
3348 format %{ %}
3349 interface(REG_INTER);
3350 %}
3351
3352 operand rRegP()
3353 %{
3354 constraint(ALLOC_IN_RC(ptr_reg));
3355 match(RegP);
3356 match(rax_RegP);
3357 match(rbx_RegP);
3358 match(rdi_RegP);
3359 match(rsi_RegP);
3360 match(rbp_RegP); // See Q&A below about
3361 match(r15_RegP); // r15_RegP and rbp_RegP.
3362
3363 format %{ %}
3364 interface(REG_INTER);
3365 %}
3366
3367 operand rRegN() %{
3368 constraint(ALLOC_IN_RC(int_reg));
3369 match(RegN);
3370
3371 format %{ %}
3372 interface(REG_INTER);
3373 %}
3374
3375 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3376 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3377 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3378 // The output of an instruction is controlled by the allocator, which respects
3379 // register class masks, not match rules. Unless an instruction mentions
3380 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3381 // by the allocator as an input.
3382 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3383 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3384 // result, RBP is not included in the output of the instruction either.
3385
3386 operand no_rax_RegP()
3387 %{
3388 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3389 match(RegP);
3390 match(rbx_RegP);
3391 match(rsi_RegP);
3392 match(rdi_RegP);
3393
3394 format %{ %}
3395 interface(REG_INTER);
3396 %}
3397
3398 // This operand is not allowed to use RBP even if
3399 // RBP is not used to hold the frame pointer.
3400 operand no_rbp_RegP()
3401 %{
3402 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3403 match(RegP);
3404 match(rbx_RegP);
3405 match(rsi_RegP);
3406 match(rdi_RegP);
3407
3408 format %{ %}
3409 interface(REG_INTER);
3410 %}
3411
3412 operand no_rax_rbx_RegP()
3413 %{
3414 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3415 match(RegP);
3416 match(rsi_RegP);
3417 match(rdi_RegP);
3418
3419 format %{ %}
3420 interface(REG_INTER);
3421 %}
3422
3423 // Special Registers
3424 // Return a pointer value
3425 operand rax_RegP()
3426 %{
3427 constraint(ALLOC_IN_RC(ptr_rax_reg));
3428 match(RegP);
3429 match(rRegP);
3430
3431 format %{ %}
3432 interface(REG_INTER);
3433 %}
3434
3435 // Special Registers
3436 // Return a compressed pointer value
3437 operand rax_RegN()
3438 %{
3439 constraint(ALLOC_IN_RC(int_rax_reg));
3440 match(RegN);
3441 match(rRegN);
3442
3443 format %{ %}
3444 interface(REG_INTER);
3445 %}
3446
3447 // Used in AtomicAdd
3448 operand rbx_RegP()
3449 %{
3450 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3451 match(RegP);
3452 match(rRegP);
3453
3454 format %{ %}
3455 interface(REG_INTER);
3456 %}
3457
3458 operand rsi_RegP()
3459 %{
3460 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3461 match(RegP);
3462 match(rRegP);
3463
3464 format %{ %}
3465 interface(REG_INTER);
3466 %}
3467
3468 // Used in rep stosq
3469 operand rdi_RegP()
3470 %{
3471 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3472 match(RegP);
3473 match(rRegP);
3474
3475 format %{ %}
3476 interface(REG_INTER);
3477 %}
3478
3479 operand r15_RegP()
3480 %{
3481 constraint(ALLOC_IN_RC(ptr_r15_reg));
3482 match(RegP);
3483 match(rRegP);
3484
3485 format %{ %}
3486 interface(REG_INTER);
3487 %}
3488
3489 operand rRegL()
3490 %{
3491 constraint(ALLOC_IN_RC(long_reg));
3492 match(RegL);
3493 match(rax_RegL);
3494 match(rdx_RegL);
3495
3496 format %{ %}
3497 interface(REG_INTER);
3498 %}
3499
3500 // Special Registers
3501 operand no_rax_rdx_RegL()
3502 %{
3503 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3504 match(RegL);
3505 match(rRegL);
3506
3507 format %{ %}
3508 interface(REG_INTER);
3509 %}
3510
3511 operand no_rax_RegL()
3512 %{
3513 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3514 match(RegL);
3515 match(rRegL);
3516 match(rdx_RegL);
3517
3518 format %{ %}
3519 interface(REG_INTER);
3520 %}
3521
3522 operand no_rcx_RegL()
3523 %{
3524 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3525 match(RegL);
3526 match(rRegL);
3527
3528 format %{ %}
3529 interface(REG_INTER);
3530 %}
3531
3532 operand rax_RegL()
3533 %{
3534 constraint(ALLOC_IN_RC(long_rax_reg));
3535 match(RegL);
3536 match(rRegL);
3537
3538 format %{ "RAX" %}
3539 interface(REG_INTER);
3540 %}
3541
3542 operand rcx_RegL()
3543 %{
3544 constraint(ALLOC_IN_RC(long_rcx_reg));
3545 match(RegL);
3546 match(rRegL);
3547
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand rdx_RegL()
3553 %{
3554 constraint(ALLOC_IN_RC(long_rdx_reg));
3555 match(RegL);
3556 match(rRegL);
3557
3558 format %{ %}
3559 interface(REG_INTER);
3560 %}
3561
3562 // Flags register, used as output of compare instructions
3563 operand rFlagsReg()
3564 %{
3565 constraint(ALLOC_IN_RC(int_flags));
3566 match(RegFlags);
3567
3568 format %{ "RFLAGS" %}
3569 interface(REG_INTER);
3570 %}
3571
3572 // Flags register, used as output of FLOATING POINT compare instructions
3573 operand rFlagsRegU()
3574 %{
3575 constraint(ALLOC_IN_RC(int_flags));
3576 match(RegFlags);
3577
3578 format %{ "RFLAGS_U" %}
3579 interface(REG_INTER);
3580 %}
3581
3582 operand rFlagsRegUCF() %{
3583 constraint(ALLOC_IN_RC(int_flags));
3584 match(RegFlags);
3585 predicate(false);
3586
3587 format %{ "RFLAGS_U_CF" %}
3588 interface(REG_INTER);
3589 %}
3590
3591 // Float register operands
3592 operand regF()
3593 %{
3594 constraint(ALLOC_IN_RC(float_reg));
3595 match(RegF);
3596
3597 format %{ %}
3598 interface(REG_INTER);
3599 %}
3600
3601 // Double register operands
3602 operand regD()
3603 %{
3604 constraint(ALLOC_IN_RC(double_reg));
3605 match(RegD);
3606
3607 format %{ %}
3608 interface(REG_INTER);
3609 %}
3610
3611 //----------Memory Operands----------------------------------------------------
3612 // Direct Memory Operand
3613 // operand direct(immP addr)
3614 // %{
3615 // match(addr);
3616
3617 // format %{ "[$addr]" %}
3618 // interface(MEMORY_INTER) %{
3619 // base(0xFFFFFFFF);
3620 // index(0x4);
3621 // scale(0x0);
3622 // disp($addr);
3623 // %}
3624 // %}
3625
3626 // Indirect Memory Operand
3627 operand indirect(any_RegP reg)
3628 %{
3629 constraint(ALLOC_IN_RC(ptr_reg));
3630 match(reg);
3631
3632 format %{ "[$reg]" %}
3633 interface(MEMORY_INTER) %{
3634 base($reg);
3635 index(0x4);
3636 scale(0x0);
3637 disp(0x0);
3638 %}
3639 %}
3640
3641 // Indirect Memory Plus Short Offset Operand
3642 operand indOffset8(any_RegP reg, immL8 off)
3643 %{
3644 constraint(ALLOC_IN_RC(ptr_reg));
3645 match(AddP reg off);
3646
3647 format %{ "[$reg + $off (8-bit)]" %}
3648 interface(MEMORY_INTER) %{
3649 base($reg);
3650 index(0x4);
3651 scale(0x0);
3652 disp($off);
3653 %}
3654 %}
3655
3656 // Indirect Memory Plus Long Offset Operand
3657 operand indOffset32(any_RegP reg, immL32 off)
3658 %{
3659 constraint(ALLOC_IN_RC(ptr_reg));
3660 match(AddP reg off);
3661
3662 format %{ "[$reg + $off (32-bit)]" %}
3663 interface(MEMORY_INTER) %{
3664 base($reg);
3665 index(0x4);
3666 scale(0x0);
3667 disp($off);
3668 %}
3669 %}
3670
3671 // Indirect Memory Plus Index Register Plus Offset Operand
3672 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3673 %{
3674 constraint(ALLOC_IN_RC(ptr_reg));
3675 match(AddP (AddP reg lreg) off);
3676
3677 op_cost(10);
3678 format %{"[$reg + $off + $lreg]" %}
3679 interface(MEMORY_INTER) %{
3680 base($reg);
3681 index($lreg);
3682 scale(0x0);
3683 disp($off);
3684 %}
3685 %}
3686
3687 // Indirect Memory Plus Index Register Plus Offset Operand
3688 operand indIndex(any_RegP reg, rRegL lreg)
3689 %{
3690 constraint(ALLOC_IN_RC(ptr_reg));
3691 match(AddP reg lreg);
3692
3693 op_cost(10);
3694 format %{"[$reg + $lreg]" %}
3695 interface(MEMORY_INTER) %{
3696 base($reg);
3697 index($lreg);
3698 scale(0x0);
3699 disp(0x0);
3700 %}
3701 %}
3702
3703 // Indirect Memory Times Scale Plus Index Register
3704 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3705 %{
3706 constraint(ALLOC_IN_RC(ptr_reg));
3707 match(AddP reg (LShiftL lreg scale));
3708
3709 op_cost(10);
3710 format %{"[$reg + $lreg << $scale]" %}
3711 interface(MEMORY_INTER) %{
3712 base($reg);
3713 index($lreg);
3714 scale($scale);
3715 disp(0x0);
3716 %}
3717 %}
3718
3719 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3720 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3721 %{
3722 constraint(ALLOC_IN_RC(ptr_reg));
3723 match(AddP (AddP reg (LShiftL lreg scale)) off);
3724
3725 op_cost(10);
3726 format %{"[$reg + $off + $lreg << $scale]" %}
3727 interface(MEMORY_INTER) %{
3728 base($reg);
3729 index($lreg);
3730 scale($scale);
3731 disp($off);
3732 %}
3733 %}
3734
3735 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3736 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3737 %{
3738 constraint(ALLOC_IN_RC(ptr_reg));
3739 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3740 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3741
3742 op_cost(10);
3743 format %{"[$reg + $off + $idx << $scale]" %}
3744 interface(MEMORY_INTER) %{
3745 base($reg);
3746 index($idx);
3747 scale($scale);
3748 disp($off);
3749 %}
3750 %}
3751
3752 // Indirect Narrow Oop Plus Offset Operand
3753 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3754 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3755 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3756 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3757 constraint(ALLOC_IN_RC(ptr_reg));
3758 match(AddP (DecodeN reg) off);
3759
3760 op_cost(10);
3761 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3762 interface(MEMORY_INTER) %{
3763 base(0xc); // R12
3764 index($reg);
3765 scale(0x3);
3766 disp($off);
3767 %}
3768 %}
3769
3770 // Indirect Memory Operand
3771 operand indirectNarrow(rRegN reg)
3772 %{
3773 predicate(Universe::narrow_oop_shift() == 0);
3774 constraint(ALLOC_IN_RC(ptr_reg));
3775 match(DecodeN reg);
3776
3777 format %{ "[$reg]" %}
3778 interface(MEMORY_INTER) %{
3779 base($reg);
3780 index(0x4);
3781 scale(0x0);
3782 disp(0x0);
3783 %}
3784 %}
3785
3786 // Indirect Memory Plus Short Offset Operand
3787 operand indOffset8Narrow(rRegN reg, immL8 off)
3788 %{
3789 predicate(Universe::narrow_oop_shift() == 0);
3790 constraint(ALLOC_IN_RC(ptr_reg));
3791 match(AddP (DecodeN reg) off);
3792
3793 format %{ "[$reg + $off (8-bit)]" %}
3794 interface(MEMORY_INTER) %{
3795 base($reg);
3796 index(0x4);
3797 scale(0x0);
3798 disp($off);
3799 %}
3800 %}
3801
3802 // Indirect Memory Plus Long Offset Operand
3803 operand indOffset32Narrow(rRegN reg, immL32 off)
3804 %{
3805 predicate(Universe::narrow_oop_shift() == 0);
3806 constraint(ALLOC_IN_RC(ptr_reg));
3807 match(AddP (DecodeN reg) off);
3808
3809 format %{ "[$reg + $off (32-bit)]" %}
3810 interface(MEMORY_INTER) %{
3811 base($reg);
3812 index(0x4);
3813 scale(0x0);
3814 disp($off);
3815 %}
3816 %}
3817
3818 // Indirect Memory Plus Index Register Plus Offset Operand
3819 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3820 %{
3821 predicate(Universe::narrow_oop_shift() == 0);
3822 constraint(ALLOC_IN_RC(ptr_reg));
3823 match(AddP (AddP (DecodeN reg) lreg) off);
3824
3825 op_cost(10);
3826 format %{"[$reg + $off + $lreg]" %}
3827 interface(MEMORY_INTER) %{
3828 base($reg);
3829 index($lreg);
3830 scale(0x0);
3831 disp($off);
3832 %}
3833 %}
3834
3835 // Indirect Memory Plus Index Register Plus Offset Operand
3836 operand indIndexNarrow(rRegN reg, rRegL lreg)
3837 %{
3838 predicate(Universe::narrow_oop_shift() == 0);
3839 constraint(ALLOC_IN_RC(ptr_reg));
3840 match(AddP (DecodeN reg) lreg);
3841
3842 op_cost(10);
3843 format %{"[$reg + $lreg]" %}
3844 interface(MEMORY_INTER) %{
3845 base($reg);
3846 index($lreg);
3847 scale(0x0);
3848 disp(0x0);
3849 %}
3850 %}
3851
3852 // Indirect Memory Times Scale Plus Index Register
3853 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3854 %{
3855 predicate(Universe::narrow_oop_shift() == 0);
3856 constraint(ALLOC_IN_RC(ptr_reg));
3857 match(AddP (DecodeN reg) (LShiftL lreg scale));
3858
3859 op_cost(10);
3860 format %{"[$reg + $lreg << $scale]" %}
3861 interface(MEMORY_INTER) %{
3862 base($reg);
3863 index($lreg);
3864 scale($scale);
3865 disp(0x0);
3866 %}
3867 %}
3868
3869 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3870 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3871 %{
3872 predicate(Universe::narrow_oop_shift() == 0);
3873 constraint(ALLOC_IN_RC(ptr_reg));
3874 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3875
3876 op_cost(10);
3877 format %{"[$reg + $off + $lreg << $scale]" %}
3878 interface(MEMORY_INTER) %{
3879 base($reg);
3880 index($lreg);
3881 scale($scale);
3882 disp($off);
3883 %}
3884 %}
3885
3886 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3887 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3888 %{
3889 constraint(ALLOC_IN_RC(ptr_reg));
3890 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3891 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3892
3893 op_cost(10);
3894 format %{"[$reg + $off + $idx << $scale]" %}
3895 interface(MEMORY_INTER) %{
3896 base($reg);
3897 index($idx);
3898 scale($scale);
3899 disp($off);
3900 %}
3901 %}
3902
3903 //----------Special Memory Operands--------------------------------------------
3904 // Stack Slot Operand - This operand is used for loading and storing temporary
3905 // values on the stack where a match requires a value to
3906 // flow through memory.
3907 operand stackSlotP(sRegP reg)
3908 %{
3909 constraint(ALLOC_IN_RC(stack_slots));
3910 // No match rule because this operand is only generated in matching
3911
3912 format %{ "[$reg]" %}
3913 interface(MEMORY_INTER) %{
3914 base(0x4); // RSP
3915 index(0x4); // No Index
3916 scale(0x0); // No Scale
3917 disp($reg); // Stack Offset
3918 %}
3919 %}
3920
3921 operand stackSlotI(sRegI reg)
3922 %{
3923 constraint(ALLOC_IN_RC(stack_slots));
3924 // No match rule because this operand is only generated in matching
3925
3926 format %{ "[$reg]" %}
3927 interface(MEMORY_INTER) %{
3928 base(0x4); // RSP
3929 index(0x4); // No Index
3930 scale(0x0); // No Scale
3931 disp($reg); // Stack Offset
3932 %}
3933 %}
3934
3935 operand stackSlotF(sRegF reg)
3936 %{
3937 constraint(ALLOC_IN_RC(stack_slots));
3938 // No match rule because this operand is only generated in matching
3939
3940 format %{ "[$reg]" %}
3941 interface(MEMORY_INTER) %{
3942 base(0x4); // RSP
3943 index(0x4); // No Index
3944 scale(0x0); // No Scale
3945 disp($reg); // Stack Offset
3946 %}
3947 %}
3948
3949 operand stackSlotD(sRegD reg)
3950 %{
3951 constraint(ALLOC_IN_RC(stack_slots));
3952 // No match rule because this operand is only generated in matching
3953
3954 format %{ "[$reg]" %}
3955 interface(MEMORY_INTER) %{
3956 base(0x4); // RSP
3957 index(0x4); // No Index
3958 scale(0x0); // No Scale
3959 disp($reg); // Stack Offset
3960 %}
3961 %}
3962 operand stackSlotL(sRegL reg)
3963 %{
3964 constraint(ALLOC_IN_RC(stack_slots));
3965 // No match rule because this operand is only generated in matching
3966
3967 format %{ "[$reg]" %}
3968 interface(MEMORY_INTER) %{
3969 base(0x4); // RSP
3970 index(0x4); // No Index
3971 scale(0x0); // No Scale
3972 disp($reg); // Stack Offset
3973 %}
3974 %}
3975
3976 //----------Conditional Branch Operands----------------------------------------
3977 // Comparison Op - This is the operation of the comparison, and is limited to
3978 // the following set of codes:
3979 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3980 //
3981 // Other attributes of the comparison, such as unsignedness, are specified
3982 // by the comparison instruction that sets a condition code flags register.
3983 // That result is represented by a flags operand whose subtype is appropriate
3984 // to the unsignedness (etc.) of the comparison.
3985 //
3986 // Later, the instruction which matches both the Comparison Op (a Bool) and
3987 // the flags (produced by the Cmp) specifies the coding of the comparison op
3988 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3989
3990 // Comparision Code
3991 operand cmpOp()
3992 %{
3993 match(Bool);
3994
3995 format %{ "" %}
3996 interface(COND_INTER) %{
3997 equal(0x4, "e");
3998 not_equal(0x5, "ne");
3999 less(0xC, "l");
4000 greater_equal(0xD, "ge");
4001 less_equal(0xE, "le");
4002 greater(0xF, "g");
4003 overflow(0x0, "o");
4004 no_overflow(0x1, "no");
4005 %}
4006 %}
4007
4008 // Comparison Code, unsigned compare. Used by FP also, with
4009 // C2 (unordered) turned into GT or LT already. The other bits
4010 // C0 and C3 are turned into Carry & Zero flags.
4011 operand cmpOpU()
4012 %{
4013 match(Bool);
4014
4015 format %{ "" %}
4016 interface(COND_INTER) %{
4017 equal(0x4, "e");
4018 not_equal(0x5, "ne");
4019 less(0x2, "b");
4020 greater_equal(0x3, "nb");
4021 less_equal(0x6, "be");
4022 greater(0x7, "nbe");
4023 overflow(0x0, "o");
4024 no_overflow(0x1, "no");
4025 %}
4026 %}
4027
4028
4029 // Floating comparisons that don't require any fixup for the unordered case
4030 operand cmpOpUCF() %{
4031 match(Bool);
4032 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4033 n->as_Bool()->_test._test == BoolTest::ge ||
4034 n->as_Bool()->_test._test == BoolTest::le ||
4035 n->as_Bool()->_test._test == BoolTest::gt);
4036 format %{ "" %}
4037 interface(COND_INTER) %{
4038 equal(0x4, "e");
4039 not_equal(0x5, "ne");
4040 less(0x2, "b");
4041 greater_equal(0x3, "nb");
4042 less_equal(0x6, "be");
4043 greater(0x7, "nbe");
4044 overflow(0x0, "o");
4045 no_overflow(0x1, "no");
4046 %}
4047 %}
4048
4049
4050 // Floating comparisons that can be fixed up with extra conditional jumps
4051 operand cmpOpUCF2() %{
4052 match(Bool);
4053 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4054 n->as_Bool()->_test._test == BoolTest::eq);
4055 format %{ "" %}
4056 interface(COND_INTER) %{
4057 equal(0x4, "e");
4058 not_equal(0x5, "ne");
4059 less(0x2, "b");
4060 greater_equal(0x3, "nb");
4061 less_equal(0x6, "be");
4062 greater(0x7, "nbe");
4063 overflow(0x0, "o");
4064 no_overflow(0x1, "no");
4065 %}
4066 %}
4067
4068
4069 //----------OPERAND CLASSES----------------------------------------------------
4070 // Operand Classes are groups of operands that are used as to simplify
4071 // instruction definitions by not requiring the AD writer to specify separate
4072 // instructions for every form of operand when the instruction accepts
4073 // multiple operand types with the same basic encoding and format. The classic
4074 // case of this is memory operands.
4075
4076 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4077 indIndexScale, indIndexScaleOffset, indPosIndexScaleOffset,
4078 indCompressedOopOffset,
4079 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4080 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4081 indIndexScaleOffsetNarrow, indPosIndexScaleOffsetNarrow);
4082
4083 //----------PIPELINE-----------------------------------------------------------
4084 // Rules which define the behavior of the target architectures pipeline.
4085 pipeline %{
4086
4087 //----------ATTRIBUTES---------------------------------------------------------
4088 attributes %{
4089 variable_size_instructions; // Fixed size instructions
4090 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4091 instruction_unit_size = 1; // An instruction is 1 bytes long
4092 instruction_fetch_unit_size = 16; // The processor fetches one line
4093 instruction_fetch_units = 1; // of 16 bytes
4094
4095 // List of nop instructions
4096 nops( MachNop );
4097 %}
4098
4099 //----------RESOURCES----------------------------------------------------------
4100 // Resources are the functional units available to the machine
4101
4102 // Generic P2/P3 pipeline
4103 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4104 // 3 instructions decoded per cycle.
4105 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4106 // 3 ALU op, only ALU0 handles mul instructions.
4107 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4108 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4109 BR, FPU,
4110 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4111
4112 //----------PIPELINE DESCRIPTION-----------------------------------------------
4113 // Pipeline Description specifies the stages in the machine's pipeline
4114
4115 // Generic P2/P3 pipeline
4116 pipe_desc(S0, S1, S2, S3, S4, S5);
4117
4118 //----------PIPELINE CLASSES---------------------------------------------------
4119 // Pipeline Classes describe the stages in which input and output are
4120 // referenced by the hardware pipeline.
4121
4122 // Naming convention: ialu or fpu
4123 // Then: _reg
4124 // Then: _reg if there is a 2nd register
4125 // Then: _long if it's a pair of instructions implementing a long
4126 // Then: _fat if it requires the big decoder
4127 // Or: _mem if it requires the big decoder and a memory unit.
4128
4129 // Integer ALU reg operation
4130 pipe_class ialu_reg(rRegI dst)
4131 %{
4132 single_instruction;
4133 dst : S4(write);
4134 dst : S3(read);
4135 DECODE : S0; // any decoder
4136 ALU : S3; // any alu
4137 %}
4138
4139 // Long ALU reg operation
4140 pipe_class ialu_reg_long(rRegL dst)
4141 %{
4142 instruction_count(2);
4143 dst : S4(write);
4144 dst : S3(read);
4145 DECODE : S0(2); // any 2 decoders
4146 ALU : S3(2); // both alus
4147 %}
4148
4149 // Integer ALU reg operation using big decoder
4150 pipe_class ialu_reg_fat(rRegI dst)
4151 %{
4152 single_instruction;
4153 dst : S4(write);
4154 dst : S3(read);
4155 D0 : S0; // big decoder only
4156 ALU : S3; // any alu
4157 %}
4158
4159 // Long ALU reg operation using big decoder
4160 pipe_class ialu_reg_long_fat(rRegL dst)
4161 %{
4162 instruction_count(2);
4163 dst : S4(write);
4164 dst : S3(read);
4165 D0 : S0(2); // big decoder only; twice
4166 ALU : S3(2); // any 2 alus
4167 %}
4168
4169 // Integer ALU reg-reg operation
4170 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4171 %{
4172 single_instruction;
4173 dst : S4(write);
4174 src : S3(read);
4175 DECODE : S0; // any decoder
4176 ALU : S3; // any alu
4177 %}
4178
4179 // Long ALU reg-reg operation
4180 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4181 %{
4182 instruction_count(2);
4183 dst : S4(write);
4184 src : S3(read);
4185 DECODE : S0(2); // any 2 decoders
4186 ALU : S3(2); // both alus
4187 %}
4188
4189 // Integer ALU reg-reg operation
4190 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4191 %{
4192 single_instruction;
4193 dst : S4(write);
4194 src : S3(read);
4195 D0 : S0; // big decoder only
4196 ALU : S3; // any alu
4197 %}
4198
4199 // Long ALU reg-reg operation
4200 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4201 %{
4202 instruction_count(2);
4203 dst : S4(write);
4204 src : S3(read);
4205 D0 : S0(2); // big decoder only; twice
4206 ALU : S3(2); // both alus
4207 %}
4208
4209 // Integer ALU reg-mem operation
4210 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4211 %{
4212 single_instruction;
4213 dst : S5(write);
4214 mem : S3(read);
4215 D0 : S0; // big decoder only
4216 ALU : S4; // any alu
4217 MEM : S3; // any mem
4218 %}
4219
4220 // Integer mem operation (prefetch)
4221 pipe_class ialu_mem(memory mem)
4222 %{
4223 single_instruction;
4224 mem : S3(read);
4225 D0 : S0; // big decoder only
4226 MEM : S3; // any mem
4227 %}
4228
4229 // Integer Store to Memory
4230 pipe_class ialu_mem_reg(memory mem, rRegI src)
4231 %{
4232 single_instruction;
4233 mem : S3(read);
4234 src : S5(read);
4235 D0 : S0; // big decoder only
4236 ALU : S4; // any alu
4237 MEM : S3;
4238 %}
4239
4240 // // Long Store to Memory
4241 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4242 // %{
4243 // instruction_count(2);
4244 // mem : S3(read);
4245 // src : S5(read);
4246 // D0 : S0(2); // big decoder only; twice
4247 // ALU : S4(2); // any 2 alus
4248 // MEM : S3(2); // Both mems
4249 // %}
4250
4251 // Integer Store to Memory
4252 pipe_class ialu_mem_imm(memory mem)
4253 %{
4254 single_instruction;
4255 mem : S3(read);
4256 D0 : S0; // big decoder only
4257 ALU : S4; // any alu
4258 MEM : S3;
4259 %}
4260
4261 // Integer ALU0 reg-reg operation
4262 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4263 %{
4264 single_instruction;
4265 dst : S4(write);
4266 src : S3(read);
4267 D0 : S0; // Big decoder only
4268 ALU0 : S3; // only alu0
4269 %}
4270
4271 // Integer ALU0 reg-mem operation
4272 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4273 %{
4274 single_instruction;
4275 dst : S5(write);
4276 mem : S3(read);
4277 D0 : S0; // big decoder only
4278 ALU0 : S4; // ALU0 only
4279 MEM : S3; // any mem
4280 %}
4281
4282 // Integer ALU reg-reg operation
4283 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4284 %{
4285 single_instruction;
4286 cr : S4(write);
4287 src1 : S3(read);
4288 src2 : S3(read);
4289 DECODE : S0; // any decoder
4290 ALU : S3; // any alu
4291 %}
4292
4293 // Integer ALU reg-imm operation
4294 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4295 %{
4296 single_instruction;
4297 cr : S4(write);
4298 src1 : S3(read);
4299 DECODE : S0; // any decoder
4300 ALU : S3; // any alu
4301 %}
4302
4303 // Integer ALU reg-mem operation
4304 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4305 %{
4306 single_instruction;
4307 cr : S4(write);
4308 src1 : S3(read);
4309 src2 : S3(read);
4310 D0 : S0; // big decoder only
4311 ALU : S4; // any alu
4312 MEM : S3;
4313 %}
4314
4315 // Conditional move reg-reg
4316 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4317 %{
4318 instruction_count(4);
4319 y : S4(read);
4320 q : S3(read);
4321 p : S3(read);
4322 DECODE : S0(4); // any decoder
4323 %}
4324
4325 // Conditional move reg-reg
4326 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4327 %{
4328 single_instruction;
4329 dst : S4(write);
4330 src : S3(read);
4331 cr : S3(read);
4332 DECODE : S0; // any decoder
4333 %}
4334
4335 // Conditional move reg-mem
4336 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4337 %{
4338 single_instruction;
4339 dst : S4(write);
4340 src : S3(read);
4341 cr : S3(read);
4342 DECODE : S0; // any decoder
4343 MEM : S3;
4344 %}
4345
4346 // Conditional move reg-reg long
4347 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4348 %{
4349 single_instruction;
4350 dst : S4(write);
4351 src : S3(read);
4352 cr : S3(read);
4353 DECODE : S0(2); // any 2 decoders
4354 %}
4355
4356 // XXX
4357 // // Conditional move double reg-reg
4358 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4359 // %{
4360 // single_instruction;
4361 // dst : S4(write);
4362 // src : S3(read);
4363 // cr : S3(read);
4364 // DECODE : S0; // any decoder
4365 // %}
4366
4367 // Float reg-reg operation
4368 pipe_class fpu_reg(regD dst)
4369 %{
4370 instruction_count(2);
4371 dst : S3(read);
4372 DECODE : S0(2); // any 2 decoders
4373 FPU : S3;
4374 %}
4375
4376 // Float reg-reg operation
4377 pipe_class fpu_reg_reg(regD dst, regD src)
4378 %{
4379 instruction_count(2);
4380 dst : S4(write);
4381 src : S3(read);
4382 DECODE : S0(2); // any 2 decoders
4383 FPU : S3;
4384 %}
4385
4386 // Float reg-reg operation
4387 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4388 %{
4389 instruction_count(3);
4390 dst : S4(write);
4391 src1 : S3(read);
4392 src2 : S3(read);
4393 DECODE : S0(3); // any 3 decoders
4394 FPU : S3(2);
4395 %}
4396
4397 // Float reg-reg operation
4398 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4399 %{
4400 instruction_count(4);
4401 dst : S4(write);
4402 src1 : S3(read);
4403 src2 : S3(read);
4404 src3 : S3(read);
4405 DECODE : S0(4); // any 3 decoders
4406 FPU : S3(2);
4407 %}
4408
4409 // Float reg-reg operation
4410 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4411 %{
4412 instruction_count(4);
4413 dst : S4(write);
4414 src1 : S3(read);
4415 src2 : S3(read);
4416 src3 : S3(read);
4417 DECODE : S1(3); // any 3 decoders
4418 D0 : S0; // Big decoder only
4419 FPU : S3(2);
4420 MEM : S3;
4421 %}
4422
4423 // Float reg-mem operation
4424 pipe_class fpu_reg_mem(regD dst, memory mem)
4425 %{
4426 instruction_count(2);
4427 dst : S5(write);
4428 mem : S3(read);
4429 D0 : S0; // big decoder only
4430 DECODE : S1; // any decoder for FPU POP
4431 FPU : S4;
4432 MEM : S3; // any mem
4433 %}
4434
4435 // Float reg-mem operation
4436 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4437 %{
4438 instruction_count(3);
4439 dst : S5(write);
4440 src1 : S3(read);
4441 mem : S3(read);
4442 D0 : S0; // big decoder only
4443 DECODE : S1(2); // any decoder for FPU POP
4444 FPU : S4;
4445 MEM : S3; // any mem
4446 %}
4447
4448 // Float mem-reg operation
4449 pipe_class fpu_mem_reg(memory mem, regD src)
4450 %{
4451 instruction_count(2);
4452 src : S5(read);
4453 mem : S3(read);
4454 DECODE : S0; // any decoder for FPU PUSH
4455 D0 : S1; // big decoder only
4456 FPU : S4;
4457 MEM : S3; // any mem
4458 %}
4459
4460 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4461 %{
4462 instruction_count(3);
4463 src1 : S3(read);
4464 src2 : S3(read);
4465 mem : S3(read);
4466 DECODE : S0(2); // any decoder for FPU PUSH
4467 D0 : S1; // big decoder only
4468 FPU : S4;
4469 MEM : S3; // any mem
4470 %}
4471
4472 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4473 %{
4474 instruction_count(3);
4475 src1 : S3(read);
4476 src2 : S3(read);
4477 mem : S4(read);
4478 DECODE : S0; // any decoder for FPU PUSH
4479 D0 : S0(2); // big decoder only
4480 FPU : S4;
4481 MEM : S3(2); // any mem
4482 %}
4483
4484 pipe_class fpu_mem_mem(memory dst, memory src1)
4485 %{
4486 instruction_count(2);
4487 src1 : S3(read);
4488 dst : S4(read);
4489 D0 : S0(2); // big decoder only
4490 MEM : S3(2); // any mem
4491 %}
4492
4493 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4494 %{
4495 instruction_count(3);
4496 src1 : S3(read);
4497 src2 : S3(read);
4498 dst : S4(read);
4499 D0 : S0(3); // big decoder only
4500 FPU : S4;
4501 MEM : S3(3); // any mem
4502 %}
4503
4504 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4505 %{
4506 instruction_count(3);
4507 src1 : S4(read);
4508 mem : S4(read);
4509 DECODE : S0; // any decoder for FPU PUSH
4510 D0 : S0(2); // big decoder only
4511 FPU : S4;
4512 MEM : S3(2); // any mem
4513 %}
4514
4515 // Float load constant
4516 pipe_class fpu_reg_con(regD dst)
4517 %{
4518 instruction_count(2);
4519 dst : S5(write);
4520 D0 : S0; // big decoder only for the load
4521 DECODE : S1; // any decoder for FPU POP
4522 FPU : S4;
4523 MEM : S3; // any mem
4524 %}
4525
4526 // Float load constant
4527 pipe_class fpu_reg_reg_con(regD dst, regD src)
4528 %{
4529 instruction_count(3);
4530 dst : S5(write);
4531 src : S3(read);
4532 D0 : S0; // big decoder only for the load
4533 DECODE : S1(2); // any decoder for FPU POP
4534 FPU : S4;
4535 MEM : S3; // any mem
4536 %}
4537
4538 // UnConditional branch
4539 pipe_class pipe_jmp(label labl)
4540 %{
4541 single_instruction;
4542 BR : S3;
4543 %}
4544
4545 // Conditional branch
4546 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4547 %{
4548 single_instruction;
4549 cr : S1(read);
4550 BR : S3;
4551 %}
4552
4553 // Allocation idiom
4554 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4555 %{
4556 instruction_count(1); force_serialization;
4557 fixed_latency(6);
4558 heap_ptr : S3(read);
4559 DECODE : S0(3);
4560 D0 : S2;
4561 MEM : S3;
4562 ALU : S3(2);
4563 dst : S5(write);
4564 BR : S5;
4565 %}
4566
4567 // Generic big/slow expanded idiom
4568 pipe_class pipe_slow()
4569 %{
4570 instruction_count(10); multiple_bundles; force_serialization;
4571 fixed_latency(100);
4572 D0 : S0(2);
4573 MEM : S3(2);
4574 %}
4575
4576 // The real do-nothing guy
4577 pipe_class empty()
4578 %{
4579 instruction_count(0);
4580 %}
4581
4582 // Define the class for the Nop node
4583 define
4584 %{
4585 MachNop = empty;
4586 %}
4587
4588 %}
4589
4590 //----------INSTRUCTIONS-------------------------------------------------------
4591 //
4592 // match -- States which machine-independent subtree may be replaced
4593 // by this instruction.
4594 // ins_cost -- The estimated cost of this instruction is used by instruction
4595 // selection to identify a minimum cost tree of machine
4596 // instructions that matches a tree of machine-independent
4597 // instructions.
4598 // format -- A string providing the disassembly for this instruction.
4599 // The value of an instruction's operand may be inserted
4600 // by referring to it with a '$' prefix.
4601 // opcode -- Three instruction opcodes may be provided. These are referred
4602 // to within an encode class as $primary, $secondary, and $tertiary
4603 // rrspectively. The primary opcode is commonly used to
4604 // indicate the type of machine instruction, while secondary
4605 // and tertiary are often used for prefix options or addressing
4606 // modes.
4607 // ins_encode -- A list of encode classes with parameters. The encode class
4608 // name must have been defined in an 'enc_class' specification
4609 // in the encode section of the architecture description.
4610
4611
4612 //----------Load/Store/Move Instructions---------------------------------------
4613 //----------Load Instructions--------------------------------------------------
4614
4615 // Load Byte (8 bit signed)
4616 instruct loadB(rRegI dst, memory mem)
4617 %{
4618 match(Set dst (LoadB mem));
4619
4620 ins_cost(125);
4621 format %{ "movsbl $dst, $mem\t# byte" %}
4622
4623 ins_encode %{
4624 __ movsbl($dst$$Register, $mem$$Address);
4625 %}
4626
4627 ins_pipe(ialu_reg_mem);
4628 %}
4629
4630 // Load Byte (8 bit signed) into Long Register
4631 instruct loadB2L(rRegL dst, memory mem)
4632 %{
4633 match(Set dst (ConvI2L (LoadB mem)));
4634
4635 ins_cost(125);
4636 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4637
4638 ins_encode %{
4639 __ movsbq($dst$$Register, $mem$$Address);
4640 %}
4641
4642 ins_pipe(ialu_reg_mem);
4643 %}
4644
4645 // Load Unsigned Byte (8 bit UNsigned)
4646 instruct loadUB(rRegI dst, memory mem)
4647 %{
4648 match(Set dst (LoadUB mem));
4649
4650 ins_cost(125);
4651 format %{ "movzbl $dst, $mem\t# ubyte" %}
4652
4653 ins_encode %{
4654 __ movzbl($dst$$Register, $mem$$Address);
4655 %}
4656
4657 ins_pipe(ialu_reg_mem);
4658 %}
4659
4660 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4661 instruct loadUB2L(rRegL dst, memory mem)
4662 %{
4663 match(Set dst (ConvI2L (LoadUB mem)));
4664
4665 ins_cost(125);
4666 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4667
4668 ins_encode %{
4669 __ movzbq($dst$$Register, $mem$$Address);
4670 %}
4671
4672 ins_pipe(ialu_reg_mem);
4673 %}
4674
4675 // Load Unsigned Byte (8 bit UNsigned) with a 8-bit mask into Long Register
4676 instruct loadUB2L_immI8(rRegL dst, memory mem, immI8 mask, rFlagsReg cr) %{
4677 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4678 effect(KILL cr);
4679
4680 format %{ "movzbq $dst, $mem\t# ubyte & 8-bit mask -> long\n\t"
4681 "andl $dst, $mask" %}
4682 ins_encode %{
4683 Register Rdst = $dst$$Register;
4684 __ movzbq(Rdst, $mem$$Address);
4685 __ andl(Rdst, $mask$$constant);
4686 %}
4687 ins_pipe(ialu_reg_mem);
4688 %}
4689
4690 // Load Short (16 bit signed)
4691 instruct loadS(rRegI dst, memory mem)
4692 %{
4693 match(Set dst (LoadS mem));
4694
4695 ins_cost(125);
4696 format %{ "movswl $dst, $mem\t# short" %}
4697
4698 ins_encode %{
4699 __ movswl($dst$$Register, $mem$$Address);
4700 %}
4701
4702 ins_pipe(ialu_reg_mem);
4703 %}
4704
4705 // Load Short (16 bit signed) to Byte (8 bit signed)
4706 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4707 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4708
4709 ins_cost(125);
4710 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4711 ins_encode %{
4712 __ movsbl($dst$$Register, $mem$$Address);
4713 %}
4714 ins_pipe(ialu_reg_mem);
4715 %}
4716
4717 // Load Short (16 bit signed) into Long Register
4718 instruct loadS2L(rRegL dst, memory mem)
4719 %{
4720 match(Set dst (ConvI2L (LoadS mem)));
4721
4722 ins_cost(125);
4723 format %{ "movswq $dst, $mem\t# short -> long" %}
4724
4725 ins_encode %{
4726 __ movswq($dst$$Register, $mem$$Address);
4727 %}
4728
4729 ins_pipe(ialu_reg_mem);
4730 %}
4731
4732 // Load Unsigned Short/Char (16 bit UNsigned)
4733 instruct loadUS(rRegI dst, memory mem)
4734 %{
4735 match(Set dst (LoadUS mem));
4736
4737 ins_cost(125);
4738 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4739
4740 ins_encode %{
4741 __ movzwl($dst$$Register, $mem$$Address);
4742 %}
4743
4744 ins_pipe(ialu_reg_mem);
4745 %}
4746
4747 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4748 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4749 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4750
4751 ins_cost(125);
4752 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4753 ins_encode %{
4754 __ movsbl($dst$$Register, $mem$$Address);
4755 %}
4756 ins_pipe(ialu_reg_mem);
4757 %}
4758
4759 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4760 instruct loadUS2L(rRegL dst, memory mem)
4761 %{
4762 match(Set dst (ConvI2L (LoadUS mem)));
4763
4764 ins_cost(125);
4765 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4766
4767 ins_encode %{
4768 __ movzwq($dst$$Register, $mem$$Address);
4769 %}
4770
4771 ins_pipe(ialu_reg_mem);
4772 %}
4773
4774 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4775 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4776 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4777
4778 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4779 ins_encode %{
4780 __ movzbq($dst$$Register, $mem$$Address);
4781 %}
4782 ins_pipe(ialu_reg_mem);
4783 %}
4784
4785 // Load Unsigned Short/Char (16 bit UNsigned) with mask into Long Register
4786 instruct loadUS2L_immI16(rRegL dst, memory mem, immI16 mask, rFlagsReg cr) %{
4787 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4788 effect(KILL cr);
4789
4790 format %{ "movzwq $dst, $mem\t# ushort/char & 16-bit mask -> long\n\t"
4791 "andl $dst, $mask" %}
4792 ins_encode %{
4793 Register Rdst = $dst$$Register;
4794 __ movzwq(Rdst, $mem$$Address);
4795 __ andl(Rdst, $mask$$constant);
4796 %}
4797 ins_pipe(ialu_reg_mem);
4798 %}
4799
4800 // Load Integer
4801 instruct loadI(rRegI dst, memory mem)
4802 %{
4803 match(Set dst (LoadI mem));
4804
4805 ins_cost(125);
4806 format %{ "movl $dst, $mem\t# int" %}
4807
4808 ins_encode %{
4809 __ movl($dst$$Register, $mem$$Address);
4810 %}
4811
4812 ins_pipe(ialu_reg_mem);
4813 %}
4814
4815 // Load Integer (32 bit signed) to Byte (8 bit signed)
4816 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4817 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4818
4819 ins_cost(125);
4820 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4821 ins_encode %{
4822 __ movsbl($dst$$Register, $mem$$Address);
4823 %}
4824 ins_pipe(ialu_reg_mem);
4825 %}
4826
4827 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4828 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4829 match(Set dst (AndI (LoadI mem) mask));
4830
4831 ins_cost(125);
4832 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4833 ins_encode %{
4834 __ movzbl($dst$$Register, $mem$$Address);
4835 %}
4836 ins_pipe(ialu_reg_mem);
4837 %}
4838
4839 // Load Integer (32 bit signed) to Short (16 bit signed)
4840 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4841 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4842
4843 ins_cost(125);
4844 format %{ "movswl $dst, $mem\t# int -> short" %}
4845 ins_encode %{
4846 __ movswl($dst$$Register, $mem$$Address);
4847 %}
4848 ins_pipe(ialu_reg_mem);
4849 %}
4850
4851 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4852 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4853 match(Set dst (AndI (LoadI mem) mask));
4854
4855 ins_cost(125);
4856 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4857 ins_encode %{
4858 __ movzwl($dst$$Register, $mem$$Address);
4859 %}
4860 ins_pipe(ialu_reg_mem);
4861 %}
4862
4863 // Load Integer into Long Register
4864 instruct loadI2L(rRegL dst, memory mem)
4865 %{
4866 match(Set dst (ConvI2L (LoadI mem)));
4867
4868 ins_cost(125);
4869 format %{ "movslq $dst, $mem\t# int -> long" %}
4870
4871 ins_encode %{
4872 __ movslq($dst$$Register, $mem$$Address);
4873 %}
4874
4875 ins_pipe(ialu_reg_mem);
4876 %}
4877
4878 // Load Integer with mask 0xFF into Long Register
4879 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4880 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4881
4882 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4883 ins_encode %{
4884 __ movzbq($dst$$Register, $mem$$Address);
4885 %}
4886 ins_pipe(ialu_reg_mem);
4887 %}
4888
4889 // Load Integer with mask 0xFFFF into Long Register
4890 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4891 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4892
4893 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4894 ins_encode %{
4895 __ movzwq($dst$$Register, $mem$$Address);
4896 %}
4897 ins_pipe(ialu_reg_mem);
4898 %}
4899
4900 // Load Integer with a 31-bit mask into Long Register
4901 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4902 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4903 effect(KILL cr);
4904
4905 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4906 "andl $dst, $mask" %}
4907 ins_encode %{
4908 Register Rdst = $dst$$Register;
4909 __ movl(Rdst, $mem$$Address);
4910 __ andl(Rdst, $mask$$constant);
4911 %}
4912 ins_pipe(ialu_reg_mem);
4913 %}
4914
4915 // Load Unsigned Integer into Long Register
4916 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4917 %{
4918 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4919
4920 ins_cost(125);
4921 format %{ "movl $dst, $mem\t# uint -> long" %}
4922
4923 ins_encode %{
4924 __ movl($dst$$Register, $mem$$Address);
4925 %}
4926
4927 ins_pipe(ialu_reg_mem);
4928 %}
4929
4930 // Load Long
4931 instruct loadL(rRegL dst, memory mem)
4932 %{
4933 match(Set dst (LoadL mem));
4934
4935 ins_cost(125);
4936 format %{ "movq $dst, $mem\t# long" %}
4937
4938 ins_encode %{
4939 __ movq($dst$$Register, $mem$$Address);
4940 %}
4941
4942 ins_pipe(ialu_reg_mem); // XXX
4943 %}
4944
4945 // Load Range
4946 instruct loadRange(rRegI dst, memory mem)
4947 %{
4948 match(Set dst (LoadRange mem));
4949
4950 ins_cost(125); // XXX
4951 format %{ "movl $dst, $mem\t# range" %}
4952 opcode(0x8B);
4953 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
4954 ins_pipe(ialu_reg_mem);
4955 %}
4956
4957 // Load Pointer
4958 instruct loadP(rRegP dst, memory mem)
4959 %{
4960 match(Set dst (LoadP mem));
4961
4962 ins_cost(125); // XXX
4963 format %{ "movq $dst, $mem\t# ptr" %}
4964 opcode(0x8B);
4965 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4966 ins_pipe(ialu_reg_mem); // XXX
4967 %}
4968
4969 // Load Compressed Pointer
4970 instruct loadN(rRegN dst, memory mem)
4971 %{
4972 match(Set dst (LoadN mem));
4973
4974 ins_cost(125); // XXX
4975 format %{ "movl $dst, $mem\t# compressed ptr" %}
4976 ins_encode %{
4977 __ movl($dst$$Register, $mem$$Address);
4978 %}
4979 ins_pipe(ialu_reg_mem); // XXX
4980 %}
4981
4982
4983 // Load Klass Pointer
4984 instruct loadKlass(rRegP dst, memory mem)
4985 %{
4986 match(Set dst (LoadKlass mem));
4987
4988 ins_cost(125); // XXX
4989 format %{ "movq $dst, $mem\t# class" %}
4990 opcode(0x8B);
4991 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
4992 ins_pipe(ialu_reg_mem); // XXX
4993 %}
4994
4995 // Load narrow Klass Pointer
4996 instruct loadNKlass(rRegN dst, memory mem)
4997 %{
4998 match(Set dst (LoadNKlass mem));
4999
5000 ins_cost(125); // XXX
5001 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5002 ins_encode %{
5003 __ movl($dst$$Register, $mem$$Address);
5004 %}
5005 ins_pipe(ialu_reg_mem); // XXX
5006 %}
5007
5008 // Load Float
5009 instruct loadF(regF dst, memory mem)
5010 %{
5011 match(Set dst (LoadF mem));
5012
5013 ins_cost(145); // XXX
5014 format %{ "movss $dst, $mem\t# float" %}
5015 ins_encode %{
5016 __ movflt($dst$$XMMRegister, $mem$$Address);
5017 %}
5018 ins_pipe(pipe_slow); // XXX
5019 %}
5020
5021 // Load Double
5022 instruct loadD_partial(regD dst, memory mem)
5023 %{
5024 predicate(!UseXmmLoadAndClearUpper);
5025 match(Set dst (LoadD mem));
5026
5027 ins_cost(145); // XXX
5028 format %{ "movlpd $dst, $mem\t# double" %}
5029 ins_encode %{
5030 __ movdbl($dst$$XMMRegister, $mem$$Address);
5031 %}
5032 ins_pipe(pipe_slow); // XXX
5033 %}
5034
5035 instruct loadD(regD dst, memory mem)
5036 %{
5037 predicate(UseXmmLoadAndClearUpper);
5038 match(Set dst (LoadD mem));
5039
5040 ins_cost(145); // XXX
5041 format %{ "movsd $dst, $mem\t# double" %}
5042 ins_encode %{
5043 __ movdbl($dst$$XMMRegister, $mem$$Address);
5044 %}
5045 ins_pipe(pipe_slow); // XXX
5046 %}
5047
5048 // Load Effective Address
5049 instruct leaP8(rRegP dst, indOffset8 mem)
5050 %{
5051 match(Set dst mem);
5052
5053 ins_cost(110); // XXX
5054 format %{ "leaq $dst, $mem\t# ptr 8" %}
5055 opcode(0x8D);
5056 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5057 ins_pipe(ialu_reg_reg_fat);
5058 %}
5059
5060 instruct leaP32(rRegP dst, indOffset32 mem)
5061 %{
5062 match(Set dst mem);
5063
5064 ins_cost(110);
5065 format %{ "leaq $dst, $mem\t# ptr 32" %}
5066 opcode(0x8D);
5067 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5068 ins_pipe(ialu_reg_reg_fat);
5069 %}
5070
5071 // instruct leaPIdx(rRegP dst, indIndex mem)
5072 // %{
5073 // match(Set dst mem);
5074
5075 // ins_cost(110);
5076 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5077 // opcode(0x8D);
5078 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5079 // ins_pipe(ialu_reg_reg_fat);
5080 // %}
5081
5082 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5083 %{
5084 match(Set dst mem);
5085
5086 ins_cost(110);
5087 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5088 opcode(0x8D);
5089 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5090 ins_pipe(ialu_reg_reg_fat);
5091 %}
5092
5093 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5094 %{
5095 match(Set dst mem);
5096
5097 ins_cost(110);
5098 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5099 opcode(0x8D);
5100 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5101 ins_pipe(ialu_reg_reg_fat);
5102 %}
5103
5104 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5105 %{
5106 match(Set dst mem);
5107
5108 ins_cost(110);
5109 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5110 opcode(0x8D);
5111 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5112 ins_pipe(ialu_reg_reg_fat);
5113 %}
5114
5115 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5116 %{
5117 match(Set dst mem);
5118
5119 ins_cost(110);
5120 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5121 opcode(0x8D);
5122 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5123 ins_pipe(ialu_reg_reg_fat);
5124 %}
5125
5126 // Load Effective Address which uses Narrow (32-bits) oop
5127 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5128 %{
5129 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5130 match(Set dst mem);
5131
5132 ins_cost(110);
5133 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5134 opcode(0x8D);
5135 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5136 ins_pipe(ialu_reg_reg_fat);
5137 %}
5138
5139 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5140 %{
5141 predicate(Universe::narrow_oop_shift() == 0);
5142 match(Set dst mem);
5143
5144 ins_cost(110); // XXX
5145 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5146 opcode(0x8D);
5147 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5148 ins_pipe(ialu_reg_reg_fat);
5149 %}
5150
5151 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5152 %{
5153 predicate(Universe::narrow_oop_shift() == 0);
5154 match(Set dst mem);
5155
5156 ins_cost(110);
5157 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5158 opcode(0x8D);
5159 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5160 ins_pipe(ialu_reg_reg_fat);
5161 %}
5162
5163 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5164 %{
5165 predicate(Universe::narrow_oop_shift() == 0);
5166 match(Set dst mem);
5167
5168 ins_cost(110);
5169 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5170 opcode(0x8D);
5171 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5172 ins_pipe(ialu_reg_reg_fat);
5173 %}
5174
5175 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5176 %{
5177 predicate(Universe::narrow_oop_shift() == 0);
5178 match(Set dst mem);
5179
5180 ins_cost(110);
5181 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5182 opcode(0x8D);
5183 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5184 ins_pipe(ialu_reg_reg_fat);
5185 %}
5186
5187 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5188 %{
5189 predicate(Universe::narrow_oop_shift() == 0);
5190 match(Set dst mem);
5191
5192 ins_cost(110);
5193 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5194 opcode(0x8D);
5195 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5196 ins_pipe(ialu_reg_reg_fat);
5197 %}
5198
5199 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5200 %{
5201 predicate(Universe::narrow_oop_shift() == 0);
5202 match(Set dst mem);
5203
5204 ins_cost(110);
5205 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5206 opcode(0x8D);
5207 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5208 ins_pipe(ialu_reg_reg_fat);
5209 %}
5210
5211 instruct loadConI(rRegI dst, immI src)
5212 %{
5213 match(Set dst src);
5214
5215 format %{ "movl $dst, $src\t# int" %}
5216 ins_encode(load_immI(dst, src));
5217 ins_pipe(ialu_reg_fat); // XXX
5218 %}
5219
5220 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5221 %{
5222 match(Set dst src);
5223 effect(KILL cr);
5224
5225 ins_cost(50);
5226 format %{ "xorl $dst, $dst\t# int" %}
5227 opcode(0x33); /* + rd */
5228 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5229 ins_pipe(ialu_reg);
5230 %}
5231
5232 instruct loadConL(rRegL dst, immL src)
5233 %{
5234 match(Set dst src);
5235
5236 ins_cost(150);
5237 format %{ "movq $dst, $src\t# long" %}
5238 ins_encode(load_immL(dst, src));
5239 ins_pipe(ialu_reg);
5240 %}
5241
5242 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5243 %{
5244 match(Set dst src);
5245 effect(KILL cr);
5246
5247 ins_cost(50);
5248 format %{ "xorl $dst, $dst\t# long" %}
5249 opcode(0x33); /* + rd */
5250 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5251 ins_pipe(ialu_reg); // XXX
5252 %}
5253
5254 instruct loadConUL32(rRegL dst, immUL32 src)
5255 %{
5256 match(Set dst src);
5257
5258 ins_cost(60);
5259 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5260 ins_encode(load_immUL32(dst, src));
5261 ins_pipe(ialu_reg);
5262 %}
5263
5264 instruct loadConL32(rRegL dst, immL32 src)
5265 %{
5266 match(Set dst src);
5267
5268 ins_cost(70);
5269 format %{ "movq $dst, $src\t# long (32-bit)" %}
5270 ins_encode(load_immL32(dst, src));
5271 ins_pipe(ialu_reg);
5272 %}
5273
5274 instruct loadConP(rRegP dst, immP con) %{
5275 match(Set dst con);
5276
5277 format %{ "movq $dst, $con\t# ptr" %}
5278 ins_encode(load_immP(dst, con));
5279 ins_pipe(ialu_reg_fat); // XXX
5280 %}
5281
5282 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5283 %{
5284 match(Set dst src);
5285 effect(KILL cr);
5286
5287 ins_cost(50);
5288 format %{ "xorl $dst, $dst\t# ptr" %}
5289 opcode(0x33); /* + rd */
5290 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5291 ins_pipe(ialu_reg);
5292 %}
5293
5294 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5295 %{
5296 match(Set dst src);
5297 effect(KILL cr);
5298
5299 ins_cost(60);
5300 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5301 ins_encode(load_immP31(dst, src));
5302 ins_pipe(ialu_reg);
5303 %}
5304
5305 instruct loadConF(regF dst, immF con) %{
5306 match(Set dst con);
5307 ins_cost(125);
5308 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5309 ins_encode %{
5310 __ movflt($dst$$XMMRegister, $constantaddress($con));
5311 %}
5312 ins_pipe(pipe_slow);
5313 %}
5314
5315 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5316 match(Set dst src);
5317 effect(KILL cr);
5318 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5319 ins_encode %{
5320 __ xorq($dst$$Register, $dst$$Register);
5321 %}
5322 ins_pipe(ialu_reg);
5323 %}
5324
5325 instruct loadConN(rRegN dst, immN src) %{
5326 match(Set dst src);
5327
5328 ins_cost(125);
5329 format %{ "movl $dst, $src\t# compressed ptr" %}
5330 ins_encode %{
5331 address con = (address)$src$$constant;
5332 if (con == NULL) {
5333 ShouldNotReachHere();
5334 } else {
5335 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5336 }
5337 %}
5338 ins_pipe(ialu_reg_fat); // XXX
5339 %}
5340
5341 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5342 match(Set dst src);
5343
5344 ins_cost(125);
5345 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5346 ins_encode %{
5347 address con = (address)$src$$constant;
5348 if (con == NULL) {
5349 ShouldNotReachHere();
5350 } else {
5351 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5352 }
5353 %}
5354 ins_pipe(ialu_reg_fat); // XXX
5355 %}
5356
5357 instruct loadConF0(regF dst, immF0 src)
5358 %{
5359 match(Set dst src);
5360 ins_cost(100);
5361
5362 format %{ "xorps $dst, $dst\t# float 0.0" %}
5363 ins_encode %{
5364 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5365 %}
5366 ins_pipe(pipe_slow);
5367 %}
5368
5369 // Use the same format since predicate() can not be used here.
5370 instruct loadConD(regD dst, immD con) %{
5371 match(Set dst con);
5372 ins_cost(125);
5373 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5374 ins_encode %{
5375 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5376 %}
5377 ins_pipe(pipe_slow);
5378 %}
5379
5380 instruct loadConD0(regD dst, immD0 src)
5381 %{
5382 match(Set dst src);
5383 ins_cost(100);
5384
5385 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5386 ins_encode %{
5387 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5388 %}
5389 ins_pipe(pipe_slow);
5390 %}
5391
5392 instruct loadSSI(rRegI dst, stackSlotI src)
5393 %{
5394 match(Set dst src);
5395
5396 ins_cost(125);
5397 format %{ "movl $dst, $src\t# int stk" %}
5398 opcode(0x8B);
5399 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5400 ins_pipe(ialu_reg_mem);
5401 %}
5402
5403 instruct loadSSL(rRegL dst, stackSlotL src)
5404 %{
5405 match(Set dst src);
5406
5407 ins_cost(125);
5408 format %{ "movq $dst, $src\t# long stk" %}
5409 opcode(0x8B);
5410 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5411 ins_pipe(ialu_reg_mem);
5412 %}
5413
5414 instruct loadSSP(rRegP dst, stackSlotP src)
5415 %{
5416 match(Set dst src);
5417
5418 ins_cost(125);
5419 format %{ "movq $dst, $src\t# ptr stk" %}
5420 opcode(0x8B);
5421 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5422 ins_pipe(ialu_reg_mem);
5423 %}
5424
5425 instruct loadSSF(regF dst, stackSlotF src)
5426 %{
5427 match(Set dst src);
5428
5429 ins_cost(125);
5430 format %{ "movss $dst, $src\t# float stk" %}
5431 ins_encode %{
5432 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5433 %}
5434 ins_pipe(pipe_slow); // XXX
5435 %}
5436
5437 // Use the same format since predicate() can not be used here.
5438 instruct loadSSD(regD dst, stackSlotD src)
5439 %{
5440 match(Set dst src);
5441
5442 ins_cost(125);
5443 format %{ "movsd $dst, $src\t# double stk" %}
5444 ins_encode %{
5445 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5446 %}
5447 ins_pipe(pipe_slow); // XXX
5448 %}
5449
5450 // Prefetch instructions.
5451 // Must be safe to execute with invalid address (cannot fault).
5452
5453 instruct prefetchr( memory mem ) %{
5454 predicate(ReadPrefetchInstr==3);
5455 match(PrefetchRead mem);
5456 ins_cost(125);
5457
5458 format %{ "PREFETCHR $mem\t# Prefetch into level 1 cache" %}
5459 ins_encode %{
5460 __ prefetchr($mem$$Address);
5461 %}
5462 ins_pipe(ialu_mem);
5463 %}
5464
5465 instruct prefetchrNTA( memory mem ) %{
5466 predicate(ReadPrefetchInstr==0);
5467 match(PrefetchRead mem);
5468 ins_cost(125);
5469
5470 format %{ "PREFETCHNTA $mem\t# Prefetch into non-temporal cache for read" %}
5471 ins_encode %{
5472 __ prefetchnta($mem$$Address);
5473 %}
5474 ins_pipe(ialu_mem);
5475 %}
5476
5477 instruct prefetchrT0( memory mem ) %{
5478 predicate(ReadPrefetchInstr==1);
5479 match(PrefetchRead mem);
5480 ins_cost(125);
5481
5482 format %{ "PREFETCHT0 $mem\t# prefetch into L1 and L2 caches for read" %}
5483 ins_encode %{
5484 __ prefetcht0($mem$$Address);
5485 %}
5486 ins_pipe(ialu_mem);
5487 %}
5488
5489 instruct prefetchrT2( memory mem ) %{
5490 predicate(ReadPrefetchInstr==2);
5491 match(PrefetchRead mem);
5492 ins_cost(125);
5493
5494 format %{ "PREFETCHT2 $mem\t# prefetch into L2 caches for read" %}
5495 ins_encode %{
5496 __ prefetcht2($mem$$Address);
5497 %}
5498 ins_pipe(ialu_mem);
5499 %}
5500
5501 instruct prefetchwNTA( memory mem ) %{
5502 match(PrefetchWrite mem);
5503 ins_cost(125);
5504
5505 format %{ "PREFETCHNTA $mem\t# Prefetch to non-temporal cache for write" %}
5506 ins_encode %{
5507 __ prefetchnta($mem$$Address);
5508 %}
5509 ins_pipe(ialu_mem);
5510 %}
5511
5512 // Prefetch instructions for allocation.
5513
5514 instruct prefetchAlloc( memory mem ) %{
5515 predicate(AllocatePrefetchInstr==3);
5516 match(PrefetchAllocation mem);
5517 ins_cost(125);
5518
5519 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5520 ins_encode %{
5521 __ prefetchw($mem$$Address);
5522 %}
5523 ins_pipe(ialu_mem);
5524 %}
5525
5526 instruct prefetchAllocNTA( memory mem ) %{
5527 predicate(AllocatePrefetchInstr==0);
5528 match(PrefetchAllocation mem);
5529 ins_cost(125);
5530
5531 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5532 ins_encode %{
5533 __ prefetchnta($mem$$Address);
5534 %}
5535 ins_pipe(ialu_mem);
5536 %}
5537
5538 instruct prefetchAllocT0( memory mem ) %{
5539 predicate(AllocatePrefetchInstr==1);
5540 match(PrefetchAllocation mem);
5541 ins_cost(125);
5542
5543 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5544 ins_encode %{
5545 __ prefetcht0($mem$$Address);
5546 %}
5547 ins_pipe(ialu_mem);
5548 %}
5549
5550 instruct prefetchAllocT2( memory mem ) %{
5551 predicate(AllocatePrefetchInstr==2);
5552 match(PrefetchAllocation mem);
5553 ins_cost(125);
5554
5555 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5556 ins_encode %{
5557 __ prefetcht2($mem$$Address);
5558 %}
5559 ins_pipe(ialu_mem);
5560 %}
5561
5562 //----------Store Instructions-------------------------------------------------
5563
5564 // Store Byte
5565 instruct storeB(memory mem, rRegI src)
5566 %{
5567 match(Set mem (StoreB mem src));
5568
5569 ins_cost(125); // XXX
5570 format %{ "movb $mem, $src\t# byte" %}
5571 opcode(0x88);
5572 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5573 ins_pipe(ialu_mem_reg);
5574 %}
5575
5576 // Store Char/Short
5577 instruct storeC(memory mem, rRegI src)
5578 %{
5579 match(Set mem (StoreC mem src));
5580
5581 ins_cost(125); // XXX
5582 format %{ "movw $mem, $src\t# char/short" %}
5583 opcode(0x89);
5584 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5585 ins_pipe(ialu_mem_reg);
5586 %}
5587
5588 // Store Integer
5589 instruct storeI(memory mem, rRegI src)
5590 %{
5591 match(Set mem (StoreI mem src));
5592
5593 ins_cost(125); // XXX
5594 format %{ "movl $mem, $src\t# int" %}
5595 opcode(0x89);
5596 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5597 ins_pipe(ialu_mem_reg);
5598 %}
5599
5600 // Store Long
5601 instruct storeL(memory mem, rRegL src)
5602 %{
5603 match(Set mem (StoreL mem src));
5604
5605 ins_cost(125); // XXX
5606 format %{ "movq $mem, $src\t# long" %}
5607 opcode(0x89);
5608 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5609 ins_pipe(ialu_mem_reg); // XXX
5610 %}
5611
5612 // Store Pointer
5613 instruct storeP(memory mem, any_RegP src)
5614 %{
5615 match(Set mem (StoreP mem src));
5616
5617 ins_cost(125); // XXX
5618 format %{ "movq $mem, $src\t# ptr" %}
5619 opcode(0x89);
5620 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5621 ins_pipe(ialu_mem_reg);
5622 %}
5623
5624 instruct storeImmP0(memory mem, immP0 zero)
5625 %{
5626 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5627 match(Set mem (StoreP mem zero));
5628
5629 ins_cost(125); // XXX
5630 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5631 ins_encode %{
5632 __ movq($mem$$Address, r12);
5633 %}
5634 ins_pipe(ialu_mem_reg);
5635 %}
5636
5637 // Store NULL Pointer, mark word, or other simple pointer constant.
5638 instruct storeImmP(memory mem, immP31 src)
5639 %{
5640 match(Set mem (StoreP mem src));
5641
5642 ins_cost(150); // XXX
5643 format %{ "movq $mem, $src\t# ptr" %}
5644 opcode(0xC7); /* C7 /0 */
5645 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5646 ins_pipe(ialu_mem_imm);
5647 %}
5648
5649 // Store Compressed Pointer
5650 instruct storeN(memory mem, rRegN src)
5651 %{
5652 match(Set mem (StoreN mem src));
5653
5654 ins_cost(125); // XXX
5655 format %{ "movl $mem, $src\t# compressed ptr" %}
5656 ins_encode %{
5657 __ movl($mem$$Address, $src$$Register);
5658 %}
5659 ins_pipe(ialu_mem_reg);
5660 %}
5661
5662 instruct storeNKlass(memory mem, rRegN src)
5663 %{
5664 match(Set mem (StoreNKlass mem src));
5665
5666 ins_cost(125); // XXX
5667 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5668 ins_encode %{
5669 __ movl($mem$$Address, $src$$Register);
5670 %}
5671 ins_pipe(ialu_mem_reg);
5672 %}
5673
5674 instruct storeImmN0(memory mem, immN0 zero)
5675 %{
5676 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5677 match(Set mem (StoreN mem zero));
5678
5679 ins_cost(125); // XXX
5680 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5681 ins_encode %{
5682 __ movl($mem$$Address, r12);
5683 %}
5684 ins_pipe(ialu_mem_reg);
5685 %}
5686
5687 instruct storeImmN(memory mem, immN src)
5688 %{
5689 match(Set mem (StoreN mem src));
5690
5691 ins_cost(150); // XXX
5692 format %{ "movl $mem, $src\t# compressed ptr" %}
5693 ins_encode %{
5694 address con = (address)$src$$constant;
5695 if (con == NULL) {
5696 __ movl($mem$$Address, (int32_t)0);
5697 } else {
5698 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5699 }
5700 %}
5701 ins_pipe(ialu_mem_imm);
5702 %}
5703
5704 instruct storeImmNKlass(memory mem, immNKlass src)
5705 %{
5706 match(Set mem (StoreNKlass mem src));
5707
5708 ins_cost(150); // XXX
5709 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5710 ins_encode %{
5711 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5712 %}
5713 ins_pipe(ialu_mem_imm);
5714 %}
5715
5716 // Store Integer Immediate
5717 instruct storeImmI0(memory mem, immI0 zero)
5718 %{
5719 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5720 match(Set mem (StoreI mem zero));
5721
5722 ins_cost(125); // XXX
5723 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5724 ins_encode %{
5725 __ movl($mem$$Address, r12);
5726 %}
5727 ins_pipe(ialu_mem_reg);
5728 %}
5729
5730 instruct storeImmI(memory mem, immI src)
5731 %{
5732 match(Set mem (StoreI mem src));
5733
5734 ins_cost(150);
5735 format %{ "movl $mem, $src\t# int" %}
5736 opcode(0xC7); /* C7 /0 */
5737 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5738 ins_pipe(ialu_mem_imm);
5739 %}
5740
5741 // Store Long Immediate
5742 instruct storeImmL0(memory mem, immL0 zero)
5743 %{
5744 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5745 match(Set mem (StoreL mem zero));
5746
5747 ins_cost(125); // XXX
5748 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5749 ins_encode %{
5750 __ movq($mem$$Address, r12);
5751 %}
5752 ins_pipe(ialu_mem_reg);
5753 %}
5754
5755 instruct storeImmL(memory mem, immL32 src)
5756 %{
5757 match(Set mem (StoreL mem src));
5758
5759 ins_cost(150);
5760 format %{ "movq $mem, $src\t# long" %}
5761 opcode(0xC7); /* C7 /0 */
5762 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5763 ins_pipe(ialu_mem_imm);
5764 %}
5765
5766 // Store Short/Char Immediate
5767 instruct storeImmC0(memory mem, immI0 zero)
5768 %{
5769 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5770 match(Set mem (StoreC mem zero));
5771
5772 ins_cost(125); // XXX
5773 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5774 ins_encode %{
5775 __ movw($mem$$Address, r12);
5776 %}
5777 ins_pipe(ialu_mem_reg);
5778 %}
5779
5780 instruct storeImmI16(memory mem, immI16 src)
5781 %{
5782 predicate(UseStoreImmI16);
5783 match(Set mem (StoreC mem src));
5784
5785 ins_cost(150);
5786 format %{ "movw $mem, $src\t# short/char" %}
5787 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5788 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5789 ins_pipe(ialu_mem_imm);
5790 %}
5791
5792 // Store Byte Immediate
5793 instruct storeImmB0(memory mem, immI0 zero)
5794 %{
5795 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5796 match(Set mem (StoreB mem zero));
5797
5798 ins_cost(125); // XXX
5799 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5800 ins_encode %{
5801 __ movb($mem$$Address, r12);
5802 %}
5803 ins_pipe(ialu_mem_reg);
5804 %}
5805
5806 instruct storeImmB(memory mem, immI8 src)
5807 %{
5808 match(Set mem (StoreB mem src));
5809
5810 ins_cost(150); // XXX
5811 format %{ "movb $mem, $src\t# byte" %}
5812 opcode(0xC6); /* C6 /0 */
5813 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5814 ins_pipe(ialu_mem_imm);
5815 %}
5816
5817 // Store CMS card-mark Immediate
5818 instruct storeImmCM0_reg(memory mem, immI0 zero)
5819 %{
5820 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5821 match(Set mem (StoreCM mem zero));
5822
5823 ins_cost(125); // XXX
5824 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5825 ins_encode %{
5826 __ movb($mem$$Address, r12);
5827 %}
5828 ins_pipe(ialu_mem_reg);
5829 %}
5830
5831 instruct storeImmCM0(memory mem, immI0 src)
5832 %{
5833 match(Set mem (StoreCM mem src));
5834
5835 ins_cost(150); // XXX
5836 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5837 opcode(0xC6); /* C6 /0 */
5838 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5839 ins_pipe(ialu_mem_imm);
5840 %}
5841
5842 // Store Float
5843 instruct storeF(memory mem, regF src)
5844 %{
5845 match(Set mem (StoreF mem src));
5846
5847 ins_cost(95); // XXX
5848 format %{ "movss $mem, $src\t# float" %}
5849 ins_encode %{
5850 __ movflt($mem$$Address, $src$$XMMRegister);
5851 %}
5852 ins_pipe(pipe_slow); // XXX
5853 %}
5854
5855 // Store immediate Float value (it is faster than store from XMM register)
5856 instruct storeF0(memory mem, immF0 zero)
5857 %{
5858 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5859 match(Set mem (StoreF mem zero));
5860
5861 ins_cost(25); // XXX
5862 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5863 ins_encode %{
5864 __ movl($mem$$Address, r12);
5865 %}
5866 ins_pipe(ialu_mem_reg);
5867 %}
5868
5869 instruct storeF_imm(memory mem, immF src)
5870 %{
5871 match(Set mem (StoreF mem src));
5872
5873 ins_cost(50);
5874 format %{ "movl $mem, $src\t# float" %}
5875 opcode(0xC7); /* C7 /0 */
5876 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5877 ins_pipe(ialu_mem_imm);
5878 %}
5879
5880 // Store Double
5881 instruct storeD(memory mem, regD src)
5882 %{
5883 match(Set mem (StoreD mem src));
5884
5885 ins_cost(95); // XXX
5886 format %{ "movsd $mem, $src\t# double" %}
5887 ins_encode %{
5888 __ movdbl($mem$$Address, $src$$XMMRegister);
5889 %}
5890 ins_pipe(pipe_slow); // XXX
5891 %}
5892
5893 // Store immediate double 0.0 (it is faster than store from XMM register)
5894 instruct storeD0_imm(memory mem, immD0 src)
5895 %{
5896 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5897 match(Set mem (StoreD mem src));
5898
5899 ins_cost(50);
5900 format %{ "movq $mem, $src\t# double 0." %}
5901 opcode(0xC7); /* C7 /0 */
5902 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5903 ins_pipe(ialu_mem_imm);
5904 %}
5905
5906 instruct storeD0(memory mem, immD0 zero)
5907 %{
5908 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5909 match(Set mem (StoreD mem zero));
5910
5911 ins_cost(25); // XXX
5912 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5913 ins_encode %{
5914 __ movq($mem$$Address, r12);
5915 %}
5916 ins_pipe(ialu_mem_reg);
5917 %}
5918
5919 instruct storeSSI(stackSlotI dst, rRegI src)
5920 %{
5921 match(Set dst src);
5922
5923 ins_cost(100);
5924 format %{ "movl $dst, $src\t# int stk" %}
5925 opcode(0x89);
5926 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
5927 ins_pipe( ialu_mem_reg );
5928 %}
5929
5930 instruct storeSSL(stackSlotL dst, rRegL src)
5931 %{
5932 match(Set dst src);
5933
5934 ins_cost(100);
5935 format %{ "movq $dst, $src\t# long stk" %}
5936 opcode(0x89);
5937 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5938 ins_pipe(ialu_mem_reg);
5939 %}
5940
5941 instruct storeSSP(stackSlotP dst, rRegP src)
5942 %{
5943 match(Set dst src);
5944
5945 ins_cost(100);
5946 format %{ "movq $dst, $src\t# ptr stk" %}
5947 opcode(0x89);
5948 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
5949 ins_pipe(ialu_mem_reg);
5950 %}
5951
5952 instruct storeSSF(stackSlotF dst, regF src)
5953 %{
5954 match(Set dst src);
5955
5956 ins_cost(95); // XXX
5957 format %{ "movss $dst, $src\t# float stk" %}
5958 ins_encode %{
5959 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5960 %}
5961 ins_pipe(pipe_slow); // XXX
5962 %}
5963
5964 instruct storeSSD(stackSlotD dst, regD src)
5965 %{
5966 match(Set dst src);
5967
5968 ins_cost(95); // XXX
5969 format %{ "movsd $dst, $src\t# double stk" %}
5970 ins_encode %{
5971 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5972 %}
5973 ins_pipe(pipe_slow); // XXX
5974 %}
5975
5976 //----------BSWAP Instructions-------------------------------------------------
5977 instruct bytes_reverse_int(rRegI dst) %{
5978 match(Set dst (ReverseBytesI dst));
5979
5980 format %{ "bswapl $dst" %}
5981 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
5982 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
5983 ins_pipe( ialu_reg );
5984 %}
5985
5986 instruct bytes_reverse_long(rRegL dst) %{
5987 match(Set dst (ReverseBytesL dst));
5988
5989 format %{ "bswapq $dst" %}
5990 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
5991 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
5992 ins_pipe( ialu_reg);
5993 %}
5994
5995 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5996 match(Set dst (ReverseBytesUS dst));
5997 effect(KILL cr);
5998
5999 format %{ "bswapl $dst\n\t"
6000 "shrl $dst,16\n\t" %}
6001 ins_encode %{
6002 __ bswapl($dst$$Register);
6003 __ shrl($dst$$Register, 16);
6004 %}
6005 ins_pipe( ialu_reg );
6006 %}
6007
6008 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6009 match(Set dst (ReverseBytesS dst));
6010 effect(KILL cr);
6011
6012 format %{ "bswapl $dst\n\t"
6013 "sar $dst,16\n\t" %}
6014 ins_encode %{
6015 __ bswapl($dst$$Register);
6016 __ sarl($dst$$Register, 16);
6017 %}
6018 ins_pipe( ialu_reg );
6019 %}
6020
6021 //---------- Zeros Count Instructions ------------------------------------------
6022
6023 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6024 predicate(UseCountLeadingZerosInstruction);
6025 match(Set dst (CountLeadingZerosI src));
6026 effect(KILL cr);
6027
6028 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6029 ins_encode %{
6030 __ lzcntl($dst$$Register, $src$$Register);
6031 %}
6032 ins_pipe(ialu_reg);
6033 %}
6034
6035 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6036 predicate(!UseCountLeadingZerosInstruction);
6037 match(Set dst (CountLeadingZerosI src));
6038 effect(KILL cr);
6039
6040 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6041 "jnz skip\n\t"
6042 "movl $dst, -1\n"
6043 "skip:\n\t"
6044 "negl $dst\n\t"
6045 "addl $dst, 31" %}
6046 ins_encode %{
6047 Register Rdst = $dst$$Register;
6048 Register Rsrc = $src$$Register;
6049 Label skip;
6050 __ bsrl(Rdst, Rsrc);
6051 __ jccb(Assembler::notZero, skip);
6052 __ movl(Rdst, -1);
6053 __ bind(skip);
6054 __ negl(Rdst);
6055 __ addl(Rdst, BitsPerInt - 1);
6056 %}
6057 ins_pipe(ialu_reg);
6058 %}
6059
6060 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6061 predicate(UseCountLeadingZerosInstruction);
6062 match(Set dst (CountLeadingZerosL src));
6063 effect(KILL cr);
6064
6065 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6066 ins_encode %{
6067 __ lzcntq($dst$$Register, $src$$Register);
6068 %}
6069 ins_pipe(ialu_reg);
6070 %}
6071
6072 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6073 predicate(!UseCountLeadingZerosInstruction);
6074 match(Set dst (CountLeadingZerosL src));
6075 effect(KILL cr);
6076
6077 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6078 "jnz skip\n\t"
6079 "movl $dst, -1\n"
6080 "skip:\n\t"
6081 "negl $dst\n\t"
6082 "addl $dst, 63" %}
6083 ins_encode %{
6084 Register Rdst = $dst$$Register;
6085 Register Rsrc = $src$$Register;
6086 Label skip;
6087 __ bsrq(Rdst, Rsrc);
6088 __ jccb(Assembler::notZero, skip);
6089 __ movl(Rdst, -1);
6090 __ bind(skip);
6091 __ negl(Rdst);
6092 __ addl(Rdst, BitsPerLong - 1);
6093 %}
6094 ins_pipe(ialu_reg);
6095 %}
6096
6097 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6098 predicate(UseCountTrailingZerosInstruction);
6099 match(Set dst (CountTrailingZerosI src));
6100 effect(KILL cr);
6101
6102 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6103 ins_encode %{
6104 __ tzcntl($dst$$Register, $src$$Register);
6105 %}
6106 ins_pipe(ialu_reg);
6107 %}
6108
6109 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6110 predicate(!UseCountTrailingZerosInstruction);
6111 match(Set dst (CountTrailingZerosI src));
6112 effect(KILL cr);
6113
6114 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6115 "jnz done\n\t"
6116 "movl $dst, 32\n"
6117 "done:" %}
6118 ins_encode %{
6119 Register Rdst = $dst$$Register;
6120 Label done;
6121 __ bsfl(Rdst, $src$$Register);
6122 __ jccb(Assembler::notZero, done);
6123 __ movl(Rdst, BitsPerInt);
6124 __ bind(done);
6125 %}
6126 ins_pipe(ialu_reg);
6127 %}
6128
6129 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6130 predicate(UseCountTrailingZerosInstruction);
6131 match(Set dst (CountTrailingZerosL src));
6132 effect(KILL cr);
6133
6134 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6135 ins_encode %{
6136 __ tzcntq($dst$$Register, $src$$Register);
6137 %}
6138 ins_pipe(ialu_reg);
6139 %}
6140
6141 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6142 predicate(!UseCountTrailingZerosInstruction);
6143 match(Set dst (CountTrailingZerosL src));
6144 effect(KILL cr);
6145
6146 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6147 "jnz done\n\t"
6148 "movl $dst, 64\n"
6149 "done:" %}
6150 ins_encode %{
6151 Register Rdst = $dst$$Register;
6152 Label done;
6153 __ bsfq(Rdst, $src$$Register);
6154 __ jccb(Assembler::notZero, done);
6155 __ movl(Rdst, BitsPerLong);
6156 __ bind(done);
6157 %}
6158 ins_pipe(ialu_reg);
6159 %}
6160
6161
6162 //---------- Population Count Instructions -------------------------------------
6163
6164 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6165 predicate(UsePopCountInstruction);
6166 match(Set dst (PopCountI src));
6167 effect(KILL cr);
6168
6169 format %{ "popcnt $dst, $src" %}
6170 ins_encode %{
6171 __ popcntl($dst$$Register, $src$$Register);
6172 %}
6173 ins_pipe(ialu_reg);
6174 %}
6175
6176 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6177 predicate(UsePopCountInstruction);
6178 match(Set dst (PopCountI (LoadI mem)));
6179 effect(KILL cr);
6180
6181 format %{ "popcnt $dst, $mem" %}
6182 ins_encode %{
6183 __ popcntl($dst$$Register, $mem$$Address);
6184 %}
6185 ins_pipe(ialu_reg);
6186 %}
6187
6188 // Note: Long.bitCount(long) returns an int.
6189 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6190 predicate(UsePopCountInstruction);
6191 match(Set dst (PopCountL src));
6192 effect(KILL cr);
6193
6194 format %{ "popcnt $dst, $src" %}
6195 ins_encode %{
6196 __ popcntq($dst$$Register, $src$$Register);
6197 %}
6198 ins_pipe(ialu_reg);
6199 %}
6200
6201 // Note: Long.bitCount(long) returns an int.
6202 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6203 predicate(UsePopCountInstruction);
6204 match(Set dst (PopCountL (LoadL mem)));
6205 effect(KILL cr);
6206
6207 format %{ "popcnt $dst, $mem" %}
6208 ins_encode %{
6209 __ popcntq($dst$$Register, $mem$$Address);
6210 %}
6211 ins_pipe(ialu_reg);
6212 %}
6213
6214
6215 //----------MemBar Instructions-----------------------------------------------
6216 // Memory barrier flavors
6217
6218 instruct membar_acquire()
6219 %{
6220 match(MemBarAcquire);
6221 match(LoadFence);
6222 ins_cost(0);
6223
6224 size(0);
6225 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6226 ins_encode();
6227 ins_pipe(empty);
6228 %}
6229
6230 instruct membar_acquire_lock()
6231 %{
6232 match(MemBarAcquireLock);
6233 ins_cost(0);
6234
6235 size(0);
6236 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6237 ins_encode();
6238 ins_pipe(empty);
6239 %}
6240
6241 instruct membar_release()
6242 %{
6243 match(MemBarRelease);
6244 match(StoreFence);
6245 ins_cost(0);
6246
6247 size(0);
6248 format %{ "MEMBAR-release ! (empty encoding)" %}
6249 ins_encode();
6250 ins_pipe(empty);
6251 %}
6252
6253 instruct membar_release_lock()
6254 %{
6255 match(MemBarReleaseLock);
6256 ins_cost(0);
6257
6258 size(0);
6259 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6260 ins_encode();
6261 ins_pipe(empty);
6262 %}
6263
6264 instruct membar_volatile(rFlagsReg cr) %{
6265 match(MemBarVolatile);
6266 effect(KILL cr);
6267 ins_cost(400);
6268
6269 format %{
6270 $$template
6271 if (os::is_MP()) {
6272 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6273 } else {
6274 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6275 }
6276 %}
6277 ins_encode %{
6278 __ membar(Assembler::StoreLoad);
6279 %}
6280 ins_pipe(pipe_slow);
6281 %}
6282
6283 instruct unnecessary_membar_volatile()
6284 %{
6285 match(MemBarVolatile);
6286 predicate(Matcher::post_store_load_barrier(n));
6287 ins_cost(0);
6288
6289 size(0);
6290 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6291 ins_encode();
6292 ins_pipe(empty);
6293 %}
6294
6295 instruct membar_storestore() %{
6296 match(MemBarStoreStore);
6297 ins_cost(0);
6298
6299 size(0);
6300 format %{ "MEMBAR-storestore (empty encoding)" %}
6301 ins_encode( );
6302 ins_pipe(empty);
6303 %}
6304
6305 //----------Move Instructions--------------------------------------------------
6306
6307 instruct castX2P(rRegP dst, rRegL src)
6308 %{
6309 match(Set dst (CastX2P src));
6310
6311 format %{ "movq $dst, $src\t# long->ptr" %}
6312 ins_encode %{
6313 if ($dst$$reg != $src$$reg) {
6314 __ movptr($dst$$Register, $src$$Register);
6315 }
6316 %}
6317 ins_pipe(ialu_reg_reg); // XXX
6318 %}
6319
6320 instruct castP2X(rRegL dst, rRegP src)
6321 %{
6322 match(Set dst (CastP2X src));
6323
6324 format %{ "movq $dst, $src\t# ptr -> long" %}
6325 ins_encode %{
6326 if ($dst$$reg != $src$$reg) {
6327 __ movptr($dst$$Register, $src$$Register);
6328 }
6329 %}
6330 ins_pipe(ialu_reg_reg); // XXX
6331 %}
6332
6333 // Convert oop into int for vectors alignment masking
6334 instruct convP2I(rRegI dst, rRegP src)
6335 %{
6336 match(Set dst (ConvL2I (CastP2X src)));
6337
6338 format %{ "movl $dst, $src\t# ptr -> int" %}
6339 ins_encode %{
6340 __ movl($dst$$Register, $src$$Register);
6341 %}
6342 ins_pipe(ialu_reg_reg); // XXX
6343 %}
6344
6345 // Convert compressed oop into int for vectors alignment masking
6346 // in case of 32bit oops (heap < 4Gb).
6347 instruct convN2I(rRegI dst, rRegN src)
6348 %{
6349 predicate(Universe::narrow_oop_shift() == 0);
6350 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6351
6352 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6353 ins_encode %{
6354 __ movl($dst$$Register, $src$$Register);
6355 %}
6356 ins_pipe(ialu_reg_reg); // XXX
6357 %}
6358
6359 // Convert oop pointer into compressed form
6360 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6361 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6362 match(Set dst (EncodeP src));
6363 effect(KILL cr);
6364 format %{ "encode_heap_oop $dst,$src" %}
6365 ins_encode %{
6366 Register s = $src$$Register;
6367 Register d = $dst$$Register;
6368 if (s != d) {
6369 __ movq(d, s);
6370 }
6371 __ encode_heap_oop(d);
6372 %}
6373 ins_pipe(ialu_reg_long);
6374 %}
6375
6376 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6377 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6378 match(Set dst (EncodeP src));
6379 effect(KILL cr);
6380 format %{ "encode_heap_oop_not_null $dst,$src" %}
6381 ins_encode %{
6382 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6383 %}
6384 ins_pipe(ialu_reg_long);
6385 %}
6386
6387 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6388 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6389 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6390 match(Set dst (DecodeN src));
6391 effect(KILL cr);
6392 format %{ "decode_heap_oop $dst,$src" %}
6393 ins_encode %{
6394 Register s = $src$$Register;
6395 Register d = $dst$$Register;
6396 if (s != d) {
6397 __ movq(d, s);
6398 }
6399 __ decode_heap_oop(d);
6400 %}
6401 ins_pipe(ialu_reg_long);
6402 %}
6403
6404 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6405 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6406 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6407 match(Set dst (DecodeN src));
6408 effect(KILL cr);
6409 format %{ "decode_heap_oop_not_null $dst,$src" %}
6410 ins_encode %{
6411 Register s = $src$$Register;
6412 Register d = $dst$$Register;
6413 if (s != d) {
6414 __ decode_heap_oop_not_null(d, s);
6415 } else {
6416 __ decode_heap_oop_not_null(d);
6417 }
6418 %}
6419 ins_pipe(ialu_reg_long);
6420 %}
6421
6422 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6423 match(Set dst (EncodePKlass src));
6424 effect(KILL cr);
6425 format %{ "encode_klass_not_null $dst,$src" %}
6426 ins_encode %{
6427 __ encode_klass_not_null($dst$$Register, $src$$Register);
6428 %}
6429 ins_pipe(ialu_reg_long);
6430 %}
6431
6432 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6433 match(Set dst (DecodeNKlass src));
6434 effect(KILL cr);
6435 format %{ "decode_klass_not_null $dst,$src" %}
6436 ins_encode %{
6437 Register s = $src$$Register;
6438 Register d = $dst$$Register;
6439 if (s != d) {
6440 __ decode_klass_not_null(d, s);
6441 } else {
6442 __ decode_klass_not_null(d);
6443 }
6444 %}
6445 ins_pipe(ialu_reg_long);
6446 %}
6447
6448
6449 //----------Conditional Move---------------------------------------------------
6450 // Jump
6451 // dummy instruction for generating temp registers
6452 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6453 match(Jump (LShiftL switch_val shift));
6454 ins_cost(350);
6455 predicate(false);
6456 effect(TEMP dest);
6457
6458 format %{ "leaq $dest, [$constantaddress]\n\t"
6459 "jmp [$dest + $switch_val << $shift]\n\t" %}
6460 ins_encode %{
6461 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6462 // to do that and the compiler is using that register as one it can allocate.
6463 // So we build it all by hand.
6464 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6465 // ArrayAddress dispatch(table, index);
6466 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6467 __ lea($dest$$Register, $constantaddress);
6468 __ jmp(dispatch);
6469 %}
6470 ins_pipe(pipe_jmp);
6471 %}
6472
6473 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6474 match(Jump (AddL (LShiftL switch_val shift) offset));
6475 ins_cost(350);
6476 effect(TEMP dest);
6477
6478 format %{ "leaq $dest, [$constantaddress]\n\t"
6479 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6480 ins_encode %{
6481 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6482 // to do that and the compiler is using that register as one it can allocate.
6483 // So we build it all by hand.
6484 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6485 // ArrayAddress dispatch(table, index);
6486 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6487 __ lea($dest$$Register, $constantaddress);
6488 __ jmp(dispatch);
6489 %}
6490 ins_pipe(pipe_jmp);
6491 %}
6492
6493 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6494 match(Jump switch_val);
6495 ins_cost(350);
6496 effect(TEMP dest);
6497
6498 format %{ "leaq $dest, [$constantaddress]\n\t"
6499 "jmp [$dest + $switch_val]\n\t" %}
6500 ins_encode %{
6501 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6502 // to do that and the compiler is using that register as one it can allocate.
6503 // So we build it all by hand.
6504 // Address index(noreg, switch_reg, Address::times_1);
6505 // ArrayAddress dispatch(table, index);
6506 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6507 __ lea($dest$$Register, $constantaddress);
6508 __ jmp(dispatch);
6509 %}
6510 ins_pipe(pipe_jmp);
6511 %}
6512
6513 // Conditional move
6514 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6515 %{
6516 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6517
6518 ins_cost(200); // XXX
6519 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6520 opcode(0x0F, 0x40);
6521 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6522 ins_pipe(pipe_cmov_reg);
6523 %}
6524
6525 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6526 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6527
6528 ins_cost(200); // XXX
6529 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6530 opcode(0x0F, 0x40);
6531 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6532 ins_pipe(pipe_cmov_reg);
6533 %}
6534
6535 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6536 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6537 ins_cost(200);
6538 expand %{
6539 cmovI_regU(cop, cr, dst, src);
6540 %}
6541 %}
6542
6543 // Conditional move
6544 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6545 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6546
6547 ins_cost(250); // XXX
6548 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6549 opcode(0x0F, 0x40);
6550 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6551 ins_pipe(pipe_cmov_mem);
6552 %}
6553
6554 // Conditional move
6555 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6556 %{
6557 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6558
6559 ins_cost(250); // XXX
6560 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6561 opcode(0x0F, 0x40);
6562 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6563 ins_pipe(pipe_cmov_mem);
6564 %}
6565
6566 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6567 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6568 ins_cost(250);
6569 expand %{
6570 cmovI_memU(cop, cr, dst, src);
6571 %}
6572 %}
6573
6574 // Conditional move
6575 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6576 %{
6577 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6578
6579 ins_cost(200); // XXX
6580 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6581 opcode(0x0F, 0x40);
6582 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6583 ins_pipe(pipe_cmov_reg);
6584 %}
6585
6586 // Conditional move
6587 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6588 %{
6589 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6590
6591 ins_cost(200); // XXX
6592 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6593 opcode(0x0F, 0x40);
6594 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6595 ins_pipe(pipe_cmov_reg);
6596 %}
6597
6598 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6599 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6600 ins_cost(200);
6601 expand %{
6602 cmovN_regU(cop, cr, dst, src);
6603 %}
6604 %}
6605
6606 // Conditional move
6607 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6608 %{
6609 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6610
6611 ins_cost(200); // XXX
6612 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6613 opcode(0x0F, 0x40);
6614 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6615 ins_pipe(pipe_cmov_reg); // XXX
6616 %}
6617
6618 // Conditional move
6619 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6620 %{
6621 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6622
6623 ins_cost(200); // XXX
6624 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6625 opcode(0x0F, 0x40);
6626 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6627 ins_pipe(pipe_cmov_reg); // XXX
6628 %}
6629
6630 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6631 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6632 ins_cost(200);
6633 expand %{
6634 cmovP_regU(cop, cr, dst, src);
6635 %}
6636 %}
6637
6638 // DISABLED: Requires the ADLC to emit a bottom_type call that
6639 // correctly meets the two pointer arguments; one is an incoming
6640 // register but the other is a memory operand. ALSO appears to
6641 // be buggy with implicit null checks.
6642 //
6643 //// Conditional move
6644 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6645 //%{
6646 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6647 // ins_cost(250);
6648 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6649 // opcode(0x0F,0x40);
6650 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6651 // ins_pipe( pipe_cmov_mem );
6652 //%}
6653 //
6654 //// Conditional move
6655 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6656 //%{
6657 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6658 // ins_cost(250);
6659 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6660 // opcode(0x0F,0x40);
6661 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6662 // ins_pipe( pipe_cmov_mem );
6663 //%}
6664
6665 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6666 %{
6667 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6668
6669 ins_cost(200); // XXX
6670 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6671 opcode(0x0F, 0x40);
6672 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6673 ins_pipe(pipe_cmov_reg); // XXX
6674 %}
6675
6676 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6677 %{
6678 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6679
6680 ins_cost(200); // XXX
6681 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6682 opcode(0x0F, 0x40);
6683 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6684 ins_pipe(pipe_cmov_mem); // XXX
6685 %}
6686
6687 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6688 %{
6689 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6690
6691 ins_cost(200); // XXX
6692 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6693 opcode(0x0F, 0x40);
6694 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6695 ins_pipe(pipe_cmov_reg); // XXX
6696 %}
6697
6698 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6699 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6700 ins_cost(200);
6701 expand %{
6702 cmovL_regU(cop, cr, dst, src);
6703 %}
6704 %}
6705
6706 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6707 %{
6708 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6709
6710 ins_cost(200); // XXX
6711 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6712 opcode(0x0F, 0x40);
6713 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6714 ins_pipe(pipe_cmov_mem); // XXX
6715 %}
6716
6717 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6718 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6719 ins_cost(200);
6720 expand %{
6721 cmovL_memU(cop, cr, dst, src);
6722 %}
6723 %}
6724
6725 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6726 %{
6727 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6728
6729 ins_cost(200); // XXX
6730 format %{ "jn$cop skip\t# signed cmove float\n\t"
6731 "movss $dst, $src\n"
6732 "skip:" %}
6733 ins_encode %{
6734 Label Lskip;
6735 // Invert sense of branch from sense of CMOV
6736 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6737 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6738 __ bind(Lskip);
6739 %}
6740 ins_pipe(pipe_slow);
6741 %}
6742
6743 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6744 // %{
6745 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6746
6747 // ins_cost(200); // XXX
6748 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6749 // "movss $dst, $src\n"
6750 // "skip:" %}
6751 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6752 // ins_pipe(pipe_slow);
6753 // %}
6754
6755 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6756 %{
6757 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6758
6759 ins_cost(200); // XXX
6760 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6761 "movss $dst, $src\n"
6762 "skip:" %}
6763 ins_encode %{
6764 Label Lskip;
6765 // Invert sense of branch from sense of CMOV
6766 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6767 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6768 __ bind(Lskip);
6769 %}
6770 ins_pipe(pipe_slow);
6771 %}
6772
6773 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6774 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6775 ins_cost(200);
6776 expand %{
6777 cmovF_regU(cop, cr, dst, src);
6778 %}
6779 %}
6780
6781 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6782 %{
6783 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6784
6785 ins_cost(200); // XXX
6786 format %{ "jn$cop skip\t# signed cmove double\n\t"
6787 "movsd $dst, $src\n"
6788 "skip:" %}
6789 ins_encode %{
6790 Label Lskip;
6791 // Invert sense of branch from sense of CMOV
6792 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6793 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6794 __ bind(Lskip);
6795 %}
6796 ins_pipe(pipe_slow);
6797 %}
6798
6799 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6800 %{
6801 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6802
6803 ins_cost(200); // XXX
6804 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6805 "movsd $dst, $src\n"
6806 "skip:" %}
6807 ins_encode %{
6808 Label Lskip;
6809 // Invert sense of branch from sense of CMOV
6810 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6811 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6812 __ bind(Lskip);
6813 %}
6814 ins_pipe(pipe_slow);
6815 %}
6816
6817 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6818 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6819 ins_cost(200);
6820 expand %{
6821 cmovD_regU(cop, cr, dst, src);
6822 %}
6823 %}
6824
6825 //----------Arithmetic Instructions--------------------------------------------
6826 //----------Addition Instructions----------------------------------------------
6827
6828 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6829 %{
6830 match(Set dst (AddI dst src));
6831 effect(KILL cr);
6832
6833 format %{ "addl $dst, $src\t# int" %}
6834 opcode(0x03);
6835 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6836 ins_pipe(ialu_reg_reg);
6837 %}
6838
6839 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6840 %{
6841 match(Set dst (AddI dst src));
6842 effect(KILL cr);
6843
6844 format %{ "addl $dst, $src\t# int" %}
6845 opcode(0x81, 0x00); /* /0 id */
6846 ins_encode(OpcSErm(dst, src), Con8or32(src));
6847 ins_pipe( ialu_reg );
6848 %}
6849
6850 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6851 %{
6852 match(Set dst (AddI dst (LoadI src)));
6853 effect(KILL cr);
6854
6855 ins_cost(125); // XXX
6856 format %{ "addl $dst, $src\t# int" %}
6857 opcode(0x03);
6858 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6859 ins_pipe(ialu_reg_mem);
6860 %}
6861
6862 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6863 %{
6864 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6865 effect(KILL cr);
6866
6867 ins_cost(150); // XXX
6868 format %{ "addl $dst, $src\t# int" %}
6869 opcode(0x01); /* Opcode 01 /r */
6870 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6871 ins_pipe(ialu_mem_reg);
6872 %}
6873
6874 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6875 %{
6876 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6877 effect(KILL cr);
6878
6879 ins_cost(125); // XXX
6880 format %{ "addl $dst, $src\t# int" %}
6881 opcode(0x81); /* Opcode 81 /0 id */
6882 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6883 ins_pipe(ialu_mem_imm);
6884 %}
6885
6886 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6887 %{
6888 predicate(UseIncDec);
6889 match(Set dst (AddI dst src));
6890 effect(KILL cr);
6891
6892 format %{ "incl $dst\t# int" %}
6893 opcode(0xFF, 0x00); // FF /0
6894 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6895 ins_pipe(ialu_reg);
6896 %}
6897
6898 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6899 %{
6900 predicate(UseIncDec);
6901 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6902 effect(KILL cr);
6903
6904 ins_cost(125); // XXX
6905 format %{ "incl $dst\t# int" %}
6906 opcode(0xFF); /* Opcode FF /0 */
6907 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6908 ins_pipe(ialu_mem_imm);
6909 %}
6910
6911 // XXX why does that use AddI
6912 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6913 %{
6914 predicate(UseIncDec);
6915 match(Set dst (AddI dst src));
6916 effect(KILL cr);
6917
6918 format %{ "decl $dst\t# int" %}
6919 opcode(0xFF, 0x01); // FF /1
6920 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6921 ins_pipe(ialu_reg);
6922 %}
6923
6924 // XXX why does that use AddI
6925 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6926 %{
6927 predicate(UseIncDec);
6928 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6929 effect(KILL cr);
6930
6931 ins_cost(125); // XXX
6932 format %{ "decl $dst\t# int" %}
6933 opcode(0xFF); /* Opcode FF /1 */
6934 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
6935 ins_pipe(ialu_mem_imm);
6936 %}
6937
6938 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
6939 %{
6940 match(Set dst (AddI src0 src1));
6941
6942 ins_cost(110);
6943 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
6944 opcode(0x8D); /* 0x8D /r */
6945 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
6946 ins_pipe(ialu_reg_reg);
6947 %}
6948
6949 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6950 %{
6951 match(Set dst (AddL dst src));
6952 effect(KILL cr);
6953
6954 format %{ "addq $dst, $src\t# long" %}
6955 opcode(0x03);
6956 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
6957 ins_pipe(ialu_reg_reg);
6958 %}
6959
6960 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6961 %{
6962 match(Set dst (AddL dst src));
6963 effect(KILL cr);
6964
6965 format %{ "addq $dst, $src\t# long" %}
6966 opcode(0x81, 0x00); /* /0 id */
6967 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
6968 ins_pipe( ialu_reg );
6969 %}
6970
6971 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6972 %{
6973 match(Set dst (AddL dst (LoadL src)));
6974 effect(KILL cr);
6975
6976 ins_cost(125); // XXX
6977 format %{ "addq $dst, $src\t# long" %}
6978 opcode(0x03);
6979 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
6980 ins_pipe(ialu_reg_mem);
6981 %}
6982
6983 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6984 %{
6985 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6986 effect(KILL cr);
6987
6988 ins_cost(150); // XXX
6989 format %{ "addq $dst, $src\t# long" %}
6990 opcode(0x01); /* Opcode 01 /r */
6991 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6992 ins_pipe(ialu_mem_reg);
6993 %}
6994
6995 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6996 %{
6997 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6998 effect(KILL cr);
6999
7000 ins_cost(125); // XXX
7001 format %{ "addq $dst, $src\t# long" %}
7002 opcode(0x81); /* Opcode 81 /0 id */
7003 ins_encode(REX_mem_wide(dst),
7004 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7005 ins_pipe(ialu_mem_imm);
7006 %}
7007
7008 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7009 %{
7010 predicate(UseIncDec);
7011 match(Set dst (AddL dst src));
7012 effect(KILL cr);
7013
7014 format %{ "incq $dst\t# long" %}
7015 opcode(0xFF, 0x00); // FF /0
7016 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7017 ins_pipe(ialu_reg);
7018 %}
7019
7020 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7021 %{
7022 predicate(UseIncDec);
7023 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7024 effect(KILL cr);
7025
7026 ins_cost(125); // XXX
7027 format %{ "incq $dst\t# long" %}
7028 opcode(0xFF); /* Opcode FF /0 */
7029 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7030 ins_pipe(ialu_mem_imm);
7031 %}
7032
7033 // XXX why does that use AddL
7034 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7035 %{
7036 predicate(UseIncDec);
7037 match(Set dst (AddL dst src));
7038 effect(KILL cr);
7039
7040 format %{ "decq $dst\t# long" %}
7041 opcode(0xFF, 0x01); // FF /1
7042 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7043 ins_pipe(ialu_reg);
7044 %}
7045
7046 // XXX why does that use AddL
7047 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7048 %{
7049 predicate(UseIncDec);
7050 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7051 effect(KILL cr);
7052
7053 ins_cost(125); // XXX
7054 format %{ "decq $dst\t# long" %}
7055 opcode(0xFF); /* Opcode FF /1 */
7056 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7057 ins_pipe(ialu_mem_imm);
7058 %}
7059
7060 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7061 %{
7062 match(Set dst (AddL src0 src1));
7063
7064 ins_cost(110);
7065 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7066 opcode(0x8D); /* 0x8D /r */
7067 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7068 ins_pipe(ialu_reg_reg);
7069 %}
7070
7071 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7072 %{
7073 match(Set dst (AddP dst src));
7074 effect(KILL cr);
7075
7076 format %{ "addq $dst, $src\t# ptr" %}
7077 opcode(0x03);
7078 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7079 ins_pipe(ialu_reg_reg);
7080 %}
7081
7082 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7083 %{
7084 match(Set dst (AddP dst src));
7085 effect(KILL cr);
7086
7087 format %{ "addq $dst, $src\t# ptr" %}
7088 opcode(0x81, 0x00); /* /0 id */
7089 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7090 ins_pipe( ialu_reg );
7091 %}
7092
7093 // XXX addP mem ops ????
7094
7095 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7096 %{
7097 match(Set dst (AddP src0 src1));
7098
7099 ins_cost(110);
7100 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7101 opcode(0x8D); /* 0x8D /r */
7102 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7103 ins_pipe(ialu_reg_reg);
7104 %}
7105
7106 instruct checkCastPP(rRegP dst)
7107 %{
7108 match(Set dst (CheckCastPP dst));
7109
7110 size(0);
7111 format %{ "# checkcastPP of $dst" %}
7112 ins_encode(/* empty encoding */);
7113 ins_pipe(empty);
7114 %}
7115
7116 instruct castPP(rRegP dst)
7117 %{
7118 match(Set dst (CastPP dst));
7119
7120 size(0);
7121 format %{ "# castPP of $dst" %}
7122 ins_encode(/* empty encoding */);
7123 ins_pipe(empty);
7124 %}
7125
7126 instruct castII(rRegI dst)
7127 %{
7128 match(Set dst (CastII dst));
7129
7130 size(0);
7131 format %{ "# castII of $dst" %}
7132 ins_encode(/* empty encoding */);
7133 ins_cost(0);
7134 ins_pipe(empty);
7135 %}
7136
7137 // LoadP-locked same as a regular LoadP when used with compare-swap
7138 instruct loadPLocked(rRegP dst, memory mem)
7139 %{
7140 match(Set dst (LoadPLocked mem));
7141
7142 ins_cost(125); // XXX
7143 format %{ "movq $dst, $mem\t# ptr locked" %}
7144 opcode(0x8B);
7145 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7146 ins_pipe(ialu_reg_mem); // XXX
7147 %}
7148
7149 // Conditional-store of the updated heap-top.
7150 // Used during allocation of the shared heap.
7151 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7152
7153 instruct storePConditional(memory heap_top_ptr,
7154 rax_RegP oldval, rRegP newval,
7155 rFlagsReg cr)
7156 %{
7157 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7158
7159 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7160 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7161 opcode(0x0F, 0xB1);
7162 ins_encode(lock_prefix,
7163 REX_reg_mem_wide(newval, heap_top_ptr),
7164 OpcP, OpcS,
7165 reg_mem(newval, heap_top_ptr));
7166 ins_pipe(pipe_cmpxchg);
7167 %}
7168
7169 // Conditional-store of an int value.
7170 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7171 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7172 %{
7173 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7174 effect(KILL oldval);
7175
7176 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7177 opcode(0x0F, 0xB1);
7178 ins_encode(lock_prefix,
7179 REX_reg_mem(newval, mem),
7180 OpcP, OpcS,
7181 reg_mem(newval, mem));
7182 ins_pipe(pipe_cmpxchg);
7183 %}
7184
7185 // Conditional-store of a long value.
7186 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7187 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7188 %{
7189 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7190 effect(KILL oldval);
7191
7192 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7193 opcode(0x0F, 0xB1);
7194 ins_encode(lock_prefix,
7195 REX_reg_mem_wide(newval, mem),
7196 OpcP, OpcS,
7197 reg_mem(newval, mem));
7198 ins_pipe(pipe_cmpxchg);
7199 %}
7200
7201
7202 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7203 instruct compareAndSwapP(rRegI res,
7204 memory mem_ptr,
7205 rax_RegP oldval, rRegP newval,
7206 rFlagsReg cr)
7207 %{
7208 predicate(VM_Version::supports_cx8());
7209 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7210 effect(KILL cr, KILL oldval);
7211
7212 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7213 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7214 "sete $res\n\t"
7215 "movzbl $res, $res" %}
7216 opcode(0x0F, 0xB1);
7217 ins_encode(lock_prefix,
7218 REX_reg_mem_wide(newval, mem_ptr),
7219 OpcP, OpcS,
7220 reg_mem(newval, mem_ptr),
7221 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7222 REX_reg_breg(res, res), // movzbl
7223 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7224 ins_pipe( pipe_cmpxchg );
7225 %}
7226
7227 instruct compareAndSwapL(rRegI res,
7228 memory mem_ptr,
7229 rax_RegL oldval, rRegL newval,
7230 rFlagsReg cr)
7231 %{
7232 predicate(VM_Version::supports_cx8());
7233 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7234 effect(KILL cr, KILL oldval);
7235
7236 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7237 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7238 "sete $res\n\t"
7239 "movzbl $res, $res" %}
7240 opcode(0x0F, 0xB1);
7241 ins_encode(lock_prefix,
7242 REX_reg_mem_wide(newval, mem_ptr),
7243 OpcP, OpcS,
7244 reg_mem(newval, mem_ptr),
7245 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7246 REX_reg_breg(res, res), // movzbl
7247 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7248 ins_pipe( pipe_cmpxchg );
7249 %}
7250
7251 instruct compareAndSwapI(rRegI res,
7252 memory mem_ptr,
7253 rax_RegI oldval, rRegI newval,
7254 rFlagsReg cr)
7255 %{
7256 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7257 effect(KILL cr, KILL oldval);
7258
7259 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7260 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7261 "sete $res\n\t"
7262 "movzbl $res, $res" %}
7263 opcode(0x0F, 0xB1);
7264 ins_encode(lock_prefix,
7265 REX_reg_mem(newval, mem_ptr),
7266 OpcP, OpcS,
7267 reg_mem(newval, mem_ptr),
7268 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7269 REX_reg_breg(res, res), // movzbl
7270 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7271 ins_pipe( pipe_cmpxchg );
7272 %}
7273
7274
7275 instruct compareAndSwapN(rRegI res,
7276 memory mem_ptr,
7277 rax_RegN oldval, rRegN newval,
7278 rFlagsReg cr) %{
7279 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7280 effect(KILL cr, KILL oldval);
7281
7282 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7283 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7284 "sete $res\n\t"
7285 "movzbl $res, $res" %}
7286 opcode(0x0F, 0xB1);
7287 ins_encode(lock_prefix,
7288 REX_reg_mem(newval, mem_ptr),
7289 OpcP, OpcS,
7290 reg_mem(newval, mem_ptr),
7291 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7292 REX_reg_breg(res, res), // movzbl
7293 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7294 ins_pipe( pipe_cmpxchg );
7295 %}
7296
7297 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7298 predicate(n->as_LoadStore()->result_not_used());
7299 match(Set dummy (GetAndAddI mem add));
7300 effect(KILL cr);
7301 format %{ "ADDL [$mem],$add" %}
7302 ins_encode %{
7303 if (os::is_MP()) { __ lock(); }
7304 __ addl($mem$$Address, $add$$constant);
7305 %}
7306 ins_pipe( pipe_cmpxchg );
7307 %}
7308
7309 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7310 match(Set newval (GetAndAddI mem newval));
7311 effect(KILL cr);
7312 format %{ "XADDL [$mem],$newval" %}
7313 ins_encode %{
7314 if (os::is_MP()) { __ lock(); }
7315 __ xaddl($mem$$Address, $newval$$Register);
7316 %}
7317 ins_pipe( pipe_cmpxchg );
7318 %}
7319
7320 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7321 predicate(n->as_LoadStore()->result_not_used());
7322 match(Set dummy (GetAndAddL mem add));
7323 effect(KILL cr);
7324 format %{ "ADDQ [$mem],$add" %}
7325 ins_encode %{
7326 if (os::is_MP()) { __ lock(); }
7327 __ addq($mem$$Address, $add$$constant);
7328 %}
7329 ins_pipe( pipe_cmpxchg );
7330 %}
7331
7332 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7333 match(Set newval (GetAndAddL mem newval));
7334 effect(KILL cr);
7335 format %{ "XADDQ [$mem],$newval" %}
7336 ins_encode %{
7337 if (os::is_MP()) { __ lock(); }
7338 __ xaddq($mem$$Address, $newval$$Register);
7339 %}
7340 ins_pipe( pipe_cmpxchg );
7341 %}
7342
7343 instruct xchgI( memory mem, rRegI newval) %{
7344 match(Set newval (GetAndSetI mem newval));
7345 format %{ "XCHGL $newval,[$mem]" %}
7346 ins_encode %{
7347 __ xchgl($newval$$Register, $mem$$Address);
7348 %}
7349 ins_pipe( pipe_cmpxchg );
7350 %}
7351
7352 instruct xchgL( memory mem, rRegL newval) %{
7353 match(Set newval (GetAndSetL mem newval));
7354 format %{ "XCHGL $newval,[$mem]" %}
7355 ins_encode %{
7356 __ xchgq($newval$$Register, $mem$$Address);
7357 %}
7358 ins_pipe( pipe_cmpxchg );
7359 %}
7360
7361 instruct xchgP( memory mem, rRegP newval) %{
7362 match(Set newval (GetAndSetP mem newval));
7363 format %{ "XCHGQ $newval,[$mem]" %}
7364 ins_encode %{
7365 __ xchgq($newval$$Register, $mem$$Address);
7366 %}
7367 ins_pipe( pipe_cmpxchg );
7368 %}
7369
7370 instruct xchgN( memory mem, rRegN newval) %{
7371 match(Set newval (GetAndSetN mem newval));
7372 format %{ "XCHGL $newval,$mem]" %}
7373 ins_encode %{
7374 __ xchgl($newval$$Register, $mem$$Address);
7375 %}
7376 ins_pipe( pipe_cmpxchg );
7377 %}
7378
7379 //----------Subtraction Instructions-------------------------------------------
7380
7381 // Integer Subtraction Instructions
7382 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7383 %{
7384 match(Set dst (SubI dst src));
7385 effect(KILL cr);
7386
7387 format %{ "subl $dst, $src\t# int" %}
7388 opcode(0x2B);
7389 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7390 ins_pipe(ialu_reg_reg);
7391 %}
7392
7393 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7394 %{
7395 match(Set dst (SubI dst src));
7396 effect(KILL cr);
7397
7398 format %{ "subl $dst, $src\t# int" %}
7399 opcode(0x81, 0x05); /* Opcode 81 /5 */
7400 ins_encode(OpcSErm(dst, src), Con8or32(src));
7401 ins_pipe(ialu_reg);
7402 %}
7403
7404 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7405 %{
7406 match(Set dst (SubI dst (LoadI src)));
7407 effect(KILL cr);
7408
7409 ins_cost(125);
7410 format %{ "subl $dst, $src\t# int" %}
7411 opcode(0x2B);
7412 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7413 ins_pipe(ialu_reg_mem);
7414 %}
7415
7416 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7417 %{
7418 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7419 effect(KILL cr);
7420
7421 ins_cost(150);
7422 format %{ "subl $dst, $src\t# int" %}
7423 opcode(0x29); /* Opcode 29 /r */
7424 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7425 ins_pipe(ialu_mem_reg);
7426 %}
7427
7428 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7429 %{
7430 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7431 effect(KILL cr);
7432
7433 ins_cost(125); // XXX
7434 format %{ "subl $dst, $src\t# int" %}
7435 opcode(0x81); /* Opcode 81 /5 id */
7436 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7437 ins_pipe(ialu_mem_imm);
7438 %}
7439
7440 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7441 %{
7442 match(Set dst (SubL dst src));
7443 effect(KILL cr);
7444
7445 format %{ "subq $dst, $src\t# long" %}
7446 opcode(0x2B);
7447 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7448 ins_pipe(ialu_reg_reg);
7449 %}
7450
7451 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7452 %{
7453 match(Set dst (SubL dst src));
7454 effect(KILL cr);
7455
7456 format %{ "subq $dst, $src\t# long" %}
7457 opcode(0x81, 0x05); /* Opcode 81 /5 */
7458 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7459 ins_pipe(ialu_reg);
7460 %}
7461
7462 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7463 %{
7464 match(Set dst (SubL dst (LoadL src)));
7465 effect(KILL cr);
7466
7467 ins_cost(125);
7468 format %{ "subq $dst, $src\t# long" %}
7469 opcode(0x2B);
7470 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7471 ins_pipe(ialu_reg_mem);
7472 %}
7473
7474 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7475 %{
7476 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7477 effect(KILL cr);
7478
7479 ins_cost(150);
7480 format %{ "subq $dst, $src\t# long" %}
7481 opcode(0x29); /* Opcode 29 /r */
7482 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7483 ins_pipe(ialu_mem_reg);
7484 %}
7485
7486 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7487 %{
7488 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7489 effect(KILL cr);
7490
7491 ins_cost(125); // XXX
7492 format %{ "subq $dst, $src\t# long" %}
7493 opcode(0x81); /* Opcode 81 /5 id */
7494 ins_encode(REX_mem_wide(dst),
7495 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7496 ins_pipe(ialu_mem_imm);
7497 %}
7498
7499 // Subtract from a pointer
7500 // XXX hmpf???
7501 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7502 %{
7503 match(Set dst (AddP dst (SubI zero src)));
7504 effect(KILL cr);
7505
7506 format %{ "subq $dst, $src\t# ptr - int" %}
7507 opcode(0x2B);
7508 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7509 ins_pipe(ialu_reg_reg);
7510 %}
7511
7512 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7513 %{
7514 match(Set dst (SubI zero dst));
7515 effect(KILL cr);
7516
7517 format %{ "negl $dst\t# int" %}
7518 opcode(0xF7, 0x03); // Opcode F7 /3
7519 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7520 ins_pipe(ialu_reg);
7521 %}
7522
7523 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7524 %{
7525 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7526 effect(KILL cr);
7527
7528 format %{ "negl $dst\t# int" %}
7529 opcode(0xF7, 0x03); // Opcode F7 /3
7530 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7531 ins_pipe(ialu_reg);
7532 %}
7533
7534 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7535 %{
7536 match(Set dst (SubL zero dst));
7537 effect(KILL cr);
7538
7539 format %{ "negq $dst\t# long" %}
7540 opcode(0xF7, 0x03); // Opcode F7 /3
7541 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7542 ins_pipe(ialu_reg);
7543 %}
7544
7545 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7546 %{
7547 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7548 effect(KILL cr);
7549
7550 format %{ "negq $dst\t# long" %}
7551 opcode(0xF7, 0x03); // Opcode F7 /3
7552 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7553 ins_pipe(ialu_reg);
7554 %}
7555
7556 //----------Multiplication/Division Instructions-------------------------------
7557 // Integer Multiplication Instructions
7558 // Multiply Register
7559
7560 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7561 %{
7562 match(Set dst (MulI dst src));
7563 effect(KILL cr);
7564
7565 ins_cost(300);
7566 format %{ "imull $dst, $src\t# int" %}
7567 opcode(0x0F, 0xAF);
7568 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7569 ins_pipe(ialu_reg_reg_alu0);
7570 %}
7571
7572 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7573 %{
7574 match(Set dst (MulI src imm));
7575 effect(KILL cr);
7576
7577 ins_cost(300);
7578 format %{ "imull $dst, $src, $imm\t# int" %}
7579 opcode(0x69); /* 69 /r id */
7580 ins_encode(REX_reg_reg(dst, src),
7581 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7582 ins_pipe(ialu_reg_reg_alu0);
7583 %}
7584
7585 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7586 %{
7587 match(Set dst (MulI dst (LoadI src)));
7588 effect(KILL cr);
7589
7590 ins_cost(350);
7591 format %{ "imull $dst, $src\t# int" %}
7592 opcode(0x0F, 0xAF);
7593 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7594 ins_pipe(ialu_reg_mem_alu0);
7595 %}
7596
7597 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7598 %{
7599 match(Set dst (MulI (LoadI src) imm));
7600 effect(KILL cr);
7601
7602 ins_cost(300);
7603 format %{ "imull $dst, $src, $imm\t# int" %}
7604 opcode(0x69); /* 69 /r id */
7605 ins_encode(REX_reg_mem(dst, src),
7606 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7607 ins_pipe(ialu_reg_mem_alu0);
7608 %}
7609
7610 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7611 %{
7612 match(Set dst (MulL dst src));
7613 effect(KILL cr);
7614
7615 ins_cost(300);
7616 format %{ "imulq $dst, $src\t# long" %}
7617 opcode(0x0F, 0xAF);
7618 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7619 ins_pipe(ialu_reg_reg_alu0);
7620 %}
7621
7622 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7623 %{
7624 match(Set dst (MulL src imm));
7625 effect(KILL cr);
7626
7627 ins_cost(300);
7628 format %{ "imulq $dst, $src, $imm\t# long" %}
7629 opcode(0x69); /* 69 /r id */
7630 ins_encode(REX_reg_reg_wide(dst, src),
7631 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7632 ins_pipe(ialu_reg_reg_alu0);
7633 %}
7634
7635 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7636 %{
7637 match(Set dst (MulL dst (LoadL src)));
7638 effect(KILL cr);
7639
7640 ins_cost(350);
7641 format %{ "imulq $dst, $src\t# long" %}
7642 opcode(0x0F, 0xAF);
7643 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7644 ins_pipe(ialu_reg_mem_alu0);
7645 %}
7646
7647 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7648 %{
7649 match(Set dst (MulL (LoadL src) imm));
7650 effect(KILL cr);
7651
7652 ins_cost(300);
7653 format %{ "imulq $dst, $src, $imm\t# long" %}
7654 opcode(0x69); /* 69 /r id */
7655 ins_encode(REX_reg_mem_wide(dst, src),
7656 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7657 ins_pipe(ialu_reg_mem_alu0);
7658 %}
7659
7660 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7661 %{
7662 match(Set dst (MulHiL src rax));
7663 effect(USE_KILL rax, KILL cr);
7664
7665 ins_cost(300);
7666 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7667 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7668 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7669 ins_pipe(ialu_reg_reg_alu0);
7670 %}
7671
7672 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7673 rFlagsReg cr)
7674 %{
7675 match(Set rax (DivI rax div));
7676 effect(KILL rdx, KILL cr);
7677
7678 ins_cost(30*100+10*100); // XXX
7679 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7680 "jne,s normal\n\t"
7681 "xorl rdx, rdx\n\t"
7682 "cmpl $div, -1\n\t"
7683 "je,s done\n"
7684 "normal: cdql\n\t"
7685 "idivl $div\n"
7686 "done:" %}
7687 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7688 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7689 ins_pipe(ialu_reg_reg_alu0);
7690 %}
7691
7692 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7693 rFlagsReg cr)
7694 %{
7695 match(Set rax (DivL rax div));
7696 effect(KILL rdx, KILL cr);
7697
7698 ins_cost(30*100+10*100); // XXX
7699 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7700 "cmpq rax, rdx\n\t"
7701 "jne,s normal\n\t"
7702 "xorl rdx, rdx\n\t"
7703 "cmpq $div, -1\n\t"
7704 "je,s done\n"
7705 "normal: cdqq\n\t"
7706 "idivq $div\n"
7707 "done:" %}
7708 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7709 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7710 ins_pipe(ialu_reg_reg_alu0);
7711 %}
7712
7713 // Integer DIVMOD with Register, both quotient and mod results
7714 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7715 rFlagsReg cr)
7716 %{
7717 match(DivModI rax div);
7718 effect(KILL cr);
7719
7720 ins_cost(30*100+10*100); // XXX
7721 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7722 "jne,s normal\n\t"
7723 "xorl rdx, rdx\n\t"
7724 "cmpl $div, -1\n\t"
7725 "je,s done\n"
7726 "normal: cdql\n\t"
7727 "idivl $div\n"
7728 "done:" %}
7729 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7730 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7731 ins_pipe(pipe_slow);
7732 %}
7733
7734 // Long DIVMOD with Register, both quotient and mod results
7735 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7736 rFlagsReg cr)
7737 %{
7738 match(DivModL rax div);
7739 effect(KILL cr);
7740
7741 ins_cost(30*100+10*100); // XXX
7742 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7743 "cmpq rax, rdx\n\t"
7744 "jne,s normal\n\t"
7745 "xorl rdx, rdx\n\t"
7746 "cmpq $div, -1\n\t"
7747 "je,s done\n"
7748 "normal: cdqq\n\t"
7749 "idivq $div\n"
7750 "done:" %}
7751 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7752 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7753 ins_pipe(pipe_slow);
7754 %}
7755
7756 //----------- DivL-By-Constant-Expansions--------------------------------------
7757 // DivI cases are handled by the compiler
7758
7759 // Magic constant, reciprocal of 10
7760 instruct loadConL_0x6666666666666667(rRegL dst)
7761 %{
7762 effect(DEF dst);
7763
7764 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7765 ins_encode(load_immL(dst, 0x6666666666666667));
7766 ins_pipe(ialu_reg);
7767 %}
7768
7769 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7770 %{
7771 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7772
7773 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7774 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7775 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7776 ins_pipe(ialu_reg_reg_alu0);
7777 %}
7778
7779 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7780 %{
7781 effect(USE_DEF dst, KILL cr);
7782
7783 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7784 opcode(0xC1, 0x7); /* C1 /7 ib */
7785 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7786 ins_pipe(ialu_reg);
7787 %}
7788
7789 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7790 %{
7791 effect(USE_DEF dst, KILL cr);
7792
7793 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7794 opcode(0xC1, 0x7); /* C1 /7 ib */
7795 ins_encode(reg_opc_imm_wide(dst, 0x2));
7796 ins_pipe(ialu_reg);
7797 %}
7798
7799 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7800 %{
7801 match(Set dst (DivL src div));
7802
7803 ins_cost((5+8)*100);
7804 expand %{
7805 rax_RegL rax; // Killed temp
7806 rFlagsReg cr; // Killed
7807 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7808 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7809 sarL_rReg_63(src, cr); // sarq src, 63
7810 sarL_rReg_2(dst, cr); // sarq rdx, 2
7811 subL_rReg(dst, src, cr); // subl rdx, src
7812 %}
7813 %}
7814
7815 //-----------------------------------------------------------------------------
7816
7817 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7818 rFlagsReg cr)
7819 %{
7820 match(Set rdx (ModI rax div));
7821 effect(KILL rax, KILL cr);
7822
7823 ins_cost(300); // XXX
7824 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7825 "jne,s normal\n\t"
7826 "xorl rdx, rdx\n\t"
7827 "cmpl $div, -1\n\t"
7828 "je,s done\n"
7829 "normal: cdql\n\t"
7830 "idivl $div\n"
7831 "done:" %}
7832 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7833 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7834 ins_pipe(ialu_reg_reg_alu0);
7835 %}
7836
7837 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7838 rFlagsReg cr)
7839 %{
7840 match(Set rdx (ModL rax div));
7841 effect(KILL rax, KILL cr);
7842
7843 ins_cost(300); // XXX
7844 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
7845 "cmpq rax, rdx\n\t"
7846 "jne,s normal\n\t"
7847 "xorl rdx, rdx\n\t"
7848 "cmpq $div, -1\n\t"
7849 "je,s done\n"
7850 "normal: cdqq\n\t"
7851 "idivq $div\n"
7852 "done:" %}
7853 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7854 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7855 ins_pipe(ialu_reg_reg_alu0);
7856 %}
7857
7858 // Integer Shift Instructions
7859 // Shift Left by one
7860 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7861 %{
7862 match(Set dst (LShiftI dst shift));
7863 effect(KILL cr);
7864
7865 format %{ "sall $dst, $shift" %}
7866 opcode(0xD1, 0x4); /* D1 /4 */
7867 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7868 ins_pipe(ialu_reg);
7869 %}
7870
7871 // Shift Left by one
7872 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7873 %{
7874 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7875 effect(KILL cr);
7876
7877 format %{ "sall $dst, $shift\t" %}
7878 opcode(0xD1, 0x4); /* D1 /4 */
7879 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7880 ins_pipe(ialu_mem_imm);
7881 %}
7882
7883 // Shift Left by 8-bit immediate
7884 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7885 %{
7886 match(Set dst (LShiftI dst shift));
7887 effect(KILL cr);
7888
7889 format %{ "sall $dst, $shift" %}
7890 opcode(0xC1, 0x4); /* C1 /4 ib */
7891 ins_encode(reg_opc_imm(dst, shift));
7892 ins_pipe(ialu_reg);
7893 %}
7894
7895 // Shift Left by 8-bit immediate
7896 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7897 %{
7898 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7899 effect(KILL cr);
7900
7901 format %{ "sall $dst, $shift" %}
7902 opcode(0xC1, 0x4); /* C1 /4 ib */
7903 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7904 ins_pipe(ialu_mem_imm);
7905 %}
7906
7907 // Shift Left by variable
7908 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7909 %{
7910 match(Set dst (LShiftI dst shift));
7911 effect(KILL cr);
7912
7913 format %{ "sall $dst, $shift" %}
7914 opcode(0xD3, 0x4); /* D3 /4 */
7915 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7916 ins_pipe(ialu_reg_reg);
7917 %}
7918
7919 // Shift Left by variable
7920 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7921 %{
7922 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
7923 effect(KILL cr);
7924
7925 format %{ "sall $dst, $shift" %}
7926 opcode(0xD3, 0x4); /* D3 /4 */
7927 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7928 ins_pipe(ialu_mem_reg);
7929 %}
7930
7931 // Arithmetic shift right by one
7932 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
7933 %{
7934 match(Set dst (RShiftI dst shift));
7935 effect(KILL cr);
7936
7937 format %{ "sarl $dst, $shift" %}
7938 opcode(0xD1, 0x7); /* D1 /7 */
7939 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7940 ins_pipe(ialu_reg);
7941 %}
7942
7943 // Arithmetic shift right by one
7944 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
7945 %{
7946 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7947 effect(KILL cr);
7948
7949 format %{ "sarl $dst, $shift" %}
7950 opcode(0xD1, 0x7); /* D1 /7 */
7951 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7952 ins_pipe(ialu_mem_imm);
7953 %}
7954
7955 // Arithmetic Shift Right by 8-bit immediate
7956 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
7957 %{
7958 match(Set dst (RShiftI dst shift));
7959 effect(KILL cr);
7960
7961 format %{ "sarl $dst, $shift" %}
7962 opcode(0xC1, 0x7); /* C1 /7 ib */
7963 ins_encode(reg_opc_imm(dst, shift));
7964 ins_pipe(ialu_mem_imm);
7965 %}
7966
7967 // Arithmetic Shift Right by 8-bit immediate
7968 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
7969 %{
7970 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7971 effect(KILL cr);
7972
7973 format %{ "sarl $dst, $shift" %}
7974 opcode(0xC1, 0x7); /* C1 /7 ib */
7975 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
7976 ins_pipe(ialu_mem_imm);
7977 %}
7978
7979 // Arithmetic Shift Right by variable
7980 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
7981 %{
7982 match(Set dst (RShiftI dst shift));
7983 effect(KILL cr);
7984
7985 format %{ "sarl $dst, $shift" %}
7986 opcode(0xD3, 0x7); /* D3 /7 */
7987 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7988 ins_pipe(ialu_reg_reg);
7989 %}
7990
7991 // Arithmetic Shift Right by variable
7992 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
7993 %{
7994 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
7995 effect(KILL cr);
7996
7997 format %{ "sarl $dst, $shift" %}
7998 opcode(0xD3, 0x7); /* D3 /7 */
7999 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8000 ins_pipe(ialu_mem_reg);
8001 %}
8002
8003 // Logical shift right by one
8004 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8005 %{
8006 match(Set dst (URShiftI dst shift));
8007 effect(KILL cr);
8008
8009 format %{ "shrl $dst, $shift" %}
8010 opcode(0xD1, 0x5); /* D1 /5 */
8011 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8012 ins_pipe(ialu_reg);
8013 %}
8014
8015 // Logical shift right by one
8016 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8017 %{
8018 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8019 effect(KILL cr);
8020
8021 format %{ "shrl $dst, $shift" %}
8022 opcode(0xD1, 0x5); /* D1 /5 */
8023 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8024 ins_pipe(ialu_mem_imm);
8025 %}
8026
8027 // Logical Shift Right by 8-bit immediate
8028 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8029 %{
8030 match(Set dst (URShiftI dst shift));
8031 effect(KILL cr);
8032
8033 format %{ "shrl $dst, $shift" %}
8034 opcode(0xC1, 0x5); /* C1 /5 ib */
8035 ins_encode(reg_opc_imm(dst, shift));
8036 ins_pipe(ialu_reg);
8037 %}
8038
8039 // Logical Shift Right by 8-bit immediate
8040 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8041 %{
8042 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8043 effect(KILL cr);
8044
8045 format %{ "shrl $dst, $shift" %}
8046 opcode(0xC1, 0x5); /* C1 /5 ib */
8047 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8048 ins_pipe(ialu_mem_imm);
8049 %}
8050
8051 // Logical Shift Right by variable
8052 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8053 %{
8054 match(Set dst (URShiftI dst shift));
8055 effect(KILL cr);
8056
8057 format %{ "shrl $dst, $shift" %}
8058 opcode(0xD3, 0x5); /* D3 /5 */
8059 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8060 ins_pipe(ialu_reg_reg);
8061 %}
8062
8063 // Logical Shift Right by variable
8064 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8065 %{
8066 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8067 effect(KILL cr);
8068
8069 format %{ "shrl $dst, $shift" %}
8070 opcode(0xD3, 0x5); /* D3 /5 */
8071 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8072 ins_pipe(ialu_mem_reg);
8073 %}
8074
8075 // Long Shift Instructions
8076 // Shift Left by one
8077 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8078 %{
8079 match(Set dst (LShiftL dst shift));
8080 effect(KILL cr);
8081
8082 format %{ "salq $dst, $shift" %}
8083 opcode(0xD1, 0x4); /* D1 /4 */
8084 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8085 ins_pipe(ialu_reg);
8086 %}
8087
8088 // Shift Left by one
8089 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8090 %{
8091 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8092 effect(KILL cr);
8093
8094 format %{ "salq $dst, $shift" %}
8095 opcode(0xD1, 0x4); /* D1 /4 */
8096 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8097 ins_pipe(ialu_mem_imm);
8098 %}
8099
8100 // Shift Left by 8-bit immediate
8101 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8102 %{
8103 match(Set dst (LShiftL dst shift));
8104 effect(KILL cr);
8105
8106 format %{ "salq $dst, $shift" %}
8107 opcode(0xC1, 0x4); /* C1 /4 ib */
8108 ins_encode(reg_opc_imm_wide(dst, shift));
8109 ins_pipe(ialu_reg);
8110 %}
8111
8112 // Shift Left by 8-bit immediate
8113 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8114 %{
8115 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8116 effect(KILL cr);
8117
8118 format %{ "salq $dst, $shift" %}
8119 opcode(0xC1, 0x4); /* C1 /4 ib */
8120 ins_encode(REX_mem_wide(dst), OpcP,
8121 RM_opc_mem(secondary, dst), Con8or32(shift));
8122 ins_pipe(ialu_mem_imm);
8123 %}
8124
8125 // Shift Left by variable
8126 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8127 %{
8128 match(Set dst (LShiftL dst shift));
8129 effect(KILL cr);
8130
8131 format %{ "salq $dst, $shift" %}
8132 opcode(0xD3, 0x4); /* D3 /4 */
8133 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8134 ins_pipe(ialu_reg_reg);
8135 %}
8136
8137 // Shift Left by variable
8138 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8139 %{
8140 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8141 effect(KILL cr);
8142
8143 format %{ "salq $dst, $shift" %}
8144 opcode(0xD3, 0x4); /* D3 /4 */
8145 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8146 ins_pipe(ialu_mem_reg);
8147 %}
8148
8149 // Arithmetic shift right by one
8150 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8151 %{
8152 match(Set dst (RShiftL dst shift));
8153 effect(KILL cr);
8154
8155 format %{ "sarq $dst, $shift" %}
8156 opcode(0xD1, 0x7); /* D1 /7 */
8157 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8158 ins_pipe(ialu_reg);
8159 %}
8160
8161 // Arithmetic shift right by one
8162 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8163 %{
8164 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8165 effect(KILL cr);
8166
8167 format %{ "sarq $dst, $shift" %}
8168 opcode(0xD1, 0x7); /* D1 /7 */
8169 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8170 ins_pipe(ialu_mem_imm);
8171 %}
8172
8173 // Arithmetic Shift Right by 8-bit immediate
8174 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8175 %{
8176 match(Set dst (RShiftL dst shift));
8177 effect(KILL cr);
8178
8179 format %{ "sarq $dst, $shift" %}
8180 opcode(0xC1, 0x7); /* C1 /7 ib */
8181 ins_encode(reg_opc_imm_wide(dst, shift));
8182 ins_pipe(ialu_mem_imm);
8183 %}
8184
8185 // Arithmetic Shift Right by 8-bit immediate
8186 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8187 %{
8188 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8189 effect(KILL cr);
8190
8191 format %{ "sarq $dst, $shift" %}
8192 opcode(0xC1, 0x7); /* C1 /7 ib */
8193 ins_encode(REX_mem_wide(dst), OpcP,
8194 RM_opc_mem(secondary, dst), Con8or32(shift));
8195 ins_pipe(ialu_mem_imm);
8196 %}
8197
8198 // Arithmetic Shift Right by variable
8199 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8200 %{
8201 match(Set dst (RShiftL dst shift));
8202 effect(KILL cr);
8203
8204 format %{ "sarq $dst, $shift" %}
8205 opcode(0xD3, 0x7); /* D3 /7 */
8206 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8207 ins_pipe(ialu_reg_reg);
8208 %}
8209
8210 // Arithmetic Shift Right by variable
8211 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8212 %{
8213 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8214 effect(KILL cr);
8215
8216 format %{ "sarq $dst, $shift" %}
8217 opcode(0xD3, 0x7); /* D3 /7 */
8218 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8219 ins_pipe(ialu_mem_reg);
8220 %}
8221
8222 // Logical shift right by one
8223 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8224 %{
8225 match(Set dst (URShiftL dst shift));
8226 effect(KILL cr);
8227
8228 format %{ "shrq $dst, $shift" %}
8229 opcode(0xD1, 0x5); /* D1 /5 */
8230 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8231 ins_pipe(ialu_reg);
8232 %}
8233
8234 // Logical shift right by one
8235 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8236 %{
8237 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8238 effect(KILL cr);
8239
8240 format %{ "shrq $dst, $shift" %}
8241 opcode(0xD1, 0x5); /* D1 /5 */
8242 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8243 ins_pipe(ialu_mem_imm);
8244 %}
8245
8246 // Logical Shift Right by 8-bit immediate
8247 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8248 %{
8249 match(Set dst (URShiftL dst shift));
8250 effect(KILL cr);
8251
8252 format %{ "shrq $dst, $shift" %}
8253 opcode(0xC1, 0x5); /* C1 /5 ib */
8254 ins_encode(reg_opc_imm_wide(dst, shift));
8255 ins_pipe(ialu_reg);
8256 %}
8257
8258
8259 // Logical Shift Right by 8-bit immediate
8260 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8261 %{
8262 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8263 effect(KILL cr);
8264
8265 format %{ "shrq $dst, $shift" %}
8266 opcode(0xC1, 0x5); /* C1 /5 ib */
8267 ins_encode(REX_mem_wide(dst), OpcP,
8268 RM_opc_mem(secondary, dst), Con8or32(shift));
8269 ins_pipe(ialu_mem_imm);
8270 %}
8271
8272 // Logical Shift Right by variable
8273 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8274 %{
8275 match(Set dst (URShiftL dst shift));
8276 effect(KILL cr);
8277
8278 format %{ "shrq $dst, $shift" %}
8279 opcode(0xD3, 0x5); /* D3 /5 */
8280 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8281 ins_pipe(ialu_reg_reg);
8282 %}
8283
8284 // Logical Shift Right by variable
8285 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8286 %{
8287 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8288 effect(KILL cr);
8289
8290 format %{ "shrq $dst, $shift" %}
8291 opcode(0xD3, 0x5); /* D3 /5 */
8292 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8293 ins_pipe(ialu_mem_reg);
8294 %}
8295
8296 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8297 // This idiom is used by the compiler for the i2b bytecode.
8298 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8299 %{
8300 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8301
8302 format %{ "movsbl $dst, $src\t# i2b" %}
8303 opcode(0x0F, 0xBE);
8304 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8305 ins_pipe(ialu_reg_reg);
8306 %}
8307
8308 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8309 // This idiom is used by the compiler the i2s bytecode.
8310 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8311 %{
8312 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8313
8314 format %{ "movswl $dst, $src\t# i2s" %}
8315 opcode(0x0F, 0xBF);
8316 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8317 ins_pipe(ialu_reg_reg);
8318 %}
8319
8320 // ROL/ROR instructions
8321
8322 // ROL expand
8323 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8324 effect(KILL cr, USE_DEF dst);
8325
8326 format %{ "roll $dst" %}
8327 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8328 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8329 ins_pipe(ialu_reg);
8330 %}
8331
8332 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8333 effect(USE_DEF dst, USE shift, KILL cr);
8334
8335 format %{ "roll $dst, $shift" %}
8336 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8337 ins_encode( reg_opc_imm(dst, shift) );
8338 ins_pipe(ialu_reg);
8339 %}
8340
8341 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8342 %{
8343 effect(USE_DEF dst, USE shift, KILL cr);
8344
8345 format %{ "roll $dst, $shift" %}
8346 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8347 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8348 ins_pipe(ialu_reg_reg);
8349 %}
8350 // end of ROL expand
8351
8352 // Rotate Left by one
8353 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8354 %{
8355 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8356
8357 expand %{
8358 rolI_rReg_imm1(dst, cr);
8359 %}
8360 %}
8361
8362 // Rotate Left by 8-bit immediate
8363 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8364 %{
8365 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8366 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8367
8368 expand %{
8369 rolI_rReg_imm8(dst, lshift, cr);
8370 %}
8371 %}
8372
8373 // Rotate Left by variable
8374 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8375 %{
8376 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8377
8378 expand %{
8379 rolI_rReg_CL(dst, shift, cr);
8380 %}
8381 %}
8382
8383 // Rotate Left by variable
8384 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8385 %{
8386 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8387
8388 expand %{
8389 rolI_rReg_CL(dst, shift, cr);
8390 %}
8391 %}
8392
8393 // ROR expand
8394 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8395 %{
8396 effect(USE_DEF dst, KILL cr);
8397
8398 format %{ "rorl $dst" %}
8399 opcode(0xD1, 0x1); /* D1 /1 */
8400 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8401 ins_pipe(ialu_reg);
8402 %}
8403
8404 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8405 %{
8406 effect(USE_DEF dst, USE shift, KILL cr);
8407
8408 format %{ "rorl $dst, $shift" %}
8409 opcode(0xC1, 0x1); /* C1 /1 ib */
8410 ins_encode(reg_opc_imm(dst, shift));
8411 ins_pipe(ialu_reg);
8412 %}
8413
8414 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8415 %{
8416 effect(USE_DEF dst, USE shift, KILL cr);
8417
8418 format %{ "rorl $dst, $shift" %}
8419 opcode(0xD3, 0x1); /* D3 /1 */
8420 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8421 ins_pipe(ialu_reg_reg);
8422 %}
8423 // end of ROR expand
8424
8425 // Rotate Right by one
8426 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8427 %{
8428 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8429
8430 expand %{
8431 rorI_rReg_imm1(dst, cr);
8432 %}
8433 %}
8434
8435 // Rotate Right by 8-bit immediate
8436 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8437 %{
8438 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8439 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8440
8441 expand %{
8442 rorI_rReg_imm8(dst, rshift, cr);
8443 %}
8444 %}
8445
8446 // Rotate Right by variable
8447 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8448 %{
8449 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8450
8451 expand %{
8452 rorI_rReg_CL(dst, shift, cr);
8453 %}
8454 %}
8455
8456 // Rotate Right by variable
8457 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8458 %{
8459 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8460
8461 expand %{
8462 rorI_rReg_CL(dst, shift, cr);
8463 %}
8464 %}
8465
8466 // for long rotate
8467 // ROL expand
8468 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8469 effect(USE_DEF dst, KILL cr);
8470
8471 format %{ "rolq $dst" %}
8472 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8473 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8474 ins_pipe(ialu_reg);
8475 %}
8476
8477 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8478 effect(USE_DEF dst, USE shift, KILL cr);
8479
8480 format %{ "rolq $dst, $shift" %}
8481 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8482 ins_encode( reg_opc_imm_wide(dst, shift) );
8483 ins_pipe(ialu_reg);
8484 %}
8485
8486 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8487 %{
8488 effect(USE_DEF dst, USE shift, KILL cr);
8489
8490 format %{ "rolq $dst, $shift" %}
8491 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8492 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8493 ins_pipe(ialu_reg_reg);
8494 %}
8495 // end of ROL expand
8496
8497 // Rotate Left by one
8498 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8499 %{
8500 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8501
8502 expand %{
8503 rolL_rReg_imm1(dst, cr);
8504 %}
8505 %}
8506
8507 // Rotate Left by 8-bit immediate
8508 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8509 %{
8510 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8511 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8512
8513 expand %{
8514 rolL_rReg_imm8(dst, lshift, cr);
8515 %}
8516 %}
8517
8518 // Rotate Left by variable
8519 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8520 %{
8521 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8522
8523 expand %{
8524 rolL_rReg_CL(dst, shift, cr);
8525 %}
8526 %}
8527
8528 // Rotate Left by variable
8529 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8530 %{
8531 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8532
8533 expand %{
8534 rolL_rReg_CL(dst, shift, cr);
8535 %}
8536 %}
8537
8538 // ROR expand
8539 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8540 %{
8541 effect(USE_DEF dst, KILL cr);
8542
8543 format %{ "rorq $dst" %}
8544 opcode(0xD1, 0x1); /* D1 /1 */
8545 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8546 ins_pipe(ialu_reg);
8547 %}
8548
8549 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8550 %{
8551 effect(USE_DEF dst, USE shift, KILL cr);
8552
8553 format %{ "rorq $dst, $shift" %}
8554 opcode(0xC1, 0x1); /* C1 /1 ib */
8555 ins_encode(reg_opc_imm_wide(dst, shift));
8556 ins_pipe(ialu_reg);
8557 %}
8558
8559 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8560 %{
8561 effect(USE_DEF dst, USE shift, KILL cr);
8562
8563 format %{ "rorq $dst, $shift" %}
8564 opcode(0xD3, 0x1); /* D3 /1 */
8565 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8566 ins_pipe(ialu_reg_reg);
8567 %}
8568 // end of ROR expand
8569
8570 // Rotate Right by one
8571 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8572 %{
8573 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8574
8575 expand %{
8576 rorL_rReg_imm1(dst, cr);
8577 %}
8578 %}
8579
8580 // Rotate Right by 8-bit immediate
8581 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8582 %{
8583 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8584 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8585
8586 expand %{
8587 rorL_rReg_imm8(dst, rshift, cr);
8588 %}
8589 %}
8590
8591 // Rotate Right by variable
8592 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8593 %{
8594 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8595
8596 expand %{
8597 rorL_rReg_CL(dst, shift, cr);
8598 %}
8599 %}
8600
8601 // Rotate Right by variable
8602 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8603 %{
8604 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8605
8606 expand %{
8607 rorL_rReg_CL(dst, shift, cr);
8608 %}
8609 %}
8610
8611 // Logical Instructions
8612
8613 // Integer Logical Instructions
8614
8615 // And Instructions
8616 // And Register with Register
8617 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8618 %{
8619 match(Set dst (AndI dst src));
8620 effect(KILL cr);
8621
8622 format %{ "andl $dst, $src\t# int" %}
8623 opcode(0x23);
8624 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8625 ins_pipe(ialu_reg_reg);
8626 %}
8627
8628 // And Register with Immediate 255
8629 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8630 %{
8631 match(Set dst (AndI dst src));
8632
8633 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8634 opcode(0x0F, 0xB6);
8635 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8636 ins_pipe(ialu_reg);
8637 %}
8638
8639 // And Register with Immediate 255 and promote to long
8640 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8641 %{
8642 match(Set dst (ConvI2L (AndI src mask)));
8643
8644 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8645 opcode(0x0F, 0xB6);
8646 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8647 ins_pipe(ialu_reg);
8648 %}
8649
8650 // And Register with Immediate 65535
8651 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8652 %{
8653 match(Set dst (AndI dst src));
8654
8655 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8656 opcode(0x0F, 0xB7);
8657 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8658 ins_pipe(ialu_reg);
8659 %}
8660
8661 // And Register with Immediate 65535 and promote to long
8662 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8663 %{
8664 match(Set dst (ConvI2L (AndI src mask)));
8665
8666 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8667 opcode(0x0F, 0xB7);
8668 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8669 ins_pipe(ialu_reg);
8670 %}
8671
8672 // And Register with Immediate
8673 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8674 %{
8675 match(Set dst (AndI dst src));
8676 effect(KILL cr);
8677
8678 format %{ "andl $dst, $src\t# int" %}
8679 opcode(0x81, 0x04); /* Opcode 81 /4 */
8680 ins_encode(OpcSErm(dst, src), Con8or32(src));
8681 ins_pipe(ialu_reg);
8682 %}
8683
8684 // And Register with Memory
8685 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8686 %{
8687 match(Set dst (AndI dst (LoadI src)));
8688 effect(KILL cr);
8689
8690 ins_cost(125);
8691 format %{ "andl $dst, $src\t# int" %}
8692 opcode(0x23);
8693 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8694 ins_pipe(ialu_reg_mem);
8695 %}
8696
8697 // And Memory with Register
8698 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8699 %{
8700 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8701 effect(KILL cr);
8702
8703 ins_cost(150);
8704 format %{ "andl $dst, $src\t# int" %}
8705 opcode(0x21); /* Opcode 21 /r */
8706 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8707 ins_pipe(ialu_mem_reg);
8708 %}
8709
8710 // And Memory with Immediate
8711 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8712 %{
8713 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8714 effect(KILL cr);
8715
8716 ins_cost(125);
8717 format %{ "andl $dst, $src\t# int" %}
8718 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8719 ins_encode(REX_mem(dst), OpcSE(src),
8720 RM_opc_mem(secondary, dst), Con8or32(src));
8721 ins_pipe(ialu_mem_imm);
8722 %}
8723
8724 // BMI1 instructions
8725 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8726 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8727 predicate(UseBMI1Instructions);
8728 effect(KILL cr);
8729
8730 ins_cost(125);
8731 format %{ "andnl $dst, $src1, $src2" %}
8732
8733 ins_encode %{
8734 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8735 %}
8736 ins_pipe(ialu_reg_mem);
8737 %}
8738
8739 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8740 match(Set dst (AndI (XorI src1 minus_1) src2));
8741 predicate(UseBMI1Instructions);
8742 effect(KILL cr);
8743
8744 format %{ "andnl $dst, $src1, $src2" %}
8745
8746 ins_encode %{
8747 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8748 %}
8749 ins_pipe(ialu_reg);
8750 %}
8751
8752 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8753 match(Set dst (AndI (SubI imm_zero src) src));
8754 predicate(UseBMI1Instructions);
8755 effect(KILL cr);
8756
8757 format %{ "blsil $dst, $src" %}
8758
8759 ins_encode %{
8760 __ blsil($dst$$Register, $src$$Register);
8761 %}
8762 ins_pipe(ialu_reg);
8763 %}
8764
8765 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8766 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8767 predicate(UseBMI1Instructions);
8768 effect(KILL cr);
8769
8770 ins_cost(125);
8771 format %{ "blsil $dst, $src" %}
8772
8773 ins_encode %{
8774 __ blsil($dst$$Register, $src$$Address);
8775 %}
8776 ins_pipe(ialu_reg_mem);
8777 %}
8778
8779 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8780 %{
8781 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8782 predicate(UseBMI1Instructions);
8783 effect(KILL cr);
8784
8785 ins_cost(125);
8786 format %{ "blsmskl $dst, $src" %}
8787
8788 ins_encode %{
8789 __ blsmskl($dst$$Register, $src$$Address);
8790 %}
8791 ins_pipe(ialu_reg_mem);
8792 %}
8793
8794 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8795 %{
8796 match(Set dst (XorI (AddI src minus_1) src));
8797 predicate(UseBMI1Instructions);
8798 effect(KILL cr);
8799
8800 format %{ "blsmskl $dst, $src" %}
8801
8802 ins_encode %{
8803 __ blsmskl($dst$$Register, $src$$Register);
8804 %}
8805
8806 ins_pipe(ialu_reg);
8807 %}
8808
8809 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8810 %{
8811 match(Set dst (AndI (AddI src minus_1) src) );
8812 predicate(UseBMI1Instructions);
8813 effect(KILL cr);
8814
8815 format %{ "blsrl $dst, $src" %}
8816
8817 ins_encode %{
8818 __ blsrl($dst$$Register, $src$$Register);
8819 %}
8820
8821 ins_pipe(ialu_reg_mem);
8822 %}
8823
8824 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8825 %{
8826 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8827 predicate(UseBMI1Instructions);
8828 effect(KILL cr);
8829
8830 ins_cost(125);
8831 format %{ "blsrl $dst, $src" %}
8832
8833 ins_encode %{
8834 __ blsrl($dst$$Register, $src$$Address);
8835 %}
8836
8837 ins_pipe(ialu_reg);
8838 %}
8839
8840 // Or Instructions
8841 // Or Register with Register
8842 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8843 %{
8844 match(Set dst (OrI dst src));
8845 effect(KILL cr);
8846
8847 format %{ "orl $dst, $src\t# int" %}
8848 opcode(0x0B);
8849 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8850 ins_pipe(ialu_reg_reg);
8851 %}
8852
8853 // Or Register with Immediate
8854 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8855 %{
8856 match(Set dst (OrI dst src));
8857 effect(KILL cr);
8858
8859 format %{ "orl $dst, $src\t# int" %}
8860 opcode(0x81, 0x01); /* Opcode 81 /1 id */
8861 ins_encode(OpcSErm(dst, src), Con8or32(src));
8862 ins_pipe(ialu_reg);
8863 %}
8864
8865 // Or Register with Memory
8866 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8867 %{
8868 match(Set dst (OrI dst (LoadI src)));
8869 effect(KILL cr);
8870
8871 ins_cost(125);
8872 format %{ "orl $dst, $src\t# int" %}
8873 opcode(0x0B);
8874 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8875 ins_pipe(ialu_reg_mem);
8876 %}
8877
8878 // Or Memory with Register
8879 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8880 %{
8881 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8882 effect(KILL cr);
8883
8884 ins_cost(150);
8885 format %{ "orl $dst, $src\t# int" %}
8886 opcode(0x09); /* Opcode 09 /r */
8887 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8888 ins_pipe(ialu_mem_reg);
8889 %}
8890
8891 // Or Memory with Immediate
8892 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
8893 %{
8894 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
8895 effect(KILL cr);
8896
8897 ins_cost(125);
8898 format %{ "orl $dst, $src\t# int" %}
8899 opcode(0x81, 0x1); /* Opcode 81 /1 id */
8900 ins_encode(REX_mem(dst), OpcSE(src),
8901 RM_opc_mem(secondary, dst), Con8or32(src));
8902 ins_pipe(ialu_mem_imm);
8903 %}
8904
8905 // Xor Instructions
8906 // Xor Register with Register
8907 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8908 %{
8909 match(Set dst (XorI dst src));
8910 effect(KILL cr);
8911
8912 format %{ "xorl $dst, $src\t# int" %}
8913 opcode(0x33);
8914 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8915 ins_pipe(ialu_reg_reg);
8916 %}
8917
8918 // Xor Register with Immediate -1
8919 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
8920 match(Set dst (XorI dst imm));
8921
8922 format %{ "not $dst" %}
8923 ins_encode %{
8924 __ notl($dst$$Register);
8925 %}
8926 ins_pipe(ialu_reg);
8927 %}
8928
8929 // Xor Register with Immediate
8930 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8931 %{
8932 match(Set dst (XorI dst src));
8933 effect(KILL cr);
8934
8935 format %{ "xorl $dst, $src\t# int" %}
8936 opcode(0x81, 0x06); /* Opcode 81 /6 id */
8937 ins_encode(OpcSErm(dst, src), Con8or32(src));
8938 ins_pipe(ialu_reg);
8939 %}
8940
8941 // Xor Register with Memory
8942 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8943 %{
8944 match(Set dst (XorI dst (LoadI src)));
8945 effect(KILL cr);
8946
8947 ins_cost(125);
8948 format %{ "xorl $dst, $src\t# int" %}
8949 opcode(0x33);
8950 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8951 ins_pipe(ialu_reg_mem);
8952 %}
8953
8954 // Xor Memory with Register
8955 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8956 %{
8957 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8958 effect(KILL cr);
8959
8960 ins_cost(150);
8961 format %{ "xorl $dst, $src\t# int" %}
8962 opcode(0x31); /* Opcode 31 /r */
8963 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8964 ins_pipe(ialu_mem_reg);
8965 %}
8966
8967 // Xor Memory with Immediate
8968 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
8969 %{
8970 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
8971 effect(KILL cr);
8972
8973 ins_cost(125);
8974 format %{ "xorl $dst, $src\t# int" %}
8975 opcode(0x81, 0x6); /* Opcode 81 /6 id */
8976 ins_encode(REX_mem(dst), OpcSE(src),
8977 RM_opc_mem(secondary, dst), Con8or32(src));
8978 ins_pipe(ialu_mem_imm);
8979 %}
8980
8981
8982 // Long Logical Instructions
8983
8984 // And Instructions
8985 // And Register with Register
8986 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8987 %{
8988 match(Set dst (AndL dst src));
8989 effect(KILL cr);
8990
8991 format %{ "andq $dst, $src\t# long" %}
8992 opcode(0x23);
8993 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8994 ins_pipe(ialu_reg_reg);
8995 %}
8996
8997 // And Register with Immediate 255
8998 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
8999 %{
9000 match(Set dst (AndL dst src));
9001
9002 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9003 opcode(0x0F, 0xB6);
9004 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9005 ins_pipe(ialu_reg);
9006 %}
9007
9008 // And Register with Immediate 65535
9009 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9010 %{
9011 match(Set dst (AndL dst src));
9012
9013 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9014 opcode(0x0F, 0xB7);
9015 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9016 ins_pipe(ialu_reg);
9017 %}
9018
9019 // And Register with Immediate
9020 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9021 %{
9022 match(Set dst (AndL dst src));
9023 effect(KILL cr);
9024
9025 format %{ "andq $dst, $src\t# long" %}
9026 opcode(0x81, 0x04); /* Opcode 81 /4 */
9027 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9028 ins_pipe(ialu_reg);
9029 %}
9030
9031 // And Register with Memory
9032 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9033 %{
9034 match(Set dst (AndL dst (LoadL src)));
9035 effect(KILL cr);
9036
9037 ins_cost(125);
9038 format %{ "andq $dst, $src\t# long" %}
9039 opcode(0x23);
9040 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9041 ins_pipe(ialu_reg_mem);
9042 %}
9043
9044 // And Memory with Register
9045 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9046 %{
9047 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9048 effect(KILL cr);
9049
9050 ins_cost(150);
9051 format %{ "andq $dst, $src\t# long" %}
9052 opcode(0x21); /* Opcode 21 /r */
9053 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9054 ins_pipe(ialu_mem_reg);
9055 %}
9056
9057 // And Memory with Immediate
9058 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9059 %{
9060 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9061 effect(KILL cr);
9062
9063 ins_cost(125);
9064 format %{ "andq $dst, $src\t# long" %}
9065 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9066 ins_encode(REX_mem_wide(dst), OpcSE(src),
9067 RM_opc_mem(secondary, dst), Con8or32(src));
9068 ins_pipe(ialu_mem_imm);
9069 %}
9070
9071 // BMI1 instructions
9072 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9073 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9074 predicate(UseBMI1Instructions);
9075 effect(KILL cr);
9076
9077 ins_cost(125);
9078 format %{ "andnq $dst, $src1, $src2" %}
9079
9080 ins_encode %{
9081 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9082 %}
9083 ins_pipe(ialu_reg_mem);
9084 %}
9085
9086 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9087 match(Set dst (AndL (XorL src1 minus_1) src2));
9088 predicate(UseBMI1Instructions);
9089 effect(KILL cr);
9090
9091 format %{ "andnq $dst, $src1, $src2" %}
9092
9093 ins_encode %{
9094 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9095 %}
9096 ins_pipe(ialu_reg_mem);
9097 %}
9098
9099 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9100 match(Set dst (AndL (SubL imm_zero src) src));
9101 predicate(UseBMI1Instructions);
9102 effect(KILL cr);
9103
9104 format %{ "blsiq $dst, $src" %}
9105
9106 ins_encode %{
9107 __ blsiq($dst$$Register, $src$$Register);
9108 %}
9109 ins_pipe(ialu_reg);
9110 %}
9111
9112 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9113 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9114 predicate(UseBMI1Instructions);
9115 effect(KILL cr);
9116
9117 ins_cost(125);
9118 format %{ "blsiq $dst, $src" %}
9119
9120 ins_encode %{
9121 __ blsiq($dst$$Register, $src$$Address);
9122 %}
9123 ins_pipe(ialu_reg_mem);
9124 %}
9125
9126 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9127 %{
9128 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9129 predicate(UseBMI1Instructions);
9130 effect(KILL cr);
9131
9132 ins_cost(125);
9133 format %{ "blsmskq $dst, $src" %}
9134
9135 ins_encode %{
9136 __ blsmskq($dst$$Register, $src$$Address);
9137 %}
9138 ins_pipe(ialu_reg_mem);
9139 %}
9140
9141 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9142 %{
9143 match(Set dst (XorL (AddL src minus_1) src));
9144 predicate(UseBMI1Instructions);
9145 effect(KILL cr);
9146
9147 format %{ "blsmskq $dst, $src" %}
9148
9149 ins_encode %{
9150 __ blsmskq($dst$$Register, $src$$Register);
9151 %}
9152
9153 ins_pipe(ialu_reg);
9154 %}
9155
9156 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9157 %{
9158 match(Set dst (AndL (AddL src minus_1) src) );
9159 predicate(UseBMI1Instructions);
9160 effect(KILL cr);
9161
9162 format %{ "blsrq $dst, $src" %}
9163
9164 ins_encode %{
9165 __ blsrq($dst$$Register, $src$$Register);
9166 %}
9167
9168 ins_pipe(ialu_reg);
9169 %}
9170
9171 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9172 %{
9173 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9174 predicate(UseBMI1Instructions);
9175 effect(KILL cr);
9176
9177 ins_cost(125);
9178 format %{ "blsrq $dst, $src" %}
9179
9180 ins_encode %{
9181 __ blsrq($dst$$Register, $src$$Address);
9182 %}
9183
9184 ins_pipe(ialu_reg);
9185 %}
9186
9187 // Or Instructions
9188 // Or Register with Register
9189 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9190 %{
9191 match(Set dst (OrL dst src));
9192 effect(KILL cr);
9193
9194 format %{ "orq $dst, $src\t# long" %}
9195 opcode(0x0B);
9196 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9197 ins_pipe(ialu_reg_reg);
9198 %}
9199
9200 // Use any_RegP to match R15 (TLS register) without spilling.
9201 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9202 match(Set dst (OrL dst (CastP2X src)));
9203 effect(KILL cr);
9204
9205 format %{ "orq $dst, $src\t# long" %}
9206 opcode(0x0B);
9207 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9208 ins_pipe(ialu_reg_reg);
9209 %}
9210
9211
9212 // Or Register with Immediate
9213 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9214 %{
9215 match(Set dst (OrL dst src));
9216 effect(KILL cr);
9217
9218 format %{ "orq $dst, $src\t# long" %}
9219 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9220 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9221 ins_pipe(ialu_reg);
9222 %}
9223
9224 // Or Register with Memory
9225 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9226 %{
9227 match(Set dst (OrL dst (LoadL src)));
9228 effect(KILL cr);
9229
9230 ins_cost(125);
9231 format %{ "orq $dst, $src\t# long" %}
9232 opcode(0x0B);
9233 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9234 ins_pipe(ialu_reg_mem);
9235 %}
9236
9237 // Or Memory with Register
9238 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9239 %{
9240 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9241 effect(KILL cr);
9242
9243 ins_cost(150);
9244 format %{ "orq $dst, $src\t# long" %}
9245 opcode(0x09); /* Opcode 09 /r */
9246 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9247 ins_pipe(ialu_mem_reg);
9248 %}
9249
9250 // Or Memory with Immediate
9251 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9252 %{
9253 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9254 effect(KILL cr);
9255
9256 ins_cost(125);
9257 format %{ "orq $dst, $src\t# long" %}
9258 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9259 ins_encode(REX_mem_wide(dst), OpcSE(src),
9260 RM_opc_mem(secondary, dst), Con8or32(src));
9261 ins_pipe(ialu_mem_imm);
9262 %}
9263
9264 // Xor Instructions
9265 // Xor Register with Register
9266 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9267 %{
9268 match(Set dst (XorL dst src));
9269 effect(KILL cr);
9270
9271 format %{ "xorq $dst, $src\t# long" %}
9272 opcode(0x33);
9273 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9274 ins_pipe(ialu_reg_reg);
9275 %}
9276
9277 // Xor Register with Immediate -1
9278 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9279 match(Set dst (XorL dst imm));
9280
9281 format %{ "notq $dst" %}
9282 ins_encode %{
9283 __ notq($dst$$Register);
9284 %}
9285 ins_pipe(ialu_reg);
9286 %}
9287
9288 // Xor Register with Immediate
9289 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9290 %{
9291 match(Set dst (XorL dst src));
9292 effect(KILL cr);
9293
9294 format %{ "xorq $dst, $src\t# long" %}
9295 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9296 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9297 ins_pipe(ialu_reg);
9298 %}
9299
9300 // Xor Register with Memory
9301 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9302 %{
9303 match(Set dst (XorL dst (LoadL src)));
9304 effect(KILL cr);
9305
9306 ins_cost(125);
9307 format %{ "xorq $dst, $src\t# long" %}
9308 opcode(0x33);
9309 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9310 ins_pipe(ialu_reg_mem);
9311 %}
9312
9313 // Xor Memory with Register
9314 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9315 %{
9316 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9317 effect(KILL cr);
9318
9319 ins_cost(150);
9320 format %{ "xorq $dst, $src\t# long" %}
9321 opcode(0x31); /* Opcode 31 /r */
9322 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9323 ins_pipe(ialu_mem_reg);
9324 %}
9325
9326 // Xor Memory with Immediate
9327 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9328 %{
9329 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9330 effect(KILL cr);
9331
9332 ins_cost(125);
9333 format %{ "xorq $dst, $src\t# long" %}
9334 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9335 ins_encode(REX_mem_wide(dst), OpcSE(src),
9336 RM_opc_mem(secondary, dst), Con8or32(src));
9337 ins_pipe(ialu_mem_imm);
9338 %}
9339
9340 // Convert Int to Boolean
9341 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9342 %{
9343 match(Set dst (Conv2B src));
9344 effect(KILL cr);
9345
9346 format %{ "testl $src, $src\t# ci2b\n\t"
9347 "setnz $dst\n\t"
9348 "movzbl $dst, $dst" %}
9349 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9350 setNZ_reg(dst),
9351 REX_reg_breg(dst, dst), // movzbl
9352 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9353 ins_pipe(pipe_slow); // XXX
9354 %}
9355
9356 // Convert Pointer to Boolean
9357 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9358 %{
9359 match(Set dst (Conv2B src));
9360 effect(KILL cr);
9361
9362 format %{ "testq $src, $src\t# cp2b\n\t"
9363 "setnz $dst\n\t"
9364 "movzbl $dst, $dst" %}
9365 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9366 setNZ_reg(dst),
9367 REX_reg_breg(dst, dst), // movzbl
9368 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9369 ins_pipe(pipe_slow); // XXX
9370 %}
9371
9372 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9373 %{
9374 match(Set dst (CmpLTMask p q));
9375 effect(KILL cr);
9376
9377 ins_cost(400);
9378 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9379 "setlt $dst\n\t"
9380 "movzbl $dst, $dst\n\t"
9381 "negl $dst" %}
9382 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9383 setLT_reg(dst),
9384 REX_reg_breg(dst, dst), // movzbl
9385 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9386 neg_reg(dst));
9387 ins_pipe(pipe_slow);
9388 %}
9389
9390 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9391 %{
9392 match(Set dst (CmpLTMask dst zero));
9393 effect(KILL cr);
9394
9395 ins_cost(100);
9396 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9397 ins_encode %{
9398 __ sarl($dst$$Register, 31);
9399 %}
9400 ins_pipe(ialu_reg);
9401 %}
9402
9403 /* Better to save a register than avoid a branch */
9404 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9405 %{
9406 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9407 effect(KILL cr);
9408 ins_cost(300);
9409 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9410 "jge done\n\t"
9411 "addl $p,$y\n"
9412 "done: " %}
9413 ins_encode %{
9414 Register Rp = $p$$Register;
9415 Register Rq = $q$$Register;
9416 Register Ry = $y$$Register;
9417 Label done;
9418 __ subl(Rp, Rq);
9419 __ jccb(Assembler::greaterEqual, done);
9420 __ addl(Rp, Ry);
9421 __ bind(done);
9422 %}
9423 ins_pipe(pipe_cmplt);
9424 %}
9425
9426 /* Better to save a register than avoid a branch */
9427 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9428 %{
9429 match(Set y (AndI (CmpLTMask p q) y));
9430 effect(KILL cr);
9431
9432 ins_cost(300);
9433
9434 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9435 "jlt done\n\t"
9436 "xorl $y, $y\n"
9437 "done: " %}
9438 ins_encode %{
9439 Register Rp = $p$$Register;
9440 Register Rq = $q$$Register;
9441 Register Ry = $y$$Register;
9442 Label done;
9443 __ cmpl(Rp, Rq);
9444 __ jccb(Assembler::less, done);
9445 __ xorl(Ry, Ry);
9446 __ bind(done);
9447 %}
9448 ins_pipe(pipe_cmplt);
9449 %}
9450
9451
9452 //---------- FP Instructions------------------------------------------------
9453
9454 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9455 %{
9456 match(Set cr (CmpF src1 src2));
9457
9458 ins_cost(145);
9459 format %{ "ucomiss $src1, $src2\n\t"
9460 "jnp,s exit\n\t"
9461 "pushfq\t# saw NaN, set CF\n\t"
9462 "andq [rsp], #0xffffff2b\n\t"
9463 "popfq\n"
9464 "exit:" %}
9465 ins_encode %{
9466 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9467 emit_cmpfp_fixup(_masm);
9468 %}
9469 ins_pipe(pipe_slow);
9470 %}
9471
9472 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9473 match(Set cr (CmpF src1 src2));
9474
9475 ins_cost(100);
9476 format %{ "ucomiss $src1, $src2" %}
9477 ins_encode %{
9478 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9479 %}
9480 ins_pipe(pipe_slow);
9481 %}
9482
9483 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9484 %{
9485 match(Set cr (CmpF src1 (LoadF src2)));
9486
9487 ins_cost(145);
9488 format %{ "ucomiss $src1, $src2\n\t"
9489 "jnp,s exit\n\t"
9490 "pushfq\t# saw NaN, set CF\n\t"
9491 "andq [rsp], #0xffffff2b\n\t"
9492 "popfq\n"
9493 "exit:" %}
9494 ins_encode %{
9495 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9496 emit_cmpfp_fixup(_masm);
9497 %}
9498 ins_pipe(pipe_slow);
9499 %}
9500
9501 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9502 match(Set cr (CmpF src1 (LoadF src2)));
9503
9504 ins_cost(100);
9505 format %{ "ucomiss $src1, $src2" %}
9506 ins_encode %{
9507 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9508 %}
9509 ins_pipe(pipe_slow);
9510 %}
9511
9512 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9513 match(Set cr (CmpF src con));
9514
9515 ins_cost(145);
9516 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9517 "jnp,s exit\n\t"
9518 "pushfq\t# saw NaN, set CF\n\t"
9519 "andq [rsp], #0xffffff2b\n\t"
9520 "popfq\n"
9521 "exit:" %}
9522 ins_encode %{
9523 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9524 emit_cmpfp_fixup(_masm);
9525 %}
9526 ins_pipe(pipe_slow);
9527 %}
9528
9529 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9530 match(Set cr (CmpF src con));
9531 ins_cost(100);
9532 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9533 ins_encode %{
9534 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9535 %}
9536 ins_pipe(pipe_slow);
9537 %}
9538
9539 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9540 %{
9541 match(Set cr (CmpD src1 src2));
9542
9543 ins_cost(145);
9544 format %{ "ucomisd $src1, $src2\n\t"
9545 "jnp,s exit\n\t"
9546 "pushfq\t# saw NaN, set CF\n\t"
9547 "andq [rsp], #0xffffff2b\n\t"
9548 "popfq\n"
9549 "exit:" %}
9550 ins_encode %{
9551 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9552 emit_cmpfp_fixup(_masm);
9553 %}
9554 ins_pipe(pipe_slow);
9555 %}
9556
9557 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9558 match(Set cr (CmpD src1 src2));
9559
9560 ins_cost(100);
9561 format %{ "ucomisd $src1, $src2 test" %}
9562 ins_encode %{
9563 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9564 %}
9565 ins_pipe(pipe_slow);
9566 %}
9567
9568 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9569 %{
9570 match(Set cr (CmpD src1 (LoadD src2)));
9571
9572 ins_cost(145);
9573 format %{ "ucomisd $src1, $src2\n\t"
9574 "jnp,s exit\n\t"
9575 "pushfq\t# saw NaN, set CF\n\t"
9576 "andq [rsp], #0xffffff2b\n\t"
9577 "popfq\n"
9578 "exit:" %}
9579 ins_encode %{
9580 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9581 emit_cmpfp_fixup(_masm);
9582 %}
9583 ins_pipe(pipe_slow);
9584 %}
9585
9586 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9587 match(Set cr (CmpD src1 (LoadD src2)));
9588
9589 ins_cost(100);
9590 format %{ "ucomisd $src1, $src2" %}
9591 ins_encode %{
9592 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9593 %}
9594 ins_pipe(pipe_slow);
9595 %}
9596
9597 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9598 match(Set cr (CmpD src con));
9599
9600 ins_cost(145);
9601 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9602 "jnp,s exit\n\t"
9603 "pushfq\t# saw NaN, set CF\n\t"
9604 "andq [rsp], #0xffffff2b\n\t"
9605 "popfq\n"
9606 "exit:" %}
9607 ins_encode %{
9608 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9609 emit_cmpfp_fixup(_masm);
9610 %}
9611 ins_pipe(pipe_slow);
9612 %}
9613
9614 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9615 match(Set cr (CmpD src con));
9616 ins_cost(100);
9617 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9618 ins_encode %{
9619 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9620 %}
9621 ins_pipe(pipe_slow);
9622 %}
9623
9624 // Compare into -1,0,1
9625 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9626 %{
9627 match(Set dst (CmpF3 src1 src2));
9628 effect(KILL cr);
9629
9630 ins_cost(275);
9631 format %{ "ucomiss $src1, $src2\n\t"
9632 "movl $dst, #-1\n\t"
9633 "jp,s done\n\t"
9634 "jb,s done\n\t"
9635 "setne $dst\n\t"
9636 "movzbl $dst, $dst\n"
9637 "done:" %}
9638 ins_encode %{
9639 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9640 emit_cmpfp3(_masm, $dst$$Register);
9641 %}
9642 ins_pipe(pipe_slow);
9643 %}
9644
9645 // Compare into -1,0,1
9646 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9647 %{
9648 match(Set dst (CmpF3 src1 (LoadF src2)));
9649 effect(KILL cr);
9650
9651 ins_cost(275);
9652 format %{ "ucomiss $src1, $src2\n\t"
9653 "movl $dst, #-1\n\t"
9654 "jp,s done\n\t"
9655 "jb,s done\n\t"
9656 "setne $dst\n\t"
9657 "movzbl $dst, $dst\n"
9658 "done:" %}
9659 ins_encode %{
9660 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9661 emit_cmpfp3(_masm, $dst$$Register);
9662 %}
9663 ins_pipe(pipe_slow);
9664 %}
9665
9666 // Compare into -1,0,1
9667 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9668 match(Set dst (CmpF3 src con));
9669 effect(KILL cr);
9670
9671 ins_cost(275);
9672 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9673 "movl $dst, #-1\n\t"
9674 "jp,s done\n\t"
9675 "jb,s done\n\t"
9676 "setne $dst\n\t"
9677 "movzbl $dst, $dst\n"
9678 "done:" %}
9679 ins_encode %{
9680 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9681 emit_cmpfp3(_masm, $dst$$Register);
9682 %}
9683 ins_pipe(pipe_slow);
9684 %}
9685
9686 // Compare into -1,0,1
9687 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9688 %{
9689 match(Set dst (CmpD3 src1 src2));
9690 effect(KILL cr);
9691
9692 ins_cost(275);
9693 format %{ "ucomisd $src1, $src2\n\t"
9694 "movl $dst, #-1\n\t"
9695 "jp,s done\n\t"
9696 "jb,s done\n\t"
9697 "setne $dst\n\t"
9698 "movzbl $dst, $dst\n"
9699 "done:" %}
9700 ins_encode %{
9701 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9702 emit_cmpfp3(_masm, $dst$$Register);
9703 %}
9704 ins_pipe(pipe_slow);
9705 %}
9706
9707 // Compare into -1,0,1
9708 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9709 %{
9710 match(Set dst (CmpD3 src1 (LoadD src2)));
9711 effect(KILL cr);
9712
9713 ins_cost(275);
9714 format %{ "ucomisd $src1, $src2\n\t"
9715 "movl $dst, #-1\n\t"
9716 "jp,s done\n\t"
9717 "jb,s done\n\t"
9718 "setne $dst\n\t"
9719 "movzbl $dst, $dst\n"
9720 "done:" %}
9721 ins_encode %{
9722 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9723 emit_cmpfp3(_masm, $dst$$Register);
9724 %}
9725 ins_pipe(pipe_slow);
9726 %}
9727
9728 // Compare into -1,0,1
9729 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9730 match(Set dst (CmpD3 src con));
9731 effect(KILL cr);
9732
9733 ins_cost(275);
9734 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9735 "movl $dst, #-1\n\t"
9736 "jp,s done\n\t"
9737 "jb,s done\n\t"
9738 "setne $dst\n\t"
9739 "movzbl $dst, $dst\n"
9740 "done:" %}
9741 ins_encode %{
9742 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9743 emit_cmpfp3(_masm, $dst$$Register);
9744 %}
9745 ins_pipe(pipe_slow);
9746 %}
9747
9748 // -----------Trig and Trancendental Instructions------------------------------
9749 instruct cosD_reg(regD dst) %{
9750 match(Set dst (CosD dst));
9751
9752 format %{ "dcos $dst\n\t" %}
9753 opcode(0xD9, 0xFF);
9754 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9755 ins_pipe( pipe_slow );
9756 %}
9757
9758 instruct sinD_reg(regD dst) %{
9759 match(Set dst (SinD dst));
9760
9761 format %{ "dsin $dst\n\t" %}
9762 opcode(0xD9, 0xFE);
9763 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) );
9764 ins_pipe( pipe_slow );
9765 %}
9766
9767 instruct tanD_reg(regD dst) %{
9768 match(Set dst (TanD dst));
9769
9770 format %{ "dtan $dst\n\t" %}
9771 ins_encode( Push_SrcXD(dst),
9772 Opcode(0xD9), Opcode(0xF2), //fptan
9773 Opcode(0xDD), Opcode(0xD8), //fstp st
9774 Push_ResultXD(dst) );
9775 ins_pipe( pipe_slow );
9776 %}
9777
9778 instruct log10D_reg(regD dst) %{
9779 // The source and result Double operands in XMM registers
9780 match(Set dst (Log10D dst));
9781 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9782 // fyl2x ; compute log_10(2) * log_2(x)
9783 format %{ "fldlg2\t\t\t#Log10\n\t"
9784 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9785 %}
9786 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9787 Push_SrcXD(dst),
9788 Opcode(0xD9), Opcode(0xF1), // fyl2x
9789 Push_ResultXD(dst));
9790
9791 ins_pipe( pipe_slow );
9792 %}
9793
9794 instruct logD_reg(regD dst) %{
9795 // The source and result Double operands in XMM registers
9796 match(Set dst (LogD dst));
9797 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number
9798 // fyl2x ; compute log_e(2) * log_2(x)
9799 format %{ "fldln2\t\t\t#Log_e\n\t"
9800 "fyl2x\t\t\t# Q=Log_e*Log_2(x)\n\t"
9801 %}
9802 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2
9803 Push_SrcXD(dst),
9804 Opcode(0xD9), Opcode(0xF1), // fyl2x
9805 Push_ResultXD(dst));
9806 ins_pipe( pipe_slow );
9807 %}
9808
9809 instruct powD_reg(regD dst, regD src0, regD src1, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9810 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power
9811 effect(KILL rax, KILL rdx, KILL rcx, KILL cr);
9812 format %{ "fast_pow $src0 $src1 -> $dst // KILL $rax, $rcx, $rdx" %}
9813 ins_encode %{
9814 __ subptr(rsp, 8);
9815 __ movdbl(Address(rsp, 0), $src1$$XMMRegister);
9816 __ fld_d(Address(rsp, 0));
9817 __ movdbl(Address(rsp, 0), $src0$$XMMRegister);
9818 __ fld_d(Address(rsp, 0));
9819 __ fast_pow();
9820 __ fstp_d(Address(rsp, 0));
9821 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9822 __ addptr(rsp, 8);
9823 %}
9824 ins_pipe( pipe_slow );
9825 %}
9826
9827 instruct expD_reg(regD dst, regD src, rax_RegI rax, rdx_RegI rdx, rcx_RegI rcx, rFlagsReg cr) %{
9828 match(Set dst (ExpD src));
9829 effect(KILL rax, KILL rcx, KILL rdx, KILL cr);
9830 format %{ "fast_exp $dst -> $src // KILL $rax, $rcx, $rdx" %}
9831 ins_encode %{
9832 __ subptr(rsp, 8);
9833 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9834 __ fld_d(Address(rsp, 0));
9835 __ fast_exp();
9836 __ fstp_d(Address(rsp, 0));
9837 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
9838 __ addptr(rsp, 8);
9839 %}
9840 ins_pipe( pipe_slow );
9841 %}
9842
9843 //----------Arithmetic Conversion Instructions---------------------------------
9844
9845 instruct roundFloat_nop(regF dst)
9846 %{
9847 match(Set dst (RoundFloat dst));
9848
9849 ins_cost(0);
9850 ins_encode();
9851 ins_pipe(empty);
9852 %}
9853
9854 instruct roundDouble_nop(regD dst)
9855 %{
9856 match(Set dst (RoundDouble dst));
9857
9858 ins_cost(0);
9859 ins_encode();
9860 ins_pipe(empty);
9861 %}
9862
9863 instruct convF2D_reg_reg(regD dst, regF src)
9864 %{
9865 match(Set dst (ConvF2D src));
9866
9867 format %{ "cvtss2sd $dst, $src" %}
9868 ins_encode %{
9869 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9870 %}
9871 ins_pipe(pipe_slow); // XXX
9872 %}
9873
9874 instruct convF2D_reg_mem(regD dst, memory src)
9875 %{
9876 match(Set dst (ConvF2D (LoadF src)));
9877
9878 format %{ "cvtss2sd $dst, $src" %}
9879 ins_encode %{
9880 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9881 %}
9882 ins_pipe(pipe_slow); // XXX
9883 %}
9884
9885 instruct convD2F_reg_reg(regF dst, regD src)
9886 %{
9887 match(Set dst (ConvD2F src));
9888
9889 format %{ "cvtsd2ss $dst, $src" %}
9890 ins_encode %{
9891 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9892 %}
9893 ins_pipe(pipe_slow); // XXX
9894 %}
9895
9896 instruct convD2F_reg_mem(regF dst, memory src)
9897 %{
9898 match(Set dst (ConvD2F (LoadD src)));
9899
9900 format %{ "cvtsd2ss $dst, $src" %}
9901 ins_encode %{
9902 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9903 %}
9904 ins_pipe(pipe_slow); // XXX
9905 %}
9906
9907 // XXX do mem variants
9908 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9909 %{
9910 match(Set dst (ConvF2I src));
9911 effect(KILL cr);
9912
9913 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
9914 "cmpl $dst, #0x80000000\n\t"
9915 "jne,s done\n\t"
9916 "subq rsp, #8\n\t"
9917 "movss [rsp], $src\n\t"
9918 "call f2i_fixup\n\t"
9919 "popq $dst\n"
9920 "done: "%}
9921 ins_encode %{
9922 Label done;
9923 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
9924 __ cmpl($dst$$Register, 0x80000000);
9925 __ jccb(Assembler::notEqual, done);
9926 __ subptr(rsp, 8);
9927 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9928 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9929 __ pop($dst$$Register);
9930 __ bind(done);
9931 %}
9932 ins_pipe(pipe_slow);
9933 %}
9934
9935 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
9936 %{
9937 match(Set dst (ConvF2L src));
9938 effect(KILL cr);
9939
9940 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
9941 "cmpq $dst, [0x8000000000000000]\n\t"
9942 "jne,s done\n\t"
9943 "subq rsp, #8\n\t"
9944 "movss [rsp], $src\n\t"
9945 "call f2l_fixup\n\t"
9946 "popq $dst\n"
9947 "done: "%}
9948 ins_encode %{
9949 Label done;
9950 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
9951 __ cmp64($dst$$Register,
9952 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9953 __ jccb(Assembler::notEqual, done);
9954 __ subptr(rsp, 8);
9955 __ movflt(Address(rsp, 0), $src$$XMMRegister);
9956 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9957 __ pop($dst$$Register);
9958 __ bind(done);
9959 %}
9960 ins_pipe(pipe_slow);
9961 %}
9962
9963 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
9964 %{
9965 match(Set dst (ConvD2I src));
9966 effect(KILL cr);
9967
9968 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
9969 "cmpl $dst, #0x80000000\n\t"
9970 "jne,s done\n\t"
9971 "subq rsp, #8\n\t"
9972 "movsd [rsp], $src\n\t"
9973 "call d2i_fixup\n\t"
9974 "popq $dst\n"
9975 "done: "%}
9976 ins_encode %{
9977 Label done;
9978 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
9979 __ cmpl($dst$$Register, 0x80000000);
9980 __ jccb(Assembler::notEqual, done);
9981 __ subptr(rsp, 8);
9982 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
9983 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9984 __ pop($dst$$Register);
9985 __ bind(done);
9986 %}
9987 ins_pipe(pipe_slow);
9988 %}
9989
9990 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
9991 %{
9992 match(Set dst (ConvD2L src));
9993 effect(KILL cr);
9994
9995 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
9996 "cmpq $dst, [0x8000000000000000]\n\t"
9997 "jne,s done\n\t"
9998 "subq rsp, #8\n\t"
9999 "movsd [rsp], $src\n\t"
10000 "call d2l_fixup\n\t"
10001 "popq $dst\n"
10002 "done: "%}
10003 ins_encode %{
10004 Label done;
10005 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10006 __ cmp64($dst$$Register,
10007 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10008 __ jccb(Assembler::notEqual, done);
10009 __ subptr(rsp, 8);
10010 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10011 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10012 __ pop($dst$$Register);
10013 __ bind(done);
10014 %}
10015 ins_pipe(pipe_slow);
10016 %}
10017
10018 instruct convI2F_reg_reg(regF dst, rRegI src)
10019 %{
10020 predicate(!UseXmmI2F);
10021 match(Set dst (ConvI2F src));
10022
10023 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10024 ins_encode %{
10025 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10026 %}
10027 ins_pipe(pipe_slow); // XXX
10028 %}
10029
10030 instruct convI2F_reg_mem(regF dst, memory src)
10031 %{
10032 match(Set dst (ConvI2F (LoadI src)));
10033
10034 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10035 ins_encode %{
10036 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10037 %}
10038 ins_pipe(pipe_slow); // XXX
10039 %}
10040
10041 instruct convI2D_reg_reg(regD dst, rRegI src)
10042 %{
10043 predicate(!UseXmmI2D);
10044 match(Set dst (ConvI2D src));
10045
10046 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10047 ins_encode %{
10048 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10049 %}
10050 ins_pipe(pipe_slow); // XXX
10051 %}
10052
10053 instruct convI2D_reg_mem(regD dst, memory src)
10054 %{
10055 match(Set dst (ConvI2D (LoadI src)));
10056
10057 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10058 ins_encode %{
10059 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10060 %}
10061 ins_pipe(pipe_slow); // XXX
10062 %}
10063
10064 instruct convXI2F_reg(regF dst, rRegI src)
10065 %{
10066 predicate(UseXmmI2F);
10067 match(Set dst (ConvI2F src));
10068
10069 format %{ "movdl $dst, $src\n\t"
10070 "cvtdq2psl $dst, $dst\t# i2f" %}
10071 ins_encode %{
10072 __ movdl($dst$$XMMRegister, $src$$Register);
10073 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10074 %}
10075 ins_pipe(pipe_slow); // XXX
10076 %}
10077
10078 instruct convXI2D_reg(regD dst, rRegI src)
10079 %{
10080 predicate(UseXmmI2D);
10081 match(Set dst (ConvI2D src));
10082
10083 format %{ "movdl $dst, $src\n\t"
10084 "cvtdq2pdl $dst, $dst\t# i2d" %}
10085 ins_encode %{
10086 __ movdl($dst$$XMMRegister, $src$$Register);
10087 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10088 %}
10089 ins_pipe(pipe_slow); // XXX
10090 %}
10091
10092 instruct convL2F_reg_reg(regF dst, rRegL src)
10093 %{
10094 match(Set dst (ConvL2F src));
10095
10096 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10097 ins_encode %{
10098 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10099 %}
10100 ins_pipe(pipe_slow); // XXX
10101 %}
10102
10103 instruct convL2F_reg_mem(regF dst, memory src)
10104 %{
10105 match(Set dst (ConvL2F (LoadL src)));
10106
10107 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10108 ins_encode %{
10109 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10110 %}
10111 ins_pipe(pipe_slow); // XXX
10112 %}
10113
10114 instruct convL2D_reg_reg(regD dst, rRegL src)
10115 %{
10116 match(Set dst (ConvL2D src));
10117
10118 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10119 ins_encode %{
10120 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10121 %}
10122 ins_pipe(pipe_slow); // XXX
10123 %}
10124
10125 instruct convL2D_reg_mem(regD dst, memory src)
10126 %{
10127 match(Set dst (ConvL2D (LoadL src)));
10128
10129 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10130 ins_encode %{
10131 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10132 %}
10133 ins_pipe(pipe_slow); // XXX
10134 %}
10135
10136 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10137 %{
10138 match(Set dst (ConvI2L src));
10139
10140 ins_cost(125);
10141 format %{ "movslq $dst, $src\t# i2l" %}
10142 ins_encode %{
10143 __ movslq($dst$$Register, $src$$Register);
10144 %}
10145 ins_pipe(ialu_reg_reg);
10146 %}
10147
10148 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10149 // %{
10150 // match(Set dst (ConvI2L src));
10151 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10152 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10153 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10154 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10155 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10156 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10157
10158 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10159 // ins_encode(enc_copy(dst, src));
10160 // // opcode(0x63); // needs REX.W
10161 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10162 // ins_pipe(ialu_reg_reg);
10163 // %}
10164
10165 // Zero-extend convert int to long
10166 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10167 %{
10168 match(Set dst (AndL (ConvI2L src) mask));
10169
10170 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10171 ins_encode %{
10172 if ($dst$$reg != $src$$reg) {
10173 __ movl($dst$$Register, $src$$Register);
10174 }
10175 %}
10176 ins_pipe(ialu_reg_reg);
10177 %}
10178
10179 // Zero-extend convert int to long
10180 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10181 %{
10182 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10183
10184 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10185 ins_encode %{
10186 __ movl($dst$$Register, $src$$Address);
10187 %}
10188 ins_pipe(ialu_reg_mem);
10189 %}
10190
10191 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10192 %{
10193 match(Set dst (AndL src mask));
10194
10195 format %{ "movl $dst, $src\t# zero-extend long" %}
10196 ins_encode %{
10197 __ movl($dst$$Register, $src$$Register);
10198 %}
10199 ins_pipe(ialu_reg_reg);
10200 %}
10201
10202 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10203 %{
10204 match(Set dst (ConvL2I src));
10205
10206 format %{ "movl $dst, $src\t# l2i" %}
10207 ins_encode %{
10208 __ movl($dst$$Register, $src$$Register);
10209 %}
10210 ins_pipe(ialu_reg_reg);
10211 %}
10212
10213
10214 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10215 match(Set dst (MoveF2I src));
10216 effect(DEF dst, USE src);
10217
10218 ins_cost(125);
10219 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10220 ins_encode %{
10221 __ movl($dst$$Register, Address(rsp, $src$$disp));
10222 %}
10223 ins_pipe(ialu_reg_mem);
10224 %}
10225
10226 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10227 match(Set dst (MoveI2F src));
10228 effect(DEF dst, USE src);
10229
10230 ins_cost(125);
10231 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10232 ins_encode %{
10233 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10234 %}
10235 ins_pipe(pipe_slow);
10236 %}
10237
10238 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10239 match(Set dst (MoveD2L src));
10240 effect(DEF dst, USE src);
10241
10242 ins_cost(125);
10243 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10244 ins_encode %{
10245 __ movq($dst$$Register, Address(rsp, $src$$disp));
10246 %}
10247 ins_pipe(ialu_reg_mem);
10248 %}
10249
10250 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10251 predicate(!UseXmmLoadAndClearUpper);
10252 match(Set dst (MoveL2D src));
10253 effect(DEF dst, USE src);
10254
10255 ins_cost(125);
10256 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10257 ins_encode %{
10258 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10259 %}
10260 ins_pipe(pipe_slow);
10261 %}
10262
10263 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10264 predicate(UseXmmLoadAndClearUpper);
10265 match(Set dst (MoveL2D src));
10266 effect(DEF dst, USE src);
10267
10268 ins_cost(125);
10269 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10270 ins_encode %{
10271 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10272 %}
10273 ins_pipe(pipe_slow);
10274 %}
10275
10276
10277 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10278 match(Set dst (MoveF2I src));
10279 effect(DEF dst, USE src);
10280
10281 ins_cost(95); // XXX
10282 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10283 ins_encode %{
10284 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10285 %}
10286 ins_pipe(pipe_slow);
10287 %}
10288
10289 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10290 match(Set dst (MoveI2F src));
10291 effect(DEF dst, USE src);
10292
10293 ins_cost(100);
10294 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10295 ins_encode %{
10296 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10297 %}
10298 ins_pipe( ialu_mem_reg );
10299 %}
10300
10301 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10302 match(Set dst (MoveD2L src));
10303 effect(DEF dst, USE src);
10304
10305 ins_cost(95); // XXX
10306 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10307 ins_encode %{
10308 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10309 %}
10310 ins_pipe(pipe_slow);
10311 %}
10312
10313 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10314 match(Set dst (MoveL2D src));
10315 effect(DEF dst, USE src);
10316
10317 ins_cost(100);
10318 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10319 ins_encode %{
10320 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10321 %}
10322 ins_pipe(ialu_mem_reg);
10323 %}
10324
10325 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10326 match(Set dst (MoveF2I src));
10327 effect(DEF dst, USE src);
10328 ins_cost(85);
10329 format %{ "movd $dst,$src\t# MoveF2I" %}
10330 ins_encode %{
10331 __ movdl($dst$$Register, $src$$XMMRegister);
10332 %}
10333 ins_pipe( pipe_slow );
10334 %}
10335
10336 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10337 match(Set dst (MoveD2L src));
10338 effect(DEF dst, USE src);
10339 ins_cost(85);
10340 format %{ "movd $dst,$src\t# MoveD2L" %}
10341 ins_encode %{
10342 __ movdq($dst$$Register, $src$$XMMRegister);
10343 %}
10344 ins_pipe( pipe_slow );
10345 %}
10346
10347 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10348 match(Set dst (MoveI2F src));
10349 effect(DEF dst, USE src);
10350 ins_cost(100);
10351 format %{ "movd $dst,$src\t# MoveI2F" %}
10352 ins_encode %{
10353 __ movdl($dst$$XMMRegister, $src$$Register);
10354 %}
10355 ins_pipe( pipe_slow );
10356 %}
10357
10358 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10359 match(Set dst (MoveL2D src));
10360 effect(DEF dst, USE src);
10361 ins_cost(100);
10362 format %{ "movd $dst,$src\t# MoveL2D" %}
10363 ins_encode %{
10364 __ movdq($dst$$XMMRegister, $src$$Register);
10365 %}
10366 ins_pipe( pipe_slow );
10367 %}
10368
10369
10370 // =======================================================================
10371 // fast clearing of an array
10372 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10373 rFlagsReg cr)
10374 %{
10375 predicate(!UseFastStosb);
10376 match(Set dummy (ClearArray cnt base));
10377 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10378
10379 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10380 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10381 ins_encode %{
10382 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10383 %}
10384 ins_pipe(pipe_slow);
10385 %}
10386
10387 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10388 rFlagsReg cr)
10389 %{
10390 predicate(UseFastStosb);
10391 match(Set dummy (ClearArray cnt base));
10392 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10393 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10394 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10395 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10396 ins_encode %{
10397 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10398 %}
10399 ins_pipe( pipe_slow );
10400 %}
10401
10402 instruct string_compare(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10403 rax_RegI result, regD tmp1, rFlagsReg cr)
10404 %{
10405 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10406 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10407
10408 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10409 ins_encode %{
10410 __ string_compare($str1$$Register, $str2$$Register,
10411 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10412 $tmp1$$XMMRegister);
10413 %}
10414 ins_pipe( pipe_slow );
10415 %}
10416
10417 // fast search of substring with known size.
10418 instruct string_indexof_con(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10419 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10420 %{
10421 predicate(UseSSE42Intrinsics);
10422 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10423 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10424
10425 format %{ "String IndexOf $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10426 ins_encode %{
10427 int icnt2 = (int)$int_cnt2$$constant;
10428 if (icnt2 >= 8) {
10429 // IndexOf for constant substrings with size >= 8 elements
10430 // which don't need to be loaded through stack.
10431 __ string_indexofC8($str1$$Register, $str2$$Register,
10432 $cnt1$$Register, $cnt2$$Register,
10433 icnt2, $result$$Register,
10434 $vec$$XMMRegister, $tmp$$Register);
10435 } else {
10436 // Small strings are loaded through stack if they cross page boundary.
10437 __ string_indexof($str1$$Register, $str2$$Register,
10438 $cnt1$$Register, $cnt2$$Register,
10439 icnt2, $result$$Register,
10440 $vec$$XMMRegister, $tmp$$Register);
10441 }
10442 %}
10443 ins_pipe( pipe_slow );
10444 %}
10445
10446 instruct string_indexof(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10447 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10448 %{
10449 predicate(UseSSE42Intrinsics);
10450 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10451 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10452
10453 format %{ "String IndexOf $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10454 ins_encode %{
10455 __ string_indexof($str1$$Register, $str2$$Register,
10456 $cnt1$$Register, $cnt2$$Register,
10457 (-1), $result$$Register,
10458 $vec$$XMMRegister, $tmp$$Register);
10459 %}
10460 ins_pipe( pipe_slow );
10461 %}
10462
10463 // fast string equals
10464 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10465 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10466 %{
10467 match(Set result (StrEquals (Binary str1 str2) cnt));
10468 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10469
10470 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10471 ins_encode %{
10472 __ char_arrays_equals(false, $str1$$Register, $str2$$Register,
10473 $cnt$$Register, $result$$Register, $tmp3$$Register,
10474 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10475 %}
10476 ins_pipe( pipe_slow );
10477 %}
10478
10479 // fast array equals
10480 instruct array_equals(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10481 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10482 %{
10483 match(Set result (AryEq ary1 ary2));
10484 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10485 //ins_cost(300);
10486
10487 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10488 ins_encode %{
10489 __ char_arrays_equals(true, $ary1$$Register, $ary2$$Register,
10490 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10491 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10492 %}
10493 ins_pipe( pipe_slow );
10494 %}
10495
10496 // encode char[] to byte[] in ISO_8859_1
10497 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10498 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10499 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10500 match(Set result (EncodeISOArray src (Binary dst len)));
10501 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10502
10503 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10504 ins_encode %{
10505 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10506 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10507 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10508 %}
10509 ins_pipe( pipe_slow );
10510 %}
10511
10512 //----------Overflow Math Instructions-----------------------------------------
10513
10514 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10515 %{
10516 match(Set cr (OverflowAddI op1 op2));
10517 effect(DEF cr, USE_KILL op1, USE op2);
10518
10519 format %{ "addl $op1, $op2\t# overflow check int" %}
10520
10521 ins_encode %{
10522 __ addl($op1$$Register, $op2$$Register);
10523 %}
10524 ins_pipe(ialu_reg_reg);
10525 %}
10526
10527 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10528 %{
10529 match(Set cr (OverflowAddI op1 op2));
10530 effect(DEF cr, USE_KILL op1, USE op2);
10531
10532 format %{ "addl $op1, $op2\t# overflow check int" %}
10533
10534 ins_encode %{
10535 __ addl($op1$$Register, $op2$$constant);
10536 %}
10537 ins_pipe(ialu_reg_reg);
10538 %}
10539
10540 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10541 %{
10542 match(Set cr (OverflowAddL op1 op2));
10543 effect(DEF cr, USE_KILL op1, USE op2);
10544
10545 format %{ "addq $op1, $op2\t# overflow check long" %}
10546 ins_encode %{
10547 __ addq($op1$$Register, $op2$$Register);
10548 %}
10549 ins_pipe(ialu_reg_reg);
10550 %}
10551
10552 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10553 %{
10554 match(Set cr (OverflowAddL op1 op2));
10555 effect(DEF cr, USE_KILL op1, USE op2);
10556
10557 format %{ "addq $op1, $op2\t# overflow check long" %}
10558 ins_encode %{
10559 __ addq($op1$$Register, $op2$$constant);
10560 %}
10561 ins_pipe(ialu_reg_reg);
10562 %}
10563
10564 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10565 %{
10566 match(Set cr (OverflowSubI op1 op2));
10567
10568 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10569 ins_encode %{
10570 __ cmpl($op1$$Register, $op2$$Register);
10571 %}
10572 ins_pipe(ialu_reg_reg);
10573 %}
10574
10575 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10576 %{
10577 match(Set cr (OverflowSubI op1 op2));
10578
10579 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10580 ins_encode %{
10581 __ cmpl($op1$$Register, $op2$$constant);
10582 %}
10583 ins_pipe(ialu_reg_reg);
10584 %}
10585
10586 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10587 %{
10588 match(Set cr (OverflowSubL op1 op2));
10589
10590 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10591 ins_encode %{
10592 __ cmpq($op1$$Register, $op2$$Register);
10593 %}
10594 ins_pipe(ialu_reg_reg);
10595 %}
10596
10597 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10598 %{
10599 match(Set cr (OverflowSubL op1 op2));
10600
10601 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10602 ins_encode %{
10603 __ cmpq($op1$$Register, $op2$$constant);
10604 %}
10605 ins_pipe(ialu_reg_reg);
10606 %}
10607
10608 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10609 %{
10610 match(Set cr (OverflowSubI zero op2));
10611 effect(DEF cr, USE_KILL op2);
10612
10613 format %{ "negl $op2\t# overflow check int" %}
10614 ins_encode %{
10615 __ negl($op2$$Register);
10616 %}
10617 ins_pipe(ialu_reg_reg);
10618 %}
10619
10620 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10621 %{
10622 match(Set cr (OverflowSubL zero op2));
10623 effect(DEF cr, USE_KILL op2);
10624
10625 format %{ "negq $op2\t# overflow check long" %}
10626 ins_encode %{
10627 __ negq($op2$$Register);
10628 %}
10629 ins_pipe(ialu_reg_reg);
10630 %}
10631
10632 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10633 %{
10634 match(Set cr (OverflowMulI op1 op2));
10635 effect(DEF cr, USE_KILL op1, USE op2);
10636
10637 format %{ "imull $op1, $op2\t# overflow check int" %}
10638 ins_encode %{
10639 __ imull($op1$$Register, $op2$$Register);
10640 %}
10641 ins_pipe(ialu_reg_reg_alu0);
10642 %}
10643
10644 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10645 %{
10646 match(Set cr (OverflowMulI op1 op2));
10647 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10648
10649 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10650 ins_encode %{
10651 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10652 %}
10653 ins_pipe(ialu_reg_reg_alu0);
10654 %}
10655
10656 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10657 %{
10658 match(Set cr (OverflowMulL op1 op2));
10659 effect(DEF cr, USE_KILL op1, USE op2);
10660
10661 format %{ "imulq $op1, $op2\t# overflow check long" %}
10662 ins_encode %{
10663 __ imulq($op1$$Register, $op2$$Register);
10664 %}
10665 ins_pipe(ialu_reg_reg_alu0);
10666 %}
10667
10668 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10669 %{
10670 match(Set cr (OverflowMulL op1 op2));
10671 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10672
10673 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10674 ins_encode %{
10675 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10676 %}
10677 ins_pipe(ialu_reg_reg_alu0);
10678 %}
10679
10680
10681 //----------Control Flow Instructions------------------------------------------
10682 // Signed compare Instructions
10683
10684 // XXX more variants!!
10685 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10686 %{
10687 match(Set cr (CmpI op1 op2));
10688 effect(DEF cr, USE op1, USE op2);
10689
10690 format %{ "cmpl $op1, $op2" %}
10691 opcode(0x3B); /* Opcode 3B /r */
10692 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10693 ins_pipe(ialu_cr_reg_reg);
10694 %}
10695
10696 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10697 %{
10698 match(Set cr (CmpI op1 op2));
10699
10700 format %{ "cmpl $op1, $op2" %}
10701 opcode(0x81, 0x07); /* Opcode 81 /7 */
10702 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10703 ins_pipe(ialu_cr_reg_imm);
10704 %}
10705
10706 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
10707 %{
10708 match(Set cr (CmpI op1 (LoadI op2)));
10709
10710 ins_cost(500); // XXX
10711 format %{ "cmpl $op1, $op2" %}
10712 opcode(0x3B); /* Opcode 3B /r */
10713 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10714 ins_pipe(ialu_cr_reg_mem);
10715 %}
10716
10717 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
10718 %{
10719 match(Set cr (CmpI src zero));
10720
10721 format %{ "testl $src, $src" %}
10722 opcode(0x85);
10723 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10724 ins_pipe(ialu_cr_reg_imm);
10725 %}
10726
10727 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
10728 %{
10729 match(Set cr (CmpI (AndI src con) zero));
10730
10731 format %{ "testl $src, $con" %}
10732 opcode(0xF7, 0x00);
10733 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
10734 ins_pipe(ialu_cr_reg_imm);
10735 %}
10736
10737 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
10738 %{
10739 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
10740
10741 format %{ "testl $src, $mem" %}
10742 opcode(0x85);
10743 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
10744 ins_pipe(ialu_cr_reg_mem);
10745 %}
10746
10747 // Unsigned compare Instructions; really, same as signed except they
10748 // produce an rFlagsRegU instead of rFlagsReg.
10749 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
10750 %{
10751 match(Set cr (CmpU op1 op2));
10752
10753 format %{ "cmpl $op1, $op2\t# unsigned" %}
10754 opcode(0x3B); /* Opcode 3B /r */
10755 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10756 ins_pipe(ialu_cr_reg_reg);
10757 %}
10758
10759 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
10760 %{
10761 match(Set cr (CmpU op1 op2));
10762
10763 format %{ "cmpl $op1, $op2\t# unsigned" %}
10764 opcode(0x81,0x07); /* Opcode 81 /7 */
10765 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
10766 ins_pipe(ialu_cr_reg_imm);
10767 %}
10768
10769 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
10770 %{
10771 match(Set cr (CmpU op1 (LoadI op2)));
10772
10773 ins_cost(500); // XXX
10774 format %{ "cmpl $op1, $op2\t# unsigned" %}
10775 opcode(0x3B); /* Opcode 3B /r */
10776 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
10777 ins_pipe(ialu_cr_reg_mem);
10778 %}
10779
10780 // // // Cisc-spilled version of cmpU_rReg
10781 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
10782 // //%{
10783 // // match(Set cr (CmpU (LoadI op1) op2));
10784 // //
10785 // // format %{ "CMPu $op1,$op2" %}
10786 // // ins_cost(500);
10787 // // opcode(0x39); /* Opcode 39 /r */
10788 // // ins_encode( OpcP, reg_mem( op1, op2) );
10789 // //%}
10790
10791 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
10792 %{
10793 match(Set cr (CmpU src zero));
10794
10795 format %{ "testl $src, $src\t# unsigned" %}
10796 opcode(0x85);
10797 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
10798 ins_pipe(ialu_cr_reg_imm);
10799 %}
10800
10801 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
10802 %{
10803 match(Set cr (CmpP op1 op2));
10804
10805 format %{ "cmpq $op1, $op2\t# ptr" %}
10806 opcode(0x3B); /* Opcode 3B /r */
10807 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10808 ins_pipe(ialu_cr_reg_reg);
10809 %}
10810
10811 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
10812 %{
10813 match(Set cr (CmpP op1 (LoadP op2)));
10814
10815 ins_cost(500); // XXX
10816 format %{ "cmpq $op1, $op2\t# ptr" %}
10817 opcode(0x3B); /* Opcode 3B /r */
10818 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10819 ins_pipe(ialu_cr_reg_mem);
10820 %}
10821
10822 // // // Cisc-spilled version of cmpP_rReg
10823 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
10824 // //%{
10825 // // match(Set cr (CmpP (LoadP op1) op2));
10826 // //
10827 // // format %{ "CMPu $op1,$op2" %}
10828 // // ins_cost(500);
10829 // // opcode(0x39); /* Opcode 39 /r */
10830 // // ins_encode( OpcP, reg_mem( op1, op2) );
10831 // //%}
10832
10833 // XXX this is generalized by compP_rReg_mem???
10834 // Compare raw pointer (used in out-of-heap check).
10835 // Only works because non-oop pointers must be raw pointers
10836 // and raw pointers have no anti-dependencies.
10837 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
10838 %{
10839 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
10840 match(Set cr (CmpP op1 (LoadP op2)));
10841
10842 format %{ "cmpq $op1, $op2\t# raw ptr" %}
10843 opcode(0x3B); /* Opcode 3B /r */
10844 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
10845 ins_pipe(ialu_cr_reg_mem);
10846 %}
10847
10848 // This will generate a signed flags result. This should be OK since
10849 // any compare to a zero should be eq/neq.
10850 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
10851 %{
10852 match(Set cr (CmpP src zero));
10853
10854 format %{ "testq $src, $src\t# ptr" %}
10855 opcode(0x85);
10856 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
10857 ins_pipe(ialu_cr_reg_imm);
10858 %}
10859
10860 // This will generate a signed flags result. This should be OK since
10861 // any compare to a zero should be eq/neq.
10862 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
10863 %{
10864 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
10865 match(Set cr (CmpP (LoadP op) zero));
10866
10867 ins_cost(500); // XXX
10868 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
10869 opcode(0xF7); /* Opcode F7 /0 */
10870 ins_encode(REX_mem_wide(op),
10871 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
10872 ins_pipe(ialu_cr_reg_imm);
10873 %}
10874
10875 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
10876 %{
10877 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
10878 match(Set cr (CmpP (LoadP mem) zero));
10879
10880 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
10881 ins_encode %{
10882 __ cmpq(r12, $mem$$Address);
10883 %}
10884 ins_pipe(ialu_cr_reg_mem);
10885 %}
10886
10887 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
10888 %{
10889 match(Set cr (CmpN op1 op2));
10890
10891 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10892 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
10893 ins_pipe(ialu_cr_reg_reg);
10894 %}
10895
10896 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
10897 %{
10898 match(Set cr (CmpN src (LoadN mem)));
10899
10900 format %{ "cmpl $src, $mem\t# compressed ptr" %}
10901 ins_encode %{
10902 __ cmpl($src$$Register, $mem$$Address);
10903 %}
10904 ins_pipe(ialu_cr_reg_mem);
10905 %}
10906
10907 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
10908 match(Set cr (CmpN op1 op2));
10909
10910 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
10911 ins_encode %{
10912 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
10913 %}
10914 ins_pipe(ialu_cr_reg_imm);
10915 %}
10916
10917 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
10918 %{
10919 match(Set cr (CmpN src (LoadN mem)));
10920
10921 format %{ "cmpl $mem, $src\t# compressed ptr" %}
10922 ins_encode %{
10923 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
10924 %}
10925 ins_pipe(ialu_cr_reg_mem);
10926 %}
10927
10928 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
10929 match(Set cr (CmpN op1 op2));
10930
10931 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
10932 ins_encode %{
10933 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
10934 %}
10935 ins_pipe(ialu_cr_reg_imm);
10936 %}
10937
10938 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
10939 %{
10940 match(Set cr (CmpN src (LoadNKlass mem)));
10941
10942 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
10943 ins_encode %{
10944 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
10945 %}
10946 ins_pipe(ialu_cr_reg_mem);
10947 %}
10948
10949 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
10950 match(Set cr (CmpN src zero));
10951
10952 format %{ "testl $src, $src\t# compressed ptr" %}
10953 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
10954 ins_pipe(ialu_cr_reg_imm);
10955 %}
10956
10957 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
10958 %{
10959 predicate(Universe::narrow_oop_base() != NULL);
10960 match(Set cr (CmpN (LoadN mem) zero));
10961
10962 ins_cost(500); // XXX
10963 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
10964 ins_encode %{
10965 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
10966 %}
10967 ins_pipe(ialu_cr_reg_mem);
10968 %}
10969
10970 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
10971 %{
10972 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
10973 match(Set cr (CmpN (LoadN mem) zero));
10974
10975 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
10976 ins_encode %{
10977 __ cmpl(r12, $mem$$Address);
10978 %}
10979 ins_pipe(ialu_cr_reg_mem);
10980 %}
10981
10982 // Yanked all unsigned pointer compare operations.
10983 // Pointer compares are done with CmpP which is already unsigned.
10984
10985 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10986 %{
10987 match(Set cr (CmpL op1 op2));
10988
10989 format %{ "cmpq $op1, $op2" %}
10990 opcode(0x3B); /* Opcode 3B /r */
10991 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
10992 ins_pipe(ialu_cr_reg_reg);
10993 %}
10994
10995 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10996 %{
10997 match(Set cr (CmpL op1 op2));
10998
10999 format %{ "cmpq $op1, $op2" %}
11000 opcode(0x81, 0x07); /* Opcode 81 /7 */
11001 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11002 ins_pipe(ialu_cr_reg_imm);
11003 %}
11004
11005 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11006 %{
11007 match(Set cr (CmpL op1 (LoadL op2)));
11008
11009 format %{ "cmpq $op1, $op2" %}
11010 opcode(0x3B); /* Opcode 3B /r */
11011 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11012 ins_pipe(ialu_cr_reg_mem);
11013 %}
11014
11015 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11016 %{
11017 match(Set cr (CmpL src zero));
11018
11019 format %{ "testq $src, $src" %}
11020 opcode(0x85);
11021 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11022 ins_pipe(ialu_cr_reg_imm);
11023 %}
11024
11025 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11026 %{
11027 match(Set cr (CmpL (AndL src con) zero));
11028
11029 format %{ "testq $src, $con\t# long" %}
11030 opcode(0xF7, 0x00);
11031 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11032 ins_pipe(ialu_cr_reg_imm);
11033 %}
11034
11035 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11036 %{
11037 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11038
11039 format %{ "testq $src, $mem" %}
11040 opcode(0x85);
11041 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11042 ins_pipe(ialu_cr_reg_mem);
11043 %}
11044
11045 // Manifest a CmpL result in an integer register. Very painful.
11046 // This is the test to avoid.
11047 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11048 %{
11049 match(Set dst (CmpL3 src1 src2));
11050 effect(KILL flags);
11051
11052 ins_cost(275); // XXX
11053 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11054 "movl $dst, -1\n\t"
11055 "jl,s done\n\t"
11056 "setne $dst\n\t"
11057 "movzbl $dst, $dst\n\t"
11058 "done:" %}
11059 ins_encode(cmpl3_flag(src1, src2, dst));
11060 ins_pipe(pipe_slow);
11061 %}
11062
11063 //----------Max and Min--------------------------------------------------------
11064 // Min Instructions
11065
11066 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11067 %{
11068 effect(USE_DEF dst, USE src, USE cr);
11069
11070 format %{ "cmovlgt $dst, $src\t# min" %}
11071 opcode(0x0F, 0x4F);
11072 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11073 ins_pipe(pipe_cmov_reg);
11074 %}
11075
11076
11077 instruct minI_rReg(rRegI dst, rRegI src)
11078 %{
11079 match(Set dst (MinI dst src));
11080
11081 ins_cost(200);
11082 expand %{
11083 rFlagsReg cr;
11084 compI_rReg(cr, dst, src);
11085 cmovI_reg_g(dst, src, cr);
11086 %}
11087 %}
11088
11089 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11090 %{
11091 effect(USE_DEF dst, USE src, USE cr);
11092
11093 format %{ "cmovllt $dst, $src\t# max" %}
11094 opcode(0x0F, 0x4C);
11095 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11096 ins_pipe(pipe_cmov_reg);
11097 %}
11098
11099
11100 instruct maxI_rReg(rRegI dst, rRegI src)
11101 %{
11102 match(Set dst (MaxI dst src));
11103
11104 ins_cost(200);
11105 expand %{
11106 rFlagsReg cr;
11107 compI_rReg(cr, dst, src);
11108 cmovI_reg_l(dst, src, cr);
11109 %}
11110 %}
11111
11112 // ============================================================================
11113 // Branch Instructions
11114
11115 // Jump Direct - Label defines a relative address from JMP+1
11116 instruct jmpDir(label labl)
11117 %{
11118 match(Goto);
11119 effect(USE labl);
11120
11121 ins_cost(300);
11122 format %{ "jmp $labl" %}
11123 size(5);
11124 ins_encode %{
11125 Label* L = $labl$$label;
11126 __ jmp(*L, false); // Always long jump
11127 %}
11128 ins_pipe(pipe_jmp);
11129 %}
11130
11131 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11132 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11133 %{
11134 match(If cop cr);
11135 effect(USE labl);
11136
11137 ins_cost(300);
11138 format %{ "j$cop $labl" %}
11139 size(6);
11140 ins_encode %{
11141 Label* L = $labl$$label;
11142 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11143 %}
11144 ins_pipe(pipe_jcc);
11145 %}
11146
11147 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11148 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11149 %{
11150 match(CountedLoopEnd cop cr);
11151 effect(USE labl);
11152
11153 ins_cost(300);
11154 format %{ "j$cop $labl\t# loop end" %}
11155 size(6);
11156 ins_encode %{
11157 Label* L = $labl$$label;
11158 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11159 %}
11160 ins_pipe(pipe_jcc);
11161 %}
11162
11163 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11164 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11165 match(CountedLoopEnd cop cmp);
11166 effect(USE labl);
11167
11168 ins_cost(300);
11169 format %{ "j$cop,u $labl\t# loop end" %}
11170 size(6);
11171 ins_encode %{
11172 Label* L = $labl$$label;
11173 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11174 %}
11175 ins_pipe(pipe_jcc);
11176 %}
11177
11178 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11179 match(CountedLoopEnd cop cmp);
11180 effect(USE labl);
11181
11182 ins_cost(200);
11183 format %{ "j$cop,u $labl\t# loop end" %}
11184 size(6);
11185 ins_encode %{
11186 Label* L = $labl$$label;
11187 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11188 %}
11189 ins_pipe(pipe_jcc);
11190 %}
11191
11192 // Jump Direct Conditional - using unsigned comparison
11193 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11194 match(If cop cmp);
11195 effect(USE labl);
11196
11197 ins_cost(300);
11198 format %{ "j$cop,u $labl" %}
11199 size(6);
11200 ins_encode %{
11201 Label* L = $labl$$label;
11202 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11203 %}
11204 ins_pipe(pipe_jcc);
11205 %}
11206
11207 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11208 match(If cop cmp);
11209 effect(USE labl);
11210
11211 ins_cost(200);
11212 format %{ "j$cop,u $labl" %}
11213 size(6);
11214 ins_encode %{
11215 Label* L = $labl$$label;
11216 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11217 %}
11218 ins_pipe(pipe_jcc);
11219 %}
11220
11221 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11222 match(If cop cmp);
11223 effect(USE labl);
11224
11225 ins_cost(200);
11226 format %{ $$template
11227 if ($cop$$cmpcode == Assembler::notEqual) {
11228 $$emit$$"jp,u $labl\n\t"
11229 $$emit$$"j$cop,u $labl"
11230 } else {
11231 $$emit$$"jp,u done\n\t"
11232 $$emit$$"j$cop,u $labl\n\t"
11233 $$emit$$"done:"
11234 }
11235 %}
11236 ins_encode %{
11237 Label* l = $labl$$label;
11238 if ($cop$$cmpcode == Assembler::notEqual) {
11239 __ jcc(Assembler::parity, *l, false);
11240 __ jcc(Assembler::notEqual, *l, false);
11241 } else if ($cop$$cmpcode == Assembler::equal) {
11242 Label done;
11243 __ jccb(Assembler::parity, done);
11244 __ jcc(Assembler::equal, *l, false);
11245 __ bind(done);
11246 } else {
11247 ShouldNotReachHere();
11248 }
11249 %}
11250 ins_pipe(pipe_jcc);
11251 %}
11252
11253 // ============================================================================
11254 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11255 // superklass array for an instance of the superklass. Set a hidden
11256 // internal cache on a hit (cache is checked with exposed code in
11257 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11258 // encoding ALSO sets flags.
11259
11260 instruct partialSubtypeCheck(rdi_RegP result,
11261 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11262 rFlagsReg cr)
11263 %{
11264 match(Set result (PartialSubtypeCheck sub super));
11265 effect(KILL rcx, KILL cr);
11266
11267 ins_cost(1100); // slightly larger than the next version
11268 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11269 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11270 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11271 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11272 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11273 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11274 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11275 "miss:\t" %}
11276
11277 opcode(0x1); // Force a XOR of RDI
11278 ins_encode(enc_PartialSubtypeCheck());
11279 ins_pipe(pipe_slow);
11280 %}
11281
11282 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11283 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11284 immP0 zero,
11285 rdi_RegP result)
11286 %{
11287 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11288 effect(KILL rcx, KILL result);
11289
11290 ins_cost(1000);
11291 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11292 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11293 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11294 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11295 "jne,s miss\t\t# Missed: flags nz\n\t"
11296 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11297 "miss:\t" %}
11298
11299 opcode(0x0); // No need to XOR RDI
11300 ins_encode(enc_PartialSubtypeCheck());
11301 ins_pipe(pipe_slow);
11302 %}
11303
11304 // ============================================================================
11305 // Branch Instructions -- short offset versions
11306 //
11307 // These instructions are used to replace jumps of a long offset (the default
11308 // match) with jumps of a shorter offset. These instructions are all tagged
11309 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11310 // match rules in general matching. Instead, the ADLC generates a conversion
11311 // method in the MachNode which can be used to do in-place replacement of the
11312 // long variant with the shorter variant. The compiler will determine if a
11313 // branch can be taken by the is_short_branch_offset() predicate in the machine
11314 // specific code section of the file.
11315
11316 // Jump Direct - Label defines a relative address from JMP+1
11317 instruct jmpDir_short(label labl) %{
11318 match(Goto);
11319 effect(USE labl);
11320
11321 ins_cost(300);
11322 format %{ "jmp,s $labl" %}
11323 size(2);
11324 ins_encode %{
11325 Label* L = $labl$$label;
11326 __ jmpb(*L);
11327 %}
11328 ins_pipe(pipe_jmp);
11329 ins_short_branch(1);
11330 %}
11331
11332 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11333 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11334 match(If cop cr);
11335 effect(USE labl);
11336
11337 ins_cost(300);
11338 format %{ "j$cop,s $labl" %}
11339 size(2);
11340 ins_encode %{
11341 Label* L = $labl$$label;
11342 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11343 %}
11344 ins_pipe(pipe_jcc);
11345 ins_short_branch(1);
11346 %}
11347
11348 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11349 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11350 match(CountedLoopEnd cop cr);
11351 effect(USE labl);
11352
11353 ins_cost(300);
11354 format %{ "j$cop,s $labl\t# loop end" %}
11355 size(2);
11356 ins_encode %{
11357 Label* L = $labl$$label;
11358 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11359 %}
11360 ins_pipe(pipe_jcc);
11361 ins_short_branch(1);
11362 %}
11363
11364 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11365 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11366 match(CountedLoopEnd cop cmp);
11367 effect(USE labl);
11368
11369 ins_cost(300);
11370 format %{ "j$cop,us $labl\t# loop end" %}
11371 size(2);
11372 ins_encode %{
11373 Label* L = $labl$$label;
11374 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11375 %}
11376 ins_pipe(pipe_jcc);
11377 ins_short_branch(1);
11378 %}
11379
11380 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11381 match(CountedLoopEnd cop cmp);
11382 effect(USE labl);
11383
11384 ins_cost(300);
11385 format %{ "j$cop,us $labl\t# loop end" %}
11386 size(2);
11387 ins_encode %{
11388 Label* L = $labl$$label;
11389 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11390 %}
11391 ins_pipe(pipe_jcc);
11392 ins_short_branch(1);
11393 %}
11394
11395 // Jump Direct Conditional - using unsigned comparison
11396 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11397 match(If cop cmp);
11398 effect(USE labl);
11399
11400 ins_cost(300);
11401 format %{ "j$cop,us $labl" %}
11402 size(2);
11403 ins_encode %{
11404 Label* L = $labl$$label;
11405 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11406 %}
11407 ins_pipe(pipe_jcc);
11408 ins_short_branch(1);
11409 %}
11410
11411 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11412 match(If cop cmp);
11413 effect(USE labl);
11414
11415 ins_cost(300);
11416 format %{ "j$cop,us $labl" %}
11417 size(2);
11418 ins_encode %{
11419 Label* L = $labl$$label;
11420 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11421 %}
11422 ins_pipe(pipe_jcc);
11423 ins_short_branch(1);
11424 %}
11425
11426 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11427 match(If cop cmp);
11428 effect(USE labl);
11429
11430 ins_cost(300);
11431 format %{ $$template
11432 if ($cop$$cmpcode == Assembler::notEqual) {
11433 $$emit$$"jp,u,s $labl\n\t"
11434 $$emit$$"j$cop,u,s $labl"
11435 } else {
11436 $$emit$$"jp,u,s done\n\t"
11437 $$emit$$"j$cop,u,s $labl\n\t"
11438 $$emit$$"done:"
11439 }
11440 %}
11441 size(4);
11442 ins_encode %{
11443 Label* l = $labl$$label;
11444 if ($cop$$cmpcode == Assembler::notEqual) {
11445 __ jccb(Assembler::parity, *l);
11446 __ jccb(Assembler::notEqual, *l);
11447 } else if ($cop$$cmpcode == Assembler::equal) {
11448 Label done;
11449 __ jccb(Assembler::parity, done);
11450 __ jccb(Assembler::equal, *l);
11451 __ bind(done);
11452 } else {
11453 ShouldNotReachHere();
11454 }
11455 %}
11456 ins_pipe(pipe_jcc);
11457 ins_short_branch(1);
11458 %}
11459
11460 // ============================================================================
11461 // inlined locking and unlocking
11462
11463 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11464 predicate(Compile::current()->use_rtm());
11465 match(Set cr (FastLock object box));
11466 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11467 ins_cost(300);
11468 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11469 ins_encode %{
11470 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11471 $scr$$Register, $cx1$$Register, $cx2$$Register,
11472 _counters, _rtm_counters, _stack_rtm_counters,
11473 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11474 true, ra_->C->profile_rtm());
11475 %}
11476 ins_pipe(pipe_slow);
11477 %}
11478
11479 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11480 predicate(!Compile::current()->use_rtm());
11481 match(Set cr (FastLock object box));
11482 effect(TEMP tmp, TEMP scr, USE_KILL box);
11483 ins_cost(300);
11484 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11485 ins_encode %{
11486 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11487 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11488 %}
11489 ins_pipe(pipe_slow);
11490 %}
11491
11492 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11493 match(Set cr (FastUnlock object box));
11494 effect(TEMP tmp, USE_KILL box);
11495 ins_cost(300);
11496 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11497 ins_encode %{
11498 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11499 %}
11500 ins_pipe(pipe_slow);
11501 %}
11502
11503
11504 // ============================================================================
11505 // Safepoint Instructions
11506 instruct safePoint_poll(rFlagsReg cr)
11507 %{
11508 predicate(!Assembler::is_polling_page_far());
11509 match(SafePoint);
11510 effect(KILL cr);
11511
11512 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11513 "# Safepoint: poll for GC" %}
11514 ins_cost(125);
11515 ins_encode %{
11516 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11517 __ testl(rax, addr);
11518 %}
11519 ins_pipe(ialu_reg_mem);
11520 %}
11521
11522 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11523 %{
11524 predicate(Assembler::is_polling_page_far());
11525 match(SafePoint poll);
11526 effect(KILL cr, USE poll);
11527
11528 format %{ "testl rax, [$poll]\t"
11529 "# Safepoint: poll for GC" %}
11530 ins_cost(125);
11531 ins_encode %{
11532 __ relocate(relocInfo::poll_type);
11533 __ testl(rax, Address($poll$$Register, 0));
11534 %}
11535 ins_pipe(ialu_reg_mem);
11536 %}
11537
11538 // ============================================================================
11539 // Procedure Call/Return Instructions
11540 // Call Java Static Instruction
11541 // Note: If this code changes, the corresponding ret_addr_offset() and
11542 // compute_padding() functions will have to be adjusted.
11543 instruct CallStaticJavaDirect(method meth) %{
11544 match(CallStaticJava);
11545 effect(USE meth);
11546
11547 ins_cost(300);
11548 format %{ "call,static " %}
11549 opcode(0xE8); /* E8 cd */
11550 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11551 ins_pipe(pipe_slow);
11552 ins_alignment(4);
11553 %}
11554
11555 // Call Java Dynamic Instruction
11556 // Note: If this code changes, the corresponding ret_addr_offset() and
11557 // compute_padding() functions will have to be adjusted.
11558 instruct CallDynamicJavaDirect(method meth)
11559 %{
11560 match(CallDynamicJava);
11561 effect(USE meth);
11562
11563 ins_cost(300);
11564 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11565 "call,dynamic " %}
11566 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11567 ins_pipe(pipe_slow);
11568 ins_alignment(4);
11569 %}
11570
11571 // Call Runtime Instruction
11572 instruct CallRuntimeDirect(method meth)
11573 %{
11574 match(CallRuntime);
11575 effect(USE meth);
11576
11577 ins_cost(300);
11578 format %{ "call,runtime " %}
11579 ins_encode(clear_avx, Java_To_Runtime(meth));
11580 ins_pipe(pipe_slow);
11581 %}
11582
11583 // Call runtime without safepoint
11584 instruct CallLeafDirect(method meth)
11585 %{
11586 match(CallLeaf);
11587 effect(USE meth);
11588
11589 ins_cost(300);
11590 format %{ "call_leaf,runtime " %}
11591 ins_encode(clear_avx, Java_To_Runtime(meth));
11592 ins_pipe(pipe_slow);
11593 %}
11594
11595 // Call runtime without safepoint
11596 instruct CallLeafNoFPDirect(method meth)
11597 %{
11598 match(CallLeafNoFP);
11599 effect(USE meth);
11600
11601 ins_cost(300);
11602 format %{ "call_leaf_nofp,runtime " %}
11603 ins_encode(Java_To_Runtime(meth));
11604 ins_pipe(pipe_slow);
11605 %}
11606
11607 // Return Instruction
11608 // Remove the return address & jump to it.
11609 // Notice: We always emit a nop after a ret to make sure there is room
11610 // for safepoint patching
11611 instruct Ret()
11612 %{
11613 match(Return);
11614
11615 format %{ "ret" %}
11616 opcode(0xC3);
11617 ins_encode(OpcP);
11618 ins_pipe(pipe_jmp);
11619 %}
11620
11621 // Tail Call; Jump from runtime stub to Java code.
11622 // Also known as an 'interprocedural jump'.
11623 // Target of jump will eventually return to caller.
11624 // TailJump below removes the return address.
11625 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11626 %{
11627 match(TailCall jump_target method_oop);
11628
11629 ins_cost(300);
11630 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11631 opcode(0xFF, 0x4); /* Opcode FF /4 */
11632 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11633 ins_pipe(pipe_jmp);
11634 %}
11635
11636 // Tail Jump; remove the return address; jump to target.
11637 // TailCall above leaves the return address around.
11638 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11639 %{
11640 match(TailJump jump_target ex_oop);
11641
11642 ins_cost(300);
11643 format %{ "popq rdx\t# pop return address\n\t"
11644 "jmp $jump_target" %}
11645 opcode(0xFF, 0x4); /* Opcode FF /4 */
11646 ins_encode(Opcode(0x5a), // popq rdx
11647 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11648 ins_pipe(pipe_jmp);
11649 %}
11650
11651 // Create exception oop: created by stack-crawling runtime code.
11652 // Created exception is now available to this handler, and is setup
11653 // just prior to jumping to this handler. No code emitted.
11654 instruct CreateException(rax_RegP ex_oop)
11655 %{
11656 match(Set ex_oop (CreateEx));
11657
11658 size(0);
11659 // use the following format syntax
11660 format %{ "# exception oop is in rax; no code emitted" %}
11661 ins_encode();
11662 ins_pipe(empty);
11663 %}
11664
11665 // Rethrow exception:
11666 // The exception oop will come in the first argument position.
11667 // Then JUMP (not call) to the rethrow stub code.
11668 instruct RethrowException()
11669 %{
11670 match(Rethrow);
11671
11672 // use the following format syntax
11673 format %{ "jmp rethrow_stub" %}
11674 ins_encode(enc_rethrow);
11675 ins_pipe(pipe_jmp);
11676 %}
11677
11678
11679 // ============================================================================
11680 // This name is KNOWN by the ADLC and cannot be changed.
11681 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11682 // for this guy.
11683 instruct tlsLoadP(r15_RegP dst) %{
11684 match(Set dst (ThreadLocal));
11685 effect(DEF dst);
11686
11687 size(0);
11688 format %{ "# TLS is in R15" %}
11689 ins_encode( /*empty encoding*/ );
11690 ins_pipe(ialu_reg_reg);
11691 %}
11692
11693
11694 //----------PEEPHOLE RULES-----------------------------------------------------
11695 // These must follow all instruction definitions as they use the names
11696 // defined in the instructions definitions.
11697 //
11698 // peepmatch ( root_instr_name [preceding_instruction]* );
11699 //
11700 // peepconstraint %{
11701 // (instruction_number.operand_name relational_op instruction_number.operand_name
11702 // [, ...] );
11703 // // instruction numbers are zero-based using left to right order in peepmatch
11704 //
11705 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
11706 // // provide an instruction_number.operand_name for each operand that appears
11707 // // in the replacement instruction's match rule
11708 //
11709 // ---------VM FLAGS---------------------------------------------------------
11710 //
11711 // All peephole optimizations can be turned off using -XX:-OptoPeephole
11712 //
11713 // Each peephole rule is given an identifying number starting with zero and
11714 // increasing by one in the order seen by the parser. An individual peephole
11715 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
11716 // on the command-line.
11717 //
11718 // ---------CURRENT LIMITATIONS----------------------------------------------
11719 //
11720 // Only match adjacent instructions in same basic block
11721 // Only equality constraints
11722 // Only constraints between operands, not (0.dest_reg == RAX_enc)
11723 // Only one replacement instruction
11724 //
11725 // ---------EXAMPLE----------------------------------------------------------
11726 //
11727 // // pertinent parts of existing instructions in architecture description
11728 // instruct movI(rRegI dst, rRegI src)
11729 // %{
11730 // match(Set dst (CopyI src));
11731 // %}
11732 //
11733 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
11734 // %{
11735 // match(Set dst (AddI dst src));
11736 // effect(KILL cr);
11737 // %}
11738 //
11739 // // Change (inc mov) to lea
11740 // peephole %{
11741 // // increment preceeded by register-register move
11742 // peepmatch ( incI_rReg movI );
11743 // // require that the destination register of the increment
11744 // // match the destination register of the move
11745 // peepconstraint ( 0.dst == 1.dst );
11746 // // construct a replacement instruction that sets
11747 // // the destination to ( move's source register + one )
11748 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
11749 // %}
11750 //
11751
11752 // Implementation no longer uses movX instructions since
11753 // machine-independent system no longer uses CopyX nodes.
11754 //
11755 // peephole
11756 // %{
11757 // peepmatch (incI_rReg movI);
11758 // peepconstraint (0.dst == 1.dst);
11759 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11760 // %}
11761
11762 // peephole
11763 // %{
11764 // peepmatch (decI_rReg movI);
11765 // peepconstraint (0.dst == 1.dst);
11766 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11767 // %}
11768
11769 // peephole
11770 // %{
11771 // peepmatch (addI_rReg_imm movI);
11772 // peepconstraint (0.dst == 1.dst);
11773 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
11774 // %}
11775
11776 // peephole
11777 // %{
11778 // peepmatch (incL_rReg movL);
11779 // peepconstraint (0.dst == 1.dst);
11780 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11781 // %}
11782
11783 // peephole
11784 // %{
11785 // peepmatch (decL_rReg movL);
11786 // peepconstraint (0.dst == 1.dst);
11787 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11788 // %}
11789
11790 // peephole
11791 // %{
11792 // peepmatch (addL_rReg_imm movL);
11793 // peepconstraint (0.dst == 1.dst);
11794 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
11795 // %}
11796
11797 // peephole
11798 // %{
11799 // peepmatch (addP_rReg_imm movP);
11800 // peepconstraint (0.dst == 1.dst);
11801 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
11802 // %}
11803
11804 // // Change load of spilled value to only a spill
11805 // instruct storeI(memory mem, rRegI src)
11806 // %{
11807 // match(Set mem (StoreI mem src));
11808 // %}
11809 //
11810 // instruct loadI(rRegI dst, memory mem)
11811 // %{
11812 // match(Set dst (LoadI mem));
11813 // %}
11814 //
11815
11816 peephole
11817 %{
11818 peepmatch (loadI storeI);
11819 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11820 peepreplace (storeI(1.mem 1.mem 1.src));
11821 %}
11822
11823 peephole
11824 %{
11825 peepmatch (loadL storeL);
11826 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
11827 peepreplace (storeL(1.mem 1.mem 1.src));
11828 %}
11829
11830 //----------SMARTSPILL RULES---------------------------------------------------
11831 // These must follow all instruction definitions as they use the names
11832 // defined in the instructions definitions.