1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1658 }
1659 }
1660
1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1664 emit_int8(0x2A);
1665 emit_int8((unsigned char)(0xC0 | encode));
1666 }
1667
1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1669 if (VM_Version::supports_evex()) {
1670 tuple_type = EVEX_T1S;
1671 input_size_in_bits = EVEX_32bit;
1672 }
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1675 }
1676
1677 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1679 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1680 }
1681
1682 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1683 if (VM_Version::supports_evex()) {
1684 tuple_type = EVEX_T1S;
1685 input_size_in_bits = EVEX_32bit;
1686 }
1687 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1688 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1689 }
1690
1691
1692 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1693 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1694 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1695 emit_int8(0x2C);
1696 emit_int8((unsigned char)(0xC0 | encode));
6585 emit_operand(reg, adr);
6586 }
6587
6588 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6590 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6591 emit_int8(0x2A);
6592 emit_int8((unsigned char)(0xC0 | encode));
6593 }
6594
6595 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6597 if (VM_Version::supports_evex()) {
6598 tuple_type = EVEX_T1S;
6599 input_size_in_bits = EVEX_32bit;
6600 }
6601 InstructionMark im(this);
6602 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6603 emit_int8(0x2A);
6604 emit_operand(dst, src);
6605 }
6606
6607 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
6608 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6609 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
6610 emit_int8(0x2A);
6611 emit_int8((unsigned char)(0xC0 | encode));
6612 }
6613
6614 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6616 if (VM_Version::supports_evex()) {
6617 tuple_type = EVEX_T1S;
6618 input_size_in_bits = EVEX_32bit;
6619 }
6620 InstructionMark im(this);
6621 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6622 emit_int8(0x2A);
6623 emit_operand(dst, src);
6624 }
6625
6626 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6628 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6629 emit_int8(0x2C);
6630 emit_int8((unsigned char)(0xC0 | encode));
6631 }
|
1657 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F2);
1658 }
1659 }
1660
1661 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, true);
1664 emit_int8(0x2A);
1665 emit_int8((unsigned char)(0xC0 | encode));
1666 }
1667
1668 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1669 if (VM_Version::supports_evex()) {
1670 tuple_type = EVEX_T1S;
1671 input_size_in_bits = EVEX_32bit;
1672 }
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 emit_simd_arith(0x2A, dst, src, VEX_SIMD_F3, true);
1675 }
1676
1677 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1678 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1679 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F3, true);
1680 emit_int8(0x2A);
1681 emit_int8((unsigned char)(0xC0 | encode));
1682 }
1683
1684 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1685 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1686 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1687 }
1688
1689 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1690 if (VM_Version::supports_evex()) {
1691 tuple_type = EVEX_T1S;
1692 input_size_in_bits = EVEX_32bit;
1693 }
1694 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1695 emit_simd_arith(0x5A, dst, src, VEX_SIMD_F3);
1696 }
1697
1698
1699 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1701 int encode = simd_prefix_and_encode(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
1702 emit_int8(0x2C);
1703 emit_int8((unsigned char)(0xC0 | encode));
6592 emit_operand(reg, adr);
6593 }
6594
6595 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
6596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6597 int encode = simd_prefix_and_encode_q(dst, dst, src, VEX_SIMD_F2, true);
6598 emit_int8(0x2A);
6599 emit_int8((unsigned char)(0xC0 | encode));
6600 }
6601
6602 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
6603 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6604 if (VM_Version::supports_evex()) {
6605 tuple_type = EVEX_T1S;
6606 input_size_in_bits = EVEX_32bit;
6607 }
6608 InstructionMark im(this);
6609 simd_prefix_q(dst, dst, src, VEX_SIMD_F2, true);
6610 emit_int8(0x2A);
6611 emit_operand(dst, src);
6612 }
6613
6614 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
6615 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6616 if (VM_Version::supports_evex()) {
6617 tuple_type = EVEX_T1S;
6618 input_size_in_bits = EVEX_32bit;
6619 }
6620 InstructionMark im(this);
6621 simd_prefix_q(dst, dst, src, VEX_SIMD_F3, true);
6622 emit_int8(0x2A);
6623 emit_operand(dst, src);
6624 }
6625
6626 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
6627 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6628 int encode = simd_prefix_and_encode_q(dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, true);
6629 emit_int8(0x2C);
6630 emit_int8((unsigned char)(0xC0 | encode));
6631 }
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