1071 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1072 }
1073
1074 // Use fast-string operations if available.
1075 if (supports_erms()) {
1076 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1077 UseFastStosb = true;
1078 }
1079 } else if (UseFastStosb) {
1080 warning("fast-string operations are not available on this CPU");
1081 FLAG_SET_DEFAULT(UseFastStosb, false);
1082 }
1083
1084 #ifdef COMPILER2
1085 if (FLAG_IS_DEFAULT(AlignVector)) {
1086 // Modern processors allow misaligned memory operations for vectors.
1087 AlignVector = !UseUnalignedLoadStores;
1088 }
1089 #endif // COMPILER2
1090
1091 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
1092
1093 // set valid Prefetch instruction
1094 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
1095 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
1096 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1097 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1098
1099 // Allocation prefetch settings
1100 intx cache_line_size = prefetch_data_size();
1101 if( cache_line_size > AllocatePrefetchStepSize )
1102 AllocatePrefetchStepSize = cache_line_size;
1103
1104 assert(AllocatePrefetchLines > 0, "invalid value");
1105 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1106 AllocatePrefetchLines = 3;
1107 assert(AllocateInstancePrefetchLines > 0, "invalid value");
1108 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
1109 AllocateInstancePrefetchLines = 1;
1110
1111 AllocatePrefetchDistance = allocate_prefetch_distance();
1112 AllocatePrefetchStyle = allocate_prefetch_style();
1113
1114 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1115 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1116 #ifdef _LP64
1117 AllocatePrefetchDistance = 384;
1118 #else
1119 AllocatePrefetchDistance = 320;
1120 #endif
1121 }
1122 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1123 AllocatePrefetchDistance = 192;
1124 AllocatePrefetchLines = 4;
1125 }
1126 #ifdef COMPILER2
1127 if (supports_sse4_2()) {
1128 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1129 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1130 }
1131 }
1132 #endif
1133 }
1134 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
1135
1136 #ifdef _LP64
1137 // Prefetch settings
1138 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1139 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1140 PrefetchFieldsAhead = prefetch_fields_ahead();
1141 #endif
1142
1143 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1144 (cache_line_size > ContendedPaddingWidth))
1145 ContendedPaddingWidth = cache_line_size;
1146
1147 // This machine allows unaligned memory accesses
1148 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1149 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1150 }
1151
1152 #ifndef PRODUCT
1153 if (PrintMiscellaneous && Verbose) {
1154 tty->print_cr("Logical CPUs per core: %u",
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1071 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1072 }
1073
1074 // Use fast-string operations if available.
1075 if (supports_erms()) {
1076 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1077 UseFastStosb = true;
1078 }
1079 } else if (UseFastStosb) {
1080 warning("fast-string operations are not available on this CPU");
1081 FLAG_SET_DEFAULT(UseFastStosb, false);
1082 }
1083
1084 #ifdef COMPILER2
1085 if (FLAG_IS_DEFAULT(AlignVector)) {
1086 // Modern processors allow misaligned memory operations for vectors.
1087 AlignVector = !UseUnalignedLoadStores;
1088 }
1089 #endif // COMPILER2
1090
1091 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1092 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1093
1094 // Allocation prefetch settings
1095 intx cache_line_size = prefetch_data_size();
1096 if( cache_line_size > AllocatePrefetchStepSize )
1097 AllocatePrefetchStepSize = cache_line_size;
1098
1099 assert(AllocatePrefetchLines > 0, "invalid value");
1100 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
1101 AllocatePrefetchLines = 3;
1102 assert(AllocateInstancePrefetchLines > 0, "invalid value");
1103 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
1104 AllocateInstancePrefetchLines = 1;
1105
1106 AllocatePrefetchDistance = allocate_prefetch_distance();
1107 AllocatePrefetchStyle = allocate_prefetch_style();
1108
1109 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1110 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1111 #ifdef _LP64
1112 AllocatePrefetchDistance = 384;
1113 #else
1114 AllocatePrefetchDistance = 320;
1115 #endif
1116 }
1117 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1118 AllocatePrefetchDistance = 192;
1119 AllocatePrefetchLines = 4;
1120 }
1121 #ifdef COMPILER2
1122 if (supports_sse4_2()) {
1123 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1124 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1125 }
1126 }
1127 #endif
1128 }
1129
1130 #ifdef _LP64
1131 // Prefetch settings
1132 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1133 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1134 PrefetchFieldsAhead = prefetch_fields_ahead();
1135 #endif
1136
1137 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1138 (cache_line_size > ContendedPaddingWidth))
1139 ContendedPaddingWidth = cache_line_size;
1140
1141 // This machine allows unaligned memory accesses
1142 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1143 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1144 }
1145
1146 #ifndef PRODUCT
1147 if (PrintMiscellaneous && Verbose) {
1148 tty->print_cr("Logical CPUs per core: %u",
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