1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/os.hpp"
30 #include "runtime/stubCodeGenerator.hpp"
31 #include "vm_version_sparc.hpp"
32
33 int VM_Version::_features = VM_Version::unknown_m;
34 const char* VM_Version::_features_str = "";
35 unsigned int VM_Version::_L2_data_cache_line_size = 0;
36
37 void VM_Version::initialize() {
38 _features = determine_features();
39 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
40 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
41 PrefetchFieldsAhead = prefetch_fields_ahead();
42
43 // Allocation prefetch settings
44 intx cache_line_size = prefetch_data_size();
45 if( cache_line_size > AllocatePrefetchStepSize )
46 AllocatePrefetchStepSize = cache_line_size;
47
48 assert(AllocatePrefetchLines > 0, "invalid value");
49 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
50 AllocatePrefetchLines = 3;
51 assert(AllocateInstancePrefetchLines > 0, "invalid value");
52 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
53 AllocateInstancePrefetchLines = 1;
54
55 AllocatePrefetchDistance = allocate_prefetch_distance();
56 AllocatePrefetchStyle = allocate_prefetch_style();
57
58 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
59 warning("BIS instructions are not available on this CPU");
60 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
61 }
62
63 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
64
65 UseSSE = 0; // Only on x86 and x64
66
67 _supports_cx8 = has_v9();
68 _supports_atomic_getset4 = true; // swap instruction
69
70 if (is_niagara()) {
71 // Indirect branch is the same cost as direct
72 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
73 FLAG_SET_DEFAULT(UseInlineCaches, false);
74 }
75 // Align loops on a single instruction boundary.
76 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
77 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
78 }
79 #ifdef _LP64
80 // 32-bit oops don't make sense for the 64-bit VM on sparc
81 // since the 32-bit VM has the same registers and smaller objects.
82 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
83 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
84 #endif // _LP64
85 #ifdef COMPILER2
86 // Indirect branch is the same cost as direct
87 if (FLAG_IS_DEFAULT(UseJumpTables)) {
88 FLAG_SET_DEFAULT(UseJumpTables, true);
89 }
90 // Single-issue, so entry and loop tops are
91 // aligned on a single instruction boundary
92 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
93 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
94 }
95 if (is_niagara_plus()) {
96 if (has_blk_init() && UseTLAB &&
97 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
98 // Use BIS instruction for TLAB allocation prefetch.
99 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
100 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
101 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
102 }
103 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
104 // Use smaller prefetch distance with BIS
105 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
106 }
107 }
108 if (is_T4()) {
109 // Double number of prefetched cache lines on T4
110 // since L2 cache line size is smaller (32 bytes).
111 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
112 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
113 }
114 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
115 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
116 }
117 }
118 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
119 // Use different prefetch distance without BIS
120 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
121 }
122 if (AllocatePrefetchInstr == 1) {
123 // Need a space at the end of TLAB for BIS since it
124 // will fault when accessing memory outside of heap.
125
126 // +1 for rounding up to next cache line, +1 to be safe
127 int lines = AllocatePrefetchLines + 2;
128 int step_size = AllocatePrefetchStepSize;
129 int distance = AllocatePrefetchDistance;
130 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
131 }
132 }
133 #endif
134 }
135
136 // Use hardware population count instruction if available.
137 if (has_hardware_popc()) {
138 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
139 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
140 }
141 } else if (UsePopCountInstruction) {
142 warning("POPC instruction is not available on this CPU");
143 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
144 }
145
146 // T4 and newer Sparc cpus have new compare and branch instruction.
147 if (has_cbcond()) {
148 if (FLAG_IS_DEFAULT(UseCBCond)) {
149 FLAG_SET_DEFAULT(UseCBCond, true);
150 }
151 } else if (UseCBCond) {
152 warning("CBCOND instruction is not available on this CPU");
153 FLAG_SET_DEFAULT(UseCBCond, false);
154 }
155
156 assert(BlockZeroingLowLimit > 0, "invalid value");
157 if (has_block_zeroing() && cache_line_size > 0) {
158 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
159 FLAG_SET_DEFAULT(UseBlockZeroing, true);
160 }
161 } else if (UseBlockZeroing) {
162 warning("BIS zeroing instructions are not available on this CPU");
163 FLAG_SET_DEFAULT(UseBlockZeroing, false);
164 }
165
166 assert(BlockCopyLowLimit > 0, "invalid value");
167 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
168 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
169 FLAG_SET_DEFAULT(UseBlockCopy, true);
170 }
171 } else if (UseBlockCopy) {
172 warning("BIS instructions are not available or expensive on this CPU");
173 FLAG_SET_DEFAULT(UseBlockCopy, false);
174 }
175
176 #ifdef COMPILER2
177 // T4 and newer Sparc cpus have fast RDPC.
178 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
179 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
180 }
181
182 // Currently not supported anywhere.
183 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
184
185 MaxVectorSize = 8;
186
187 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
188 #endif
189
190 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
191 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
192
193 char buf[512];
194 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
195 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
196 (has_hardware_popc() ? ", popc" : ""),
197 (has_vis1() ? ", vis1" : ""),
198 (has_vis2() ? ", vis2" : ""),
199 (has_vis3() ? ", vis3" : ""),
200 (has_blk_init() ? ", blk_init" : ""),
201 (has_cbcond() ? ", cbcond" : ""),
202 (has_aes() ? ", aes" : ""),
203 (has_sha1() ? ", sha1" : ""),
204 (has_sha256() ? ", sha256" : ""),
205 (has_sha512() ? ", sha512" : ""),
206 (has_crc32c() ? ", crc32c" : ""),
207 (is_ultra3() ? ", ultra3" : ""),
208 (is_sun4v() ? ", sun4v" : ""),
209 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
210 (is_sparc64() ? ", sparc64" : ""),
211 (!has_hardware_mul32() ? ", no-mul32" : ""),
212 (!has_hardware_div32() ? ", no-div32" : ""),
213 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
214
215 // buf is started with ", " or is empty
216 _features_str = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
217
218 // UseVIS is set to the smallest of what hardware supports and what
219 // the command line requires. I.e., you cannot set UseVIS to 3 on
220 // older UltraSparc which do not support it.
221 if (UseVIS > 3) UseVIS=3;
222 if (UseVIS < 0) UseVIS=0;
223 if (!has_vis3()) // Drop to 2 if no VIS3 support
224 UseVIS = MIN2((intx)2,UseVIS);
225 if (!has_vis2()) // Drop to 1 if no VIS2 support
226 UseVIS = MIN2((intx)1,UseVIS);
227 if (!has_vis1()) // Drop to 0 if no VIS1 support
228 UseVIS = 0;
229
230 // SPARC T4 and above should have support for AES instructions
231 if (has_aes()) {
232 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
233 if (FLAG_IS_DEFAULT(UseAES)) {
234 FLAG_SET_DEFAULT(UseAES, true);
235 }
236 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
237 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
238 }
239 // we disable both the AES flags if either of them is disabled on the command line
240 if (!UseAES || !UseAESIntrinsics) {
241 FLAG_SET_DEFAULT(UseAES, false);
242 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
243 }
244 } else {
245 if (UseAES || UseAESIntrinsics) {
246 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
247 if (UseAES) {
248 FLAG_SET_DEFAULT(UseAES, false);
249 }
250 if (UseAESIntrinsics) {
251 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
252 }
253 }
254 }
255 } else if (UseAES || UseAESIntrinsics) {
256 warning("AES instructions are not available on this CPU");
257 if (UseAES) {
258 FLAG_SET_DEFAULT(UseAES, false);
259 }
260 if (UseAESIntrinsics) {
261 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
262 }
263 }
264
265 // GHASH/GCM intrinsics
266 if (has_vis3() && (UseVIS > 2)) {
267 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
268 UseGHASHIntrinsics = true;
269 }
270 } else if (UseGHASHIntrinsics) {
271 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
272 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
273 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
274 }
275
276 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
277 if (has_sha1() || has_sha256() || has_sha512()) {
278 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
279 if (FLAG_IS_DEFAULT(UseSHA)) {
280 FLAG_SET_DEFAULT(UseSHA, true);
281 }
282 } else {
283 if (UseSHA) {
284 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
285 FLAG_SET_DEFAULT(UseSHA, false);
286 }
287 }
288 } else if (UseSHA) {
289 warning("SHA instructions are not available on this CPU");
290 FLAG_SET_DEFAULT(UseSHA, false);
291 }
292
293 if (UseSHA && has_sha1()) {
294 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
295 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
296 }
297 } else if (UseSHA1Intrinsics) {
298 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
299 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
300 }
301
302 if (UseSHA && has_sha256()) {
303 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
304 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
305 }
306 } else if (UseSHA256Intrinsics) {
307 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
308 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
309 }
310
311 if (UseSHA && has_sha512()) {
312 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
313 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
314 }
315 } else if (UseSHA512Intrinsics) {
316 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
317 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
318 }
319
320 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
321 FLAG_SET_DEFAULT(UseSHA, false);
322 }
323
324 // SPARC T4 and above should have support for CRC32C instruction
325 if (has_crc32c()) {
326 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
327 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
328 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
329 }
330 } else {
331 if (UseCRC32CIntrinsics) {
332 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
333 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
334 }
335 }
336 } else if (UseCRC32CIntrinsics) {
337 warning("CRC32C instruction is not available on this CPU");
338 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
339 }
340
341 if (UseVIS > 2) {
342 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
343 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
344 }
345 } else if (UseAdler32Intrinsics) {
346 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
347 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
348 }
349
350 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
351 (cache_line_size > ContendedPaddingWidth))
352 ContendedPaddingWidth = cache_line_size;
353
354 // This machine does not allow unaligned memory accesses
355 if (UseUnalignedAccesses) {
356 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
357 warning("Unaligned memory access is not available on this CPU");
358 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
359 }
360
361 #ifndef PRODUCT
362 if (PrintMiscellaneous && Verbose) {
363 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
364 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
365 tty->print("Allocation");
366 if (AllocatePrefetchStyle <= 0) {
367 tty->print_cr(": no prefetching");
368 } else {
369 tty->print(" prefetching: ");
370 if (AllocatePrefetchInstr == 0) {
371 tty->print("PREFETCH");
372 } else if (AllocatePrefetchInstr == 1) {
373 tty->print("BIS");
374 }
375 if (AllocatePrefetchLines > 1) {
376 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
377 } else {
378 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
379 }
380 }
381 if (PrefetchCopyIntervalInBytes > 0) {
382 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
383 }
384 if (PrefetchScanIntervalInBytes > 0) {
385 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
386 }
387 if (PrefetchFieldsAhead > 0) {
388 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
389 }
390 if (ContendedPaddingWidth > 0) {
391 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
392 }
393 }
394 #endif // PRODUCT
395 }
396
397 void VM_Version::print_features() {
398 tty->print_cr("Version:%s", cpu_features());
399 }
400
401 int VM_Version::determine_features() {
402 if (UseV8InstrsOnly) {
403 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
404 return generic_v8_m;
405 }
406
407 int features = platform_features(unknown_m); // platform_features() is os_arch specific
408
409 if (features == unknown_m) {
410 features = generic_v9_m;
411 warning("Cannot recognize SPARC version. Default to V9");
412 }
413
414 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
415 if (UseNiagaraInstrs) { // Force code generation for Niagara
416 if (is_T_family(features)) {
417 // Happy to accomodate...
418 } else {
419 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
420 features |= T_family_m;
421 }
422 } else {
423 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
424 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
425 features &= ~(T_family_m | T1_model_m);
426 } else {
427 // Happy to accomodate...
428 }
429 }
430
431 return features;
432 }
433
434 static int saved_features = 0;
435
436 void VM_Version::allow_all() {
437 saved_features = _features;
438 _features = all_features_m;
439 }
440
441 void VM_Version::revert() {
442 _features = saved_features;
443 }
444
445 unsigned int VM_Version::calc_parallel_worker_threads() {
446 unsigned int result;
447 if (is_M_series()) {
448 // for now, use same gc thread calculation for M-series as for niagara-plus
449 // in future, we may want to tweak parameters for nof_parallel_worker_thread
450 result = nof_parallel_worker_threads(5, 16, 8);
451 } else if (is_niagara_plus()) {
452 result = nof_parallel_worker_threads(5, 16, 8);
453 } else {
454 result = nof_parallel_worker_threads(5, 8, 8);
455 }
456 return result;
457 }