1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "utilities/macros.hpp"
43 #if INCLUDE_ALL_GCS
44 #include "gc/g1/g1CollectedHeap.inline.hpp"
45 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
46 #include "gc/g1/heapRegion.hpp"
47 #endif // INCLUDE_ALL_GCS
48 #include "crc32c.h"
49
50 #ifdef PRODUCT
51 #define BLOCK_COMMENT(str) /* nothing */
52 #define STOP(error) stop(error)
53 #else
54 #define BLOCK_COMMENT(str) block_comment(str)
55 #define STOP(error) block_comment(error); stop(error)
56 #endif
57
58 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
59
60 PRAGMA_FORMAT_MUTE_WARNINGS_FOR_GCC
61
62 #ifdef ASSERT
63 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
64 #endif
65
66 static Assembler::Condition reverse[] = {
67 Assembler::noOverflow /* overflow = 0x0 */ ,
68 Assembler::overflow /* noOverflow = 0x1 */ ,
69 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
70 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
71 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
72 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
73 Assembler::above /* belowEqual = 0x6 */ ,
74 Assembler::belowEqual /* above = 0x7 */ ,
75 Assembler::positive /* negative = 0x8 */ ,
76 Assembler::negative /* positive = 0x9 */ ,
77 Assembler::noParity /* parity = 0xa */ ,
78 Assembler::parity /* noParity = 0xb */ ,
79 Assembler::greaterEqual /* less = 0xc */ ,
80 Assembler::less /* greaterEqual = 0xd */ ,
81 Assembler::greater /* lessEqual = 0xe */ ,
82 Assembler::lessEqual /* greater = 0xf, */
83
84 };
85
86
87 // Implementation of MacroAssembler
88
89 // First all the versions that have distinct versions depending on 32/64 bit
90 // Unless the difference is trivial (1 line or so).
91
92 #ifndef _LP64
93
94 // 32bit versions
95
96 Address MacroAssembler::as_Address(AddressLiteral adr) {
97 return Address(adr.target(), adr.rspec());
98 }
99
100 Address MacroAssembler::as_Address(ArrayAddress adr) {
101 return Address::make_array(adr);
102 }
103
104 void MacroAssembler::call_VM_leaf_base(address entry_point,
105 int number_of_arguments) {
106 call(RuntimeAddress(entry_point));
107 increment(rsp, number_of_arguments * wordSize);
108 }
109
110 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
111 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
112 }
113
114 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
118 void MacroAssembler::cmpoop(Address src1, jobject obj) {
119 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
120 }
121
122 void MacroAssembler::cmpoop(Register src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
126 void MacroAssembler::extend_sign(Register hi, Register lo) {
127 // According to Intel Doc. AP-526, "Integer Divide", p.18.
128 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
129 cdql();
130 } else {
131 movl(hi, lo);
132 sarl(hi, 31);
133 }
134 }
135
136 void MacroAssembler::jC2(Register tmp, Label& L) {
137 // set parity bit if FPU flag C2 is set (via rax)
138 save_rax(tmp);
139 fwait(); fnstsw_ax();
140 sahf();
141 restore_rax(tmp);
142 // branch
143 jcc(Assembler::parity, L);
144 }
145
146 void MacroAssembler::jnC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::noParity, L);
154 }
155
156 // 32bit can do a case table jump in one instruction but we no longer allow the base
157 // to be installed in the Address class
158 void MacroAssembler::jump(ArrayAddress entry) {
159 jmp(as_Address(entry));
160 }
161
162 // Note: y_lo will be destroyed
163 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
164 // Long compare for Java (semantics as described in JVM spec.)
165 Label high, low, done;
166
167 cmpl(x_hi, y_hi);
168 jcc(Assembler::less, low);
169 jcc(Assembler::greater, high);
170 // x_hi is the return register
171 xorl(x_hi, x_hi);
172 cmpl(x_lo, y_lo);
173 jcc(Assembler::below, low);
174 jcc(Assembler::equal, done);
175
176 bind(high);
177 xorl(x_hi, x_hi);
178 increment(x_hi);
179 jmp(done);
180
181 bind(low);
182 xorl(x_hi, x_hi);
183 decrementl(x_hi);
184
185 bind(done);
186 }
187
188 void MacroAssembler::lea(Register dst, AddressLiteral src) {
189 mov_literal32(dst, (int32_t)src.target(), src.rspec());
190 }
191
192 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
193 // leal(dst, as_Address(adr));
194 // see note in movl as to why we must use a move
195 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
196 }
197
198 void MacroAssembler::leave() {
199 mov(rsp, rbp);
200 pop(rbp);
201 }
202
203 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
204 // Multiplication of two Java long values stored on the stack
205 // as illustrated below. Result is in rdx:rax.
206 //
207 // rsp ---> [ ?? ] \ \
208 // .... | y_rsp_offset |
209 // [ y_lo ] / (in bytes) | x_rsp_offset
210 // [ y_hi ] | (in bytes)
211 // .... |
212 // [ x_lo ] /
213 // [ x_hi ]
214 // ....
215 //
216 // Basic idea: lo(result) = lo(x_lo * y_lo)
217 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
218 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
219 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
220 Label quick;
221 // load x_hi, y_hi and check if quick
222 // multiplication is possible
223 movl(rbx, x_hi);
224 movl(rcx, y_hi);
225 movl(rax, rbx);
226 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
227 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
228 // do full multiplication
229 // 1st step
230 mull(y_lo); // x_hi * y_lo
231 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
232 // 2nd step
233 movl(rax, x_lo);
234 mull(rcx); // x_lo * y_hi
235 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
236 // 3rd step
237 bind(quick); // note: rbx, = 0 if quick multiply!
238 movl(rax, x_lo);
239 mull(y_lo); // x_lo * y_lo
240 addl(rdx, rbx); // correct hi(x_lo * y_lo)
241 }
242
243 void MacroAssembler::lneg(Register hi, Register lo) {
244 negl(lo);
245 adcl(hi, 0);
246 negl(hi);
247 }
248
249 void MacroAssembler::lshl(Register hi, Register lo) {
250 // Java shift left long support (semantics as described in JVM spec., p.305)
251 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
252 // shift value is in rcx !
253 assert(hi != rcx, "must not use rcx");
254 assert(lo != rcx, "must not use rcx");
255 const Register s = rcx; // shift count
256 const int n = BitsPerWord;
257 Label L;
258 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
259 cmpl(s, n); // if (s < n)
260 jcc(Assembler::less, L); // else (s >= n)
261 movl(hi, lo); // x := x << n
262 xorl(lo, lo);
263 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
264 bind(L); // s (mod n) < n
265 shldl(hi, lo); // x := x << s
266 shll(lo);
267 }
268
269
270 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
271 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
272 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
273 assert(hi != rcx, "must not use rcx");
274 assert(lo != rcx, "must not use rcx");
275 const Register s = rcx; // shift count
276 const int n = BitsPerWord;
277 Label L;
278 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
279 cmpl(s, n); // if (s < n)
280 jcc(Assembler::less, L); // else (s >= n)
281 movl(lo, hi); // x := x >> n
282 if (sign_extension) sarl(hi, 31);
283 else xorl(hi, hi);
284 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
285 bind(L); // s (mod n) < n
286 shrdl(lo, hi); // x := x >> s
287 if (sign_extension) sarl(hi);
288 else shrl(hi);
289 }
290
291 void MacroAssembler::movoop(Register dst, jobject obj) {
292 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
293 }
294
295 void MacroAssembler::movoop(Address dst, jobject obj) {
296 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
297 }
298
299 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
300 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
301 }
302
303 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
304 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
305 }
306
307 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
308 // scratch register is not used,
309 // it is defined to match parameters of 64-bit version of this method.
310 if (src.is_lval()) {
311 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
312 } else {
313 movl(dst, as_Address(src));
314 }
315 }
316
317 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
318 movl(as_Address(dst), src);
319 }
320
321 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
322 movl(dst, as_Address(src));
323 }
324
325 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
326 void MacroAssembler::movptr(Address dst, intptr_t src) {
327 movl(dst, src);
328 }
329
330
331 void MacroAssembler::pop_callee_saved_registers() {
332 pop(rcx);
333 pop(rdx);
334 pop(rdi);
335 pop(rsi);
336 }
337
338 void MacroAssembler::pop_fTOS() {
339 fld_d(Address(rsp, 0));
340 addl(rsp, 2 * wordSize);
341 }
342
343 void MacroAssembler::push_callee_saved_registers() {
344 push(rsi);
345 push(rdi);
346 push(rdx);
347 push(rcx);
348 }
349
350 void MacroAssembler::push_fTOS() {
351 subl(rsp, 2 * wordSize);
352 fstp_d(Address(rsp, 0));
353 }
354
355
356 void MacroAssembler::pushoop(jobject obj) {
357 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
358 }
359
360 void MacroAssembler::pushklass(Metadata* obj) {
361 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
362 }
363
364 void MacroAssembler::pushptr(AddressLiteral src) {
365 if (src.is_lval()) {
366 push_literal32((int32_t)src.target(), src.rspec());
367 } else {
368 pushl(as_Address(src));
369 }
370 }
371
372 void MacroAssembler::set_word_if_not_zero(Register dst) {
373 xorl(dst, dst);
374 set_byte_if_not_zero(dst);
375 }
376
377 static void pass_arg0(MacroAssembler* masm, Register arg) {
378 masm->push(arg);
379 }
380
381 static void pass_arg1(MacroAssembler* masm, Register arg) {
382 masm->push(arg);
383 }
384
385 static void pass_arg2(MacroAssembler* masm, Register arg) {
386 masm->push(arg);
387 }
388
389 static void pass_arg3(MacroAssembler* masm, Register arg) {
390 masm->push(arg);
391 }
392
393 #ifndef PRODUCT
394 extern "C" void findpc(intptr_t x);
395 #endif
396
397 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
398 // In order to get locks to work, we need to fake a in_VM state
399 JavaThread* thread = JavaThread::current();
400 JavaThreadState saved_state = thread->thread_state();
401 thread->set_thread_state(_thread_in_vm);
402 if (ShowMessageBoxOnError) {
403 JavaThread* thread = JavaThread::current();
404 JavaThreadState saved_state = thread->thread_state();
405 thread->set_thread_state(_thread_in_vm);
406 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
407 ttyLocker ttyl;
408 BytecodeCounter::print();
409 }
410 // To see where a verify_oop failed, get $ebx+40/X for this frame.
411 // This is the value of eip which points to where verify_oop will return.
412 if (os::message_box(msg, "Execution stopped, print registers?")) {
413 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
414 BREAKPOINT;
415 }
416 } else {
417 ttyLocker ttyl;
418 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
419 }
420 // Don't assert holding the ttyLock
421 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
422 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
423 }
424
425 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
426 ttyLocker ttyl;
427 FlagSetting fs(Debugging, true);
428 tty->print_cr("eip = 0x%08x", eip);
429 #ifndef PRODUCT
430 if ((WizardMode || Verbose) && PrintMiscellaneous) {
431 tty->cr();
432 findpc(eip);
433 tty->cr();
434 }
435 #endif
436 #define PRINT_REG(rax) \
437 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
438 PRINT_REG(rax);
439 PRINT_REG(rbx);
440 PRINT_REG(rcx);
441 PRINT_REG(rdx);
442 PRINT_REG(rdi);
443 PRINT_REG(rsi);
444 PRINT_REG(rbp);
445 PRINT_REG(rsp);
446 #undef PRINT_REG
447 // Print some words near top of staack.
448 int* dump_sp = (int*) rsp;
449 for (int col1 = 0; col1 < 8; col1++) {
450 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
451 os::print_location(tty, *dump_sp++);
452 }
453 for (int row = 0; row < 16; row++) {
454 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
455 for (int col = 0; col < 8; col++) {
456 tty->print(" 0x%08x", *dump_sp++);
457 }
458 tty->cr();
459 }
460 // Print some instructions around pc:
461 Disassembler::decode((address)eip-64, (address)eip);
462 tty->print_cr("--------");
463 Disassembler::decode((address)eip, (address)eip+32);
464 }
465
466 void MacroAssembler::stop(const char* msg) {
467 ExternalAddress message((address)msg);
468 // push address of message
469 pushptr(message.addr());
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
473 hlt();
474 }
475
476 void MacroAssembler::warn(const char* msg) {
477 push_CPU_state();
478
479 ExternalAddress message((address) msg);
480 // push address of message
481 pushptr(message.addr());
482
483 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
484 addl(rsp, wordSize); // discard argument
485 pop_CPU_state();
486 }
487
488 void MacroAssembler::print_state() {
489 { Label L; call(L, relocInfo::none); bind(L); } // push eip
490 pusha(); // push registers
491
492 push_CPU_state();
493 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
494 pop_CPU_state();
495
496 popa();
497 addl(rsp, wordSize);
498 }
499
500 #else // _LP64
501
502 // 64 bit versions
503
504 Address MacroAssembler::as_Address(AddressLiteral adr) {
505 // amd64 always does this as a pc-rel
506 // we can be absolute or disp based on the instruction type
507 // jmp/call are displacements others are absolute
508 assert(!adr.is_lval(), "must be rval");
509 assert(reachable(adr), "must be");
510 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
511
512 }
513
514 Address MacroAssembler::as_Address(ArrayAddress adr) {
515 AddressLiteral base = adr.base();
516 lea(rscratch1, base);
517 Address index = adr.index();
518 assert(index._disp == 0, "must not have disp"); // maybe it can?
519 Address array(rscratch1, index._index, index._scale, index._disp);
520 return array;
521 }
522
523 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
524 Label L, E;
525
526 #ifdef _WIN64
527 // Windows always allocates space for it's register args
528 assert(num_args <= 4, "only register arguments supported");
529 subq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531
532 // Align stack if necessary
533 testl(rsp, 15);
534 jcc(Assembler::zero, L);
535
536 subq(rsp, 8);
537 {
538 call(RuntimeAddress(entry_point));
539 }
540 addq(rsp, 8);
541 jmp(E);
542
543 bind(L);
544 {
545 call(RuntimeAddress(entry_point));
546 }
547
548 bind(E);
549
550 #ifdef _WIN64
551 // restore stack pointer
552 addq(rsp, frame::arg_reg_save_area_bytes);
553 #endif
554
555 }
556
557 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
558 assert(!src2.is_lval(), "should use cmpptr");
559
560 if (reachable(src2)) {
561 cmpq(src1, as_Address(src2));
562 } else {
563 lea(rscratch1, src2);
564 Assembler::cmpq(src1, Address(rscratch1, 0));
565 }
566 }
567
568 int MacroAssembler::corrected_idivq(Register reg) {
569 // Full implementation of Java ldiv and lrem; checks for special
570 // case as described in JVM spec., p.243 & p.271. The function
571 // returns the (pc) offset of the idivl instruction - may be needed
572 // for implicit exceptions.
573 //
574 // normal case special case
575 //
576 // input : rax: dividend min_long
577 // reg: divisor (may not be eax/edx) -1
578 //
579 // output: rax: quotient (= rax idiv reg) min_long
580 // rdx: remainder (= rax irem reg) 0
581 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
582 static const int64_t min_long = 0x8000000000000000;
583 Label normal_case, special_case;
584
585 // check for special case
586 cmp64(rax, ExternalAddress((address) &min_long));
587 jcc(Assembler::notEqual, normal_case);
588 xorl(rdx, rdx); // prepare rdx for possible special case (where
589 // remainder = 0)
590 cmpq(reg, -1);
591 jcc(Assembler::equal, special_case);
592
593 // handle normal case
594 bind(normal_case);
595 cdqq();
596 int idivq_offset = offset();
597 idivq(reg);
598
599 // normal and special case exit
600 bind(special_case);
601
602 return idivq_offset;
603 }
604
605 void MacroAssembler::decrementq(Register reg, int value) {
606 if (value == min_jint) { subq(reg, value); return; }
607 if (value < 0) { incrementq(reg, -value); return; }
608 if (value == 0) { ; return; }
609 if (value == 1 && UseIncDec) { decq(reg) ; return; }
610 /* else */ { subq(reg, value) ; return; }
611 }
612
613 void MacroAssembler::decrementq(Address dst, int value) {
614 if (value == min_jint) { subq(dst, value); return; }
615 if (value < 0) { incrementq(dst, -value); return; }
616 if (value == 0) { ; return; }
617 if (value == 1 && UseIncDec) { decq(dst) ; return; }
618 /* else */ { subq(dst, value) ; return; }
619 }
620
621 void MacroAssembler::incrementq(AddressLiteral dst) {
622 if (reachable(dst)) {
623 incrementq(as_Address(dst));
624 } else {
625 lea(rscratch1, dst);
626 incrementq(Address(rscratch1, 0));
627 }
628 }
629
630 void MacroAssembler::incrementq(Register reg, int value) {
631 if (value == min_jint) { addq(reg, value); return; }
632 if (value < 0) { decrementq(reg, -value); return; }
633 if (value == 0) { ; return; }
634 if (value == 1 && UseIncDec) { incq(reg) ; return; }
635 /* else */ { addq(reg, value) ; return; }
636 }
637
638 void MacroAssembler::incrementq(Address dst, int value) {
639 if (value == min_jint) { addq(dst, value); return; }
640 if (value < 0) { decrementq(dst, -value); return; }
641 if (value == 0) { ; return; }
642 if (value == 1 && UseIncDec) { incq(dst) ; return; }
643 /* else */ { addq(dst, value) ; return; }
644 }
645
646 // 32bit can do a case table jump in one instruction but we no longer allow the base
647 // to be installed in the Address class
648 void MacroAssembler::jump(ArrayAddress entry) {
649 lea(rscratch1, entry.base());
650 Address dispatch = entry.index();
651 assert(dispatch._base == noreg, "must be");
652 dispatch._base = rscratch1;
653 jmp(dispatch);
654 }
655
656 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
657 ShouldNotReachHere(); // 64bit doesn't use two regs
658 cmpq(x_lo, y_lo);
659 }
660
661 void MacroAssembler::lea(Register dst, AddressLiteral src) {
662 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
663 }
664
665 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
666 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
667 movptr(dst, rscratch1);
668 }
669
670 void MacroAssembler::leave() {
671 // %%% is this really better? Why not on 32bit too?
672 emit_int8((unsigned char)0xC9); // LEAVE
673 }
674
675 void MacroAssembler::lneg(Register hi, Register lo) {
676 ShouldNotReachHere(); // 64bit doesn't use two regs
677 negq(lo);
678 }
679
680 void MacroAssembler::movoop(Register dst, jobject obj) {
681 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
682 }
683
684 void MacroAssembler::movoop(Address dst, jobject obj) {
685 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
686 movq(dst, rscratch1);
687 }
688
689 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
690 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
691 }
692
693 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
694 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
695 movq(dst, rscratch1);
696 }
697
698 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
699 if (src.is_lval()) {
700 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
701 } else {
702 if (reachable(src)) {
703 movq(dst, as_Address(src));
704 } else {
705 lea(scratch, src);
706 movq(dst, Address(scratch, 0));
707 }
708 }
709 }
710
711 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
712 movq(as_Address(dst), src);
713 }
714
715 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
716 movq(dst, as_Address(src));
717 }
718
719 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
720 void MacroAssembler::movptr(Address dst, intptr_t src) {
721 mov64(rscratch1, src);
722 movq(dst, rscratch1);
723 }
724
725 // These are mostly for initializing NULL
726 void MacroAssembler::movptr(Address dst, int32_t src) {
727 movslq(dst, src);
728 }
729
730 void MacroAssembler::movptr(Register dst, int32_t src) {
731 mov64(dst, (intptr_t)src);
732 }
733
734 void MacroAssembler::pushoop(jobject obj) {
735 movoop(rscratch1, obj);
736 push(rscratch1);
737 }
738
739 void MacroAssembler::pushklass(Metadata* obj) {
740 mov_metadata(rscratch1, obj);
741 push(rscratch1);
742 }
743
744 void MacroAssembler::pushptr(AddressLiteral src) {
745 lea(rscratch1, src);
746 if (src.is_lval()) {
747 push(rscratch1);
748 } else {
749 pushq(Address(rscratch1, 0));
750 }
751 }
752
753 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
754 bool clear_pc) {
755 // we must set sp to zero to clear frame
756 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
757 // must clear fp, so that compiled frames are not confused; it is
758 // possible that we need it only for debugging
759 if (clear_fp) {
760 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
761 }
762
763 if (clear_pc) {
764 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
765 }
766 }
767
768 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
769 Register last_java_fp,
770 address last_java_pc) {
771 // determine last_java_sp register
772 if (!last_java_sp->is_valid()) {
773 last_java_sp = rsp;
774 }
775
776 // last_java_fp is optional
777 if (last_java_fp->is_valid()) {
778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
779 last_java_fp);
780 }
781
782 // last_java_pc is optional
783 if (last_java_pc != NULL) {
784 Address java_pc(r15_thread,
785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
786 lea(rscratch1, InternalAddress(last_java_pc));
787 movptr(java_pc, rscratch1);
788 }
789
790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
791 }
792
793 static void pass_arg0(MacroAssembler* masm, Register arg) {
794 if (c_rarg0 != arg ) {
795 masm->mov(c_rarg0, arg);
796 }
797 }
798
799 static void pass_arg1(MacroAssembler* masm, Register arg) {
800 if (c_rarg1 != arg ) {
801 masm->mov(c_rarg1, arg);
802 }
803 }
804
805 static void pass_arg2(MacroAssembler* masm, Register arg) {
806 if (c_rarg2 != arg ) {
807 masm->mov(c_rarg2, arg);
808 }
809 }
810
811 static void pass_arg3(MacroAssembler* masm, Register arg) {
812 if (c_rarg3 != arg ) {
813 masm->mov(c_rarg3, arg);
814 }
815 }
816
817 void MacroAssembler::stop(const char* msg) {
818 address rip = pc();
819 pusha(); // get regs on stack
820 lea(c_rarg0, ExternalAddress((address) msg));
821 lea(c_rarg1, InternalAddress(rip));
822 movq(c_rarg2, rsp); // pass pointer to regs array
823 andq(rsp, -16); // align stack as required by ABI
824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
825 hlt();
826 }
827
828 void MacroAssembler::warn(const char* msg) {
829 push(rbp);
830 movq(rbp, rsp);
831 andq(rsp, -16); // align stack as required by push_CPU_state and call
832 push_CPU_state(); // keeps alignment at 16 bytes
833 lea(c_rarg0, ExternalAddress((address) msg));
834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
835 pop_CPU_state();
836 mov(rsp, rbp);
837 pop(rbp);
838 }
839
840 void MacroAssembler::print_state() {
841 address rip = pc();
842 pusha(); // get regs on stack
843 push(rbp);
844 movq(rbp, rsp);
845 andq(rsp, -16); // align stack as required by push_CPU_state and call
846 push_CPU_state(); // keeps alignment at 16 bytes
847
848 lea(c_rarg0, InternalAddress(rip));
849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
851
852 pop_CPU_state();
853 mov(rsp, rbp);
854 pop(rbp);
855 popa();
856 }
857
858 #ifndef PRODUCT
859 extern "C" void findpc(intptr_t x);
860 #endif
861
862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
863 // In order to get locks to work, we need to fake a in_VM state
864 if (ShowMessageBoxOnError) {
865 JavaThread* thread = JavaThread::current();
866 JavaThreadState saved_state = thread->thread_state();
867 thread->set_thread_state(_thread_in_vm);
868 #ifndef PRODUCT
869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
870 ttyLocker ttyl;
871 BytecodeCounter::print();
872 }
873 #endif
874 // To see where a verify_oop failed, get $ebx+40/X for this frame.
875 // XXX correct this offset for amd64
876 // This is the value of eip which points to where verify_oop will return.
877 if (os::message_box(msg, "Execution stopped, print registers?")) {
878 print_state64(pc, regs);
879 BREAKPOINT;
880 assert(false, "start up GDB");
881 }
882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
883 } else {
884 ttyLocker ttyl;
885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
886 msg);
887 assert(false, err_msg("DEBUG MESSAGE: %s", msg));
888 }
889 }
890
891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
892 ttyLocker ttyl;
893 FlagSetting fs(Debugging, true);
894 tty->print_cr("rip = 0x%016lx", pc);
895 #ifndef PRODUCT
896 tty->cr();
897 findpc(pc);
898 tty->cr();
899 #endif
900 #define PRINT_REG(rax, value) \
901 { tty->print("%s = ", #rax); os::print_location(tty, value); }
902 PRINT_REG(rax, regs[15]);
903 PRINT_REG(rbx, regs[12]);
904 PRINT_REG(rcx, regs[14]);
905 PRINT_REG(rdx, regs[13]);
906 PRINT_REG(rdi, regs[8]);
907 PRINT_REG(rsi, regs[9]);
908 PRINT_REG(rbp, regs[10]);
909 PRINT_REG(rsp, regs[11]);
910 PRINT_REG(r8 , regs[7]);
911 PRINT_REG(r9 , regs[6]);
912 PRINT_REG(r10, regs[5]);
913 PRINT_REG(r11, regs[4]);
914 PRINT_REG(r12, regs[3]);
915 PRINT_REG(r13, regs[2]);
916 PRINT_REG(r14, regs[1]);
917 PRINT_REG(r15, regs[0]);
918 #undef PRINT_REG
919 // Print some words near top of staack.
920 int64_t* rsp = (int64_t*) regs[11];
921 int64_t* dump_sp = rsp;
922 for (int col1 = 0; col1 < 8; col1++) {
923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
924 os::print_location(tty, *dump_sp++);
925 }
926 for (int row = 0; row < 25; row++) {
927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
928 for (int col = 0; col < 4; col++) {
929 tty->print(" 0x%016lx", *dump_sp++);
930 }
931 tty->cr();
932 }
933 // Print some instructions around pc:
934 Disassembler::decode((address)pc-64, (address)pc);
935 tty->print_cr("--------");
936 Disassembler::decode((address)pc, (address)pc+32);
937 }
938
939 #endif // _LP64
940
941 // Now versions that are common to 32/64 bit
942
943 void MacroAssembler::addptr(Register dst, int32_t imm32) {
944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
945 }
946
947 void MacroAssembler::addptr(Register dst, Register src) {
948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
949 }
950
951 void MacroAssembler::addptr(Address dst, Register src) {
952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
953 }
954
955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
956 if (reachable(src)) {
957 Assembler::addsd(dst, as_Address(src));
958 } else {
959 lea(rscratch1, src);
960 Assembler::addsd(dst, Address(rscratch1, 0));
961 }
962 }
963
964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
965 if (reachable(src)) {
966 addss(dst, as_Address(src));
967 } else {
968 lea(rscratch1, src);
969 addss(dst, Address(rscratch1, 0));
970 }
971 }
972
973 void MacroAssembler::align(int modulus) {
974 align(modulus, offset());
975 }
976
977 void MacroAssembler::align(int modulus, int target) {
978 if (target % modulus != 0) {
979 nop(modulus - (target % modulus));
980 }
981 }
982
983 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
984 // Used in sign-masking with aligned address.
985 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
986 if (reachable(src)) {
987 Assembler::andpd(dst, as_Address(src));
988 } else {
989 lea(rscratch1, src);
990 Assembler::andpd(dst, Address(rscratch1, 0));
991 }
992 }
993
994 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andps(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andps(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1006 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1007 }
1008
1009 void MacroAssembler::atomic_incl(Address counter_addr) {
1010 if (os::is_MP())
1011 lock();
1012 incrementl(counter_addr);
1013 }
1014
1015 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1016 if (reachable(counter_addr)) {
1017 atomic_incl(as_Address(counter_addr));
1018 } else {
1019 lea(scr, counter_addr);
1020 atomic_incl(Address(scr, 0));
1021 }
1022 }
1023
1024 #ifdef _LP64
1025 void MacroAssembler::atomic_incq(Address counter_addr) {
1026 if (os::is_MP())
1027 lock();
1028 incrementq(counter_addr);
1029 }
1030
1031 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1032 if (reachable(counter_addr)) {
1033 atomic_incq(as_Address(counter_addr));
1034 } else {
1035 lea(scr, counter_addr);
1036 atomic_incq(Address(scr, 0));
1037 }
1038 }
1039 #endif
1040
1041 // Writes to stack successive pages until offset reached to check for
1042 // stack overflow + shadow pages. This clobbers tmp.
1043 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1044 movptr(tmp, rsp);
1045 // Bang stack for total size given plus shadow page size.
1046 // Bang one page at a time because large size can bang beyond yellow and
1047 // red zones.
1048 Label loop;
1049 bind(loop);
1050 movl(Address(tmp, (-os::vm_page_size())), size );
1051 subptr(tmp, os::vm_page_size());
1052 subl(size, os::vm_page_size());
1053 jcc(Assembler::greater, loop);
1054
1055 // Bang down shadow pages too.
1056 // At this point, (tmp-0) is the last address touched, so don't
1057 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1058 // was post-decremented.) Skip this address by starting at i=1, and
1059 // touch a few more pages below. N.B. It is important to touch all
1060 // the way down to and including i=StackShadowPages.
1061 for (int i = 1; i < StackShadowPages; i++) {
1062 // this could be any sized move but this is can be a debugging crumb
1063 // so the bigger the better.
1064 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1065 }
1066 }
1067
1068 int MacroAssembler::biased_locking_enter(Register lock_reg,
1069 Register obj_reg,
1070 Register swap_reg,
1071 Register tmp_reg,
1072 bool swap_reg_contains_mark,
1073 Label& done,
1074 Label* slow_case,
1075 BiasedLockingCounters* counters) {
1076 assert(UseBiasedLocking, "why call this otherwise?");
1077 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1078 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1079 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1080 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1081 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1082 Address saved_mark_addr(lock_reg, 0);
1083
1084 if (PrintBiasedLockingStatistics && counters == NULL) {
1085 counters = BiasedLocking::counters();
1086 }
1087 // Biased locking
1088 // See whether the lock is currently biased toward our thread and
1089 // whether the epoch is still valid
1090 // Note that the runtime guarantees sufficient alignment of JavaThread
1091 // pointers to allow age to be placed into low bits
1092 // First check to see whether biasing is even enabled for this object
1093 Label cas_label;
1094 int null_check_offset = -1;
1095 if (!swap_reg_contains_mark) {
1096 null_check_offset = offset();
1097 movptr(swap_reg, mark_addr);
1098 }
1099 movptr(tmp_reg, swap_reg);
1100 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1101 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1102 jcc(Assembler::notEqual, cas_label);
1103 // The bias pattern is present in the object's header. Need to check
1104 // whether the bias owner and the epoch are both still current.
1105 #ifndef _LP64
1106 // Note that because there is no current thread register on x86_32 we
1107 // need to store off the mark word we read out of the object to
1108 // avoid reloading it and needing to recheck invariants below. This
1109 // store is unfortunate but it makes the overall code shorter and
1110 // simpler.
1111 movptr(saved_mark_addr, swap_reg);
1112 #endif
1113 if (swap_reg_contains_mark) {
1114 null_check_offset = offset();
1115 }
1116 load_prototype_header(tmp_reg, obj_reg);
1117 #ifdef _LP64
1118 orptr(tmp_reg, r15_thread);
1119 xorptr(tmp_reg, swap_reg);
1120 Register header_reg = tmp_reg;
1121 #else
1122 xorptr(tmp_reg, swap_reg);
1123 get_thread(swap_reg);
1124 xorptr(swap_reg, tmp_reg);
1125 Register header_reg = swap_reg;
1126 #endif
1127 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1128 if (counters != NULL) {
1129 cond_inc32(Assembler::zero,
1130 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1131 }
1132 jcc(Assembler::equal, done);
1133
1134 Label try_revoke_bias;
1135 Label try_rebias;
1136
1137 // At this point we know that the header has the bias pattern and
1138 // that we are not the bias owner in the current epoch. We need to
1139 // figure out more details about the state of the header in order to
1140 // know what operations can be legally performed on the object's
1141 // header.
1142
1143 // If the low three bits in the xor result aren't clear, that means
1144 // the prototype header is no longer biased and we have to revoke
1145 // the bias on this object.
1146 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1147 jccb(Assembler::notZero, try_revoke_bias);
1148
1149 // Biasing is still enabled for this data type. See whether the
1150 // epoch of the current bias is still valid, meaning that the epoch
1151 // bits of the mark word are equal to the epoch bits of the
1152 // prototype header. (Note that the prototype header's epoch bits
1153 // only change at a safepoint.) If not, attempt to rebias the object
1154 // toward the current thread. Note that we must be absolutely sure
1155 // that the current epoch is invalid in order to do this because
1156 // otherwise the manipulations it performs on the mark word are
1157 // illegal.
1158 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1159 jccb(Assembler::notZero, try_rebias);
1160
1161 // The epoch of the current bias is still valid but we know nothing
1162 // about the owner; it might be set or it might be clear. Try to
1163 // acquire the bias of the object using an atomic operation. If this
1164 // fails we will go in to the runtime to revoke the object's bias.
1165 // Note that we first construct the presumed unbiased header so we
1166 // don't accidentally blow away another thread's valid bias.
1167 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1168 andptr(swap_reg,
1169 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1170 #ifdef _LP64
1171 movptr(tmp_reg, swap_reg);
1172 orptr(tmp_reg, r15_thread);
1173 #else
1174 get_thread(tmp_reg);
1175 orptr(tmp_reg, swap_reg);
1176 #endif
1177 if (os::is_MP()) {
1178 lock();
1179 }
1180 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1181 // If the biasing toward our thread failed, this means that
1182 // another thread succeeded in biasing it toward itself and we
1183 // need to revoke that bias. The revocation will occur in the
1184 // interpreter runtime in the slow case.
1185 if (counters != NULL) {
1186 cond_inc32(Assembler::zero,
1187 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1188 }
1189 if (slow_case != NULL) {
1190 jcc(Assembler::notZero, *slow_case);
1191 }
1192 jmp(done);
1193
1194 bind(try_rebias);
1195 // At this point we know the epoch has expired, meaning that the
1196 // current "bias owner", if any, is actually invalid. Under these
1197 // circumstances _only_, we are allowed to use the current header's
1198 // value as the comparison value when doing the cas to acquire the
1199 // bias in the current epoch. In other words, we allow transfer of
1200 // the bias from one thread to another directly in this situation.
1201 //
1202 // FIXME: due to a lack of registers we currently blow away the age
1203 // bits in this situation. Should attempt to preserve them.
1204 load_prototype_header(tmp_reg, obj_reg);
1205 #ifdef _LP64
1206 orptr(tmp_reg, r15_thread);
1207 #else
1208 get_thread(swap_reg);
1209 orptr(tmp_reg, swap_reg);
1210 movptr(swap_reg, saved_mark_addr);
1211 #endif
1212 if (os::is_MP()) {
1213 lock();
1214 }
1215 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1216 // If the biasing toward our thread failed, then another thread
1217 // succeeded in biasing it toward itself and we need to revoke that
1218 // bias. The revocation will occur in the runtime in the slow case.
1219 if (counters != NULL) {
1220 cond_inc32(Assembler::zero,
1221 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1222 }
1223 if (slow_case != NULL) {
1224 jcc(Assembler::notZero, *slow_case);
1225 }
1226 jmp(done);
1227
1228 bind(try_revoke_bias);
1229 // The prototype mark in the klass doesn't have the bias bit set any
1230 // more, indicating that objects of this data type are not supposed
1231 // to be biased any more. We are going to try to reset the mark of
1232 // this object to the prototype value and fall through to the
1233 // CAS-based locking scheme. Note that if our CAS fails, it means
1234 // that another thread raced us for the privilege of revoking the
1235 // bias of this particular object, so it's okay to continue in the
1236 // normal locking code.
1237 //
1238 // FIXME: due to a lack of registers we currently blow away the age
1239 // bits in this situation. Should attempt to preserve them.
1240 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1241 load_prototype_header(tmp_reg, obj_reg);
1242 if (os::is_MP()) {
1243 lock();
1244 }
1245 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1246 // Fall through to the normal CAS-based lock, because no matter what
1247 // the result of the above CAS, some thread must have succeeded in
1248 // removing the bias bit from the object's header.
1249 if (counters != NULL) {
1250 cond_inc32(Assembler::zero,
1251 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1252 }
1253
1254 bind(cas_label);
1255
1256 return null_check_offset;
1257 }
1258
1259 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1260 assert(UseBiasedLocking, "why call this otherwise?");
1261
1262 // Check for biased locking unlock case, which is a no-op
1263 // Note: we do not have to check the thread ID for two reasons.
1264 // First, the interpreter checks for IllegalMonitorStateException at
1265 // a higher level. Second, if the bias was revoked while we held the
1266 // lock, the object could not be rebiased toward another thread, so
1267 // the bias bit would be clear.
1268 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1269 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1270 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1271 jcc(Assembler::equal, done);
1272 }
1273
1274 #ifdef COMPILER2
1275
1276 #if INCLUDE_RTM_OPT
1277
1278 // Update rtm_counters based on abort status
1279 // input: abort_status
1280 // rtm_counters (RTMLockingCounters*)
1281 // flags are killed
1282 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1283
1284 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1285 if (PrintPreciseRTMLockingStatistics) {
1286 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1287 Label check_abort;
1288 testl(abort_status, (1<<i));
1289 jccb(Assembler::equal, check_abort);
1290 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1291 bind(check_abort);
1292 }
1293 }
1294 }
1295
1296 // Branch if (random & (count-1) != 0), count is 2^n
1297 // tmp, scr and flags are killed
1298 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1299 assert(tmp == rax, "");
1300 assert(scr == rdx, "");
1301 rdtsc(); // modifies EDX:EAX
1302 andptr(tmp, count-1);
1303 jccb(Assembler::notZero, brLabel);
1304 }
1305
1306 // Perform abort ratio calculation, set no_rtm bit if high ratio
1307 // input: rtm_counters_Reg (RTMLockingCounters* address)
1308 // tmpReg, rtm_counters_Reg and flags are killed
1309 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1310 Register rtm_counters_Reg,
1311 RTMLockingCounters* rtm_counters,
1312 Metadata* method_data) {
1313 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1314
1315 if (RTMLockingCalculationDelay > 0) {
1316 // Delay calculation
1317 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1318 testptr(tmpReg, tmpReg);
1319 jccb(Assembler::equal, L_done);
1320 }
1321 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1322 // Aborted transactions = abort_count * 100
1323 // All transactions = total_count * RTMTotalCountIncrRate
1324 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1325
1326 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1327 cmpptr(tmpReg, RTMAbortThreshold);
1328 jccb(Assembler::below, L_check_always_rtm2);
1329 imulptr(tmpReg, tmpReg, 100);
1330
1331 Register scrReg = rtm_counters_Reg;
1332 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1333 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1334 imulptr(scrReg, scrReg, RTMAbortRatio);
1335 cmpptr(tmpReg, scrReg);
1336 jccb(Assembler::below, L_check_always_rtm1);
1337 if (method_data != NULL) {
1338 // set rtm_state to "no rtm" in MDO
1339 mov_metadata(tmpReg, method_data);
1340 if (os::is_MP()) {
1341 lock();
1342 }
1343 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1344 }
1345 jmpb(L_done);
1346 bind(L_check_always_rtm1);
1347 // Reload RTMLockingCounters* address
1348 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1349 bind(L_check_always_rtm2);
1350 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1351 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1352 jccb(Assembler::below, L_done);
1353 if (method_data != NULL) {
1354 // set rtm_state to "always rtm" in MDO
1355 mov_metadata(tmpReg, method_data);
1356 if (os::is_MP()) {
1357 lock();
1358 }
1359 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1360 }
1361 bind(L_done);
1362 }
1363
1364 // Update counters and perform abort ratio calculation
1365 // input: abort_status_Reg
1366 // rtm_counters_Reg, flags are killed
1367 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1368 Register rtm_counters_Reg,
1369 RTMLockingCounters* rtm_counters,
1370 Metadata* method_data,
1371 bool profile_rtm) {
1372
1373 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1374 // update rtm counters based on rax value at abort
1375 // reads abort_status_Reg, updates flags
1376 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1377 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1378 if (profile_rtm) {
1379 // Save abort status because abort_status_Reg is used by following code.
1380 if (RTMRetryCount > 0) {
1381 push(abort_status_Reg);
1382 }
1383 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1384 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1385 // restore abort status
1386 if (RTMRetryCount > 0) {
1387 pop(abort_status_Reg);
1388 }
1389 }
1390 }
1391
1392 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1393 // inputs: retry_count_Reg
1394 // : abort_status_Reg
1395 // output: retry_count_Reg decremented by 1
1396 // flags are killed
1397 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1398 Label doneRetry;
1399 assert(abort_status_Reg == rax, "");
1400 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1401 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1402 // if reason is in 0x6 and retry count != 0 then retry
1403 andptr(abort_status_Reg, 0x6);
1404 jccb(Assembler::zero, doneRetry);
1405 testl(retry_count_Reg, retry_count_Reg);
1406 jccb(Assembler::zero, doneRetry);
1407 pause();
1408 decrementl(retry_count_Reg);
1409 jmp(retryLabel);
1410 bind(doneRetry);
1411 }
1412
1413 // Spin and retry if lock is busy,
1414 // inputs: box_Reg (monitor address)
1415 // : retry_count_Reg
1416 // output: retry_count_Reg decremented by 1
1417 // : clear z flag if retry count exceeded
1418 // tmp_Reg, scr_Reg, flags are killed
1419 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1420 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1421 Label SpinLoop, SpinExit, doneRetry;
1422 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1423
1424 testl(retry_count_Reg, retry_count_Reg);
1425 jccb(Assembler::zero, doneRetry);
1426 decrementl(retry_count_Reg);
1427 movptr(scr_Reg, RTMSpinLoopCount);
1428
1429 bind(SpinLoop);
1430 pause();
1431 decrementl(scr_Reg);
1432 jccb(Assembler::lessEqual, SpinExit);
1433 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1434 testptr(tmp_Reg, tmp_Reg);
1435 jccb(Assembler::notZero, SpinLoop);
1436
1437 bind(SpinExit);
1438 jmp(retryLabel);
1439 bind(doneRetry);
1440 incrementl(retry_count_Reg); // clear z flag
1441 }
1442
1443 // Use RTM for normal stack locks
1444 // Input: objReg (object to lock)
1445 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1446 Register retry_on_abort_count_Reg,
1447 RTMLockingCounters* stack_rtm_counters,
1448 Metadata* method_data, bool profile_rtm,
1449 Label& DONE_LABEL, Label& IsInflated) {
1450 assert(UseRTMForStackLocks, "why call this otherwise?");
1451 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1452 assert(tmpReg == rax, "");
1453 assert(scrReg == rdx, "");
1454 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1455
1456 if (RTMRetryCount > 0) {
1457 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1458 bind(L_rtm_retry);
1459 }
1460 movptr(tmpReg, Address(objReg, 0));
1461 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1462 jcc(Assembler::notZero, IsInflated);
1463
1464 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1465 Label L_noincrement;
1466 if (RTMTotalCountIncrRate > 1) {
1467 // tmpReg, scrReg and flags are killed
1468 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1469 }
1470 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1471 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1472 bind(L_noincrement);
1473 }
1474 xbegin(L_on_abort);
1475 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1476 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1477 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1478 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1479
1480 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1481 if (UseRTMXendForLockBusy) {
1482 xend();
1483 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1484 jmp(L_decrement_retry);
1485 }
1486 else {
1487 xabort(0);
1488 }
1489 bind(L_on_abort);
1490 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1491 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1492 }
1493 bind(L_decrement_retry);
1494 if (RTMRetryCount > 0) {
1495 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1496 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1497 }
1498 }
1499
1500 // Use RTM for inflating locks
1501 // inputs: objReg (object to lock)
1502 // boxReg (on-stack box address (displaced header location) - KILLED)
1503 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1504 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1505 Register scrReg, Register retry_on_busy_count_Reg,
1506 Register retry_on_abort_count_Reg,
1507 RTMLockingCounters* rtm_counters,
1508 Metadata* method_data, bool profile_rtm,
1509 Label& DONE_LABEL) {
1510 assert(UseRTMLocking, "why call this otherwise?");
1511 assert(tmpReg == rax, "");
1512 assert(scrReg == rdx, "");
1513 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1514 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1515
1516 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1517 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1518 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1519
1520 if (RTMRetryCount > 0) {
1521 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1522 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1523 bind(L_rtm_retry);
1524 }
1525 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1526 Label L_noincrement;
1527 if (RTMTotalCountIncrRate > 1) {
1528 // tmpReg, scrReg and flags are killed
1529 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1530 }
1531 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1532 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1533 bind(L_noincrement);
1534 }
1535 xbegin(L_on_abort);
1536 movptr(tmpReg, Address(objReg, 0));
1537 movptr(tmpReg, Address(tmpReg, owner_offset));
1538 testptr(tmpReg, tmpReg);
1539 jcc(Assembler::zero, DONE_LABEL);
1540 if (UseRTMXendForLockBusy) {
1541 xend();
1542 jmp(L_decrement_retry);
1543 }
1544 else {
1545 xabort(0);
1546 }
1547 bind(L_on_abort);
1548 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1549 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1550 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1551 }
1552 if (RTMRetryCount > 0) {
1553 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1554 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1555 }
1556
1557 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1558 testptr(tmpReg, tmpReg) ;
1559 jccb(Assembler::notZero, L_decrement_retry) ;
1560
1561 // Appears unlocked - try to swing _owner from null to non-null.
1562 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1563 #ifdef _LP64
1564 Register threadReg = r15_thread;
1565 #else
1566 get_thread(scrReg);
1567 Register threadReg = scrReg;
1568 #endif
1569 if (os::is_MP()) {
1570 lock();
1571 }
1572 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1573
1574 if (RTMRetryCount > 0) {
1575 // success done else retry
1576 jccb(Assembler::equal, DONE_LABEL) ;
1577 bind(L_decrement_retry);
1578 // Spin and retry if lock is busy.
1579 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1580 }
1581 else {
1582 bind(L_decrement_retry);
1583 }
1584 }
1585
1586 #endif // INCLUDE_RTM_OPT
1587
1588 // Fast_Lock and Fast_Unlock used by C2
1589
1590 // Because the transitions from emitted code to the runtime
1591 // monitorenter/exit helper stubs are so slow it's critical that
1592 // we inline both the stack-locking fast-path and the inflated fast path.
1593 //
1594 // See also: cmpFastLock and cmpFastUnlock.
1595 //
1596 // What follows is a specialized inline transliteration of the code
1597 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1598 // another option would be to emit TrySlowEnter and TrySlowExit methods
1599 // at startup-time. These methods would accept arguments as
1600 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1601 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1602 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1603 // In practice, however, the # of lock sites is bounded and is usually small.
1604 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1605 // if the processor uses simple bimodal branch predictors keyed by EIP
1606 // Since the helper routines would be called from multiple synchronization
1607 // sites.
1608 //
1609 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1610 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1611 // to those specialized methods. That'd give us a mostly platform-independent
1612 // implementation that the JITs could optimize and inline at their pleasure.
1613 // Done correctly, the only time we'd need to cross to native could would be
1614 // to park() or unpark() threads. We'd also need a few more unsafe operators
1615 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1616 // (b) explicit barriers or fence operations.
1617 //
1618 // TODO:
1619 //
1620 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1621 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1622 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1623 // the lock operators would typically be faster than reifying Self.
1624 //
1625 // * Ideally I'd define the primitives as:
1626 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1627 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1628 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1629 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1630 // Furthermore the register assignments are overconstrained, possibly resulting in
1631 // sub-optimal code near the synchronization site.
1632 //
1633 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1634 // Alternately, use a better sp-proximity test.
1635 //
1636 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1637 // Either one is sufficient to uniquely identify a thread.
1638 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1639 //
1640 // * Intrinsify notify() and notifyAll() for the common cases where the
1641 // object is locked by the calling thread but the waitlist is empty.
1642 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1643 //
1644 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1645 // But beware of excessive branch density on AMD Opterons.
1646 //
1647 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1648 // or failure of the fast-path. If the fast-path fails then we pass
1649 // control to the slow-path, typically in C. In Fast_Lock and
1650 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1651 // will emit a conditional branch immediately after the node.
1652 // So we have branches to branches and lots of ICC.ZF games.
1653 // Instead, it might be better to have C2 pass a "FailureLabel"
1654 // into Fast_Lock and Fast_Unlock. In the case of success, control
1655 // will drop through the node. ICC.ZF is undefined at exit.
1656 // In the case of failure, the node will branch directly to the
1657 // FailureLabel
1658
1659
1660 // obj: object to lock
1661 // box: on-stack box address (displaced header location) - KILLED
1662 // rax,: tmp -- KILLED
1663 // scr: tmp -- KILLED
1664 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1665 Register scrReg, Register cx1Reg, Register cx2Reg,
1666 BiasedLockingCounters* counters,
1667 RTMLockingCounters* rtm_counters,
1668 RTMLockingCounters* stack_rtm_counters,
1669 Metadata* method_data,
1670 bool use_rtm, bool profile_rtm) {
1671 // Ensure the register assignents are disjoint
1672 assert(tmpReg == rax, "");
1673
1674 if (use_rtm) {
1675 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1676 } else {
1677 assert(cx1Reg == noreg, "");
1678 assert(cx2Reg == noreg, "");
1679 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1680 }
1681
1682 if (counters != NULL) {
1683 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1684 }
1685 if (EmitSync & 1) {
1686 // set box->dhw = markOopDesc::unused_mark()
1687 // Force all sync thru slow-path: slow_enter() and slow_exit()
1688 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1689 cmpptr (rsp, (int32_t)NULL_WORD);
1690 } else {
1691 // Possible cases that we'll encounter in fast_lock
1692 // ------------------------------------------------
1693 // * Inflated
1694 // -- unlocked
1695 // -- Locked
1696 // = by self
1697 // = by other
1698 // * biased
1699 // -- by Self
1700 // -- by other
1701 // * neutral
1702 // * stack-locked
1703 // -- by self
1704 // = sp-proximity test hits
1705 // = sp-proximity test generates false-negative
1706 // -- by other
1707 //
1708
1709 Label IsInflated, DONE_LABEL;
1710
1711 // it's stack-locked, biased or neutral
1712 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1713 // order to reduce the number of conditional branches in the most common cases.
1714 // Beware -- there's a subtle invariant that fetch of the markword
1715 // at [FETCH], below, will never observe a biased encoding (*101b).
1716 // If this invariant is not held we risk exclusion (safety) failure.
1717 if (UseBiasedLocking && !UseOptoBiasInlining) {
1718 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1719 }
1720
1721 #if INCLUDE_RTM_OPT
1722 if (UseRTMForStackLocks && use_rtm) {
1723 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1724 stack_rtm_counters, method_data, profile_rtm,
1725 DONE_LABEL, IsInflated);
1726 }
1727 #endif // INCLUDE_RTM_OPT
1728
1729 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1730 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1731 jccb(Assembler::notZero, IsInflated);
1732
1733 // Attempt stack-locking ...
1734 orptr (tmpReg, markOopDesc::unlocked_value);
1735 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1736 if (os::is_MP()) {
1737 lock();
1738 }
1739 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1740 if (counters != NULL) {
1741 cond_inc32(Assembler::equal,
1742 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1743 }
1744 jcc(Assembler::equal, DONE_LABEL); // Success
1745
1746 // Recursive locking.
1747 // The object is stack-locked: markword contains stack pointer to BasicLock.
1748 // Locked by current thread if difference with current SP is less than one page.
1749 subptr(tmpReg, rsp);
1750 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1751 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1752 movptr(Address(boxReg, 0), tmpReg);
1753 if (counters != NULL) {
1754 cond_inc32(Assembler::equal,
1755 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1756 }
1757 jmp(DONE_LABEL);
1758
1759 bind(IsInflated);
1760 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1761
1762 #if INCLUDE_RTM_OPT
1763 // Use the same RTM locking code in 32- and 64-bit VM.
1764 if (use_rtm) {
1765 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1766 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1767 } else {
1768 #endif // INCLUDE_RTM_OPT
1769
1770 #ifndef _LP64
1771 // The object is inflated.
1772
1773 // boxReg refers to the on-stack BasicLock in the current frame.
1774 // We'd like to write:
1775 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1776 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1777 // additional latency as we have another ST in the store buffer that must drain.
1778
1779 if (EmitSync & 8192) {
1780 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1781 get_thread (scrReg);
1782 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1783 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1784 if (os::is_MP()) {
1785 lock();
1786 }
1787 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1788 } else
1789 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1790 // register juggle because we need tmpReg for cmpxchgptr below
1791 movptr(scrReg, boxReg);
1792 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1793
1794 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1795 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1796 // prefetchw [eax + Offset(_owner)-2]
1797 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1798 }
1799
1800 if ((EmitSync & 64) == 0) {
1801 // Optimistic form: consider XORL tmpReg,tmpReg
1802 movptr(tmpReg, NULL_WORD);
1803 } else {
1804 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1805 // Test-And-CAS instead of CAS
1806 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1807 testptr(tmpReg, tmpReg); // Locked ?
1808 jccb (Assembler::notZero, DONE_LABEL);
1809 }
1810
1811 // Appears unlocked - try to swing _owner from null to non-null.
1812 // Ideally, I'd manifest "Self" with get_thread and then attempt
1813 // to CAS the register containing Self into m->Owner.
1814 // But we don't have enough registers, so instead we can either try to CAS
1815 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1816 // we later store "Self" into m->Owner. Transiently storing a stack address
1817 // (rsp or the address of the box) into m->owner is harmless.
1818 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1819 if (os::is_MP()) {
1820 lock();
1821 }
1822 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1823 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1824 // If we weren't able to swing _owner from NULL to the BasicLock
1825 // then take the slow path.
1826 jccb (Assembler::notZero, DONE_LABEL);
1827 // update _owner from BasicLock to thread
1828 get_thread (scrReg); // beware: clobbers ICCs
1829 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1830 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1831
1832 // If the CAS fails we can either retry or pass control to the slow-path.
1833 // We use the latter tactic.
1834 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1835 // If the CAS was successful ...
1836 // Self has acquired the lock
1837 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1838 // Intentional fall-through into DONE_LABEL ...
1839 } else {
1840 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1841 movptr(boxReg, tmpReg);
1842
1843 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1844 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1845 // prefetchw [eax + Offset(_owner)-2]
1846 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1847 }
1848
1849 if ((EmitSync & 64) == 0) {
1850 // Optimistic form
1851 xorptr (tmpReg, tmpReg);
1852 } else {
1853 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1854 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1855 testptr(tmpReg, tmpReg); // Locked ?
1856 jccb (Assembler::notZero, DONE_LABEL);
1857 }
1858
1859 // Appears unlocked - try to swing _owner from null to non-null.
1860 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1861 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1862 get_thread (scrReg);
1863 if (os::is_MP()) {
1864 lock();
1865 }
1866 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1867
1868 // If the CAS fails we can either retry or pass control to the slow-path.
1869 // We use the latter tactic.
1870 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1871 // If the CAS was successful ...
1872 // Self has acquired the lock
1873 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1874 // Intentional fall-through into DONE_LABEL ...
1875 }
1876 #else // _LP64
1877 // It's inflated
1878 movq(scrReg, tmpReg);
1879 xorq(tmpReg, tmpReg);
1880
1881 if (os::is_MP()) {
1882 lock();
1883 }
1884 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1885 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1886 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1887 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1888 // Intentional fall-through into DONE_LABEL ...
1889 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1890 #endif // _LP64
1891 #if INCLUDE_RTM_OPT
1892 } // use_rtm()
1893 #endif
1894 // DONE_LABEL is a hot target - we'd really like to place it at the
1895 // start of cache line by padding with NOPs.
1896 // See the AMD and Intel software optimization manuals for the
1897 // most efficient "long" NOP encodings.
1898 // Unfortunately none of our alignment mechanisms suffice.
1899 bind(DONE_LABEL);
1900
1901 // At DONE_LABEL the icc ZFlag is set as follows ...
1902 // Fast_Unlock uses the same protocol.
1903 // ZFlag == 1 -> Success
1904 // ZFlag == 0 -> Failure - force control through the slow-path
1905 }
1906 }
1907
1908 // obj: object to unlock
1909 // box: box address (displaced header location), killed. Must be EAX.
1910 // tmp: killed, cannot be obj nor box.
1911 //
1912 // Some commentary on balanced locking:
1913 //
1914 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1915 // Methods that don't have provably balanced locking are forced to run in the
1916 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1917 // The interpreter provides two properties:
1918 // I1: At return-time the interpreter automatically and quietly unlocks any
1919 // objects acquired the current activation (frame). Recall that the
1920 // interpreter maintains an on-stack list of locks currently held by
1921 // a frame.
1922 // I2: If a method attempts to unlock an object that is not held by the
1923 // the frame the interpreter throws IMSX.
1924 //
1925 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1926 // B() doesn't have provably balanced locking so it runs in the interpreter.
1927 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1928 // is still locked by A().
1929 //
1930 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1931 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1932 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1933 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1934 // Arguably given that the spec legislates the JNI case as undefined our implementation
1935 // could reasonably *avoid* checking owner in Fast_Unlock().
1936 // In the interest of performance we elide m->Owner==Self check in unlock.
1937 // A perfectly viable alternative is to elide the owner check except when
1938 // Xcheck:jni is enabled.
1939
1940 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1941 assert(boxReg == rax, "");
1942 assert_different_registers(objReg, boxReg, tmpReg);
1943
1944 if (EmitSync & 4) {
1945 // Disable - inhibit all inlining. Force control through the slow-path
1946 cmpptr (rsp, 0);
1947 } else {
1948 Label DONE_LABEL, Stacked, CheckSucc;
1949
1950 // Critically, the biased locking test must have precedence over
1951 // and appear before the (box->dhw == 0) recursive stack-lock test.
1952 if (UseBiasedLocking && !UseOptoBiasInlining) {
1953 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1954 }
1955
1956 #if INCLUDE_RTM_OPT
1957 if (UseRTMForStackLocks && use_rtm) {
1958 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1959 Label L_regular_unlock;
1960 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1961 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1962 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1963 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1964 xend(); // otherwise end...
1965 jmp(DONE_LABEL); // ... and we're done
1966 bind(L_regular_unlock);
1967 }
1968 #endif
1969
1970 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1971 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1972 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
1973 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1974 jccb (Assembler::zero, Stacked);
1975
1976 // It's inflated.
1977 #if INCLUDE_RTM_OPT
1978 if (use_rtm) {
1979 Label L_regular_inflated_unlock;
1980 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1981 movptr(boxReg, Address(tmpReg, owner_offset));
1982 testptr(boxReg, boxReg);
1983 jccb(Assembler::notZero, L_regular_inflated_unlock);
1984 xend();
1985 jmpb(DONE_LABEL);
1986 bind(L_regular_inflated_unlock);
1987 }
1988 #endif
1989
1990 // Despite our balanced locking property we still check that m->_owner == Self
1991 // as java routines or native JNI code called by this thread might
1992 // have released the lock.
1993 // Refer to the comments in synchronizer.cpp for how we might encode extra
1994 // state in _succ so we can avoid fetching EntryList|cxq.
1995 //
1996 // I'd like to add more cases in fast_lock() and fast_unlock() --
1997 // such as recursive enter and exit -- but we have to be wary of
1998 // I$ bloat, T$ effects and BP$ effects.
1999 //
2000 // If there's no contention try a 1-0 exit. That is, exit without
2001 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2002 // we detect and recover from the race that the 1-0 exit admits.
2003 //
2004 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2005 // before it STs null into _owner, releasing the lock. Updates
2006 // to data protected by the critical section must be visible before
2007 // we drop the lock (and thus before any other thread could acquire
2008 // the lock and observe the fields protected by the lock).
2009 // IA32's memory-model is SPO, so STs are ordered with respect to
2010 // each other and there's no need for an explicit barrier (fence).
2011 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2012 #ifndef _LP64
2013 get_thread (boxReg);
2014 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2015 // prefetchw [ebx + Offset(_owner)-2]
2016 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2017 }
2018
2019 // Note that we could employ various encoding schemes to reduce
2020 // the number of loads below (currently 4) to just 2 or 3.
2021 // Refer to the comments in synchronizer.cpp.
2022 // In practice the chain of fetches doesn't seem to impact performance, however.
2023 xorptr(boxReg, boxReg);
2024 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2025 // Attempt to reduce branch density - AMD's branch predictor.
2026 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2027 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2028 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2029 jccb (Assembler::notZero, DONE_LABEL);
2030 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2031 jmpb (DONE_LABEL);
2032 } else {
2033 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2034 jccb (Assembler::notZero, DONE_LABEL);
2035 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2036 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2037 jccb (Assembler::notZero, CheckSucc);
2038 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2039 jmpb (DONE_LABEL);
2040 }
2041
2042 // The Following code fragment (EmitSync & 65536) improves the performance of
2043 // contended applications and contended synchronization microbenchmarks.
2044 // Unfortunately the emission of the code - even though not executed - causes regressions
2045 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2046 // with an equal number of never-executed NOPs results in the same regression.
2047 // We leave it off by default.
2048
2049 if ((EmitSync & 65536) != 0) {
2050 Label LSuccess, LGoSlowPath ;
2051
2052 bind (CheckSucc);
2053
2054 // Optional pre-test ... it's safe to elide this
2055 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2056 jccb(Assembler::zero, LGoSlowPath);
2057
2058 // We have a classic Dekker-style idiom:
2059 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2060 // There are a number of ways to implement the barrier:
2061 // (1) lock:andl &m->_owner, 0
2062 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2063 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2064 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2065 // (2) If supported, an explicit MFENCE is appealing.
2066 // In older IA32 processors MFENCE is slower than lock:add or xchg
2067 // particularly if the write-buffer is full as might be the case if
2068 // if stores closely precede the fence or fence-equivalent instruction.
2069 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2070 // as the situation has changed with Nehalem and Shanghai.
2071 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2072 // The $lines underlying the top-of-stack should be in M-state.
2073 // The locked add instruction is serializing, of course.
2074 // (4) Use xchg, which is serializing
2075 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2076 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2077 // The integer condition codes will tell us if succ was 0.
2078 // Since _succ and _owner should reside in the same $line and
2079 // we just stored into _owner, it's likely that the $line
2080 // remains in M-state for the lock:orl.
2081 //
2082 // We currently use (3), although it's likely that switching to (2)
2083 // is correct for the future.
2084
2085 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2086 if (os::is_MP()) {
2087 lock(); addptr(Address(rsp, 0), 0);
2088 }
2089 // Ratify _succ remains non-null
2090 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2091 jccb (Assembler::notZero, LSuccess);
2092
2093 xorptr(boxReg, boxReg); // box is really EAX
2094 if (os::is_MP()) { lock(); }
2095 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2096 // There's no successor so we tried to regrab the lock with the
2097 // placeholder value. If that didn't work, then another thread
2098 // grabbed the lock so we're done (and exit was a success).
2099 jccb (Assembler::notEqual, LSuccess);
2100 // Since we're low on registers we installed rsp as a placeholding in _owner.
2101 // Now install Self over rsp. This is safe as we're transitioning from
2102 // non-null to non=null
2103 get_thread (boxReg);
2104 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2105 // Intentional fall-through into LGoSlowPath ...
2106
2107 bind (LGoSlowPath);
2108 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2109 jmpb (DONE_LABEL);
2110
2111 bind (LSuccess);
2112 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2113 jmpb (DONE_LABEL);
2114 }
2115
2116 bind (Stacked);
2117 // It's not inflated and it's not recursively stack-locked and it's not biased.
2118 // It must be stack-locked.
2119 // Try to reset the header to displaced header.
2120 // The "box" value on the stack is stable, so we can reload
2121 // and be assured we observe the same value as above.
2122 movptr(tmpReg, Address(boxReg, 0));
2123 if (os::is_MP()) {
2124 lock();
2125 }
2126 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2127 // Intention fall-thru into DONE_LABEL
2128
2129 // DONE_LABEL is a hot target - we'd really like to place it at the
2130 // start of cache line by padding with NOPs.
2131 // See the AMD and Intel software optimization manuals for the
2132 // most efficient "long" NOP encodings.
2133 // Unfortunately none of our alignment mechanisms suffice.
2134 if ((EmitSync & 65536) == 0) {
2135 bind (CheckSucc);
2136 }
2137 #else // _LP64
2138 // It's inflated
2139 if (EmitSync & 1024) {
2140 // Emit code to check that _owner == Self
2141 // We could fold the _owner test into subsequent code more efficiently
2142 // than using a stand-alone check, but since _owner checking is off by
2143 // default we don't bother. We also might consider predicating the
2144 // _owner==Self check on Xcheck:jni or running on a debug build.
2145 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2146 xorptr(boxReg, r15_thread);
2147 } else {
2148 xorptr(boxReg, boxReg);
2149 }
2150 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2151 jccb (Assembler::notZero, DONE_LABEL);
2152 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2153 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2154 jccb (Assembler::notZero, CheckSucc);
2155 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2156 jmpb (DONE_LABEL);
2157
2158 if ((EmitSync & 65536) == 0) {
2159 // Try to avoid passing control into the slow_path ...
2160 Label LSuccess, LGoSlowPath ;
2161 bind (CheckSucc);
2162
2163 // The following optional optimization can be elided if necessary
2164 // Effectively: if (succ == null) goto SlowPath
2165 // The code reduces the window for a race, however,
2166 // and thus benefits performance.
2167 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2168 jccb (Assembler::zero, LGoSlowPath);
2169
2170 if ((EmitSync & 16) && os::is_MP()) {
2171 orptr(boxReg, boxReg);
2172 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 } else {
2174 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2175 if (os::is_MP()) {
2176 // Memory barrier/fence
2177 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2178 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2179 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2180 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2181 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2182 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2183 lock(); addl(Address(rsp, 0), 0);
2184 }
2185 }
2186 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2187 jccb (Assembler::notZero, LSuccess);
2188
2189 // Rare inopportune interleaving - race.
2190 // The successor vanished in the small window above.
2191 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2192 // We need to ensure progress and succession.
2193 // Try to reacquire the lock.
2194 // If that fails then the new owner is responsible for succession and this
2195 // thread needs to take no further action and can exit via the fast path (success).
2196 // If the re-acquire succeeds then pass control into the slow path.
2197 // As implemented, this latter mode is horrible because we generated more
2198 // coherence traffic on the lock *and* artifically extended the critical section
2199 // length while by virtue of passing control into the slow path.
2200
2201 // box is really RAX -- the following CMPXCHG depends on that binding
2202 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2203 movptr(boxReg, (int32_t)NULL_WORD);
2204 if (os::is_MP()) { lock(); }
2205 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2206 // There's no successor so we tried to regrab the lock.
2207 // If that didn't work, then another thread grabbed the
2208 // lock so we're done (and exit was a success).
2209 jccb (Assembler::notEqual, LSuccess);
2210 // Intentional fall-through into slow-path
2211
2212 bind (LGoSlowPath);
2213 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2214 jmpb (DONE_LABEL);
2215
2216 bind (LSuccess);
2217 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2218 jmpb (DONE_LABEL);
2219 }
2220
2221 bind (Stacked);
2222 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2223 if (os::is_MP()) { lock(); }
2224 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2225
2226 if (EmitSync & 65536) {
2227 bind (CheckSucc);
2228 }
2229 #endif
2230 bind(DONE_LABEL);
2231 }
2232 }
2233 #endif // COMPILER2
2234
2235 void MacroAssembler::c2bool(Register x) {
2236 // implements x == 0 ? 0 : 1
2237 // note: must only look at least-significant byte of x
2238 // since C-style booleans are stored in one byte
2239 // only! (was bug)
2240 andl(x, 0xFF);
2241 setb(Assembler::notZero, x);
2242 }
2243
2244 // Wouldn't need if AddressLiteral version had new name
2245 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2246 Assembler::call(L, rtype);
2247 }
2248
2249 void MacroAssembler::call(Register entry) {
2250 Assembler::call(entry);
2251 }
2252
2253 void MacroAssembler::call(AddressLiteral entry) {
2254 if (reachable(entry)) {
2255 Assembler::call_literal(entry.target(), entry.rspec());
2256 } else {
2257 lea(rscratch1, entry);
2258 Assembler::call(rscratch1);
2259 }
2260 }
2261
2262 void MacroAssembler::ic_call(address entry) {
2263 RelocationHolder rh = virtual_call_Relocation::spec(pc());
2264 movptr(rax, (intptr_t)Universe::non_oop_word());
2265 call(AddressLiteral(entry, rh));
2266 }
2267
2268 // Implementation of call_VM versions
2269
2270 void MacroAssembler::call_VM(Register oop_result,
2271 address entry_point,
2272 bool check_exceptions) {
2273 Label C, E;
2274 call(C, relocInfo::none);
2275 jmp(E);
2276
2277 bind(C);
2278 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2279 ret(0);
2280
2281 bind(E);
2282 }
2283
2284 void MacroAssembler::call_VM(Register oop_result,
2285 address entry_point,
2286 Register arg_1,
2287 bool check_exceptions) {
2288 Label C, E;
2289 call(C, relocInfo::none);
2290 jmp(E);
2291
2292 bind(C);
2293 pass_arg1(this, arg_1);
2294 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2295 ret(0);
2296
2297 bind(E);
2298 }
2299
2300 void MacroAssembler::call_VM(Register oop_result,
2301 address entry_point,
2302 Register arg_1,
2303 Register arg_2,
2304 bool check_exceptions) {
2305 Label C, E;
2306 call(C, relocInfo::none);
2307 jmp(E);
2308
2309 bind(C);
2310
2311 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2312
2313 pass_arg2(this, arg_2);
2314 pass_arg1(this, arg_1);
2315 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2316 ret(0);
2317
2318 bind(E);
2319 }
2320
2321 void MacroAssembler::call_VM(Register oop_result,
2322 address entry_point,
2323 Register arg_1,
2324 Register arg_2,
2325 Register arg_3,
2326 bool check_exceptions) {
2327 Label C, E;
2328 call(C, relocInfo::none);
2329 jmp(E);
2330
2331 bind(C);
2332
2333 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2334 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2335 pass_arg3(this, arg_3);
2336
2337 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2338 pass_arg2(this, arg_2);
2339
2340 pass_arg1(this, arg_1);
2341 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2342 ret(0);
2343
2344 bind(E);
2345 }
2346
2347 void MacroAssembler::call_VM(Register oop_result,
2348 Register last_java_sp,
2349 address entry_point,
2350 int number_of_arguments,
2351 bool check_exceptions) {
2352 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2353 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2354 }
2355
2356 void MacroAssembler::call_VM(Register oop_result,
2357 Register last_java_sp,
2358 address entry_point,
2359 Register arg_1,
2360 bool check_exceptions) {
2361 pass_arg1(this, arg_1);
2362 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2363 }
2364
2365 void MacroAssembler::call_VM(Register oop_result,
2366 Register last_java_sp,
2367 address entry_point,
2368 Register arg_1,
2369 Register arg_2,
2370 bool check_exceptions) {
2371
2372 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2373 pass_arg2(this, arg_2);
2374 pass_arg1(this, arg_1);
2375 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2376 }
2377
2378 void MacroAssembler::call_VM(Register oop_result,
2379 Register last_java_sp,
2380 address entry_point,
2381 Register arg_1,
2382 Register arg_2,
2383 Register arg_3,
2384 bool check_exceptions) {
2385 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2386 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2387 pass_arg3(this, arg_3);
2388 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2389 pass_arg2(this, arg_2);
2390 pass_arg1(this, arg_1);
2391 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2392 }
2393
2394 void MacroAssembler::super_call_VM(Register oop_result,
2395 Register last_java_sp,
2396 address entry_point,
2397 int number_of_arguments,
2398 bool check_exceptions) {
2399 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2400 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2401 }
2402
2403 void MacroAssembler::super_call_VM(Register oop_result,
2404 Register last_java_sp,
2405 address entry_point,
2406 Register arg_1,
2407 bool check_exceptions) {
2408 pass_arg1(this, arg_1);
2409 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2410 }
2411
2412 void MacroAssembler::super_call_VM(Register oop_result,
2413 Register last_java_sp,
2414 address entry_point,
2415 Register arg_1,
2416 Register arg_2,
2417 bool check_exceptions) {
2418
2419 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2420 pass_arg2(this, arg_2);
2421 pass_arg1(this, arg_1);
2422 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2423 }
2424
2425 void MacroAssembler::super_call_VM(Register oop_result,
2426 Register last_java_sp,
2427 address entry_point,
2428 Register arg_1,
2429 Register arg_2,
2430 Register arg_3,
2431 bool check_exceptions) {
2432 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2433 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2434 pass_arg3(this, arg_3);
2435 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2436 pass_arg2(this, arg_2);
2437 pass_arg1(this, arg_1);
2438 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2439 }
2440
2441 void MacroAssembler::call_VM_base(Register oop_result,
2442 Register java_thread,
2443 Register last_java_sp,
2444 address entry_point,
2445 int number_of_arguments,
2446 bool check_exceptions) {
2447 // determine java_thread register
2448 if (!java_thread->is_valid()) {
2449 #ifdef _LP64
2450 java_thread = r15_thread;
2451 #else
2452 java_thread = rdi;
2453 get_thread(java_thread);
2454 #endif // LP64
2455 }
2456 // determine last_java_sp register
2457 if (!last_java_sp->is_valid()) {
2458 last_java_sp = rsp;
2459 }
2460 // debugging support
2461 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2462 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2463 #ifdef ASSERT
2464 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2465 // r12 is the heapbase.
2466 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2467 #endif // ASSERT
2468
2469 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2470 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2471
2472 // push java thread (becomes first argument of C function)
2473
2474 NOT_LP64(push(java_thread); number_of_arguments++);
2475 LP64_ONLY(mov(c_rarg0, r15_thread));
2476
2477 // set last Java frame before call
2478 assert(last_java_sp != rbp, "can't use ebp/rbp");
2479
2480 // Only interpreter should have to set fp
2481 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2482
2483 // do the call, remove parameters
2484 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2485
2486 // restore the thread (cannot use the pushed argument since arguments
2487 // may be overwritten by C code generated by an optimizing compiler);
2488 // however can use the register value directly if it is callee saved.
2489 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2490 // rdi & rsi (also r15) are callee saved -> nothing to do
2491 #ifdef ASSERT
2492 guarantee(java_thread != rax, "change this code");
2493 push(rax);
2494 { Label L;
2495 get_thread(rax);
2496 cmpptr(java_thread, rax);
2497 jcc(Assembler::equal, L);
2498 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2499 bind(L);
2500 }
2501 pop(rax);
2502 #endif
2503 } else {
2504 get_thread(java_thread);
2505 }
2506 // reset last Java frame
2507 // Only interpreter should have to clear fp
2508 reset_last_Java_frame(java_thread, true, false);
2509
2510 #ifndef CC_INTERP
2511 // C++ interp handles this in the interpreter
2512 check_and_handle_popframe(java_thread);
2513 check_and_handle_earlyret(java_thread);
2514 #endif /* CC_INTERP */
2515
2516 if (check_exceptions) {
2517 // check for pending exceptions (java_thread is set upon return)
2518 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2519 #ifndef _LP64
2520 jump_cc(Assembler::notEqual,
2521 RuntimeAddress(StubRoutines::forward_exception_entry()));
2522 #else
2523 // This used to conditionally jump to forward_exception however it is
2524 // possible if we relocate that the branch will not reach. So we must jump
2525 // around so we can always reach
2526
2527 Label ok;
2528 jcc(Assembler::equal, ok);
2529 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2530 bind(ok);
2531 #endif // LP64
2532 }
2533
2534 // get oop result if there is one and reset the value in the thread
2535 if (oop_result->is_valid()) {
2536 get_vm_result(oop_result, java_thread);
2537 }
2538 }
2539
2540 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2541
2542 // Calculate the value for last_Java_sp
2543 // somewhat subtle. call_VM does an intermediate call
2544 // which places a return address on the stack just under the
2545 // stack pointer as the user finsihed with it. This allows
2546 // use to retrieve last_Java_pc from last_Java_sp[-1].
2547 // On 32bit we then have to push additional args on the stack to accomplish
2548 // the actual requested call. On 64bit call_VM only can use register args
2549 // so the only extra space is the return address that call_VM created.
2550 // This hopefully explains the calculations here.
2551
2552 #ifdef _LP64
2553 // We've pushed one address, correct last_Java_sp
2554 lea(rax, Address(rsp, wordSize));
2555 #else
2556 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2557 #endif // LP64
2558
2559 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2560
2561 }
2562
2563 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2564 call_VM_leaf_base(entry_point, number_of_arguments);
2565 }
2566
2567 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2568 pass_arg0(this, arg_0);
2569 call_VM_leaf(entry_point, 1);
2570 }
2571
2572 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2573
2574 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2575 pass_arg1(this, arg_1);
2576 pass_arg0(this, arg_0);
2577 call_VM_leaf(entry_point, 2);
2578 }
2579
2580 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2581 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2582 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2583 pass_arg2(this, arg_2);
2584 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2585 pass_arg1(this, arg_1);
2586 pass_arg0(this, arg_0);
2587 call_VM_leaf(entry_point, 3);
2588 }
2589
2590 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2591 pass_arg0(this, arg_0);
2592 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2593 }
2594
2595 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2596
2597 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2598 pass_arg1(this, arg_1);
2599 pass_arg0(this, arg_0);
2600 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2601 }
2602
2603 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2604 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2605 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2606 pass_arg2(this, arg_2);
2607 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2608 pass_arg1(this, arg_1);
2609 pass_arg0(this, arg_0);
2610 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2611 }
2612
2613 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2614 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2615 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2616 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2617 pass_arg3(this, arg_3);
2618 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2619 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2620 pass_arg2(this, arg_2);
2621 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2622 pass_arg1(this, arg_1);
2623 pass_arg0(this, arg_0);
2624 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2625 }
2626
2627 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2628 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2629 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2630 verify_oop(oop_result, "broken oop in call_VM_base");
2631 }
2632
2633 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2634 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2635 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2636 }
2637
2638 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2639 }
2640
2641 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2642 }
2643
2644 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2645 if (reachable(src1)) {
2646 cmpl(as_Address(src1), imm);
2647 } else {
2648 lea(rscratch1, src1);
2649 cmpl(Address(rscratch1, 0), imm);
2650 }
2651 }
2652
2653 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2654 assert(!src2.is_lval(), "use cmpptr");
2655 if (reachable(src2)) {
2656 cmpl(src1, as_Address(src2));
2657 } else {
2658 lea(rscratch1, src2);
2659 cmpl(src1, Address(rscratch1, 0));
2660 }
2661 }
2662
2663 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2664 Assembler::cmpl(src1, imm);
2665 }
2666
2667 void MacroAssembler::cmp32(Register src1, Address src2) {
2668 Assembler::cmpl(src1, src2);
2669 }
2670
2671 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2672 ucomisd(opr1, opr2);
2673
2674 Label L;
2675 if (unordered_is_less) {
2676 movl(dst, -1);
2677 jcc(Assembler::parity, L);
2678 jcc(Assembler::below , L);
2679 movl(dst, 0);
2680 jcc(Assembler::equal , L);
2681 increment(dst);
2682 } else { // unordered is greater
2683 movl(dst, 1);
2684 jcc(Assembler::parity, L);
2685 jcc(Assembler::above , L);
2686 movl(dst, 0);
2687 jcc(Assembler::equal , L);
2688 decrementl(dst);
2689 }
2690 bind(L);
2691 }
2692
2693 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2694 ucomiss(opr1, opr2);
2695
2696 Label L;
2697 if (unordered_is_less) {
2698 movl(dst, -1);
2699 jcc(Assembler::parity, L);
2700 jcc(Assembler::below , L);
2701 movl(dst, 0);
2702 jcc(Assembler::equal , L);
2703 increment(dst);
2704 } else { // unordered is greater
2705 movl(dst, 1);
2706 jcc(Assembler::parity, L);
2707 jcc(Assembler::above , L);
2708 movl(dst, 0);
2709 jcc(Assembler::equal , L);
2710 decrementl(dst);
2711 }
2712 bind(L);
2713 }
2714
2715
2716 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2717 if (reachable(src1)) {
2718 cmpb(as_Address(src1), imm);
2719 } else {
2720 lea(rscratch1, src1);
2721 cmpb(Address(rscratch1, 0), imm);
2722 }
2723 }
2724
2725 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2726 #ifdef _LP64
2727 if (src2.is_lval()) {
2728 movptr(rscratch1, src2);
2729 Assembler::cmpq(src1, rscratch1);
2730 } else if (reachable(src2)) {
2731 cmpq(src1, as_Address(src2));
2732 } else {
2733 lea(rscratch1, src2);
2734 Assembler::cmpq(src1, Address(rscratch1, 0));
2735 }
2736 #else
2737 if (src2.is_lval()) {
2738 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2739 } else {
2740 cmpl(src1, as_Address(src2));
2741 }
2742 #endif // _LP64
2743 }
2744
2745 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2746 assert(src2.is_lval(), "not a mem-mem compare");
2747 #ifdef _LP64
2748 // moves src2's literal address
2749 movptr(rscratch1, src2);
2750 Assembler::cmpq(src1, rscratch1);
2751 #else
2752 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2753 #endif // _LP64
2754 }
2755
2756 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2757 if (reachable(adr)) {
2758 if (os::is_MP())
2759 lock();
2760 cmpxchgptr(reg, as_Address(adr));
2761 } else {
2762 lea(rscratch1, adr);
2763 if (os::is_MP())
2764 lock();
2765 cmpxchgptr(reg, Address(rscratch1, 0));
2766 }
2767 }
2768
2769 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2770 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2771 }
2772
2773 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2774 if (reachable(src)) {
2775 Assembler::comisd(dst, as_Address(src));
2776 } else {
2777 lea(rscratch1, src);
2778 Assembler::comisd(dst, Address(rscratch1, 0));
2779 }
2780 }
2781
2782 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2783 if (reachable(src)) {
2784 Assembler::comiss(dst, as_Address(src));
2785 } else {
2786 lea(rscratch1, src);
2787 Assembler::comiss(dst, Address(rscratch1, 0));
2788 }
2789 }
2790
2791
2792 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2793 Condition negated_cond = negate_condition(cond);
2794 Label L;
2795 jcc(negated_cond, L);
2796 pushf(); // Preserve flags
2797 atomic_incl(counter_addr);
2798 popf();
2799 bind(L);
2800 }
2801
2802 int MacroAssembler::corrected_idivl(Register reg) {
2803 // Full implementation of Java idiv and irem; checks for
2804 // special case as described in JVM spec., p.243 & p.271.
2805 // The function returns the (pc) offset of the idivl
2806 // instruction - may be needed for implicit exceptions.
2807 //
2808 // normal case special case
2809 //
2810 // input : rax,: dividend min_int
2811 // reg: divisor (may not be rax,/rdx) -1
2812 //
2813 // output: rax,: quotient (= rax, idiv reg) min_int
2814 // rdx: remainder (= rax, irem reg) 0
2815 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2816 const int min_int = 0x80000000;
2817 Label normal_case, special_case;
2818
2819 // check for special case
2820 cmpl(rax, min_int);
2821 jcc(Assembler::notEqual, normal_case);
2822 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2823 cmpl(reg, -1);
2824 jcc(Assembler::equal, special_case);
2825
2826 // handle normal case
2827 bind(normal_case);
2828 cdql();
2829 int idivl_offset = offset();
2830 idivl(reg);
2831
2832 // normal and special case exit
2833 bind(special_case);
2834
2835 return idivl_offset;
2836 }
2837
2838
2839
2840 void MacroAssembler::decrementl(Register reg, int value) {
2841 if (value == min_jint) {subl(reg, value) ; return; }
2842 if (value < 0) { incrementl(reg, -value); return; }
2843 if (value == 0) { ; return; }
2844 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2845 /* else */ { subl(reg, value) ; return; }
2846 }
2847
2848 void MacroAssembler::decrementl(Address dst, int value) {
2849 if (value == min_jint) {subl(dst, value) ; return; }
2850 if (value < 0) { incrementl(dst, -value); return; }
2851 if (value == 0) { ; return; }
2852 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2853 /* else */ { subl(dst, value) ; return; }
2854 }
2855
2856 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2857 assert (shift_value > 0, "illegal shift value");
2858 Label _is_positive;
2859 testl (reg, reg);
2860 jcc (Assembler::positive, _is_positive);
2861 int offset = (1 << shift_value) - 1 ;
2862
2863 if (offset == 1) {
2864 incrementl(reg);
2865 } else {
2866 addl(reg, offset);
2867 }
2868
2869 bind (_is_positive);
2870 sarl(reg, shift_value);
2871 }
2872
2873 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2874 if (reachable(src)) {
2875 Assembler::divsd(dst, as_Address(src));
2876 } else {
2877 lea(rscratch1, src);
2878 Assembler::divsd(dst, Address(rscratch1, 0));
2879 }
2880 }
2881
2882 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2883 if (reachable(src)) {
2884 Assembler::divss(dst, as_Address(src));
2885 } else {
2886 lea(rscratch1, src);
2887 Assembler::divss(dst, Address(rscratch1, 0));
2888 }
2889 }
2890
2891 // !defined(COMPILER2) is because of stupid core builds
2892 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2893 void MacroAssembler::empty_FPU_stack() {
2894 if (VM_Version::supports_mmx()) {
2895 emms();
2896 } else {
2897 for (int i = 8; i-- > 0; ) ffree(i);
2898 }
2899 }
2900 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2901
2902
2903 // Defines obj, preserves var_size_in_bytes
2904 void MacroAssembler::eden_allocate(Register obj,
2905 Register var_size_in_bytes,
2906 int con_size_in_bytes,
2907 Register t1,
2908 Label& slow_case) {
2909 assert(obj == rax, "obj must be in rax, for cmpxchg");
2910 assert_different_registers(obj, var_size_in_bytes, t1);
2911 if (!Universe::heap()->supports_inline_contig_alloc()) {
2912 jmp(slow_case);
2913 } else {
2914 Register end = t1;
2915 Label retry;
2916 bind(retry);
2917 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2918 movptr(obj, heap_top);
2919 if (var_size_in_bytes == noreg) {
2920 lea(end, Address(obj, con_size_in_bytes));
2921 } else {
2922 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2923 }
2924 // if end < obj then we wrapped around => object too long => slow case
2925 cmpptr(end, obj);
2926 jcc(Assembler::below, slow_case);
2927 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2928 jcc(Assembler::above, slow_case);
2929 // Compare obj with the top addr, and if still equal, store the new top addr in
2930 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2931 // it otherwise. Use lock prefix for atomicity on MPs.
2932 locked_cmpxchgptr(end, heap_top);
2933 jcc(Assembler::notEqual, retry);
2934 }
2935 }
2936
2937 void MacroAssembler::enter() {
2938 push(rbp);
2939 mov(rbp, rsp);
2940 }
2941
2942 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2943 void MacroAssembler::fat_nop() {
2944 if (UseAddressNop) {
2945 addr_nop_5();
2946 } else {
2947 emit_int8(0x26); // es:
2948 emit_int8(0x2e); // cs:
2949 emit_int8(0x64); // fs:
2950 emit_int8(0x65); // gs:
2951 emit_int8((unsigned char)0x90);
2952 }
2953 }
2954
2955 void MacroAssembler::fcmp(Register tmp) {
2956 fcmp(tmp, 1, true, true);
2957 }
2958
2959 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2960 assert(!pop_right || pop_left, "usage error");
2961 if (VM_Version::supports_cmov()) {
2962 assert(tmp == noreg, "unneeded temp");
2963 if (pop_left) {
2964 fucomip(index);
2965 } else {
2966 fucomi(index);
2967 }
2968 if (pop_right) {
2969 fpop();
2970 }
2971 } else {
2972 assert(tmp != noreg, "need temp");
2973 if (pop_left) {
2974 if (pop_right) {
2975 fcompp();
2976 } else {
2977 fcomp(index);
2978 }
2979 } else {
2980 fcom(index);
2981 }
2982 // convert FPU condition into eflags condition via rax,
2983 save_rax(tmp);
2984 fwait(); fnstsw_ax();
2985 sahf();
2986 restore_rax(tmp);
2987 }
2988 // condition codes set as follows:
2989 //
2990 // CF (corresponds to C0) if x < y
2991 // PF (corresponds to C2) if unordered
2992 // ZF (corresponds to C3) if x = y
2993 }
2994
2995 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2996 fcmp2int(dst, unordered_is_less, 1, true, true);
2997 }
2998
2999 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3000 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3001 Label L;
3002 if (unordered_is_less) {
3003 movl(dst, -1);
3004 jcc(Assembler::parity, L);
3005 jcc(Assembler::below , L);
3006 movl(dst, 0);
3007 jcc(Assembler::equal , L);
3008 increment(dst);
3009 } else { // unordered is greater
3010 movl(dst, 1);
3011 jcc(Assembler::parity, L);
3012 jcc(Assembler::above , L);
3013 movl(dst, 0);
3014 jcc(Assembler::equal , L);
3015 decrementl(dst);
3016 }
3017 bind(L);
3018 }
3019
3020 void MacroAssembler::fld_d(AddressLiteral src) {
3021 fld_d(as_Address(src));
3022 }
3023
3024 void MacroAssembler::fld_s(AddressLiteral src) {
3025 fld_s(as_Address(src));
3026 }
3027
3028 void MacroAssembler::fld_x(AddressLiteral src) {
3029 Assembler::fld_x(as_Address(src));
3030 }
3031
3032 void MacroAssembler::fldcw(AddressLiteral src) {
3033 Assembler::fldcw(as_Address(src));
3034 }
3035
3036 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3037 if (reachable(src)) {
3038 Assembler::mulpd(dst, as_Address(src));
3039 } else {
3040 lea(rscratch1, src);
3041 Assembler::mulpd(dst, Address(rscratch1, 0));
3042 }
3043 }
3044
3045 void MacroAssembler::pow_exp_core_encoding() {
3046 // kills rax, rcx, rdx
3047 subptr(rsp,sizeof(jdouble));
3048 // computes 2^X. Stack: X ...
3049 // f2xm1 computes 2^X-1 but only operates on -1<=X<=1. Get int(X) and
3050 // keep it on the thread's stack to compute 2^int(X) later
3051 // then compute 2^(X-int(X)) as (2^(X-int(X)-1+1)
3052 // final result is obtained with: 2^X = 2^int(X) * 2^(X-int(X))
3053 fld_s(0); // Stack: X X ...
3054 frndint(); // Stack: int(X) X ...
3055 fsuba(1); // Stack: int(X) X-int(X) ...
3056 fistp_s(Address(rsp,0)); // move int(X) as integer to thread's stack. Stack: X-int(X) ...
3057 f2xm1(); // Stack: 2^(X-int(X))-1 ...
3058 fld1(); // Stack: 1 2^(X-int(X))-1 ...
3059 faddp(1); // Stack: 2^(X-int(X))
3060 // computes 2^(int(X)): add exponent bias (1023) to int(X), then
3061 // shift int(X)+1023 to exponent position.
3062 // Exponent is limited to 11 bits if int(X)+1023 does not fit in 11
3063 // bits, set result to NaN. 0x000 and 0x7FF are reserved exponent
3064 // values so detect them and set result to NaN.
3065 movl(rax,Address(rsp,0));
3066 movl(rcx, -2048); // 11 bit mask and valid NaN binary encoding
3067 addl(rax, 1023);
3068 movl(rdx,rax);
3069 shll(rax,20);
3070 // Check that 0 < int(X)+1023 < 2047. Otherwise set rax to NaN.
3071 addl(rdx,1);
3072 // Check that 1 < int(X)+1023+1 < 2048
3073 // in 3 steps:
3074 // 1- (int(X)+1023+1)&-2048 == 0 => 0 <= int(X)+1023+1 < 2048
3075 // 2- (int(X)+1023+1)&-2048 != 0
3076 // 3- (int(X)+1023+1)&-2048 != 1
3077 // Do 2- first because addl just updated the flags.
3078 cmov32(Assembler::equal,rax,rcx);
3079 cmpl(rdx,1);
3080 cmov32(Assembler::equal,rax,rcx);
3081 testl(rdx,rcx);
3082 cmov32(Assembler::notEqual,rax,rcx);
3083 movl(Address(rsp,4),rax);
3084 movl(Address(rsp,0),0);
3085 fmul_d(Address(rsp,0)); // Stack: 2^X ...
3086 addptr(rsp,sizeof(jdouble));
3087 }
3088
3089 void MacroAssembler::increase_precision() {
3090 subptr(rsp, BytesPerWord);
3091 fnstcw(Address(rsp, 0));
3092 movl(rax, Address(rsp, 0));
3093 orl(rax, 0x300);
3094 push(rax);
3095 fldcw(Address(rsp, 0));
3096 pop(rax);
3097 }
3098
3099 void MacroAssembler::restore_precision() {
3100 fldcw(Address(rsp, 0));
3101 addptr(rsp, BytesPerWord);
3102 }
3103
3104 void MacroAssembler::fast_pow() {
3105 // computes X^Y = 2^(Y * log2(X))
3106 // if fast computation is not possible, result is NaN. Requires
3107 // fallback from user of this macro.
3108 // increase precision for intermediate steps of the computation
3109 BLOCK_COMMENT("fast_pow {");
3110 increase_precision();
3111 fyl2x(); // Stack: (Y*log2(X)) ...
3112 pow_exp_core_encoding(); // Stack: exp(X) ...
3113 restore_precision();
3114 BLOCK_COMMENT("} fast_pow");
3115 }
3116
3117 void MacroAssembler::pow_or_exp(int num_fpu_regs_in_use) {
3118 // kills rax, rcx, rdx
3119 // pow and exp needs 2 extra registers on the fpu stack.
3120 Label slow_case, done;
3121 Register tmp = noreg;
3122 if (!VM_Version::supports_cmov()) {
3123 // fcmp needs a temporary so preserve rdx,
3124 tmp = rdx;
3125 }
3126 Register tmp2 = rax;
3127 Register tmp3 = rcx;
3128
3129 // Stack: X Y
3130 Label x_negative, y_not_2;
3131
3132 static double two = 2.0;
3133 ExternalAddress two_addr((address)&two);
3134
3135 // constant maybe too far on 64 bit
3136 lea(tmp2, two_addr);
3137 fld_d(Address(tmp2, 0)); // Stack: 2 X Y
3138 fcmp(tmp, 2, true, false); // Stack: X Y
3139 jcc(Assembler::parity, y_not_2);
3140 jcc(Assembler::notEqual, y_not_2);
3141
3142 fxch(); fpop(); // Stack: X
3143 fmul(0); // Stack: X*X
3144
3145 jmp(done);
3146
3147 bind(y_not_2);
3148
3149 fldz(); // Stack: 0 X Y
3150 fcmp(tmp, 1, true, false); // Stack: X Y
3151 jcc(Assembler::above, x_negative);
3152
3153 // X >= 0
3154
3155 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3156 fld_s(1); // Stack: X Y X Y
3157 fast_pow(); // Stack: X^Y X Y
3158 fcmp(tmp, 0, false, false); // Stack: X^Y X Y
3159 // X^Y not equal to itself: X^Y is NaN go to slow case.
3160 jcc(Assembler::parity, slow_case);
3161 // get rid of duplicate arguments. Stack: X^Y
3162 if (num_fpu_regs_in_use > 0) {
3163 fxch(); fpop();
3164 fxch(); fpop();
3165 } else {
3166 ffree(2);
3167 ffree(1);
3168 }
3169 jmp(done);
3170
3171 // X <= 0
3172 bind(x_negative);
3173
3174 fld_s(1); // Stack: Y X Y
3175 frndint(); // Stack: int(Y) X Y
3176 fcmp(tmp, 2, false, false); // Stack: int(Y) X Y
3177 jcc(Assembler::notEqual, slow_case);
3178
3179 subptr(rsp, 8);
3180
3181 // For X^Y, when X < 0, Y has to be an integer and the final
3182 // result depends on whether it's odd or even. We just checked
3183 // that int(Y) == Y. We move int(Y) to gp registers as a 64 bit
3184 // integer to test its parity. If int(Y) is huge and doesn't fit
3185 // in the 64 bit integer range, the integer indefinite value will
3186 // end up in the gp registers. Huge numbers are all even, the
3187 // integer indefinite number is even so it's fine.
3188
3189 #ifdef ASSERT
3190 // Let's check we don't end up with an integer indefinite number
3191 // when not expected. First test for huge numbers: check whether
3192 // int(Y)+1 == int(Y) which is true for very large numbers and
3193 // those are all even. A 64 bit integer is guaranteed to not
3194 // overflow for numbers where y+1 != y (when precision is set to
3195 // double precision).
3196 Label y_not_huge;
3197
3198 fld1(); // Stack: 1 int(Y) X Y
3199 fadd(1); // Stack: 1+int(Y) int(Y) X Y
3200
3201 #ifdef _LP64
3202 // trip to memory to force the precision down from double extended
3203 // precision
3204 fstp_d(Address(rsp, 0));
3205 fld_d(Address(rsp, 0));
3206 #endif
3207
3208 fcmp(tmp, 1, true, false); // Stack: int(Y) X Y
3209 #endif
3210
3211 // move int(Y) as 64 bit integer to thread's stack
3212 fistp_d(Address(rsp,0)); // Stack: X Y
3213
3214 #ifdef ASSERT
3215 jcc(Assembler::notEqual, y_not_huge);
3216
3217 // Y is huge so we know it's even. It may not fit in a 64 bit
3218 // integer and we don't want the debug code below to see the
3219 // integer indefinite value so overwrite int(Y) on the thread's
3220 // stack with 0.
3221 movl(Address(rsp, 0), 0);
3222 movl(Address(rsp, 4), 0);
3223
3224 bind(y_not_huge);
3225 #endif
3226
3227 fld_s(1); // duplicate arguments for runtime call. Stack: Y X Y
3228 fld_s(1); // Stack: X Y X Y
3229 fabs(); // Stack: abs(X) Y X Y
3230 fast_pow(); // Stack: abs(X)^Y X Y
3231 fcmp(tmp, 0, false, false); // Stack: abs(X)^Y X Y
3232 // abs(X)^Y not equal to itself: abs(X)^Y is NaN go to slow case.
3233
3234 pop(tmp2);
3235 NOT_LP64(pop(tmp3));
3236 jcc(Assembler::parity, slow_case);
3237
3238 #ifdef ASSERT
3239 // Check that int(Y) is not integer indefinite value (int
3240 // overflow). Shouldn't happen because for values that would
3241 // overflow, 1+int(Y)==Y which was tested earlier.
3242 #ifndef _LP64
3243 {
3244 Label integer;
3245 testl(tmp2, tmp2);
3246 jcc(Assembler::notZero, integer);
3247 cmpl(tmp3, 0x80000000);
3248 jcc(Assembler::notZero, integer);
3249 STOP("integer indefinite value shouldn't be seen here");
3250 bind(integer);
3251 }
3252 #else
3253 {
3254 Label integer;
3255 mov(tmp3, tmp2); // preserve tmp2 for parity check below
3256 shlq(tmp3, 1);
3257 jcc(Assembler::carryClear, integer);
3258 jcc(Assembler::notZero, integer);
3259 STOP("integer indefinite value shouldn't be seen here");
3260 bind(integer);
3261 }
3262 #endif
3263 #endif
3264
3265 // get rid of duplicate arguments. Stack: X^Y
3266 if (num_fpu_regs_in_use > 0) {
3267 fxch(); fpop();
3268 fxch(); fpop();
3269 } else {
3270 ffree(2);
3271 ffree(1);
3272 }
3273
3274 testl(tmp2, 1);
3275 jcc(Assembler::zero, done); // X <= 0, Y even: X^Y = abs(X)^Y
3276 // X <= 0, Y even: X^Y = -abs(X)^Y
3277
3278 fchs(); // Stack: -abs(X)^Y Y
3279 jmp(done);
3280
3281 // slow case: runtime call
3282 bind(slow_case);
3283
3284 fpop(); // pop incorrect result or int(Y)
3285
3286 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dpow), 2, num_fpu_regs_in_use);
3287
3288 // Come here with result in F-TOS
3289 bind(done);
3290 }
3291
3292 void MacroAssembler::fpop() {
3293 ffree();
3294 fincstp();
3295 }
3296
3297 void MacroAssembler::load_float(Address src) {
3298 if (UseSSE >= 1) {
3299 movflt(xmm0, src);
3300 } else {
3301 LP64_ONLY(ShouldNotReachHere());
3302 NOT_LP64(fld_s(src));
3303 }
3304 }
3305
3306 void MacroAssembler::store_float(Address dst) {
3307 if (UseSSE >= 1) {
3308 movflt(dst, xmm0);
3309 } else {
3310 LP64_ONLY(ShouldNotReachHere());
3311 NOT_LP64(fstp_s(dst));
3312 }
3313 }
3314
3315 void MacroAssembler::load_double(Address src) {
3316 if (UseSSE >= 2) {
3317 movdbl(xmm0, src);
3318 } else {
3319 LP64_ONLY(ShouldNotReachHere());
3320 NOT_LP64(fld_d(src));
3321 }
3322 }
3323
3324 void MacroAssembler::store_double(Address dst) {
3325 if (UseSSE >= 2) {
3326 movdbl(dst, xmm0);
3327 } else {
3328 LP64_ONLY(ShouldNotReachHere());
3329 NOT_LP64(fstp_d(dst));
3330 }
3331 }
3332
3333 void MacroAssembler::fremr(Register tmp) {
3334 save_rax(tmp);
3335 { Label L;
3336 bind(L);
3337 fprem();
3338 fwait(); fnstsw_ax();
3339 #ifdef _LP64
3340 testl(rax, 0x400);
3341 jcc(Assembler::notEqual, L);
3342 #else
3343 sahf();
3344 jcc(Assembler::parity, L);
3345 #endif // _LP64
3346 }
3347 restore_rax(tmp);
3348 // Result is in ST0.
3349 // Note: fxch & fpop to get rid of ST1
3350 // (otherwise FPU stack could overflow eventually)
3351 fxch(1);
3352 fpop();
3353 }
3354
3355
3356 void MacroAssembler::incrementl(AddressLiteral dst) {
3357 if (reachable(dst)) {
3358 incrementl(as_Address(dst));
3359 } else {
3360 lea(rscratch1, dst);
3361 incrementl(Address(rscratch1, 0));
3362 }
3363 }
3364
3365 void MacroAssembler::incrementl(ArrayAddress dst) {
3366 incrementl(as_Address(dst));
3367 }
3368
3369 void MacroAssembler::incrementl(Register reg, int value) {
3370 if (value == min_jint) {addl(reg, value) ; return; }
3371 if (value < 0) { decrementl(reg, -value); return; }
3372 if (value == 0) { ; return; }
3373 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3374 /* else */ { addl(reg, value) ; return; }
3375 }
3376
3377 void MacroAssembler::incrementl(Address dst, int value) {
3378 if (value == min_jint) {addl(dst, value) ; return; }
3379 if (value < 0) { decrementl(dst, -value); return; }
3380 if (value == 0) { ; return; }
3381 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3382 /* else */ { addl(dst, value) ; return; }
3383 }
3384
3385 void MacroAssembler::jump(AddressLiteral dst) {
3386 if (reachable(dst)) {
3387 jmp_literal(dst.target(), dst.rspec());
3388 } else {
3389 lea(rscratch1, dst);
3390 jmp(rscratch1);
3391 }
3392 }
3393
3394 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3395 if (reachable(dst)) {
3396 InstructionMark im(this);
3397 relocate(dst.reloc());
3398 const int short_size = 2;
3399 const int long_size = 6;
3400 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3401 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3402 // 0111 tttn #8-bit disp
3403 emit_int8(0x70 | cc);
3404 emit_int8((offs - short_size) & 0xFF);
3405 } else {
3406 // 0000 1111 1000 tttn #32-bit disp
3407 emit_int8(0x0F);
3408 emit_int8((unsigned char)(0x80 | cc));
3409 emit_int32(offs - long_size);
3410 }
3411 } else {
3412 #ifdef ASSERT
3413 warning("reversing conditional branch");
3414 #endif /* ASSERT */
3415 Label skip;
3416 jccb(reverse[cc], skip);
3417 lea(rscratch1, dst);
3418 Assembler::jmp(rscratch1);
3419 bind(skip);
3420 }
3421 }
3422
3423 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3424 if (reachable(src)) {
3425 Assembler::ldmxcsr(as_Address(src));
3426 } else {
3427 lea(rscratch1, src);
3428 Assembler::ldmxcsr(Address(rscratch1, 0));
3429 }
3430 }
3431
3432 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3433 int off;
3434 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3435 off = offset();
3436 movsbl(dst, src); // movsxb
3437 } else {
3438 off = load_unsigned_byte(dst, src);
3439 shll(dst, 24);
3440 sarl(dst, 24);
3441 }
3442 return off;
3443 }
3444
3445 // Note: load_signed_short used to be called load_signed_word.
3446 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3447 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3448 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3449 int MacroAssembler::load_signed_short(Register dst, Address src) {
3450 int off;
3451 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3452 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3453 // version but this is what 64bit has always done. This seems to imply
3454 // that users are only using 32bits worth.
3455 off = offset();
3456 movswl(dst, src); // movsxw
3457 } else {
3458 off = load_unsigned_short(dst, src);
3459 shll(dst, 16);
3460 sarl(dst, 16);
3461 }
3462 return off;
3463 }
3464
3465 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3466 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3467 // and "3.9 Partial Register Penalties", p. 22).
3468 int off;
3469 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3470 off = offset();
3471 movzbl(dst, src); // movzxb
3472 } else {
3473 xorl(dst, dst);
3474 off = offset();
3475 movb(dst, src);
3476 }
3477 return off;
3478 }
3479
3480 // Note: load_unsigned_short used to be called load_unsigned_word.
3481 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3482 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3483 // and "3.9 Partial Register Penalties", p. 22).
3484 int off;
3485 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3486 off = offset();
3487 movzwl(dst, src); // movzxw
3488 } else {
3489 xorl(dst, dst);
3490 off = offset();
3491 movw(dst, src);
3492 }
3493 return off;
3494 }
3495
3496 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3497 switch (size_in_bytes) {
3498 #ifndef _LP64
3499 case 8:
3500 assert(dst2 != noreg, "second dest register required");
3501 movl(dst, src);
3502 movl(dst2, src.plus_disp(BytesPerInt));
3503 break;
3504 #else
3505 case 8: movq(dst, src); break;
3506 #endif
3507 case 4: movl(dst, src); break;
3508 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3509 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3510 default: ShouldNotReachHere();
3511 }
3512 }
3513
3514 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3515 switch (size_in_bytes) {
3516 #ifndef _LP64
3517 case 8:
3518 assert(src2 != noreg, "second source register required");
3519 movl(dst, src);
3520 movl(dst.plus_disp(BytesPerInt), src2);
3521 break;
3522 #else
3523 case 8: movq(dst, src); break;
3524 #endif
3525 case 4: movl(dst, src); break;
3526 case 2: movw(dst, src); break;
3527 case 1: movb(dst, src); break;
3528 default: ShouldNotReachHere();
3529 }
3530 }
3531
3532 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3533 if (reachable(dst)) {
3534 movl(as_Address(dst), src);
3535 } else {
3536 lea(rscratch1, dst);
3537 movl(Address(rscratch1, 0), src);
3538 }
3539 }
3540
3541 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3542 if (reachable(src)) {
3543 movl(dst, as_Address(src));
3544 } else {
3545 lea(rscratch1, src);
3546 movl(dst, Address(rscratch1, 0));
3547 }
3548 }
3549
3550 // C++ bool manipulation
3551
3552 void MacroAssembler::movbool(Register dst, Address src) {
3553 if(sizeof(bool) == 1)
3554 movb(dst, src);
3555 else if(sizeof(bool) == 2)
3556 movw(dst, src);
3557 else if(sizeof(bool) == 4)
3558 movl(dst, src);
3559 else
3560 // unsupported
3561 ShouldNotReachHere();
3562 }
3563
3564 void MacroAssembler::movbool(Address dst, bool boolconst) {
3565 if(sizeof(bool) == 1)
3566 movb(dst, (int) boolconst);
3567 else if(sizeof(bool) == 2)
3568 movw(dst, (int) boolconst);
3569 else if(sizeof(bool) == 4)
3570 movl(dst, (int) boolconst);
3571 else
3572 // unsupported
3573 ShouldNotReachHere();
3574 }
3575
3576 void MacroAssembler::movbool(Address dst, Register src) {
3577 if(sizeof(bool) == 1)
3578 movb(dst, src);
3579 else if(sizeof(bool) == 2)
3580 movw(dst, src);
3581 else if(sizeof(bool) == 4)
3582 movl(dst, src);
3583 else
3584 // unsupported
3585 ShouldNotReachHere();
3586 }
3587
3588 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3589 movb(as_Address(dst), src);
3590 }
3591
3592 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3593 if (reachable(src)) {
3594 movdl(dst, as_Address(src));
3595 } else {
3596 lea(rscratch1, src);
3597 movdl(dst, Address(rscratch1, 0));
3598 }
3599 }
3600
3601 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3602 if (reachable(src)) {
3603 movq(dst, as_Address(src));
3604 } else {
3605 lea(rscratch1, src);
3606 movq(dst, Address(rscratch1, 0));
3607 }
3608 }
3609
3610 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3611 if (reachable(src)) {
3612 if (UseXmmLoadAndClearUpper) {
3613 movsd (dst, as_Address(src));
3614 } else {
3615 movlpd(dst, as_Address(src));
3616 }
3617 } else {
3618 lea(rscratch1, src);
3619 if (UseXmmLoadAndClearUpper) {
3620 movsd (dst, Address(rscratch1, 0));
3621 } else {
3622 movlpd(dst, Address(rscratch1, 0));
3623 }
3624 }
3625 }
3626
3627 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3628 if (reachable(src)) {
3629 movss(dst, as_Address(src));
3630 } else {
3631 lea(rscratch1, src);
3632 movss(dst, Address(rscratch1, 0));
3633 }
3634 }
3635
3636 void MacroAssembler::movptr(Register dst, Register src) {
3637 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3638 }
3639
3640 void MacroAssembler::movptr(Register dst, Address src) {
3641 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3642 }
3643
3644 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3645 void MacroAssembler::movptr(Register dst, intptr_t src) {
3646 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3647 }
3648
3649 void MacroAssembler::movptr(Address dst, Register src) {
3650 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3651 }
3652
3653 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3654 if (reachable(src)) {
3655 Assembler::movdqu(dst, as_Address(src));
3656 } else {
3657 lea(rscratch1, src);
3658 Assembler::movdqu(dst, Address(rscratch1, 0));
3659 }
3660 }
3661
3662 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3663 if (reachable(src)) {
3664 Assembler::movdqa(dst, as_Address(src));
3665 } else {
3666 lea(rscratch1, src);
3667 Assembler::movdqa(dst, Address(rscratch1, 0));
3668 }
3669 }
3670
3671 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3672 if (reachable(src)) {
3673 Assembler::movsd(dst, as_Address(src));
3674 } else {
3675 lea(rscratch1, src);
3676 Assembler::movsd(dst, Address(rscratch1, 0));
3677 }
3678 }
3679
3680 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3681 if (reachable(src)) {
3682 Assembler::movss(dst, as_Address(src));
3683 } else {
3684 lea(rscratch1, src);
3685 Assembler::movss(dst, Address(rscratch1, 0));
3686 }
3687 }
3688
3689 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3690 if (reachable(src)) {
3691 Assembler::mulsd(dst, as_Address(src));
3692 } else {
3693 lea(rscratch1, src);
3694 Assembler::mulsd(dst, Address(rscratch1, 0));
3695 }
3696 }
3697
3698 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3699 if (reachable(src)) {
3700 Assembler::mulss(dst, as_Address(src));
3701 } else {
3702 lea(rscratch1, src);
3703 Assembler::mulss(dst, Address(rscratch1, 0));
3704 }
3705 }
3706
3707 void MacroAssembler::null_check(Register reg, int offset) {
3708 if (needs_explicit_null_check(offset)) {
3709 // provoke OS NULL exception if reg = NULL by
3710 // accessing M[reg] w/o changing any (non-CC) registers
3711 // NOTE: cmpl is plenty here to provoke a segv
3712 cmpptr(rax, Address(reg, 0));
3713 // Note: should probably use testl(rax, Address(reg, 0));
3714 // may be shorter code (however, this version of
3715 // testl needs to be implemented first)
3716 } else {
3717 // nothing to do, (later) access of M[reg + offset]
3718 // will provoke OS NULL exception if reg = NULL
3719 }
3720 }
3721
3722 void MacroAssembler::os_breakpoint() {
3723 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3724 // (e.g., MSVC can't call ps() otherwise)
3725 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3726 }
3727
3728 void MacroAssembler::pop_CPU_state() {
3729 pop_FPU_state();
3730 pop_IU_state();
3731 }
3732
3733 void MacroAssembler::pop_FPU_state() {
3734 #ifndef _LP64
3735 frstor(Address(rsp, 0));
3736 #else
3737 // AVX will continue to use the fxsave area.
3738 // EVEX needs to utilize the xsave area, which is under different
3739 // management.
3740 if(VM_Version::supports_evex()) {
3741 // EDX:EAX describe the XSAVE header and
3742 // are obtained while fetching info for XCR0 via cpuid.
3743 // These two registers make up 64-bits in the header for which bits
3744 // 62:10 are currently reserved for future implementations and unused. Bit 63
3745 // is unused for our implementation as we do not utilize
3746 // compressed XSAVE areas. Bits 9..8 are currently ignored as we do not use
3747 // the functionality for PKRU state and MSR tracing.
3748 // Ergo we are primarily concerned with bits 7..0, which define
3749 // which ISA extensions and features are enabled for a given machine and are
3750 // defined in XemXcr0Eax and is used to map the XSAVE area
3751 // for restoring registers as described via XCR0.
3752 movl(rdx,VM_Version::get_xsave_header_upper_segment());
3753 movl(rax,VM_Version::get_xsave_header_lower_segment());
3754 xrstor(Address(rsp, 0));
3755 } else {
3756 fxrstor(Address(rsp, 0));
3757 }
3758 #endif
3759 addptr(rsp, FPUStateSizeInWords * wordSize);
3760 }
3761
3762 void MacroAssembler::pop_IU_state() {
3763 popa();
3764 LP64_ONLY(addq(rsp, 8));
3765 popf();
3766 }
3767
3768 // Save Integer and Float state
3769 // Warning: Stack must be 16 byte aligned (64bit)
3770 void MacroAssembler::push_CPU_state() {
3771 push_IU_state();
3772 push_FPU_state();
3773 }
3774
3775 #ifdef _LP64
3776 #define XSTATE_BV 0x200
3777 #endif
3778
3779 void MacroAssembler::push_FPU_state() {
3780 subptr(rsp, FPUStateSizeInWords * wordSize);
3781 #ifndef _LP64
3782 fnsave(Address(rsp, 0));
3783 fwait();
3784 #else
3785 // AVX will continue to use the fxsave area.
3786 // EVEX needs to utilize the xsave area, which is under different
3787 // management.
3788 if(VM_Version::supports_evex()) {
3789 // Save a copy of EAX and EDX
3790 push(rax);
3791 push(rdx);
3792 // EDX:EAX describe the XSAVE header and
3793 // are obtained while fetching info for XCR0 via cpuid.
3794 // These two registers make up 64-bits in the header for which bits
3795 // 62:10 are currently reserved for future implementations and unused. Bit 63
3796 // is unused for our implementation as we do not utilize
3797 // compressed XSAVE areas. Bits 9..8 are currently ignored as we do not use
3798 // the functionality for PKRU state and MSR tracing.
3799 // Ergo we are primarily concerned with bits 7..0, which define
3800 // which ISA extensions and features are enabled for a given machine and are
3801 // defined in XemXcr0Eax and is used to program XSAVE area
3802 // for saving the required registers as defined in XCR0.
3803 int xcr0_edx = VM_Version::get_xsave_header_upper_segment();
3804 int xcr0_eax = VM_Version::get_xsave_header_lower_segment();
3805 movl(rdx,xcr0_edx);
3806 movl(rax,xcr0_eax);
3807 xsave(Address(rsp, wordSize*2));
3808 // now Apply control bits and clear bytes 8..23 in the header
3809 pop(rdx);
3810 pop(rax);
3811 movl(Address(rsp, XSTATE_BV), xcr0_eax);
3812 movl(Address(rsp, XSTATE_BV+4), xcr0_edx);
3813 andq(Address(rsp, XSTATE_BV+8), 0);
3814 andq(Address(rsp, XSTATE_BV+16), 0);
3815 } else {
3816 fxsave(Address(rsp, 0));
3817 }
3818 #endif // LP64
3819 }
3820
3821 void MacroAssembler::push_IU_state() {
3822 // Push flags first because pusha kills them
3823 pushf();
3824 // Make sure rsp stays 16-byte aligned
3825 LP64_ONLY(subq(rsp, 8));
3826 pusha();
3827 }
3828
3829 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3830 // determine java_thread register
3831 if (!java_thread->is_valid()) {
3832 java_thread = rdi;
3833 get_thread(java_thread);
3834 }
3835 // we must set sp to zero to clear frame
3836 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3837 if (clear_fp) {
3838 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3839 }
3840
3841 if (clear_pc)
3842 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3843
3844 }
3845
3846 void MacroAssembler::restore_rax(Register tmp) {
3847 if (tmp == noreg) pop(rax);
3848 else if (tmp != rax) mov(rax, tmp);
3849 }
3850
3851 void MacroAssembler::round_to(Register reg, int modulus) {
3852 addptr(reg, modulus - 1);
3853 andptr(reg, -modulus);
3854 }
3855
3856 void MacroAssembler::save_rax(Register tmp) {
3857 if (tmp == noreg) push(rax);
3858 else if (tmp != rax) mov(tmp, rax);
3859 }
3860
3861 // Write serialization page so VM thread can do a pseudo remote membar.
3862 // We use the current thread pointer to calculate a thread specific
3863 // offset to write to within the page. This minimizes bus traffic
3864 // due to cache line collision.
3865 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3866 movl(tmp, thread);
3867 shrl(tmp, os::get_serialize_page_shift_count());
3868 andl(tmp, (os::vm_page_size() - sizeof(int)));
3869
3870 Address index(noreg, tmp, Address::times_1);
3871 ExternalAddress page(os::get_memory_serialize_page());
3872
3873 // Size of store must match masking code above
3874 movl(as_Address(ArrayAddress(page, index)), tmp);
3875 }
3876
3877 // Calls to C land
3878 //
3879 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3880 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3881 // has to be reset to 0. This is required to allow proper stack traversal.
3882 void MacroAssembler::set_last_Java_frame(Register java_thread,
3883 Register last_java_sp,
3884 Register last_java_fp,
3885 address last_java_pc) {
3886 // determine java_thread register
3887 if (!java_thread->is_valid()) {
3888 java_thread = rdi;
3889 get_thread(java_thread);
3890 }
3891 // determine last_java_sp register
3892 if (!last_java_sp->is_valid()) {
3893 last_java_sp = rsp;
3894 }
3895
3896 // last_java_fp is optional
3897
3898 if (last_java_fp->is_valid()) {
3899 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3900 }
3901
3902 // last_java_pc is optional
3903
3904 if (last_java_pc != NULL) {
3905 lea(Address(java_thread,
3906 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3907 InternalAddress(last_java_pc));
3908
3909 }
3910 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3911 }
3912
3913 void MacroAssembler::shlptr(Register dst, int imm8) {
3914 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3915 }
3916
3917 void MacroAssembler::shrptr(Register dst, int imm8) {
3918 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3919 }
3920
3921 void MacroAssembler::sign_extend_byte(Register reg) {
3922 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3923 movsbl(reg, reg); // movsxb
3924 } else {
3925 shll(reg, 24);
3926 sarl(reg, 24);
3927 }
3928 }
3929
3930 void MacroAssembler::sign_extend_short(Register reg) {
3931 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3932 movswl(reg, reg); // movsxw
3933 } else {
3934 shll(reg, 16);
3935 sarl(reg, 16);
3936 }
3937 }
3938
3939 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3940 assert(reachable(src), "Address should be reachable");
3941 testl(dst, as_Address(src));
3942 }
3943
3944 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3945 if (reachable(src)) {
3946 Assembler::sqrtsd(dst, as_Address(src));
3947 } else {
3948 lea(rscratch1, src);
3949 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3950 }
3951 }
3952
3953 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3954 if (reachable(src)) {
3955 Assembler::sqrtss(dst, as_Address(src));
3956 } else {
3957 lea(rscratch1, src);
3958 Assembler::sqrtss(dst, Address(rscratch1, 0));
3959 }
3960 }
3961
3962 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3963 if (reachable(src)) {
3964 Assembler::subsd(dst, as_Address(src));
3965 } else {
3966 lea(rscratch1, src);
3967 Assembler::subsd(dst, Address(rscratch1, 0));
3968 }
3969 }
3970
3971 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3972 if (reachable(src)) {
3973 Assembler::subss(dst, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 Assembler::subss(dst, Address(rscratch1, 0));
3977 }
3978 }
3979
3980 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3981 if (reachable(src)) {
3982 Assembler::ucomisd(dst, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 Assembler::ucomisd(dst, Address(rscratch1, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3990 if (reachable(src)) {
3991 Assembler::ucomiss(dst, as_Address(src));
3992 } else {
3993 lea(rscratch1, src);
3994 Assembler::ucomiss(dst, Address(rscratch1, 0));
3995 }
3996 }
3997
3998 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
3999 // Used in sign-bit flipping with aligned address.
4000 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4001 if (reachable(src)) {
4002 Assembler::xorpd(dst, as_Address(src));
4003 } else {
4004 lea(rscratch1, src);
4005 Assembler::xorpd(dst, Address(rscratch1, 0));
4006 }
4007 }
4008
4009 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4010 // Used in sign-bit flipping with aligned address.
4011 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4012 if (reachable(src)) {
4013 Assembler::xorps(dst, as_Address(src));
4014 } else {
4015 lea(rscratch1, src);
4016 Assembler::xorps(dst, Address(rscratch1, 0));
4017 }
4018 }
4019
4020 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4021 // Used in sign-bit flipping with aligned address.
4022 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4023 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4024 if (reachable(src)) {
4025 Assembler::pshufb(dst, as_Address(src));
4026 } else {
4027 lea(rscratch1, src);
4028 Assembler::pshufb(dst, Address(rscratch1, 0));
4029 }
4030 }
4031
4032 // AVX 3-operands instructions
4033
4034 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4035 if (reachable(src)) {
4036 vaddsd(dst, nds, as_Address(src));
4037 } else {
4038 lea(rscratch1, src);
4039 vaddsd(dst, nds, Address(rscratch1, 0));
4040 }
4041 }
4042
4043 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4044 if (reachable(src)) {
4045 vaddss(dst, nds, as_Address(src));
4046 } else {
4047 lea(rscratch1, src);
4048 vaddss(dst, nds, Address(rscratch1, 0));
4049 }
4050 }
4051
4052 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4053 if (reachable(src)) {
4054 vandpd(dst, nds, as_Address(src), vector_len);
4055 } else {
4056 lea(rscratch1, src);
4057 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4058 }
4059 }
4060
4061 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4062 if (reachable(src)) {
4063 vandps(dst, nds, as_Address(src), vector_len);
4064 } else {
4065 lea(rscratch1, src);
4066 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4067 }
4068 }
4069
4070 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4071 if (reachable(src)) {
4072 vdivsd(dst, nds, as_Address(src));
4073 } else {
4074 lea(rscratch1, src);
4075 vdivsd(dst, nds, Address(rscratch1, 0));
4076 }
4077 }
4078
4079 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4080 if (reachable(src)) {
4081 vdivss(dst, nds, as_Address(src));
4082 } else {
4083 lea(rscratch1, src);
4084 vdivss(dst, nds, Address(rscratch1, 0));
4085 }
4086 }
4087
4088 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4089 if (reachable(src)) {
4090 vmulsd(dst, nds, as_Address(src));
4091 } else {
4092 lea(rscratch1, src);
4093 vmulsd(dst, nds, Address(rscratch1, 0));
4094 }
4095 }
4096
4097 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4098 if (reachable(src)) {
4099 vmulss(dst, nds, as_Address(src));
4100 } else {
4101 lea(rscratch1, src);
4102 vmulss(dst, nds, Address(rscratch1, 0));
4103 }
4104 }
4105
4106 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4107 if (reachable(src)) {
4108 vsubsd(dst, nds, as_Address(src));
4109 } else {
4110 lea(rscratch1, src);
4111 vsubsd(dst, nds, Address(rscratch1, 0));
4112 }
4113 }
4114
4115 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4116 if (reachable(src)) {
4117 vsubss(dst, nds, as_Address(src));
4118 } else {
4119 lea(rscratch1, src);
4120 vsubss(dst, nds, Address(rscratch1, 0));
4121 }
4122 }
4123
4124 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4125 int nds_enc = nds->encoding();
4126 int dst_enc = dst->encoding();
4127 bool dst_upper_bank = (dst_enc > 15);
4128 bool nds_upper_bank = (nds_enc > 15);
4129 if (VM_Version::supports_avx512novl() &&
4130 (nds_upper_bank || dst_upper_bank)) {
4131 if (dst_upper_bank) {
4132 subptr(rsp, 64);
4133 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4134 movflt(xmm0, nds);
4135 if (reachable(src)) {
4136 vxorps(xmm0, xmm0, as_Address(src), Assembler::AVX_128bit);
4137 } else {
4138 lea(rscratch1, src);
4139 vxorps(xmm0, xmm0, Address(rscratch1, 0), Assembler::AVX_128bit);
4140 }
4141 movflt(dst, xmm0);
4142 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4143 addptr(rsp, 64);
4144 } else {
4145 movflt(dst, nds);
4146 if (reachable(src)) {
4147 vxorps(dst, dst, as_Address(src), Assembler::AVX_128bit);
4148 } else {
4149 lea(rscratch1, src);
4150 vxorps(dst, dst, Address(rscratch1, 0), Assembler::AVX_128bit);
4151 }
4152 }
4153 } else {
4154 if (reachable(src)) {
4155 vxorps(dst, nds, as_Address(src), Assembler::AVX_128bit);
4156 } else {
4157 lea(rscratch1, src);
4158 vxorps(dst, nds, Address(rscratch1, 0), Assembler::AVX_128bit);
4159 }
4160 }
4161 }
4162
4163 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4164 int nds_enc = nds->encoding();
4165 int dst_enc = dst->encoding();
4166 bool dst_upper_bank = (dst_enc > 15);
4167 bool nds_upper_bank = (nds_enc > 15);
4168 if (VM_Version::supports_avx512novl() &&
4169 (nds_upper_bank || dst_upper_bank)) {
4170 if (dst_upper_bank) {
4171 subptr(rsp, 64);
4172 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4173 movdbl(xmm0, nds);
4174 if (reachable(src)) {
4175 vxorps(xmm0, xmm0, as_Address(src), Assembler::AVX_128bit);
4176 } else {
4177 lea(rscratch1, src);
4178 vxorps(xmm0, xmm0, Address(rscratch1, 0), Assembler::AVX_128bit);
4179 }
4180 movdbl(dst, xmm0);
4181 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4182 addptr(rsp, 64);
4183 } else {
4184 movdbl(dst, nds);
4185 if (reachable(src)) {
4186 vxorps(dst, dst, as_Address(src), Assembler::AVX_128bit);
4187 } else {
4188 lea(rscratch1, src);
4189 vxorps(dst, dst, Address(rscratch1, 0), Assembler::AVX_128bit);
4190 }
4191 }
4192 } else {
4193 if (reachable(src)) {
4194 vxorpd(dst, nds, as_Address(src), Assembler::AVX_128bit);
4195 } else {
4196 lea(rscratch1, src);
4197 vxorpd(dst, nds, Address(rscratch1, 0), Assembler::AVX_128bit);
4198 }
4199 }
4200 }
4201
4202 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4203 if (reachable(src)) {
4204 vxorpd(dst, nds, as_Address(src), vector_len);
4205 } else {
4206 lea(rscratch1, src);
4207 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
4208 }
4209 }
4210
4211 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4212 if (reachable(src)) {
4213 vxorps(dst, nds, as_Address(src), vector_len);
4214 } else {
4215 lea(rscratch1, src);
4216 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
4217 }
4218 }
4219
4220
4221 //////////////////////////////////////////////////////////////////////////////////
4222 #if INCLUDE_ALL_GCS
4223
4224 void MacroAssembler::g1_write_barrier_pre(Register obj,
4225 Register pre_val,
4226 Register thread,
4227 Register tmp,
4228 bool tosca_live,
4229 bool expand_call) {
4230
4231 // If expand_call is true then we expand the call_VM_leaf macro
4232 // directly to skip generating the check by
4233 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
4234
4235 #ifdef _LP64
4236 assert(thread == r15_thread, "must be");
4237 #endif // _LP64
4238
4239 Label done;
4240 Label runtime;
4241
4242 assert(pre_val != noreg, "check this code");
4243
4244 if (obj != noreg) {
4245 assert_different_registers(obj, pre_val, tmp);
4246 assert(pre_val != rax, "check this code");
4247 }
4248
4249 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4250 PtrQueue::byte_offset_of_active()));
4251 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4252 PtrQueue::byte_offset_of_index()));
4253 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
4254 PtrQueue::byte_offset_of_buf()));
4255
4256
4257 // Is marking active?
4258 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) {
4259 cmpl(in_progress, 0);
4260 } else {
4261 assert(in_bytes(PtrQueue::byte_width_of_active()) == 1, "Assumption");
4262 cmpb(in_progress, 0);
4263 }
4264 jcc(Assembler::equal, done);
4265
4266 // Do we need to load the previous value?
4267 if (obj != noreg) {
4268 load_heap_oop(pre_val, Address(obj, 0));
4269 }
4270
4271 // Is the previous value null?
4272 cmpptr(pre_val, (int32_t) NULL_WORD);
4273 jcc(Assembler::equal, done);
4274
4275 // Can we store original value in the thread's buffer?
4276 // Is index == 0?
4277 // (The index field is typed as size_t.)
4278
4279 movptr(tmp, index); // tmp := *index_adr
4280 cmpptr(tmp, 0); // tmp == 0?
4281 jcc(Assembler::equal, runtime); // If yes, goto runtime
4282
4283 subptr(tmp, wordSize); // tmp := tmp - wordSize
4284 movptr(index, tmp); // *index_adr := tmp
4285 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
4286
4287 // Record the previous value
4288 movptr(Address(tmp, 0), pre_val);
4289 jmp(done);
4290
4291 bind(runtime);
4292 // save the live input values
4293 if(tosca_live) push(rax);
4294
4295 if (obj != noreg && obj != rax)
4296 push(obj);
4297
4298 if (pre_val != rax)
4299 push(pre_val);
4300
4301 // Calling the runtime using the regular call_VM_leaf mechanism generates
4302 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
4303 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
4304 //
4305 // If we care generating the pre-barrier without a frame (e.g. in the
4306 // intrinsified Reference.get() routine) then ebp might be pointing to
4307 // the caller frame and so this check will most likely fail at runtime.
4308 //
4309 // Expanding the call directly bypasses the generation of the check.
4310 // So when we do not have have a full interpreter frame on the stack
4311 // expand_call should be passed true.
4312
4313 NOT_LP64( push(thread); )
4314
4315 if (expand_call) {
4316 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
4317 pass_arg1(this, thread);
4318 pass_arg0(this, pre_val);
4319 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
4320 } else {
4321 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
4322 }
4323
4324 NOT_LP64( pop(thread); )
4325
4326 // save the live input values
4327 if (pre_val != rax)
4328 pop(pre_val);
4329
4330 if (obj != noreg && obj != rax)
4331 pop(obj);
4332
4333 if(tosca_live) pop(rax);
4334
4335 bind(done);
4336 }
4337
4338 void MacroAssembler::g1_write_barrier_post(Register store_addr,
4339 Register new_val,
4340 Register thread,
4341 Register tmp,
4342 Register tmp2) {
4343 #ifdef _LP64
4344 assert(thread == r15_thread, "must be");
4345 #endif // _LP64
4346
4347 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4348 PtrQueue::byte_offset_of_index()));
4349 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
4350 PtrQueue::byte_offset_of_buf()));
4351
4352 CardTableModRefBS* ct =
4353 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
4354 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4355
4356 Label done;
4357 Label runtime;
4358
4359 // Does store cross heap regions?
4360
4361 movptr(tmp, store_addr);
4362 xorptr(tmp, new_val);
4363 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
4364 jcc(Assembler::equal, done);
4365
4366 // crosses regions, storing NULL?
4367
4368 cmpptr(new_val, (int32_t) NULL_WORD);
4369 jcc(Assembler::equal, done);
4370
4371 // storing region crossing non-NULL, is card already dirty?
4372
4373 const Register card_addr = tmp;
4374 const Register cardtable = tmp2;
4375
4376 movptr(card_addr, store_addr);
4377 shrptr(card_addr, CardTableModRefBS::card_shift);
4378 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
4379 // a valid address and therefore is not properly handled by the relocation code.
4380 movptr(cardtable, (intptr_t)ct->byte_map_base);
4381 addptr(card_addr, cardtable);
4382
4383 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
4384 jcc(Assembler::equal, done);
4385
4386 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
4387 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4388 jcc(Assembler::equal, done);
4389
4390
4391 // storing a region crossing, non-NULL oop, card is clean.
4392 // dirty card and log.
4393
4394 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
4395
4396 cmpl(queue_index, 0);
4397 jcc(Assembler::equal, runtime);
4398 subl(queue_index, wordSize);
4399 movptr(tmp2, buffer);
4400 #ifdef _LP64
4401 movslq(rscratch1, queue_index);
4402 addq(tmp2, rscratch1);
4403 movq(Address(tmp2, 0), card_addr);
4404 #else
4405 addl(tmp2, queue_index);
4406 movl(Address(tmp2, 0), card_addr);
4407 #endif
4408 jmp(done);
4409
4410 bind(runtime);
4411 // save the live input values
4412 push(store_addr);
4413 push(new_val);
4414 #ifdef _LP64
4415 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
4416 #else
4417 push(thread);
4418 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
4419 pop(thread);
4420 #endif
4421 pop(new_val);
4422 pop(store_addr);
4423
4424 bind(done);
4425 }
4426
4427 #endif // INCLUDE_ALL_GCS
4428 //////////////////////////////////////////////////////////////////////////////////
4429
4430
4431 void MacroAssembler::store_check(Register obj, Address dst) {
4432 store_check(obj);
4433 }
4434
4435 void MacroAssembler::store_check(Register obj) {
4436 // Does a store check for the oop in register obj. The content of
4437 // register obj is destroyed afterwards.
4438 BarrierSet* bs = Universe::heap()->barrier_set();
4439 assert(bs->kind() == BarrierSet::CardTableForRS ||
4440 bs->kind() == BarrierSet::CardTableExtension,
4441 "Wrong barrier set kind");
4442
4443 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
4444 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
4445
4446 shrptr(obj, CardTableModRefBS::card_shift);
4447
4448 Address card_addr;
4449
4450 // The calculation for byte_map_base is as follows:
4451 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
4452 // So this essentially converts an address to a displacement and it will
4453 // never need to be relocated. On 64bit however the value may be too
4454 // large for a 32bit displacement.
4455 intptr_t disp = (intptr_t) ct->byte_map_base;
4456 if (is_simm32(disp)) {
4457 card_addr = Address(noreg, obj, Address::times_1, disp);
4458 } else {
4459 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
4460 // displacement and done in a single instruction given favorable mapping and a
4461 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
4462 // entry and that entry is not properly handled by the relocation code.
4463 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
4464 Address index(noreg, obj, Address::times_1);
4465 card_addr = as_Address(ArrayAddress(cardtable, index));
4466 }
4467
4468 int dirty = CardTableModRefBS::dirty_card_val();
4469 if (UseCondCardMark) {
4470 Label L_already_dirty;
4471 if (UseConcMarkSweepGC) {
4472 membar(Assembler::StoreLoad);
4473 }
4474 cmpb(card_addr, dirty);
4475 jcc(Assembler::equal, L_already_dirty);
4476 movb(card_addr, dirty);
4477 bind(L_already_dirty);
4478 } else {
4479 movb(card_addr, dirty);
4480 }
4481 }
4482
4483 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4484 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4485 }
4486
4487 // Force generation of a 4 byte immediate value even if it fits into 8bit
4488 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4489 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4490 }
4491
4492 void MacroAssembler::subptr(Register dst, Register src) {
4493 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4494 }
4495
4496 // C++ bool manipulation
4497 void MacroAssembler::testbool(Register dst) {
4498 if(sizeof(bool) == 1)
4499 testb(dst, 0xff);
4500 else if(sizeof(bool) == 2) {
4501 // testw implementation needed for two byte bools
4502 ShouldNotReachHere();
4503 } else if(sizeof(bool) == 4)
4504 testl(dst, dst);
4505 else
4506 // unsupported
4507 ShouldNotReachHere();
4508 }
4509
4510 void MacroAssembler::testptr(Register dst, Register src) {
4511 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4512 }
4513
4514 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4515 void MacroAssembler::tlab_allocate(Register obj,
4516 Register var_size_in_bytes,
4517 int con_size_in_bytes,
4518 Register t1,
4519 Register t2,
4520 Label& slow_case) {
4521 assert_different_registers(obj, t1, t2);
4522 assert_different_registers(obj, var_size_in_bytes, t1);
4523 Register end = t2;
4524 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
4525
4526 verify_tlab();
4527
4528 NOT_LP64(get_thread(thread));
4529
4530 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
4531 if (var_size_in_bytes == noreg) {
4532 lea(end, Address(obj, con_size_in_bytes));
4533 } else {
4534 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
4535 }
4536 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
4537 jcc(Assembler::above, slow_case);
4538
4539 // update the tlab top pointer
4540 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
4541
4542 // recover var_size_in_bytes if necessary
4543 if (var_size_in_bytes == end) {
4544 subptr(var_size_in_bytes, obj);
4545 }
4546 verify_tlab();
4547 }
4548
4549 // Preserves rbx, and rdx.
4550 Register MacroAssembler::tlab_refill(Label& retry,
4551 Label& try_eden,
4552 Label& slow_case) {
4553 Register top = rax;
4554 Register t1 = rcx;
4555 Register t2 = rsi;
4556 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
4557 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
4558 Label do_refill, discard_tlab;
4559
4560 if (!Universe::heap()->supports_inline_contig_alloc()) {
4561 // No allocation in the shared eden.
4562 jmp(slow_case);
4563 }
4564
4565 NOT_LP64(get_thread(thread_reg));
4566
4567 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4568 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4569
4570 // calculate amount of free space
4571 subptr(t1, top);
4572 shrptr(t1, LogHeapWordSize);
4573
4574 // Retain tlab and allocate object in shared space if
4575 // the amount free in the tlab is too large to discard.
4576 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
4577 jcc(Assembler::lessEqual, discard_tlab);
4578
4579 // Retain
4580 // %%% yuck as movptr...
4581 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
4582 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
4583 if (TLABStats) {
4584 // increment number of slow_allocations
4585 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
4586 }
4587 jmp(try_eden);
4588
4589 bind(discard_tlab);
4590 if (TLABStats) {
4591 // increment number of refills
4592 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
4593 // accumulate wastage -- t1 is amount free in tlab
4594 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
4595 }
4596
4597 // if tlab is currently allocated (top or end != null) then
4598 // fill [top, end + alignment_reserve) with array object
4599 testptr(top, top);
4600 jcc(Assembler::zero, do_refill);
4601
4602 // set up the mark word
4603 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
4604 // set the length to the remaining space
4605 subptr(t1, typeArrayOopDesc::header_size(T_INT));
4606 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
4607 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
4608 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
4609 // set klass to intArrayKlass
4610 // dubious reloc why not an oop reloc?
4611 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
4612 // store klass last. concurrent gcs assumes klass length is valid if
4613 // klass field is not null.
4614 store_klass(top, t1);
4615
4616 movptr(t1, top);
4617 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4618 incr_allocated_bytes(thread_reg, t1, 0);
4619
4620 // refill the tlab with an eden allocation
4621 bind(do_refill);
4622 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4623 shlptr(t1, LogHeapWordSize);
4624 // allocate new tlab, address returned in top
4625 eden_allocate(top, t1, 0, t2, slow_case);
4626
4627 // Check that t1 was preserved in eden_allocate.
4628 #ifdef ASSERT
4629 if (UseTLAB) {
4630 Label ok;
4631 Register tsize = rsi;
4632 assert_different_registers(tsize, thread_reg, t1);
4633 push(tsize);
4634 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
4635 shlptr(tsize, LogHeapWordSize);
4636 cmpptr(t1, tsize);
4637 jcc(Assembler::equal, ok);
4638 STOP("assert(t1 != tlab size)");
4639 should_not_reach_here();
4640
4641 bind(ok);
4642 pop(tsize);
4643 }
4644 #endif
4645 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
4646 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
4647 addptr(top, t1);
4648 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
4649 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
4650 verify_tlab();
4651 jmp(retry);
4652
4653 return thread_reg; // for use by caller
4654 }
4655
4656 void MacroAssembler::incr_allocated_bytes(Register thread,
4657 Register var_size_in_bytes,
4658 int con_size_in_bytes,
4659 Register t1) {
4660 if (!thread->is_valid()) {
4661 #ifdef _LP64
4662 thread = r15_thread;
4663 #else
4664 assert(t1->is_valid(), "need temp reg");
4665 thread = t1;
4666 get_thread(thread);
4667 #endif
4668 }
4669
4670 #ifdef _LP64
4671 if (var_size_in_bytes->is_valid()) {
4672 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4673 } else {
4674 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4675 }
4676 #else
4677 if (var_size_in_bytes->is_valid()) {
4678 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
4679 } else {
4680 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
4681 }
4682 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
4683 #endif
4684 }
4685
4686 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
4687 pusha();
4688
4689 // if we are coming from c1, xmm registers may be live
4690 int off = 0;
4691 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8);
4692 if (UseAVX > 2) {
4693 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8);
4694 }
4695
4696 if (UseSSE == 1) {
4697 subptr(rsp, sizeof(jdouble)*8);
4698 for (int n = 0; n < 8; n++) {
4699 movflt(Address(rsp, off++*sizeof(jdouble)), as_XMMRegister(n));
4700 }
4701 } else if (UseSSE >= 2) {
4702 if (UseAVX > 2) {
4703 push(rbx);
4704 movl(rbx, 0xffff);
4705 kmovwl(k1, rbx);
4706 pop(rbx);
4707 }
4708 #ifdef COMPILER2
4709 if (MaxVectorSize > 16) {
4710 if(UseAVX > 2) {
4711 // Save upper half of ZMM registes
4712 subptr(rsp, 32*num_xmm_regs);
4713 for (int n = 0; n < num_xmm_regs; n++) {
4714 vextractf64x4h(Address(rsp, off++*32), as_XMMRegister(n));
4715 }
4716 off = 0;
4717 }
4718 assert(UseAVX > 0, "256 bit vectors are supported only with AVX");
4719 // Save upper half of YMM registes
4720 subptr(rsp, 16*num_xmm_regs);
4721 for (int n = 0; n < num_xmm_regs; n++) {
4722 vextractf128h(Address(rsp, off++*16), as_XMMRegister(n));
4723 }
4724 }
4725 #endif
4726 // Save whole 128bit (16 bytes) XMM registers
4727 subptr(rsp, 16*num_xmm_regs);
4728 off = 0;
4729 #ifdef _LP64
4730 if (VM_Version::supports_avx512novl()) {
4731 for (int n = 0; n < num_xmm_regs; n++) {
4732 vextractf32x4h(Address(rsp, off++*16), as_XMMRegister(n), 0);
4733 }
4734 } else {
4735 for (int n = 0; n < num_xmm_regs; n++) {
4736 movdqu(Address(rsp, off++*16), as_XMMRegister(n));
4737 }
4738 }
4739 #else
4740 for (int n = 0; n < num_xmm_regs; n++) {
4741 movdqu(Address(rsp, off++*16), as_XMMRegister(n));
4742 }
4743 #endif
4744 }
4745
4746 // Preserve registers across runtime call
4747 int incoming_argument_and_return_value_offset = -1;
4748 if (num_fpu_regs_in_use > 1) {
4749 // Must preserve all other FPU regs (could alternatively convert
4750 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
4751 // FPU state, but can not trust C compiler)
4752 NEEDS_CLEANUP;
4753 // NOTE that in this case we also push the incoming argument(s) to
4754 // the stack and restore it later; we also use this stack slot to
4755 // hold the return value from dsin, dcos etc.
4756 for (int i = 0; i < num_fpu_regs_in_use; i++) {
4757 subptr(rsp, sizeof(jdouble));
4758 fstp_d(Address(rsp, 0));
4759 }
4760 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
4761 for (int i = nb_args-1; i >= 0; i--) {
4762 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
4763 }
4764 }
4765
4766 subptr(rsp, nb_args*sizeof(jdouble));
4767 for (int i = 0; i < nb_args; i++) {
4768 fstp_d(Address(rsp, i*sizeof(jdouble)));
4769 }
4770
4771 #ifdef _LP64
4772 if (nb_args > 0) {
4773 movdbl(xmm0, Address(rsp, 0));
4774 }
4775 if (nb_args > 1) {
4776 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
4777 }
4778 assert(nb_args <= 2, "unsupported number of args");
4779 #endif // _LP64
4780
4781 // NOTE: we must not use call_VM_leaf here because that requires a
4782 // complete interpreter frame in debug mode -- same bug as 4387334
4783 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
4784 // do proper 64bit abi
4785
4786 NEEDS_CLEANUP;
4787 // Need to add stack banging before this runtime call if it needs to
4788 // be taken; however, there is no generic stack banging routine at
4789 // the MacroAssembler level
4790
4791 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
4792
4793 #ifdef _LP64
4794 movsd(Address(rsp, 0), xmm0);
4795 fld_d(Address(rsp, 0));
4796 #endif // _LP64
4797 addptr(rsp, sizeof(jdouble)*nb_args);
4798 if (num_fpu_regs_in_use > 1) {
4799 // Must save return value to stack and then restore entire FPU
4800 // stack except incoming arguments
4801 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
4802 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
4803 fld_d(Address(rsp, 0));
4804 addptr(rsp, sizeof(jdouble));
4805 }
4806 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
4807 addptr(rsp, sizeof(jdouble)*nb_args);
4808 }
4809
4810 off = 0;
4811 if (UseSSE == 1) {
4812 for (int n = 0; n < 8; n++) {
4813 movflt(as_XMMRegister(n), Address(rsp, off++*sizeof(jdouble)));
4814 }
4815 addptr(rsp, sizeof(jdouble)*8);
4816 } else if (UseSSE >= 2) {
4817 // Restore whole 128bit (16 bytes) XMM regiters
4818 #ifdef _LP64
4819 if (VM_Version::supports_avx512novl()) {
4820 for (int n = 0; n < num_xmm_regs; n++) {
4821 vinsertf32x4h(as_XMMRegister(n), Address(rsp, off++*16), 0);
4822 }
4823 }
4824 else {
4825 for (int n = 0; n < num_xmm_regs; n++) {
4826 movdqu(as_XMMRegister(n), Address(rsp, off++*16));
4827 }
4828 }
4829 #else
4830 for (int n = 0; n < num_xmm_regs; n++) {
4831 movdqu(as_XMMRegister(n), Address(rsp, off++ * 16));
4832 }
4833 #endif
4834 addptr(rsp, 16*num_xmm_regs);
4835
4836 #ifdef COMPILER2
4837 if (MaxVectorSize > 16) {
4838 // Restore upper half of YMM registes.
4839 off = 0;
4840 for (int n = 0; n < num_xmm_regs; n++) {
4841 vinsertf128h(as_XMMRegister(n), Address(rsp, off++*16));
4842 }
4843 addptr(rsp, 16*num_xmm_regs);
4844 if(UseAVX > 2) {
4845 off = 0;
4846 for (int n = 0; n < num_xmm_regs; n++) {
4847 vinsertf64x4h(as_XMMRegister(n), Address(rsp, off++*32));
4848 }
4849 addptr(rsp, 32*num_xmm_regs);
4850 }
4851 }
4852 #endif
4853 }
4854 popa();
4855 }
4856
4857 static const double pi_4 = 0.7853981633974483;
4858
4859 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
4860 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
4861 // was attempted in this code; unfortunately it appears that the
4862 // switch to 80-bit precision and back causes this to be
4863 // unprofitable compared with simply performing a runtime call if
4864 // the argument is out of the (-pi/4, pi/4) range.
4865
4866 Register tmp = noreg;
4867 if (!VM_Version::supports_cmov()) {
4868 // fcmp needs a temporary so preserve rbx,
4869 tmp = rbx;
4870 push(tmp);
4871 }
4872
4873 Label slow_case, done;
4874
4875 ExternalAddress pi4_adr = (address)&pi_4;
4876 if (reachable(pi4_adr)) {
4877 // x ?<= pi/4
4878 fld_d(pi4_adr);
4879 fld_s(1); // Stack: X PI/4 X
4880 fabs(); // Stack: |X| PI/4 X
4881 fcmp(tmp);
4882 jcc(Assembler::above, slow_case);
4883
4884 // fastest case: -pi/4 <= x <= pi/4
4885 switch(trig) {
4886 case 's':
4887 fsin();
4888 break;
4889 case 'c':
4890 fcos();
4891 break;
4892 case 't':
4893 ftan();
4894 break;
4895 default:
4896 assert(false, "bad intrinsic");
4897 break;
4898 }
4899 jmp(done);
4900 }
4901
4902 // slow case: runtime call
4903 bind(slow_case);
4904
4905 switch(trig) {
4906 case 's':
4907 {
4908 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
4909 }
4910 break;
4911 case 'c':
4912 {
4913 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
4914 }
4915 break;
4916 case 't':
4917 {
4918 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
4919 }
4920 break;
4921 default:
4922 assert(false, "bad intrinsic");
4923 break;
4924 }
4925
4926 // Come here with result in F-TOS
4927 bind(done);
4928
4929 if (tmp != noreg) {
4930 pop(tmp);
4931 }
4932 }
4933
4934
4935 // Look up the method for a megamorphic invokeinterface call.
4936 // The target method is determined by <intf_klass, itable_index>.
4937 // The receiver klass is in recv_klass.
4938 // On success, the result will be in method_result, and execution falls through.
4939 // On failure, execution transfers to the given label.
4940 void MacroAssembler::lookup_interface_method(Register recv_klass,
4941 Register intf_klass,
4942 RegisterOrConstant itable_index,
4943 Register method_result,
4944 Register scan_temp,
4945 Label& L_no_such_interface) {
4946 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
4947 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4948 "caller must use same register for non-constant itable index as for method");
4949
4950 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4951 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
4952 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4953 int scan_step = itableOffsetEntry::size() * wordSize;
4954 int vte_size = vtableEntry::size() * wordSize;
4955 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4956 assert(vte_size == wordSize, "else adjust times_vte_scale");
4957
4958 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
4959
4960 // %%% Could store the aligned, prescaled offset in the klassoop.
4961 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4962 if (HeapWordsPerLong > 1) {
4963 // Round up to align_object_offset boundary
4964 // see code for InstanceKlass::start_of_itable!
4965 round_to(scan_temp, BytesPerLong);
4966 }
4967
4968 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4969 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4970 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4971
4972 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4973 // if (scan->interface() == intf) {
4974 // result = (klass + scan->offset() + itable_index);
4975 // }
4976 // }
4977 Label search, found_method;
4978
4979 for (int peel = 1; peel >= 0; peel--) {
4980 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4981 cmpptr(intf_klass, method_result);
4982
4983 if (peel) {
4984 jccb(Assembler::equal, found_method);
4985 } else {
4986 jccb(Assembler::notEqual, search);
4987 // (invert the test to fall through to found_method...)
4988 }
4989
4990 if (!peel) break;
4991
4992 bind(search);
4993
4994 // Check that the previous entry is non-null. A null entry means that
4995 // the receiver class doesn't implement the interface, and wasn't the
4996 // same as when the caller was compiled.
4997 testptr(method_result, method_result);
4998 jcc(Assembler::zero, L_no_such_interface);
4999 addptr(scan_temp, scan_step);
5000 }
5001
5002 bind(found_method);
5003
5004 // Got a hit.
5005 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5006 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5007 }
5008
5009
5010 // virtual method calling
5011 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5012 RegisterOrConstant vtable_index,
5013 Register method_result) {
5014 const int base = InstanceKlass::vtable_start_offset() * wordSize;
5015 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5016 Address vtable_entry_addr(recv_klass,
5017 vtable_index, Address::times_ptr,
5018 base + vtableEntry::method_offset_in_bytes());
5019 movptr(method_result, vtable_entry_addr);
5020 }
5021
5022
5023 void MacroAssembler::check_klass_subtype(Register sub_klass,
5024 Register super_klass,
5025 Register temp_reg,
5026 Label& L_success) {
5027 Label L_failure;
5028 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5029 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5030 bind(L_failure);
5031 }
5032
5033
5034 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5035 Register super_klass,
5036 Register temp_reg,
5037 Label* L_success,
5038 Label* L_failure,
5039 Label* L_slow_path,
5040 RegisterOrConstant super_check_offset) {
5041 assert_different_registers(sub_klass, super_klass, temp_reg);
5042 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5043 if (super_check_offset.is_register()) {
5044 assert_different_registers(sub_klass, super_klass,
5045 super_check_offset.as_register());
5046 } else if (must_load_sco) {
5047 assert(temp_reg != noreg, "supply either a temp or a register offset");
5048 }
5049
5050 Label L_fallthrough;
5051 int label_nulls = 0;
5052 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5053 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5054 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5055 assert(label_nulls <= 1, "at most one NULL in the batch");
5056
5057 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5058 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5059 Address super_check_offset_addr(super_klass, sco_offset);
5060
5061 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5062 // range of a jccb. If this routine grows larger, reconsider at
5063 // least some of these.
5064 #define local_jcc(assembler_cond, label) \
5065 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5066 else jcc( assembler_cond, label) /*omit semi*/
5067
5068 // Hacked jmp, which may only be used just before L_fallthrough.
5069 #define final_jmp(label) \
5070 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5071 else jmp(label) /*omit semi*/
5072
5073 // If the pointers are equal, we are done (e.g., String[] elements).
5074 // This self-check enables sharing of secondary supertype arrays among
5075 // non-primary types such as array-of-interface. Otherwise, each such
5076 // type would need its own customized SSA.
5077 // We move this check to the front of the fast path because many
5078 // type checks are in fact trivially successful in this manner,
5079 // so we get a nicely predicted branch right at the start of the check.
5080 cmpptr(sub_klass, super_klass);
5081 local_jcc(Assembler::equal, *L_success);
5082
5083 // Check the supertype display:
5084 if (must_load_sco) {
5085 // Positive movl does right thing on LP64.
5086 movl(temp_reg, super_check_offset_addr);
5087 super_check_offset = RegisterOrConstant(temp_reg);
5088 }
5089 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5090 cmpptr(super_klass, super_check_addr); // load displayed supertype
5091
5092 // This check has worked decisively for primary supers.
5093 // Secondary supers are sought in the super_cache ('super_cache_addr').
5094 // (Secondary supers are interfaces and very deeply nested subtypes.)
5095 // This works in the same check above because of a tricky aliasing
5096 // between the super_cache and the primary super display elements.
5097 // (The 'super_check_addr' can address either, as the case requires.)
5098 // Note that the cache is updated below if it does not help us find
5099 // what we need immediately.
5100 // So if it was a primary super, we can just fail immediately.
5101 // Otherwise, it's the slow path for us (no success at this point).
5102
5103 if (super_check_offset.is_register()) {
5104 local_jcc(Assembler::equal, *L_success);
5105 cmpl(super_check_offset.as_register(), sc_offset);
5106 if (L_failure == &L_fallthrough) {
5107 local_jcc(Assembler::equal, *L_slow_path);
5108 } else {
5109 local_jcc(Assembler::notEqual, *L_failure);
5110 final_jmp(*L_slow_path);
5111 }
5112 } else if (super_check_offset.as_constant() == sc_offset) {
5113 // Need a slow path; fast failure is impossible.
5114 if (L_slow_path == &L_fallthrough) {
5115 local_jcc(Assembler::equal, *L_success);
5116 } else {
5117 local_jcc(Assembler::notEqual, *L_slow_path);
5118 final_jmp(*L_success);
5119 }
5120 } else {
5121 // No slow path; it's a fast decision.
5122 if (L_failure == &L_fallthrough) {
5123 local_jcc(Assembler::equal, *L_success);
5124 } else {
5125 local_jcc(Assembler::notEqual, *L_failure);
5126 final_jmp(*L_success);
5127 }
5128 }
5129
5130 bind(L_fallthrough);
5131
5132 #undef local_jcc
5133 #undef final_jmp
5134 }
5135
5136
5137 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5138 Register super_klass,
5139 Register temp_reg,
5140 Register temp2_reg,
5141 Label* L_success,
5142 Label* L_failure,
5143 bool set_cond_codes) {
5144 assert_different_registers(sub_klass, super_klass, temp_reg);
5145 if (temp2_reg != noreg)
5146 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5147 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5148
5149 Label L_fallthrough;
5150 int label_nulls = 0;
5151 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5152 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5153 assert(label_nulls <= 1, "at most one NULL in the batch");
5154
5155 // a couple of useful fields in sub_klass:
5156 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5157 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5158 Address secondary_supers_addr(sub_klass, ss_offset);
5159 Address super_cache_addr( sub_klass, sc_offset);
5160
5161 // Do a linear scan of the secondary super-klass chain.
5162 // This code is rarely used, so simplicity is a virtue here.
5163 // The repne_scan instruction uses fixed registers, which we must spill.
5164 // Don't worry too much about pre-existing connections with the input regs.
5165
5166 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5167 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5168
5169 // Get super_klass value into rax (even if it was in rdi or rcx).
5170 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5171 if (super_klass != rax || UseCompressedOops) {
5172 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5173 mov(rax, super_klass);
5174 }
5175 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5176 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5177
5178 #ifndef PRODUCT
5179 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5180 ExternalAddress pst_counter_addr((address) pst_counter);
5181 NOT_LP64( incrementl(pst_counter_addr) );
5182 LP64_ONLY( lea(rcx, pst_counter_addr) );
5183 LP64_ONLY( incrementl(Address(rcx, 0)) );
5184 #endif //PRODUCT
5185
5186 // We will consult the secondary-super array.
5187 movptr(rdi, secondary_supers_addr);
5188 // Load the array length. (Positive movl does right thing on LP64.)
5189 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5190 // Skip to start of data.
5191 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5192
5193 // Scan RCX words at [RDI] for an occurrence of RAX.
5194 // Set NZ/Z based on last compare.
5195 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5196 // not change flags (only scas instruction which is repeated sets flags).
5197 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5198
5199 testptr(rax,rax); // Set Z = 0
5200 repne_scan();
5201
5202 // Unspill the temp. registers:
5203 if (pushed_rdi) pop(rdi);
5204 if (pushed_rcx) pop(rcx);
5205 if (pushed_rax) pop(rax);
5206
5207 if (set_cond_codes) {
5208 // Special hack for the AD files: rdi is guaranteed non-zero.
5209 assert(!pushed_rdi, "rdi must be left non-NULL");
5210 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5211 }
5212
5213 if (L_failure == &L_fallthrough)
5214 jccb(Assembler::notEqual, *L_failure);
5215 else jcc(Assembler::notEqual, *L_failure);
5216
5217 // Success. Cache the super we found and proceed in triumph.
5218 movptr(super_cache_addr, super_klass);
5219
5220 if (L_success != &L_fallthrough) {
5221 jmp(*L_success);
5222 }
5223
5224 #undef IS_A_TEMP
5225
5226 bind(L_fallthrough);
5227 }
5228
5229
5230 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5231 if (VM_Version::supports_cmov()) {
5232 cmovl(cc, dst, src);
5233 } else {
5234 Label L;
5235 jccb(negate_condition(cc), L);
5236 movl(dst, src);
5237 bind(L);
5238 }
5239 }
5240
5241 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5242 if (VM_Version::supports_cmov()) {
5243 cmovl(cc, dst, src);
5244 } else {
5245 Label L;
5246 jccb(negate_condition(cc), L);
5247 movl(dst, src);
5248 bind(L);
5249 }
5250 }
5251
5252 void MacroAssembler::verify_oop(Register reg, const char* s) {
5253 if (!VerifyOops) return;
5254
5255 // Pass register number to verify_oop_subroutine
5256 const char* b = NULL;
5257 {
5258 ResourceMark rm;
5259 stringStream ss;
5260 ss.print("verify_oop: %s: %s", reg->name(), s);
5261 b = code_string(ss.as_string());
5262 }
5263 BLOCK_COMMENT("verify_oop {");
5264 #ifdef _LP64
5265 push(rscratch1); // save r10, trashed by movptr()
5266 #endif
5267 push(rax); // save rax,
5268 push(reg); // pass register argument
5269 ExternalAddress buffer((address) b);
5270 // avoid using pushptr, as it modifies scratch registers
5271 // and our contract is not to modify anything
5272 movptr(rax, buffer.addr());
5273 push(rax);
5274 // call indirectly to solve generation ordering problem
5275 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5276 call(rax);
5277 // Caller pops the arguments (oop, message) and restores rax, r10
5278 BLOCK_COMMENT("} verify_oop");
5279 }
5280
5281
5282 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
5283 Register tmp,
5284 int offset) {
5285 intptr_t value = *delayed_value_addr;
5286 if (value != 0)
5287 return RegisterOrConstant(value + offset);
5288
5289 // load indirectly to solve generation ordering problem
5290 movptr(tmp, ExternalAddress((address) delayed_value_addr));
5291
5292 #ifdef ASSERT
5293 { Label L;
5294 testptr(tmp, tmp);
5295 if (WizardMode) {
5296 const char* buf = NULL;
5297 {
5298 ResourceMark rm;
5299 stringStream ss;
5300 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
5301 buf = code_string(ss.as_string());
5302 }
5303 jcc(Assembler::notZero, L);
5304 STOP(buf);
5305 } else {
5306 jccb(Assembler::notZero, L);
5307 hlt();
5308 }
5309 bind(L);
5310 }
5311 #endif
5312
5313 if (offset != 0)
5314 addptr(tmp, offset);
5315
5316 return RegisterOrConstant(tmp);
5317 }
5318
5319
5320 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5321 int extra_slot_offset) {
5322 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5323 int stackElementSize = Interpreter::stackElementSize;
5324 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5325 #ifdef ASSERT
5326 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5327 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5328 #endif
5329 Register scale_reg = noreg;
5330 Address::ScaleFactor scale_factor = Address::no_scale;
5331 if (arg_slot.is_constant()) {
5332 offset += arg_slot.as_constant() * stackElementSize;
5333 } else {
5334 scale_reg = arg_slot.as_register();
5335 scale_factor = Address::times(stackElementSize);
5336 }
5337 offset += wordSize; // return PC is on stack
5338 return Address(rsp, scale_reg, scale_factor, offset);
5339 }
5340
5341
5342 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
5343 if (!VerifyOops) return;
5344
5345 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
5346 // Pass register number to verify_oop_subroutine
5347 const char* b = NULL;
5348 {
5349 ResourceMark rm;
5350 stringStream ss;
5351 ss.print("verify_oop_addr: %s", s);
5352 b = code_string(ss.as_string());
5353 }
5354 #ifdef _LP64
5355 push(rscratch1); // save r10, trashed by movptr()
5356 #endif
5357 push(rax); // save rax,
5358 // addr may contain rsp so we will have to adjust it based on the push
5359 // we just did (and on 64 bit we do two pushes)
5360 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5361 // stores rax into addr which is backwards of what was intended.
5362 if (addr.uses(rsp)) {
5363 lea(rax, addr);
5364 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5365 } else {
5366 pushptr(addr);
5367 }
5368
5369 ExternalAddress buffer((address) b);
5370 // pass msg argument
5371 // avoid using pushptr, as it modifies scratch registers
5372 // and our contract is not to modify anything
5373 movptr(rax, buffer.addr());
5374 push(rax);
5375
5376 // call indirectly to solve generation ordering problem
5377 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5378 call(rax);
5379 // Caller pops the arguments (addr, message) and restores rax, r10.
5380 }
5381
5382 void MacroAssembler::verify_tlab() {
5383 #ifdef ASSERT
5384 if (UseTLAB && VerifyOops) {
5385 Label next, ok;
5386 Register t1 = rsi;
5387 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5388
5389 push(t1);
5390 NOT_LP64(push(thread_reg));
5391 NOT_LP64(get_thread(thread_reg));
5392
5393 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5394 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5395 jcc(Assembler::aboveEqual, next);
5396 STOP("assert(top >= start)");
5397 should_not_reach_here();
5398
5399 bind(next);
5400 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5401 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5402 jcc(Assembler::aboveEqual, ok);
5403 STOP("assert(top <= end)");
5404 should_not_reach_here();
5405
5406 bind(ok);
5407 NOT_LP64(pop(thread_reg));
5408 pop(t1);
5409 }
5410 #endif
5411 }
5412
5413 class ControlWord {
5414 public:
5415 int32_t _value;
5416
5417 int rounding_control() const { return (_value >> 10) & 3 ; }
5418 int precision_control() const { return (_value >> 8) & 3 ; }
5419 bool precision() const { return ((_value >> 5) & 1) != 0; }
5420 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5421 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5422 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5423 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5424 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5425
5426 void print() const {
5427 // rounding control
5428 const char* rc;
5429 switch (rounding_control()) {
5430 case 0: rc = "round near"; break;
5431 case 1: rc = "round down"; break;
5432 case 2: rc = "round up "; break;
5433 case 3: rc = "chop "; break;
5434 };
5435 // precision control
5436 const char* pc;
5437 switch (precision_control()) {
5438 case 0: pc = "24 bits "; break;
5439 case 1: pc = "reserved"; break;
5440 case 2: pc = "53 bits "; break;
5441 case 3: pc = "64 bits "; break;
5442 };
5443 // flags
5444 char f[9];
5445 f[0] = ' ';
5446 f[1] = ' ';
5447 f[2] = (precision ()) ? 'P' : 'p';
5448 f[3] = (underflow ()) ? 'U' : 'u';
5449 f[4] = (overflow ()) ? 'O' : 'o';
5450 f[5] = (zero_divide ()) ? 'Z' : 'z';
5451 f[6] = (denormalized()) ? 'D' : 'd';
5452 f[7] = (invalid ()) ? 'I' : 'i';
5453 f[8] = '\x0';
5454 // output
5455 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5456 }
5457
5458 };
5459
5460 class StatusWord {
5461 public:
5462 int32_t _value;
5463
5464 bool busy() const { return ((_value >> 15) & 1) != 0; }
5465 bool C3() const { return ((_value >> 14) & 1) != 0; }
5466 bool C2() const { return ((_value >> 10) & 1) != 0; }
5467 bool C1() const { return ((_value >> 9) & 1) != 0; }
5468 bool C0() const { return ((_value >> 8) & 1) != 0; }
5469 int top() const { return (_value >> 11) & 7 ; }
5470 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5471 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5472 bool precision() const { return ((_value >> 5) & 1) != 0; }
5473 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5474 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5475 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5476 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5477 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5478
5479 void print() const {
5480 // condition codes
5481 char c[5];
5482 c[0] = (C3()) ? '3' : '-';
5483 c[1] = (C2()) ? '2' : '-';
5484 c[2] = (C1()) ? '1' : '-';
5485 c[3] = (C0()) ? '0' : '-';
5486 c[4] = '\x0';
5487 // flags
5488 char f[9];
5489 f[0] = (error_status()) ? 'E' : '-';
5490 f[1] = (stack_fault ()) ? 'S' : '-';
5491 f[2] = (precision ()) ? 'P' : '-';
5492 f[3] = (underflow ()) ? 'U' : '-';
5493 f[4] = (overflow ()) ? 'O' : '-';
5494 f[5] = (zero_divide ()) ? 'Z' : '-';
5495 f[6] = (denormalized()) ? 'D' : '-';
5496 f[7] = (invalid ()) ? 'I' : '-';
5497 f[8] = '\x0';
5498 // output
5499 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5500 }
5501
5502 };
5503
5504 class TagWord {
5505 public:
5506 int32_t _value;
5507
5508 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5509
5510 void print() const {
5511 printf("%04x", _value & 0xFFFF);
5512 }
5513
5514 };
5515
5516 class FPU_Register {
5517 public:
5518 int32_t _m0;
5519 int32_t _m1;
5520 int16_t _ex;
5521
5522 bool is_indefinite() const {
5523 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5524 }
5525
5526 void print() const {
5527 char sign = (_ex < 0) ? '-' : '+';
5528 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5529 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5530 };
5531
5532 };
5533
5534 class FPU_State {
5535 public:
5536 enum {
5537 register_size = 10,
5538 number_of_registers = 8,
5539 register_mask = 7
5540 };
5541
5542 ControlWord _control_word;
5543 StatusWord _status_word;
5544 TagWord _tag_word;
5545 int32_t _error_offset;
5546 int32_t _error_selector;
5547 int32_t _data_offset;
5548 int32_t _data_selector;
5549 int8_t _register[register_size * number_of_registers];
5550
5551 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5552 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5553
5554 const char* tag_as_string(int tag) const {
5555 switch (tag) {
5556 case 0: return "valid";
5557 case 1: return "zero";
5558 case 2: return "special";
5559 case 3: return "empty";
5560 }
5561 ShouldNotReachHere();
5562 return NULL;
5563 }
5564
5565 void print() const {
5566 // print computation registers
5567 { int t = _status_word.top();
5568 for (int i = 0; i < number_of_registers; i++) {
5569 int j = (i - t) & register_mask;
5570 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5571 st(j)->print();
5572 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5573 }
5574 }
5575 printf("\n");
5576 // print control registers
5577 printf("ctrl = "); _control_word.print(); printf("\n");
5578 printf("stat = "); _status_word .print(); printf("\n");
5579 printf("tags = "); _tag_word .print(); printf("\n");
5580 }
5581
5582 };
5583
5584 class Flag_Register {
5585 public:
5586 int32_t _value;
5587
5588 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5589 bool direction() const { return ((_value >> 10) & 1) != 0; }
5590 bool sign() const { return ((_value >> 7) & 1) != 0; }
5591 bool zero() const { return ((_value >> 6) & 1) != 0; }
5592 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5593 bool parity() const { return ((_value >> 2) & 1) != 0; }
5594 bool carry() const { return ((_value >> 0) & 1) != 0; }
5595
5596 void print() const {
5597 // flags
5598 char f[8];
5599 f[0] = (overflow ()) ? 'O' : '-';
5600 f[1] = (direction ()) ? 'D' : '-';
5601 f[2] = (sign ()) ? 'S' : '-';
5602 f[3] = (zero ()) ? 'Z' : '-';
5603 f[4] = (auxiliary_carry()) ? 'A' : '-';
5604 f[5] = (parity ()) ? 'P' : '-';
5605 f[6] = (carry ()) ? 'C' : '-';
5606 f[7] = '\x0';
5607 // output
5608 printf("%08x flags = %s", _value, f);
5609 }
5610
5611 };
5612
5613 class IU_Register {
5614 public:
5615 int32_t _value;
5616
5617 void print() const {
5618 printf("%08x %11d", _value, _value);
5619 }
5620
5621 };
5622
5623 class IU_State {
5624 public:
5625 Flag_Register _eflags;
5626 IU_Register _rdi;
5627 IU_Register _rsi;
5628 IU_Register _rbp;
5629 IU_Register _rsp;
5630 IU_Register _rbx;
5631 IU_Register _rdx;
5632 IU_Register _rcx;
5633 IU_Register _rax;
5634
5635 void print() const {
5636 // computation registers
5637 printf("rax, = "); _rax.print(); printf("\n");
5638 printf("rbx, = "); _rbx.print(); printf("\n");
5639 printf("rcx = "); _rcx.print(); printf("\n");
5640 printf("rdx = "); _rdx.print(); printf("\n");
5641 printf("rdi = "); _rdi.print(); printf("\n");
5642 printf("rsi = "); _rsi.print(); printf("\n");
5643 printf("rbp, = "); _rbp.print(); printf("\n");
5644 printf("rsp = "); _rsp.print(); printf("\n");
5645 printf("\n");
5646 // control registers
5647 printf("flgs = "); _eflags.print(); printf("\n");
5648 }
5649 };
5650
5651
5652 class CPU_State {
5653 public:
5654 FPU_State _fpu_state;
5655 IU_State _iu_state;
5656
5657 void print() const {
5658 printf("--------------------------------------------------\n");
5659 _iu_state .print();
5660 printf("\n");
5661 _fpu_state.print();
5662 printf("--------------------------------------------------\n");
5663 }
5664
5665 };
5666
5667
5668 static void _print_CPU_state(CPU_State* state) {
5669 state->print();
5670 };
5671
5672
5673 void MacroAssembler::print_CPU_state() {
5674 push_CPU_state();
5675 push(rsp); // pass CPU state
5676 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5677 addptr(rsp, wordSize); // discard argument
5678 pop_CPU_state();
5679 }
5680
5681
5682 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5683 static int counter = 0;
5684 FPU_State* fs = &state->_fpu_state;
5685 counter++;
5686 // For leaf calls, only verify that the top few elements remain empty.
5687 // We only need 1 empty at the top for C2 code.
5688 if( stack_depth < 0 ) {
5689 if( fs->tag_for_st(7) != 3 ) {
5690 printf("FPR7 not empty\n");
5691 state->print();
5692 assert(false, "error");
5693 return false;
5694 }
5695 return true; // All other stack states do not matter
5696 }
5697
5698 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5699 "bad FPU control word");
5700
5701 // compute stack depth
5702 int i = 0;
5703 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5704 int d = i;
5705 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5706 // verify findings
5707 if (i != FPU_State::number_of_registers) {
5708 // stack not contiguous
5709 printf("%s: stack not contiguous at ST%d\n", s, i);
5710 state->print();
5711 assert(false, "error");
5712 return false;
5713 }
5714 // check if computed stack depth corresponds to expected stack depth
5715 if (stack_depth < 0) {
5716 // expected stack depth is -stack_depth or less
5717 if (d > -stack_depth) {
5718 // too many elements on the stack
5719 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5720 state->print();
5721 assert(false, "error");
5722 return false;
5723 }
5724 } else {
5725 // expected stack depth is stack_depth
5726 if (d != stack_depth) {
5727 // wrong stack depth
5728 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5729 state->print();
5730 assert(false, "error");
5731 return false;
5732 }
5733 }
5734 // everything is cool
5735 return true;
5736 }
5737
5738
5739 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5740 if (!VerifyFPU) return;
5741 push_CPU_state();
5742 push(rsp); // pass CPU state
5743 ExternalAddress msg((address) s);
5744 // pass message string s
5745 pushptr(msg.addr());
5746 push(stack_depth); // pass stack depth
5747 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5748 addptr(rsp, 3 * wordSize); // discard arguments
5749 // check for error
5750 { Label L;
5751 testl(rax, rax);
5752 jcc(Assembler::notZero, L);
5753 int3(); // break if error condition
5754 bind(L);
5755 }
5756 pop_CPU_state();
5757 }
5758
5759 void MacroAssembler::restore_cpu_control_state_after_jni() {
5760 // Either restore the MXCSR register after returning from the JNI Call
5761 // or verify that it wasn't changed (with -Xcheck:jni flag).
5762 if (VM_Version::supports_sse()) {
5763 if (RestoreMXCSROnJNICalls) {
5764 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5765 } else if (CheckJNICalls) {
5766 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5767 }
5768 }
5769 if (VM_Version::supports_avx()) {
5770 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5771 vzeroupper();
5772 }
5773
5774 #ifndef _LP64
5775 // Either restore the x87 floating pointer control word after returning
5776 // from the JNI call or verify that it wasn't changed.
5777 if (CheckJNICalls) {
5778 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5779 }
5780 #endif // _LP64
5781 }
5782
5783
5784 void MacroAssembler::load_klass(Register dst, Register src) {
5785 #ifdef _LP64
5786 if (UseCompressedClassPointers) {
5787 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5788 decode_klass_not_null(dst);
5789 } else
5790 #endif
5791 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5792 }
5793
5794 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5795 load_klass(dst, src);
5796 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5797 }
5798
5799 void MacroAssembler::store_klass(Register dst, Register src) {
5800 #ifdef _LP64
5801 if (UseCompressedClassPointers) {
5802 encode_klass_not_null(src);
5803 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5804 } else
5805 #endif
5806 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5807 }
5808
5809 void MacroAssembler::load_heap_oop(Register dst, Address src) {
5810 #ifdef _LP64
5811 // FIXME: Must change all places where we try to load the klass.
5812 if (UseCompressedOops) {
5813 movl(dst, src);
5814 decode_heap_oop(dst);
5815 } else
5816 #endif
5817 movptr(dst, src);
5818 }
5819
5820 // Doesn't do verfication, generates fixed size code
5821 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
5822 #ifdef _LP64
5823 if (UseCompressedOops) {
5824 movl(dst, src);
5825 decode_heap_oop_not_null(dst);
5826 } else
5827 #endif
5828 movptr(dst, src);
5829 }
5830
5831 void MacroAssembler::store_heap_oop(Address dst, Register src) {
5832 #ifdef _LP64
5833 if (UseCompressedOops) {
5834 assert(!dst.uses(src), "not enough registers");
5835 encode_heap_oop(src);
5836 movl(dst, src);
5837 } else
5838 #endif
5839 movptr(dst, src);
5840 }
5841
5842 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
5843 assert_different_registers(src1, tmp);
5844 #ifdef _LP64
5845 if (UseCompressedOops) {
5846 bool did_push = false;
5847 if (tmp == noreg) {
5848 tmp = rax;
5849 push(tmp);
5850 did_push = true;
5851 assert(!src2.uses(rsp), "can't push");
5852 }
5853 load_heap_oop(tmp, src2);
5854 cmpptr(src1, tmp);
5855 if (did_push) pop(tmp);
5856 } else
5857 #endif
5858 cmpptr(src1, src2);
5859 }
5860
5861 // Used for storing NULLs.
5862 void MacroAssembler::store_heap_oop_null(Address dst) {
5863 #ifdef _LP64
5864 if (UseCompressedOops) {
5865 movl(dst, (int32_t)NULL_WORD);
5866 } else {
5867 movslq(dst, (int32_t)NULL_WORD);
5868 }
5869 #else
5870 movl(dst, (int32_t)NULL_WORD);
5871 #endif
5872 }
5873
5874 #ifdef _LP64
5875 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5876 if (UseCompressedClassPointers) {
5877 // Store to klass gap in destination
5878 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5879 }
5880 }
5881
5882 #ifdef ASSERT
5883 void MacroAssembler::verify_heapbase(const char* msg) {
5884 assert (UseCompressedOops, "should be compressed");
5885 assert (Universe::heap() != NULL, "java heap should be initialized");
5886 if (CheckCompressedOops) {
5887 Label ok;
5888 push(rscratch1); // cmpptr trashes rscratch1
5889 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
5890 jcc(Assembler::equal, ok);
5891 STOP(msg);
5892 bind(ok);
5893 pop(rscratch1);
5894 }
5895 }
5896 #endif
5897
5898 // Algorithm must match oop.inline.hpp encode_heap_oop.
5899 void MacroAssembler::encode_heap_oop(Register r) {
5900 #ifdef ASSERT
5901 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5902 #endif
5903 verify_oop(r, "broken oop in encode_heap_oop");
5904 if (Universe::narrow_oop_base() == NULL) {
5905 if (Universe::narrow_oop_shift() != 0) {
5906 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5907 shrq(r, LogMinObjAlignmentInBytes);
5908 }
5909 return;
5910 }
5911 testq(r, r);
5912 cmovq(Assembler::equal, r, r12_heapbase);
5913 subq(r, r12_heapbase);
5914 shrq(r, LogMinObjAlignmentInBytes);
5915 }
5916
5917 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5918 #ifdef ASSERT
5919 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5920 if (CheckCompressedOops) {
5921 Label ok;
5922 testq(r, r);
5923 jcc(Assembler::notEqual, ok);
5924 STOP("null oop passed to encode_heap_oop_not_null");
5925 bind(ok);
5926 }
5927 #endif
5928 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5929 if (Universe::narrow_oop_base() != NULL) {
5930 subq(r, r12_heapbase);
5931 }
5932 if (Universe::narrow_oop_shift() != 0) {
5933 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5934 shrq(r, LogMinObjAlignmentInBytes);
5935 }
5936 }
5937
5938 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5939 #ifdef ASSERT
5940 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5941 if (CheckCompressedOops) {
5942 Label ok;
5943 testq(src, src);
5944 jcc(Assembler::notEqual, ok);
5945 STOP("null oop passed to encode_heap_oop_not_null2");
5946 bind(ok);
5947 }
5948 #endif
5949 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5950 if (dst != src) {
5951 movq(dst, src);
5952 }
5953 if (Universe::narrow_oop_base() != NULL) {
5954 subq(dst, r12_heapbase);
5955 }
5956 if (Universe::narrow_oop_shift() != 0) {
5957 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5958 shrq(dst, LogMinObjAlignmentInBytes);
5959 }
5960 }
5961
5962 void MacroAssembler::decode_heap_oop(Register r) {
5963 #ifdef ASSERT
5964 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5965 #endif
5966 if (Universe::narrow_oop_base() == NULL) {
5967 if (Universe::narrow_oop_shift() != 0) {
5968 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5969 shlq(r, LogMinObjAlignmentInBytes);
5970 }
5971 } else {
5972 Label done;
5973 shlq(r, LogMinObjAlignmentInBytes);
5974 jccb(Assembler::equal, done);
5975 addq(r, r12_heapbase);
5976 bind(done);
5977 }
5978 verify_oop(r, "broken oop in decode_heap_oop");
5979 }
5980
5981 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5982 // Note: it will change flags
5983 assert (UseCompressedOops, "should only be used for compressed headers");
5984 assert (Universe::heap() != NULL, "java heap should be initialized");
5985 // Cannot assert, unverified entry point counts instructions (see .ad file)
5986 // vtableStubs also counts instructions in pd_code_size_limit.
5987 // Also do not verify_oop as this is called by verify_oop.
5988 if (Universe::narrow_oop_shift() != 0) {
5989 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
5990 shlq(r, LogMinObjAlignmentInBytes);
5991 if (Universe::narrow_oop_base() != NULL) {
5992 addq(r, r12_heapbase);
5993 }
5994 } else {
5995 assert (Universe::narrow_oop_base() == NULL, "sanity");
5996 }
5997 }
5998
5999 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6000 // Note: it will change flags
6001 assert (UseCompressedOops, "should only be used for compressed headers");
6002 assert (Universe::heap() != NULL, "java heap should be initialized");
6003 // Cannot assert, unverified entry point counts instructions (see .ad file)
6004 // vtableStubs also counts instructions in pd_code_size_limit.
6005 // Also do not verify_oop as this is called by verify_oop.
6006 if (Universe::narrow_oop_shift() != 0) {
6007 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6008 if (LogMinObjAlignmentInBytes == Address::times_8) {
6009 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6010 } else {
6011 if (dst != src) {
6012 movq(dst, src);
6013 }
6014 shlq(dst, LogMinObjAlignmentInBytes);
6015 if (Universe::narrow_oop_base() != NULL) {
6016 addq(dst, r12_heapbase);
6017 }
6018 }
6019 } else {
6020 assert (Universe::narrow_oop_base() == NULL, "sanity");
6021 if (dst != src) {
6022 movq(dst, src);
6023 }
6024 }
6025 }
6026
6027 void MacroAssembler::encode_klass_not_null(Register r) {
6028 if (Universe::narrow_klass_base() != NULL) {
6029 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6030 assert(r != r12_heapbase, "Encoding a klass in r12");
6031 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6032 subq(r, r12_heapbase);
6033 }
6034 if (Universe::narrow_klass_shift() != 0) {
6035 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6036 shrq(r, LogKlassAlignmentInBytes);
6037 }
6038 if (Universe::narrow_klass_base() != NULL) {
6039 reinit_heapbase();
6040 }
6041 }
6042
6043 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6044 if (dst == src) {
6045 encode_klass_not_null(src);
6046 } else {
6047 if (Universe::narrow_klass_base() != NULL) {
6048 mov64(dst, (int64_t)Universe::narrow_klass_base());
6049 negq(dst);
6050 addq(dst, src);
6051 } else {
6052 movptr(dst, src);
6053 }
6054 if (Universe::narrow_klass_shift() != 0) {
6055 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6056 shrq(dst, LogKlassAlignmentInBytes);
6057 }
6058 }
6059 }
6060
6061 // Function instr_size_for_decode_klass_not_null() counts the instructions
6062 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6063 // when (Universe::heap() != NULL). Hence, if the instructions they
6064 // generate change, then this method needs to be updated.
6065 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6066 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6067 if (Universe::narrow_klass_base() != NULL) {
6068 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6069 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6070 } else {
6071 // longest load decode klass function, mov64, leaq
6072 return 16;
6073 }
6074 }
6075
6076 // !!! If the instructions that get generated here change then function
6077 // instr_size_for_decode_klass_not_null() needs to get updated.
6078 void MacroAssembler::decode_klass_not_null(Register r) {
6079 // Note: it will change flags
6080 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6081 assert(r != r12_heapbase, "Decoding a klass in r12");
6082 // Cannot assert, unverified entry point counts instructions (see .ad file)
6083 // vtableStubs also counts instructions in pd_code_size_limit.
6084 // Also do not verify_oop as this is called by verify_oop.
6085 if (Universe::narrow_klass_shift() != 0) {
6086 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6087 shlq(r, LogKlassAlignmentInBytes);
6088 }
6089 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6090 if (Universe::narrow_klass_base() != NULL) {
6091 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6092 addq(r, r12_heapbase);
6093 reinit_heapbase();
6094 }
6095 }
6096
6097 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6098 // Note: it will change flags
6099 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6100 if (dst == src) {
6101 decode_klass_not_null(dst);
6102 } else {
6103 // Cannot assert, unverified entry point counts instructions (see .ad file)
6104 // vtableStubs also counts instructions in pd_code_size_limit.
6105 // Also do not verify_oop as this is called by verify_oop.
6106 mov64(dst, (int64_t)Universe::narrow_klass_base());
6107 if (Universe::narrow_klass_shift() != 0) {
6108 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6109 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6110 leaq(dst, Address(dst, src, Address::times_8, 0));
6111 } else {
6112 addq(dst, src);
6113 }
6114 }
6115 }
6116
6117 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6118 assert (UseCompressedOops, "should only be used for compressed headers");
6119 assert (Universe::heap() != NULL, "java heap should be initialized");
6120 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6121 int oop_index = oop_recorder()->find_index(obj);
6122 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6123 mov_narrow_oop(dst, oop_index, rspec);
6124 }
6125
6126 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6127 assert (UseCompressedOops, "should only be used for compressed headers");
6128 assert (Universe::heap() != NULL, "java heap should be initialized");
6129 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6130 int oop_index = oop_recorder()->find_index(obj);
6131 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6132 mov_narrow_oop(dst, oop_index, rspec);
6133 }
6134
6135 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6136 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6137 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6138 int klass_index = oop_recorder()->find_index(k);
6139 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6140 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6141 }
6142
6143 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6144 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6145 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6146 int klass_index = oop_recorder()->find_index(k);
6147 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6148 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6149 }
6150
6151 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6152 assert (UseCompressedOops, "should only be used for compressed headers");
6153 assert (Universe::heap() != NULL, "java heap should be initialized");
6154 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6155 int oop_index = oop_recorder()->find_index(obj);
6156 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6157 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6158 }
6159
6160 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6161 assert (UseCompressedOops, "should only be used for compressed headers");
6162 assert (Universe::heap() != NULL, "java heap should be initialized");
6163 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6164 int oop_index = oop_recorder()->find_index(obj);
6165 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6166 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6167 }
6168
6169 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6170 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6171 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6172 int klass_index = oop_recorder()->find_index(k);
6173 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6174 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6175 }
6176
6177 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6178 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6179 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6180 int klass_index = oop_recorder()->find_index(k);
6181 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6182 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6183 }
6184
6185 void MacroAssembler::reinit_heapbase() {
6186 if (UseCompressedOops || UseCompressedClassPointers) {
6187 if (Universe::heap() != NULL) {
6188 if (Universe::narrow_oop_base() == NULL) {
6189 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6190 } else {
6191 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6192 }
6193 } else {
6194 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6195 }
6196 }
6197 }
6198
6199 #endif // _LP64
6200
6201
6202 // C2 compiled method's prolog code.
6203 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6204
6205 // WARNING: Initial instruction MUST be 5 bytes or longer so that
6206 // NativeJump::patch_verified_entry will be able to patch out the entry
6207 // code safely. The push to verify stack depth is ok at 5 bytes,
6208 // the frame allocation can be either 3 or 6 bytes. So if we don't do
6209 // stack bang then we must use the 6 byte frame allocation even if
6210 // we have no frame. :-(
6211 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
6212
6213 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6214 // Remove word for return addr
6215 framesize -= wordSize;
6216 stack_bang_size -= wordSize;
6217
6218 // Calls to C2R adapters often do not accept exceptional returns.
6219 // We require that their callers must bang for them. But be careful, because
6220 // some VM calls (such as call site linkage) can use several kilobytes of
6221 // stack. But the stack safety zone should account for that.
6222 // See bugs 4446381, 4468289, 4497237.
6223 if (stack_bang_size > 0) {
6224 generate_stack_overflow_check(stack_bang_size);
6225
6226 // We always push rbp, so that on return to interpreter rbp, will be
6227 // restored correctly and we can correct the stack.
6228 push(rbp);
6229 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6230 if (PreserveFramePointer) {
6231 mov(rbp, rsp);
6232 }
6233 // Remove word for ebp
6234 framesize -= wordSize;
6235
6236 // Create frame
6237 if (framesize) {
6238 subptr(rsp, framesize);
6239 }
6240 } else {
6241 // Create frame (force generation of a 4 byte immediate value)
6242 subptr_imm32(rsp, framesize);
6243
6244 // Save RBP register now.
6245 framesize -= wordSize;
6246 movptr(Address(rsp, framesize), rbp);
6247 // Save caller's stack pointer into RBP if the frame pointer is preserved.
6248 if (PreserveFramePointer) {
6249 movptr(rbp, rsp);
6250 addptr(rbp, framesize + wordSize);
6251 }
6252 }
6253
6254 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
6255 framesize -= wordSize;
6256 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
6257 }
6258
6259 #ifndef _LP64
6260 // If method sets FPU control word do it now
6261 if (fp_mode_24b) {
6262 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
6263 }
6264 if (UseSSE >= 2 && VerifyFPU) {
6265 verify_FPU(0, "FPU stack must be clean on entry");
6266 }
6267 #endif
6268
6269 #ifdef ASSERT
6270 if (VerifyStackAtCalls) {
6271 Label L;
6272 push(rax);
6273 mov(rax, rsp);
6274 andptr(rax, StackAlignmentInBytes-1);
6275 cmpptr(rax, StackAlignmentInBytes-wordSize);
6276 pop(rax);
6277 jcc(Assembler::equal, L);
6278 STOP("Stack is not properly aligned!");
6279 bind(L);
6280 }
6281 #endif
6282
6283 }
6284
6285 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
6286 // cnt - number of qwords (8-byte words).
6287 // base - start address, qword aligned.
6288 assert(base==rdi, "base register must be edi for rep stos");
6289 assert(tmp==rax, "tmp register must be eax for rep stos");
6290 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6291
6292 xorptr(tmp, tmp);
6293 if (UseFastStosb) {
6294 shlptr(cnt,3); // convert to number of bytes
6295 rep_stosb();
6296 } else {
6297 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
6298 rep_stos();
6299 }
6300 }
6301
6302 // IndexOf for constant substrings with size >= 8 chars
6303 // which don't need to be loaded through stack.
6304 void MacroAssembler::string_indexofC8(Register str1, Register str2,
6305 Register cnt1, Register cnt2,
6306 int int_cnt2, Register result,
6307 XMMRegister vec, Register tmp) {
6308 ShortBranchVerifier sbv(this);
6309 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6310
6311 // This method uses pcmpestri instruction with bound registers
6312 // inputs:
6313 // xmm - substring
6314 // rax - substring length (elements count)
6315 // mem - scanned string
6316 // rdx - string length (elements count)
6317 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6318 // outputs:
6319 // rcx - matched index in string
6320 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6321
6322 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
6323 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
6324 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
6325
6326 // Note, inline_string_indexOf() generates checks:
6327 // if (substr.count > string.count) return -1;
6328 // if (substr.count == 0) return 0;
6329 assert(int_cnt2 >= 8, "this code isused only for cnt2 >= 8 chars");
6330
6331 // Load substring.
6332 movdqu(vec, Address(str2, 0));
6333 movl(cnt2, int_cnt2);
6334 movptr(result, str1); // string addr
6335
6336 if (int_cnt2 > 8) {
6337 jmpb(SCAN_TO_SUBSTR);
6338
6339 // Reload substr for rescan, this code
6340 // is executed only for large substrings (> 8 chars)
6341 bind(RELOAD_SUBSTR);
6342 movdqu(vec, Address(str2, 0));
6343 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
6344
6345 bind(RELOAD_STR);
6346 // We came here after the beginning of the substring was
6347 // matched but the rest of it was not so we need to search
6348 // again. Start from the next element after the previous match.
6349
6350 // cnt2 is number of substring reminding elements and
6351 // cnt1 is number of string reminding elements when cmp failed.
6352 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
6353 subl(cnt1, cnt2);
6354 addl(cnt1, int_cnt2);
6355 movl(cnt2, int_cnt2); // Now restore cnt2
6356
6357 decrementl(cnt1); // Shift to next element
6358 cmpl(cnt1, cnt2);
6359 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6360
6361 addptr(result, 2);
6362
6363 } // (int_cnt2 > 8)
6364
6365 // Scan string for start of substr in 16-byte vectors
6366 bind(SCAN_TO_SUBSTR);
6367 pcmpestri(vec, Address(result, 0), 0x0d);
6368 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6369 subl(cnt1, 8);
6370 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6371 cmpl(cnt1, cnt2);
6372 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6373 addptr(result, 16);
6374 jmpb(SCAN_TO_SUBSTR);
6375
6376 // Found a potential substr
6377 bind(FOUND_CANDIDATE);
6378 // Matched whole vector if first element matched (tmp(rcx) == 0).
6379 if (int_cnt2 == 8) {
6380 jccb(Assembler::overflow, RET_FOUND); // OF == 1
6381 } else { // int_cnt2 > 8
6382 jccb(Assembler::overflow, FOUND_SUBSTR);
6383 }
6384 // After pcmpestri tmp(rcx) contains matched element index
6385 // Compute start addr of substr
6386 lea(result, Address(result, tmp, Address::times_2));
6387
6388 // Make sure string is still long enough
6389 subl(cnt1, tmp);
6390 cmpl(cnt1, cnt2);
6391 if (int_cnt2 == 8) {
6392 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6393 } else { // int_cnt2 > 8
6394 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
6395 }
6396 // Left less then substring.
6397
6398 bind(RET_NOT_FOUND);
6399 movl(result, -1);
6400 jmpb(EXIT);
6401
6402 if (int_cnt2 > 8) {
6403 // This code is optimized for the case when whole substring
6404 // is matched if its head is matched.
6405 bind(MATCH_SUBSTR_HEAD);
6406 pcmpestri(vec, Address(result, 0), 0x0d);
6407 // Reload only string if does not match
6408 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
6409
6410 Label CONT_SCAN_SUBSTR;
6411 // Compare the rest of substring (> 8 chars).
6412 bind(FOUND_SUBSTR);
6413 // First 8 chars are already matched.
6414 negptr(cnt2);
6415 addptr(cnt2, 8);
6416
6417 bind(SCAN_SUBSTR);
6418 subl(cnt1, 8);
6419 cmpl(cnt2, -8); // Do not read beyond substring
6420 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
6421 // Back-up strings to avoid reading beyond substring:
6422 // cnt1 = cnt1 - cnt2 + 8
6423 addl(cnt1, cnt2); // cnt2 is negative
6424 addl(cnt1, 8);
6425 movl(cnt2, 8); negptr(cnt2);
6426 bind(CONT_SCAN_SUBSTR);
6427 if (int_cnt2 < (int)G) {
6428 movdqu(vec, Address(str2, cnt2, Address::times_2, int_cnt2*2));
6429 pcmpestri(vec, Address(result, cnt2, Address::times_2, int_cnt2*2), 0x0d);
6430 } else {
6431 // calculate index in register to avoid integer overflow (int_cnt2*2)
6432 movl(tmp, int_cnt2);
6433 addptr(tmp, cnt2);
6434 movdqu(vec, Address(str2, tmp, Address::times_2, 0));
6435 pcmpestri(vec, Address(result, tmp, Address::times_2, 0), 0x0d);
6436 }
6437 // Need to reload strings pointers if not matched whole vector
6438 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6439 addptr(cnt2, 8);
6440 jcc(Assembler::negative, SCAN_SUBSTR);
6441 // Fall through if found full substring
6442
6443 } // (int_cnt2 > 8)
6444
6445 bind(RET_FOUND);
6446 // Found result if we matched full small substring.
6447 // Compute substr offset
6448 subptr(result, str1);
6449 shrl(result, 1); // index
6450 bind(EXIT);
6451
6452 } // string_indexofC8
6453
6454 // Small strings are loaded through stack if they cross page boundary.
6455 void MacroAssembler::string_indexof(Register str1, Register str2,
6456 Register cnt1, Register cnt2,
6457 int int_cnt2, Register result,
6458 XMMRegister vec, Register tmp) {
6459 ShortBranchVerifier sbv(this);
6460 assert(UseSSE42Intrinsics, "SSE4.2 is required");
6461 //
6462 // int_cnt2 is length of small (< 8 chars) constant substring
6463 // or (-1) for non constant substring in which case its length
6464 // is in cnt2 register.
6465 //
6466 // Note, inline_string_indexOf() generates checks:
6467 // if (substr.count > string.count) return -1;
6468 // if (substr.count == 0) return 0;
6469 //
6470 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < 8), "should be != 0");
6471
6472 // This method uses pcmpestri instruction with bound registers
6473 // inputs:
6474 // xmm - substring
6475 // rax - substring length (elements count)
6476 // mem - scanned string
6477 // rdx - string length (elements count)
6478 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6479 // outputs:
6480 // rcx - matched index in string
6481 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6482
6483 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6484 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6485 FOUND_CANDIDATE;
6486
6487 { //========================================================
6488 // We don't know where these strings are located
6489 // and we can't read beyond them. Load them through stack.
6490 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6491
6492 movptr(tmp, rsp); // save old SP
6493
6494 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6495 if (int_cnt2 == 1) { // One char
6496 load_unsigned_short(result, Address(str2, 0));
6497 movdl(vec, result); // move 32 bits
6498 } else if (int_cnt2 == 2) { // Two chars
6499 movdl(vec, Address(str2, 0)); // move 32 bits
6500 } else if (int_cnt2 == 4) { // Four chars
6501 movq(vec, Address(str2, 0)); // move 64 bits
6502 } else { // cnt2 = { 3, 5, 6, 7 }
6503 // Array header size is 12 bytes in 32-bit VM
6504 // + 6 bytes for 3 chars == 18 bytes,
6505 // enough space to load vec and shift.
6506 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6507 movdqu(vec, Address(str2, (int_cnt2*2)-16));
6508 psrldq(vec, 16-(int_cnt2*2));
6509 }
6510 } else { // not constant substring
6511 cmpl(cnt2, 8);
6512 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6513
6514 // We can read beyond string if srt+16 does not cross page boundary
6515 // since heaps are aligned and mapped by pages.
6516 assert(os::vm_page_size() < (int)G, "default page should be small");
6517 movl(result, str2); // We need only low 32 bits
6518 andl(result, (os::vm_page_size()-1));
6519 cmpl(result, (os::vm_page_size()-16));
6520 jccb(Assembler::belowEqual, CHECK_STR);
6521
6522 // Move small strings to stack to allow load 16 bytes into vec.
6523 subptr(rsp, 16);
6524 int stk_offset = wordSize-2;
6525 push(cnt2);
6526
6527 bind(COPY_SUBSTR);
6528 load_unsigned_short(result, Address(str2, cnt2, Address::times_2, -2));
6529 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6530 decrement(cnt2);
6531 jccb(Assembler::notZero, COPY_SUBSTR);
6532
6533 pop(cnt2);
6534 movptr(str2, rsp); // New substring address
6535 } // non constant
6536
6537 bind(CHECK_STR);
6538 cmpl(cnt1, 8);
6539 jccb(Assembler::aboveEqual, BIG_STRINGS);
6540
6541 // Check cross page boundary.
6542 movl(result, str1); // We need only low 32 bits
6543 andl(result, (os::vm_page_size()-1));
6544 cmpl(result, (os::vm_page_size()-16));
6545 jccb(Assembler::belowEqual, BIG_STRINGS);
6546
6547 subptr(rsp, 16);
6548 int stk_offset = -2;
6549 if (int_cnt2 < 0) { // not constant
6550 push(cnt2);
6551 stk_offset += wordSize;
6552 }
6553 movl(cnt2, cnt1);
6554
6555 bind(COPY_STR);
6556 load_unsigned_short(result, Address(str1, cnt2, Address::times_2, -2));
6557 movw(Address(rsp, cnt2, Address::times_2, stk_offset), result);
6558 decrement(cnt2);
6559 jccb(Assembler::notZero, COPY_STR);
6560
6561 if (int_cnt2 < 0) { // not constant
6562 pop(cnt2);
6563 }
6564 movptr(str1, rsp); // New string address
6565
6566 bind(BIG_STRINGS);
6567 // Load substring.
6568 if (int_cnt2 < 0) { // -1
6569 movdqu(vec, Address(str2, 0));
6570 push(cnt2); // substr count
6571 push(str2); // substr addr
6572 push(str1); // string addr
6573 } else {
6574 // Small (< 8 chars) constant substrings are loaded already.
6575 movl(cnt2, int_cnt2);
6576 }
6577 push(tmp); // original SP
6578
6579 } // Finished loading
6580
6581 //========================================================
6582 // Start search
6583 //
6584
6585 movptr(result, str1); // string addr
6586
6587 if (int_cnt2 < 0) { // Only for non constant substring
6588 jmpb(SCAN_TO_SUBSTR);
6589
6590 // SP saved at sp+0
6591 // String saved at sp+1*wordSize
6592 // Substr saved at sp+2*wordSize
6593 // Substr count saved at sp+3*wordSize
6594
6595 // Reload substr for rescan, this code
6596 // is executed only for large substrings (> 8 chars)
6597 bind(RELOAD_SUBSTR);
6598 movptr(str2, Address(rsp, 2*wordSize));
6599 movl(cnt2, Address(rsp, 3*wordSize));
6600 movdqu(vec, Address(str2, 0));
6601 // We came here after the beginning of the substring was
6602 // matched but the rest of it was not so we need to search
6603 // again. Start from the next element after the previous match.
6604 subptr(str1, result); // Restore counter
6605 shrl(str1, 1);
6606 addl(cnt1, str1);
6607 decrementl(cnt1); // Shift to next element
6608 cmpl(cnt1, cnt2);
6609 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6610
6611 addptr(result, 2);
6612 } // non constant
6613
6614 // Scan string for start of substr in 16-byte vectors
6615 bind(SCAN_TO_SUBSTR);
6616 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6617 pcmpestri(vec, Address(result, 0), 0x0d);
6618 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6619 subl(cnt1, 8);
6620 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6621 cmpl(cnt1, cnt2);
6622 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6623 addptr(result, 16);
6624
6625 bind(ADJUST_STR);
6626 cmpl(cnt1, 8); // Do not read beyond string
6627 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6628 // Back-up string to avoid reading beyond string.
6629 lea(result, Address(result, cnt1, Address::times_2, -16));
6630 movl(cnt1, 8);
6631 jmpb(SCAN_TO_SUBSTR);
6632
6633 // Found a potential substr
6634 bind(FOUND_CANDIDATE);
6635 // After pcmpestri tmp(rcx) contains matched element index
6636
6637 // Make sure string is still long enough
6638 subl(cnt1, tmp);
6639 cmpl(cnt1, cnt2);
6640 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6641 // Left less then substring.
6642
6643 bind(RET_NOT_FOUND);
6644 movl(result, -1);
6645 jmpb(CLEANUP);
6646
6647 bind(FOUND_SUBSTR);
6648 // Compute start addr of substr
6649 lea(result, Address(result, tmp, Address::times_2));
6650
6651 if (int_cnt2 > 0) { // Constant substring
6652 // Repeat search for small substring (< 8 chars)
6653 // from new point without reloading substring.
6654 // Have to check that we don't read beyond string.
6655 cmpl(tmp, 8-int_cnt2);
6656 jccb(Assembler::greater, ADJUST_STR);
6657 // Fall through if matched whole substring.
6658 } else { // non constant
6659 assert(int_cnt2 == -1, "should be != 0");
6660
6661 addl(tmp, cnt2);
6662 // Found result if we matched whole substring.
6663 cmpl(tmp, 8);
6664 jccb(Assembler::lessEqual, RET_FOUND);
6665
6666 // Repeat search for small substring (<= 8 chars)
6667 // from new point 'str1' without reloading substring.
6668 cmpl(cnt2, 8);
6669 // Have to check that we don't read beyond string.
6670 jccb(Assembler::lessEqual, ADJUST_STR);
6671
6672 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6673 // Compare the rest of substring (> 8 chars).
6674 movptr(str1, result);
6675
6676 cmpl(tmp, cnt2);
6677 // First 8 chars are already matched.
6678 jccb(Assembler::equal, CHECK_NEXT);
6679
6680 bind(SCAN_SUBSTR);
6681 pcmpestri(vec, Address(str1, 0), 0x0d);
6682 // Need to reload strings pointers if not matched whole vector
6683 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6684
6685 bind(CHECK_NEXT);
6686 subl(cnt2, 8);
6687 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6688 addptr(str1, 16);
6689 addptr(str2, 16);
6690 subl(cnt1, 8);
6691 cmpl(cnt2, 8); // Do not read beyond substring
6692 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6693 // Back-up strings to avoid reading beyond substring.
6694 lea(str2, Address(str2, cnt2, Address::times_2, -16));
6695 lea(str1, Address(str1, cnt2, Address::times_2, -16));
6696 subl(cnt1, cnt2);
6697 movl(cnt2, 8);
6698 addl(cnt1, 8);
6699 bind(CONT_SCAN_SUBSTR);
6700 movdqu(vec, Address(str2, 0));
6701 jmpb(SCAN_SUBSTR);
6702
6703 bind(RET_FOUND_LONG);
6704 movptr(str1, Address(rsp, wordSize));
6705 } // non constant
6706
6707 bind(RET_FOUND);
6708 // Compute substr offset
6709 subptr(result, str1);
6710 shrl(result, 1); // index
6711
6712 bind(CLEANUP);
6713 pop(rsp); // restore SP
6714
6715 } // string_indexof
6716
6717 // Compare strings.
6718 void MacroAssembler::string_compare(Register str1, Register str2,
6719 Register cnt1, Register cnt2, Register result,
6720 XMMRegister vec1) {
6721 ShortBranchVerifier sbv(this);
6722 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6723
6724 // Compute the minimum of the string lengths and the
6725 // difference of the string lengths (stack).
6726 // Do the conditional move stuff
6727 movl(result, cnt1);
6728 subl(cnt1, cnt2);
6729 push(cnt1);
6730 cmov32(Assembler::lessEqual, cnt2, result);
6731
6732 // Is the minimum length zero?
6733 testl(cnt2, cnt2);
6734 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6735
6736 // Compare first characters
6737 load_unsigned_short(result, Address(str1, 0));
6738 load_unsigned_short(cnt1, Address(str2, 0));
6739 subl(result, cnt1);
6740 jcc(Assembler::notZero, POP_LABEL);
6741 cmpl(cnt2, 1);
6742 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6743
6744 // Check if the strings start at the same location.
6745 cmpptr(str1, str2);
6746 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6747
6748 Address::ScaleFactor scale = Address::times_2;
6749 int stride = 8;
6750
6751 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6752 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6753 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6754 Label COMPARE_TAIL_LONG;
6755 int pcmpmask = 0x19;
6756
6757 // Setup to compare 16-chars (32-bytes) vectors,
6758 // start from first character again because it has aligned address.
6759 int stride2 = 16;
6760 int adr_stride = stride << scale;
6761
6762 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6763 // rax and rdx are used by pcmpestri as elements counters
6764 movl(result, cnt2);
6765 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6766 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6767
6768 // fast path : compare first 2 8-char vectors.
6769 bind(COMPARE_16_CHARS);
6770 movdqu(vec1, Address(str1, 0));
6771 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6772 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6773
6774 movdqu(vec1, Address(str1, adr_stride));
6775 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6776 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6777 addl(cnt1, stride);
6778
6779 // Compare the characters at index in cnt1
6780 bind(COMPARE_INDEX_CHAR); //cnt1 has the offset of the mismatching character
6781 load_unsigned_short(result, Address(str1, cnt1, scale));
6782 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6783 subl(result, cnt2);
6784 jmp(POP_LABEL);
6785
6786 // Setup the registers to start vector comparison loop
6787 bind(COMPARE_WIDE_VECTORS);
6788 lea(str1, Address(str1, result, scale));
6789 lea(str2, Address(str2, result, scale));
6790 subl(result, stride2);
6791 subl(cnt2, stride2);
6792 jccb(Assembler::zero, COMPARE_WIDE_TAIL);
6793 negptr(result);
6794
6795 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6796 bind(COMPARE_WIDE_VECTORS_LOOP);
6797 vmovdqu(vec1, Address(str1, result, scale));
6798 vpxor(vec1, Address(str2, result, scale));
6799 vptest(vec1, vec1);
6800 jccb(Assembler::notZero, VECTOR_NOT_EQUAL);
6801 addptr(result, stride2);
6802 subl(cnt2, stride2);
6803 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6804 // clean upper bits of YMM registers
6805 vpxor(vec1, vec1);
6806
6807 // compare wide vectors tail
6808 bind(COMPARE_WIDE_TAIL);
6809 testptr(result, result);
6810 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6811
6812 movl(result, stride2);
6813 movl(cnt2, result);
6814 negptr(result);
6815 jmpb(COMPARE_WIDE_VECTORS_LOOP);
6816
6817 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6818 bind(VECTOR_NOT_EQUAL);
6819 // clean upper bits of YMM registers
6820 vpxor(vec1, vec1);
6821 lea(str1, Address(str1, result, scale));
6822 lea(str2, Address(str2, result, scale));
6823 jmp(COMPARE_16_CHARS);
6824
6825 // Compare tail chars, length between 1 to 15 chars
6826 bind(COMPARE_TAIL_LONG);
6827 movl(cnt2, result);
6828 cmpl(cnt2, stride);
6829 jccb(Assembler::less, COMPARE_SMALL_STR);
6830
6831 movdqu(vec1, Address(str1, 0));
6832 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6833 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6834 subptr(cnt2, stride);
6835 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6836 lea(str1, Address(str1, result, scale));
6837 lea(str2, Address(str2, result, scale));
6838 negptr(cnt2);
6839 jmpb(WHILE_HEAD_LABEL);
6840
6841 bind(COMPARE_SMALL_STR);
6842 } else if (UseSSE42Intrinsics) {
6843 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6844 int pcmpmask = 0x19;
6845 // Setup to compare 8-char (16-byte) vectors,
6846 // start from first character again because it has aligned address.
6847 movl(result, cnt2);
6848 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6849 jccb(Assembler::zero, COMPARE_TAIL);
6850
6851 lea(str1, Address(str1, result, scale));
6852 lea(str2, Address(str2, result, scale));
6853 negptr(result);
6854
6855 // pcmpestri
6856 // inputs:
6857 // vec1- substring
6858 // rax - negative string length (elements count)
6859 // mem - scanned string
6860 // rdx - string length (elements count)
6861 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6862 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6863 // outputs:
6864 // rcx - first mismatched element index
6865 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6866
6867 bind(COMPARE_WIDE_VECTORS);
6868 movdqu(vec1, Address(str1, result, scale));
6869 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6870 // After pcmpestri cnt1(rcx) contains mismatched element index
6871
6872 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6873 addptr(result, stride);
6874 subptr(cnt2, stride);
6875 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6876
6877 // compare wide vectors tail
6878 testptr(result, result);
6879 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
6880
6881 movl(cnt2, stride);
6882 movl(result, stride);
6883 negptr(result);
6884 movdqu(vec1, Address(str1, result, scale));
6885 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6886 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6887
6888 // Mismatched characters in the vectors
6889 bind(VECTOR_NOT_EQUAL);
6890 addptr(cnt1, result);
6891 load_unsigned_short(result, Address(str1, cnt1, scale));
6892 load_unsigned_short(cnt2, Address(str2, cnt1, scale));
6893 subl(result, cnt2);
6894 jmpb(POP_LABEL);
6895
6896 bind(COMPARE_TAIL); // limit is zero
6897 movl(cnt2, result);
6898 // Fallthru to tail compare
6899 }
6900 // Shift str2 and str1 to the end of the arrays, negate min
6901 lea(str1, Address(str1, cnt2, scale));
6902 lea(str2, Address(str2, cnt2, scale));
6903 decrementl(cnt2); // first character was compared already
6904 negptr(cnt2);
6905
6906 // Compare the rest of the elements
6907 bind(WHILE_HEAD_LABEL);
6908 load_unsigned_short(result, Address(str1, cnt2, scale, 0));
6909 load_unsigned_short(cnt1, Address(str2, cnt2, scale, 0));
6910 subl(result, cnt1);
6911 jccb(Assembler::notZero, POP_LABEL);
6912 increment(cnt2);
6913 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6914
6915 // Strings are equal up to min length. Return the length difference.
6916 bind(LENGTH_DIFF_LABEL);
6917 pop(result);
6918 jmpb(DONE_LABEL);
6919
6920 // Discard the stored length difference
6921 bind(POP_LABEL);
6922 pop(cnt1);
6923
6924 // That's it
6925 bind(DONE_LABEL);
6926 }
6927
6928 // Compare char[] arrays aligned to 4 bytes or substrings.
6929 void MacroAssembler::char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
6930 Register limit, Register result, Register chr,
6931 XMMRegister vec1, XMMRegister vec2) {
6932 ShortBranchVerifier sbv(this);
6933 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR;
6934
6935 int length_offset = arrayOopDesc::length_offset_in_bytes();
6936 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
6937
6938 // Check the input args
6939 cmpptr(ary1, ary2);
6940 jcc(Assembler::equal, TRUE_LABEL);
6941
6942 if (is_array_equ) {
6943 // Need additional checks for arrays_equals.
6944 testptr(ary1, ary1);
6945 jcc(Assembler::zero, FALSE_LABEL);
6946 testptr(ary2, ary2);
6947 jcc(Assembler::zero, FALSE_LABEL);
6948
6949 // Check the lengths
6950 movl(limit, Address(ary1, length_offset));
6951 cmpl(limit, Address(ary2, length_offset));
6952 jcc(Assembler::notEqual, FALSE_LABEL);
6953 }
6954
6955 // count == 0
6956 testl(limit, limit);
6957 jcc(Assembler::zero, TRUE_LABEL);
6958
6959 if (is_array_equ) {
6960 // Load array address
6961 lea(ary1, Address(ary1, base_offset));
6962 lea(ary2, Address(ary2, base_offset));
6963 }
6964
6965 shll(limit, 1); // byte count != 0
6966 movl(result, limit); // copy
6967
6968 if (UseAVX >= 2) {
6969 // With AVX2, use 32-byte vector compare
6970 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6971
6972 // Compare 32-byte vectors
6973 andl(result, 0x0000001e); // tail count (in bytes)
6974 andl(limit, 0xffffffe0); // vector count (in bytes)
6975 jccb(Assembler::zero, COMPARE_TAIL);
6976
6977 lea(ary1, Address(ary1, limit, Address::times_1));
6978 lea(ary2, Address(ary2, limit, Address::times_1));
6979 negptr(limit);
6980
6981 bind(COMPARE_WIDE_VECTORS);
6982 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
6983 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
6984 vpxor(vec1, vec2);
6985
6986 vptest(vec1, vec1);
6987 jccb(Assembler::notZero, FALSE_LABEL);
6988 addptr(limit, 32);
6989 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6990
6991 testl(result, result);
6992 jccb(Assembler::zero, TRUE_LABEL);
6993
6994 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6995 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
6996 vpxor(vec1, vec2);
6997
6998 vptest(vec1, vec1);
6999 jccb(Assembler::notZero, FALSE_LABEL);
7000 jmpb(TRUE_LABEL);
7001
7002 bind(COMPARE_TAIL); // limit is zero
7003 movl(limit, result);
7004 // Fallthru to tail compare
7005 } else if (UseSSE42Intrinsics) {
7006 // With SSE4.2, use double quad vector compare
7007 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7008
7009 // Compare 16-byte vectors
7010 andl(result, 0x0000000e); // tail count (in bytes)
7011 andl(limit, 0xfffffff0); // vector count (in bytes)
7012 jccb(Assembler::zero, COMPARE_TAIL);
7013
7014 lea(ary1, Address(ary1, limit, Address::times_1));
7015 lea(ary2, Address(ary2, limit, Address::times_1));
7016 negptr(limit);
7017
7018 bind(COMPARE_WIDE_VECTORS);
7019 movdqu(vec1, Address(ary1, limit, Address::times_1));
7020 movdqu(vec2, Address(ary2, limit, Address::times_1));
7021 pxor(vec1, vec2);
7022
7023 ptest(vec1, vec1);
7024 jccb(Assembler::notZero, FALSE_LABEL);
7025 addptr(limit, 16);
7026 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7027
7028 testl(result, result);
7029 jccb(Assembler::zero, TRUE_LABEL);
7030
7031 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7032 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7033 pxor(vec1, vec2);
7034
7035 ptest(vec1, vec1);
7036 jccb(Assembler::notZero, FALSE_LABEL);
7037 jmpb(TRUE_LABEL);
7038
7039 bind(COMPARE_TAIL); // limit is zero
7040 movl(limit, result);
7041 // Fallthru to tail compare
7042 }
7043
7044 // Compare 4-byte vectors
7045 andl(limit, 0xfffffffc); // vector count (in bytes)
7046 jccb(Assembler::zero, COMPARE_CHAR);
7047
7048 lea(ary1, Address(ary1, limit, Address::times_1));
7049 lea(ary2, Address(ary2, limit, Address::times_1));
7050 negptr(limit);
7051
7052 bind(COMPARE_VECTORS);
7053 movl(chr, Address(ary1, limit, Address::times_1));
7054 cmpl(chr, Address(ary2, limit, Address::times_1));
7055 jccb(Assembler::notEqual, FALSE_LABEL);
7056 addptr(limit, 4);
7057 jcc(Assembler::notZero, COMPARE_VECTORS);
7058
7059 // Compare trailing char (final 2 bytes), if any
7060 bind(COMPARE_CHAR);
7061 testl(result, 0x2); // tail char
7062 jccb(Assembler::zero, TRUE_LABEL);
7063 load_unsigned_short(chr, Address(ary1, 0));
7064 load_unsigned_short(limit, Address(ary2, 0));
7065 cmpl(chr, limit);
7066 jccb(Assembler::notEqual, FALSE_LABEL);
7067
7068 bind(TRUE_LABEL);
7069 movl(result, 1); // return true
7070 jmpb(DONE);
7071
7072 bind(FALSE_LABEL);
7073 xorl(result, result); // return false
7074
7075 // That's it
7076 bind(DONE);
7077 if (UseAVX >= 2) {
7078 // clean upper bits of YMM registers
7079 vpxor(vec1, vec1);
7080 vpxor(vec2, vec2);
7081 }
7082 }
7083
7084 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7085 Register to, Register value, Register count,
7086 Register rtmp, XMMRegister xtmp) {
7087 ShortBranchVerifier sbv(this);
7088 assert_different_registers(to, value, count, rtmp);
7089 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
7090 Label L_fill_2_bytes, L_fill_4_bytes;
7091
7092 int shift = -1;
7093 switch (t) {
7094 case T_BYTE:
7095 shift = 2;
7096 break;
7097 case T_SHORT:
7098 shift = 1;
7099 break;
7100 case T_INT:
7101 shift = 0;
7102 break;
7103 default: ShouldNotReachHere();
7104 }
7105
7106 if (t == T_BYTE) {
7107 andl(value, 0xff);
7108 movl(rtmp, value);
7109 shll(rtmp, 8);
7110 orl(value, rtmp);
7111 }
7112 if (t == T_SHORT) {
7113 andl(value, 0xffff);
7114 }
7115 if (t == T_BYTE || t == T_SHORT) {
7116 movl(rtmp, value);
7117 shll(rtmp, 16);
7118 orl(value, rtmp);
7119 }
7120
7121 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7122 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7123 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7124 // align source address at 4 bytes address boundary
7125 if (t == T_BYTE) {
7126 // One byte misalignment happens only for byte arrays
7127 testptr(to, 1);
7128 jccb(Assembler::zero, L_skip_align1);
7129 movb(Address(to, 0), value);
7130 increment(to);
7131 decrement(count);
7132 BIND(L_skip_align1);
7133 }
7134 // Two bytes misalignment happens only for byte and short (char) arrays
7135 testptr(to, 2);
7136 jccb(Assembler::zero, L_skip_align2);
7137 movw(Address(to, 0), value);
7138 addptr(to, 2);
7139 subl(count, 1<<(shift-1));
7140 BIND(L_skip_align2);
7141 }
7142 if (UseSSE < 2) {
7143 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7144 // Fill 32-byte chunks
7145 subl(count, 8 << shift);
7146 jcc(Assembler::less, L_check_fill_8_bytes);
7147 align(16);
7148
7149 BIND(L_fill_32_bytes_loop);
7150
7151 for (int i = 0; i < 32; i += 4) {
7152 movl(Address(to, i), value);
7153 }
7154
7155 addptr(to, 32);
7156 subl(count, 8 << shift);
7157 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7158 BIND(L_check_fill_8_bytes);
7159 addl(count, 8 << shift);
7160 jccb(Assembler::zero, L_exit);
7161 jmpb(L_fill_8_bytes);
7162
7163 //
7164 // length is too short, just fill qwords
7165 //
7166 BIND(L_fill_8_bytes_loop);
7167 movl(Address(to, 0), value);
7168 movl(Address(to, 4), value);
7169 addptr(to, 8);
7170 BIND(L_fill_8_bytes);
7171 subl(count, 1 << (shift + 1));
7172 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7173 // fall through to fill 4 bytes
7174 } else {
7175 Label L_fill_32_bytes;
7176 if (!UseUnalignedLoadStores) {
7177 // align to 8 bytes, we know we are 4 byte aligned to start
7178 testptr(to, 4);
7179 jccb(Assembler::zero, L_fill_32_bytes);
7180 movl(Address(to, 0), value);
7181 addptr(to, 4);
7182 subl(count, 1<<shift);
7183 }
7184 BIND(L_fill_32_bytes);
7185 {
7186 assert( UseSSE >= 2, "supported cpu only" );
7187 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7188 if (UseAVX > 2) {
7189 movl(rtmp, 0xffff);
7190 kmovwl(k1, rtmp);
7191 }
7192 movdl(xtmp, value);
7193 if (UseAVX > 2 && UseUnalignedLoadStores) {
7194 // Fill 64-byte chunks
7195 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7196 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7197
7198 subl(count, 16 << shift);
7199 jcc(Assembler::less, L_check_fill_32_bytes);
7200 align(16);
7201
7202 BIND(L_fill_64_bytes_loop);
7203 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7204 addptr(to, 64);
7205 subl(count, 16 << shift);
7206 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7207
7208 BIND(L_check_fill_32_bytes);
7209 addl(count, 8 << shift);
7210 jccb(Assembler::less, L_check_fill_8_bytes);
7211 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_256bit);
7212 addptr(to, 32);
7213 subl(count, 8 << shift);
7214
7215 BIND(L_check_fill_8_bytes);
7216 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
7217 // Fill 64-byte chunks
7218 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
7219 vpbroadcastd(xtmp, xtmp);
7220
7221 subl(count, 16 << shift);
7222 jcc(Assembler::less, L_check_fill_32_bytes);
7223 align(16);
7224
7225 BIND(L_fill_64_bytes_loop);
7226 vmovdqu(Address(to, 0), xtmp);
7227 vmovdqu(Address(to, 32), xtmp);
7228 addptr(to, 64);
7229 subl(count, 16 << shift);
7230 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7231
7232 BIND(L_check_fill_32_bytes);
7233 addl(count, 8 << shift);
7234 jccb(Assembler::less, L_check_fill_8_bytes);
7235 vmovdqu(Address(to, 0), xtmp);
7236 addptr(to, 32);
7237 subl(count, 8 << shift);
7238
7239 BIND(L_check_fill_8_bytes);
7240 // clean upper bits of YMM registers
7241 movdl(xtmp, value);
7242 pshufd(xtmp, xtmp, 0);
7243 } else {
7244 // Fill 32-byte chunks
7245 pshufd(xtmp, xtmp, 0);
7246
7247 subl(count, 8 << shift);
7248 jcc(Assembler::less, L_check_fill_8_bytes);
7249 align(16);
7250
7251 BIND(L_fill_32_bytes_loop);
7252
7253 if (UseUnalignedLoadStores) {
7254 movdqu(Address(to, 0), xtmp);
7255 movdqu(Address(to, 16), xtmp);
7256 } else {
7257 movq(Address(to, 0), xtmp);
7258 movq(Address(to, 8), xtmp);
7259 movq(Address(to, 16), xtmp);
7260 movq(Address(to, 24), xtmp);
7261 }
7262
7263 addptr(to, 32);
7264 subl(count, 8 << shift);
7265 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7266
7267 BIND(L_check_fill_8_bytes);
7268 }
7269 addl(count, 8 << shift);
7270 jccb(Assembler::zero, L_exit);
7271 jmpb(L_fill_8_bytes);
7272
7273 //
7274 // length is too short, just fill qwords
7275 //
7276 BIND(L_fill_8_bytes_loop);
7277 movq(Address(to, 0), xtmp);
7278 addptr(to, 8);
7279 BIND(L_fill_8_bytes);
7280 subl(count, 1 << (shift + 1));
7281 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7282 }
7283 }
7284 // fill trailing 4 bytes
7285 BIND(L_fill_4_bytes);
7286 testl(count, 1<<shift);
7287 jccb(Assembler::zero, L_fill_2_bytes);
7288 movl(Address(to, 0), value);
7289 if (t == T_BYTE || t == T_SHORT) {
7290 addptr(to, 4);
7291 BIND(L_fill_2_bytes);
7292 // fill trailing 2 bytes
7293 testl(count, 1<<(shift-1));
7294 jccb(Assembler::zero, L_fill_byte);
7295 movw(Address(to, 0), value);
7296 if (t == T_BYTE) {
7297 addptr(to, 2);
7298 BIND(L_fill_byte);
7299 // fill trailing byte
7300 testl(count, 1);
7301 jccb(Assembler::zero, L_exit);
7302 movb(Address(to, 0), value);
7303 } else {
7304 BIND(L_fill_byte);
7305 }
7306 } else {
7307 BIND(L_fill_2_bytes);
7308 }
7309 BIND(L_exit);
7310 }
7311
7312 // encode char[] to byte[] in ISO_8859_1
7313 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7314 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7315 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7316 Register tmp5, Register result) {
7317 // rsi: src
7318 // rdi: dst
7319 // rdx: len
7320 // rcx: tmp5
7321 // rax: result
7322 ShortBranchVerifier sbv(this);
7323 assert_different_registers(src, dst, len, tmp5, result);
7324 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7325
7326 // set result
7327 xorl(result, result);
7328 // check for zero length
7329 testl(len, len);
7330 jcc(Assembler::zero, L_done);
7331 movl(result, len);
7332
7333 // Setup pointers
7334 lea(src, Address(src, len, Address::times_2)); // char[]
7335 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7336 negptr(len);
7337
7338 if (UseSSE42Intrinsics || UseAVX >= 2) {
7339 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
7340 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7341
7342 if (UseAVX >= 2) {
7343 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7344 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7345 movdl(tmp1Reg, tmp5);
7346 vpbroadcastd(tmp1Reg, tmp1Reg);
7347 jmpb(L_chars_32_check);
7348
7349 bind(L_copy_32_chars);
7350 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7351 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7352 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7353 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7354 jccb(Assembler::notZero, L_copy_32_chars_exit);
7355 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7356 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7357 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7358
7359 bind(L_chars_32_check);
7360 addptr(len, 32);
7361 jccb(Assembler::lessEqual, L_copy_32_chars);
7362
7363 bind(L_copy_32_chars_exit);
7364 subptr(len, 16);
7365 jccb(Assembler::greater, L_copy_16_chars_exit);
7366
7367 } else if (UseSSE42Intrinsics) {
7368 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7369 movdl(tmp1Reg, tmp5);
7370 pshufd(tmp1Reg, tmp1Reg, 0);
7371 jmpb(L_chars_16_check);
7372 }
7373
7374 bind(L_copy_16_chars);
7375 if (UseAVX >= 2) {
7376 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7377 vptest(tmp2Reg, tmp1Reg);
7378 jccb(Assembler::notZero, L_copy_16_chars_exit);
7379 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7380 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7381 } else {
7382 if (UseAVX > 0) {
7383 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7384 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7385 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7386 } else {
7387 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7388 por(tmp2Reg, tmp3Reg);
7389 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7390 por(tmp2Reg, tmp4Reg);
7391 }
7392 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7393 jccb(Assembler::notZero, L_copy_16_chars_exit);
7394 packuswb(tmp3Reg, tmp4Reg);
7395 }
7396 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7397
7398 bind(L_chars_16_check);
7399 addptr(len, 16);
7400 jccb(Assembler::lessEqual, L_copy_16_chars);
7401
7402 bind(L_copy_16_chars_exit);
7403 if (UseAVX >= 2) {
7404 // clean upper bits of YMM registers
7405 vpxor(tmp2Reg, tmp2Reg);
7406 vpxor(tmp3Reg, tmp3Reg);
7407 vpxor(tmp4Reg, tmp4Reg);
7408 movdl(tmp1Reg, tmp5);
7409 pshufd(tmp1Reg, tmp1Reg, 0);
7410 }
7411 subptr(len, 8);
7412 jccb(Assembler::greater, L_copy_8_chars_exit);
7413
7414 bind(L_copy_8_chars);
7415 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7416 ptest(tmp3Reg, tmp1Reg);
7417 jccb(Assembler::notZero, L_copy_8_chars_exit);
7418 packuswb(tmp3Reg, tmp1Reg);
7419 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7420 addptr(len, 8);
7421 jccb(Assembler::lessEqual, L_copy_8_chars);
7422
7423 bind(L_copy_8_chars_exit);
7424 subptr(len, 8);
7425 jccb(Assembler::zero, L_done);
7426 }
7427
7428 bind(L_copy_1_char);
7429 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7430 testl(tmp5, 0xff00); // check if Unicode char
7431 jccb(Assembler::notZero, L_copy_1_char_exit);
7432 movb(Address(dst, len, Address::times_1, 0), tmp5);
7433 addptr(len, 1);
7434 jccb(Assembler::less, L_copy_1_char);
7435
7436 bind(L_copy_1_char_exit);
7437 addptr(result, len); // len is negative count of not processed elements
7438 bind(L_done);
7439 }
7440
7441 #ifdef _LP64
7442 /**
7443 * Helper for multiply_to_len().
7444 */
7445 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7446 addq(dest_lo, src1);
7447 adcq(dest_hi, 0);
7448 addq(dest_lo, src2);
7449 adcq(dest_hi, 0);
7450 }
7451
7452 /**
7453 * Multiply 64 bit by 64 bit first loop.
7454 */
7455 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7456 Register y, Register y_idx, Register z,
7457 Register carry, Register product,
7458 Register idx, Register kdx) {
7459 //
7460 // jlong carry, x[], y[], z[];
7461 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7462 // huge_128 product = y[idx] * x[xstart] + carry;
7463 // z[kdx] = (jlong)product;
7464 // carry = (jlong)(product >>> 64);
7465 // }
7466 // z[xstart] = carry;
7467 //
7468
7469 Label L_first_loop, L_first_loop_exit;
7470 Label L_one_x, L_one_y, L_multiply;
7471
7472 decrementl(xstart);
7473 jcc(Assembler::negative, L_one_x);
7474
7475 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7476 rorq(x_xstart, 32); // convert big-endian to little-endian
7477
7478 bind(L_first_loop);
7479 decrementl(idx);
7480 jcc(Assembler::negative, L_first_loop_exit);
7481 decrementl(idx);
7482 jcc(Assembler::negative, L_one_y);
7483 movq(y_idx, Address(y, idx, Address::times_4, 0));
7484 rorq(y_idx, 32); // convert big-endian to little-endian
7485 bind(L_multiply);
7486 movq(product, x_xstart);
7487 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7488 addq(product, carry);
7489 adcq(rdx, 0);
7490 subl(kdx, 2);
7491 movl(Address(z, kdx, Address::times_4, 4), product);
7492 shrq(product, 32);
7493 movl(Address(z, kdx, Address::times_4, 0), product);
7494 movq(carry, rdx);
7495 jmp(L_first_loop);
7496
7497 bind(L_one_y);
7498 movl(y_idx, Address(y, 0));
7499 jmp(L_multiply);
7500
7501 bind(L_one_x);
7502 movl(x_xstart, Address(x, 0));
7503 jmp(L_first_loop);
7504
7505 bind(L_first_loop_exit);
7506 }
7507
7508 /**
7509 * Multiply 64 bit by 64 bit and add 128 bit.
7510 */
7511 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7512 Register yz_idx, Register idx,
7513 Register carry, Register product, int offset) {
7514 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7515 // z[kdx] = (jlong)product;
7516
7517 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7518 rorq(yz_idx, 32); // convert big-endian to little-endian
7519 movq(product, x_xstart);
7520 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7521 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7522 rorq(yz_idx, 32); // convert big-endian to little-endian
7523
7524 add2_with_carry(rdx, product, carry, yz_idx);
7525
7526 movl(Address(z, idx, Address::times_4, offset+4), product);
7527 shrq(product, 32);
7528 movl(Address(z, idx, Address::times_4, offset), product);
7529
7530 }
7531
7532 /**
7533 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7534 */
7535 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7536 Register yz_idx, Register idx, Register jdx,
7537 Register carry, Register product,
7538 Register carry2) {
7539 // jlong carry, x[], y[], z[];
7540 // int kdx = ystart+1;
7541 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7542 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7543 // z[kdx+idx+1] = (jlong)product;
7544 // jlong carry2 = (jlong)(product >>> 64);
7545 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7546 // z[kdx+idx] = (jlong)product;
7547 // carry = (jlong)(product >>> 64);
7548 // }
7549 // idx += 2;
7550 // if (idx > 0) {
7551 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7552 // z[kdx+idx] = (jlong)product;
7553 // carry = (jlong)(product >>> 64);
7554 // }
7555 //
7556
7557 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7558
7559 movl(jdx, idx);
7560 andl(jdx, 0xFFFFFFFC);
7561 shrl(jdx, 2);
7562
7563 bind(L_third_loop);
7564 subl(jdx, 1);
7565 jcc(Assembler::negative, L_third_loop_exit);
7566 subl(idx, 4);
7567
7568 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7569 movq(carry2, rdx);
7570
7571 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7572 movq(carry, rdx);
7573 jmp(L_third_loop);
7574
7575 bind (L_third_loop_exit);
7576
7577 andl (idx, 0x3);
7578 jcc(Assembler::zero, L_post_third_loop_done);
7579
7580 Label L_check_1;
7581 subl(idx, 2);
7582 jcc(Assembler::negative, L_check_1);
7583
7584 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7585 movq(carry, rdx);
7586
7587 bind (L_check_1);
7588 addl (idx, 0x2);
7589 andl (idx, 0x1);
7590 subl(idx, 1);
7591 jcc(Assembler::negative, L_post_third_loop_done);
7592
7593 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7594 movq(product, x_xstart);
7595 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7596 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7597
7598 add2_with_carry(rdx, product, yz_idx, carry);
7599
7600 movl(Address(z, idx, Address::times_4, 0), product);
7601 shrq(product, 32);
7602
7603 shlq(rdx, 32);
7604 orq(product, rdx);
7605 movq(carry, product);
7606
7607 bind(L_post_third_loop_done);
7608 }
7609
7610 /**
7611 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7612 *
7613 */
7614 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7615 Register carry, Register carry2,
7616 Register idx, Register jdx,
7617 Register yz_idx1, Register yz_idx2,
7618 Register tmp, Register tmp3, Register tmp4) {
7619 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7620
7621 // jlong carry, x[], y[], z[];
7622 // int kdx = ystart+1;
7623 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7624 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7625 // jlong carry2 = (jlong)(tmp3 >>> 64);
7626 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7627 // carry = (jlong)(tmp4 >>> 64);
7628 // z[kdx+idx+1] = (jlong)tmp3;
7629 // z[kdx+idx] = (jlong)tmp4;
7630 // }
7631 // idx += 2;
7632 // if (idx > 0) {
7633 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7634 // z[kdx+idx] = (jlong)yz_idx1;
7635 // carry = (jlong)(yz_idx1 >>> 64);
7636 // }
7637 //
7638
7639 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7640
7641 movl(jdx, idx);
7642 andl(jdx, 0xFFFFFFFC);
7643 shrl(jdx, 2);
7644
7645 bind(L_third_loop);
7646 subl(jdx, 1);
7647 jcc(Assembler::negative, L_third_loop_exit);
7648 subl(idx, 4);
7649
7650 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7651 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7652 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7653 rorxq(yz_idx2, yz_idx2, 32);
7654
7655 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7656 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7657
7658 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7659 rorxq(yz_idx1, yz_idx1, 32);
7660 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7661 rorxq(yz_idx2, yz_idx2, 32);
7662
7663 if (VM_Version::supports_adx()) {
7664 adcxq(tmp3, carry);
7665 adoxq(tmp3, yz_idx1);
7666
7667 adcxq(tmp4, tmp);
7668 adoxq(tmp4, yz_idx2);
7669
7670 movl(carry, 0); // does not affect flags
7671 adcxq(carry2, carry);
7672 adoxq(carry2, carry);
7673 } else {
7674 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7675 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7676 }
7677 movq(carry, carry2);
7678
7679 movl(Address(z, idx, Address::times_4, 12), tmp3);
7680 shrq(tmp3, 32);
7681 movl(Address(z, idx, Address::times_4, 8), tmp3);
7682
7683 movl(Address(z, idx, Address::times_4, 4), tmp4);
7684 shrq(tmp4, 32);
7685 movl(Address(z, idx, Address::times_4, 0), tmp4);
7686
7687 jmp(L_third_loop);
7688
7689 bind (L_third_loop_exit);
7690
7691 andl (idx, 0x3);
7692 jcc(Assembler::zero, L_post_third_loop_done);
7693
7694 Label L_check_1;
7695 subl(idx, 2);
7696 jcc(Assembler::negative, L_check_1);
7697
7698 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7699 rorxq(yz_idx1, yz_idx1, 32);
7700 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7701 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7702 rorxq(yz_idx2, yz_idx2, 32);
7703
7704 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7705
7706 movl(Address(z, idx, Address::times_4, 4), tmp3);
7707 shrq(tmp3, 32);
7708 movl(Address(z, idx, Address::times_4, 0), tmp3);
7709 movq(carry, tmp4);
7710
7711 bind (L_check_1);
7712 addl (idx, 0x2);
7713 andl (idx, 0x1);
7714 subl(idx, 1);
7715 jcc(Assembler::negative, L_post_third_loop_done);
7716 movl(tmp4, Address(y, idx, Address::times_4, 0));
7717 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7718 movl(tmp4, Address(z, idx, Address::times_4, 0));
7719
7720 add2_with_carry(carry2, tmp3, tmp4, carry);
7721
7722 movl(Address(z, idx, Address::times_4, 0), tmp3);
7723 shrq(tmp3, 32);
7724
7725 shlq(carry2, 32);
7726 orq(tmp3, carry2);
7727 movq(carry, tmp3);
7728
7729 bind(L_post_third_loop_done);
7730 }
7731
7732 /**
7733 * Code for BigInteger::multiplyToLen() instrinsic.
7734 *
7735 * rdi: x
7736 * rax: xlen
7737 * rsi: y
7738 * rcx: ylen
7739 * r8: z
7740 * r11: zlen
7741 * r12: tmp1
7742 * r13: tmp2
7743 * r14: tmp3
7744 * r15: tmp4
7745 * rbx: tmp5
7746 *
7747 */
7748 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7749 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7750 ShortBranchVerifier sbv(this);
7751 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7752
7753 push(tmp1);
7754 push(tmp2);
7755 push(tmp3);
7756 push(tmp4);
7757 push(tmp5);
7758
7759 push(xlen);
7760 push(zlen);
7761
7762 const Register idx = tmp1;
7763 const Register kdx = tmp2;
7764 const Register xstart = tmp3;
7765
7766 const Register y_idx = tmp4;
7767 const Register carry = tmp5;
7768 const Register product = xlen;
7769 const Register x_xstart = zlen; // reuse register
7770
7771 // First Loop.
7772 //
7773 // final static long LONG_MASK = 0xffffffffL;
7774 // int xstart = xlen - 1;
7775 // int ystart = ylen - 1;
7776 // long carry = 0;
7777 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7778 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7779 // z[kdx] = (int)product;
7780 // carry = product >>> 32;
7781 // }
7782 // z[xstart] = (int)carry;
7783 //
7784
7785 movl(idx, ylen); // idx = ylen;
7786 movl(kdx, zlen); // kdx = xlen+ylen;
7787 xorq(carry, carry); // carry = 0;
7788
7789 Label L_done;
7790
7791 movl(xstart, xlen);
7792 decrementl(xstart);
7793 jcc(Assembler::negative, L_done);
7794
7795 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7796
7797 Label L_second_loop;
7798 testl(kdx, kdx);
7799 jcc(Assembler::zero, L_second_loop);
7800
7801 Label L_carry;
7802 subl(kdx, 1);
7803 jcc(Assembler::zero, L_carry);
7804
7805 movl(Address(z, kdx, Address::times_4, 0), carry);
7806 shrq(carry, 32);
7807 subl(kdx, 1);
7808
7809 bind(L_carry);
7810 movl(Address(z, kdx, Address::times_4, 0), carry);
7811
7812 // Second and third (nested) loops.
7813 //
7814 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7815 // carry = 0;
7816 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7817 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7818 // (z[k] & LONG_MASK) + carry;
7819 // z[k] = (int)product;
7820 // carry = product >>> 32;
7821 // }
7822 // z[i] = (int)carry;
7823 // }
7824 //
7825 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7826
7827 const Register jdx = tmp1;
7828
7829 bind(L_second_loop);
7830 xorl(carry, carry); // carry = 0;
7831 movl(jdx, ylen); // j = ystart+1
7832
7833 subl(xstart, 1); // i = xstart-1;
7834 jcc(Assembler::negative, L_done);
7835
7836 push (z);
7837
7838 Label L_last_x;
7839 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7840 subl(xstart, 1); // i = xstart-1;
7841 jcc(Assembler::negative, L_last_x);
7842
7843 if (UseBMI2Instructions) {
7844 movq(rdx, Address(x, xstart, Address::times_4, 0));
7845 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7846 } else {
7847 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7848 rorq(x_xstart, 32); // convert big-endian to little-endian
7849 }
7850
7851 Label L_third_loop_prologue;
7852 bind(L_third_loop_prologue);
7853
7854 push (x);
7855 push (xstart);
7856 push (ylen);
7857
7858
7859 if (UseBMI2Instructions) {
7860 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7861 } else { // !UseBMI2Instructions
7862 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7863 }
7864
7865 pop(ylen);
7866 pop(xlen);
7867 pop(x);
7868 pop(z);
7869
7870 movl(tmp3, xlen);
7871 addl(tmp3, 1);
7872 movl(Address(z, tmp3, Address::times_4, 0), carry);
7873 subl(tmp3, 1);
7874 jccb(Assembler::negative, L_done);
7875
7876 shrq(carry, 32);
7877 movl(Address(z, tmp3, Address::times_4, 0), carry);
7878 jmp(L_second_loop);
7879
7880 // Next infrequent code is moved outside loops.
7881 bind(L_last_x);
7882 if (UseBMI2Instructions) {
7883 movl(rdx, Address(x, 0));
7884 } else {
7885 movl(x_xstart, Address(x, 0));
7886 }
7887 jmp(L_third_loop_prologue);
7888
7889 bind(L_done);
7890
7891 pop(zlen);
7892 pop(xlen);
7893
7894 pop(tmp5);
7895 pop(tmp4);
7896 pop(tmp3);
7897 pop(tmp2);
7898 pop(tmp1);
7899 }
7900
7901 //Helper functions for square_to_len()
7902
7903 /**
7904 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7905 * Preserves x and z and modifies rest of the registers.
7906 */
7907
7908 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7909 // Perform square and right shift by 1
7910 // Handle odd xlen case first, then for even xlen do the following
7911 // jlong carry = 0;
7912 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7913 // huge_128 product = x[j:j+1] * x[j:j+1];
7914 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7915 // z[i+2:i+3] = (jlong)(product >>> 1);
7916 // carry = (jlong)product;
7917 // }
7918
7919 xorq(tmp5, tmp5); // carry
7920 xorq(rdxReg, rdxReg);
7921 xorl(tmp1, tmp1); // index for x
7922 xorl(tmp4, tmp4); // index for z
7923
7924 Label L_first_loop, L_first_loop_exit;
7925
7926 testl(xlen, 1);
7927 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7928
7929 // Square and right shift by 1 the odd element using 32 bit multiply
7930 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7931 imulq(raxReg, raxReg);
7932 shrq(raxReg, 1);
7933 adcq(tmp5, 0);
7934 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7935 incrementl(tmp1);
7936 addl(tmp4, 2);
7937
7938 // Square and right shift by 1 the rest using 64 bit multiply
7939 bind(L_first_loop);
7940 cmpptr(tmp1, xlen);
7941 jccb(Assembler::equal, L_first_loop_exit);
7942
7943 // Square
7944 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7945 rorq(raxReg, 32); // convert big-endian to little-endian
7946 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7947
7948 // Right shift by 1 and save carry
7949 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7950 rcrq(rdxReg, 1);
7951 rcrq(raxReg, 1);
7952 adcq(tmp5, 0);
7953
7954 // Store result in z
7955 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7956 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7957
7958 // Update indices for x and z
7959 addl(tmp1, 2);
7960 addl(tmp4, 4);
7961 jmp(L_first_loop);
7962
7963 bind(L_first_loop_exit);
7964 }
7965
7966
7967 /**
7968 * Perform the following multiply add operation using BMI2 instructions
7969 * carry:sum = sum + op1*op2 + carry
7970 * op2 should be in rdx
7971 * op2 is preserved, all other registers are modified
7972 */
7973 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7974 // assert op2 is rdx
7975 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7976 addq(sum, carry);
7977 adcq(tmp2, 0);
7978 addq(sum, op1);
7979 adcq(tmp2, 0);
7980 movq(carry, tmp2);
7981 }
7982
7983 /**
7984 * Perform the following multiply add operation:
7985 * carry:sum = sum + op1*op2 + carry
7986 * Preserves op1, op2 and modifies rest of registers
7987 */
7988 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7989 // rdx:rax = op1 * op2
7990 movq(raxReg, op2);
7991 mulq(op1);
7992
7993 // rdx:rax = sum + carry + rdx:rax
7994 addq(sum, carry);
7995 adcq(rdxReg, 0);
7996 addq(sum, raxReg);
7997 adcq(rdxReg, 0);
7998
7999 // carry:sum = rdx:sum
8000 movq(carry, rdxReg);
8001 }
8002
8003 /**
8004 * Add 64 bit long carry into z[] with carry propogation.
8005 * Preserves z and carry register values and modifies rest of registers.
8006 *
8007 */
8008 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8009 Label L_fourth_loop, L_fourth_loop_exit;
8010
8011 movl(tmp1, 1);
8012 subl(zlen, 2);
8013 addq(Address(z, zlen, Address::times_4, 0), carry);
8014
8015 bind(L_fourth_loop);
8016 jccb(Assembler::carryClear, L_fourth_loop_exit);
8017 subl(zlen, 2);
8018 jccb(Assembler::negative, L_fourth_loop_exit);
8019 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8020 jmp(L_fourth_loop);
8021 bind(L_fourth_loop_exit);
8022 }
8023
8024 /**
8025 * Shift z[] left by 1 bit.
8026 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8027 *
8028 */
8029 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8030
8031 Label L_fifth_loop, L_fifth_loop_exit;
8032
8033 // Fifth loop
8034 // Perform primitiveLeftShift(z, zlen, 1)
8035
8036 const Register prev_carry = tmp1;
8037 const Register new_carry = tmp4;
8038 const Register value = tmp2;
8039 const Register zidx = tmp3;
8040
8041 // int zidx, carry;
8042 // long value;
8043 // carry = 0;
8044 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8045 // (carry:value) = (z[i] << 1) | carry ;
8046 // z[i] = value;
8047 // }
8048
8049 movl(zidx, zlen);
8050 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8051
8052 bind(L_fifth_loop);
8053 decl(zidx); // Use decl to preserve carry flag
8054 decl(zidx);
8055 jccb(Assembler::negative, L_fifth_loop_exit);
8056
8057 if (UseBMI2Instructions) {
8058 movq(value, Address(z, zidx, Address::times_4, 0));
8059 rclq(value, 1);
8060 rorxq(value, value, 32);
8061 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8062 }
8063 else {
8064 // clear new_carry
8065 xorl(new_carry, new_carry);
8066
8067 // Shift z[i] by 1, or in previous carry and save new carry
8068 movq(value, Address(z, zidx, Address::times_4, 0));
8069 shlq(value, 1);
8070 adcl(new_carry, 0);
8071
8072 orq(value, prev_carry);
8073 rorq(value, 0x20);
8074 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8075
8076 // Set previous carry = new carry
8077 movl(prev_carry, new_carry);
8078 }
8079 jmp(L_fifth_loop);
8080
8081 bind(L_fifth_loop_exit);
8082 }
8083
8084
8085 /**
8086 * Code for BigInteger::squareToLen() intrinsic
8087 *
8088 * rdi: x
8089 * rsi: len
8090 * r8: z
8091 * rcx: zlen
8092 * r12: tmp1
8093 * r13: tmp2
8094 * r14: tmp3
8095 * r15: tmp4
8096 * rbx: tmp5
8097 *
8098 */
8099 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8100
8101 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
8102 push(tmp1);
8103 push(tmp2);
8104 push(tmp3);
8105 push(tmp4);
8106 push(tmp5);
8107
8108 // First loop
8109 // Store the squares, right shifted one bit (i.e., divided by 2).
8110 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8111
8112 // Add in off-diagonal sums.
8113 //
8114 // Second, third (nested) and fourth loops.
8115 // zlen +=2;
8116 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8117 // carry = 0;
8118 // long op2 = x[xidx:xidx+1];
8119 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8120 // k -= 2;
8121 // long op1 = x[j:j+1];
8122 // long sum = z[k:k+1];
8123 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8124 // z[k:k+1] = sum;
8125 // }
8126 // add_one_64(z, k, carry, tmp_regs);
8127 // }
8128
8129 const Register carry = tmp5;
8130 const Register sum = tmp3;
8131 const Register op1 = tmp4;
8132 Register op2 = tmp2;
8133
8134 push(zlen);
8135 push(len);
8136 addl(zlen,2);
8137 bind(L_second_loop);
8138 xorq(carry, carry);
8139 subl(zlen, 4);
8140 subl(len, 2);
8141 push(zlen);
8142 push(len);
8143 cmpl(len, 0);
8144 jccb(Assembler::lessEqual, L_second_loop_exit);
8145
8146 // Multiply an array by one 64 bit long.
8147 if (UseBMI2Instructions) {
8148 op2 = rdxReg;
8149 movq(op2, Address(x, len, Address::times_4, 0));
8150 rorxq(op2, op2, 32);
8151 }
8152 else {
8153 movq(op2, Address(x, len, Address::times_4, 0));
8154 rorq(op2, 32);
8155 }
8156
8157 bind(L_third_loop);
8158 decrementl(len);
8159 jccb(Assembler::negative, L_third_loop_exit);
8160 decrementl(len);
8161 jccb(Assembler::negative, L_last_x);
8162
8163 movq(op1, Address(x, len, Address::times_4, 0));
8164 rorq(op1, 32);
8165
8166 bind(L_multiply);
8167 subl(zlen, 2);
8168 movq(sum, Address(z, zlen, Address::times_4, 0));
8169
8170 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8171 if (UseBMI2Instructions) {
8172 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8173 }
8174 else {
8175 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8176 }
8177
8178 movq(Address(z, zlen, Address::times_4, 0), sum);
8179
8180 jmp(L_third_loop);
8181 bind(L_third_loop_exit);
8182
8183 // Fourth loop
8184 // Add 64 bit long carry into z with carry propogation.
8185 // Uses offsetted zlen.
8186 add_one_64(z, zlen, carry, tmp1);
8187
8188 pop(len);
8189 pop(zlen);
8190 jmp(L_second_loop);
8191
8192 // Next infrequent code is moved outside loops.
8193 bind(L_last_x);
8194 movl(op1, Address(x, 0));
8195 jmp(L_multiply);
8196
8197 bind(L_second_loop_exit);
8198 pop(len);
8199 pop(zlen);
8200 pop(len);
8201 pop(zlen);
8202
8203 // Fifth loop
8204 // Shift z left 1 bit.
8205 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8206
8207 // z[zlen-1] |= x[len-1] & 1;
8208 movl(tmp3, Address(x, len, Address::times_4, -4));
8209 andl(tmp3, 1);
8210 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8211
8212 pop(tmp5);
8213 pop(tmp4);
8214 pop(tmp3);
8215 pop(tmp2);
8216 pop(tmp1);
8217 }
8218
8219 /**
8220 * Helper function for mul_add()
8221 * Multiply the in[] by int k and add to out[] starting at offset offs using
8222 * 128 bit by 32 bit multiply and return the carry in tmp5.
8223 * Only quad int aligned length of in[] is operated on in this function.
8224 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8225 * This function preserves out, in and k registers.
8226 * len and offset point to the appropriate index in "in" & "out" correspondingly
8227 * tmp5 has the carry.
8228 * other registers are temporary and are modified.
8229 *
8230 */
8231 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8232 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8233 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8234
8235 Label L_first_loop, L_first_loop_exit;
8236
8237 movl(tmp1, len);
8238 shrl(tmp1, 2);
8239
8240 bind(L_first_loop);
8241 subl(tmp1, 1);
8242 jccb(Assembler::negative, L_first_loop_exit);
8243
8244 subl(len, 4);
8245 subl(offset, 4);
8246
8247 Register op2 = tmp2;
8248 const Register sum = tmp3;
8249 const Register op1 = tmp4;
8250 const Register carry = tmp5;
8251
8252 if (UseBMI2Instructions) {
8253 op2 = rdxReg;
8254 }
8255
8256 movq(op1, Address(in, len, Address::times_4, 8));
8257 rorq(op1, 32);
8258 movq(sum, Address(out, offset, Address::times_4, 8));
8259 rorq(sum, 32);
8260 if (UseBMI2Instructions) {
8261 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8262 }
8263 else {
8264 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8265 }
8266 // Store back in big endian from little endian
8267 rorq(sum, 0x20);
8268 movq(Address(out, offset, Address::times_4, 8), sum);
8269
8270 movq(op1, Address(in, len, Address::times_4, 0));
8271 rorq(op1, 32);
8272 movq(sum, Address(out, offset, Address::times_4, 0));
8273 rorq(sum, 32);
8274 if (UseBMI2Instructions) {
8275 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8276 }
8277 else {
8278 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8279 }
8280 // Store back in big endian from little endian
8281 rorq(sum, 0x20);
8282 movq(Address(out, offset, Address::times_4, 0), sum);
8283
8284 jmp(L_first_loop);
8285 bind(L_first_loop_exit);
8286 }
8287
8288 /**
8289 * Code for BigInteger::mulAdd() intrinsic
8290 *
8291 * rdi: out
8292 * rsi: in
8293 * r11: offs (out.length - offset)
8294 * rcx: len
8295 * r8: k
8296 * r12: tmp1
8297 * r13: tmp2
8298 * r14: tmp3
8299 * r15: tmp4
8300 * rbx: tmp5
8301 * Multiply the in[] by word k and add to out[], return the carry in rax
8302 */
8303 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8304 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8305 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8306
8307 Label L_carry, L_last_in, L_done;
8308
8309 // carry = 0;
8310 // for (int j=len-1; j >= 0; j--) {
8311 // long product = (in[j] & LONG_MASK) * kLong +
8312 // (out[offs] & LONG_MASK) + carry;
8313 // out[offs--] = (int)product;
8314 // carry = product >>> 32;
8315 // }
8316 //
8317 push(tmp1);
8318 push(tmp2);
8319 push(tmp3);
8320 push(tmp4);
8321 push(tmp5);
8322
8323 Register op2 = tmp2;
8324 const Register sum = tmp3;
8325 const Register op1 = tmp4;
8326 const Register carry = tmp5;
8327
8328 if (UseBMI2Instructions) {
8329 op2 = rdxReg;
8330 movl(op2, k);
8331 }
8332 else {
8333 movl(op2, k);
8334 }
8335
8336 xorq(carry, carry);
8337
8338 //First loop
8339
8340 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8341 //The carry is in tmp5
8342 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8343
8344 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8345 decrementl(len);
8346 jccb(Assembler::negative, L_carry);
8347 decrementl(len);
8348 jccb(Assembler::negative, L_last_in);
8349
8350 movq(op1, Address(in, len, Address::times_4, 0));
8351 rorq(op1, 32);
8352
8353 subl(offs, 2);
8354 movq(sum, Address(out, offs, Address::times_4, 0));
8355 rorq(sum, 32);
8356
8357 if (UseBMI2Instructions) {
8358 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8359 }
8360 else {
8361 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8362 }
8363
8364 // Store back in big endian from little endian
8365 rorq(sum, 0x20);
8366 movq(Address(out, offs, Address::times_4, 0), sum);
8367
8368 testl(len, len);
8369 jccb(Assembler::zero, L_carry);
8370
8371 //Multiply the last in[] entry, if any
8372 bind(L_last_in);
8373 movl(op1, Address(in, 0));
8374 movl(sum, Address(out, offs, Address::times_4, -4));
8375
8376 movl(raxReg, k);
8377 mull(op1); //tmp4 * eax -> edx:eax
8378 addl(sum, carry);
8379 adcl(rdxReg, 0);
8380 addl(sum, raxReg);
8381 adcl(rdxReg, 0);
8382 movl(carry, rdxReg);
8383
8384 movl(Address(out, offs, Address::times_4, -4), sum);
8385
8386 bind(L_carry);
8387 //return tmp5/carry as carry in rax
8388 movl(rax, carry);
8389
8390 bind(L_done);
8391 pop(tmp5);
8392 pop(tmp4);
8393 pop(tmp3);
8394 pop(tmp2);
8395 pop(tmp1);
8396 }
8397 #endif
8398
8399 /**
8400 * Emits code to update CRC-32 with a byte value according to constants in table
8401 *
8402 * @param [in,out]crc Register containing the crc.
8403 * @param [in]val Register containing the byte to fold into the CRC.
8404 * @param [in]table Register containing the table of crc constants.
8405 *
8406 * uint32_t crc;
8407 * val = crc_table[(val ^ crc) & 0xFF];
8408 * crc = val ^ (crc >> 8);
8409 *
8410 */
8411 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8412 xorl(val, crc);
8413 andl(val, 0xFF);
8414 shrl(crc, 8); // unsigned shift
8415 xorl(crc, Address(table, val, Address::times_4, 0));
8416 }
8417
8418 /**
8419 * Fold 128-bit data chunk
8420 */
8421 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8422 if (UseAVX > 0) {
8423 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8424 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8425 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8426 pxor(xcrc, xtmp);
8427 } else {
8428 movdqa(xtmp, xcrc);
8429 pclmulhdq(xtmp, xK); // [123:64]
8430 pclmulldq(xcrc, xK); // [63:0]
8431 pxor(xcrc, xtmp);
8432 movdqu(xtmp, Address(buf, offset));
8433 pxor(xcrc, xtmp);
8434 }
8435 }
8436
8437 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8438 if (UseAVX > 0) {
8439 vpclmulhdq(xtmp, xK, xcrc);
8440 vpclmulldq(xcrc, xK, xcrc);
8441 pxor(xcrc, xbuf);
8442 pxor(xcrc, xtmp);
8443 } else {
8444 movdqa(xtmp, xcrc);
8445 pclmulhdq(xtmp, xK);
8446 pclmulldq(xcrc, xK);
8447 pxor(xcrc, xbuf);
8448 pxor(xcrc, xtmp);
8449 }
8450 }
8451
8452 /**
8453 * 8-bit folds to compute 32-bit CRC
8454 *
8455 * uint64_t xcrc;
8456 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8457 */
8458 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8459 movdl(tmp, xcrc);
8460 andl(tmp, 0xFF);
8461 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8462 psrldq(xcrc, 1); // unsigned shift one byte
8463 pxor(xcrc, xtmp);
8464 }
8465
8466 /**
8467 * uint32_t crc;
8468 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8469 */
8470 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8471 movl(tmp, crc);
8472 andl(tmp, 0xFF);
8473 shrl(crc, 8);
8474 xorl(crc, Address(table, tmp, Address::times_4, 0));
8475 }
8476
8477 /**
8478 * @param crc register containing existing CRC (32-bit)
8479 * @param buf register pointing to input byte buffer (byte*)
8480 * @param len register containing number of bytes
8481 * @param table register that will contain address of CRC table
8482 * @param tmp scratch register
8483 */
8484 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8485 assert_different_registers(crc, buf, len, table, tmp, rax);
8486
8487 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8488 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8489
8490 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8491 // context for the registers used, where all instructions below are using 128-bit mode
8492 // On EVEX without VL and BW, these instructions will all be AVX.
8493 if (VM_Version::supports_avx512vlbw()) {
8494 movl(tmp, 0xffff);
8495 kmovwl(k1, tmp);
8496 }
8497
8498 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8499 notl(crc); // ~crc
8500 cmpl(len, 16);
8501 jcc(Assembler::less, L_tail);
8502
8503 // Align buffer to 16 bytes
8504 movl(tmp, buf);
8505 andl(tmp, 0xF);
8506 jccb(Assembler::zero, L_aligned);
8507 subl(tmp, 16);
8508 addl(len, tmp);
8509
8510 align(4);
8511 BIND(L_align_loop);
8512 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8513 update_byte_crc32(crc, rax, table);
8514 increment(buf);
8515 incrementl(tmp);
8516 jccb(Assembler::less, L_align_loop);
8517
8518 BIND(L_aligned);
8519 movl(tmp, len); // save
8520 shrl(len, 4);
8521 jcc(Assembler::zero, L_tail_restore);
8522
8523 // Fold crc into first bytes of vector
8524 movdqa(xmm1, Address(buf, 0));
8525 movdl(rax, xmm1);
8526 xorl(crc, rax);
8527 pinsrd(xmm1, crc, 0);
8528 addptr(buf, 16);
8529 subl(len, 4); // len > 0
8530 jcc(Assembler::less, L_fold_tail);
8531
8532 movdqa(xmm2, Address(buf, 0));
8533 movdqa(xmm3, Address(buf, 16));
8534 movdqa(xmm4, Address(buf, 32));
8535 addptr(buf, 48);
8536 subl(len, 3);
8537 jcc(Assembler::lessEqual, L_fold_512b);
8538
8539 // Fold total 512 bits of polynomial on each iteration,
8540 // 128 bits per each of 4 parallel streams.
8541 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8542
8543 align(32);
8544 BIND(L_fold_512b_loop);
8545 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8546 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8547 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8548 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8549 addptr(buf, 64);
8550 subl(len, 4);
8551 jcc(Assembler::greater, L_fold_512b_loop);
8552
8553 // Fold 512 bits to 128 bits.
8554 BIND(L_fold_512b);
8555 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8556 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8557 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8558 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8559
8560 // Fold the rest of 128 bits data chunks
8561 BIND(L_fold_tail);
8562 addl(len, 3);
8563 jccb(Assembler::lessEqual, L_fold_128b);
8564 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8565
8566 BIND(L_fold_tail_loop);
8567 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8568 addptr(buf, 16);
8569 decrementl(len);
8570 jccb(Assembler::greater, L_fold_tail_loop);
8571
8572 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8573 BIND(L_fold_128b);
8574 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
8575 if (UseAVX > 0) {
8576 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8577 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8578 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8579 } else {
8580 movdqa(xmm2, xmm0);
8581 pclmulqdq(xmm2, xmm1, 0x1);
8582 movdqa(xmm3, xmm0);
8583 pand(xmm3, xmm2);
8584 pclmulqdq(xmm0, xmm3, 0x1);
8585 }
8586 psrldq(xmm1, 8);
8587 psrldq(xmm2, 4);
8588 pxor(xmm0, xmm1);
8589 pxor(xmm0, xmm2);
8590
8591 // 8 8-bit folds to compute 32-bit CRC.
8592 for (int j = 0; j < 4; j++) {
8593 fold_8bit_crc32(xmm0, table, xmm1, rax);
8594 }
8595 movdl(crc, xmm0); // mov 32 bits to general register
8596 for (int j = 0; j < 4; j++) {
8597 fold_8bit_crc32(crc, table, rax);
8598 }
8599
8600 BIND(L_tail_restore);
8601 movl(len, tmp); // restore
8602 BIND(L_tail);
8603 andl(len, 0xf);
8604 jccb(Assembler::zero, L_exit);
8605
8606 // Fold the rest of bytes
8607 align(4);
8608 BIND(L_tail_loop);
8609 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8610 update_byte_crc32(crc, rax, table);
8611 increment(buf);
8612 decrementl(len);
8613 jccb(Assembler::greater, L_tail_loop);
8614
8615 BIND(L_exit);
8616 notl(crc); // ~c
8617 }
8618
8619 #ifdef _LP64
8620 // S. Gueron / Information Processing Letters 112 (2012) 184
8621 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8622 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8623 // Output: the 64-bit carry-less product of B * CONST
8624 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8625 Register tmp1, Register tmp2, Register tmp3) {
8626 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8627 if (n > 0) {
8628 addq(tmp3, n * 256 * 8);
8629 }
8630 // Q1 = TABLEExt[n][B & 0xFF];
8631 movl(tmp1, in);
8632 andl(tmp1, 0x000000FF);
8633 shll(tmp1, 3);
8634 addq(tmp1, tmp3);
8635 movq(tmp1, Address(tmp1, 0));
8636
8637 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8638 movl(tmp2, in);
8639 shrl(tmp2, 8);
8640 andl(tmp2, 0x000000FF);
8641 shll(tmp2, 3);
8642 addq(tmp2, tmp3);
8643 movq(tmp2, Address(tmp2, 0));
8644
8645 shlq(tmp2, 8);
8646 xorq(tmp1, tmp2);
8647
8648 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8649 movl(tmp2, in);
8650 shrl(tmp2, 16);
8651 andl(tmp2, 0x000000FF);
8652 shll(tmp2, 3);
8653 addq(tmp2, tmp3);
8654 movq(tmp2, Address(tmp2, 0));
8655
8656 shlq(tmp2, 16);
8657 xorq(tmp1, tmp2);
8658
8659 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8660 shrl(in, 24);
8661 andl(in, 0x000000FF);
8662 shll(in, 3);
8663 addq(in, tmp3);
8664 movq(in, Address(in, 0));
8665
8666 shlq(in, 24);
8667 xorq(in, tmp1);
8668 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8669 }
8670
8671 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8672 Register in_out,
8673 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8674 XMMRegister w_xtmp2,
8675 Register tmp1,
8676 Register n_tmp2, Register n_tmp3) {
8677 if (is_pclmulqdq_supported) {
8678 movdl(w_xtmp1, in_out); // modified blindly
8679
8680 movl(tmp1, const_or_pre_comp_const_index);
8681 movdl(w_xtmp2, tmp1);
8682 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8683
8684 movdq(in_out, w_xtmp1);
8685 } else {
8686 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8687 }
8688 }
8689
8690 // Recombination Alternative 2: No bit-reflections
8691 // T1 = (CRC_A * U1) << 1
8692 // T2 = (CRC_B * U2) << 1
8693 // C1 = T1 >> 32
8694 // C2 = T2 >> 32
8695 // T1 = T1 & 0xFFFFFFFF
8696 // T2 = T2 & 0xFFFFFFFF
8697 // T1 = CRC32(0, T1)
8698 // T2 = CRC32(0, T2)
8699 // C1 = C1 ^ T1
8700 // C2 = C2 ^ T2
8701 // CRC = C1 ^ C2 ^ CRC_C
8702 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8703 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8704 Register tmp1, Register tmp2,
8705 Register n_tmp3) {
8706 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8707 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8708 shlq(in_out, 1);
8709 movl(tmp1, in_out);
8710 shrq(in_out, 32);
8711 xorl(tmp2, tmp2);
8712 crc32(tmp2, tmp1, 4);
8713 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8714 shlq(in1, 1);
8715 movl(tmp1, in1);
8716 shrq(in1, 32);
8717 xorl(tmp2, tmp2);
8718 crc32(tmp2, tmp1, 4);
8719 xorl(in1, tmp2);
8720 xorl(in_out, in1);
8721 xorl(in_out, in2);
8722 }
8723
8724 // Set N to predefined value
8725 // Subtract from a lenght of a buffer
8726 // execute in a loop:
8727 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8728 // for i = 1 to N do
8729 // CRC_A = CRC32(CRC_A, A[i])
8730 // CRC_B = CRC32(CRC_B, B[i])
8731 // CRC_C = CRC32(CRC_C, C[i])
8732 // end for
8733 // Recombine
8734 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8735 Register in_out1, Register in_out2, Register in_out3,
8736 Register tmp1, Register tmp2, Register tmp3,
8737 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8738 Register tmp4, Register tmp5,
8739 Register n_tmp6) {
8740 Label L_processPartitions;
8741 Label L_processPartition;
8742 Label L_exit;
8743
8744 bind(L_processPartitions);
8745 cmpl(in_out1, 3 * size);
8746 jcc(Assembler::less, L_exit);
8747 xorl(tmp1, tmp1);
8748 xorl(tmp2, tmp2);
8749 movq(tmp3, in_out2);
8750 addq(tmp3, size);
8751
8752 bind(L_processPartition);
8753 crc32(in_out3, Address(in_out2, 0), 8);
8754 crc32(tmp1, Address(in_out2, size), 8);
8755 crc32(tmp2, Address(in_out2, size * 2), 8);
8756 addq(in_out2, 8);
8757 cmpq(in_out2, tmp3);
8758 jcc(Assembler::less, L_processPartition);
8759 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8760 w_xtmp1, w_xtmp2, w_xtmp3,
8761 tmp4, tmp5,
8762 n_tmp6);
8763 addq(in_out2, 2 * size);
8764 subl(in_out1, 3 * size);
8765 jmp(L_processPartitions);
8766
8767 bind(L_exit);
8768 }
8769 #else
8770 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8771 Register tmp1, Register tmp2, Register tmp3,
8772 XMMRegister xtmp1, XMMRegister xtmp2) {
8773 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8774 if (n > 0) {
8775 addl(tmp3, n * 256 * 8);
8776 }
8777 // Q1 = TABLEExt[n][B & 0xFF];
8778 movl(tmp1, in_out);
8779 andl(tmp1, 0x000000FF);
8780 shll(tmp1, 3);
8781 addl(tmp1, tmp3);
8782 movq(xtmp1, Address(tmp1, 0));
8783
8784 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8785 movl(tmp2, in_out);
8786 shrl(tmp2, 8);
8787 andl(tmp2, 0x000000FF);
8788 shll(tmp2, 3);
8789 addl(tmp2, tmp3);
8790 movq(xtmp2, Address(tmp2, 0));
8791
8792 psllq(xtmp2, 8);
8793 pxor(xtmp1, xtmp2);
8794
8795 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8796 movl(tmp2, in_out);
8797 shrl(tmp2, 16);
8798 andl(tmp2, 0x000000FF);
8799 shll(tmp2, 3);
8800 addl(tmp2, tmp3);
8801 movq(xtmp2, Address(tmp2, 0));
8802
8803 psllq(xtmp2, 16);
8804 pxor(xtmp1, xtmp2);
8805
8806 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8807 shrl(in_out, 24);
8808 andl(in_out, 0x000000FF);
8809 shll(in_out, 3);
8810 addl(in_out, tmp3);
8811 movq(xtmp2, Address(in_out, 0));
8812
8813 psllq(xtmp2, 24);
8814 pxor(xtmp1, xtmp2); // Result in CXMM
8815 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8816 }
8817
8818 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8819 Register in_out,
8820 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8821 XMMRegister w_xtmp2,
8822 Register tmp1,
8823 Register n_tmp2, Register n_tmp3) {
8824 if (is_pclmulqdq_supported) {
8825 movdl(w_xtmp1, in_out);
8826
8827 movl(tmp1, const_or_pre_comp_const_index);
8828 movdl(w_xtmp2, tmp1);
8829 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8830 // Keep result in XMM since GPR is 32 bit in length
8831 } else {
8832 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
8833 }
8834 }
8835
8836 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8837 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8838 Register tmp1, Register tmp2,
8839 Register n_tmp3) {
8840 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8841 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8842
8843 psllq(w_xtmp1, 1);
8844 movdl(tmp1, w_xtmp1);
8845 psrlq(w_xtmp1, 32);
8846 movdl(in_out, w_xtmp1);
8847
8848 xorl(tmp2, tmp2);
8849 crc32(tmp2, tmp1, 4);
8850 xorl(in_out, tmp2);
8851
8852 psllq(w_xtmp2, 1);
8853 movdl(tmp1, w_xtmp2);
8854 psrlq(w_xtmp2, 32);
8855 movdl(in1, w_xtmp2);
8856
8857 xorl(tmp2, tmp2);
8858 crc32(tmp2, tmp1, 4);
8859 xorl(in1, tmp2);
8860 xorl(in_out, in1);
8861 xorl(in_out, in2);
8862 }
8863
8864 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8865 Register in_out1, Register in_out2, Register in_out3,
8866 Register tmp1, Register tmp2, Register tmp3,
8867 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8868 Register tmp4, Register tmp5,
8869 Register n_tmp6) {
8870 Label L_processPartitions;
8871 Label L_processPartition;
8872 Label L_exit;
8873
8874 bind(L_processPartitions);
8875 cmpl(in_out1, 3 * size);
8876 jcc(Assembler::less, L_exit);
8877 xorl(tmp1, tmp1);
8878 xorl(tmp2, tmp2);
8879 movl(tmp3, in_out2);
8880 addl(tmp3, size);
8881
8882 bind(L_processPartition);
8883 crc32(in_out3, Address(in_out2, 0), 4);
8884 crc32(tmp1, Address(in_out2, size), 4);
8885 crc32(tmp2, Address(in_out2, size*2), 4);
8886 crc32(in_out3, Address(in_out2, 0+4), 4);
8887 crc32(tmp1, Address(in_out2, size+4), 4);
8888 crc32(tmp2, Address(in_out2, size*2+4), 4);
8889 addl(in_out2, 8);
8890 cmpl(in_out2, tmp3);
8891 jcc(Assembler::less, L_processPartition);
8892
8893 push(tmp3);
8894 push(in_out1);
8895 push(in_out2);
8896 tmp4 = tmp3;
8897 tmp5 = in_out1;
8898 n_tmp6 = in_out2;
8899
8900 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8901 w_xtmp1, w_xtmp2, w_xtmp3,
8902 tmp4, tmp5,
8903 n_tmp6);
8904
8905 pop(in_out2);
8906 pop(in_out1);
8907 pop(tmp3);
8908
8909 addl(in_out2, 2 * size);
8910 subl(in_out1, 3 * size);
8911 jmp(L_processPartitions);
8912
8913 bind(L_exit);
8914 }
8915 #endif //LP64
8916
8917 #ifdef _LP64
8918 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8919 // Input: A buffer I of L bytes.
8920 // Output: the CRC32C value of the buffer.
8921 // Notations:
8922 // Write L = 24N + r, with N = floor (L/24).
8923 // r = L mod 24 (0 <= r < 24).
8924 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8925 // N quadwords, and R consists of r bytes.
8926 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8927 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8928 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8929 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8930 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8931 Register tmp1, Register tmp2, Register tmp3,
8932 Register tmp4, Register tmp5, Register tmp6,
8933 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8934 bool is_pclmulqdq_supported) {
8935 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8936 Label L_wordByWord;
8937 Label L_byteByByteProlog;
8938 Label L_byteByByte;
8939 Label L_exit;
8940
8941 if (is_pclmulqdq_supported ) {
8942 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8943 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
8944
8945 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8946 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8947
8948 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8949 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8950 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8951 } else {
8952 const_or_pre_comp_const_index[0] = 1;
8953 const_or_pre_comp_const_index[1] = 0;
8954
8955 const_or_pre_comp_const_index[2] = 3;
8956 const_or_pre_comp_const_index[3] = 2;
8957
8958 const_or_pre_comp_const_index[4] = 5;
8959 const_or_pre_comp_const_index[5] = 4;
8960 }
8961 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8962 in2, in1, in_out,
8963 tmp1, tmp2, tmp3,
8964 w_xtmp1, w_xtmp2, w_xtmp3,
8965 tmp4, tmp5,
8966 tmp6);
8967 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8968 in2, in1, in_out,
8969 tmp1, tmp2, tmp3,
8970 w_xtmp1, w_xtmp2, w_xtmp3,
8971 tmp4, tmp5,
8972 tmp6);
8973 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8974 in2, in1, in_out,
8975 tmp1, tmp2, tmp3,
8976 w_xtmp1, w_xtmp2, w_xtmp3,
8977 tmp4, tmp5,
8978 tmp6);
8979 movl(tmp1, in2);
8980 andl(tmp1, 0x00000007);
8981 negl(tmp1);
8982 addl(tmp1, in2);
8983 addq(tmp1, in1);
8984
8985 BIND(L_wordByWord);
8986 cmpq(in1, tmp1);
8987 jcc(Assembler::greaterEqual, L_byteByByteProlog);
8988 crc32(in_out, Address(in1, 0), 4);
8989 addq(in1, 4);
8990 jmp(L_wordByWord);
8991
8992 BIND(L_byteByByteProlog);
8993 andl(in2, 0x00000007);
8994 movl(tmp2, 1);
8995
8996 BIND(L_byteByByte);
8997 cmpl(tmp2, in2);
8998 jccb(Assembler::greater, L_exit);
8999 crc32(in_out, Address(in1, 0), 1);
9000 incq(in1);
9001 incl(tmp2);
9002 jmp(L_byteByByte);
9003
9004 BIND(L_exit);
9005 }
9006 #else
9007 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9008 Register tmp1, Register tmp2, Register tmp3,
9009 Register tmp4, Register tmp5, Register tmp6,
9010 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9011 bool is_pclmulqdq_supported) {
9012 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9013 Label L_wordByWord;
9014 Label L_byteByByteProlog;
9015 Label L_byteByByte;
9016 Label L_exit;
9017
9018 if (is_pclmulqdq_supported) {
9019 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9020 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9021
9022 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9023 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9024
9025 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9026 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9027 } else {
9028 const_or_pre_comp_const_index[0] = 1;
9029 const_or_pre_comp_const_index[1] = 0;
9030
9031 const_or_pre_comp_const_index[2] = 3;
9032 const_or_pre_comp_const_index[3] = 2;
9033
9034 const_or_pre_comp_const_index[4] = 5;
9035 const_or_pre_comp_const_index[5] = 4;
9036 }
9037 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9038 in2, in1, in_out,
9039 tmp1, tmp2, tmp3,
9040 w_xtmp1, w_xtmp2, w_xtmp3,
9041 tmp4, tmp5,
9042 tmp6);
9043 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9044 in2, in1, in_out,
9045 tmp1, tmp2, tmp3,
9046 w_xtmp1, w_xtmp2, w_xtmp3,
9047 tmp4, tmp5,
9048 tmp6);
9049 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9050 in2, in1, in_out,
9051 tmp1, tmp2, tmp3,
9052 w_xtmp1, w_xtmp2, w_xtmp3,
9053 tmp4, tmp5,
9054 tmp6);
9055 movl(tmp1, in2);
9056 andl(tmp1, 0x00000007);
9057 negl(tmp1);
9058 addl(tmp1, in2);
9059 addl(tmp1, in1);
9060
9061 BIND(L_wordByWord);
9062 cmpl(in1, tmp1);
9063 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9064 crc32(in_out, Address(in1,0), 4);
9065 addl(in1, 4);
9066 jmp(L_wordByWord);
9067
9068 BIND(L_byteByByteProlog);
9069 andl(in2, 0x00000007);
9070 movl(tmp2, 1);
9071
9072 BIND(L_byteByByte);
9073 cmpl(tmp2, in2);
9074 jccb(Assembler::greater, L_exit);
9075 movb(tmp1, Address(in1, 0));
9076 crc32(in_out, tmp1, 1);
9077 incl(in1);
9078 incl(tmp2);
9079 jmp(L_byteByByte);
9080
9081 BIND(L_exit);
9082 }
9083 #endif // LP64
9084 #undef BIND
9085 #undef BLOCK_COMMENT
9086
9087
9088 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9089 switch (cond) {
9090 // Note some conditions are synonyms for others
9091 case Assembler::zero: return Assembler::notZero;
9092 case Assembler::notZero: return Assembler::zero;
9093 case Assembler::less: return Assembler::greaterEqual;
9094 case Assembler::lessEqual: return Assembler::greater;
9095 case Assembler::greater: return Assembler::lessEqual;
9096 case Assembler::greaterEqual: return Assembler::less;
9097 case Assembler::below: return Assembler::aboveEqual;
9098 case Assembler::belowEqual: return Assembler::above;
9099 case Assembler::above: return Assembler::belowEqual;
9100 case Assembler::aboveEqual: return Assembler::below;
9101 case Assembler::overflow: return Assembler::noOverflow;
9102 case Assembler::noOverflow: return Assembler::overflow;
9103 case Assembler::negative: return Assembler::positive;
9104 case Assembler::positive: return Assembler::negative;
9105 case Assembler::parity: return Assembler::noParity;
9106 case Assembler::noParity: return Assembler::parity;
9107 }
9108 ShouldNotReachHere(); return Assembler::overflow;
9109 }
9110
9111 SkipIfEqual::SkipIfEqual(
9112 MacroAssembler* masm, const bool* flag_addr, bool value) {
9113 _masm = masm;
9114 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9115 _masm->jcc(Assembler::equal, _label);
9116 }
9117
9118 SkipIfEqual::~SkipIfEqual() {
9119 _masm->bind(_label);
9120 }