1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "compiler/disassembler.hpp" 28 #include "gc/shared/cardTableModRefBS.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "memory/universe.hpp" 33 #include "oops/klass.inline.hpp" 34 #include "prims/methodHandles.hpp" 35 #include "runtime/biasedLocking.hpp" 36 #include "runtime/interfaceSupport.hpp" 37 #include "runtime/objectMonitor.hpp" 38 #include "runtime/os.inline.hpp" 39 #include "runtime/sharedRuntime.hpp" 40 #include "runtime/stubRoutines.hpp" 41 #include "utilities/macros.hpp" 42 #if INCLUDE_ALL_GCS 43 #include "gc/g1/g1CollectedHeap.inline.hpp" 44 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 45 #include "gc/g1/heapRegion.hpp" 46 #endif // INCLUDE_ALL_GCS 47 #ifdef COMPILER2 48 #include "opto/intrinsicnode.hpp" 49 #endif 50 51 #ifdef PRODUCT 52 #define BLOCK_COMMENT(str) /* nothing */ 53 #define STOP(error) stop(error) 54 #else 55 #define BLOCK_COMMENT(str) block_comment(str) 56 #define STOP(error) block_comment(error); stop(error) 57 #endif 58 59 // Convert the raw encoding form into the form expected by the 60 // constructor for Address. 61 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 62 assert(scale == 0, "not supported"); 63 RelocationHolder rspec; 64 if (disp_reloc != relocInfo::none) { 65 rspec = Relocation::spec_simple(disp_reloc); 66 } 67 68 Register rindex = as_Register(index); 69 if (rindex != G0) { 70 Address madr(as_Register(base), rindex); 71 madr._rspec = rspec; 72 return madr; 73 } else { 74 Address madr(as_Register(base), disp); 75 madr._rspec = rspec; 76 return madr; 77 } 78 } 79 80 Address Argument::address_in_frame() const { 81 // Warning: In LP64 mode disp will occupy more than 10 bits, but 82 // op codes such as ld or ldx, only access disp() to get 83 // their simm13 argument. 84 int disp = ((_number - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; 85 if (is_in()) 86 return Address(FP, disp); // In argument. 87 else 88 return Address(SP, disp); // Out argument. 89 } 90 91 static const char* argumentNames[][2] = { 92 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, 93 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, 94 {"A(n>9)","P(n>9)"} 95 }; 96 97 const char* Argument::name() const { 98 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; 99 int num = number(); 100 if (num >= nofArgs) num = nofArgs - 1; 101 return argumentNames[num][is_in() ? 1 : 0]; 102 } 103 104 #ifdef ASSERT 105 // On RISC, there's no benefit to verifying instruction boundaries. 106 bool AbstractAssembler::pd_check_instruction_mark() { return false; } 107 #endif 108 109 // Patch instruction inst at offset inst_pos to refer to dest_pos 110 // and return the resulting instruction. 111 // We should have pcs, not offsets, but since all is relative, it will work out 112 // OK. 113 int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) { 114 int m; // mask for displacement field 115 int v; // new value for displacement field 116 const int word_aligned_ones = -4; 117 switch (inv_op(inst)) { 118 default: ShouldNotReachHere(); 119 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; 120 case branch_op: 121 switch (inv_op2(inst)) { 122 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 123 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 124 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 125 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 126 case bpr_op2: { 127 if (is_cbcond(inst)) { 128 m = wdisp10(word_aligned_ones, 0); 129 v = wdisp10(dest_pos, inst_pos); 130 } else { 131 m = wdisp16(word_aligned_ones, 0); 132 v = wdisp16(dest_pos, inst_pos); 133 } 134 break; 135 } 136 default: ShouldNotReachHere(); 137 } 138 } 139 return inst & ~m | v; 140 } 141 142 // Return the offset of the branch destionation of instruction inst 143 // at offset pos. 144 // Should have pcs, but since all is relative, it works out. 145 int MacroAssembler::branch_destination(int inst, int pos) { 146 int r; 147 switch (inv_op(inst)) { 148 default: ShouldNotReachHere(); 149 case call_op: r = inv_wdisp(inst, pos, 30); break; 150 case branch_op: 151 switch (inv_op2(inst)) { 152 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; 153 case bp_op2: r = inv_wdisp( inst, pos, 19); break; 154 case fb_op2: r = inv_wdisp( inst, pos, 22); break; 155 case br_op2: r = inv_wdisp( inst, pos, 22); break; 156 case bpr_op2: { 157 if (is_cbcond(inst)) { 158 r = inv_wdisp10(inst, pos); 159 } else { 160 r = inv_wdisp16(inst, pos); 161 } 162 break; 163 } 164 default: ShouldNotReachHere(); 165 } 166 } 167 return r; 168 } 169 170 void MacroAssembler::null_check(Register reg, int offset) { 171 if (needs_explicit_null_check((intptr_t)offset)) { 172 // provoke OS NULL exception if reg = NULL by 173 // accessing M[reg] w/o changing any registers 174 ld_ptr(reg, 0, G0); 175 } 176 else { 177 // nothing to do, (later) access of M[reg + offset] 178 // will provoke OS NULL exception if reg = NULL 179 } 180 } 181 182 // Ring buffer jumps 183 184 185 void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { 186 assert_not_delayed(); 187 // This can only be traceable if r1 & r2 are visible after a window save 188 if (TraceJumps) { 189 #ifndef PRODUCT 190 save_frame(0); 191 verify_thread(); 192 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 193 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 194 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 195 add(O2, O1, O1); 196 197 add(r1->after_save(), r2->after_save(), O2); 198 set((intptr_t)file, O3); 199 set(line, O4); 200 Label L; 201 // get nearby pc, store jmp target 202 call(L, relocInfo::none); // No relocation for call to pc+0x8 203 delayed()->st(O2, O1, 0); 204 bind(L); 205 206 // store nearby pc 207 st(O7, O1, sizeof(intptr_t)); 208 // store file 209 st(O3, O1, 2*sizeof(intptr_t)); 210 // store line 211 st(O4, O1, 3*sizeof(intptr_t)); 212 add(O0, 1, O0); 213 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 214 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 215 restore(); 216 #endif /* PRODUCT */ 217 } 218 jmpl(r1, r2, G0); 219 } 220 void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { 221 assert_not_delayed(); 222 // This can only be traceable if r1 is visible after a window save 223 if (TraceJumps) { 224 #ifndef PRODUCT 225 save_frame(0); 226 verify_thread(); 227 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 228 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 229 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 230 add(O2, O1, O1); 231 232 add(r1->after_save(), offset, O2); 233 set((intptr_t)file, O3); 234 set(line, O4); 235 Label L; 236 // get nearby pc, store jmp target 237 call(L, relocInfo::none); // No relocation for call to pc+0x8 238 delayed()->st(O2, O1, 0); 239 bind(L); 240 241 // store nearby pc 242 st(O7, O1, sizeof(intptr_t)); 243 // store file 244 st(O3, O1, 2*sizeof(intptr_t)); 245 // store line 246 st(O4, O1, 3*sizeof(intptr_t)); 247 add(O0, 1, O0); 248 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 249 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 250 restore(); 251 #endif /* PRODUCT */ 252 } 253 jmp(r1, offset); 254 } 255 256 // This code sequence is relocatable to any address, even on LP64. 257 void MacroAssembler::jumpl(const AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line) { 258 assert_not_delayed(); 259 // Force fixed length sethi because NativeJump and NativeFarCall don't handle 260 // variable length instruction streams. 261 patchable_sethi(addrlit, temp); 262 Address a(temp, addrlit.low10() + offset); // Add the offset to the displacement. 263 if (TraceJumps) { 264 #ifndef PRODUCT 265 // Must do the add here so relocation can find the remainder of the 266 // value to be relocated. 267 add(a.base(), a.disp(), a.base(), addrlit.rspec(offset)); 268 save_frame(0); 269 verify_thread(); 270 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 271 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 272 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 273 add(O2, O1, O1); 274 275 set((intptr_t)file, O3); 276 set(line, O4); 277 Label L; 278 279 // get nearby pc, store jmp target 280 call(L, relocInfo::none); // No relocation for call to pc+0x8 281 delayed()->st(a.base()->after_save(), O1, 0); 282 bind(L); 283 284 // store nearby pc 285 st(O7, O1, sizeof(intptr_t)); 286 // store file 287 st(O3, O1, 2*sizeof(intptr_t)); 288 // store line 289 st(O4, O1, 3*sizeof(intptr_t)); 290 add(O0, 1, O0); 291 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 292 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 293 restore(); 294 jmpl(a.base(), G0, d); 295 #else 296 jmpl(a.base(), a.disp(), d); 297 #endif /* PRODUCT */ 298 } else { 299 jmpl(a.base(), a.disp(), d); 300 } 301 } 302 303 void MacroAssembler::jump(const AddressLiteral& addrlit, Register temp, int offset, const char* file, int line) { 304 jumpl(addrlit, temp, G0, offset, file, line); 305 } 306 307 308 // Conditional breakpoint (for assertion checks in assembly code) 309 void MacroAssembler::breakpoint_trap(Condition c, CC cc) { 310 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); 311 } 312 313 // We want to use ST_BREAKPOINT here, but the debugger is confused by it. 314 void MacroAssembler::breakpoint_trap() { 315 trap(ST_RESERVED_FOR_USER_0); 316 } 317 318 // Write serialization page so VM thread can do a pseudo remote membar 319 // We use the current thread pointer to calculate a thread specific 320 // offset to write to within the page. This minimizes bus traffic 321 // due to cache line collision. 322 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { 323 srl(thread, os::get_serialize_page_shift_count(), tmp2); 324 if (Assembler::is_simm13(os::vm_page_size())) { 325 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); 326 } 327 else { 328 set((os::vm_page_size() - sizeof(int)), tmp1); 329 and3(tmp2, tmp1, tmp2); 330 } 331 set(os::get_memory_serialize_page(), tmp1); 332 st(G0, tmp1, tmp2); 333 } 334 335 336 337 void MacroAssembler::enter() { 338 Unimplemented(); 339 } 340 341 void MacroAssembler::leave() { 342 Unimplemented(); 343 } 344 345 // Calls to C land 346 347 #ifdef ASSERT 348 // a hook for debugging 349 static Thread* reinitialize_thread() { 350 return Thread::current(); 351 } 352 #else 353 #define reinitialize_thread Thread::current 354 #endif 355 356 #ifdef ASSERT 357 address last_get_thread = NULL; 358 #endif 359 360 // call this when G2_thread is not known to be valid 361 void MacroAssembler::get_thread() { 362 save_frame(0); // to avoid clobbering O0 363 mov(G1, L0); // avoid clobbering G1 364 mov(G5_method, L1); // avoid clobbering G5 365 mov(G3, L2); // avoid clobbering G3 also 366 mov(G4, L5); // avoid clobbering G4 367 #ifdef ASSERT 368 AddressLiteral last_get_thread_addrlit(&last_get_thread); 369 set(last_get_thread_addrlit, L3); 370 rdpc(L4); 371 inc(L4, 3 * BytesPerInstWord); // skip rdpc + inc + st_ptr to point L4 at call st_ptr(L4, L3, 0); 372 #endif 373 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); 374 delayed()->nop(); 375 mov(L0, G1); 376 mov(L1, G5_method); 377 mov(L2, G3); 378 mov(L5, G4); 379 restore(O0, 0, G2_thread); 380 } 381 382 static Thread* verify_thread_subroutine(Thread* gthread_value) { 383 Thread* correct_value = Thread::current(); 384 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); 385 return correct_value; 386 } 387 388 void MacroAssembler::verify_thread() { 389 if (VerifyThread) { 390 // NOTE: this chops off the heads of the 64-bit O registers. 391 #ifdef CC_INTERP 392 save_frame(0); 393 #else 394 // make sure G2_thread contains the right value 395 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) 396 mov(G1, L1); // avoid clobbering G1 397 // G2 saved below 398 mov(G3, L3); // avoid clobbering G3 399 mov(G4, L4); // avoid clobbering G4 400 mov(G5_method, L5); // avoid clobbering G5_method 401 #endif /* CC_INTERP */ 402 #if defined(COMPILER2) && !defined(_LP64) 403 // Save & restore possible 64-bit Long arguments in G-regs 404 srlx(G1,32,L0); 405 srlx(G4,32,L6); 406 #endif 407 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); 408 delayed()->mov(G2_thread, O0); 409 410 mov(L1, G1); // Restore G1 411 // G2 restored below 412 mov(L3, G3); // restore G3 413 mov(L4, G4); // restore G4 414 mov(L5, G5_method); // restore G5_method 415 #if defined(COMPILER2) && !defined(_LP64) 416 // Save & restore possible 64-bit Long arguments in G-regs 417 sllx(L0,32,G2); // Move old high G1 bits high in G2 418 srl(G1, 0,G1); // Clear current high G1 bits 419 or3 (G1,G2,G1); // Recover 64-bit G1 420 sllx(L6,32,G2); // Move old high G4 bits high in G2 421 srl(G4, 0,G4); // Clear current high G4 bits 422 or3 (G4,G2,G4); // Recover 64-bit G4 423 #endif 424 restore(O0, 0, G2_thread); 425 } 426 } 427 428 429 void MacroAssembler::save_thread(const Register thread_cache) { 430 verify_thread(); 431 if (thread_cache->is_valid()) { 432 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 433 mov(G2_thread, thread_cache); 434 } 435 if (VerifyThread) { 436 // smash G2_thread, as if the VM were about to anyway 437 set(0x67676767, G2_thread); 438 } 439 } 440 441 442 void MacroAssembler::restore_thread(const Register thread_cache) { 443 if (thread_cache->is_valid()) { 444 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 445 mov(thread_cache, G2_thread); 446 verify_thread(); 447 } else { 448 // do it the slow way 449 get_thread(); 450 } 451 } 452 453 454 // %%% maybe get rid of [re]set_last_Java_frame 455 void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { 456 assert_not_delayed(); 457 Address flags(G2_thread, JavaThread::frame_anchor_offset() + 458 JavaFrameAnchor::flags_offset()); 459 Address pc_addr(G2_thread, JavaThread::last_Java_pc_offset()); 460 461 // Always set last_Java_pc and flags first because once last_Java_sp is visible 462 // has_last_Java_frame is true and users will look at the rest of the fields. 463 // (Note: flags should always be zero before we get here so doesn't need to be set.) 464 465 #ifdef ASSERT 466 // Verify that flags was zeroed on return to Java 467 Label PcOk; 468 save_frame(0); // to avoid clobbering O0 469 ld_ptr(pc_addr, L0); 470 br_null_short(L0, Assembler::pt, PcOk); 471 STOP("last_Java_pc not zeroed before leaving Java"); 472 bind(PcOk); 473 474 // Verify that flags was zeroed on return to Java 475 Label FlagsOk; 476 ld(flags, L0); 477 tst(L0); 478 br(Assembler::zero, false, Assembler::pt, FlagsOk); 479 delayed() -> restore(); 480 STOP("flags not zeroed before leaving Java"); 481 bind(FlagsOk); 482 #endif /* ASSERT */ 483 // 484 // When returning from calling out from Java mode the frame anchor's last_Java_pc 485 // will always be set to NULL. It is set here so that if we are doing a call to 486 // native (not VM) that we capture the known pc and don't have to rely on the 487 // native call having a standard frame linkage where we can find the pc. 488 489 if (last_Java_pc->is_valid()) { 490 st_ptr(last_Java_pc, pc_addr); 491 } 492 493 #ifdef _LP64 494 #ifdef ASSERT 495 // Make sure that we have an odd stack 496 Label StackOk; 497 andcc(last_java_sp, 0x01, G0); 498 br(Assembler::notZero, false, Assembler::pt, StackOk); 499 delayed()->nop(); 500 STOP("Stack Not Biased in set_last_Java_frame"); 501 bind(StackOk); 502 #endif // ASSERT 503 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); 504 add( last_java_sp, STACK_BIAS, G4_scratch ); 505 st_ptr(G4_scratch, G2_thread, JavaThread::last_Java_sp_offset()); 506 #else 507 st_ptr(last_java_sp, G2_thread, JavaThread::last_Java_sp_offset()); 508 #endif // _LP64 509 } 510 511 void MacroAssembler::reset_last_Java_frame(void) { 512 assert_not_delayed(); 513 514 Address sp_addr(G2_thread, JavaThread::last_Java_sp_offset()); 515 Address pc_addr(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 516 Address flags (G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); 517 518 #ifdef ASSERT 519 // check that it WAS previously set 520 #ifdef CC_INTERP 521 save_frame(0); 522 #else 523 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof 524 #endif /* CC_INTERP */ 525 ld_ptr(sp_addr, L0); 526 tst(L0); 527 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); 528 restore(); 529 #endif // ASSERT 530 531 st_ptr(G0, sp_addr); 532 // Always return last_Java_pc to zero 533 st_ptr(G0, pc_addr); 534 // Always null flags after return to Java 535 st(G0, flags); 536 } 537 538 539 void MacroAssembler::call_VM_base( 540 Register oop_result, 541 Register thread_cache, 542 Register last_java_sp, 543 address entry_point, 544 int number_of_arguments, 545 bool check_exceptions) 546 { 547 assert_not_delayed(); 548 549 // determine last_java_sp register 550 if (!last_java_sp->is_valid()) { 551 last_java_sp = SP; 552 } 553 // debugging support 554 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 555 556 // 64-bit last_java_sp is biased! 557 set_last_Java_frame(last_java_sp, noreg); 558 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early 559 save_thread(thread_cache); 560 // do the call 561 call(entry_point, relocInfo::runtime_call_type); 562 if (!VerifyThread) 563 delayed()->mov(G2_thread, O0); // pass thread as first argument 564 else 565 delayed()->nop(); // (thread already passed) 566 restore_thread(thread_cache); 567 reset_last_Java_frame(); 568 569 // check for pending exceptions. use Gtemp as scratch register. 570 if (check_exceptions) { 571 check_and_forward_exception(Gtemp); 572 } 573 574 #ifdef ASSERT 575 set(badHeapWordVal, G3); 576 set(badHeapWordVal, G4); 577 set(badHeapWordVal, G5); 578 #endif 579 580 // get oop result if there is one and reset the value in the thread 581 if (oop_result->is_valid()) { 582 get_vm_result(oop_result); 583 } 584 } 585 586 void MacroAssembler::check_and_forward_exception(Register scratch_reg) 587 { 588 Label L; 589 590 check_and_handle_popframe(scratch_reg); 591 check_and_handle_earlyret(scratch_reg); 592 593 Address exception_addr(G2_thread, Thread::pending_exception_offset()); 594 ld_ptr(exception_addr, scratch_reg); 595 br_null_short(scratch_reg, pt, L); 596 // we use O7 linkage so that forward_exception_entry has the issuing PC 597 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); 598 delayed()->nop(); 599 bind(L); 600 } 601 602 603 void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { 604 } 605 606 607 void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { 608 } 609 610 611 void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 612 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 613 } 614 615 616 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { 617 // O0 is reserved for the thread 618 mov(arg_1, O1); 619 call_VM(oop_result, entry_point, 1, check_exceptions); 620 } 621 622 623 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 624 // O0 is reserved for the thread 625 mov(arg_1, O1); 626 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 627 call_VM(oop_result, entry_point, 2, check_exceptions); 628 } 629 630 631 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 632 // O0 is reserved for the thread 633 mov(arg_1, O1); 634 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 635 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 636 call_VM(oop_result, entry_point, 3, check_exceptions); 637 } 638 639 640 641 // Note: The following call_VM overloadings are useful when a "save" 642 // has already been performed by a stub, and the last Java frame is 643 // the previous one. In that case, last_java_sp must be passed as FP 644 // instead of SP. 645 646 647 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { 648 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); 649 } 650 651 652 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { 653 // O0 is reserved for the thread 654 mov(arg_1, O1); 655 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 656 } 657 658 659 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 660 // O0 is reserved for the thread 661 mov(arg_1, O1); 662 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 663 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 664 } 665 666 667 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 668 // O0 is reserved for the thread 669 mov(arg_1, O1); 670 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 671 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 672 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 673 } 674 675 676 677 void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { 678 assert_not_delayed(); 679 save_thread(thread_cache); 680 // do the call 681 call(entry_point, relocInfo::runtime_call_type); 682 delayed()->nop(); 683 restore_thread(thread_cache); 684 #ifdef ASSERT 685 set(badHeapWordVal, G3); 686 set(badHeapWordVal, G4); 687 set(badHeapWordVal, G5); 688 #endif 689 } 690 691 692 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { 693 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); 694 } 695 696 697 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { 698 mov(arg_1, O0); 699 call_VM_leaf(thread_cache, entry_point, 1); 700 } 701 702 703 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { 704 mov(arg_1, O0); 705 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 706 call_VM_leaf(thread_cache, entry_point, 2); 707 } 708 709 710 void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { 711 mov(arg_1, O0); 712 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 713 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); 714 call_VM_leaf(thread_cache, entry_point, 3); 715 } 716 717 718 void MacroAssembler::get_vm_result(Register oop_result) { 719 verify_thread(); 720 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); 721 ld_ptr( vm_result_addr, oop_result); 722 st_ptr(G0, vm_result_addr); 723 verify_oop(oop_result); 724 } 725 726 727 void MacroAssembler::get_vm_result_2(Register metadata_result) { 728 verify_thread(); 729 Address vm_result_addr_2(G2_thread, JavaThread::vm_result_2_offset()); 730 ld_ptr(vm_result_addr_2, metadata_result); 731 st_ptr(G0, vm_result_addr_2); 732 } 733 734 735 // We require that C code which does not return a value in vm_result will 736 // leave it undisturbed. 737 void MacroAssembler::set_vm_result(Register oop_result) { 738 verify_thread(); 739 Address vm_result_addr(G2_thread, JavaThread::vm_result_offset()); 740 verify_oop(oop_result); 741 742 # ifdef ASSERT 743 // Check that we are not overwriting any other oop. 744 #ifdef CC_INTERP 745 save_frame(0); 746 #else 747 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof 748 #endif /* CC_INTERP */ 749 ld_ptr(vm_result_addr, L0); 750 tst(L0); 751 restore(); 752 breakpoint_trap(notZero, Assembler::ptr_cc); 753 // } 754 # endif 755 756 st_ptr(oop_result, vm_result_addr); 757 } 758 759 760 void MacroAssembler::ic_call(address entry, bool emit_delay, jint method_index) { 761 RelocationHolder rspec = virtual_call_Relocation::spec(pc(), method_index); 762 patchable_set((intptr_t)Universe::non_oop_word(), G5_inline_cache_reg); 763 relocate(rspec); 764 call(entry, relocInfo::none); 765 if (emit_delay) { 766 delayed()->nop(); 767 } 768 } 769 770 void MacroAssembler::card_table_write(jbyte* byte_map_base, 771 Register tmp, Register obj) { 772 #ifdef _LP64 773 srlx(obj, CardTableModRefBS::card_shift, obj); 774 #else 775 srl(obj, CardTableModRefBS::card_shift, obj); 776 #endif 777 assert(tmp != obj, "need separate temp reg"); 778 set((address) byte_map_base, tmp); 779 stb(G0, tmp, obj); 780 } 781 782 783 void MacroAssembler::internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { 784 address save_pc; 785 int shiftcnt; 786 #ifdef _LP64 787 # ifdef CHECK_DELAY 788 assert_not_delayed((char*) "cannot put two instructions in delay slot"); 789 # endif 790 v9_dep(); 791 save_pc = pc(); 792 793 int msb32 = (int) (addrlit.value() >> 32); 794 int lsb32 = (int) (addrlit.value()); 795 796 if (msb32 == 0 && lsb32 >= 0) { 797 Assembler::sethi(lsb32, d, addrlit.rspec()); 798 } 799 else if (msb32 == -1) { 800 Assembler::sethi(~lsb32, d, addrlit.rspec()); 801 xor3(d, ~low10(~0), d); 802 } 803 else { 804 Assembler::sethi(msb32, d, addrlit.rspec()); // msb 22-bits 805 if (msb32 & 0x3ff) // Any bits? 806 or3(d, msb32 & 0x3ff, d); // msb 32-bits are now in lsb 32 807 if (lsb32 & 0xFFFFFC00) { // done? 808 if ((lsb32 >> 20) & 0xfff) { // Any bits set? 809 sllx(d, 12, d); // Make room for next 12 bits 810 or3(d, (lsb32 >> 20) & 0xfff, d); // Or in next 12 811 shiftcnt = 0; // We already shifted 812 } 813 else 814 shiftcnt = 12; 815 if ((lsb32 >> 10) & 0x3ff) { 816 sllx(d, shiftcnt + 10, d); // Make room for last 10 bits 817 or3(d, (lsb32 >> 10) & 0x3ff, d); // Or in next 10 818 shiftcnt = 0; 819 } 820 else 821 shiftcnt = 10; 822 sllx(d, shiftcnt + 10, d); // Shift leaving disp field 0'd 823 } 824 else 825 sllx(d, 32, d); 826 } 827 // Pad out the instruction sequence so it can be patched later. 828 if (ForceRelocatable || (addrlit.rtype() != relocInfo::none && 829 addrlit.rtype() != relocInfo::runtime_call_type)) { 830 while (pc() < (save_pc + (7 * BytesPerInstWord))) 831 nop(); 832 } 833 #else 834 Assembler::sethi(addrlit.value(), d, addrlit.rspec()); 835 #endif 836 } 837 838 839 void MacroAssembler::sethi(const AddressLiteral& addrlit, Register d) { 840 internal_sethi(addrlit, d, false); 841 } 842 843 844 void MacroAssembler::patchable_sethi(const AddressLiteral& addrlit, Register d) { 845 internal_sethi(addrlit, d, true); 846 } 847 848 849 int MacroAssembler::insts_for_sethi(address a, bool worst_case) { 850 #ifdef _LP64 851 if (worst_case) return 7; 852 intptr_t iaddr = (intptr_t) a; 853 int msb32 = (int) (iaddr >> 32); 854 int lsb32 = (int) (iaddr); 855 int count; 856 if (msb32 == 0 && lsb32 >= 0) 857 count = 1; 858 else if (msb32 == -1) 859 count = 2; 860 else { 861 count = 2; 862 if (msb32 & 0x3ff) 863 count++; 864 if (lsb32 & 0xFFFFFC00 ) { 865 if ((lsb32 >> 20) & 0xfff) count += 2; 866 if ((lsb32 >> 10) & 0x3ff) count += 2; 867 } 868 } 869 return count; 870 #else 871 return 1; 872 #endif 873 } 874 875 int MacroAssembler::worst_case_insts_for_set() { 876 return insts_for_sethi(NULL, true) + 1; 877 } 878 879 880 // Keep in sync with MacroAssembler::insts_for_internal_set 881 void MacroAssembler::internal_set(const AddressLiteral& addrlit, Register d, bool ForceRelocatable) { 882 intptr_t value = addrlit.value(); 883 884 if (!ForceRelocatable && addrlit.rspec().type() == relocInfo::none) { 885 // can optimize 886 if (-4096 <= value && value <= 4095) { 887 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) 888 return; 889 } 890 if (inv_hi22(hi22(value)) == value) { 891 sethi(addrlit, d); 892 return; 893 } 894 } 895 assert_not_delayed((char*) "cannot put two instructions in delay slot"); 896 internal_sethi(addrlit, d, ForceRelocatable); 897 if (ForceRelocatable || addrlit.rspec().type() != relocInfo::none || addrlit.low10() != 0) { 898 add(d, addrlit.low10(), d, addrlit.rspec()); 899 } 900 } 901 902 // Keep in sync with MacroAssembler::internal_set 903 int MacroAssembler::insts_for_internal_set(intptr_t value) { 904 // can optimize 905 if (-4096 <= value && value <= 4095) { 906 return 1; 907 } 908 if (inv_hi22(hi22(value)) == value) { 909 return insts_for_sethi((address) value); 910 } 911 int count = insts_for_sethi((address) value); 912 AddressLiteral al(value); 913 if (al.low10() != 0) { 914 count++; 915 } 916 return count; 917 } 918 919 void MacroAssembler::set(const AddressLiteral& al, Register d) { 920 internal_set(al, d, false); 921 } 922 923 void MacroAssembler::set(intptr_t value, Register d) { 924 AddressLiteral al(value); 925 internal_set(al, d, false); 926 } 927 928 void MacroAssembler::set(address addr, Register d, RelocationHolder const& rspec) { 929 AddressLiteral al(addr, rspec); 930 internal_set(al, d, false); 931 } 932 933 void MacroAssembler::patchable_set(const AddressLiteral& al, Register d) { 934 internal_set(al, d, true); 935 } 936 937 void MacroAssembler::patchable_set(intptr_t value, Register d) { 938 AddressLiteral al(value); 939 internal_set(al, d, true); 940 } 941 942 943 void MacroAssembler::set64(jlong value, Register d, Register tmp) { 944 assert_not_delayed(); 945 v9_dep(); 946 947 int hi = (int)(value >> 32); 948 int lo = (int)(value & ~0); 949 int bits_33to2 = (int)((value >> 2) & ~0); 950 // (Matcher::isSimpleConstant64 knows about the following optimizations.) 951 if (Assembler::is_simm13(lo) && value == lo) { 952 or3(G0, lo, d); 953 } else if (hi == 0) { 954 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 955 if (low10(lo) != 0) 956 or3(d, low10(lo), d); 957 } 958 else if ((hi >> 2) == 0) { 959 Assembler::sethi(bits_33to2, d); // hardware version zero-extends to upper 32 960 sllx(d, 2, d); 961 if (low12(lo) != 0) 962 or3(d, low12(lo), d); 963 } 964 else if (hi == -1) { 965 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 966 xor3(d, low10(lo) ^ ~low10(~0), d); 967 } 968 else if (lo == 0) { 969 if (Assembler::is_simm13(hi)) { 970 or3(G0, hi, d); 971 } else { 972 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 973 if (low10(hi) != 0) 974 or3(d, low10(hi), d); 975 } 976 sllx(d, 32, d); 977 } 978 else { 979 Assembler::sethi(hi, tmp); 980 Assembler::sethi(lo, d); // macro assembler version sign-extends 981 if (low10(hi) != 0) 982 or3 (tmp, low10(hi), tmp); 983 if (low10(lo) != 0) 984 or3 ( d, low10(lo), d); 985 sllx(tmp, 32, tmp); 986 or3 (d, tmp, d); 987 } 988 } 989 990 int MacroAssembler::insts_for_set64(jlong value) { 991 v9_dep(); 992 993 int hi = (int) (value >> 32); 994 int lo = (int) (value & ~0); 995 int count = 0; 996 997 // (Matcher::isSimpleConstant64 knows about the following optimizations.) 998 if (Assembler::is_simm13(lo) && value == lo) { 999 count++; 1000 } else if (hi == 0) { 1001 count++; 1002 if (low10(lo) != 0) 1003 count++; 1004 } 1005 else if (hi == -1) { 1006 count += 2; 1007 } 1008 else if (lo == 0) { 1009 if (Assembler::is_simm13(hi)) { 1010 count++; 1011 } else { 1012 count++; 1013 if (low10(hi) != 0) 1014 count++; 1015 } 1016 count++; 1017 } 1018 else { 1019 count += 2; 1020 if (low10(hi) != 0) 1021 count++; 1022 if (low10(lo) != 0) 1023 count++; 1024 count += 2; 1025 } 1026 return count; 1027 } 1028 1029 // compute size in bytes of sparc frame, given 1030 // number of extraWords 1031 int MacroAssembler::total_frame_size_in_bytes(int extraWords) { 1032 1033 int nWords = frame::memory_parameter_word_sp_offset; 1034 1035 nWords += extraWords; 1036 1037 if (nWords & 1) ++nWords; // round up to double-word 1038 1039 return nWords * BytesPerWord; 1040 } 1041 1042 1043 // save_frame: given number of "extra" words in frame, 1044 // issue approp. save instruction (p 200, v8 manual) 1045 1046 void MacroAssembler::save_frame(int extraWords) { 1047 int delta = -total_frame_size_in_bytes(extraWords); 1048 if (is_simm13(delta)) { 1049 save(SP, delta, SP); 1050 } else { 1051 set(delta, G3_scratch); 1052 save(SP, G3_scratch, SP); 1053 } 1054 } 1055 1056 1057 void MacroAssembler::save_frame_c1(int size_in_bytes) { 1058 if (is_simm13(-size_in_bytes)) { 1059 save(SP, -size_in_bytes, SP); 1060 } else { 1061 set(-size_in_bytes, G3_scratch); 1062 save(SP, G3_scratch, SP); 1063 } 1064 } 1065 1066 1067 void MacroAssembler::save_frame_and_mov(int extraWords, 1068 Register s1, Register d1, 1069 Register s2, Register d2) { 1070 assert_not_delayed(); 1071 1072 // The trick here is to use precisely the same memory word 1073 // that trap handlers also use to save the register. 1074 // This word cannot be used for any other purpose, but 1075 // it works fine to save the register's value, whether or not 1076 // an interrupt flushes register windows at any given moment! 1077 Address s1_addr; 1078 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { 1079 s1_addr = s1->address_in_saved_window(); 1080 st_ptr(s1, s1_addr); 1081 } 1082 1083 Address s2_addr; 1084 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { 1085 s2_addr = s2->address_in_saved_window(); 1086 st_ptr(s2, s2_addr); 1087 } 1088 1089 save_frame(extraWords); 1090 1091 if (s1_addr.base() == SP) { 1092 ld_ptr(s1_addr.after_save(), d1); 1093 } else if (s1->is_valid()) { 1094 mov(s1->after_save(), d1); 1095 } 1096 1097 if (s2_addr.base() == SP) { 1098 ld_ptr(s2_addr.after_save(), d2); 1099 } else if (s2->is_valid()) { 1100 mov(s2->after_save(), d2); 1101 } 1102 } 1103 1104 1105 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) { 1106 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 1107 int index = oop_recorder()->allocate_metadata_index(obj); 1108 RelocationHolder rspec = metadata_Relocation::spec(index); 1109 return AddressLiteral((address)obj, rspec); 1110 } 1111 1112 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) { 1113 assert(oop_recorder() != NULL, "this assembler needs a Recorder"); 1114 int index = oop_recorder()->find_index(obj); 1115 RelocationHolder rspec = metadata_Relocation::spec(index); 1116 return AddressLiteral((address)obj, rspec); 1117 } 1118 1119 1120 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) { 1121 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1122 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(obj)), "not an oop"); 1123 int oop_index = oop_recorder()->find_index(obj); 1124 return AddressLiteral(obj, oop_Relocation::spec(oop_index)); 1125 } 1126 1127 void MacroAssembler::set_narrow_oop(jobject obj, Register d) { 1128 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1129 int oop_index = oop_recorder()->find_index(obj); 1130 RelocationHolder rspec = oop_Relocation::spec(oop_index); 1131 1132 assert_not_delayed(); 1133 // Relocation with special format (see relocInfo_sparc.hpp). 1134 relocate(rspec, 1); 1135 // Assembler::sethi(0x3fffff, d); 1136 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); 1137 // Don't add relocation for 'add'. Do patching during 'sethi' processing. 1138 add(d, 0x3ff, d); 1139 1140 } 1141 1142 void MacroAssembler::set_narrow_klass(Klass* k, Register d) { 1143 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1144 int klass_index = oop_recorder()->find_index(k); 1145 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 1146 narrowOop encoded_k = Klass::encode_klass(k); 1147 1148 assert_not_delayed(); 1149 // Relocation with special format (see relocInfo_sparc.hpp). 1150 relocate(rspec, 1); 1151 // Assembler::sethi(encoded_k, d); 1152 emit_int32( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(encoded_k) ); 1153 // Don't add relocation for 'add'. Do patching during 'sethi' processing. 1154 add(d, low10(encoded_k), d); 1155 1156 } 1157 1158 void MacroAssembler::align(int modulus) { 1159 while (offset() % modulus != 0) nop(); 1160 } 1161 1162 void RegistersForDebugging::print(outputStream* s) { 1163 FlagSetting fs(Debugging, true); 1164 int j; 1165 for (j = 0; j < 8; ++j) { 1166 if (j != 6) { s->print("i%d = ", j); os::print_location(s, i[j]); } 1167 else { s->print( "fp = " ); os::print_location(s, i[j]); } 1168 } 1169 s->cr(); 1170 1171 for (j = 0; j < 8; ++j) { 1172 s->print("l%d = ", j); os::print_location(s, l[j]); 1173 } 1174 s->cr(); 1175 1176 for (j = 0; j < 8; ++j) { 1177 if (j != 6) { s->print("o%d = ", j); os::print_location(s, o[j]); } 1178 else { s->print( "sp = " ); os::print_location(s, o[j]); } 1179 } 1180 s->cr(); 1181 1182 for (j = 0; j < 8; ++j) { 1183 s->print("g%d = ", j); os::print_location(s, g[j]); 1184 } 1185 s->cr(); 1186 1187 // print out floats with compression 1188 for (j = 0; j < 32; ) { 1189 jfloat val = f[j]; 1190 int last = j; 1191 for ( ; last+1 < 32; ++last ) { 1192 char b1[1024], b2[1024]; 1193 sprintf(b1, "%f", val); 1194 sprintf(b2, "%f", f[last+1]); 1195 if (strcmp(b1, b2)) 1196 break; 1197 } 1198 s->print("f%d", j); 1199 if ( j != last ) s->print(" - f%d", last); 1200 s->print(" = %f", val); 1201 s->fill_to(25); 1202 s->print_cr(" (0x%x)", *(int*)&val); 1203 j = last + 1; 1204 } 1205 s->cr(); 1206 1207 // and doubles (evens only) 1208 for (j = 0; j < 32; ) { 1209 jdouble val = d[j]; 1210 int last = j; 1211 for ( ; last+1 < 32; ++last ) { 1212 char b1[1024], b2[1024]; 1213 sprintf(b1, "%f", val); 1214 sprintf(b2, "%f", d[last+1]); 1215 if (strcmp(b1, b2)) 1216 break; 1217 } 1218 s->print("d%d", 2 * j); 1219 if ( j != last ) s->print(" - d%d", last); 1220 s->print(" = %f", val); 1221 s->fill_to(30); 1222 s->print("(0x%x)", *(int*)&val); 1223 s->fill_to(42); 1224 s->print_cr("(0x%x)", *(1 + (int*)&val)); 1225 j = last + 1; 1226 } 1227 s->cr(); 1228 } 1229 1230 void RegistersForDebugging::save_registers(MacroAssembler* a) { 1231 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); 1232 a->flushw(); 1233 int i; 1234 for (i = 0; i < 8; ++i) { 1235 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); 1236 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); 1237 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); 1238 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); 1239 } 1240 for (i = 0; i < 32; ++i) { 1241 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); 1242 } 1243 for (i = 0; i < 64; i += 2) { 1244 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); 1245 } 1246 } 1247 1248 void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { 1249 for (int i = 1; i < 8; ++i) { 1250 a->ld_ptr(r, g_offset(i), as_gRegister(i)); 1251 } 1252 for (int j = 0; j < 32; ++j) { 1253 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); 1254 } 1255 for (int k = 0; k < 64; k += 2) { 1256 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); 1257 } 1258 } 1259 1260 1261 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1262 void MacroAssembler::push_fTOS() { 1263 // %%%%%% need to implement this 1264 } 1265 1266 // pops double TOS element from CPU stack and pushes on FPU stack 1267 void MacroAssembler::pop_fTOS() { 1268 // %%%%%% need to implement this 1269 } 1270 1271 void MacroAssembler::empty_FPU_stack() { 1272 // %%%%%% need to implement this 1273 } 1274 1275 void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { 1276 // plausibility check for oops 1277 if (!VerifyOops) return; 1278 1279 if (reg == G0) return; // always NULL, which is always an oop 1280 1281 BLOCK_COMMENT("verify_oop {"); 1282 char buffer[64]; 1283 #ifdef COMPILER1 1284 if (CommentedAssembly) { 1285 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); 1286 block_comment(buffer); 1287 } 1288 #endif 1289 1290 const char* real_msg = NULL; 1291 { 1292 ResourceMark rm; 1293 stringStream ss; 1294 ss.print("%s at offset %d (%s:%d)", msg, offset(), file, line); 1295 real_msg = code_string(ss.as_string()); 1296 } 1297 1298 // Call indirectly to solve generation ordering problem 1299 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); 1300 1301 // Make some space on stack above the current register window. 1302 // Enough to hold 8 64-bit registers. 1303 add(SP,-8*8,SP); 1304 1305 // Save some 64-bit registers; a normal 'save' chops the heads off 1306 // of 64-bit longs in the 32-bit build. 1307 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1308 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1309 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed 1310 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1311 1312 // Size of set() should stay the same 1313 patchable_set((intptr_t)real_msg, O1); 1314 // Load address to call to into O7 1315 load_ptr_contents(a, O7); 1316 // Register call to verify_oop_subroutine 1317 callr(O7, G0); 1318 delayed()->nop(); 1319 // recover frame size 1320 add(SP, 8*8,SP); 1321 BLOCK_COMMENT("} verify_oop"); 1322 } 1323 1324 void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { 1325 // plausibility check for oops 1326 if (!VerifyOops) return; 1327 1328 const char* real_msg = NULL; 1329 { 1330 ResourceMark rm; 1331 stringStream ss; 1332 ss.print("%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); 1333 real_msg = code_string(ss.as_string()); 1334 } 1335 1336 // Call indirectly to solve generation ordering problem 1337 AddressLiteral a(StubRoutines::verify_oop_subroutine_entry_address()); 1338 1339 // Make some space on stack above the current register window. 1340 // Enough to hold 8 64-bit registers. 1341 add(SP,-8*8,SP); 1342 1343 // Save some 64-bit registers; a normal 'save' chops the heads off 1344 // of 64-bit longs in the 32-bit build. 1345 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1346 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1347 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed 1348 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1349 1350 // Size of set() should stay the same 1351 patchable_set((intptr_t)real_msg, O1); 1352 // Load address to call to into O7 1353 load_ptr_contents(a, O7); 1354 // Register call to verify_oop_subroutine 1355 callr(O7, G0); 1356 delayed()->nop(); 1357 // recover frame size 1358 add(SP, 8*8,SP); 1359 } 1360 1361 // side-door communication with signalHandler in os_solaris.cpp 1362 address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; 1363 1364 // This macro is expanded just once; it creates shared code. Contract: 1365 // receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY 1366 // registers, including flags. May not use a register 'save', as this blows 1367 // the high bits of the O-regs if they contain Long values. Acts as a 'leaf' 1368 // call. 1369 void MacroAssembler::verify_oop_subroutine() { 1370 // Leaf call; no frame. 1371 Label succeed, fail, null_or_fail; 1372 1373 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). 1374 // O0 is now the oop to be checked. O7 is the return address. 1375 Register O0_obj = O0; 1376 1377 // Save some more registers for temps. 1378 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); 1379 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); 1380 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); 1381 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); 1382 1383 // Save flags 1384 Register O5_save_flags = O5; 1385 rdccr( O5_save_flags ); 1386 1387 { // count number of verifies 1388 Register O2_adr = O2; 1389 Register O3_accum = O3; 1390 inc_counter(StubRoutines::verify_oop_count_addr(), O2_adr, O3_accum); 1391 } 1392 1393 Register O2_mask = O2; 1394 Register O3_bits = O3; 1395 Register O4_temp = O4; 1396 1397 // mark lower end of faulting range 1398 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); 1399 _verify_oop_implicit_branch[0] = pc(); 1400 1401 // We can't check the mark oop because it could be in the process of 1402 // locking or unlocking while this is running. 1403 set(Universe::verify_oop_mask (), O2_mask); 1404 set(Universe::verify_oop_bits (), O3_bits); 1405 1406 // assert((obj & oop_mask) == oop_bits); 1407 and3(O0_obj, O2_mask, O4_temp); 1408 cmp_and_brx_short(O4_temp, O3_bits, notEqual, pn, null_or_fail); 1409 1410 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { 1411 // the null_or_fail case is useless; must test for null separately 1412 br_null_short(O0_obj, pn, succeed); 1413 } 1414 1415 // Check the Klass* of this object for being in the right area of memory. 1416 // Cannot do the load in the delay above slot in case O0 is null 1417 load_klass(O0_obj, O0_obj); 1418 // assert((klass != NULL) 1419 br_null_short(O0_obj, pn, fail); 1420 1421 wrccr( O5_save_flags ); // Restore CCR's 1422 1423 // mark upper end of faulting range 1424 _verify_oop_implicit_branch[1] = pc(); 1425 1426 //----------------------- 1427 // all tests pass 1428 bind(succeed); 1429 1430 // Restore prior 64-bit registers 1431 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); 1432 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); 1433 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); 1434 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); 1435 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); 1436 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); 1437 1438 retl(); // Leaf return; restore prior O7 in delay slot 1439 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); 1440 1441 //----------------------- 1442 bind(null_or_fail); // nulls are less common but OK 1443 br_null(O0_obj, false, pt, succeed); 1444 delayed()->wrccr( O5_save_flags ); // Restore CCR's 1445 1446 //----------------------- 1447 // report failure: 1448 bind(fail); 1449 _verify_oop_implicit_branch[2] = pc(); 1450 1451 wrccr( O5_save_flags ); // Restore CCR's 1452 1453 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1454 1455 // stop_subroutine expects message pointer in I1. 1456 mov(I1, O1); 1457 1458 // Restore prior 64-bit registers 1459 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); 1460 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); 1461 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); 1462 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); 1463 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); 1464 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); 1465 1466 // factor long stop-sequence into subroutine to save space 1467 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1468 1469 // call indirectly to solve generation ordering problem 1470 AddressLiteral al(StubRoutines::Sparc::stop_subroutine_entry_address()); 1471 load_ptr_contents(al, O5); 1472 jmpl(O5, 0, O7); 1473 delayed()->nop(); 1474 } 1475 1476 1477 void MacroAssembler::stop(const char* msg) { 1478 // save frame first to get O7 for return address 1479 // add one word to size in case struct is odd number of words long 1480 // It must be doubleword-aligned for storing doubles into it. 1481 1482 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1483 1484 // stop_subroutine expects message pointer in I1. 1485 // Size of set() should stay the same 1486 patchable_set((intptr_t)msg, O1); 1487 1488 // factor long stop-sequence into subroutine to save space 1489 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1490 1491 // call indirectly to solve generation ordering problem 1492 AddressLiteral a(StubRoutines::Sparc::stop_subroutine_entry_address()); 1493 load_ptr_contents(a, O5); 1494 jmpl(O5, 0, O7); 1495 delayed()->nop(); 1496 1497 breakpoint_trap(); // make stop actually stop rather than writing 1498 // unnoticeable results in the output files. 1499 1500 // restore(); done in callee to save space! 1501 } 1502 1503 1504 void MacroAssembler::warn(const char* msg) { 1505 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1506 RegistersForDebugging::save_registers(this); 1507 mov(O0, L0); 1508 // Size of set() should stay the same 1509 patchable_set((intptr_t)msg, O0); 1510 call( CAST_FROM_FN_PTR(address, warning) ); 1511 delayed()->nop(); 1512 // ret(); 1513 // delayed()->restore(); 1514 RegistersForDebugging::restore_registers(this, L0); 1515 restore(); 1516 } 1517 1518 1519 void MacroAssembler::untested(const char* what) { 1520 // We must be able to turn interactive prompting off 1521 // in order to run automated test scripts on the VM 1522 // Use the flag ShowMessageBoxOnError 1523 1524 const char* b = NULL; 1525 { 1526 ResourceMark rm; 1527 stringStream ss; 1528 ss.print("untested: %s", what); 1529 b = code_string(ss.as_string()); 1530 } 1531 if (ShowMessageBoxOnError) { STOP(b); } 1532 else { warn(b); } 1533 } 1534 1535 1536 void MacroAssembler::stop_subroutine() { 1537 RegistersForDebugging::save_registers(this); 1538 1539 // for the sake of the debugger, stick a PC on the current frame 1540 // (this assumes that the caller has performed an extra "save") 1541 mov(I7, L7); 1542 add(O7, -7 * BytesPerInt, I7); 1543 1544 save_frame(); // one more save to free up another O7 register 1545 mov(I0, O1); // addr of reg save area 1546 1547 // We expect pointer to message in I1. Caller must set it up in O1 1548 mov(I1, O0); // get msg 1549 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); 1550 delayed()->nop(); 1551 1552 restore(); 1553 1554 RegistersForDebugging::restore_registers(this, O0); 1555 1556 save_frame(0); 1557 call(CAST_FROM_FN_PTR(address,breakpoint)); 1558 delayed()->nop(); 1559 restore(); 1560 1561 mov(L7, I7); 1562 retl(); 1563 delayed()->restore(); // see stop above 1564 } 1565 1566 1567 void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { 1568 if ( ShowMessageBoxOnError ) { 1569 JavaThread* thread = JavaThread::current(); 1570 JavaThreadState saved_state = thread->thread_state(); 1571 thread->set_thread_state(_thread_in_vm); 1572 { 1573 // In order to get locks work, we need to fake a in_VM state 1574 ttyLocker ttyl; 1575 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); 1576 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 1577 BytecodeCounter::print(); 1578 } 1579 if (os::message_box(msg, "Execution stopped, print registers?")) 1580 regs->print(::tty); 1581 } 1582 BREAKPOINT; 1583 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); 1584 } 1585 else { 1586 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 1587 } 1588 assert(false, "DEBUG MESSAGE: %s", msg); 1589 } 1590 1591 1592 void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { 1593 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? 1594 Label no_extras; 1595 br( negative, true, pt, no_extras ); // if neg, clear reg 1596 delayed()->set(0, Rresult); // annuled, so only if taken 1597 bind( no_extras ); 1598 } 1599 1600 1601 void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { 1602 #ifdef _LP64 1603 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); 1604 #else 1605 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); 1606 #endif 1607 bclr(1, Rresult); 1608 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes 1609 } 1610 1611 1612 void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { 1613 calc_frame_size(Rextra_words, Rresult); 1614 neg(Rresult); 1615 save(SP, Rresult, SP); 1616 } 1617 1618 1619 // --------------------------------------------------------- 1620 Assembler::RCondition cond2rcond(Assembler::Condition c) { 1621 switch (c) { 1622 /*case zero: */ 1623 case Assembler::equal: return Assembler::rc_z; 1624 case Assembler::lessEqual: return Assembler::rc_lez; 1625 case Assembler::less: return Assembler::rc_lz; 1626 /*case notZero:*/ 1627 case Assembler::notEqual: return Assembler::rc_nz; 1628 case Assembler::greater: return Assembler::rc_gz; 1629 case Assembler::greaterEqual: return Assembler::rc_gez; 1630 } 1631 ShouldNotReachHere(); 1632 return Assembler::rc_z; 1633 } 1634 1635 // compares (32 bit) register with zero and branches. NOT FOR USE WITH 64-bit POINTERS 1636 void MacroAssembler::cmp_zero_and_br(Condition c, Register s1, Label& L, bool a, Predict p) { 1637 tst(s1); 1638 br (c, a, p, L); 1639 } 1640 1641 // Compares a pointer register with zero and branches on null. 1642 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. 1643 void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { 1644 assert_not_delayed(); 1645 #ifdef _LP64 1646 bpr( rc_z, a, p, s1, L ); 1647 #else 1648 tst(s1); 1649 br ( zero, a, p, L ); 1650 #endif 1651 } 1652 1653 void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { 1654 assert_not_delayed(); 1655 #ifdef _LP64 1656 bpr( rc_nz, a, p, s1, L ); 1657 #else 1658 tst(s1); 1659 br ( notZero, a, p, L ); 1660 #endif 1661 } 1662 1663 // Compare registers and branch with nop in delay slot or cbcond without delay slot. 1664 1665 // Compare integer (32 bit) values (icc only). 1666 void MacroAssembler::cmp_and_br_short(Register s1, Register s2, Condition c, 1667 Predict p, Label& L) { 1668 assert_not_delayed(); 1669 if (use_cbcond(L)) { 1670 Assembler::cbcond(c, icc, s1, s2, L); 1671 } else { 1672 cmp(s1, s2); 1673 br(c, false, p, L); 1674 delayed()->nop(); 1675 } 1676 } 1677 1678 // Compare integer (32 bit) values (icc only). 1679 void MacroAssembler::cmp_and_br_short(Register s1, int simm13a, Condition c, 1680 Predict p, Label& L) { 1681 assert_not_delayed(); 1682 if (is_simm(simm13a,5) && use_cbcond(L)) { 1683 Assembler::cbcond(c, icc, s1, simm13a, L); 1684 } else { 1685 cmp(s1, simm13a); 1686 br(c, false, p, L); 1687 delayed()->nop(); 1688 } 1689 } 1690 1691 // Branch that tests xcc in LP64 and icc in !LP64 1692 void MacroAssembler::cmp_and_brx_short(Register s1, Register s2, Condition c, 1693 Predict p, Label& L) { 1694 assert_not_delayed(); 1695 if (use_cbcond(L)) { 1696 Assembler::cbcond(c, ptr_cc, s1, s2, L); 1697 } else { 1698 cmp(s1, s2); 1699 brx(c, false, p, L); 1700 delayed()->nop(); 1701 } 1702 } 1703 1704 // Branch that tests xcc in LP64 and icc in !LP64 1705 void MacroAssembler::cmp_and_brx_short(Register s1, int simm13a, Condition c, 1706 Predict p, Label& L) { 1707 assert_not_delayed(); 1708 if (is_simm(simm13a,5) && use_cbcond(L)) { 1709 Assembler::cbcond(c, ptr_cc, s1, simm13a, L); 1710 } else { 1711 cmp(s1, simm13a); 1712 brx(c, false, p, L); 1713 delayed()->nop(); 1714 } 1715 } 1716 1717 // Short branch version for compares a pointer with zero. 1718 1719 void MacroAssembler::br_null_short(Register s1, Predict p, Label& L) { 1720 assert_not_delayed(); 1721 if (use_cbcond(L)) { 1722 Assembler::cbcond(zero, ptr_cc, s1, 0, L); 1723 return; 1724 } 1725 br_null(s1, false, p, L); 1726 delayed()->nop(); 1727 } 1728 1729 void MacroAssembler::br_notnull_short(Register s1, Predict p, Label& L) { 1730 assert_not_delayed(); 1731 if (use_cbcond(L)) { 1732 Assembler::cbcond(notZero, ptr_cc, s1, 0, L); 1733 return; 1734 } 1735 br_notnull(s1, false, p, L); 1736 delayed()->nop(); 1737 } 1738 1739 // Unconditional short branch 1740 void MacroAssembler::ba_short(Label& L) { 1741 if (use_cbcond(L)) { 1742 Assembler::cbcond(equal, icc, G0, G0, L); 1743 return; 1744 } 1745 br(always, false, pt, L); 1746 delayed()->nop(); 1747 } 1748 1749 // instruction sequences factored across compiler & interpreter 1750 1751 1752 void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, 1753 Register Rb_hi, Register Rb_low, 1754 Register Rresult) { 1755 1756 Label check_low_parts, done; 1757 1758 cmp(Ra_hi, Rb_hi ); // compare hi parts 1759 br(equal, true, pt, check_low_parts); 1760 delayed()->cmp(Ra_low, Rb_low); // test low parts 1761 1762 // And, with an unsigned comparison, it does not matter if the numbers 1763 // are negative or not. 1764 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. 1765 // The second one is bigger (unsignedly). 1766 1767 // Other notes: The first move in each triplet can be unconditional 1768 // (and therefore probably prefetchable). 1769 // And the equals case for the high part does not need testing, 1770 // since that triplet is reached only after finding the high halves differ. 1771 1772 mov(-1, Rresult); 1773 ba(done); 1774 delayed()->movcc(greater, false, icc, 1, Rresult); 1775 1776 bind(check_low_parts); 1777 1778 mov( -1, Rresult); 1779 movcc(equal, false, icc, 0, Rresult); 1780 movcc(greaterUnsigned, false, icc, 1, Rresult); 1781 1782 bind(done); 1783 } 1784 1785 void MacroAssembler::lneg( Register Rhi, Register Rlow ) { 1786 subcc( G0, Rlow, Rlow ); 1787 subc( G0, Rhi, Rhi ); 1788 } 1789 1790 void MacroAssembler::lshl( Register Rin_high, Register Rin_low, 1791 Register Rcount, 1792 Register Rout_high, Register Rout_low, 1793 Register Rtemp ) { 1794 1795 1796 Register Ralt_count = Rtemp; 1797 Register Rxfer_bits = Rtemp; 1798 1799 assert( Ralt_count != Rin_high 1800 && Ralt_count != Rin_low 1801 && Ralt_count != Rcount 1802 && Rxfer_bits != Rin_low 1803 && Rxfer_bits != Rin_high 1804 && Rxfer_bits != Rcount 1805 && Rxfer_bits != Rout_low 1806 && Rout_low != Rin_high, 1807 "register alias checks"); 1808 1809 Label big_shift, done; 1810 1811 // This code can be optimized to use the 64 bit shifts in V9. 1812 // Here we use the 32 bit shifts. 1813 1814 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 1815 subcc(Rcount, 31, Ralt_count); 1816 br(greater, true, pn, big_shift); 1817 delayed()->dec(Ralt_count); 1818 1819 // shift < 32 bits, Ralt_count = Rcount-31 1820 1821 // We get the transfer bits by shifting right by 32-count the low 1822 // register. This is done by shifting right by 31-count and then by one 1823 // more to take care of the special (rare) case where count is zero 1824 // (shifting by 32 would not work). 1825 1826 neg(Ralt_count); 1827 1828 // The order of the next two instructions is critical in the case where 1829 // Rin and Rout are the same and should not be reversed. 1830 1831 srl(Rin_low, Ralt_count, Rxfer_bits); // shift right by 31-count 1832 if (Rcount != Rout_low) { 1833 sll(Rin_low, Rcount, Rout_low); // low half 1834 } 1835 sll(Rin_high, Rcount, Rout_high); 1836 if (Rcount == Rout_low) { 1837 sll(Rin_low, Rcount, Rout_low); // low half 1838 } 1839 srl(Rxfer_bits, 1, Rxfer_bits ); // shift right by one more 1840 ba(done); 1841 delayed()->or3(Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low 1842 1843 // shift >= 32 bits, Ralt_count = Rcount-32 1844 bind(big_shift); 1845 sll(Rin_low, Ralt_count, Rout_high ); 1846 clr(Rout_low); 1847 1848 bind(done); 1849 } 1850 1851 1852 void MacroAssembler::lshr( Register Rin_high, Register Rin_low, 1853 Register Rcount, 1854 Register Rout_high, Register Rout_low, 1855 Register Rtemp ) { 1856 1857 Register Ralt_count = Rtemp; 1858 Register Rxfer_bits = Rtemp; 1859 1860 assert( Ralt_count != Rin_high 1861 && Ralt_count != Rin_low 1862 && Ralt_count != Rcount 1863 && Rxfer_bits != Rin_low 1864 && Rxfer_bits != Rin_high 1865 && Rxfer_bits != Rcount 1866 && Rxfer_bits != Rout_high 1867 && Rout_high != Rin_low, 1868 "register alias checks"); 1869 1870 Label big_shift, done; 1871 1872 // This code can be optimized to use the 64 bit shifts in V9. 1873 // Here we use the 32 bit shifts. 1874 1875 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 1876 subcc(Rcount, 31, Ralt_count); 1877 br(greater, true, pn, big_shift); 1878 delayed()->dec(Ralt_count); 1879 1880 // shift < 32 bits, Ralt_count = Rcount-31 1881 1882 // We get the transfer bits by shifting left by 32-count the high 1883 // register. This is done by shifting left by 31-count and then by one 1884 // more to take care of the special (rare) case where count is zero 1885 // (shifting by 32 would not work). 1886 1887 neg(Ralt_count); 1888 if (Rcount != Rout_low) { 1889 srl(Rin_low, Rcount, Rout_low); 1890 } 1891 1892 // The order of the next two instructions is critical in the case where 1893 // Rin and Rout are the same and should not be reversed. 1894 1895 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count 1896 sra(Rin_high, Rcount, Rout_high ); // high half 1897 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more 1898 if (Rcount == Rout_low) { 1899 srl(Rin_low, Rcount, Rout_low); 1900 } 1901 ba(done); 1902 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high 1903 1904 // shift >= 32 bits, Ralt_count = Rcount-32 1905 bind(big_shift); 1906 1907 sra(Rin_high, Ralt_count, Rout_low); 1908 sra(Rin_high, 31, Rout_high); // sign into hi 1909 1910 bind( done ); 1911 } 1912 1913 1914 1915 void MacroAssembler::lushr( Register Rin_high, Register Rin_low, 1916 Register Rcount, 1917 Register Rout_high, Register Rout_low, 1918 Register Rtemp ) { 1919 1920 Register Ralt_count = Rtemp; 1921 Register Rxfer_bits = Rtemp; 1922 1923 assert( Ralt_count != Rin_high 1924 && Ralt_count != Rin_low 1925 && Ralt_count != Rcount 1926 && Rxfer_bits != Rin_low 1927 && Rxfer_bits != Rin_high 1928 && Rxfer_bits != Rcount 1929 && Rxfer_bits != Rout_high 1930 && Rout_high != Rin_low, 1931 "register alias checks"); 1932 1933 Label big_shift, done; 1934 1935 // This code can be optimized to use the 64 bit shifts in V9. 1936 // Here we use the 32 bit shifts. 1937 1938 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 1939 subcc(Rcount, 31, Ralt_count); 1940 br(greater, true, pn, big_shift); 1941 delayed()->dec(Ralt_count); 1942 1943 // shift < 32 bits, Ralt_count = Rcount-31 1944 1945 // We get the transfer bits by shifting left by 32-count the high 1946 // register. This is done by shifting left by 31-count and then by one 1947 // more to take care of the special (rare) case where count is zero 1948 // (shifting by 32 would not work). 1949 1950 neg(Ralt_count); 1951 if (Rcount != Rout_low) { 1952 srl(Rin_low, Rcount, Rout_low); 1953 } 1954 1955 // The order of the next two instructions is critical in the case where 1956 // Rin and Rout are the same and should not be reversed. 1957 1958 sll(Rin_high, Ralt_count, Rxfer_bits); // shift left by 31-count 1959 srl(Rin_high, Rcount, Rout_high ); // high half 1960 sll(Rxfer_bits, 1, Rxfer_bits); // shift left by one more 1961 if (Rcount == Rout_low) { 1962 srl(Rin_low, Rcount, Rout_low); 1963 } 1964 ba(done); 1965 delayed()->or3(Rout_low, Rxfer_bits, Rout_low); // new low value: or shifted old low part and xfer from high 1966 1967 // shift >= 32 bits, Ralt_count = Rcount-32 1968 bind(big_shift); 1969 1970 srl(Rin_high, Ralt_count, Rout_low); 1971 clr(Rout_high); 1972 1973 bind( done ); 1974 } 1975 1976 #ifdef _LP64 1977 void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { 1978 cmp(Ra, Rb); 1979 mov(-1, Rresult); 1980 movcc(equal, false, xcc, 0, Rresult); 1981 movcc(greater, false, xcc, 1, Rresult); 1982 } 1983 #endif 1984 1985 1986 void MacroAssembler::load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed) { 1987 switch (size_in_bytes) { 1988 case 8: ld_long(src, dst); break; 1989 case 4: ld( src, dst); break; 1990 case 2: is_signed ? ldsh(src, dst) : lduh(src, dst); break; 1991 case 1: is_signed ? ldsb(src, dst) : ldub(src, dst); break; 1992 default: ShouldNotReachHere(); 1993 } 1994 } 1995 1996 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) { 1997 switch (size_in_bytes) { 1998 case 8: st_long(src, dst); break; 1999 case 4: st( src, dst); break; 2000 case 2: sth( src, dst); break; 2001 case 1: stb( src, dst); break; 2002 default: ShouldNotReachHere(); 2003 } 2004 } 2005 2006 2007 void MacroAssembler::float_cmp( bool is_float, int unordered_result, 2008 FloatRegister Fa, FloatRegister Fb, 2009 Register Rresult) { 2010 if (is_float) { 2011 fcmp(FloatRegisterImpl::S, fcc0, Fa, Fb); 2012 } else { 2013 fcmp(FloatRegisterImpl::D, fcc0, Fa, Fb); 2014 } 2015 2016 if (unordered_result == 1) { 2017 mov( -1, Rresult); 2018 movcc(f_equal, true, fcc0, 0, Rresult); 2019 movcc(f_unorderedOrGreater, true, fcc0, 1, Rresult); 2020 } else { 2021 mov( -1, Rresult); 2022 movcc(f_equal, true, fcc0, 0, Rresult); 2023 movcc(f_greater, true, fcc0, 1, Rresult); 2024 } 2025 } 2026 2027 2028 void MacroAssembler::save_all_globals_into_locals() { 2029 mov(G1,L1); 2030 mov(G2,L2); 2031 mov(G3,L3); 2032 mov(G4,L4); 2033 mov(G5,L5); 2034 mov(G6,L6); 2035 mov(G7,L7); 2036 } 2037 2038 void MacroAssembler::restore_globals_from_locals() { 2039 mov(L1,G1); 2040 mov(L2,G2); 2041 mov(L3,G3); 2042 mov(L4,G4); 2043 mov(L5,G5); 2044 mov(L6,G6); 2045 mov(L7,G7); 2046 } 2047 2048 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 2049 Register tmp, 2050 int offset) { 2051 intptr_t value = *delayed_value_addr; 2052 if (value != 0) 2053 return RegisterOrConstant(value + offset); 2054 2055 // load indirectly to solve generation ordering problem 2056 AddressLiteral a(delayed_value_addr); 2057 load_ptr_contents(a, tmp); 2058 2059 #ifdef ASSERT 2060 tst(tmp); 2061 breakpoint_trap(zero, xcc); 2062 #endif 2063 2064 if (offset != 0) 2065 add(tmp, offset, tmp); 2066 2067 return RegisterOrConstant(tmp); 2068 } 2069 2070 2071 RegisterOrConstant MacroAssembler::regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { 2072 assert(d.register_or_noreg() != G0, "lost side effect"); 2073 if ((s2.is_constant() && s2.as_constant() == 0) || 2074 (s2.is_register() && s2.as_register() == G0)) { 2075 // Do nothing, just move value. 2076 if (s1.is_register()) { 2077 if (d.is_constant()) d = temp; 2078 mov(s1.as_register(), d.as_register()); 2079 return d; 2080 } else { 2081 return s1; 2082 } 2083 } 2084 2085 if (s1.is_register()) { 2086 assert_different_registers(s1.as_register(), temp); 2087 if (d.is_constant()) d = temp; 2088 andn(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); 2089 return d; 2090 } else { 2091 if (s2.is_register()) { 2092 assert_different_registers(s2.as_register(), temp); 2093 if (d.is_constant()) d = temp; 2094 set(s1.as_constant(), temp); 2095 andn(temp, s2.as_register(), d.as_register()); 2096 return d; 2097 } else { 2098 intptr_t res = s1.as_constant() & ~s2.as_constant(); 2099 return res; 2100 } 2101 } 2102 } 2103 2104 RegisterOrConstant MacroAssembler::regcon_inc_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { 2105 assert(d.register_or_noreg() != G0, "lost side effect"); 2106 if ((s2.is_constant() && s2.as_constant() == 0) || 2107 (s2.is_register() && s2.as_register() == G0)) { 2108 // Do nothing, just move value. 2109 if (s1.is_register()) { 2110 if (d.is_constant()) d = temp; 2111 mov(s1.as_register(), d.as_register()); 2112 return d; 2113 } else { 2114 return s1; 2115 } 2116 } 2117 2118 if (s1.is_register()) { 2119 assert_different_registers(s1.as_register(), temp); 2120 if (d.is_constant()) d = temp; 2121 add(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); 2122 return d; 2123 } else { 2124 if (s2.is_register()) { 2125 assert_different_registers(s2.as_register(), temp); 2126 if (d.is_constant()) d = temp; 2127 add(s2.as_register(), ensure_simm13_or_reg(s1, temp), d.as_register()); 2128 return d; 2129 } else { 2130 intptr_t res = s1.as_constant() + s2.as_constant(); 2131 return res; 2132 } 2133 } 2134 } 2135 2136 RegisterOrConstant MacroAssembler::regcon_sll_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp) { 2137 assert(d.register_or_noreg() != G0, "lost side effect"); 2138 if (!is_simm13(s2.constant_or_zero())) 2139 s2 = (s2.as_constant() & 0xFF); 2140 if ((s2.is_constant() && s2.as_constant() == 0) || 2141 (s2.is_register() && s2.as_register() == G0)) { 2142 // Do nothing, just move value. 2143 if (s1.is_register()) { 2144 if (d.is_constant()) d = temp; 2145 mov(s1.as_register(), d.as_register()); 2146 return d; 2147 } else { 2148 return s1; 2149 } 2150 } 2151 2152 if (s1.is_register()) { 2153 assert_different_registers(s1.as_register(), temp); 2154 if (d.is_constant()) d = temp; 2155 sll_ptr(s1.as_register(), ensure_simm13_or_reg(s2, temp), d.as_register()); 2156 return d; 2157 } else { 2158 if (s2.is_register()) { 2159 assert_different_registers(s2.as_register(), temp); 2160 if (d.is_constant()) d = temp; 2161 set(s1.as_constant(), temp); 2162 sll_ptr(temp, s2.as_register(), d.as_register()); 2163 return d; 2164 } else { 2165 intptr_t res = s1.as_constant() << s2.as_constant(); 2166 return res; 2167 } 2168 } 2169 } 2170 2171 2172 // Look up the method for a megamorphic invokeinterface call. 2173 // The target method is determined by <intf_klass, itable_index>. 2174 // The receiver klass is in recv_klass. 2175 // On success, the result will be in method_result, and execution falls through. 2176 // On failure, execution transfers to the given label. 2177 void MacroAssembler::lookup_interface_method(Register recv_klass, 2178 Register intf_klass, 2179 RegisterOrConstant itable_index, 2180 Register method_result, 2181 Register scan_temp, 2182 Register sethi_temp, 2183 Label& L_no_such_interface) { 2184 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 2185 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 2186 "caller must use same register for non-constant itable index as for method"); 2187 2188 Label L_no_such_interface_restore; 2189 bool did_save = false; 2190 if (scan_temp == noreg || sethi_temp == noreg) { 2191 Register recv_2 = recv_klass->is_global() ? recv_klass : L0; 2192 Register intf_2 = intf_klass->is_global() ? intf_klass : L1; 2193 assert(method_result->is_global(), "must be able to return value"); 2194 scan_temp = L2; 2195 sethi_temp = L3; 2196 save_frame_and_mov(0, recv_klass, recv_2, intf_klass, intf_2); 2197 recv_klass = recv_2; 2198 intf_klass = intf_2; 2199 did_save = true; 2200 } 2201 2202 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 2203 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize; 2204 int scan_step = itableOffsetEntry::size() * wordSize; 2205 int vte_size = vtableEntry::size() * wordSize; 2206 2207 lduw(recv_klass, InstanceKlass::vtable_length_offset() * wordSize, scan_temp); 2208 // %%% We should store the aligned, prescaled offset in the klassoop. 2209 // Then the next several instructions would fold away. 2210 2211 int round_to_unit = ((HeapWordsPerLong > 1) ? BytesPerLong : 0); 2212 int itb_offset = vtable_base; 2213 if (round_to_unit != 0) { 2214 // hoist first instruction of round_to(scan_temp, BytesPerLong): 2215 itb_offset += round_to_unit - wordSize; 2216 } 2217 int itb_scale = exact_log2(vtableEntry::size() * wordSize); 2218 sll(scan_temp, itb_scale, scan_temp); 2219 add(scan_temp, itb_offset, scan_temp); 2220 if (round_to_unit != 0) { 2221 // Round up to align_object_offset boundary 2222 // see code for InstanceKlass::start_of_itable! 2223 // Was: round_to(scan_temp, BytesPerLong); 2224 // Hoisted: add(scan_temp, BytesPerLong-1, scan_temp); 2225 and3(scan_temp, -round_to_unit, scan_temp); 2226 } 2227 add(recv_klass, scan_temp, scan_temp); 2228 2229 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 2230 RegisterOrConstant itable_offset = itable_index; 2231 itable_offset = regcon_sll_ptr(itable_index, exact_log2(itableMethodEntry::size() * wordSize), itable_offset); 2232 itable_offset = regcon_inc_ptr(itable_offset, itableMethodEntry::method_offset_in_bytes(), itable_offset); 2233 add(recv_klass, ensure_simm13_or_reg(itable_offset, sethi_temp), recv_klass); 2234 2235 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 2236 // if (scan->interface() == intf) { 2237 // result = (klass + scan->offset() + itable_index); 2238 // } 2239 // } 2240 Label L_search, L_found_method; 2241 2242 for (int peel = 1; peel >= 0; peel--) { 2243 // %%%% Could load both offset and interface in one ldx, if they were 2244 // in the opposite order. This would save a load. 2245 ld_ptr(scan_temp, itableOffsetEntry::interface_offset_in_bytes(), method_result); 2246 2247 // Check that this entry is non-null. A null entry means that 2248 // the receiver class doesn't implement the interface, and wasn't the 2249 // same as when the caller was compiled. 2250 bpr(Assembler::rc_z, false, Assembler::pn, method_result, did_save ? L_no_such_interface_restore : L_no_such_interface); 2251 delayed()->cmp(method_result, intf_klass); 2252 2253 if (peel) { 2254 brx(Assembler::equal, false, Assembler::pt, L_found_method); 2255 } else { 2256 brx(Assembler::notEqual, false, Assembler::pn, L_search); 2257 // (invert the test to fall through to found_method...) 2258 } 2259 delayed()->add(scan_temp, scan_step, scan_temp); 2260 2261 if (!peel) break; 2262 2263 bind(L_search); 2264 } 2265 2266 bind(L_found_method); 2267 2268 // Got a hit. 2269 int ito_offset = itableOffsetEntry::offset_offset_in_bytes(); 2270 // scan_temp[-scan_step] points to the vtable offset we need 2271 ito_offset -= scan_step; 2272 lduw(scan_temp, ito_offset, scan_temp); 2273 ld_ptr(recv_klass, scan_temp, method_result); 2274 2275 if (did_save) { 2276 Label L_done; 2277 ba(L_done); 2278 delayed()->restore(); 2279 2280 bind(L_no_such_interface_restore); 2281 ba(L_no_such_interface); 2282 delayed()->restore(); 2283 2284 bind(L_done); 2285 } 2286 } 2287 2288 2289 // virtual method calling 2290 void MacroAssembler::lookup_virtual_method(Register recv_klass, 2291 RegisterOrConstant vtable_index, 2292 Register method_result) { 2293 assert_different_registers(recv_klass, method_result, vtable_index.register_or_noreg()); 2294 Register sethi_temp = method_result; 2295 const int base = (InstanceKlass::vtable_start_offset() * wordSize + 2296 // method pointer offset within the vtable entry: 2297 vtableEntry::method_offset_in_bytes()); 2298 RegisterOrConstant vtable_offset = vtable_index; 2299 // Each of the following three lines potentially generates an instruction. 2300 // But the total number of address formation instructions will always be 2301 // at most two, and will often be zero. In any case, it will be optimal. 2302 // If vtable_index is a register, we will have (sll_ptr N,x; inc_ptr B,x; ld_ptr k,x). 2303 // If vtable_index is a constant, we will have at most (set B+X<<N,t; ld_ptr k,t). 2304 vtable_offset = regcon_sll_ptr(vtable_index, exact_log2(vtableEntry::size() * wordSize), vtable_offset); 2305 vtable_offset = regcon_inc_ptr(vtable_offset, base, vtable_offset, sethi_temp); 2306 Address vtable_entry_addr(recv_klass, ensure_simm13_or_reg(vtable_offset, sethi_temp)); 2307 ld_ptr(vtable_entry_addr, method_result); 2308 } 2309 2310 2311 void MacroAssembler::check_klass_subtype(Register sub_klass, 2312 Register super_klass, 2313 Register temp_reg, 2314 Register temp2_reg, 2315 Label& L_success) { 2316 Register sub_2 = sub_klass; 2317 Register sup_2 = super_klass; 2318 if (!sub_2->is_global()) sub_2 = L0; 2319 if (!sup_2->is_global()) sup_2 = L1; 2320 bool did_save = false; 2321 if (temp_reg == noreg || temp2_reg == noreg) { 2322 temp_reg = L2; 2323 temp2_reg = L3; 2324 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); 2325 sub_klass = sub_2; 2326 super_klass = sup_2; 2327 did_save = true; 2328 } 2329 Label L_failure, L_pop_to_failure, L_pop_to_success; 2330 check_klass_subtype_fast_path(sub_klass, super_klass, 2331 temp_reg, temp2_reg, 2332 (did_save ? &L_pop_to_success : &L_success), 2333 (did_save ? &L_pop_to_failure : &L_failure), NULL); 2334 2335 if (!did_save) 2336 save_frame_and_mov(0, sub_klass, sub_2, super_klass, sup_2); 2337 check_klass_subtype_slow_path(sub_2, sup_2, 2338 L2, L3, L4, L5, 2339 NULL, &L_pop_to_failure); 2340 2341 // on success: 2342 bind(L_pop_to_success); 2343 restore(); 2344 ba_short(L_success); 2345 2346 // on failure: 2347 bind(L_pop_to_failure); 2348 restore(); 2349 bind(L_failure); 2350 } 2351 2352 2353 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 2354 Register super_klass, 2355 Register temp_reg, 2356 Register temp2_reg, 2357 Label* L_success, 2358 Label* L_failure, 2359 Label* L_slow_path, 2360 RegisterOrConstant super_check_offset) { 2361 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 2362 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2363 2364 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 2365 bool need_slow_path = (must_load_sco || 2366 super_check_offset.constant_or_zero() == sco_offset); 2367 2368 assert_different_registers(sub_klass, super_klass, temp_reg); 2369 if (super_check_offset.is_register()) { 2370 assert_different_registers(sub_klass, super_klass, temp_reg, 2371 super_check_offset.as_register()); 2372 } else if (must_load_sco) { 2373 assert(temp2_reg != noreg, "supply either a temp or a register offset"); 2374 } 2375 2376 Label L_fallthrough; 2377 int label_nulls = 0; 2378 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 2379 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 2380 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 2381 assert(label_nulls <= 1 || 2382 (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path), 2383 "at most one NULL in the batch, usually"); 2384 2385 // If the pointers are equal, we are done (e.g., String[] elements). 2386 // This self-check enables sharing of secondary supertype arrays among 2387 // non-primary types such as array-of-interface. Otherwise, each such 2388 // type would need its own customized SSA. 2389 // We move this check to the front of the fast path because many 2390 // type checks are in fact trivially successful in this manner, 2391 // so we get a nicely predicted branch right at the start of the check. 2392 cmp(super_klass, sub_klass); 2393 brx(Assembler::equal, false, Assembler::pn, *L_success); 2394 delayed()->nop(); 2395 2396 // Check the supertype display: 2397 if (must_load_sco) { 2398 // The super check offset is always positive... 2399 lduw(super_klass, sco_offset, temp2_reg); 2400 super_check_offset = RegisterOrConstant(temp2_reg); 2401 // super_check_offset is register. 2402 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset.as_register()); 2403 } 2404 ld_ptr(sub_klass, super_check_offset, temp_reg); 2405 cmp(super_klass, temp_reg); 2406 2407 // This check has worked decisively for primary supers. 2408 // Secondary supers are sought in the super_cache ('super_cache_addr'). 2409 // (Secondary supers are interfaces and very deeply nested subtypes.) 2410 // This works in the same check above because of a tricky aliasing 2411 // between the super_cache and the primary super display elements. 2412 // (The 'super_check_addr' can address either, as the case requires.) 2413 // Note that the cache is updated below if it does not help us find 2414 // what we need immediately. 2415 // So if it was a primary super, we can just fail immediately. 2416 // Otherwise, it's the slow path for us (no success at this point). 2417 2418 // Hacked ba(), which may only be used just before L_fallthrough. 2419 #define FINAL_JUMP(label) \ 2420 if (&(label) != &L_fallthrough) { \ 2421 ba(label); delayed()->nop(); \ 2422 } 2423 2424 if (super_check_offset.is_register()) { 2425 brx(Assembler::equal, false, Assembler::pn, *L_success); 2426 delayed()->cmp(super_check_offset.as_register(), sc_offset); 2427 2428 if (L_failure == &L_fallthrough) { 2429 brx(Assembler::equal, false, Assembler::pt, *L_slow_path); 2430 delayed()->nop(); 2431 } else { 2432 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); 2433 delayed()->nop(); 2434 FINAL_JUMP(*L_slow_path); 2435 } 2436 } else if (super_check_offset.as_constant() == sc_offset) { 2437 // Need a slow path; fast failure is impossible. 2438 if (L_slow_path == &L_fallthrough) { 2439 brx(Assembler::equal, false, Assembler::pt, *L_success); 2440 delayed()->nop(); 2441 } else { 2442 brx(Assembler::notEqual, false, Assembler::pn, *L_slow_path); 2443 delayed()->nop(); 2444 FINAL_JUMP(*L_success); 2445 } 2446 } else { 2447 // No slow path; it's a fast decision. 2448 if (L_failure == &L_fallthrough) { 2449 brx(Assembler::equal, false, Assembler::pt, *L_success); 2450 delayed()->nop(); 2451 } else { 2452 brx(Assembler::notEqual, false, Assembler::pn, *L_failure); 2453 delayed()->nop(); 2454 FINAL_JUMP(*L_success); 2455 } 2456 } 2457 2458 bind(L_fallthrough); 2459 2460 #undef FINAL_JUMP 2461 } 2462 2463 2464 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 2465 Register super_klass, 2466 Register count_temp, 2467 Register scan_temp, 2468 Register scratch_reg, 2469 Register coop_reg, 2470 Label* L_success, 2471 Label* L_failure) { 2472 assert_different_registers(sub_klass, super_klass, 2473 count_temp, scan_temp, scratch_reg, coop_reg); 2474 2475 Label L_fallthrough, L_loop; 2476 int label_nulls = 0; 2477 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 2478 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 2479 assert(label_nulls <= 1, "at most one NULL in the batch"); 2480 2481 // a couple of useful fields in sub_klass: 2482 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 2483 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 2484 2485 // Do a linear scan of the secondary super-klass chain. 2486 // This code is rarely used, so simplicity is a virtue here. 2487 2488 #ifndef PRODUCT 2489 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 2490 inc_counter((address) pst_counter, count_temp, scan_temp); 2491 #endif 2492 2493 // We will consult the secondary-super array. 2494 ld_ptr(sub_klass, ss_offset, scan_temp); 2495 2496 Register search_key = super_klass; 2497 2498 // Load the array length. (Positive movl does right thing on LP64.) 2499 lduw(scan_temp, Array<Klass*>::length_offset_in_bytes(), count_temp); 2500 2501 // Check for empty secondary super list 2502 tst(count_temp); 2503 2504 // In the array of super classes elements are pointer sized. 2505 int element_size = wordSize; 2506 2507 // Top of search loop 2508 bind(L_loop); 2509 br(Assembler::equal, false, Assembler::pn, *L_failure); 2510 delayed()->add(scan_temp, element_size, scan_temp); 2511 2512 // Skip the array header in all array accesses. 2513 int elem_offset = Array<Klass*>::base_offset_in_bytes(); 2514 elem_offset -= element_size; // the scan pointer was pre-incremented also 2515 2516 // Load next super to check 2517 ld_ptr( scan_temp, elem_offset, scratch_reg ); 2518 2519 // Look for Rsuper_klass on Rsub_klass's secondary super-class-overflow list 2520 cmp(scratch_reg, search_key); 2521 2522 // A miss means we are NOT a subtype and need to keep looping 2523 brx(Assembler::notEqual, false, Assembler::pn, L_loop); 2524 delayed()->deccc(count_temp); // decrement trip counter in delay slot 2525 2526 // Success. Cache the super we found and proceed in triumph. 2527 st_ptr(super_klass, sub_klass, sc_offset); 2528 2529 if (L_success != &L_fallthrough) { 2530 ba(*L_success); 2531 delayed()->nop(); 2532 } 2533 2534 bind(L_fallthrough); 2535 } 2536 2537 2538 RegisterOrConstant MacroAssembler::argument_offset(RegisterOrConstant arg_slot, 2539 Register temp_reg, 2540 int extra_slot_offset) { 2541 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 2542 int stackElementSize = Interpreter::stackElementSize; 2543 int offset = extra_slot_offset * stackElementSize; 2544 if (arg_slot.is_constant()) { 2545 offset += arg_slot.as_constant() * stackElementSize; 2546 return offset; 2547 } else { 2548 assert(temp_reg != noreg, "must specify"); 2549 sll_ptr(arg_slot.as_register(), exact_log2(stackElementSize), temp_reg); 2550 if (offset != 0) 2551 add(temp_reg, offset, temp_reg); 2552 return temp_reg; 2553 } 2554 } 2555 2556 2557 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 2558 Register temp_reg, 2559 int extra_slot_offset) { 2560 return Address(Gargs, argument_offset(arg_slot, temp_reg, extra_slot_offset)); 2561 } 2562 2563 2564 void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, 2565 Register temp_reg, 2566 Label& done, Label* slow_case, 2567 BiasedLockingCounters* counters) { 2568 assert(UseBiasedLocking, "why call this otherwise?"); 2569 2570 if (PrintBiasedLockingStatistics) { 2571 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); 2572 if (counters == NULL) 2573 counters = BiasedLocking::counters(); 2574 } 2575 2576 Label cas_label; 2577 2578 // Biased locking 2579 // See whether the lock is currently biased toward our thread and 2580 // whether the epoch is still valid 2581 // Note that the runtime guarantees sufficient alignment of JavaThread 2582 // pointers to allow age to be placed into low bits 2583 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 2584 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2585 cmp_and_brx_short(temp_reg, markOopDesc::biased_lock_pattern, Assembler::notEqual, Assembler::pn, cas_label); 2586 2587 load_klass(obj_reg, temp_reg); 2588 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); 2589 or3(G2_thread, temp_reg, temp_reg); 2590 xor3(mark_reg, temp_reg, temp_reg); 2591 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); 2592 if (counters != NULL) { 2593 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); 2594 // Reload mark_reg as we may need it later 2595 ld_ptr(Address(obj_reg, oopDesc::mark_offset_in_bytes()), mark_reg); 2596 } 2597 brx(Assembler::equal, true, Assembler::pt, done); 2598 delayed()->nop(); 2599 2600 Label try_revoke_bias; 2601 Label try_rebias; 2602 Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes()); 2603 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2604 2605 // At this point we know that the header has the bias pattern and 2606 // that we are not the bias owner in the current epoch. We need to 2607 // figure out more details about the state of the header in order to 2608 // know what operations can be legally performed on the object's 2609 // header. 2610 2611 // If the low three bits in the xor result aren't clear, that means 2612 // the prototype header is no longer biased and we have to revoke 2613 // the bias on this object. 2614 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); 2615 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); 2616 2617 // Biasing is still enabled for this data type. See whether the 2618 // epoch of the current bias is still valid, meaning that the epoch 2619 // bits of the mark word are equal to the epoch bits of the 2620 // prototype header. (Note that the prototype header's epoch bits 2621 // only change at a safepoint.) If not, attempt to rebias the object 2622 // toward the current thread. Note that we must be absolutely sure 2623 // that the current epoch is invalid in order to do this because 2624 // otherwise the manipulations it performs on the mark word are 2625 // illegal. 2626 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); 2627 brx(Assembler::notZero, false, Assembler::pn, try_rebias); 2628 2629 // The epoch of the current bias is still valid but we know nothing 2630 // about the owner; it might be set or it might be clear. Try to 2631 // acquire the bias of the object using an atomic operation. If this 2632 // fails we will go in to the runtime to revoke the object's bias. 2633 // Note that we first construct the presumed unbiased header so we 2634 // don't accidentally blow away another thread's valid bias. 2635 delayed()->and3(mark_reg, 2636 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, 2637 mark_reg); 2638 or3(G2_thread, mark_reg, temp_reg); 2639 cas_ptr(mark_addr.base(), mark_reg, temp_reg); 2640 // If the biasing toward our thread failed, this means that 2641 // another thread succeeded in biasing it toward itself and we 2642 // need to revoke that bias. The revocation will occur in the 2643 // interpreter runtime in the slow case. 2644 cmp(mark_reg, temp_reg); 2645 if (counters != NULL) { 2646 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); 2647 } 2648 if (slow_case != NULL) { 2649 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2650 delayed()->nop(); 2651 } 2652 ba_short(done); 2653 2654 bind(try_rebias); 2655 // At this point we know the epoch has expired, meaning that the 2656 // current "bias owner", if any, is actually invalid. Under these 2657 // circumstances _only_, we are allowed to use the current header's 2658 // value as the comparison value when doing the cas to acquire the 2659 // bias in the current epoch. In other words, we allow transfer of 2660 // the bias from one thread to another directly in this situation. 2661 // 2662 // FIXME: due to a lack of registers we currently blow away the age 2663 // bits in this situation. Should attempt to preserve them. 2664 load_klass(obj_reg, temp_reg); 2665 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); 2666 or3(G2_thread, temp_reg, temp_reg); 2667 cas_ptr(mark_addr.base(), mark_reg, temp_reg); 2668 // If the biasing toward our thread failed, this means that 2669 // another thread succeeded in biasing it toward itself and we 2670 // need to revoke that bias. The revocation will occur in the 2671 // interpreter runtime in the slow case. 2672 cmp(mark_reg, temp_reg); 2673 if (counters != NULL) { 2674 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); 2675 } 2676 if (slow_case != NULL) { 2677 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2678 delayed()->nop(); 2679 } 2680 ba_short(done); 2681 2682 bind(try_revoke_bias); 2683 // The prototype mark in the klass doesn't have the bias bit set any 2684 // more, indicating that objects of this data type are not supposed 2685 // to be biased any more. We are going to try to reset the mark of 2686 // this object to the prototype value and fall through to the 2687 // CAS-based locking scheme. Note that if our CAS fails, it means 2688 // that another thread raced us for the privilege of revoking the 2689 // bias of this particular object, so it's okay to continue in the 2690 // normal locking code. 2691 // 2692 // FIXME: due to a lack of registers we currently blow away the age 2693 // bits in this situation. Should attempt to preserve them. 2694 load_klass(obj_reg, temp_reg); 2695 ld_ptr(Address(temp_reg, Klass::prototype_header_offset()), temp_reg); 2696 cas_ptr(mark_addr.base(), mark_reg, temp_reg); 2697 // Fall through to the normal CAS-based lock, because no matter what 2698 // the result of the above CAS, some thread must have succeeded in 2699 // removing the bias bit from the object's header. 2700 if (counters != NULL) { 2701 cmp(mark_reg, temp_reg); 2702 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); 2703 } 2704 2705 bind(cas_label); 2706 } 2707 2708 void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, 2709 bool allow_delay_slot_filling) { 2710 // Check for biased locking unlock case, which is a no-op 2711 // Note: we do not have to check the thread ID for two reasons. 2712 // First, the interpreter checks for IllegalMonitorStateException at 2713 // a higher level. Second, if the bias was revoked while we held the 2714 // lock, the object could not be rebiased toward another thread, so 2715 // the bias bit would be clear. 2716 ld_ptr(mark_addr, temp_reg); 2717 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2718 cmp(temp_reg, markOopDesc::biased_lock_pattern); 2719 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); 2720 delayed(); 2721 if (!allow_delay_slot_filling) { 2722 nop(); 2723 } 2724 } 2725 2726 2727 // compiler_lock_object() and compiler_unlock_object() are direct transliterations 2728 // of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. 2729 // The code could be tightened up considerably. 2730 // 2731 // box->dhw disposition - post-conditions at DONE_LABEL. 2732 // - Successful inflated lock: box->dhw != 0. 2733 // Any non-zero value suffices. 2734 // Consider G2_thread, rsp, boxReg, or markOopDesc::unused_mark() 2735 // - Successful Stack-lock: box->dhw == mark. 2736 // box->dhw must contain the displaced mark word value 2737 // - Failure -- icc.ZFlag == 0 and box->dhw is undefined. 2738 // The slow-path fast_enter() and slow_enter() operators 2739 // are responsible for setting box->dhw = NonZero (typically markOopDesc::unused_mark()). 2740 // - Biased: box->dhw is undefined 2741 // 2742 // SPARC refworkload performance - specifically jetstream and scimark - are 2743 // extremely sensitive to the size of the code emitted by compiler_lock_object 2744 // and compiler_unlock_object. Critically, the key factor is code size, not path 2745 // length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the 2746 // effect). 2747 2748 2749 void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, 2750 Register Rbox, Register Rscratch, 2751 BiasedLockingCounters* counters, 2752 bool try_bias) { 2753 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); 2754 2755 verify_oop(Roop); 2756 Label done ; 2757 2758 if (counters != NULL) { 2759 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); 2760 } 2761 2762 if (EmitSync & 1) { 2763 mov(3, Rscratch); 2764 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2765 cmp(SP, G0); 2766 return ; 2767 } 2768 2769 if (EmitSync & 2) { 2770 2771 // Fetch object's markword 2772 ld_ptr(mark_addr, Rmark); 2773 2774 if (try_bias) { 2775 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2776 } 2777 2778 // Save Rbox in Rscratch to be used for the cas operation 2779 mov(Rbox, Rscratch); 2780 2781 // set Rmark to markOop | markOopDesc::unlocked_value 2782 or3(Rmark, markOopDesc::unlocked_value, Rmark); 2783 2784 // Initialize the box. (Must happen before we update the object mark!) 2785 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2786 2787 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop 2788 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2789 cas_ptr(mark_addr.base(), Rmark, Rscratch); 2790 2791 // if compare/exchange succeeded we found an unlocked object and we now have locked it 2792 // hence we are done 2793 cmp(Rmark, Rscratch); 2794 #ifdef _LP64 2795 sub(Rscratch, STACK_BIAS, Rscratch); 2796 #endif 2797 brx(Assembler::equal, false, Assembler::pt, done); 2798 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot 2799 2800 // we did not find an unlocked object so see if this is a recursive case 2801 // sub(Rscratch, SP, Rscratch); 2802 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2803 andcc(Rscratch, 0xfffff003, Rscratch); 2804 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2805 bind (done); 2806 return ; 2807 } 2808 2809 Label Egress ; 2810 2811 if (EmitSync & 256) { 2812 Label IsInflated ; 2813 2814 ld_ptr(mark_addr, Rmark); // fetch obj->mark 2815 // Triage: biased, stack-locked, neutral, inflated 2816 if (try_bias) { 2817 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2818 // Invariant: if control reaches this point in the emitted stream 2819 // then Rmark has not been modified. 2820 } 2821 2822 // Store mark into displaced mark field in the on-stack basic-lock "box" 2823 // Critically, this must happen before the CAS 2824 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. 2825 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2826 andcc(Rmark, 2, G0); 2827 brx(Assembler::notZero, false, Assembler::pn, IsInflated); 2828 delayed()-> 2829 2830 // Try stack-lock acquisition. 2831 // Beware: the 1st instruction is in a delay slot 2832 mov(Rbox, Rscratch); 2833 or3(Rmark, markOopDesc::unlocked_value, Rmark); 2834 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2835 cas_ptr(mark_addr.base(), Rmark, Rscratch); 2836 cmp(Rmark, Rscratch); 2837 brx(Assembler::equal, false, Assembler::pt, done); 2838 delayed()->sub(Rscratch, SP, Rscratch); 2839 2840 // Stack-lock attempt failed - check for recursive stack-lock. 2841 // See the comments below about how we might remove this case. 2842 #ifdef _LP64 2843 sub(Rscratch, STACK_BIAS, Rscratch); 2844 #endif 2845 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2846 andcc(Rscratch, 0xfffff003, Rscratch); 2847 br(Assembler::always, false, Assembler::pt, done); 2848 delayed()-> st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2849 2850 bind(IsInflated); 2851 if (EmitSync & 64) { 2852 // If m->owner != null goto IsLocked 2853 // Pessimistic form: Test-and-CAS vs CAS 2854 // The optimistic form avoids RTS->RTO cache line upgrades. 2855 ld_ptr(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rscratch); 2856 andcc(Rscratch, Rscratch, G0); 2857 brx(Assembler::notZero, false, Assembler::pn, done); 2858 delayed()->nop(); 2859 // m->owner == null : it's unlocked. 2860 } 2861 2862 // Try to CAS m->owner from null to Self 2863 // Invariant: if we acquire the lock then _recursions should be 0. 2864 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark); 2865 mov(G2_thread, Rscratch); 2866 cas_ptr(Rmark, G0, Rscratch); 2867 cmp(Rscratch, G0); 2868 // Intentional fall-through into done 2869 } else { 2870 // Aggressively avoid the Store-before-CAS penalty 2871 // Defer the store into box->dhw until after the CAS 2872 Label IsInflated, Recursive ; 2873 2874 // Anticipate CAS -- Avoid RTS->RTO upgrade 2875 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); 2876 2877 ld_ptr(mark_addr, Rmark); // fetch obj->mark 2878 // Triage: biased, stack-locked, neutral, inflated 2879 2880 if (try_bias) { 2881 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2882 // Invariant: if control reaches this point in the emitted stream 2883 // then Rmark has not been modified. 2884 } 2885 andcc(Rmark, 2, G0); 2886 brx(Assembler::notZero, false, Assembler::pn, IsInflated); 2887 delayed()-> // Beware - dangling delay-slot 2888 2889 // Try stack-lock acquisition. 2890 // Transiently install BUSY (0) encoding in the mark word. 2891 // if the CAS of 0 into the mark was successful then we execute: 2892 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box 2893 // ST obj->mark = box -- overwrite transient 0 value 2894 // This presumes TSO, of course. 2895 2896 mov(0, Rscratch); 2897 or3(Rmark, markOopDesc::unlocked_value, Rmark); 2898 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2899 cas_ptr(mark_addr.base(), Rmark, Rscratch); 2900 // prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads); 2901 cmp(Rscratch, Rmark); 2902 brx(Assembler::notZero, false, Assembler::pn, Recursive); 2903 delayed()->st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2904 if (counters != NULL) { 2905 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 2906 } 2907 ba(done); 2908 delayed()->st_ptr(Rbox, mark_addr); 2909 2910 bind(Recursive); 2911 // Stack-lock attempt failed - check for recursive stack-lock. 2912 // Tests show that we can remove the recursive case with no impact 2913 // on refworkload 0.83. If we need to reduce the size of the code 2914 // emitted by compiler_lock_object() the recursive case is perfect 2915 // candidate. 2916 // 2917 // A more extreme idea is to always inflate on stack-lock recursion. 2918 // This lets us eliminate the recursive checks in compiler_lock_object 2919 // and compiler_unlock_object and the (box->dhw == 0) encoding. 2920 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, 2921 // and showed a performance *increase*. In the same experiment I eliminated 2922 // the fast-path stack-lock code from the interpreter and always passed 2923 // control to the "slow" operators in synchronizer.cpp. 2924 2925 // RScratch contains the fetched obj->mark value from the failed CAS. 2926 #ifdef _LP64 2927 sub(Rscratch, STACK_BIAS, Rscratch); 2928 #endif 2929 sub(Rscratch, SP, Rscratch); 2930 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2931 andcc(Rscratch, 0xfffff003, Rscratch); 2932 if (counters != NULL) { 2933 // Accounting needs the Rscratch register 2934 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2935 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 2936 ba_short(done); 2937 } else { 2938 ba(done); 2939 delayed()->st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2940 } 2941 2942 bind (IsInflated); 2943 2944 // Try to CAS m->owner from null to Self 2945 // Invariant: if we acquire the lock then _recursions should be 0. 2946 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark); 2947 mov(G2_thread, Rscratch); 2948 cas_ptr(Rmark, G0, Rscratch); 2949 andcc(Rscratch, Rscratch, G0); // set ICCs for done: icc.zf iff success 2950 // set icc.zf : 1=success 0=failure 2951 // ST box->displaced_header = NonZero. 2952 // Any non-zero value suffices: 2953 // markOopDesc::unused_mark(), G2_thread, RBox, RScratch, rsp, etc. 2954 st_ptr(Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2955 // Intentional fall-through into done 2956 } 2957 2958 bind (done); 2959 } 2960 2961 void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, 2962 Register Rbox, Register Rscratch, 2963 bool try_bias) { 2964 Address mark_addr(Roop, oopDesc::mark_offset_in_bytes()); 2965 2966 Label done ; 2967 2968 if (EmitSync & 4) { 2969 cmp(SP, G0); 2970 return ; 2971 } 2972 2973 if (EmitSync & 8) { 2974 if (try_bias) { 2975 biased_locking_exit(mark_addr, Rscratch, done); 2976 } 2977 2978 // Test first if it is a fast recursive unlock 2979 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); 2980 br_null_short(Rmark, Assembler::pt, done); 2981 2982 // Check if it is still a light weight lock, this is is true if we see 2983 // the stack address of the basicLock in the markOop of the object 2984 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2985 cas_ptr(mark_addr.base(), Rbox, Rmark); 2986 ba(done); 2987 delayed()->cmp(Rbox, Rmark); 2988 bind(done); 2989 return ; 2990 } 2991 2992 // Beware ... If the aggregate size of the code emitted by CLO and CUO is 2993 // is too large performance rolls abruptly off a cliff. 2994 // This could be related to inlining policies, code cache management, or 2995 // I$ effects. 2996 Label LStacked ; 2997 2998 if (try_bias) { 2999 // TODO: eliminate redundant LDs of obj->mark 3000 biased_locking_exit(mark_addr, Rscratch, done); 3001 } 3002 3003 ld_ptr(Roop, oopDesc::mark_offset_in_bytes(), Rmark); 3004 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); 3005 andcc(Rscratch, Rscratch, G0); 3006 brx(Assembler::zero, false, Assembler::pn, done); 3007 delayed()->nop(); // consider: relocate fetch of mark, above, into this DS 3008 andcc(Rmark, 2, G0); 3009 brx(Assembler::zero, false, Assembler::pt, LStacked); 3010 delayed()->nop(); 3011 3012 // It's inflated 3013 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before 3014 // the ST of 0 into _owner which releases the lock. This prevents loads 3015 // and stores within the critical section from reordering (floating) 3016 // past the store that releases the lock. But TSO is a strong memory model 3017 // and that particular flavor of barrier is a noop, so we can safely elide it. 3018 // Note that we use 1-0 locking by default for the inflated case. We 3019 // close the resultant (and rare) race by having contended threads in 3020 // monitorenter periodically poll _owner. 3021 3022 if (EmitSync & 1024) { 3023 // Emit code to check that _owner == Self 3024 // We could fold the _owner test into subsequent code more efficiently 3025 // than using a stand-alone check, but since _owner checking is off by 3026 // default we don't bother. We also might consider predicating the 3027 // _owner==Self check on Xcheck:jni or running on a debug build. 3028 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), Rscratch); 3029 orcc(Rscratch, G0, G0); 3030 brx(Assembler::notZero, false, Assembler::pn, done); 3031 delayed()->nop(); 3032 } 3033 3034 if (EmitSync & 512) { 3035 // classic lock release code absent 1-0 locking 3036 // m->Owner = null; 3037 // membar #storeload 3038 // if (m->cxq|m->EntryList) == null goto Success 3039 // if (m->succ != null) goto Success 3040 // if CAS (&m->Owner,0,Self) != 0 goto Success 3041 // goto SlowPath 3042 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)), Rbox); 3043 orcc(Rbox, G0, G0); 3044 brx(Assembler::notZero, false, Assembler::pn, done); 3045 delayed()->nop(); 3046 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 3047 if (os::is_MP()) { membar(StoreLoad); } 3048 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)), Rscratch); 3049 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)), Rbox); 3050 orcc(Rbox, Rscratch, G0); 3051 brx(Assembler::zero, false, Assembler::pt, done); 3052 delayed()-> 3053 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch); 3054 andcc(Rscratch, Rscratch, G0); 3055 brx(Assembler::notZero, false, Assembler::pt, done); 3056 delayed()->andcc(G0, G0, G0); 3057 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark); 3058 mov(G2_thread, Rscratch); 3059 cas_ptr(Rmark, G0, Rscratch); 3060 cmp(Rscratch, G0); 3061 // invert icc.zf and goto done 3062 brx(Assembler::notZero, false, Assembler::pt, done); 3063 delayed()->cmp(G0, G0); 3064 br(Assembler::always, false, Assembler::pt, done); 3065 delayed()->cmp(G0, 1); 3066 } else { 3067 // 1-0 form : avoids CAS and MEMBAR in the common case 3068 // Do not bother to ratify that m->Owner == Self. 3069 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)), Rbox); 3070 orcc(Rbox, G0, G0); 3071 brx(Assembler::notZero, false, Assembler::pn, done); 3072 delayed()-> 3073 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)), Rscratch); 3074 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)), Rbox); 3075 orcc(Rbox, Rscratch, G0); 3076 if (EmitSync & 16384) { 3077 // As an optional optimization, if (EntryList|cxq) != null and _succ is null then 3078 // we should transfer control directly to the slow-path. 3079 // This test makes the reacquire operation below very infrequent. 3080 // The logic is equivalent to : 3081 // if (cxq|EntryList) == null : Owner=null; goto Success 3082 // if succ == null : goto SlowPath 3083 // Owner=null; membar #storeload 3084 // if succ != null : goto Success 3085 // if CAS(&Owner,null,Self) != null goto Success 3086 // goto SlowPath 3087 brx(Assembler::zero, true, Assembler::pt, done); 3088 delayed()-> 3089 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 3090 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch); 3091 andcc(Rscratch, Rscratch, G0) ; 3092 brx(Assembler::zero, false, Assembler::pt, done); 3093 delayed()->orcc(G0, 1, G0); 3094 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 3095 } else { 3096 brx(Assembler::zero, false, Assembler::pt, done); 3097 delayed()-> 3098 st_ptr(G0, Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 3099 } 3100 if (os::is_MP()) { membar(StoreLoad); } 3101 // Check that _succ is (or remains) non-zero 3102 ld_ptr(Address(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), Rscratch); 3103 andcc(Rscratch, Rscratch, G0); 3104 brx(Assembler::notZero, false, Assembler::pt, done); 3105 delayed()->andcc(G0, G0, G0); 3106 add(Rmark, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), Rmark); 3107 mov(G2_thread, Rscratch); 3108 cas_ptr(Rmark, G0, Rscratch); 3109 cmp(Rscratch, G0); 3110 // invert icc.zf and goto done 3111 // A slightly better v8+/v9 idiom would be the following: 3112 // movrnz Rscratch,1,Rscratch 3113 // ba done 3114 // xorcc Rscratch,1,G0 3115 // In v8+ mode the idiom would be valid IFF Rscratch was a G or O register 3116 brx(Assembler::notZero, false, Assembler::pt, done); 3117 delayed()->cmp(G0, G0); 3118 br(Assembler::always, false, Assembler::pt, done); 3119 delayed()->cmp(G0, 1); 3120 } 3121 3122 bind (LStacked); 3123 // Consider: we could replace the expensive CAS in the exit 3124 // path with a simple ST of the displaced mark value fetched from 3125 // the on-stack basiclock box. That admits a race where a thread T2 3126 // in the slow lock path -- inflating with monitor M -- could race a 3127 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. 3128 // More precisely T1 in the stack-lock unlock path could "stomp" the 3129 // inflated mark value M installed by T2, resulting in an orphan 3130 // object monitor M and T2 becoming stranded. We can remedy that situation 3131 // by having T2 periodically poll the object's mark word using timed wait 3132 // operations. If T2 discovers that a stomp has occurred it vacates 3133 // the monitor M and wakes any other threads stranded on the now-orphan M. 3134 // In addition the monitor scavenger, which performs deflation, 3135 // would also need to check for orpan monitors and stranded threads. 3136 // 3137 // Finally, inflation is also used when T2 needs to assign a hashCode 3138 // to O and O is stack-locked by T1. The "stomp" race could cause 3139 // an assigned hashCode value to be lost. We can avoid that condition 3140 // and provide the necessary hashCode stability invariants by ensuring 3141 // that hashCode generation is idempotent between copying GCs. 3142 // For example we could compute the hashCode of an object O as 3143 // O's heap address XOR some high quality RNG value that is refreshed 3144 // at GC-time. The monitor scavenger would install the hashCode 3145 // found in any orphan monitors. Again, the mechanism admits a 3146 // lost-update "stomp" WAW race but detects and recovers as needed. 3147 // 3148 // A prototype implementation showed excellent results, although 3149 // the scavenger and timeout code was rather involved. 3150 3151 cas_ptr(mark_addr.base(), Rbox, Rscratch); 3152 cmp(Rbox, Rscratch); 3153 // Intentional fall through into done ... 3154 3155 bind(done); 3156 } 3157 3158 3159 3160 void MacroAssembler::print_CPU_state() { 3161 // %%%%% need to implement this 3162 } 3163 3164 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 3165 // %%%%% need to implement this 3166 } 3167 3168 void MacroAssembler::push_IU_state() { 3169 // %%%%% need to implement this 3170 } 3171 3172 3173 void MacroAssembler::pop_IU_state() { 3174 // %%%%% need to implement this 3175 } 3176 3177 3178 void MacroAssembler::push_FPU_state() { 3179 // %%%%% need to implement this 3180 } 3181 3182 3183 void MacroAssembler::pop_FPU_state() { 3184 // %%%%% need to implement this 3185 } 3186 3187 3188 void MacroAssembler::push_CPU_state() { 3189 // %%%%% need to implement this 3190 } 3191 3192 3193 void MacroAssembler::pop_CPU_state() { 3194 // %%%%% need to implement this 3195 } 3196 3197 3198 3199 void MacroAssembler::verify_tlab() { 3200 #ifdef ASSERT 3201 if (UseTLAB && VerifyOops) { 3202 Label next, next2, ok; 3203 Register t1 = L0; 3204 Register t2 = L1; 3205 Register t3 = L2; 3206 3207 save_frame(0); 3208 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3209 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); 3210 or3(t1, t2, t3); 3211 cmp_and_br_short(t1, t2, Assembler::greaterEqual, Assembler::pn, next); 3212 STOP("assert(top >= start)"); 3213 should_not_reach_here(); 3214 3215 bind(next); 3216 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3217 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); 3218 or3(t3, t2, t3); 3219 cmp_and_br_short(t1, t2, Assembler::lessEqual, Assembler::pn, next2); 3220 STOP("assert(top <= end)"); 3221 should_not_reach_here(); 3222 3223 bind(next2); 3224 and3(t3, MinObjAlignmentInBytesMask, t3); 3225 cmp_and_br_short(t3, 0, Assembler::lessEqual, Assembler::pn, ok); 3226 STOP("assert(aligned)"); 3227 should_not_reach_here(); 3228 3229 bind(ok); 3230 restore(); 3231 } 3232 #endif 3233 } 3234 3235 3236 void MacroAssembler::eden_allocate( 3237 Register obj, // result: pointer to object after successful allocation 3238 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3239 int con_size_in_bytes, // object size in bytes if known at compile time 3240 Register t1, // temp register 3241 Register t2, // temp register 3242 Label& slow_case // continuation point if fast allocation fails 3243 ){ 3244 // make sure arguments make sense 3245 assert_different_registers(obj, var_size_in_bytes, t1, t2); 3246 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); 3247 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3248 3249 if (!Universe::heap()->supports_inline_contig_alloc()) { 3250 // No allocation in the shared eden. 3251 ba(slow_case); 3252 delayed()->nop(); 3253 } else { 3254 // get eden boundaries 3255 // note: we need both top & top_addr! 3256 const Register top_addr = t1; 3257 const Register end = t2; 3258 3259 CollectedHeap* ch = Universe::heap(); 3260 set((intx)ch->top_addr(), top_addr); 3261 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); 3262 ld_ptr(top_addr, delta, end); 3263 ld_ptr(top_addr, 0, obj); 3264 3265 // try to allocate 3266 Label retry; 3267 bind(retry); 3268 #ifdef ASSERT 3269 // make sure eden top is properly aligned 3270 { 3271 Label L; 3272 btst(MinObjAlignmentInBytesMask, obj); 3273 br(Assembler::zero, false, Assembler::pt, L); 3274 delayed()->nop(); 3275 STOP("eden top is not properly aligned"); 3276 bind(L); 3277 } 3278 #endif // ASSERT 3279 const Register free = end; 3280 sub(end, obj, free); // compute amount of free space 3281 if (var_size_in_bytes->is_valid()) { 3282 // size is unknown at compile time 3283 cmp(free, var_size_in_bytes); 3284 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3285 delayed()->add(obj, var_size_in_bytes, end); 3286 } else { 3287 // size is known at compile time 3288 cmp(free, con_size_in_bytes); 3289 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3290 delayed()->add(obj, con_size_in_bytes, end); 3291 } 3292 // Compare obj with the value at top_addr; if still equal, swap the value of 3293 // end with the value at top_addr. If not equal, read the value at top_addr 3294 // into end. 3295 cas_ptr(top_addr, obj, end); 3296 // if someone beat us on the allocation, try again, otherwise continue 3297 cmp(obj, end); 3298 brx(Assembler::notEqual, false, Assembler::pn, retry); 3299 delayed()->mov(end, obj); // nop if successfull since obj == end 3300 3301 #ifdef ASSERT 3302 // make sure eden top is properly aligned 3303 { 3304 Label L; 3305 const Register top_addr = t1; 3306 3307 set((intx)ch->top_addr(), top_addr); 3308 ld_ptr(top_addr, 0, top_addr); 3309 btst(MinObjAlignmentInBytesMask, top_addr); 3310 br(Assembler::zero, false, Assembler::pt, L); 3311 delayed()->nop(); 3312 STOP("eden top is not properly aligned"); 3313 bind(L); 3314 } 3315 #endif // ASSERT 3316 } 3317 } 3318 3319 3320 void MacroAssembler::tlab_allocate( 3321 Register obj, // result: pointer to object after successful allocation 3322 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3323 int con_size_in_bytes, // object size in bytes if known at compile time 3324 Register t1, // temp register 3325 Label& slow_case // continuation point if fast allocation fails 3326 ){ 3327 // make sure arguments make sense 3328 assert_different_registers(obj, var_size_in_bytes, t1); 3329 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); 3330 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3331 3332 const Register free = t1; 3333 3334 verify_tlab(); 3335 3336 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); 3337 3338 // calculate amount of free space 3339 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); 3340 sub(free, obj, free); 3341 3342 Label done; 3343 if (var_size_in_bytes == noreg) { 3344 cmp(free, con_size_in_bytes); 3345 } else { 3346 cmp(free, var_size_in_bytes); 3347 } 3348 br(Assembler::less, false, Assembler::pn, slow_case); 3349 // calculate the new top pointer 3350 if (var_size_in_bytes == noreg) { 3351 delayed()->add(obj, con_size_in_bytes, free); 3352 } else { 3353 delayed()->add(obj, var_size_in_bytes, free); 3354 } 3355 3356 bind(done); 3357 3358 #ifdef ASSERT 3359 // make sure new free pointer is properly aligned 3360 { 3361 Label L; 3362 btst(MinObjAlignmentInBytesMask, free); 3363 br(Assembler::zero, false, Assembler::pt, L); 3364 delayed()->nop(); 3365 STOP("updated TLAB free is not properly aligned"); 3366 bind(L); 3367 } 3368 #endif // ASSERT 3369 3370 // update the tlab top pointer 3371 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3372 verify_tlab(); 3373 } 3374 3375 3376 void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { 3377 Register top = O0; 3378 Register t1 = G1; 3379 Register t2 = G3; 3380 Register t3 = O1; 3381 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); 3382 Label do_refill, discard_tlab; 3383 3384 if (!Universe::heap()->supports_inline_contig_alloc()) { 3385 // No allocation in the shared eden. 3386 ba(slow_case); 3387 delayed()->nop(); 3388 } 3389 3390 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); 3391 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); 3392 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); 3393 3394 // calculate amount of free space 3395 sub(t1, top, t1); 3396 srl_ptr(t1, LogHeapWordSize, t1); 3397 3398 // Retain tlab and allocate object in shared space if 3399 // the amount free in the tlab is too large to discard. 3400 cmp(t1, t2); 3401 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); 3402 3403 // increment waste limit to prevent getting stuck on this slow path 3404 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); 3405 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); 3406 if (TLABStats) { 3407 // increment number of slow_allocations 3408 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); 3409 add(t2, 1, t2); 3410 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); 3411 } 3412 ba(try_eden); 3413 delayed()->nop(); 3414 3415 bind(discard_tlab); 3416 if (TLABStats) { 3417 // increment number of refills 3418 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); 3419 add(t2, 1, t2); 3420 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); 3421 // accumulate wastage 3422 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); 3423 add(t2, t1, t2); 3424 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); 3425 } 3426 3427 // if tlab is currently allocated (top or end != null) then 3428 // fill [top, end + alignment_reserve) with array object 3429 br_null_short(top, Assembler::pn, do_refill); 3430 3431 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); 3432 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word 3433 // set klass to intArrayKlass 3434 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); 3435 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); 3436 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); 3437 st(t1, top, arrayOopDesc::length_offset_in_bytes()); 3438 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); 3439 ld_ptr(t2, 0, t2); 3440 // store klass last. concurrent gcs assumes klass length is valid if 3441 // klass field is not null. 3442 store_klass(t2, top); 3443 verify_oop(top); 3444 3445 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t1); 3446 sub(top, t1, t1); // size of tlab's allocated portion 3447 incr_allocated_bytes(t1, t2, t3); 3448 3449 // refill the tlab with an eden allocation 3450 bind(do_refill); 3451 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); 3452 sll_ptr(t1, LogHeapWordSize, t1); 3453 // allocate new tlab, address returned in top 3454 eden_allocate(top, t1, 0, t2, t3, slow_case); 3455 3456 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); 3457 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3458 #ifdef ASSERT 3459 // check that tlab_size (t1) is still valid 3460 { 3461 Label ok; 3462 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); 3463 sll_ptr(t2, LogHeapWordSize, t2); 3464 cmp_and_br_short(t1, t2, Assembler::equal, Assembler::pt, ok); 3465 STOP("assert(t1 == tlab_size)"); 3466 should_not_reach_here(); 3467 3468 bind(ok); 3469 } 3470 #endif // ASSERT 3471 add(top, t1, top); // t1 is tlab_size 3472 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); 3473 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); 3474 verify_tlab(); 3475 ba(retry); 3476 delayed()->nop(); 3477 } 3478 3479 void MacroAssembler::incr_allocated_bytes(RegisterOrConstant size_in_bytes, 3480 Register t1, Register t2) { 3481 // Bump total bytes allocated by this thread 3482 assert(t1->is_global(), "must be global reg"); // so all 64 bits are saved on a context switch 3483 assert_different_registers(size_in_bytes.register_or_noreg(), t1, t2); 3484 // v8 support has gone the way of the dodo 3485 ldx(G2_thread, in_bytes(JavaThread::allocated_bytes_offset()), t1); 3486 add(t1, ensure_simm13_or_reg(size_in_bytes, t2), t1); 3487 stx(t1, G2_thread, in_bytes(JavaThread::allocated_bytes_offset())); 3488 } 3489 3490 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 3491 switch (cond) { 3492 // Note some conditions are synonyms for others 3493 case Assembler::never: return Assembler::always; 3494 case Assembler::zero: return Assembler::notZero; 3495 case Assembler::lessEqual: return Assembler::greater; 3496 case Assembler::less: return Assembler::greaterEqual; 3497 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; 3498 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; 3499 case Assembler::negative: return Assembler::positive; 3500 case Assembler::overflowSet: return Assembler::overflowClear; 3501 case Assembler::always: return Assembler::never; 3502 case Assembler::notZero: return Assembler::zero; 3503 case Assembler::greater: return Assembler::lessEqual; 3504 case Assembler::greaterEqual: return Assembler::less; 3505 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; 3506 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; 3507 case Assembler::positive: return Assembler::negative; 3508 case Assembler::overflowClear: return Assembler::overflowSet; 3509 } 3510 3511 ShouldNotReachHere(); return Assembler::overflowClear; 3512 } 3513 3514 void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, 3515 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { 3516 Condition negated_cond = negate_condition(cond); 3517 Label L; 3518 brx(negated_cond, false, Assembler::pt, L); 3519 delayed()->nop(); 3520 inc_counter(counter_ptr, Rtmp1, Rtmp2); 3521 bind(L); 3522 } 3523 3524 void MacroAssembler::inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2) { 3525 AddressLiteral addrlit(counter_addr); 3526 sethi(addrlit, Rtmp1); // Move hi22 bits into temporary register. 3527 Address addr(Rtmp1, addrlit.low10()); // Build an address with low10 bits. 3528 ld(addr, Rtmp2); 3529 inc(Rtmp2); 3530 st(Rtmp2, addr); 3531 } 3532 3533 void MacroAssembler::inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2) { 3534 inc_counter((address) counter_addr, Rtmp1, Rtmp2); 3535 } 3536 3537 SkipIfEqual::SkipIfEqual( 3538 MacroAssembler* masm, Register temp, const bool* flag_addr, 3539 Assembler::Condition condition) { 3540 _masm = masm; 3541 AddressLiteral flag(flag_addr); 3542 _masm->sethi(flag, temp); 3543 _masm->ldub(temp, flag.low10(), temp); 3544 _masm->tst(temp); 3545 _masm->br(condition, false, Assembler::pt, _label); 3546 _masm->delayed()->nop(); 3547 } 3548 3549 SkipIfEqual::~SkipIfEqual() { 3550 _masm->bind(_label); 3551 } 3552 3553 3554 // Writes to stack successive pages until offset reached to check for 3555 // stack overflow + shadow pages. This clobbers tsp and scratch. 3556 void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, 3557 Register Rscratch) { 3558 // Use stack pointer in temp stack pointer 3559 mov(SP, Rtsp); 3560 3561 // Bang stack for total size given plus stack shadow page size. 3562 // Bang one page at a time because a large size can overflow yellow and 3563 // red zones (the bang will fail but stack overflow handling can't tell that 3564 // it was a stack overflow bang vs a regular segv). 3565 int offset = os::vm_page_size(); 3566 Register Roffset = Rscratch; 3567 3568 Label loop; 3569 bind(loop); 3570 set((-offset)+STACK_BIAS, Rscratch); 3571 st(G0, Rtsp, Rscratch); 3572 set(offset, Roffset); 3573 sub(Rsize, Roffset, Rsize); 3574 cmp(Rsize, G0); 3575 br(Assembler::greater, false, Assembler::pn, loop); 3576 delayed()->sub(Rtsp, Roffset, Rtsp); 3577 3578 // Bang down shadow pages too. 3579 // At this point, (tmp-0) is the last address touched, so don't 3580 // touch it again. (It was touched as (tmp-pagesize) but then tmp 3581 // was post-decremented.) Skip this address by starting at i=1, and 3582 // touch a few more pages below. N.B. It is important to touch all 3583 // the way down to and including i=StackShadowPages. 3584 for (int i = 1; i < StackShadowPages; i++) { 3585 set((-i*offset)+STACK_BIAS, Rscratch); 3586 st(G0, Rtsp, Rscratch); 3587 } 3588 } 3589 3590 void MacroAssembler::reserved_stack_check() { 3591 // testing if reserved zone needs to be enabled 3592 Label no_reserved_zone_enabling; 3593 3594 ld_ptr(G2_thread, JavaThread::reserved_stack_activation_offset(), G4_scratch); 3595 cmp_and_brx_short(SP, G4_scratch, Assembler::lessUnsigned, Assembler::pt, no_reserved_zone_enabling); 3596 3597 call_VM_leaf(L0, CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), G2_thread); 3598 3599 AddressLiteral stub(StubRoutines::throw_delayed_StackOverflowError_entry()); 3600 jump_to(stub, G4_scratch); 3601 delayed()->restore(); 3602 3603 should_not_reach_here(); 3604 3605 bind(no_reserved_zone_enabling); 3606 } 3607 3608 /////////////////////////////////////////////////////////////////////////////////// 3609 #if INCLUDE_ALL_GCS 3610 3611 static address satb_log_enqueue_with_frame = NULL; 3612 static u_char* satb_log_enqueue_with_frame_end = NULL; 3613 3614 static address satb_log_enqueue_frameless = NULL; 3615 static u_char* satb_log_enqueue_frameless_end = NULL; 3616 3617 static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? 3618 3619 static void generate_satb_log_enqueue(bool with_frame) { 3620 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); 3621 CodeBuffer buf(bb); 3622 MacroAssembler masm(&buf); 3623 3624 #define __ masm. 3625 3626 address start = __ pc(); 3627 Register pre_val; 3628 3629 Label refill, restart; 3630 if (with_frame) { 3631 __ save_frame(0); 3632 pre_val = I0; // Was O0 before the save. 3633 } else { 3634 pre_val = O0; 3635 } 3636 3637 int satb_q_index_byte_offset = 3638 in_bytes(JavaThread::satb_mark_queue_offset() + 3639 SATBMarkQueue::byte_offset_of_index()); 3640 3641 int satb_q_buf_byte_offset = 3642 in_bytes(JavaThread::satb_mark_queue_offset() + 3643 SATBMarkQueue::byte_offset_of_buf()); 3644 3645 assert(in_bytes(SATBMarkQueue::byte_width_of_index()) == sizeof(intptr_t) && 3646 in_bytes(SATBMarkQueue::byte_width_of_buf()) == sizeof(intptr_t), 3647 "check sizes in assembly below"); 3648 3649 __ bind(restart); 3650 3651 // Load the index into the SATB buffer. SATBMarkQueue::_index is a size_t 3652 // so ld_ptr is appropriate. 3653 __ ld_ptr(G2_thread, satb_q_index_byte_offset, L0); 3654 3655 // index == 0? 3656 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); 3657 3658 __ ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); 3659 __ sub(L0, oopSize, L0); 3660 3661 __ st_ptr(pre_val, L1, L0); // [_buf + index] := I0 3662 if (!with_frame) { 3663 // Use return-from-leaf 3664 __ retl(); 3665 __ delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); 3666 } else { 3667 // Not delayed. 3668 __ st_ptr(L0, G2_thread, satb_q_index_byte_offset); 3669 } 3670 if (with_frame) { 3671 __ ret(); 3672 __ delayed()->restore(); 3673 } 3674 __ bind(refill); 3675 3676 address handle_zero = 3677 CAST_FROM_FN_PTR(address, 3678 &SATBMarkQueueSet::handle_zero_index_for_thread); 3679 // This should be rare enough that we can afford to save all the 3680 // scratch registers that the calling context might be using. 3681 __ mov(G1_scratch, L0); 3682 __ mov(G3_scratch, L1); 3683 __ mov(G4, L2); 3684 // We need the value of O0 above (for the write into the buffer), so we 3685 // save and restore it. 3686 __ mov(O0, L3); 3687 // Since the call will overwrite O7, we save and restore that, as well. 3688 __ mov(O7, L4); 3689 __ call_VM_leaf(L5, handle_zero, G2_thread); 3690 __ mov(L0, G1_scratch); 3691 __ mov(L1, G3_scratch); 3692 __ mov(L2, G4); 3693 __ mov(L3, O0); 3694 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); 3695 __ delayed()->mov(L4, O7); 3696 3697 if (with_frame) { 3698 satb_log_enqueue_with_frame = start; 3699 satb_log_enqueue_with_frame_end = __ pc(); 3700 } else { 3701 satb_log_enqueue_frameless = start; 3702 satb_log_enqueue_frameless_end = __ pc(); 3703 } 3704 3705 #undef __ 3706 } 3707 3708 static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { 3709 if (with_frame) { 3710 if (satb_log_enqueue_with_frame == 0) { 3711 generate_satb_log_enqueue(with_frame); 3712 assert(satb_log_enqueue_with_frame != 0, "postcondition."); 3713 } 3714 } else { 3715 if (satb_log_enqueue_frameless == 0) { 3716 generate_satb_log_enqueue(with_frame); 3717 assert(satb_log_enqueue_frameless != 0, "postcondition."); 3718 } 3719 } 3720 } 3721 3722 void MacroAssembler::g1_write_barrier_pre(Register obj, 3723 Register index, 3724 int offset, 3725 Register pre_val, 3726 Register tmp, 3727 bool preserve_o_regs) { 3728 Label filtered; 3729 3730 if (obj == noreg) { 3731 // We are not loading the previous value so make 3732 // sure that we don't trash the value in pre_val 3733 // with the code below. 3734 assert_different_registers(pre_val, tmp); 3735 } else { 3736 // We will be loading the previous value 3737 // in this code so... 3738 assert(offset == 0 || index == noreg, "choose one"); 3739 assert(pre_val == noreg, "check this code"); 3740 } 3741 3742 // Is marking active? 3743 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 3744 ld(G2, 3745 in_bytes(JavaThread::satb_mark_queue_offset() + 3746 SATBMarkQueue::byte_offset_of_active()), 3747 tmp); 3748 } else { 3749 guarantee(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, 3750 "Assumption"); 3751 ldsb(G2, 3752 in_bytes(JavaThread::satb_mark_queue_offset() + 3753 SATBMarkQueue::byte_offset_of_active()), 3754 tmp); 3755 } 3756 3757 // Is marking active? 3758 cmp_and_br_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); 3759 3760 // Do we need to load the previous value? 3761 if (obj != noreg) { 3762 // Load the previous value... 3763 if (index == noreg) { 3764 if (Assembler::is_simm13(offset)) { 3765 load_heap_oop(obj, offset, tmp); 3766 } else { 3767 set(offset, tmp); 3768 load_heap_oop(obj, tmp, tmp); 3769 } 3770 } else { 3771 load_heap_oop(obj, index, tmp); 3772 } 3773 // Previous value has been loaded into tmp 3774 pre_val = tmp; 3775 } 3776 3777 assert(pre_val != noreg, "must have a real register"); 3778 3779 // Is the previous value null? 3780 cmp_and_brx_short(pre_val, G0, Assembler::equal, Assembler::pt, filtered); 3781 3782 // OK, it's not filtered, so we'll need to call enqueue. In the normal 3783 // case, pre_val will be a scratch G-reg, but there are some cases in 3784 // which it's an O-reg. In the first case, do a normal call. In the 3785 // latter, do a save here and call the frameless version. 3786 3787 guarantee(pre_val->is_global() || pre_val->is_out(), 3788 "Or we need to think harder."); 3789 3790 if (pre_val->is_global() && !preserve_o_regs) { 3791 generate_satb_log_enqueue_if_necessary(true); // with frame 3792 3793 call(satb_log_enqueue_with_frame); 3794 delayed()->mov(pre_val, O0); 3795 } else { 3796 generate_satb_log_enqueue_if_necessary(false); // frameless 3797 3798 save_frame(0); 3799 call(satb_log_enqueue_frameless); 3800 delayed()->mov(pre_val->after_save(), O0); 3801 restore(); 3802 } 3803 3804 bind(filtered); 3805 } 3806 3807 static address dirty_card_log_enqueue = 0; 3808 static u_char* dirty_card_log_enqueue_end = 0; 3809 3810 // This gets to assume that o0 contains the object address. 3811 static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { 3812 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); 3813 CodeBuffer buf(bb); 3814 MacroAssembler masm(&buf); 3815 #define __ masm. 3816 address start = __ pc(); 3817 3818 Label not_already_dirty, restart, refill, young_card; 3819 3820 #ifdef _LP64 3821 __ srlx(O0, CardTableModRefBS::card_shift, O0); 3822 #else 3823 __ srl(O0, CardTableModRefBS::card_shift, O0); 3824 #endif 3825 AddressLiteral addrlit(byte_map_base); 3826 __ set(addrlit, O1); // O1 := <card table base> 3827 __ ldub(O0, O1, O2); // O2 := [O0 + O1] 3828 3829 __ cmp_and_br_short(O2, G1SATBCardTableModRefBS::g1_young_card_val(), Assembler::equal, Assembler::pt, young_card); 3830 3831 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3832 __ ldub(O0, O1, O2); // O2 := [O0 + O1] 3833 3834 assert(CardTableModRefBS::dirty_card_val() == 0, "otherwise check this code"); 3835 __ cmp_and_br_short(O2, G0, Assembler::notEqual, Assembler::pt, not_already_dirty); 3836 3837 __ bind(young_card); 3838 // We didn't take the branch, so we're already dirty: return. 3839 // Use return-from-leaf 3840 __ retl(); 3841 __ delayed()->nop(); 3842 3843 // Not dirty. 3844 __ bind(not_already_dirty); 3845 3846 // Get O0 + O1 into a reg by itself 3847 __ add(O0, O1, O3); 3848 3849 // First, dirty it. 3850 __ stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). 3851 3852 int dirty_card_q_index_byte_offset = 3853 in_bytes(JavaThread::dirty_card_queue_offset() + 3854 DirtyCardQueue::byte_offset_of_index()); 3855 int dirty_card_q_buf_byte_offset = 3856 in_bytes(JavaThread::dirty_card_queue_offset() + 3857 DirtyCardQueue::byte_offset_of_buf()); 3858 __ bind(restart); 3859 3860 // Load the index into the update buffer. DirtyCardQueue::_index is 3861 // a size_t so ld_ptr is appropriate here. 3862 __ ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); 3863 3864 // index == 0? 3865 __ cmp_and_brx_short(L0, G0, Assembler::equal, Assembler::pn, refill); 3866 3867 __ ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); 3868 __ sub(L0, oopSize, L0); 3869 3870 __ st_ptr(O3, L1, L0); // [_buf + index] := I0 3871 // Use return-from-leaf 3872 __ retl(); 3873 __ delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); 3874 3875 __ bind(refill); 3876 address handle_zero = 3877 CAST_FROM_FN_PTR(address, 3878 &DirtyCardQueueSet::handle_zero_index_for_thread); 3879 // This should be rare enough that we can afford to save all the 3880 // scratch registers that the calling context might be using. 3881 __ mov(G1_scratch, L3); 3882 __ mov(G3_scratch, L5); 3883 // We need the value of O3 above (for the write into the buffer), so we 3884 // save and restore it. 3885 __ mov(O3, L6); 3886 // Since the call will overwrite O7, we save and restore that, as well. 3887 __ mov(O7, L4); 3888 3889 __ call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); 3890 __ mov(L3, G1_scratch); 3891 __ mov(L5, G3_scratch); 3892 __ mov(L6, O3); 3893 __ br(Assembler::always, /*annul*/false, Assembler::pt, restart); 3894 __ delayed()->mov(L4, O7); 3895 3896 dirty_card_log_enqueue = start; 3897 dirty_card_log_enqueue_end = __ pc(); 3898 // XXX Should have a guarantee here about not going off the end! 3899 // Does it already do so? Do an experiment... 3900 3901 #undef __ 3902 3903 } 3904 3905 static inline void 3906 generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { 3907 if (dirty_card_log_enqueue == 0) { 3908 generate_dirty_card_log_enqueue(byte_map_base); 3909 assert(dirty_card_log_enqueue != 0, "postcondition."); 3910 } 3911 } 3912 3913 3914 void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { 3915 3916 Label filtered; 3917 MacroAssembler* post_filter_masm = this; 3918 3919 if (new_val == G0) return; 3920 3921 G1SATBCardTableLoggingModRefBS* bs = 3922 barrier_set_cast<G1SATBCardTableLoggingModRefBS>(Universe::heap()->barrier_set()); 3923 3924 if (G1RSBarrierRegionFilter) { 3925 xor3(store_addr, new_val, tmp); 3926 #ifdef _LP64 3927 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); 3928 #else 3929 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); 3930 #endif 3931 3932 // XXX Should I predict this taken or not? Does it matter? 3933 cmp_and_brx_short(tmp, G0, Assembler::equal, Assembler::pt, filtered); 3934 } 3935 3936 // If the "store_addr" register is an "in" or "local" register, move it to 3937 // a scratch reg so we can pass it as an argument. 3938 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); 3939 // Pick a scratch register different from "tmp". 3940 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); 3941 // Make sure we use up the delay slot! 3942 if (use_scr) { 3943 post_filter_masm->mov(store_addr, scr); 3944 } else { 3945 post_filter_masm->nop(); 3946 } 3947 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); 3948 save_frame(0); 3949 call(dirty_card_log_enqueue); 3950 if (use_scr) { 3951 delayed()->mov(scr, O0); 3952 } else { 3953 delayed()->mov(store_addr->after_save(), O0); 3954 } 3955 restore(); 3956 3957 bind(filtered); 3958 } 3959 3960 #endif // INCLUDE_ALL_GCS 3961 /////////////////////////////////////////////////////////////////////////////////// 3962 3963 void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { 3964 // If we're writing constant NULL, we can skip the write barrier. 3965 if (new_val == G0) return; 3966 CardTableModRefBS* bs = 3967 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 3968 assert(bs->kind() == BarrierSet::CardTableForRS || 3969 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); 3970 card_table_write(bs->byte_map_base, tmp, store_addr); 3971 } 3972 3973 void MacroAssembler::load_klass(Register src_oop, Register klass) { 3974 // The number of bytes in this code is used by 3975 // MachCallDynamicJavaNode::ret_addr_offset() 3976 // if this changes, change that. 3977 if (UseCompressedClassPointers) { 3978 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); 3979 decode_klass_not_null(klass); 3980 } else { 3981 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); 3982 } 3983 } 3984 3985 void MacroAssembler::store_klass(Register klass, Register dst_oop) { 3986 if (UseCompressedClassPointers) { 3987 assert(dst_oop != klass, "not enough registers"); 3988 encode_klass_not_null(klass); 3989 st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); 3990 } else { 3991 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); 3992 } 3993 } 3994 3995 void MacroAssembler::store_klass_gap(Register s, Register d) { 3996 if (UseCompressedClassPointers) { 3997 assert(s != d, "not enough registers"); 3998 st(s, d, oopDesc::klass_gap_offset_in_bytes()); 3999 } 4000 } 4001 4002 void MacroAssembler::load_heap_oop(const Address& s, Register d) { 4003 if (UseCompressedOops) { 4004 lduw(s, d); 4005 decode_heap_oop(d); 4006 } else { 4007 ld_ptr(s, d); 4008 } 4009 } 4010 4011 void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { 4012 if (UseCompressedOops) { 4013 lduw(s1, s2, d); 4014 decode_heap_oop(d, d); 4015 } else { 4016 ld_ptr(s1, s2, d); 4017 } 4018 } 4019 4020 void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { 4021 if (UseCompressedOops) { 4022 lduw(s1, simm13a, d); 4023 decode_heap_oop(d, d); 4024 } else { 4025 ld_ptr(s1, simm13a, d); 4026 } 4027 } 4028 4029 void MacroAssembler::load_heap_oop(Register s1, RegisterOrConstant s2, Register d) { 4030 if (s2.is_constant()) load_heap_oop(s1, s2.as_constant(), d); 4031 else load_heap_oop(s1, s2.as_register(), d); 4032 } 4033 4034 void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { 4035 if (UseCompressedOops) { 4036 assert(s1 != d && s2 != d, "not enough registers"); 4037 encode_heap_oop(d); 4038 st(d, s1, s2); 4039 } else { 4040 st_ptr(d, s1, s2); 4041 } 4042 } 4043 4044 void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { 4045 if (UseCompressedOops) { 4046 assert(s1 != d, "not enough registers"); 4047 encode_heap_oop(d); 4048 st(d, s1, simm13a); 4049 } else { 4050 st_ptr(d, s1, simm13a); 4051 } 4052 } 4053 4054 void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { 4055 if (UseCompressedOops) { 4056 assert(a.base() != d, "not enough registers"); 4057 encode_heap_oop(d); 4058 st(d, a, offset); 4059 } else { 4060 st_ptr(d, a, offset); 4061 } 4062 } 4063 4064 4065 void MacroAssembler::encode_heap_oop(Register src, Register dst) { 4066 assert (UseCompressedOops, "must be compressed"); 4067 assert (Universe::heap() != NULL, "java heap should be initialized"); 4068 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4069 verify_oop(src); 4070 if (Universe::narrow_oop_base() == NULL) { 4071 srlx(src, LogMinObjAlignmentInBytes, dst); 4072 return; 4073 } 4074 Label done; 4075 if (src == dst) { 4076 // optimize for frequent case src == dst 4077 bpr(rc_nz, true, Assembler::pt, src, done); 4078 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken 4079 bind(done); 4080 srlx(src, LogMinObjAlignmentInBytes, dst); 4081 } else { 4082 bpr(rc_z, false, Assembler::pn, src, done); 4083 delayed() -> mov(G0, dst); 4084 // could be moved before branch, and annulate delay, 4085 // but may add some unneeded work decoding null 4086 sub(src, G6_heapbase, dst); 4087 srlx(dst, LogMinObjAlignmentInBytes, dst); 4088 bind(done); 4089 } 4090 } 4091 4092 4093 void MacroAssembler::encode_heap_oop_not_null(Register r) { 4094 assert (UseCompressedOops, "must be compressed"); 4095 assert (Universe::heap() != NULL, "java heap should be initialized"); 4096 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4097 verify_oop(r); 4098 if (Universe::narrow_oop_base() != NULL) 4099 sub(r, G6_heapbase, r); 4100 srlx(r, LogMinObjAlignmentInBytes, r); 4101 } 4102 4103 void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { 4104 assert (UseCompressedOops, "must be compressed"); 4105 assert (Universe::heap() != NULL, "java heap should be initialized"); 4106 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4107 verify_oop(src); 4108 if (Universe::narrow_oop_base() == NULL) { 4109 srlx(src, LogMinObjAlignmentInBytes, dst); 4110 } else { 4111 sub(src, G6_heapbase, dst); 4112 srlx(dst, LogMinObjAlignmentInBytes, dst); 4113 } 4114 } 4115 4116 // Same algorithm as oops.inline.hpp decode_heap_oop. 4117 void MacroAssembler::decode_heap_oop(Register src, Register dst) { 4118 assert (UseCompressedOops, "must be compressed"); 4119 assert (Universe::heap() != NULL, "java heap should be initialized"); 4120 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4121 sllx(src, LogMinObjAlignmentInBytes, dst); 4122 if (Universe::narrow_oop_base() != NULL) { 4123 Label done; 4124 bpr(rc_nz, true, Assembler::pt, dst, done); 4125 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken 4126 bind(done); 4127 } 4128 verify_oop(dst); 4129 } 4130 4131 void MacroAssembler::decode_heap_oop_not_null(Register r) { 4132 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4133 // pd_code_size_limit. 4134 // Also do not verify_oop as this is called by verify_oop. 4135 assert (UseCompressedOops, "must be compressed"); 4136 assert (Universe::heap() != NULL, "java heap should be initialized"); 4137 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4138 sllx(r, LogMinObjAlignmentInBytes, r); 4139 if (Universe::narrow_oop_base() != NULL) 4140 add(r, G6_heapbase, r); 4141 } 4142 4143 void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { 4144 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4145 // pd_code_size_limit. 4146 // Also do not verify_oop as this is called by verify_oop. 4147 assert (UseCompressedOops, "must be compressed"); 4148 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 4149 sllx(src, LogMinObjAlignmentInBytes, dst); 4150 if (Universe::narrow_oop_base() != NULL) 4151 add(dst, G6_heapbase, dst); 4152 } 4153 4154 void MacroAssembler::encode_klass_not_null(Register r) { 4155 assert (UseCompressedClassPointers, "must be compressed"); 4156 if (Universe::narrow_klass_base() != NULL) { 4157 assert(r != G6_heapbase, "bad register choice"); 4158 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); 4159 sub(r, G6_heapbase, r); 4160 if (Universe::narrow_klass_shift() != 0) { 4161 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 4162 srlx(r, LogKlassAlignmentInBytes, r); 4163 } 4164 reinit_heapbase(); 4165 } else { 4166 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong"); 4167 srlx(r, Universe::narrow_klass_shift(), r); 4168 } 4169 } 4170 4171 void MacroAssembler::encode_klass_not_null(Register src, Register dst) { 4172 if (src == dst) { 4173 encode_klass_not_null(src); 4174 } else { 4175 assert (UseCompressedClassPointers, "must be compressed"); 4176 if (Universe::narrow_klass_base() != NULL) { 4177 set((intptr_t)Universe::narrow_klass_base(), dst); 4178 sub(src, dst, dst); 4179 if (Universe::narrow_klass_shift() != 0) { 4180 srlx(dst, LogKlassAlignmentInBytes, dst); 4181 } 4182 } else { 4183 // shift src into dst 4184 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong"); 4185 srlx(src, Universe::narrow_klass_shift(), dst); 4186 } 4187 } 4188 } 4189 4190 // Function instr_size_for_decode_klass_not_null() counts the instructions 4191 // generated by decode_klass_not_null() and reinit_heapbase(). Hence, if 4192 // the instructions they generate change, then this method needs to be updated. 4193 int MacroAssembler::instr_size_for_decode_klass_not_null() { 4194 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 4195 int num_instrs = 1; // shift src,dst or add 4196 if (Universe::narrow_klass_base() != NULL) { 4197 // set + add + set 4198 num_instrs += insts_for_internal_set((intptr_t)Universe::narrow_klass_base()) + 4199 insts_for_internal_set((intptr_t)Universe::narrow_ptrs_base()); 4200 if (Universe::narrow_klass_shift() != 0) { 4201 num_instrs += 1; // sllx 4202 } 4203 } 4204 return num_instrs * BytesPerInstWord; 4205 } 4206 4207 // !!! If the instructions that get generated here change then function 4208 // instr_size_for_decode_klass_not_null() needs to get updated. 4209 void MacroAssembler::decode_klass_not_null(Register r) { 4210 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4211 // pd_code_size_limit. 4212 assert (UseCompressedClassPointers, "must be compressed"); 4213 if (Universe::narrow_klass_base() != NULL) { 4214 assert(r != G6_heapbase, "bad register choice"); 4215 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); 4216 if (Universe::narrow_klass_shift() != 0) 4217 sllx(r, LogKlassAlignmentInBytes, r); 4218 add(r, G6_heapbase, r); 4219 reinit_heapbase(); 4220 } else { 4221 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong"); 4222 sllx(r, Universe::narrow_klass_shift(), r); 4223 } 4224 } 4225 4226 void MacroAssembler::decode_klass_not_null(Register src, Register dst) { 4227 if (src == dst) { 4228 decode_klass_not_null(src); 4229 } else { 4230 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4231 // pd_code_size_limit. 4232 assert (UseCompressedClassPointers, "must be compressed"); 4233 if (Universe::narrow_klass_base() != NULL) { 4234 if (Universe::narrow_klass_shift() != 0) { 4235 assert((src != G6_heapbase) && (dst != G6_heapbase), "bad register choice"); 4236 set((intptr_t)Universe::narrow_klass_base(), G6_heapbase); 4237 sllx(src, LogKlassAlignmentInBytes, dst); 4238 add(dst, G6_heapbase, dst); 4239 reinit_heapbase(); 4240 } else { 4241 set((intptr_t)Universe::narrow_klass_base(), dst); 4242 add(src, dst, dst); 4243 } 4244 } else { 4245 // shift/mov src into dst. 4246 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift() || Universe::narrow_klass_shift() == 0, "decode alg wrong"); 4247 sllx(src, Universe::narrow_klass_shift(), dst); 4248 } 4249 } 4250 } 4251 4252 void MacroAssembler::reinit_heapbase() { 4253 if (UseCompressedOops || UseCompressedClassPointers) { 4254 if (Universe::heap() != NULL) { 4255 set((intptr_t)Universe::narrow_ptrs_base(), G6_heapbase); 4256 } else { 4257 AddressLiteral base(Universe::narrow_ptrs_base_addr()); 4258 load_ptr_contents(base, G6_heapbase); 4259 } 4260 } 4261 } 4262 4263 #ifdef COMPILER2 4264 4265 // Compress char[] to byte[] by compressing 16 bytes at once. Return 0 on failure. 4266 void MacroAssembler::string_compress_16(Register src, Register dst, Register cnt, Register result, 4267 Register tmp1, Register tmp2, Register tmp3, Register tmp4, 4268 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, Label& Ldone) { 4269 Label Lloop, Lslow; 4270 assert(UseVIS >= 3, "VIS3 is required"); 4271 assert_different_registers(src, dst, cnt, tmp1, tmp2, tmp3, tmp4, result); 4272 assert_different_registers(ftmp1, ftmp2, ftmp3); 4273 4274 // Check if cnt >= 8 (= 16 bytes) 4275 cmp(cnt, 8); 4276 br(Assembler::less, false, Assembler::pn, Lslow); 4277 delayed()->mov(cnt, result); // copy count 4278 4279 // Check for 8-byte alignment of src and dst 4280 or3(src, dst, tmp1); 4281 andcc(tmp1, 7, G0); 4282 br(Assembler::notZero, false, Assembler::pn, Lslow); 4283 delayed()->nop(); 4284 4285 // Set mask for bshuffle instruction 4286 Register mask = tmp4; 4287 set(0x13579bdf, mask); 4288 bmask(mask, G0, G0); 4289 4290 // Set mask to 0xff00 ff00 ff00 ff00 to check for non-latin1 characters 4291 Assembler::sethi(0xff00fc00, mask); // mask = 0x0000 0000 ff00 fc00 4292 add(mask, 0x300, mask); // mask = 0x0000 0000 ff00 ff00 4293 sllx(mask, 32, tmp1); // tmp1 = 0xff00 ff00 0000 0000 4294 or3(mask, tmp1, mask); // mask = 0xff00 ff00 ff00 ff00 4295 4296 // Load first 8 bytes 4297 ldx(src, 0, tmp1); 4298 4299 bind(Lloop); 4300 // Load next 8 bytes 4301 ldx(src, 8, tmp2); 4302 4303 // Check for non-latin1 character by testing if the most significant byte of a char is set. 4304 // Although we have to move the data between integer and floating point registers, this is 4305 // still faster than the corresponding VIS instructions (ford/fand/fcmpd). 4306 or3(tmp1, tmp2, tmp3); 4307 btst(tmp3, mask); 4308 // annul zeroing if branch is not taken to preserve original count 4309 brx(Assembler::notZero, true, Assembler::pn, Ldone); 4310 delayed()->mov(G0, result); // 0 - failed 4311 4312 // Move bytes into float register 4313 movxtod(tmp1, ftmp1); 4314 movxtod(tmp2, ftmp2); 4315 4316 // Compress by copying one byte per char from ftmp1 and ftmp2 to ftmp3 4317 bshuffle(ftmp1, ftmp2, ftmp3); 4318 stf(FloatRegisterImpl::D, ftmp3, dst, 0); 4319 4320 // Increment addresses and decrement count 4321 inc(src, 16); 4322 inc(dst, 8); 4323 dec(cnt, 8); 4324 4325 cmp(cnt, 8); 4326 // annul LDX if branch is not taken to prevent access past end of string 4327 br(Assembler::greaterEqual, true, Assembler::pt, Lloop); 4328 delayed()->ldx(src, 0, tmp1); 4329 4330 // Fallback to slow version 4331 bind(Lslow); 4332 } 4333 4334 // Compress char[] to byte[]. Return 0 on failure. 4335 void MacroAssembler::string_compress(Register src, Register dst, Register cnt, Register result, Register tmp, Label& Ldone) { 4336 Label Lloop; 4337 assert_different_registers(src, dst, cnt, tmp, result); 4338 4339 lduh(src, 0, tmp); 4340 4341 bind(Lloop); 4342 inc(src, sizeof(jchar)); 4343 cmp(tmp, 0xff); 4344 // annul zeroing if branch is not taken to preserve original count 4345 br(Assembler::greater, true, Assembler::pn, Ldone); // don't check xcc 4346 delayed()->mov(G0, result); // 0 - failed 4347 deccc(cnt); 4348 stb(tmp, dst, 0); 4349 inc(dst); 4350 // annul LDUH if branch is not taken to prevent access past end of string 4351 br(Assembler::notZero, true, Assembler::pt, Lloop); 4352 delayed()->lduh(src, 0, tmp); // hoisted 4353 } 4354 4355 // Inflate byte[] to char[] by inflating 16 bytes at once. 4356 void MacroAssembler::string_inflate_16(Register src, Register dst, Register cnt, Register tmp, 4357 FloatRegister ftmp1, FloatRegister ftmp2, FloatRegister ftmp3, FloatRegister ftmp4, Label& Ldone) { 4358 Label Lloop, Lslow; 4359 assert(UseVIS >= 3, "VIS3 is required"); 4360 assert_different_registers(src, dst, cnt, tmp); 4361 assert_different_registers(ftmp1, ftmp2, ftmp3, ftmp4); 4362 4363 // Check if cnt >= 8 (= 16 bytes) 4364 cmp(cnt, 8); 4365 br(Assembler::less, false, Assembler::pn, Lslow); 4366 delayed()->nop(); 4367 4368 // Check for 8-byte alignment of src and dst 4369 or3(src, dst, tmp); 4370 andcc(tmp, 7, G0); 4371 br(Assembler::notZero, false, Assembler::pn, Lslow); 4372 // Initialize float register to zero 4373 FloatRegister zerof = ftmp4; 4374 delayed()->fzero(FloatRegisterImpl::D, zerof); 4375 4376 // Load first 8 bytes 4377 ldf(FloatRegisterImpl::D, src, 0, ftmp1); 4378 4379 bind(Lloop); 4380 inc(src, 8); 4381 dec(cnt, 8); 4382 4383 // Inflate the string by interleaving each byte from the source array 4384 // with a zero byte and storing the result in the destination array. 4385 fpmerge(zerof, ftmp1->successor(), ftmp2); 4386 stf(FloatRegisterImpl::D, ftmp2, dst, 8); 4387 fpmerge(zerof, ftmp1, ftmp3); 4388 stf(FloatRegisterImpl::D, ftmp3, dst, 0); 4389 4390 inc(dst, 16); 4391 4392 cmp(cnt, 8); 4393 // annul LDX if branch is not taken to prevent access past end of string 4394 br(Assembler::greaterEqual, true, Assembler::pt, Lloop); 4395 delayed()->ldf(FloatRegisterImpl::D, src, 0, ftmp1); 4396 4397 // Fallback to slow version 4398 bind(Lslow); 4399 } 4400 4401 // Inflate byte[] to char[]. 4402 void MacroAssembler::string_inflate(Register src, Register dst, Register cnt, Register tmp, Label& Ldone) { 4403 Label Loop; 4404 assert_different_registers(src, dst, cnt, tmp); 4405 4406 ldub(src, 0, tmp); 4407 bind(Loop); 4408 inc(src); 4409 deccc(cnt); 4410 sth(tmp, dst, 0); 4411 inc(dst, sizeof(jchar)); 4412 // annul LDUB if branch is not taken to prevent access past end of string 4413 br(Assembler::notZero, true, Assembler::pt, Loop); 4414 delayed()->ldub(src, 0, tmp); // hoisted 4415 } 4416 4417 void MacroAssembler::string_compare(Register str1, Register str2, 4418 Register cnt1, Register cnt2, 4419 Register tmp1, Register tmp2, 4420 Register result, int ae) { 4421 Label Ldone, Lloop; 4422 assert_different_registers(str1, str2, cnt1, cnt2, tmp1, result); 4423 int stride1, stride2; 4424 4425 // Note: Making use of the fact that compareTo(a, b) == -compareTo(b, a) 4426 // we interchange str1 and str2 in the UL case and negate the result. 4427 // Like this, str1 is always latin1 encoded, expect for the UU case. 4428 4429 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 4430 srl(cnt2, 1, cnt2); 4431 } 4432 4433 // See if the lengths are different, and calculate min in cnt1. 4434 // Save diff in case we need it for a tie-breaker. 4435 Label Lskip; 4436 Register diff = tmp1; 4437 subcc(cnt1, cnt2, diff); 4438 br(Assembler::greater, true, Assembler::pt, Lskip); 4439 // cnt2 is shorter, so use its count: 4440 delayed()->mov(cnt2, cnt1); 4441 bind(Lskip); 4442 4443 // Rename registers 4444 Register limit1 = cnt1; 4445 Register limit2 = limit1; 4446 Register chr1 = result; 4447 Register chr2 = cnt2; 4448 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 4449 // We need an additional register to keep track of two limits 4450 assert_different_registers(str1, str2, cnt1, cnt2, tmp1, tmp2, result); 4451 limit2 = tmp2; 4452 } 4453 4454 // Is the minimum length zero? 4455 cmp(limit1, (int)0); // use cast to resolve overloading ambiguity 4456 br(Assembler::equal, true, Assembler::pn, Ldone); 4457 // result is difference in lengths 4458 if (ae == StrIntrinsicNode::UU) { 4459 delayed()->sra(diff, 1, result); // Divide by 2 to get number of chars 4460 } else { 4461 delayed()->mov(diff, result); 4462 } 4463 4464 // Load first characters 4465 if (ae == StrIntrinsicNode::LL) { 4466 stride1 = stride2 = sizeof(jbyte); 4467 ldub(str1, 0, chr1); 4468 ldub(str2, 0, chr2); 4469 } else if (ae == StrIntrinsicNode::UU) { 4470 stride1 = stride2 = sizeof(jchar); 4471 lduh(str1, 0, chr1); 4472 lduh(str2, 0, chr2); 4473 } else { 4474 stride1 = sizeof(jbyte); 4475 stride2 = sizeof(jchar); 4476 ldub(str1, 0, chr1); 4477 lduh(str2, 0, chr2); 4478 } 4479 4480 // Compare first characters 4481 subcc(chr1, chr2, chr1); 4482 br(Assembler::notZero, false, Assembler::pt, Ldone); 4483 assert(chr1 == result, "result must be pre-placed"); 4484 delayed()->nop(); 4485 4486 // Check if the strings start at same location 4487 cmp(str1, str2); 4488 brx(Assembler::equal, true, Assembler::pn, Ldone); 4489 delayed()->mov(G0, result); // result is zero 4490 4491 // We have no guarantee that on 64 bit the higher half of limit is 0 4492 signx(limit1); 4493 4494 // Get limit 4495 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 4496 sll(limit1, 1, limit2); 4497 subcc(limit2, stride2, chr2); 4498 } 4499 subcc(limit1, stride1, chr1); 4500 br(Assembler::zero, true, Assembler::pn, Ldone); 4501 // result is difference in lengths 4502 if (ae == StrIntrinsicNode::UU) { 4503 delayed()->sra(diff, 1, result); // Divide by 2 to get number of chars 4504 } else { 4505 delayed()->mov(diff, result); 4506 } 4507 4508 // Shift str1 and str2 to the end of the arrays, negate limit 4509 add(str1, limit1, str1); 4510 add(str2, limit2, str2); 4511 neg(chr1, limit1); // limit1 = -(limit1-stride1) 4512 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 4513 neg(chr2, limit2); // limit2 = -(limit2-stride2) 4514 } 4515 4516 // Compare the rest of the characters 4517 if (ae == StrIntrinsicNode::UU) { 4518 lduh(str1, limit1, chr1); 4519 } else { 4520 ldub(str1, limit1, chr1); 4521 } 4522 4523 bind(Lloop); 4524 if (ae == StrIntrinsicNode::LL) { 4525 ldub(str2, limit2, chr2); 4526 } else { 4527 lduh(str2, limit2, chr2); 4528 } 4529 4530 subcc(chr1, chr2, chr1); 4531 br(Assembler::notZero, false, Assembler::pt, Ldone); 4532 assert(chr1 == result, "result must be pre-placed"); 4533 delayed()->inccc(limit1, stride1); 4534 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 4535 inccc(limit2, stride2); 4536 } 4537 4538 // annul LDUB if branch is not taken to prevent access past end of string 4539 br(Assembler::notZero, true, Assembler::pt, Lloop); 4540 if (ae == StrIntrinsicNode::UU) { 4541 delayed()->lduh(str1, limit2, chr1); 4542 } else { 4543 delayed()->ldub(str1, limit1, chr1); 4544 } 4545 4546 // If strings are equal up to min length, return the length difference. 4547 if (ae == StrIntrinsicNode::UU) { 4548 // Divide by 2 to get number of chars 4549 sra(diff, 1, result); 4550 } else { 4551 mov(diff, result); 4552 } 4553 4554 // Otherwise, return the difference between the first mismatched chars. 4555 bind(Ldone); 4556 if(ae == StrIntrinsicNode::UL) { 4557 // Negate result (see note above) 4558 neg(result); 4559 } 4560 } 4561 4562 void MacroAssembler::array_equals(bool is_array_equ, Register ary1, Register ary2, 4563 Register limit, Register tmp, Register result, bool is_byte) { 4564 Label Ldone, Lvector, Lloop; 4565 assert_different_registers(ary1, ary2, limit, tmp, result); 4566 4567 int length_offset = arrayOopDesc::length_offset_in_bytes(); 4568 int base_offset = arrayOopDesc::base_offset_in_bytes(is_byte ? T_BYTE : T_CHAR); 4569 4570 if (is_array_equ) { 4571 // return true if the same array 4572 cmp(ary1, ary2); 4573 brx(Assembler::equal, true, Assembler::pn, Ldone); 4574 delayed()->add(G0, 1, result); // equal 4575 4576 br_null(ary1, true, Assembler::pn, Ldone); 4577 delayed()->mov(G0, result); // not equal 4578 4579 br_null(ary2, true, Assembler::pn, Ldone); 4580 delayed()->mov(G0, result); // not equal 4581 4582 // load the lengths of arrays 4583 ld(Address(ary1, length_offset), limit); 4584 ld(Address(ary2, length_offset), tmp); 4585 4586 // return false if the two arrays are not equal length 4587 cmp(limit, tmp); 4588 br(Assembler::notEqual, true, Assembler::pn, Ldone); 4589 delayed()->mov(G0, result); // not equal 4590 } 4591 4592 cmp_zero_and_br(Assembler::zero, limit, Ldone, true, Assembler::pn); 4593 delayed()->add(G0, 1, result); // zero-length arrays are equal 4594 4595 if (is_array_equ) { 4596 // load array addresses 4597 add(ary1, base_offset, ary1); 4598 add(ary2, base_offset, ary2); 4599 } else { 4600 // We have no guarantee that on 64 bit the higher half of limit is 0 4601 signx(limit); 4602 } 4603 4604 if (is_byte) { 4605 Label Lskip; 4606 // check for trailing byte 4607 andcc(limit, 0x1, tmp); 4608 br(Assembler::zero, false, Assembler::pt, Lskip); 4609 delayed()->nop(); 4610 4611 // compare the trailing byte 4612 sub(limit, sizeof(jbyte), limit); 4613 ldub(ary1, limit, result); 4614 ldub(ary2, limit, tmp); 4615 cmp(result, tmp); 4616 br(Assembler::notEqual, true, Assembler::pt, Ldone); 4617 delayed()->mov(G0, result); // not equal 4618 4619 // only one byte? 4620 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); 4621 delayed()->add(G0, 1, result); // zero-length arrays are equal 4622 bind(Lskip); 4623 } else if (is_array_equ) { 4624 // set byte count 4625 sll(limit, exact_log2(sizeof(jchar)), limit); 4626 } 4627 4628 // check for trailing character 4629 andcc(limit, 0x2, tmp); 4630 br(Assembler::zero, false, Assembler::pt, Lvector); 4631 delayed()->nop(); 4632 4633 // compare the trailing char 4634 sub(limit, sizeof(jchar), limit); 4635 lduh(ary1, limit, result); 4636 lduh(ary2, limit, tmp); 4637 cmp(result, tmp); 4638 br(Assembler::notEqual, true, Assembler::pt, Ldone); 4639 delayed()->mov(G0, result); // not equal 4640 4641 // only one char? 4642 cmp_zero_and_br(zero, limit, Ldone, true, Assembler::pn); 4643 delayed()->add(G0, 1, result); // zero-length arrays are equal 4644 4645 // word by word compare, dont't need alignment check 4646 bind(Lvector); 4647 // Shift ary1 and ary2 to the end of the arrays, negate limit 4648 add(ary1, limit, ary1); 4649 add(ary2, limit, ary2); 4650 neg(limit, limit); 4651 4652 lduw(ary1, limit, result); 4653 bind(Lloop); 4654 lduw(ary2, limit, tmp); 4655 cmp(result, tmp); 4656 br(Assembler::notEqual, true, Assembler::pt, Ldone); 4657 delayed()->mov(G0, result); // not equal 4658 inccc(limit, 2*sizeof(jchar)); 4659 // annul LDUW if branch is not taken to prevent access past end of array 4660 br(Assembler::notZero, true, Assembler::pt, Lloop); 4661 delayed()->lduw(ary1, limit, result); // hoisted 4662 4663 add(G0, 1, result); // equals 4664 bind(Ldone); 4665 } 4666 4667 #endif 4668 4669 // Use BIS for zeroing (count is in bytes). 4670 void MacroAssembler::bis_zeroing(Register to, Register count, Register temp, Label& Ldone) { 4671 assert(UseBlockZeroing && VM_Version::has_block_zeroing(), "only works with BIS zeroing"); 4672 Register end = count; 4673 int cache_line_size = VM_Version::prefetch_data_size(); 4674 // Minimum count when BIS zeroing can be used since 4675 // it needs membar which is expensive. 4676 int block_zero_size = MAX2(cache_line_size*3, (int)BlockZeroingLowLimit); 4677 4678 Label small_loop; 4679 // Check if count is negative (dead code) or zero. 4680 // Note, count uses 64bit in 64 bit VM. 4681 cmp_and_brx_short(count, 0, Assembler::lessEqual, Assembler::pn, Ldone); 4682 4683 // Use BIS zeroing only for big arrays since it requires membar. 4684 if (Assembler::is_simm13(block_zero_size)) { // < 4096 4685 cmp(count, block_zero_size); 4686 } else { 4687 set(block_zero_size, temp); 4688 cmp(count, temp); 4689 } 4690 br(Assembler::lessUnsigned, false, Assembler::pt, small_loop); 4691 delayed()->add(to, count, end); 4692 4693 // Note: size is >= three (32 bytes) cache lines. 4694 4695 // Clean the beginning of space up to next cache line. 4696 for (int offs = 0; offs < cache_line_size; offs += 8) { 4697 stx(G0, to, offs); 4698 } 4699 4700 // align to next cache line 4701 add(to, cache_line_size, to); 4702 and3(to, -cache_line_size, to); 4703 4704 // Note: size left >= two (32 bytes) cache lines. 4705 4706 // BIS should not be used to zero tail (64 bytes) 4707 // to avoid zeroing a header of the following object. 4708 sub(end, (cache_line_size*2)-8, end); 4709 4710 Label bis_loop; 4711 bind(bis_loop); 4712 stxa(G0, to, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 4713 add(to, cache_line_size, to); 4714 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, bis_loop); 4715 4716 // BIS needs membar. 4717 membar(Assembler::StoreLoad); 4718 4719 add(end, (cache_line_size*2)-8, end); // restore end 4720 cmp_and_brx_short(to, end, Assembler::greaterEqualUnsigned, Assembler::pn, Ldone); 4721 4722 // Clean the tail. 4723 bind(small_loop); 4724 stx(G0, to, 0); 4725 add(to, 8, to); 4726 cmp_and_brx_short(to, end, Assembler::lessUnsigned, Assembler::pt, small_loop); 4727 nop(); // Separate short branches 4728 } 4729 4730 /** 4731 * Update CRC-32[C] with a byte value according to constants in table 4732 * 4733 * @param [in,out]crc Register containing the crc. 4734 * @param [in]val Register containing the byte to fold into the CRC. 4735 * @param [in]table Register containing the table of crc constants. 4736 * 4737 * uint32_t crc; 4738 * val = crc_table[(val ^ crc) & 0xFF]; 4739 * crc = val ^ (crc >> 8); 4740 */ 4741 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 4742 xor3(val, crc, val); 4743 and3(val, 0xFF, val); 4744 sllx(val, 2, val); 4745 lduw(table, val, val); 4746 srlx(crc, 8, crc); 4747 xor3(val, crc, crc); 4748 } 4749 4750 // Reverse byte order of lower 32 bits, assuming upper 32 bits all zeros 4751 void MacroAssembler::reverse_bytes_32(Register src, Register dst, Register tmp) { 4752 srlx(src, 24, dst); 4753 4754 sllx(src, 32+8, tmp); 4755 srlx(tmp, 32+24, tmp); 4756 sllx(tmp, 8, tmp); 4757 or3(dst, tmp, dst); 4758 4759 sllx(src, 32+16, tmp); 4760 srlx(tmp, 32+24, tmp); 4761 sllx(tmp, 16, tmp); 4762 or3(dst, tmp, dst); 4763 4764 sllx(src, 32+24, tmp); 4765 srlx(tmp, 32, tmp); 4766 or3(dst, tmp, dst); 4767 } 4768 4769 void MacroAssembler::movitof_revbytes(Register src, FloatRegister dst, Register tmp1, Register tmp2) { 4770 reverse_bytes_32(src, tmp1, tmp2); 4771 movxtod(tmp1, dst); 4772 } 4773 4774 void MacroAssembler::movftoi_revbytes(FloatRegister src, Register dst, Register tmp1, Register tmp2) { 4775 movdtox(src, tmp1); 4776 reverse_bytes_32(tmp1, dst, tmp2); 4777 } 4778 4779 void MacroAssembler::fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register buf, int offset) { 4780 xmulx(xcrc_hi, xK_hi, xtmp_lo); 4781 xmulxhi(xcrc_hi, xK_hi, xtmp_hi); 4782 xmulxhi(xcrc_lo, xK_lo, xcrc_hi); 4783 xmulx(xcrc_lo, xK_lo, xcrc_lo); 4784 xor3(xcrc_lo, xtmp_lo, xcrc_lo); 4785 xor3(xcrc_hi, xtmp_hi, xcrc_hi); 4786 ldxl(buf, G0, xtmp_lo); 4787 inc(buf, 8); 4788 ldxl(buf, G0, xtmp_hi); 4789 inc(buf, 8); 4790 xor3(xcrc_lo, xtmp_lo, xcrc_lo); 4791 xor3(xcrc_hi, xtmp_hi, xcrc_hi); 4792 } 4793 4794 void MacroAssembler::fold_128bit_crc32(Register xcrc_hi, Register xcrc_lo, Register xK_hi, Register xK_lo, Register xtmp_hi, Register xtmp_lo, Register xbuf_hi, Register xbuf_lo) { 4795 mov(xcrc_lo, xtmp_lo); 4796 mov(xcrc_hi, xtmp_hi); 4797 xmulx(xtmp_hi, xK_hi, xtmp_lo); 4798 xmulxhi(xtmp_hi, xK_hi, xtmp_hi); 4799 xmulxhi(xcrc_lo, xK_lo, xcrc_hi); 4800 xmulx(xcrc_lo, xK_lo, xcrc_lo); 4801 xor3(xcrc_lo, xbuf_lo, xcrc_lo); 4802 xor3(xcrc_hi, xbuf_hi, xcrc_hi); 4803 xor3(xcrc_lo, xtmp_lo, xcrc_lo); 4804 xor3(xcrc_hi, xtmp_hi, xcrc_hi); 4805 } 4806 4807 void MacroAssembler::fold_8bit_crc32(Register xcrc, Register table, Register xtmp, Register tmp) { 4808 and3(xcrc, 0xFF, tmp); 4809 sllx(tmp, 2, tmp); 4810 lduw(table, tmp, xtmp); 4811 srlx(xcrc, 8, xcrc); 4812 xor3(xtmp, xcrc, xcrc); 4813 } 4814 4815 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 4816 and3(crc, 0xFF, tmp); 4817 srlx(crc, 8, crc); 4818 sllx(tmp, 2, tmp); 4819 lduw(table, tmp, tmp); 4820 xor3(tmp, crc, crc); 4821 } 4822 4823 #define CRC32_TMP_REG_NUM 18 4824 4825 #define CRC32_CONST_64 0x163cd6124 4826 #define CRC32_CONST_96 0x0ccaa009e 4827 #define CRC32_CONST_160 0x1751997d0 4828 #define CRC32_CONST_480 0x1c6e41596 4829 #define CRC32_CONST_544 0x154442bd4 4830 4831 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table) { 4832 4833 Label L_cleanup_loop, L_cleanup_check, L_align_loop, L_align_check; 4834 Label L_main_loop_prologue; 4835 Label L_fold_512b, L_fold_512b_loop, L_fold_128b; 4836 Label L_fold_tail, L_fold_tail_loop; 4837 Label L_8byte_fold_loop, L_8byte_fold_check; 4838 4839 const Register tmp[CRC32_TMP_REG_NUM] = {L0, L1, L2, L3, L4, L5, L6, G1, I0, I1, I2, I3, I4, I5, I7, O4, O5, G3}; 4840 4841 Register const_64 = tmp[CRC32_TMP_REG_NUM-1]; 4842 Register const_96 = tmp[CRC32_TMP_REG_NUM-1]; 4843 Register const_160 = tmp[CRC32_TMP_REG_NUM-2]; 4844 Register const_480 = tmp[CRC32_TMP_REG_NUM-1]; 4845 Register const_544 = tmp[CRC32_TMP_REG_NUM-2]; 4846 4847 set(ExternalAddress(StubRoutines::crc_table_addr()), table); 4848 4849 not1(crc); // ~c 4850 clruwu(crc); // clear upper 32 bits of crc 4851 4852 // Check if below cutoff, proceed directly to cleanup code 4853 mov(31, G4); 4854 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_cleanup_check); 4855 4856 // Align buffer to 8 byte boundry 4857 mov(8, O5); 4858 and3(buf, 0x7, O4); 4859 sub(O5, O4, O5); 4860 and3(O5, 0x7, O5); 4861 sub(len, O5, len); 4862 ba(L_align_check); 4863 delayed()->nop(); 4864 4865 // Alignment loop, table look up method for up to 7 bytes 4866 bind(L_align_loop); 4867 ldub(buf, 0, O4); 4868 inc(buf); 4869 dec(O5); 4870 xor3(O4, crc, O4); 4871 and3(O4, 0xFF, O4); 4872 sllx(O4, 2, O4); 4873 lduw(table, O4, O4); 4874 srlx(crc, 8, crc); 4875 xor3(O4, crc, crc); 4876 bind(L_align_check); 4877 nop(); 4878 cmp_and_br_short(O5, 0, Assembler::notEqual, Assembler::pt, L_align_loop); 4879 4880 // Aligned on 64-bit (8-byte) boundry at this point 4881 // Check if still above cutoff (31-bytes) 4882 mov(31, G4); 4883 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_cleanup_check); 4884 // At least 32 bytes left to process 4885 4886 // Free up registers by storing them to FP registers 4887 for (int i = 0; i < CRC32_TMP_REG_NUM; i++) { 4888 movxtod(tmp[i], as_FloatRegister(2*i)); 4889 } 4890 4891 // Determine which loop to enter 4892 // Shared prologue 4893 ldxl(buf, G0, tmp[0]); 4894 inc(buf, 8); 4895 ldxl(buf, G0, tmp[1]); 4896 inc(buf, 8); 4897 xor3(tmp[0], crc, tmp[0]); // Fold CRC into first few bytes 4898 and3(crc, 0, crc); // Clear out the crc register 4899 // Main loop needs 128-bytes at least 4900 mov(128, G4); 4901 mov(64, tmp[2]); 4902 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_main_loop_prologue); 4903 // Less than 64 bytes 4904 nop(); 4905 cmp_and_br_short(len, tmp[2], Assembler::lessUnsigned, Assembler::pt, L_fold_tail); 4906 // Between 64 and 127 bytes 4907 set64(CRC32_CONST_96, const_96, tmp[8]); 4908 set64(CRC32_CONST_160, const_160, tmp[9]); 4909 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[2], tmp[3], buf, 0); 4910 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[4], tmp[5], buf, 16); 4911 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[6], tmp[7], buf, 32); 4912 dec(len, 48); 4913 ba(L_fold_tail); 4914 delayed()->nop(); 4915 4916 bind(L_main_loop_prologue); 4917 for (int i = 2; i < 8; i++) { 4918 ldxl(buf, G0, tmp[i]); 4919 inc(buf, 8); 4920 } 4921 4922 // Fold total 512 bits of polynomial on each iteration, 4923 // 128 bits per each of 4 parallel streams 4924 set64(CRC32_CONST_480, const_480, tmp[8]); 4925 set64(CRC32_CONST_544, const_544, tmp[9]); 4926 4927 mov(128, G4); 4928 bind(L_fold_512b_loop); 4929 fold_128bit_crc32(tmp[1], tmp[0], const_480, const_544, tmp[9], tmp[8], buf, 0); 4930 fold_128bit_crc32(tmp[3], tmp[2], const_480, const_544, tmp[11], tmp[10], buf, 16); 4931 fold_128bit_crc32(tmp[5], tmp[4], const_480, const_544, tmp[13], tmp[12], buf, 32); 4932 fold_128bit_crc32(tmp[7], tmp[6], const_480, const_544, tmp[15], tmp[14], buf, 64); 4933 dec(len, 64); 4934 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_fold_512b_loop); 4935 4936 // Fold 512 bits to 128 bits 4937 bind(L_fold_512b); 4938 set64(CRC32_CONST_96, const_96, tmp[8]); 4939 set64(CRC32_CONST_160, const_160, tmp[9]); 4940 4941 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[3], tmp[2]); 4942 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[5], tmp[4]); 4943 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[8], tmp[9], tmp[7], tmp[6]); 4944 dec(len, 48); 4945 4946 // Fold the rest of 128 bits data chunks 4947 bind(L_fold_tail); 4948 mov(32, G4); 4949 cmp_and_br_short(len, G4, Assembler::lessEqualUnsigned, Assembler::pt, L_fold_128b); 4950 4951 set64(CRC32_CONST_96, const_96, tmp[8]); 4952 set64(CRC32_CONST_160, const_160, tmp[9]); 4953 4954 bind(L_fold_tail_loop); 4955 fold_128bit_crc32(tmp[1], tmp[0], const_96, const_160, tmp[2], tmp[3], buf, 0); 4956 sub(len, 16, len); 4957 cmp_and_br_short(len, G4, Assembler::greaterEqualUnsigned, Assembler::pt, L_fold_tail_loop); 4958 4959 // Fold the 128 bits in tmps 0 - 1 into tmp 1 4960 bind(L_fold_128b); 4961 4962 set64(CRC32_CONST_64, const_64, tmp[4]); 4963 4964 xmulx(const_64, tmp[0], tmp[2]); 4965 xmulxhi(const_64, tmp[0], tmp[3]); 4966 4967 srl(tmp[2], G0, tmp[4]); 4968 xmulx(const_64, tmp[4], tmp[4]); 4969 4970 srlx(tmp[2], 32, tmp[2]); 4971 sllx(tmp[3], 32, tmp[3]); 4972 or3(tmp[2], tmp[3], tmp[2]); 4973 4974 xor3(tmp[4], tmp[1], tmp[4]); 4975 xor3(tmp[4], tmp[2], tmp[1]); 4976 dec(len, 8); 4977 4978 // Use table lookup for the 8 bytes left in tmp[1] 4979 dec(len, 8); 4980 4981 // 8 8-bit folds to compute 32-bit CRC. 4982 for (int j = 0; j < 4; j++) { 4983 fold_8bit_crc32(tmp[1], table, tmp[2], tmp[3]); 4984 } 4985 srl(tmp[1], G0, crc); // move 32 bits to general register 4986 for (int j = 0; j < 4; j++) { 4987 fold_8bit_crc32(crc, table, tmp[3]); 4988 } 4989 4990 bind(L_8byte_fold_check); 4991 4992 // Restore int registers saved in FP registers 4993 for (int i = 0; i < CRC32_TMP_REG_NUM; i++) { 4994 movdtox(as_FloatRegister(2*i), tmp[i]); 4995 } 4996 4997 ba(L_cleanup_check); 4998 delayed()->nop(); 4999 5000 // Table look-up method for the remaining few bytes 5001 bind(L_cleanup_loop); 5002 ldub(buf, 0, O4); 5003 inc(buf); 5004 dec(len); 5005 xor3(O4, crc, O4); 5006 and3(O4, 0xFF, O4); 5007 sllx(O4, 2, O4); 5008 lduw(table, O4, O4); 5009 srlx(crc, 8, crc); 5010 xor3(O4, crc, crc); 5011 bind(L_cleanup_check); 5012 nop(); 5013 cmp_and_br_short(len, 0, Assembler::greaterUnsigned, Assembler::pt, L_cleanup_loop); 5014 5015 not1(crc); 5016 } 5017