1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp,
756 bool clear_pc) {
757 // we must set sp to zero to clear frame
758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
759 // must clear fp, so that compiled frames are not confused; it is
760 // possible that we need it only for debugging
761 if (clear_fp) {
762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
763 }
764
765 if (clear_pc) {
766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
767 }
768 }
769
770 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
771 Register last_java_fp,
772 address last_java_pc) {
773 // determine last_java_sp register
774 if (!last_java_sp->is_valid()) {
775 last_java_sp = rsp;
776 }
777
778 // last_java_fp is optional
779 if (last_java_fp->is_valid()) {
780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
781 last_java_fp);
782 }
783
784 // last_java_pc is optional
785 if (last_java_pc != NULL) {
786 Address java_pc(r15_thread,
787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
788 lea(rscratch1, InternalAddress(last_java_pc));
789 movptr(java_pc, rscratch1);
790 }
791
792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
793 }
794
795 static void pass_arg0(MacroAssembler* masm, Register arg) {
796 if (c_rarg0 != arg ) {
797 masm->mov(c_rarg0, arg);
798 }
799 }
800
801 static void pass_arg1(MacroAssembler* masm, Register arg) {
802 if (c_rarg1 != arg ) {
803 masm->mov(c_rarg1, arg);
804 }
805 }
806
807 static void pass_arg2(MacroAssembler* masm, Register arg) {
808 if (c_rarg2 != arg ) {
809 masm->mov(c_rarg2, arg);
810 }
811 }
812
813 static void pass_arg3(MacroAssembler* masm, Register arg) {
814 if (c_rarg3 != arg ) {
815 masm->mov(c_rarg3, arg);
816 }
817 }
818
819 void MacroAssembler::stop(const char* msg) {
820 address rip = pc();
821 pusha(); // get regs on stack
822 lea(c_rarg0, ExternalAddress((address) msg));
823 lea(c_rarg1, InternalAddress(rip));
824 movq(c_rarg2, rsp); // pass pointer to regs array
825 andq(rsp, -16); // align stack as required by ABI
826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
827 hlt();
828 }
829
830 void MacroAssembler::warn(const char* msg) {
831 push(rbp);
832 movq(rbp, rsp);
833 andq(rsp, -16); // align stack as required by push_CPU_state and call
834 push_CPU_state(); // keeps alignment at 16 bytes
835 lea(c_rarg0, ExternalAddress((address) msg));
836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
837 pop_CPU_state();
838 mov(rsp, rbp);
839 pop(rbp);
840 }
841
842 void MacroAssembler::print_state() {
843 address rip = pc();
844 pusha(); // get regs on stack
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849
850 lea(c_rarg0, InternalAddress(rip));
851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
853
854 pop_CPU_state();
855 mov(rsp, rbp);
856 pop(rbp);
857 popa();
858 }
859
860 #ifndef PRODUCT
861 extern "C" void findpc(intptr_t x);
862 #endif
863
864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
865 // In order to get locks to work, we need to fake a in_VM state
866 if (ShowMessageBoxOnError) {
867 JavaThread* thread = JavaThread::current();
868 JavaThreadState saved_state = thread->thread_state();
869 thread->set_thread_state(_thread_in_vm);
870 #ifndef PRODUCT
871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
872 ttyLocker ttyl;
873 BytecodeCounter::print();
874 }
875 #endif
876 // To see where a verify_oop failed, get $ebx+40/X for this frame.
877 // XXX correct this offset for amd64
878 // This is the value of eip which points to where verify_oop will return.
879 if (os::message_box(msg, "Execution stopped, print registers?")) {
880 print_state64(pc, regs);
881 BREAKPOINT;
882 assert(false, "start up GDB");
883 }
884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
885 } else {
886 ttyLocker ttyl;
887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
888 msg);
889 assert(false, "DEBUG MESSAGE: %s", msg);
890 }
891 }
892
893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
894 ttyLocker ttyl;
895 FlagSetting fs(Debugging, true);
896 tty->print_cr("rip = 0x%016lx", pc);
897 #ifndef PRODUCT
898 tty->cr();
899 findpc(pc);
900 tty->cr();
901 #endif
902 #define PRINT_REG(rax, value) \
903 { tty->print("%s = ", #rax); os::print_location(tty, value); }
904 PRINT_REG(rax, regs[15]);
905 PRINT_REG(rbx, regs[12]);
906 PRINT_REG(rcx, regs[14]);
907 PRINT_REG(rdx, regs[13]);
908 PRINT_REG(rdi, regs[8]);
909 PRINT_REG(rsi, regs[9]);
910 PRINT_REG(rbp, regs[10]);
911 PRINT_REG(rsp, regs[11]);
912 PRINT_REG(r8 , regs[7]);
913 PRINT_REG(r9 , regs[6]);
914 PRINT_REG(r10, regs[5]);
915 PRINT_REG(r11, regs[4]);
916 PRINT_REG(r12, regs[3]);
917 PRINT_REG(r13, regs[2]);
918 PRINT_REG(r14, regs[1]);
919 PRINT_REG(r15, regs[0]);
920 #undef PRINT_REG
921 // Print some words near top of staack.
922 int64_t* rsp = (int64_t*) regs[11];
923 int64_t* dump_sp = rsp;
924 for (int col1 = 0; col1 < 8; col1++) {
925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
926 os::print_location(tty, *dump_sp++);
927 }
928 for (int row = 0; row < 25; row++) {
929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
930 for (int col = 0; col < 4; col++) {
931 tty->print(" 0x%016lx", *dump_sp++);
932 }
933 tty->cr();
934 }
935 // Print some instructions around pc:
936 Disassembler::decode((address)pc-64, (address)pc);
937 tty->print_cr("--------");
938 Disassembler::decode((address)pc, (address)pc+32);
939 }
940
941 #endif // _LP64
942
943 // Now versions that are common to 32/64 bit
944
945 void MacroAssembler::addptr(Register dst, int32_t imm32) {
946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
947 }
948
949 void MacroAssembler::addptr(Register dst, Register src) {
950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
951 }
952
953 void MacroAssembler::addptr(Address dst, Register src) {
954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
955 }
956
957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
958 if (reachable(src)) {
959 Assembler::addsd(dst, as_Address(src));
960 } else {
961 lea(rscratch1, src);
962 Assembler::addsd(dst, Address(rscratch1, 0));
963 }
964 }
965
966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
967 if (reachable(src)) {
968 addss(dst, as_Address(src));
969 } else {
970 lea(rscratch1, src);
971 addss(dst, Address(rscratch1, 0));
972 }
973 }
974
975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
976 if (reachable(src)) {
977 Assembler::addpd(dst, as_Address(src));
978 } else {
979 lea(rscratch1, src);
980 Assembler::addpd(dst, Address(rscratch1, 0));
981 }
982 }
983
984 void MacroAssembler::align(int modulus) {
985 align(modulus, offset());
986 }
987
988 void MacroAssembler::align(int modulus, int target) {
989 if (target % modulus != 0) {
990 nop(modulus - (target % modulus));
991 }
992 }
993
994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
995 // Used in sign-masking with aligned address.
996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
997 if (reachable(src)) {
998 Assembler::andpd(dst, as_Address(src));
999 } else {
1000 lea(rscratch1, src);
1001 Assembler::andpd(dst, Address(rscratch1, 0));
1002 }
1003 }
1004
1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1006 // Used in sign-masking with aligned address.
1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1008 if (reachable(src)) {
1009 Assembler::andps(dst, as_Address(src));
1010 } else {
1011 lea(rscratch1, src);
1012 Assembler::andps(dst, Address(rscratch1, 0));
1013 }
1014 }
1015
1016 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1018 }
1019
1020 void MacroAssembler::atomic_incl(Address counter_addr) {
1021 if (os::is_MP())
1022 lock();
1023 incrementl(counter_addr);
1024 }
1025
1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1027 if (reachable(counter_addr)) {
1028 atomic_incl(as_Address(counter_addr));
1029 } else {
1030 lea(scr, counter_addr);
1031 atomic_incl(Address(scr, 0));
1032 }
1033 }
1034
1035 #ifdef _LP64
1036 void MacroAssembler::atomic_incq(Address counter_addr) {
1037 if (os::is_MP())
1038 lock();
1039 incrementq(counter_addr);
1040 }
1041
1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1043 if (reachable(counter_addr)) {
1044 atomic_incq(as_Address(counter_addr));
1045 } else {
1046 lea(scr, counter_addr);
1047 atomic_incq(Address(scr, 0));
1048 }
1049 }
1050 #endif
1051
1052 // Writes to stack successive pages until offset reached to check for
1053 // stack overflow + shadow pages. This clobbers tmp.
1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1055 movptr(tmp, rsp);
1056 // Bang stack for total size given plus shadow page size.
1057 // Bang one page at a time because large size can bang beyond yellow and
1058 // red zones.
1059 Label loop;
1060 bind(loop);
1061 movl(Address(tmp, (-os::vm_page_size())), size );
1062 subptr(tmp, os::vm_page_size());
1063 subl(size, os::vm_page_size());
1064 jcc(Assembler::greater, loop);
1065
1066 // Bang down shadow pages too.
1067 // At this point, (tmp-0) is the last address touched, so don't
1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1069 // was post-decremented.) Skip this address by starting at i=1, and
1070 // touch a few more pages below. N.B. It is important to touch all
1071 // the way down to and including i=StackShadowPages.
1072 for (int i = 1; i < StackShadowPages; i++) {
1073 // this could be any sized move but this is can be a debugging crumb
1074 // so the bigger the better.
1075 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1076 }
1077 }
1078
1079 void MacroAssembler::reserved_stack_check() {
1080 // testing if reserved zone needs to be enabled
1081 Label no_reserved_zone_enabling;
1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1083 NOT_LP64(get_thread(rsi);)
1084
1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1086 jcc(Assembler::below, no_reserved_zone_enabling);
1087
1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1090 should_not_reach_here();
1091
1092 bind(no_reserved_zone_enabling);
1093 }
1094
1095 int MacroAssembler::biased_locking_enter(Register lock_reg,
1096 Register obj_reg,
1097 Register swap_reg,
1098 Register tmp_reg,
1099 bool swap_reg_contains_mark,
1100 Label& done,
1101 Label* slow_case,
1102 BiasedLockingCounters* counters) {
1103 assert(UseBiasedLocking, "why call this otherwise?");
1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1105 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1109 Address saved_mark_addr(lock_reg, 0);
1110
1111 if (PrintBiasedLockingStatistics && counters == NULL) {
1112 counters = BiasedLocking::counters();
1113 }
1114 // Biased locking
1115 // See whether the lock is currently biased toward our thread and
1116 // whether the epoch is still valid
1117 // Note that the runtime guarantees sufficient alignment of JavaThread
1118 // pointers to allow age to be placed into low bits
1119 // First check to see whether biasing is even enabled for this object
1120 Label cas_label;
1121 int null_check_offset = -1;
1122 if (!swap_reg_contains_mark) {
1123 null_check_offset = offset();
1124 movptr(swap_reg, mark_addr);
1125 }
1126 movptr(tmp_reg, swap_reg);
1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1129 jcc(Assembler::notEqual, cas_label);
1130 // The bias pattern is present in the object's header. Need to check
1131 // whether the bias owner and the epoch are both still current.
1132 #ifndef _LP64
1133 // Note that because there is no current thread register on x86_32 we
1134 // need to store off the mark word we read out of the object to
1135 // avoid reloading it and needing to recheck invariants below. This
1136 // store is unfortunate but it makes the overall code shorter and
1137 // simpler.
1138 movptr(saved_mark_addr, swap_reg);
1139 #endif
1140 if (swap_reg_contains_mark) {
1141 null_check_offset = offset();
1142 }
1143 load_prototype_header(tmp_reg, obj_reg);
1144 #ifdef _LP64
1145 orptr(tmp_reg, r15_thread);
1146 xorptr(tmp_reg, swap_reg);
1147 Register header_reg = tmp_reg;
1148 #else
1149 xorptr(tmp_reg, swap_reg);
1150 get_thread(swap_reg);
1151 xorptr(swap_reg, tmp_reg);
1152 Register header_reg = swap_reg;
1153 #endif
1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1155 if (counters != NULL) {
1156 cond_inc32(Assembler::zero,
1157 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1158 }
1159 jcc(Assembler::equal, done);
1160
1161 Label try_revoke_bias;
1162 Label try_rebias;
1163
1164 // At this point we know that the header has the bias pattern and
1165 // that we are not the bias owner in the current epoch. We need to
1166 // figure out more details about the state of the header in order to
1167 // know what operations can be legally performed on the object's
1168 // header.
1169
1170 // If the low three bits in the xor result aren't clear, that means
1171 // the prototype header is no longer biased and we have to revoke
1172 // the bias on this object.
1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1174 jccb(Assembler::notZero, try_revoke_bias);
1175
1176 // Biasing is still enabled for this data type. See whether the
1177 // epoch of the current bias is still valid, meaning that the epoch
1178 // bits of the mark word are equal to the epoch bits of the
1179 // prototype header. (Note that the prototype header's epoch bits
1180 // only change at a safepoint.) If not, attempt to rebias the object
1181 // toward the current thread. Note that we must be absolutely sure
1182 // that the current epoch is invalid in order to do this because
1183 // otherwise the manipulations it performs on the mark word are
1184 // illegal.
1185 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1186 jccb(Assembler::notZero, try_rebias);
1187
1188 // The epoch of the current bias is still valid but we know nothing
1189 // about the owner; it might be set or it might be clear. Try to
1190 // acquire the bias of the object using an atomic operation. If this
1191 // fails we will go in to the runtime to revoke the object's bias.
1192 // Note that we first construct the presumed unbiased header so we
1193 // don't accidentally blow away another thread's valid bias.
1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1195 andptr(swap_reg,
1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1197 #ifdef _LP64
1198 movptr(tmp_reg, swap_reg);
1199 orptr(tmp_reg, r15_thread);
1200 #else
1201 get_thread(tmp_reg);
1202 orptr(tmp_reg, swap_reg);
1203 #endif
1204 if (os::is_MP()) {
1205 lock();
1206 }
1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1208 // If the biasing toward our thread failed, this means that
1209 // another thread succeeded in biasing it toward itself and we
1210 // need to revoke that bias. The revocation will occur in the
1211 // interpreter runtime in the slow case.
1212 if (counters != NULL) {
1213 cond_inc32(Assembler::zero,
1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1215 }
1216 if (slow_case != NULL) {
1217 jcc(Assembler::notZero, *slow_case);
1218 }
1219 jmp(done);
1220
1221 bind(try_rebias);
1222 // At this point we know the epoch has expired, meaning that the
1223 // current "bias owner", if any, is actually invalid. Under these
1224 // circumstances _only_, we are allowed to use the current header's
1225 // value as the comparison value when doing the cas to acquire the
1226 // bias in the current epoch. In other words, we allow transfer of
1227 // the bias from one thread to another directly in this situation.
1228 //
1229 // FIXME: due to a lack of registers we currently blow away the age
1230 // bits in this situation. Should attempt to preserve them.
1231 load_prototype_header(tmp_reg, obj_reg);
1232 #ifdef _LP64
1233 orptr(tmp_reg, r15_thread);
1234 #else
1235 get_thread(swap_reg);
1236 orptr(tmp_reg, swap_reg);
1237 movptr(swap_reg, saved_mark_addr);
1238 #endif
1239 if (os::is_MP()) {
1240 lock();
1241 }
1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1243 // If the biasing toward our thread failed, then another thread
1244 // succeeded in biasing it toward itself and we need to revoke that
1245 // bias. The revocation will occur in the runtime in the slow case.
1246 if (counters != NULL) {
1247 cond_inc32(Assembler::zero,
1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1249 }
1250 if (slow_case != NULL) {
1251 jcc(Assembler::notZero, *slow_case);
1252 }
1253 jmp(done);
1254
1255 bind(try_revoke_bias);
1256 // The prototype mark in the klass doesn't have the bias bit set any
1257 // more, indicating that objects of this data type are not supposed
1258 // to be biased any more. We are going to try to reset the mark of
1259 // this object to the prototype value and fall through to the
1260 // CAS-based locking scheme. Note that if our CAS fails, it means
1261 // that another thread raced us for the privilege of revoking the
1262 // bias of this particular object, so it's okay to continue in the
1263 // normal locking code.
1264 //
1265 // FIXME: due to a lack of registers we currently blow away the age
1266 // bits in this situation. Should attempt to preserve them.
1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1268 load_prototype_header(tmp_reg, obj_reg);
1269 if (os::is_MP()) {
1270 lock();
1271 }
1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1273 // Fall through to the normal CAS-based lock, because no matter what
1274 // the result of the above CAS, some thread must have succeeded in
1275 // removing the bias bit from the object's header.
1276 if (counters != NULL) {
1277 cond_inc32(Assembler::zero,
1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1279 }
1280
1281 bind(cas_label);
1282
1283 return null_check_offset;
1284 }
1285
1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1287 assert(UseBiasedLocking, "why call this otherwise?");
1288
1289 // Check for biased locking unlock case, which is a no-op
1290 // Note: we do not have to check the thread ID for two reasons.
1291 // First, the interpreter checks for IllegalMonitorStateException at
1292 // a higher level. Second, if the bias was revoked while we held the
1293 // lock, the object could not be rebiased toward another thread, so
1294 // the bias bit would be clear.
1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1298 jcc(Assembler::equal, done);
1299 }
1300
1301 #ifdef COMPILER2
1302
1303 #if INCLUDE_RTM_OPT
1304
1305 // Update rtm_counters based on abort status
1306 // input: abort_status
1307 // rtm_counters (RTMLockingCounters*)
1308 // flags are killed
1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1310
1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1312 if (PrintPreciseRTMLockingStatistics) {
1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1314 Label check_abort;
1315 testl(abort_status, (1<<i));
1316 jccb(Assembler::equal, check_abort);
1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1318 bind(check_abort);
1319 }
1320 }
1321 }
1322
1323 // Branch if (random & (count-1) != 0), count is 2^n
1324 // tmp, scr and flags are killed
1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1326 assert(tmp == rax, "");
1327 assert(scr == rdx, "");
1328 rdtsc(); // modifies EDX:EAX
1329 andptr(tmp, count-1);
1330 jccb(Assembler::notZero, brLabel);
1331 }
1332
1333 // Perform abort ratio calculation, set no_rtm bit if high ratio
1334 // input: rtm_counters_Reg (RTMLockingCounters* address)
1335 // tmpReg, rtm_counters_Reg and flags are killed
1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1337 Register rtm_counters_Reg,
1338 RTMLockingCounters* rtm_counters,
1339 Metadata* method_data) {
1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1341
1342 if (RTMLockingCalculationDelay > 0) {
1343 // Delay calculation
1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1345 testptr(tmpReg, tmpReg);
1346 jccb(Assembler::equal, L_done);
1347 }
1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1349 // Aborted transactions = abort_count * 100
1350 // All transactions = total_count * RTMTotalCountIncrRate
1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1352
1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1354 cmpptr(tmpReg, RTMAbortThreshold);
1355 jccb(Assembler::below, L_check_always_rtm2);
1356 imulptr(tmpReg, tmpReg, 100);
1357
1358 Register scrReg = rtm_counters_Reg;
1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1361 imulptr(scrReg, scrReg, RTMAbortRatio);
1362 cmpptr(tmpReg, scrReg);
1363 jccb(Assembler::below, L_check_always_rtm1);
1364 if (method_data != NULL) {
1365 // set rtm_state to "no rtm" in MDO
1366 mov_metadata(tmpReg, method_data);
1367 if (os::is_MP()) {
1368 lock();
1369 }
1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1371 }
1372 jmpb(L_done);
1373 bind(L_check_always_rtm1);
1374 // Reload RTMLockingCounters* address
1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1376 bind(L_check_always_rtm2);
1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1379 jccb(Assembler::below, L_done);
1380 if (method_data != NULL) {
1381 // set rtm_state to "always rtm" in MDO
1382 mov_metadata(tmpReg, method_data);
1383 if (os::is_MP()) {
1384 lock();
1385 }
1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1387 }
1388 bind(L_done);
1389 }
1390
1391 // Update counters and perform abort ratio calculation
1392 // input: abort_status_Reg
1393 // rtm_counters_Reg, flags are killed
1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1395 Register rtm_counters_Reg,
1396 RTMLockingCounters* rtm_counters,
1397 Metadata* method_data,
1398 bool profile_rtm) {
1399
1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1401 // update rtm counters based on rax value at abort
1402 // reads abort_status_Reg, updates flags
1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1405 if (profile_rtm) {
1406 // Save abort status because abort_status_Reg is used by following code.
1407 if (RTMRetryCount > 0) {
1408 push(abort_status_Reg);
1409 }
1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1412 // restore abort status
1413 if (RTMRetryCount > 0) {
1414 pop(abort_status_Reg);
1415 }
1416 }
1417 }
1418
1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1420 // inputs: retry_count_Reg
1421 // : abort_status_Reg
1422 // output: retry_count_Reg decremented by 1
1423 // flags are killed
1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1425 Label doneRetry;
1426 assert(abort_status_Reg == rax, "");
1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1429 // if reason is in 0x6 and retry count != 0 then retry
1430 andptr(abort_status_Reg, 0x6);
1431 jccb(Assembler::zero, doneRetry);
1432 testl(retry_count_Reg, retry_count_Reg);
1433 jccb(Assembler::zero, doneRetry);
1434 pause();
1435 decrementl(retry_count_Reg);
1436 jmp(retryLabel);
1437 bind(doneRetry);
1438 }
1439
1440 // Spin and retry if lock is busy,
1441 // inputs: box_Reg (monitor address)
1442 // : retry_count_Reg
1443 // output: retry_count_Reg decremented by 1
1444 // : clear z flag if retry count exceeded
1445 // tmp_Reg, scr_Reg, flags are killed
1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1448 Label SpinLoop, SpinExit, doneRetry;
1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1450
1451 testl(retry_count_Reg, retry_count_Reg);
1452 jccb(Assembler::zero, doneRetry);
1453 decrementl(retry_count_Reg);
1454 movptr(scr_Reg, RTMSpinLoopCount);
1455
1456 bind(SpinLoop);
1457 pause();
1458 decrementl(scr_Reg);
1459 jccb(Assembler::lessEqual, SpinExit);
1460 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1461 testptr(tmp_Reg, tmp_Reg);
1462 jccb(Assembler::notZero, SpinLoop);
1463
1464 bind(SpinExit);
1465 jmp(retryLabel);
1466 bind(doneRetry);
1467 incrementl(retry_count_Reg); // clear z flag
1468 }
1469
1470 // Use RTM for normal stack locks
1471 // Input: objReg (object to lock)
1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1473 Register retry_on_abort_count_Reg,
1474 RTMLockingCounters* stack_rtm_counters,
1475 Metadata* method_data, bool profile_rtm,
1476 Label& DONE_LABEL, Label& IsInflated) {
1477 assert(UseRTMForStackLocks, "why call this otherwise?");
1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1479 assert(tmpReg == rax, "");
1480 assert(scrReg == rdx, "");
1481 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1482
1483 if (RTMRetryCount > 0) {
1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1485 bind(L_rtm_retry);
1486 }
1487 movptr(tmpReg, Address(objReg, 0));
1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1489 jcc(Assembler::notZero, IsInflated);
1490
1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1492 Label L_noincrement;
1493 if (RTMTotalCountIncrRate > 1) {
1494 // tmpReg, scrReg and flags are killed
1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1496 }
1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1499 bind(L_noincrement);
1500 }
1501 xbegin(L_on_abort);
1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1506
1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1508 if (UseRTMXendForLockBusy) {
1509 xend();
1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1511 jmp(L_decrement_retry);
1512 }
1513 else {
1514 xabort(0);
1515 }
1516 bind(L_on_abort);
1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1519 }
1520 bind(L_decrement_retry);
1521 if (RTMRetryCount > 0) {
1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1524 }
1525 }
1526
1527 // Use RTM for inflating locks
1528 // inputs: objReg (object to lock)
1529 // boxReg (on-stack box address (displaced header location) - KILLED)
1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1532 Register scrReg, Register retry_on_busy_count_Reg,
1533 Register retry_on_abort_count_Reg,
1534 RTMLockingCounters* rtm_counters,
1535 Metadata* method_data, bool profile_rtm,
1536 Label& DONE_LABEL) {
1537 assert(UseRTMLocking, "why call this otherwise?");
1538 assert(tmpReg == rax, "");
1539 assert(scrReg == rdx, "");
1540 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1542
1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1546
1547 if (RTMRetryCount > 0) {
1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1550 bind(L_rtm_retry);
1551 }
1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1553 Label L_noincrement;
1554 if (RTMTotalCountIncrRate > 1) {
1555 // tmpReg, scrReg and flags are killed
1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1557 }
1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1560 bind(L_noincrement);
1561 }
1562 xbegin(L_on_abort);
1563 movptr(tmpReg, Address(objReg, 0));
1564 movptr(tmpReg, Address(tmpReg, owner_offset));
1565 testptr(tmpReg, tmpReg);
1566 jcc(Assembler::zero, DONE_LABEL);
1567 if (UseRTMXendForLockBusy) {
1568 xend();
1569 jmp(L_decrement_retry);
1570 }
1571 else {
1572 xabort(0);
1573 }
1574 bind(L_on_abort);
1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1578 }
1579 if (RTMRetryCount > 0) {
1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1582 }
1583
1584 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1585 testptr(tmpReg, tmpReg) ;
1586 jccb(Assembler::notZero, L_decrement_retry) ;
1587
1588 // Appears unlocked - try to swing _owner from null to non-null.
1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1590 #ifdef _LP64
1591 Register threadReg = r15_thread;
1592 #else
1593 get_thread(scrReg);
1594 Register threadReg = scrReg;
1595 #endif
1596 if (os::is_MP()) {
1597 lock();
1598 }
1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1600
1601 if (RTMRetryCount > 0) {
1602 // success done else retry
1603 jccb(Assembler::equal, DONE_LABEL) ;
1604 bind(L_decrement_retry);
1605 // Spin and retry if lock is busy.
1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1607 }
1608 else {
1609 bind(L_decrement_retry);
1610 }
1611 }
1612
1613 #endif // INCLUDE_RTM_OPT
1614
1615 // Fast_Lock and Fast_Unlock used by C2
1616
1617 // Because the transitions from emitted code to the runtime
1618 // monitorenter/exit helper stubs are so slow it's critical that
1619 // we inline both the stack-locking fast-path and the inflated fast path.
1620 //
1621 // See also: cmpFastLock and cmpFastUnlock.
1622 //
1623 // What follows is a specialized inline transliteration of the code
1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1625 // another option would be to emit TrySlowEnter and TrySlowExit methods
1626 // at startup-time. These methods would accept arguments as
1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1630 // In practice, however, the # of lock sites is bounded and is usually small.
1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1632 // if the processor uses simple bimodal branch predictors keyed by EIP
1633 // Since the helper routines would be called from multiple synchronization
1634 // sites.
1635 //
1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1638 // to those specialized methods. That'd give us a mostly platform-independent
1639 // implementation that the JITs could optimize and inline at their pleasure.
1640 // Done correctly, the only time we'd need to cross to native could would be
1641 // to park() or unpark() threads. We'd also need a few more unsafe operators
1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1643 // (b) explicit barriers or fence operations.
1644 //
1645 // TODO:
1646 //
1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1650 // the lock operators would typically be faster than reifying Self.
1651 //
1652 // * Ideally I'd define the primitives as:
1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1656 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1657 // Furthermore the register assignments are overconstrained, possibly resulting in
1658 // sub-optimal code near the synchronization site.
1659 //
1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1661 // Alternately, use a better sp-proximity test.
1662 //
1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1664 // Either one is sufficient to uniquely identify a thread.
1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1666 //
1667 // * Intrinsify notify() and notifyAll() for the common cases where the
1668 // object is locked by the calling thread but the waitlist is empty.
1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1670 //
1671 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1672 // But beware of excessive branch density on AMD Opterons.
1673 //
1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1675 // or failure of the fast-path. If the fast-path fails then we pass
1676 // control to the slow-path, typically in C. In Fast_Lock and
1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1678 // will emit a conditional branch immediately after the node.
1679 // So we have branches to branches and lots of ICC.ZF games.
1680 // Instead, it might be better to have C2 pass a "FailureLabel"
1681 // into Fast_Lock and Fast_Unlock. In the case of success, control
1682 // will drop through the node. ICC.ZF is undefined at exit.
1683 // In the case of failure, the node will branch directly to the
1684 // FailureLabel
1685
1686
1687 // obj: object to lock
1688 // box: on-stack box address (displaced header location) - KILLED
1689 // rax,: tmp -- KILLED
1690 // scr: tmp -- KILLED
1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1692 Register scrReg, Register cx1Reg, Register cx2Reg,
1693 BiasedLockingCounters* counters,
1694 RTMLockingCounters* rtm_counters,
1695 RTMLockingCounters* stack_rtm_counters,
1696 Metadata* method_data,
1697 bool use_rtm, bool profile_rtm) {
1698 // Ensure the register assignents are disjoint
1699 assert(tmpReg == rax, "");
1700
1701 if (use_rtm) {
1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1703 } else {
1704 assert(cx1Reg == noreg, "");
1705 assert(cx2Reg == noreg, "");
1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1707 }
1708
1709 if (counters != NULL) {
1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1711 }
1712 if (EmitSync & 1) {
1713 // set box->dhw = markOopDesc::unused_mark()
1714 // Force all sync thru slow-path: slow_enter() and slow_exit()
1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1716 cmpptr (rsp, (int32_t)NULL_WORD);
1717 } else {
1718 // Possible cases that we'll encounter in fast_lock
1719 // ------------------------------------------------
1720 // * Inflated
1721 // -- unlocked
1722 // -- Locked
1723 // = by self
1724 // = by other
1725 // * biased
1726 // -- by Self
1727 // -- by other
1728 // * neutral
1729 // * stack-locked
1730 // -- by self
1731 // = sp-proximity test hits
1732 // = sp-proximity test generates false-negative
1733 // -- by other
1734 //
1735
1736 Label IsInflated, DONE_LABEL;
1737
1738 // it's stack-locked, biased or neutral
1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1740 // order to reduce the number of conditional branches in the most common cases.
1741 // Beware -- there's a subtle invariant that fetch of the markword
1742 // at [FETCH], below, will never observe a biased encoding (*101b).
1743 // If this invariant is not held we risk exclusion (safety) failure.
1744 if (UseBiasedLocking && !UseOptoBiasInlining) {
1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1746 }
1747
1748 #if INCLUDE_RTM_OPT
1749 if (UseRTMForStackLocks && use_rtm) {
1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1751 stack_rtm_counters, method_data, profile_rtm,
1752 DONE_LABEL, IsInflated);
1753 }
1754 #endif // INCLUDE_RTM_OPT
1755
1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1758 jccb(Assembler::notZero, IsInflated);
1759
1760 // Attempt stack-locking ...
1761 orptr (tmpReg, markOopDesc::unlocked_value);
1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1763 if (os::is_MP()) {
1764 lock();
1765 }
1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1767 if (counters != NULL) {
1768 cond_inc32(Assembler::equal,
1769 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1770 }
1771 jcc(Assembler::equal, DONE_LABEL); // Success
1772
1773 // Recursive locking.
1774 // The object is stack-locked: markword contains stack pointer to BasicLock.
1775 // Locked by current thread if difference with current SP is less than one page.
1776 subptr(tmpReg, rsp);
1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1779 movptr(Address(boxReg, 0), tmpReg);
1780 if (counters != NULL) {
1781 cond_inc32(Assembler::equal,
1782 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1783 }
1784 jmp(DONE_LABEL);
1785
1786 bind(IsInflated);
1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1788
1789 #if INCLUDE_RTM_OPT
1790 // Use the same RTM locking code in 32- and 64-bit VM.
1791 if (use_rtm) {
1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1793 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1794 } else {
1795 #endif // INCLUDE_RTM_OPT
1796
1797 #ifndef _LP64
1798 // The object is inflated.
1799
1800 // boxReg refers to the on-stack BasicLock in the current frame.
1801 // We'd like to write:
1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1804 // additional latency as we have another ST in the store buffer that must drain.
1805
1806 if (EmitSync & 8192) {
1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1808 get_thread (scrReg);
1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1811 if (os::is_MP()) {
1812 lock();
1813 }
1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1815 } else
1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1817 // register juggle because we need tmpReg for cmpxchgptr below
1818 movptr(scrReg, boxReg);
1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1820
1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1823 // prefetchw [eax + Offset(_owner)-2]
1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1825 }
1826
1827 if ((EmitSync & 64) == 0) {
1828 // Optimistic form: consider XORL tmpReg,tmpReg
1829 movptr(tmpReg, NULL_WORD);
1830 } else {
1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1832 // Test-And-CAS instead of CAS
1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1834 testptr(tmpReg, tmpReg); // Locked ?
1835 jccb (Assembler::notZero, DONE_LABEL);
1836 }
1837
1838 // Appears unlocked - try to swing _owner from null to non-null.
1839 // Ideally, I'd manifest "Self" with get_thread and then attempt
1840 // to CAS the register containing Self into m->Owner.
1841 // But we don't have enough registers, so instead we can either try to CAS
1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1843 // we later store "Self" into m->Owner. Transiently storing a stack address
1844 // (rsp or the address of the box) into m->owner is harmless.
1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1846 if (os::is_MP()) {
1847 lock();
1848 }
1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1851 // If we weren't able to swing _owner from NULL to the BasicLock
1852 // then take the slow path.
1853 jccb (Assembler::notZero, DONE_LABEL);
1854 // update _owner from BasicLock to thread
1855 get_thread (scrReg); // beware: clobbers ICCs
1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1858
1859 // If the CAS fails we can either retry or pass control to the slow-path.
1860 // We use the latter tactic.
1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1862 // If the CAS was successful ...
1863 // Self has acquired the lock
1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1865 // Intentional fall-through into DONE_LABEL ...
1866 } else {
1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1868 movptr(boxReg, tmpReg);
1869
1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1872 // prefetchw [eax + Offset(_owner)-2]
1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1874 }
1875
1876 if ((EmitSync & 64) == 0) {
1877 // Optimistic form
1878 xorptr (tmpReg, tmpReg);
1879 } else {
1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1882 testptr(tmpReg, tmpReg); // Locked ?
1883 jccb (Assembler::notZero, DONE_LABEL);
1884 }
1885
1886 // Appears unlocked - try to swing _owner from null to non-null.
1887 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1889 get_thread (scrReg);
1890 if (os::is_MP()) {
1891 lock();
1892 }
1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1894
1895 // If the CAS fails we can either retry or pass control to the slow-path.
1896 // We use the latter tactic.
1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1898 // If the CAS was successful ...
1899 // Self has acquired the lock
1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1901 // Intentional fall-through into DONE_LABEL ...
1902 }
1903 #else // _LP64
1904 // It's inflated
1905 movq(scrReg, tmpReg);
1906 xorq(tmpReg, tmpReg);
1907
1908 if (os::is_MP()) {
1909 lock();
1910 }
1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1913 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1915 // Intentional fall-through into DONE_LABEL ...
1916 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1917 #endif // _LP64
1918 #if INCLUDE_RTM_OPT
1919 } // use_rtm()
1920 #endif
1921 // DONE_LABEL is a hot target - we'd really like to place it at the
1922 // start of cache line by padding with NOPs.
1923 // See the AMD and Intel software optimization manuals for the
1924 // most efficient "long" NOP encodings.
1925 // Unfortunately none of our alignment mechanisms suffice.
1926 bind(DONE_LABEL);
1927
1928 // At DONE_LABEL the icc ZFlag is set as follows ...
1929 // Fast_Unlock uses the same protocol.
1930 // ZFlag == 1 -> Success
1931 // ZFlag == 0 -> Failure - force control through the slow-path
1932 }
1933 }
1934
1935 // obj: object to unlock
1936 // box: box address (displaced header location), killed. Must be EAX.
1937 // tmp: killed, cannot be obj nor box.
1938 //
1939 // Some commentary on balanced locking:
1940 //
1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1942 // Methods that don't have provably balanced locking are forced to run in the
1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1944 // The interpreter provides two properties:
1945 // I1: At return-time the interpreter automatically and quietly unlocks any
1946 // objects acquired the current activation (frame). Recall that the
1947 // interpreter maintains an on-stack list of locks currently held by
1948 // a frame.
1949 // I2: If a method attempts to unlock an object that is not held by the
1950 // the frame the interpreter throws IMSX.
1951 //
1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1953 // B() doesn't have provably balanced locking so it runs in the interpreter.
1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1955 // is still locked by A().
1956 //
1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1961 // Arguably given that the spec legislates the JNI case as undefined our implementation
1962 // could reasonably *avoid* checking owner in Fast_Unlock().
1963 // In the interest of performance we elide m->Owner==Self check in unlock.
1964 // A perfectly viable alternative is to elide the owner check except when
1965 // Xcheck:jni is enabled.
1966
1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1968 assert(boxReg == rax, "");
1969 assert_different_registers(objReg, boxReg, tmpReg);
1970
1971 if (EmitSync & 4) {
1972 // Disable - inhibit all inlining. Force control through the slow-path
1973 cmpptr (rsp, 0);
1974 } else {
1975 Label DONE_LABEL, Stacked, CheckSucc;
1976
1977 // Critically, the biased locking test must have precedence over
1978 // and appear before the (box->dhw == 0) recursive stack-lock test.
1979 if (UseBiasedLocking && !UseOptoBiasInlining) {
1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1981 }
1982
1983 #if INCLUDE_RTM_OPT
1984 if (UseRTMForStackLocks && use_rtm) {
1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1986 Label L_regular_unlock;
1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1991 xend(); // otherwise end...
1992 jmp(DONE_LABEL); // ... and we're done
1993 bind(L_regular_unlock);
1994 }
1995 #endif
1996
1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
2001 jccb (Assembler::zero, Stacked);
2002
2003 // It's inflated.
2004 #if INCLUDE_RTM_OPT
2005 if (use_rtm) {
2006 Label L_regular_inflated_unlock;
2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2008 movptr(boxReg, Address(tmpReg, owner_offset));
2009 testptr(boxReg, boxReg);
2010 jccb(Assembler::notZero, L_regular_inflated_unlock);
2011 xend();
2012 jmpb(DONE_LABEL);
2013 bind(L_regular_inflated_unlock);
2014 }
2015 #endif
2016
2017 // Despite our balanced locking property we still check that m->_owner == Self
2018 // as java routines or native JNI code called by this thread might
2019 // have released the lock.
2020 // Refer to the comments in synchronizer.cpp for how we might encode extra
2021 // state in _succ so we can avoid fetching EntryList|cxq.
2022 //
2023 // I'd like to add more cases in fast_lock() and fast_unlock() --
2024 // such as recursive enter and exit -- but we have to be wary of
2025 // I$ bloat, T$ effects and BP$ effects.
2026 //
2027 // If there's no contention try a 1-0 exit. That is, exit without
2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2029 // we detect and recover from the race that the 1-0 exit admits.
2030 //
2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2032 // before it STs null into _owner, releasing the lock. Updates
2033 // to data protected by the critical section must be visible before
2034 // we drop the lock (and thus before any other thread could acquire
2035 // the lock and observe the fields protected by the lock).
2036 // IA32's memory-model is SPO, so STs are ordered with respect to
2037 // each other and there's no need for an explicit barrier (fence).
2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2039 #ifndef _LP64
2040 get_thread (boxReg);
2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2042 // prefetchw [ebx + Offset(_owner)-2]
2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2044 }
2045
2046 // Note that we could employ various encoding schemes to reduce
2047 // the number of loads below (currently 4) to just 2 or 3.
2048 // Refer to the comments in synchronizer.cpp.
2049 // In practice the chain of fetches doesn't seem to impact performance, however.
2050 xorptr(boxReg, boxReg);
2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2052 // Attempt to reduce branch density - AMD's branch predictor.
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2056 jccb (Assembler::notZero, DONE_LABEL);
2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2058 jmpb (DONE_LABEL);
2059 } else {
2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2061 jccb (Assembler::notZero, DONE_LABEL);
2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2064 jccb (Assembler::notZero, CheckSucc);
2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2066 jmpb (DONE_LABEL);
2067 }
2068
2069 // The Following code fragment (EmitSync & 65536) improves the performance of
2070 // contended applications and contended synchronization microbenchmarks.
2071 // Unfortunately the emission of the code - even though not executed - causes regressions
2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2073 // with an equal number of never-executed NOPs results in the same regression.
2074 // We leave it off by default.
2075
2076 if ((EmitSync & 65536) != 0) {
2077 Label LSuccess, LGoSlowPath ;
2078
2079 bind (CheckSucc);
2080
2081 // Optional pre-test ... it's safe to elide this
2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2083 jccb(Assembler::zero, LGoSlowPath);
2084
2085 // We have a classic Dekker-style idiom:
2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2087 // There are a number of ways to implement the barrier:
2088 // (1) lock:andl &m->_owner, 0
2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2092 // (2) If supported, an explicit MFENCE is appealing.
2093 // In older IA32 processors MFENCE is slower than lock:add or xchg
2094 // particularly if the write-buffer is full as might be the case if
2095 // if stores closely precede the fence or fence-equivalent instruction.
2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2097 // as the situation has changed with Nehalem and Shanghai.
2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2099 // The $lines underlying the top-of-stack should be in M-state.
2100 // The locked add instruction is serializing, of course.
2101 // (4) Use xchg, which is serializing
2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2104 // The integer condition codes will tell us if succ was 0.
2105 // Since _succ and _owner should reside in the same $line and
2106 // we just stored into _owner, it's likely that the $line
2107 // remains in M-state for the lock:orl.
2108 //
2109 // We currently use (3), although it's likely that switching to (2)
2110 // is correct for the future.
2111
2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2113 if (os::is_MP()) {
2114 lock(); addptr(Address(rsp, 0), 0);
2115 }
2116 // Ratify _succ remains non-null
2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2118 jccb (Assembler::notZero, LSuccess);
2119
2120 xorptr(boxReg, boxReg); // box is really EAX
2121 if (os::is_MP()) { lock(); }
2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2123 // There's no successor so we tried to regrab the lock with the
2124 // placeholder value. If that didn't work, then another thread
2125 // grabbed the lock so we're done (and exit was a success).
2126 jccb (Assembler::notEqual, LSuccess);
2127 // Since we're low on registers we installed rsp as a placeholding in _owner.
2128 // Now install Self over rsp. This is safe as we're transitioning from
2129 // non-null to non=null
2130 get_thread (boxReg);
2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2132 // Intentional fall-through into LGoSlowPath ...
2133
2134 bind (LGoSlowPath);
2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2136 jmpb (DONE_LABEL);
2137
2138 bind (LSuccess);
2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2140 jmpb (DONE_LABEL);
2141 }
2142
2143 bind (Stacked);
2144 // It's not inflated and it's not recursively stack-locked and it's not biased.
2145 // It must be stack-locked.
2146 // Try to reset the header to displaced header.
2147 // The "box" value on the stack is stable, so we can reload
2148 // and be assured we observe the same value as above.
2149 movptr(tmpReg, Address(boxReg, 0));
2150 if (os::is_MP()) {
2151 lock();
2152 }
2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2154 // Intention fall-thru into DONE_LABEL
2155
2156 // DONE_LABEL is a hot target - we'd really like to place it at the
2157 // start of cache line by padding with NOPs.
2158 // See the AMD and Intel software optimization manuals for the
2159 // most efficient "long" NOP encodings.
2160 // Unfortunately none of our alignment mechanisms suffice.
2161 if ((EmitSync & 65536) == 0) {
2162 bind (CheckSucc);
2163 }
2164 #else // _LP64
2165 // It's inflated
2166 if (EmitSync & 1024) {
2167 // Emit code to check that _owner == Self
2168 // We could fold the _owner test into subsequent code more efficiently
2169 // than using a stand-alone check, but since _owner checking is off by
2170 // default we don't bother. We also might consider predicating the
2171 // _owner==Self check on Xcheck:jni or running on a debug build.
2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2173 xorptr(boxReg, r15_thread);
2174 } else {
2175 xorptr(boxReg, boxReg);
2176 }
2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2178 jccb (Assembler::notZero, DONE_LABEL);
2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2181 jccb (Assembler::notZero, CheckSucc);
2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2183 jmpb (DONE_LABEL);
2184
2185 if ((EmitSync & 65536) == 0) {
2186 // Try to avoid passing control into the slow_path ...
2187 Label LSuccess, LGoSlowPath ;
2188 bind (CheckSucc);
2189
2190 // The following optional optimization can be elided if necessary
2191 // Effectively: if (succ == null) goto SlowPath
2192 // The code reduces the window for a race, however,
2193 // and thus benefits performance.
2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2195 jccb (Assembler::zero, LGoSlowPath);
2196
2197 if ((EmitSync & 16) && os::is_MP()) {
2198 orptr(boxReg, boxReg);
2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2200 } else {
2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2202 if (os::is_MP()) {
2203 // Memory barrier/fence
2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2206 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2210 lock(); addl(Address(rsp, 0), 0);
2211 }
2212 }
2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2214 jccb (Assembler::notZero, LSuccess);
2215
2216 // Rare inopportune interleaving - race.
2217 // The successor vanished in the small window above.
2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2219 // We need to ensure progress and succession.
2220 // Try to reacquire the lock.
2221 // If that fails then the new owner is responsible for succession and this
2222 // thread needs to take no further action and can exit via the fast path (success).
2223 // If the re-acquire succeeds then pass control into the slow path.
2224 // As implemented, this latter mode is horrible because we generated more
2225 // coherence traffic on the lock *and* artifically extended the critical section
2226 // length while by virtue of passing control into the slow path.
2227
2228 // box is really RAX -- the following CMPXCHG depends on that binding
2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2230 movptr(boxReg, (int32_t)NULL_WORD);
2231 if (os::is_MP()) { lock(); }
2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2233 // There's no successor so we tried to regrab the lock.
2234 // If that didn't work, then another thread grabbed the
2235 // lock so we're done (and exit was a success).
2236 jccb (Assembler::notEqual, LSuccess);
2237 // Intentional fall-through into slow-path
2238
2239 bind (LGoSlowPath);
2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2241 jmpb (DONE_LABEL);
2242
2243 bind (LSuccess);
2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2245 jmpb (DONE_LABEL);
2246 }
2247
2248 bind (Stacked);
2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2250 if (os::is_MP()) { lock(); }
2251 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2252
2253 if (EmitSync & 65536) {
2254 bind (CheckSucc);
2255 }
2256 #endif
2257 bind(DONE_LABEL);
2258 }
2259 }
2260 #endif // COMPILER2
2261
2262 void MacroAssembler::c2bool(Register x) {
2263 // implements x == 0 ? 0 : 1
2264 // note: must only look at least-significant byte of x
2265 // since C-style booleans are stored in one byte
2266 // only! (was bug)
2267 andl(x, 0xFF);
2268 setb(Assembler::notZero, x);
2269 }
2270
2271 // Wouldn't need if AddressLiteral version had new name
2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2273 Assembler::call(L, rtype);
2274 }
2275
2276 void MacroAssembler::call(Register entry) {
2277 Assembler::call(entry);
2278 }
2279
2280 void MacroAssembler::call(AddressLiteral entry) {
2281 if (reachable(entry)) {
2282 Assembler::call_literal(entry.target(), entry.rspec());
2283 } else {
2284 lea(rscratch1, entry);
2285 Assembler::call(rscratch1);
2286 }
2287 }
2288
2289 void MacroAssembler::ic_call(address entry, jint method_index) {
2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2291 movptr(rax, (intptr_t)Universe::non_oop_word());
2292 call(AddressLiteral(entry, rh));
2293 }
2294
2295 // Implementation of call_VM versions
2296
2297 void MacroAssembler::call_VM(Register oop_result,
2298 address entry_point,
2299 bool check_exceptions) {
2300 Label C, E;
2301 call(C, relocInfo::none);
2302 jmp(E);
2303
2304 bind(C);
2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2306 ret(0);
2307
2308 bind(E);
2309 }
2310
2311 void MacroAssembler::call_VM(Register oop_result,
2312 address entry_point,
2313 Register arg_1,
2314 bool check_exceptions) {
2315 Label C, E;
2316 call(C, relocInfo::none);
2317 jmp(E);
2318
2319 bind(C);
2320 pass_arg1(this, arg_1);
2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2322 ret(0);
2323
2324 bind(E);
2325 }
2326
2327 void MacroAssembler::call_VM(Register oop_result,
2328 address entry_point,
2329 Register arg_1,
2330 Register arg_2,
2331 bool check_exceptions) {
2332 Label C, E;
2333 call(C, relocInfo::none);
2334 jmp(E);
2335
2336 bind(C);
2337
2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2339
2340 pass_arg2(this, arg_2);
2341 pass_arg1(this, arg_1);
2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2343 ret(0);
2344
2345 bind(E);
2346 }
2347
2348 void MacroAssembler::call_VM(Register oop_result,
2349 address entry_point,
2350 Register arg_1,
2351 Register arg_2,
2352 Register arg_3,
2353 bool check_exceptions) {
2354 Label C, E;
2355 call(C, relocInfo::none);
2356 jmp(E);
2357
2358 bind(C);
2359
2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2362 pass_arg3(this, arg_3);
2363
2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2365 pass_arg2(this, arg_2);
2366
2367 pass_arg1(this, arg_1);
2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2369 ret(0);
2370
2371 bind(E);
2372 }
2373
2374 void MacroAssembler::call_VM(Register oop_result,
2375 Register last_java_sp,
2376 address entry_point,
2377 int number_of_arguments,
2378 bool check_exceptions) {
2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2381 }
2382
2383 void MacroAssembler::call_VM(Register oop_result,
2384 Register last_java_sp,
2385 address entry_point,
2386 Register arg_1,
2387 bool check_exceptions) {
2388 pass_arg1(this, arg_1);
2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2390 }
2391
2392 void MacroAssembler::call_VM(Register oop_result,
2393 Register last_java_sp,
2394 address entry_point,
2395 Register arg_1,
2396 Register arg_2,
2397 bool check_exceptions) {
2398
2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2400 pass_arg2(this, arg_2);
2401 pass_arg1(this, arg_1);
2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2403 }
2404
2405 void MacroAssembler::call_VM(Register oop_result,
2406 Register last_java_sp,
2407 address entry_point,
2408 Register arg_1,
2409 Register arg_2,
2410 Register arg_3,
2411 bool check_exceptions) {
2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2414 pass_arg3(this, arg_3);
2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2416 pass_arg2(this, arg_2);
2417 pass_arg1(this, arg_1);
2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2419 }
2420
2421 void MacroAssembler::super_call_VM(Register oop_result,
2422 Register last_java_sp,
2423 address entry_point,
2424 int number_of_arguments,
2425 bool check_exceptions) {
2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2428 }
2429
2430 void MacroAssembler::super_call_VM(Register oop_result,
2431 Register last_java_sp,
2432 address entry_point,
2433 Register arg_1,
2434 bool check_exceptions) {
2435 pass_arg1(this, arg_1);
2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2437 }
2438
2439 void MacroAssembler::super_call_VM(Register oop_result,
2440 Register last_java_sp,
2441 address entry_point,
2442 Register arg_1,
2443 Register arg_2,
2444 bool check_exceptions) {
2445
2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2447 pass_arg2(this, arg_2);
2448 pass_arg1(this, arg_1);
2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2450 }
2451
2452 void MacroAssembler::super_call_VM(Register oop_result,
2453 Register last_java_sp,
2454 address entry_point,
2455 Register arg_1,
2456 Register arg_2,
2457 Register arg_3,
2458 bool check_exceptions) {
2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2461 pass_arg3(this, arg_3);
2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2463 pass_arg2(this, arg_2);
2464 pass_arg1(this, arg_1);
2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2466 }
2467
2468 void MacroAssembler::call_VM_base(Register oop_result,
2469 Register java_thread,
2470 Register last_java_sp,
2471 address entry_point,
2472 int number_of_arguments,
2473 bool check_exceptions) {
2474 // determine java_thread register
2475 if (!java_thread->is_valid()) {
2476 #ifdef _LP64
2477 java_thread = r15_thread;
2478 #else
2479 java_thread = rdi;
2480 get_thread(java_thread);
2481 #endif // LP64
2482 }
2483 // determine last_java_sp register
2484 if (!last_java_sp->is_valid()) {
2485 last_java_sp = rsp;
2486 }
2487 // debugging support
2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2490 #ifdef ASSERT
2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2492 // r12 is the heapbase.
2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2494 #endif // ASSERT
2495
2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2498
2499 // push java thread (becomes first argument of C function)
2500
2501 NOT_LP64(push(java_thread); number_of_arguments++);
2502 LP64_ONLY(mov(c_rarg0, r15_thread));
2503
2504 // set last Java frame before call
2505 assert(last_java_sp != rbp, "can't use ebp/rbp");
2506
2507 // Only interpreter should have to set fp
2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2509
2510 // do the call, remove parameters
2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2512
2513 // restore the thread (cannot use the pushed argument since arguments
2514 // may be overwritten by C code generated by an optimizing compiler);
2515 // however can use the register value directly if it is callee saved.
2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2517 // rdi & rsi (also r15) are callee saved -> nothing to do
2518 #ifdef ASSERT
2519 guarantee(java_thread != rax, "change this code");
2520 push(rax);
2521 { Label L;
2522 get_thread(rax);
2523 cmpptr(java_thread, rax);
2524 jcc(Assembler::equal, L);
2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2526 bind(L);
2527 }
2528 pop(rax);
2529 #endif
2530 } else {
2531 get_thread(java_thread);
2532 }
2533 // reset last Java frame
2534 // Only interpreter should have to clear fp
2535 reset_last_Java_frame(java_thread, true, false);
2536
2537 #ifndef CC_INTERP
2538 // C++ interp handles this in the interpreter
2539 check_and_handle_popframe(java_thread);
2540 check_and_handle_earlyret(java_thread);
2541 #endif /* CC_INTERP */
2542
2543 if (check_exceptions) {
2544 // check for pending exceptions (java_thread is set upon return)
2545 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2546 #ifndef _LP64
2547 jump_cc(Assembler::notEqual,
2548 RuntimeAddress(StubRoutines::forward_exception_entry()));
2549 #else
2550 // This used to conditionally jump to forward_exception however it is
2551 // possible if we relocate that the branch will not reach. So we must jump
2552 // around so we can always reach
2553
2554 Label ok;
2555 jcc(Assembler::equal, ok);
2556 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2557 bind(ok);
2558 #endif // LP64
2559 }
2560
2561 // get oop result if there is one and reset the value in the thread
2562 if (oop_result->is_valid()) {
2563 get_vm_result(oop_result, java_thread);
2564 }
2565 }
2566
2567 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2568
2569 // Calculate the value for last_Java_sp
2570 // somewhat subtle. call_VM does an intermediate call
2571 // which places a return address on the stack just under the
2572 // stack pointer as the user finsihed with it. This allows
2573 // use to retrieve last_Java_pc from last_Java_sp[-1].
2574 // On 32bit we then have to push additional args on the stack to accomplish
2575 // the actual requested call. On 64bit call_VM only can use register args
2576 // so the only extra space is the return address that call_VM created.
2577 // This hopefully explains the calculations here.
2578
2579 #ifdef _LP64
2580 // We've pushed one address, correct last_Java_sp
2581 lea(rax, Address(rsp, wordSize));
2582 #else
2583 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2584 #endif // LP64
2585
2586 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2587
2588 }
2589
2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2591 call_VM_leaf_base(entry_point, number_of_arguments);
2592 }
2593
2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2595 pass_arg0(this, arg_0);
2596 call_VM_leaf(entry_point, 1);
2597 }
2598
2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2600
2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2602 pass_arg1(this, arg_1);
2603 pass_arg0(this, arg_0);
2604 call_VM_leaf(entry_point, 2);
2605 }
2606
2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2608 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2609 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2610 pass_arg2(this, arg_2);
2611 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2612 pass_arg1(this, arg_1);
2613 pass_arg0(this, arg_0);
2614 call_VM_leaf(entry_point, 3);
2615 }
2616
2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2618 pass_arg0(this, arg_0);
2619 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2620 }
2621
2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2623
2624 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2625 pass_arg1(this, arg_1);
2626 pass_arg0(this, arg_0);
2627 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2628 }
2629
2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2631 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2632 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2633 pass_arg2(this, arg_2);
2634 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2635 pass_arg1(this, arg_1);
2636 pass_arg0(this, arg_0);
2637 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2638 }
2639
2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2641 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2642 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2643 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2644 pass_arg3(this, arg_3);
2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647 pass_arg2(this, arg_2);
2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649 pass_arg1(this, arg_1);
2650 pass_arg0(this, arg_0);
2651 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2652 }
2653
2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2655 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2656 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2657 verify_oop(oop_result, "broken oop in call_VM_base");
2658 }
2659
2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2661 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2662 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2663 }
2664
2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2666 }
2667
2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2669 }
2670
2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2672 if (reachable(src1)) {
2673 cmpl(as_Address(src1), imm);
2674 } else {
2675 lea(rscratch1, src1);
2676 cmpl(Address(rscratch1, 0), imm);
2677 }
2678 }
2679
2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2681 assert(!src2.is_lval(), "use cmpptr");
2682 if (reachable(src2)) {
2683 cmpl(src1, as_Address(src2));
2684 } else {
2685 lea(rscratch1, src2);
2686 cmpl(src1, Address(rscratch1, 0));
2687 }
2688 }
2689
2690 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2691 Assembler::cmpl(src1, imm);
2692 }
2693
2694 void MacroAssembler::cmp32(Register src1, Address src2) {
2695 Assembler::cmpl(src1, src2);
2696 }
2697
2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2699 ucomisd(opr1, opr2);
2700
2701 Label L;
2702 if (unordered_is_less) {
2703 movl(dst, -1);
2704 jcc(Assembler::parity, L);
2705 jcc(Assembler::below , L);
2706 movl(dst, 0);
2707 jcc(Assembler::equal , L);
2708 increment(dst);
2709 } else { // unordered is greater
2710 movl(dst, 1);
2711 jcc(Assembler::parity, L);
2712 jcc(Assembler::above , L);
2713 movl(dst, 0);
2714 jcc(Assembler::equal , L);
2715 decrementl(dst);
2716 }
2717 bind(L);
2718 }
2719
2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2721 ucomiss(opr1, opr2);
2722
2723 Label L;
2724 if (unordered_is_less) {
2725 movl(dst, -1);
2726 jcc(Assembler::parity, L);
2727 jcc(Assembler::below , L);
2728 movl(dst, 0);
2729 jcc(Assembler::equal , L);
2730 increment(dst);
2731 } else { // unordered is greater
2732 movl(dst, 1);
2733 jcc(Assembler::parity, L);
2734 jcc(Assembler::above , L);
2735 movl(dst, 0);
2736 jcc(Assembler::equal , L);
2737 decrementl(dst);
2738 }
2739 bind(L);
2740 }
2741
2742
2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2744 if (reachable(src1)) {
2745 cmpb(as_Address(src1), imm);
2746 } else {
2747 lea(rscratch1, src1);
2748 cmpb(Address(rscratch1, 0), imm);
2749 }
2750 }
2751
2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2753 #ifdef _LP64
2754 if (src2.is_lval()) {
2755 movptr(rscratch1, src2);
2756 Assembler::cmpq(src1, rscratch1);
2757 } else if (reachable(src2)) {
2758 cmpq(src1, as_Address(src2));
2759 } else {
2760 lea(rscratch1, src2);
2761 Assembler::cmpq(src1, Address(rscratch1, 0));
2762 }
2763 #else
2764 if (src2.is_lval()) {
2765 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2766 } else {
2767 cmpl(src1, as_Address(src2));
2768 }
2769 #endif // _LP64
2770 }
2771
2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2773 assert(src2.is_lval(), "not a mem-mem compare");
2774 #ifdef _LP64
2775 // moves src2's literal address
2776 movptr(rscratch1, src2);
2777 Assembler::cmpq(src1, rscratch1);
2778 #else
2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 #endif // _LP64
2781 }
2782
2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2784 if (reachable(adr)) {
2785 if (os::is_MP())
2786 lock();
2787 cmpxchgptr(reg, as_Address(adr));
2788 } else {
2789 lea(rscratch1, adr);
2790 if (os::is_MP())
2791 lock();
2792 cmpxchgptr(reg, Address(rscratch1, 0));
2793 }
2794 }
2795
2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2797 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2798 }
2799
2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2801 if (reachable(src)) {
2802 Assembler::comisd(dst, as_Address(src));
2803 } else {
2804 lea(rscratch1, src);
2805 Assembler::comisd(dst, Address(rscratch1, 0));
2806 }
2807 }
2808
2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2810 if (reachable(src)) {
2811 Assembler::comiss(dst, as_Address(src));
2812 } else {
2813 lea(rscratch1, src);
2814 Assembler::comiss(dst, Address(rscratch1, 0));
2815 }
2816 }
2817
2818
2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2820 Condition negated_cond = negate_condition(cond);
2821 Label L;
2822 jcc(negated_cond, L);
2823 pushf(); // Preserve flags
2824 atomic_incl(counter_addr);
2825 popf();
2826 bind(L);
2827 }
2828
2829 int MacroAssembler::corrected_idivl(Register reg) {
2830 // Full implementation of Java idiv and irem; checks for
2831 // special case as described in JVM spec., p.243 & p.271.
2832 // The function returns the (pc) offset of the idivl
2833 // instruction - may be needed for implicit exceptions.
2834 //
2835 // normal case special case
2836 //
2837 // input : rax,: dividend min_int
2838 // reg: divisor (may not be rax,/rdx) -1
2839 //
2840 // output: rax,: quotient (= rax, idiv reg) min_int
2841 // rdx: remainder (= rax, irem reg) 0
2842 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2843 const int min_int = 0x80000000;
2844 Label normal_case, special_case;
2845
2846 // check for special case
2847 cmpl(rax, min_int);
2848 jcc(Assembler::notEqual, normal_case);
2849 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2850 cmpl(reg, -1);
2851 jcc(Assembler::equal, special_case);
2852
2853 // handle normal case
2854 bind(normal_case);
2855 cdql();
2856 int idivl_offset = offset();
2857 idivl(reg);
2858
2859 // normal and special case exit
2860 bind(special_case);
2861
2862 return idivl_offset;
2863 }
2864
2865
2866
2867 void MacroAssembler::decrementl(Register reg, int value) {
2868 if (value == min_jint) {subl(reg, value) ; return; }
2869 if (value < 0) { incrementl(reg, -value); return; }
2870 if (value == 0) { ; return; }
2871 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2872 /* else */ { subl(reg, value) ; return; }
2873 }
2874
2875 void MacroAssembler::decrementl(Address dst, int value) {
2876 if (value == min_jint) {subl(dst, value) ; return; }
2877 if (value < 0) { incrementl(dst, -value); return; }
2878 if (value == 0) { ; return; }
2879 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2880 /* else */ { subl(dst, value) ; return; }
2881 }
2882
2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2884 assert (shift_value > 0, "illegal shift value");
2885 Label _is_positive;
2886 testl (reg, reg);
2887 jcc (Assembler::positive, _is_positive);
2888 int offset = (1 << shift_value) - 1 ;
2889
2890 if (offset == 1) {
2891 incrementl(reg);
2892 } else {
2893 addl(reg, offset);
2894 }
2895
2896 bind (_is_positive);
2897 sarl(reg, shift_value);
2898 }
2899
2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2901 if (reachable(src)) {
2902 Assembler::divsd(dst, as_Address(src));
2903 } else {
2904 lea(rscratch1, src);
2905 Assembler::divsd(dst, Address(rscratch1, 0));
2906 }
2907 }
2908
2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2910 if (reachable(src)) {
2911 Assembler::divss(dst, as_Address(src));
2912 } else {
2913 lea(rscratch1, src);
2914 Assembler::divss(dst, Address(rscratch1, 0));
2915 }
2916 }
2917
2918 // !defined(COMPILER2) is because of stupid core builds
2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2920 void MacroAssembler::empty_FPU_stack() {
2921 if (VM_Version::supports_mmx()) {
2922 emms();
2923 } else {
2924 for (int i = 8; i-- > 0; ) ffree(i);
2925 }
2926 }
2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2928
2929
2930 // Defines obj, preserves var_size_in_bytes
2931 void MacroAssembler::eden_allocate(Register obj,
2932 Register var_size_in_bytes,
2933 int con_size_in_bytes,
2934 Register t1,
2935 Label& slow_case) {
2936 assert(obj == rax, "obj must be in rax, for cmpxchg");
2937 assert_different_registers(obj, var_size_in_bytes, t1);
2938 if (!Universe::heap()->supports_inline_contig_alloc()) {
2939 jmp(slow_case);
2940 } else {
2941 Register end = t1;
2942 Label retry;
2943 bind(retry);
2944 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2945 movptr(obj, heap_top);
2946 if (var_size_in_bytes == noreg) {
2947 lea(end, Address(obj, con_size_in_bytes));
2948 } else {
2949 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2950 }
2951 // if end < obj then we wrapped around => object too long => slow case
2952 cmpptr(end, obj);
2953 jcc(Assembler::below, slow_case);
2954 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2955 jcc(Assembler::above, slow_case);
2956 // Compare obj with the top addr, and if still equal, store the new top addr in
2957 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2958 // it otherwise. Use lock prefix for atomicity on MPs.
2959 locked_cmpxchgptr(end, heap_top);
2960 jcc(Assembler::notEqual, retry);
2961 }
2962 }
2963
2964 void MacroAssembler::enter() {
2965 push(rbp);
2966 mov(rbp, rsp);
2967 }
2968
2969 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2970 void MacroAssembler::fat_nop() {
2971 if (UseAddressNop) {
2972 addr_nop_5();
2973 } else {
2974 emit_int8(0x26); // es:
2975 emit_int8(0x2e); // cs:
2976 emit_int8(0x64); // fs:
2977 emit_int8(0x65); // gs:
2978 emit_int8((unsigned char)0x90);
2979 }
2980 }
2981
2982 void MacroAssembler::fcmp(Register tmp) {
2983 fcmp(tmp, 1, true, true);
2984 }
2985
2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2987 assert(!pop_right || pop_left, "usage error");
2988 if (VM_Version::supports_cmov()) {
2989 assert(tmp == noreg, "unneeded temp");
2990 if (pop_left) {
2991 fucomip(index);
2992 } else {
2993 fucomi(index);
2994 }
2995 if (pop_right) {
2996 fpop();
2997 }
2998 } else {
2999 assert(tmp != noreg, "need temp");
3000 if (pop_left) {
3001 if (pop_right) {
3002 fcompp();
3003 } else {
3004 fcomp(index);
3005 }
3006 } else {
3007 fcom(index);
3008 }
3009 // convert FPU condition into eflags condition via rax,
3010 save_rax(tmp);
3011 fwait(); fnstsw_ax();
3012 sahf();
3013 restore_rax(tmp);
3014 }
3015 // condition codes set as follows:
3016 //
3017 // CF (corresponds to C0) if x < y
3018 // PF (corresponds to C2) if unordered
3019 // ZF (corresponds to C3) if x = y
3020 }
3021
3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3023 fcmp2int(dst, unordered_is_less, 1, true, true);
3024 }
3025
3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3027 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3028 Label L;
3029 if (unordered_is_less) {
3030 movl(dst, -1);
3031 jcc(Assembler::parity, L);
3032 jcc(Assembler::below , L);
3033 movl(dst, 0);
3034 jcc(Assembler::equal , L);
3035 increment(dst);
3036 } else { // unordered is greater
3037 movl(dst, 1);
3038 jcc(Assembler::parity, L);
3039 jcc(Assembler::above , L);
3040 movl(dst, 0);
3041 jcc(Assembler::equal , L);
3042 decrementl(dst);
3043 }
3044 bind(L);
3045 }
3046
3047 void MacroAssembler::fld_d(AddressLiteral src) {
3048 fld_d(as_Address(src));
3049 }
3050
3051 void MacroAssembler::fld_s(AddressLiteral src) {
3052 fld_s(as_Address(src));
3053 }
3054
3055 void MacroAssembler::fld_x(AddressLiteral src) {
3056 Assembler::fld_x(as_Address(src));
3057 }
3058
3059 void MacroAssembler::fldcw(AddressLiteral src) {
3060 Assembler::fldcw(as_Address(src));
3061 }
3062
3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3064 if (reachable(src)) {
3065 Assembler::mulpd(dst, as_Address(src));
3066 } else {
3067 lea(rscratch1, src);
3068 Assembler::mulpd(dst, Address(rscratch1, 0));
3069 }
3070 }
3071
3072 void MacroAssembler::increase_precision() {
3073 subptr(rsp, BytesPerWord);
3074 fnstcw(Address(rsp, 0));
3075 movl(rax, Address(rsp, 0));
3076 orl(rax, 0x300);
3077 push(rax);
3078 fldcw(Address(rsp, 0));
3079 pop(rax);
3080 }
3081
3082 void MacroAssembler::restore_precision() {
3083 fldcw(Address(rsp, 0));
3084 addptr(rsp, BytesPerWord);
3085 }
3086
3087 void MacroAssembler::fpop() {
3088 ffree();
3089 fincstp();
3090 }
3091
3092 void MacroAssembler::load_float(Address src) {
3093 if (UseSSE >= 1) {
3094 movflt(xmm0, src);
3095 } else {
3096 LP64_ONLY(ShouldNotReachHere());
3097 NOT_LP64(fld_s(src));
3098 }
3099 }
3100
3101 void MacroAssembler::store_float(Address dst) {
3102 if (UseSSE >= 1) {
3103 movflt(dst, xmm0);
3104 } else {
3105 LP64_ONLY(ShouldNotReachHere());
3106 NOT_LP64(fstp_s(dst));
3107 }
3108 }
3109
3110 void MacroAssembler::load_double(Address src) {
3111 if (UseSSE >= 2) {
3112 movdbl(xmm0, src);
3113 } else {
3114 LP64_ONLY(ShouldNotReachHere());
3115 NOT_LP64(fld_d(src));
3116 }
3117 }
3118
3119 void MacroAssembler::store_double(Address dst) {
3120 if (UseSSE >= 2) {
3121 movdbl(dst, xmm0);
3122 } else {
3123 LP64_ONLY(ShouldNotReachHere());
3124 NOT_LP64(fstp_d(dst));
3125 }
3126 }
3127
3128 void MacroAssembler::fremr(Register tmp) {
3129 save_rax(tmp);
3130 { Label L;
3131 bind(L);
3132 fprem();
3133 fwait(); fnstsw_ax();
3134 #ifdef _LP64
3135 testl(rax, 0x400);
3136 jcc(Assembler::notEqual, L);
3137 #else
3138 sahf();
3139 jcc(Assembler::parity, L);
3140 #endif // _LP64
3141 }
3142 restore_rax(tmp);
3143 // Result is in ST0.
3144 // Note: fxch & fpop to get rid of ST1
3145 // (otherwise FPU stack could overflow eventually)
3146 fxch(1);
3147 fpop();
3148 }
3149
3150
3151 void MacroAssembler::incrementl(AddressLiteral dst) {
3152 if (reachable(dst)) {
3153 incrementl(as_Address(dst));
3154 } else {
3155 lea(rscratch1, dst);
3156 incrementl(Address(rscratch1, 0));
3157 }
3158 }
3159
3160 void MacroAssembler::incrementl(ArrayAddress dst) {
3161 incrementl(as_Address(dst));
3162 }
3163
3164 void MacroAssembler::incrementl(Register reg, int value) {
3165 if (value == min_jint) {addl(reg, value) ; return; }
3166 if (value < 0) { decrementl(reg, -value); return; }
3167 if (value == 0) { ; return; }
3168 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3169 /* else */ { addl(reg, value) ; return; }
3170 }
3171
3172 void MacroAssembler::incrementl(Address dst, int value) {
3173 if (value == min_jint) {addl(dst, value) ; return; }
3174 if (value < 0) { decrementl(dst, -value); return; }
3175 if (value == 0) { ; return; }
3176 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3177 /* else */ { addl(dst, value) ; return; }
3178 }
3179
3180 void MacroAssembler::jump(AddressLiteral dst) {
3181 if (reachable(dst)) {
3182 jmp_literal(dst.target(), dst.rspec());
3183 } else {
3184 lea(rscratch1, dst);
3185 jmp(rscratch1);
3186 }
3187 }
3188
3189 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3190 if (reachable(dst)) {
3191 InstructionMark im(this);
3192 relocate(dst.reloc());
3193 const int short_size = 2;
3194 const int long_size = 6;
3195 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3196 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3197 // 0111 tttn #8-bit disp
3198 emit_int8(0x70 | cc);
3199 emit_int8((offs - short_size) & 0xFF);
3200 } else {
3201 // 0000 1111 1000 tttn #32-bit disp
3202 emit_int8(0x0F);
3203 emit_int8((unsigned char)(0x80 | cc));
3204 emit_int32(offs - long_size);
3205 }
3206 } else {
3207 #ifdef ASSERT
3208 warning("reversing conditional branch");
3209 #endif /* ASSERT */
3210 Label skip;
3211 jccb(reverse[cc], skip);
3212 lea(rscratch1, dst);
3213 Assembler::jmp(rscratch1);
3214 bind(skip);
3215 }
3216 }
3217
3218 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3219 if (reachable(src)) {
3220 Assembler::ldmxcsr(as_Address(src));
3221 } else {
3222 lea(rscratch1, src);
3223 Assembler::ldmxcsr(Address(rscratch1, 0));
3224 }
3225 }
3226
3227 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3228 int off;
3229 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3230 off = offset();
3231 movsbl(dst, src); // movsxb
3232 } else {
3233 off = load_unsigned_byte(dst, src);
3234 shll(dst, 24);
3235 sarl(dst, 24);
3236 }
3237 return off;
3238 }
3239
3240 // Note: load_signed_short used to be called load_signed_word.
3241 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3242 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3243 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3244 int MacroAssembler::load_signed_short(Register dst, Address src) {
3245 int off;
3246 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3247 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3248 // version but this is what 64bit has always done. This seems to imply
3249 // that users are only using 32bits worth.
3250 off = offset();
3251 movswl(dst, src); // movsxw
3252 } else {
3253 off = load_unsigned_short(dst, src);
3254 shll(dst, 16);
3255 sarl(dst, 16);
3256 }
3257 return off;
3258 }
3259
3260 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3261 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3262 // and "3.9 Partial Register Penalties", p. 22).
3263 int off;
3264 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3265 off = offset();
3266 movzbl(dst, src); // movzxb
3267 } else {
3268 xorl(dst, dst);
3269 off = offset();
3270 movb(dst, src);
3271 }
3272 return off;
3273 }
3274
3275 // Note: load_unsigned_short used to be called load_unsigned_word.
3276 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3277 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3278 // and "3.9 Partial Register Penalties", p. 22).
3279 int off;
3280 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3281 off = offset();
3282 movzwl(dst, src); // movzxw
3283 } else {
3284 xorl(dst, dst);
3285 off = offset();
3286 movw(dst, src);
3287 }
3288 return off;
3289 }
3290
3291 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3292 switch (size_in_bytes) {
3293 #ifndef _LP64
3294 case 8:
3295 assert(dst2 != noreg, "second dest register required");
3296 movl(dst, src);
3297 movl(dst2, src.plus_disp(BytesPerInt));
3298 break;
3299 #else
3300 case 8: movq(dst, src); break;
3301 #endif
3302 case 4: movl(dst, src); break;
3303 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3304 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3305 default: ShouldNotReachHere();
3306 }
3307 }
3308
3309 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3310 switch (size_in_bytes) {
3311 #ifndef _LP64
3312 case 8:
3313 assert(src2 != noreg, "second source register required");
3314 movl(dst, src);
3315 movl(dst.plus_disp(BytesPerInt), src2);
3316 break;
3317 #else
3318 case 8: movq(dst, src); break;
3319 #endif
3320 case 4: movl(dst, src); break;
3321 case 2: movw(dst, src); break;
3322 case 1: movb(dst, src); break;
3323 default: ShouldNotReachHere();
3324 }
3325 }
3326
3327 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3328 if (reachable(dst)) {
3329 movl(as_Address(dst), src);
3330 } else {
3331 lea(rscratch1, dst);
3332 movl(Address(rscratch1, 0), src);
3333 }
3334 }
3335
3336 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3337 if (reachable(src)) {
3338 movl(dst, as_Address(src));
3339 } else {
3340 lea(rscratch1, src);
3341 movl(dst, Address(rscratch1, 0));
3342 }
3343 }
3344
3345 // C++ bool manipulation
3346
3347 void MacroAssembler::movbool(Register dst, Address src) {
3348 if(sizeof(bool) == 1)
3349 movb(dst, src);
3350 else if(sizeof(bool) == 2)
3351 movw(dst, src);
3352 else if(sizeof(bool) == 4)
3353 movl(dst, src);
3354 else
3355 // unsupported
3356 ShouldNotReachHere();
3357 }
3358
3359 void MacroAssembler::movbool(Address dst, bool boolconst) {
3360 if(sizeof(bool) == 1)
3361 movb(dst, (int) boolconst);
3362 else if(sizeof(bool) == 2)
3363 movw(dst, (int) boolconst);
3364 else if(sizeof(bool) == 4)
3365 movl(dst, (int) boolconst);
3366 else
3367 // unsupported
3368 ShouldNotReachHere();
3369 }
3370
3371 void MacroAssembler::movbool(Address dst, Register src) {
3372 if(sizeof(bool) == 1)
3373 movb(dst, src);
3374 else if(sizeof(bool) == 2)
3375 movw(dst, src);
3376 else if(sizeof(bool) == 4)
3377 movl(dst, src);
3378 else
3379 // unsupported
3380 ShouldNotReachHere();
3381 }
3382
3383 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3384 movb(as_Address(dst), src);
3385 }
3386
3387 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3388 if (reachable(src)) {
3389 movdl(dst, as_Address(src));
3390 } else {
3391 lea(rscratch1, src);
3392 movdl(dst, Address(rscratch1, 0));
3393 }
3394 }
3395
3396 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3397 if (reachable(src)) {
3398 movq(dst, as_Address(src));
3399 } else {
3400 lea(rscratch1, src);
3401 movq(dst, Address(rscratch1, 0));
3402 }
3403 }
3404
3405 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3406 if (reachable(src)) {
3407 if (UseXmmLoadAndClearUpper) {
3408 movsd (dst, as_Address(src));
3409 } else {
3410 movlpd(dst, as_Address(src));
3411 }
3412 } else {
3413 lea(rscratch1, src);
3414 if (UseXmmLoadAndClearUpper) {
3415 movsd (dst, Address(rscratch1, 0));
3416 } else {
3417 movlpd(dst, Address(rscratch1, 0));
3418 }
3419 }
3420 }
3421
3422 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3423 if (reachable(src)) {
3424 movss(dst, as_Address(src));
3425 } else {
3426 lea(rscratch1, src);
3427 movss(dst, Address(rscratch1, 0));
3428 }
3429 }
3430
3431 void MacroAssembler::movptr(Register dst, Register src) {
3432 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3433 }
3434
3435 void MacroAssembler::movptr(Register dst, Address src) {
3436 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3437 }
3438
3439 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3440 void MacroAssembler::movptr(Register dst, intptr_t src) {
3441 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3442 }
3443
3444 void MacroAssembler::movptr(Address dst, Register src) {
3445 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3446 }
3447
3448 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3449 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3450 Assembler::vextractf32x4h(dst, src, 0);
3451 } else {
3452 Assembler::movdqu(dst, src);
3453 }
3454 }
3455
3456 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3457 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3458 Assembler::vinsertf32x4h(dst, src, 0);
3459 } else {
3460 Assembler::movdqu(dst, src);
3461 }
3462 }
3463
3464 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3465 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3466 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3467 } else {
3468 Assembler::movdqu(dst, src);
3469 }
3470 }
3471
3472 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) {
3473 if (reachable(src)) {
3474 movdqu(dst, as_Address(src));
3475 } else {
3476 lea(rscratch1, src);
3477 movdqu(dst, Address(rscratch1, 0));
3478 }
3479 }
3480
3481 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3482 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3483 Assembler::vextractf64x4h(dst, src, 0);
3484 } else {
3485 Assembler::vmovdqu(dst, src);
3486 }
3487 }
3488
3489 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3490 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3491 Assembler::vinsertf64x4h(dst, src, 0);
3492 } else {
3493 Assembler::vmovdqu(dst, src);
3494 }
3495 }
3496
3497 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3498 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3499 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3500 }
3501 else {
3502 Assembler::vmovdqu(dst, src);
3503 }
3504 }
3505
3506 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3507 if (reachable(src)) {
3508 vmovdqu(dst, as_Address(src));
3509 }
3510 else {
3511 lea(rscratch1, src);
3512 vmovdqu(dst, Address(rscratch1, 0));
3513 }
3514 }
3515
3516 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3517 if (reachable(src)) {
3518 Assembler::movdqa(dst, as_Address(src));
3519 } else {
3520 lea(rscratch1, src);
3521 Assembler::movdqa(dst, Address(rscratch1, 0));
3522 }
3523 }
3524
3525 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3526 if (reachable(src)) {
3527 Assembler::movsd(dst, as_Address(src));
3528 } else {
3529 lea(rscratch1, src);
3530 Assembler::movsd(dst, Address(rscratch1, 0));
3531 }
3532 }
3533
3534 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3535 if (reachable(src)) {
3536 Assembler::movss(dst, as_Address(src));
3537 } else {
3538 lea(rscratch1, src);
3539 Assembler::movss(dst, Address(rscratch1, 0));
3540 }
3541 }
3542
3543 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3544 if (reachable(src)) {
3545 Assembler::mulsd(dst, as_Address(src));
3546 } else {
3547 lea(rscratch1, src);
3548 Assembler::mulsd(dst, Address(rscratch1, 0));
3549 }
3550 }
3551
3552 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3553 if (reachable(src)) {
3554 Assembler::mulss(dst, as_Address(src));
3555 } else {
3556 lea(rscratch1, src);
3557 Assembler::mulss(dst, Address(rscratch1, 0));
3558 }
3559 }
3560
3561 void MacroAssembler::null_check(Register reg, int offset) {
3562 if (needs_explicit_null_check(offset)) {
3563 // provoke OS NULL exception if reg = NULL by
3564 // accessing M[reg] w/o changing any (non-CC) registers
3565 // NOTE: cmpl is plenty here to provoke a segv
3566 cmpptr(rax, Address(reg, 0));
3567 // Note: should probably use testl(rax, Address(reg, 0));
3568 // may be shorter code (however, this version of
3569 // testl needs to be implemented first)
3570 } else {
3571 // nothing to do, (later) access of M[reg + offset]
3572 // will provoke OS NULL exception if reg = NULL
3573 }
3574 }
3575
3576 void MacroAssembler::os_breakpoint() {
3577 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3578 // (e.g., MSVC can't call ps() otherwise)
3579 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3580 }
3581
3582 #ifdef _LP64
3583 #define XSTATE_BV 0x200
3584 #endif
3585
3586 void MacroAssembler::pop_CPU_state() {
3587 pop_FPU_state();
3588 pop_IU_state();
3589 }
3590
3591 void MacroAssembler::pop_FPU_state() {
3592 #ifndef _LP64
3593 frstor(Address(rsp, 0));
3594 #else
3595 fxrstor(Address(rsp, 0));
3596 #endif
3597 addptr(rsp, FPUStateSizeInWords * wordSize);
3598 }
3599
3600 void MacroAssembler::pop_IU_state() {
3601 popa();
3602 LP64_ONLY(addq(rsp, 8));
3603 popf();
3604 }
3605
3606 // Save Integer and Float state
3607 // Warning: Stack must be 16 byte aligned (64bit)
3608 void MacroAssembler::push_CPU_state() {
3609 push_IU_state();
3610 push_FPU_state();
3611 }
3612
3613 void MacroAssembler::push_FPU_state() {
3614 subptr(rsp, FPUStateSizeInWords * wordSize);
3615 #ifndef _LP64
3616 fnsave(Address(rsp, 0));
3617 fwait();
3618 #else
3619 fxsave(Address(rsp, 0));
3620 #endif // LP64
3621 }
3622
3623 void MacroAssembler::push_IU_state() {
3624 // Push flags first because pusha kills them
3625 pushf();
3626 // Make sure rsp stays 16-byte aligned
3627 LP64_ONLY(subq(rsp, 8));
3628 pusha();
3629 }
3630
3631 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) {
3632 // determine java_thread register
3633 if (!java_thread->is_valid()) {
3634 java_thread = rdi;
3635 get_thread(java_thread);
3636 }
3637 // we must set sp to zero to clear frame
3638 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3639 if (clear_fp) {
3640 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3641 }
3642
3643 if (clear_pc)
3644 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3645
3646 }
3647
3648 void MacroAssembler::restore_rax(Register tmp) {
3649 if (tmp == noreg) pop(rax);
3650 else if (tmp != rax) mov(rax, tmp);
3651 }
3652
3653 void MacroAssembler::round_to(Register reg, int modulus) {
3654 addptr(reg, modulus - 1);
3655 andptr(reg, -modulus);
3656 }
3657
3658 void MacroAssembler::save_rax(Register tmp) {
3659 if (tmp == noreg) push(rax);
3660 else if (tmp != rax) mov(tmp, rax);
3661 }
3662
3663 // Write serialization page so VM thread can do a pseudo remote membar.
3664 // We use the current thread pointer to calculate a thread specific
3665 // offset to write to within the page. This minimizes bus traffic
3666 // due to cache line collision.
3667 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3668 movl(tmp, thread);
3669 shrl(tmp, os::get_serialize_page_shift_count());
3670 andl(tmp, (os::vm_page_size() - sizeof(int)));
3671
3672 Address index(noreg, tmp, Address::times_1);
3673 ExternalAddress page(os::get_memory_serialize_page());
3674
3675 // Size of store must match masking code above
3676 movl(as_Address(ArrayAddress(page, index)), tmp);
3677 }
3678
3679 // Calls to C land
3680 //
3681 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3682 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3683 // has to be reset to 0. This is required to allow proper stack traversal.
3684 void MacroAssembler::set_last_Java_frame(Register java_thread,
3685 Register last_java_sp,
3686 Register last_java_fp,
3687 address last_java_pc) {
3688 // determine java_thread register
3689 if (!java_thread->is_valid()) {
3690 java_thread = rdi;
3691 get_thread(java_thread);
3692 }
3693 // determine last_java_sp register
3694 if (!last_java_sp->is_valid()) {
3695 last_java_sp = rsp;
3696 }
3697
3698 // last_java_fp is optional
3699
3700 if (last_java_fp->is_valid()) {
3701 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3702 }
3703
3704 // last_java_pc is optional
3705
3706 if (last_java_pc != NULL) {
3707 lea(Address(java_thread,
3708 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3709 InternalAddress(last_java_pc));
3710
3711 }
3712 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3713 }
3714
3715 void MacroAssembler::shlptr(Register dst, int imm8) {
3716 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3717 }
3718
3719 void MacroAssembler::shrptr(Register dst, int imm8) {
3720 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3721 }
3722
3723 void MacroAssembler::sign_extend_byte(Register reg) {
3724 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3725 movsbl(reg, reg); // movsxb
3726 } else {
3727 shll(reg, 24);
3728 sarl(reg, 24);
3729 }
3730 }
3731
3732 void MacroAssembler::sign_extend_short(Register reg) {
3733 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3734 movswl(reg, reg); // movsxw
3735 } else {
3736 shll(reg, 16);
3737 sarl(reg, 16);
3738 }
3739 }
3740
3741 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3742 assert(reachable(src), "Address should be reachable");
3743 testl(dst, as_Address(src));
3744 }
3745
3746 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3747 int dst_enc = dst->encoding();
3748 int src_enc = src->encoding();
3749 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3750 Assembler::pcmpeqb(dst, src);
3751 } else if ((dst_enc < 16) && (src_enc < 16)) {
3752 Assembler::pcmpeqb(dst, src);
3753 } else if (src_enc < 16) {
3754 subptr(rsp, 64);
3755 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3756 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3757 Assembler::pcmpeqb(xmm0, src);
3758 movdqu(dst, xmm0);
3759 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3760 addptr(rsp, 64);
3761 } else if (dst_enc < 16) {
3762 subptr(rsp, 64);
3763 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3764 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3765 Assembler::pcmpeqb(dst, xmm0);
3766 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3767 addptr(rsp, 64);
3768 } else {
3769 subptr(rsp, 64);
3770 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3771 subptr(rsp, 64);
3772 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3773 movdqu(xmm0, src);
3774 movdqu(xmm1, dst);
3775 Assembler::pcmpeqb(xmm1, xmm0);
3776 movdqu(dst, xmm1);
3777 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3778 addptr(rsp, 64);
3779 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3780 addptr(rsp, 64);
3781 }
3782 }
3783
3784 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3785 int dst_enc = dst->encoding();
3786 int src_enc = src->encoding();
3787 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3788 Assembler::pcmpeqw(dst, src);
3789 } else if ((dst_enc < 16) && (src_enc < 16)) {
3790 Assembler::pcmpeqw(dst, src);
3791 } else if (src_enc < 16) {
3792 subptr(rsp, 64);
3793 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3794 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3795 Assembler::pcmpeqw(xmm0, src);
3796 movdqu(dst, xmm0);
3797 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3798 addptr(rsp, 64);
3799 } else if (dst_enc < 16) {
3800 subptr(rsp, 64);
3801 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3802 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3803 Assembler::pcmpeqw(dst, xmm0);
3804 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3805 addptr(rsp, 64);
3806 } else {
3807 subptr(rsp, 64);
3808 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3809 subptr(rsp, 64);
3810 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3811 movdqu(xmm0, src);
3812 movdqu(xmm1, dst);
3813 Assembler::pcmpeqw(xmm1, xmm0);
3814 movdqu(dst, xmm1);
3815 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3816 addptr(rsp, 64);
3817 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3818 addptr(rsp, 64);
3819 }
3820 }
3821
3822 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3823 int dst_enc = dst->encoding();
3824 if (dst_enc < 16) {
3825 Assembler::pcmpestri(dst, src, imm8);
3826 } else {
3827 subptr(rsp, 64);
3828 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3829 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3830 Assembler::pcmpestri(xmm0, src, imm8);
3831 movdqu(dst, xmm0);
3832 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3833 addptr(rsp, 64);
3834 }
3835 }
3836
3837 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3838 int dst_enc = dst->encoding();
3839 int src_enc = src->encoding();
3840 if ((dst_enc < 16) && (src_enc < 16)) {
3841 Assembler::pcmpestri(dst, src, imm8);
3842 } else if (src_enc < 16) {
3843 subptr(rsp, 64);
3844 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3845 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3846 Assembler::pcmpestri(xmm0, src, imm8);
3847 movdqu(dst, xmm0);
3848 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3849 addptr(rsp, 64);
3850 } else if (dst_enc < 16) {
3851 subptr(rsp, 64);
3852 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3853 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3854 Assembler::pcmpestri(dst, xmm0, imm8);
3855 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3856 addptr(rsp, 64);
3857 } else {
3858 subptr(rsp, 64);
3859 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3860 subptr(rsp, 64);
3861 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3862 movdqu(xmm0, src);
3863 movdqu(xmm1, dst);
3864 Assembler::pcmpestri(xmm1, xmm0, imm8);
3865 movdqu(dst, xmm1);
3866 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3867 addptr(rsp, 64);
3868 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3869 addptr(rsp, 64);
3870 }
3871 }
3872
3873 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3874 int dst_enc = dst->encoding();
3875 int src_enc = src->encoding();
3876 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3877 Assembler::pmovzxbw(dst, src);
3878 } else if ((dst_enc < 16) && (src_enc < 16)) {
3879 Assembler::pmovzxbw(dst, src);
3880 } else if (src_enc < 16) {
3881 subptr(rsp, 64);
3882 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3883 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3884 Assembler::pmovzxbw(xmm0, src);
3885 movdqu(dst, xmm0);
3886 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3887 addptr(rsp, 64);
3888 } else if (dst_enc < 16) {
3889 subptr(rsp, 64);
3890 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3891 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3892 Assembler::pmovzxbw(dst, xmm0);
3893 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3894 addptr(rsp, 64);
3895 } else {
3896 subptr(rsp, 64);
3897 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3898 subptr(rsp, 64);
3899 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3900 movdqu(xmm0, src);
3901 movdqu(xmm1, dst);
3902 Assembler::pmovzxbw(xmm1, xmm0);
3903 movdqu(dst, xmm1);
3904 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3905 addptr(rsp, 64);
3906 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3907 addptr(rsp, 64);
3908 }
3909 }
3910
3911 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3912 int dst_enc = dst->encoding();
3913 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3914 Assembler::pmovzxbw(dst, src);
3915 } else if (dst_enc < 16) {
3916 Assembler::pmovzxbw(dst, src);
3917 } else {
3918 subptr(rsp, 64);
3919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3920 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3921 Assembler::pmovzxbw(xmm0, src);
3922 movdqu(dst, xmm0);
3923 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3924 addptr(rsp, 64);
3925 }
3926 }
3927
3928 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3929 int src_enc = src->encoding();
3930 if (src_enc < 16) {
3931 Assembler::pmovmskb(dst, src);
3932 } else {
3933 subptr(rsp, 64);
3934 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3935 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3936 Assembler::pmovmskb(dst, xmm0);
3937 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3938 addptr(rsp, 64);
3939 }
3940 }
3941
3942 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3943 int dst_enc = dst->encoding();
3944 int src_enc = src->encoding();
3945 if ((dst_enc < 16) && (src_enc < 16)) {
3946 Assembler::ptest(dst, src);
3947 } else if (src_enc < 16) {
3948 subptr(rsp, 64);
3949 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3950 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3951 Assembler::ptest(xmm0, src);
3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3953 addptr(rsp, 64);
3954 } else if (dst_enc < 16) {
3955 subptr(rsp, 64);
3956 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3957 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3958 Assembler::ptest(dst, xmm0);
3959 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3960 addptr(rsp, 64);
3961 } else {
3962 subptr(rsp, 64);
3963 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3964 subptr(rsp, 64);
3965 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3966 movdqu(xmm0, src);
3967 movdqu(xmm1, dst);
3968 Assembler::ptest(xmm1, xmm0);
3969 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3970 addptr(rsp, 64);
3971 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3972 addptr(rsp, 64);
3973 }
3974 }
3975
3976 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3977 if (reachable(src)) {
3978 Assembler::sqrtsd(dst, as_Address(src));
3979 } else {
3980 lea(rscratch1, src);
3981 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3982 }
3983 }
3984
3985 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3986 if (reachable(src)) {
3987 Assembler::sqrtss(dst, as_Address(src));
3988 } else {
3989 lea(rscratch1, src);
3990 Assembler::sqrtss(dst, Address(rscratch1, 0));
3991 }
3992 }
3993
3994 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3995 if (reachable(src)) {
3996 Assembler::subsd(dst, as_Address(src));
3997 } else {
3998 lea(rscratch1, src);
3999 Assembler::subsd(dst, Address(rscratch1, 0));
4000 }
4001 }
4002
4003 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4004 if (reachable(src)) {
4005 Assembler::subss(dst, as_Address(src));
4006 } else {
4007 lea(rscratch1, src);
4008 Assembler::subss(dst, Address(rscratch1, 0));
4009 }
4010 }
4011
4012 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4013 if (reachable(src)) {
4014 Assembler::ucomisd(dst, as_Address(src));
4015 } else {
4016 lea(rscratch1, src);
4017 Assembler::ucomisd(dst, Address(rscratch1, 0));
4018 }
4019 }
4020
4021 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4022 if (reachable(src)) {
4023 Assembler::ucomiss(dst, as_Address(src));
4024 } else {
4025 lea(rscratch1, src);
4026 Assembler::ucomiss(dst, Address(rscratch1, 0));
4027 }
4028 }
4029
4030 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4031 // Used in sign-bit flipping with aligned address.
4032 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4033 if (reachable(src)) {
4034 Assembler::xorpd(dst, as_Address(src));
4035 } else {
4036 lea(rscratch1, src);
4037 Assembler::xorpd(dst, Address(rscratch1, 0));
4038 }
4039 }
4040
4041 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4042 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4043 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4044 }
4045 else {
4046 Assembler::xorpd(dst, src);
4047 }
4048 }
4049
4050 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4051 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4052 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4053 } else {
4054 Assembler::xorps(dst, src);
4055 }
4056 }
4057
4058 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4059 // Used in sign-bit flipping with aligned address.
4060 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4061 if (reachable(src)) {
4062 Assembler::xorps(dst, as_Address(src));
4063 } else {
4064 lea(rscratch1, src);
4065 Assembler::xorps(dst, Address(rscratch1, 0));
4066 }
4067 }
4068
4069 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4070 // Used in sign-bit flipping with aligned address.
4071 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4072 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4073 if (reachable(src)) {
4074 Assembler::pshufb(dst, as_Address(src));
4075 } else {
4076 lea(rscratch1, src);
4077 Assembler::pshufb(dst, Address(rscratch1, 0));
4078 }
4079 }
4080
4081 // AVX 3-operands instructions
4082
4083 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4084 if (reachable(src)) {
4085 vaddsd(dst, nds, as_Address(src));
4086 } else {
4087 lea(rscratch1, src);
4088 vaddsd(dst, nds, Address(rscratch1, 0));
4089 }
4090 }
4091
4092 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4093 if (reachable(src)) {
4094 vaddss(dst, nds, as_Address(src));
4095 } else {
4096 lea(rscratch1, src);
4097 vaddss(dst, nds, Address(rscratch1, 0));
4098 }
4099 }
4100
4101 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4102 int dst_enc = dst->encoding();
4103 int nds_enc = nds->encoding();
4104 int src_enc = src->encoding();
4105 if ((dst_enc < 16) && (nds_enc < 16)) {
4106 vandps(dst, nds, negate_field, vector_len);
4107 } else if ((src_enc < 16) && (dst_enc < 16)) {
4108 movss(src, nds);
4109 vandps(dst, src, negate_field, vector_len);
4110 } else if (src_enc < 16) {
4111 movss(src, nds);
4112 vandps(src, src, negate_field, vector_len);
4113 movss(dst, src);
4114 } else if (dst_enc < 16) {
4115 movdqu(src, xmm0);
4116 movss(xmm0, nds);
4117 vandps(dst, xmm0, negate_field, vector_len);
4118 movdqu(xmm0, src);
4119 } else if (nds_enc < 16) {
4120 movdqu(src, xmm0);
4121 vandps(xmm0, nds, negate_field, vector_len);
4122 movss(dst, xmm0);
4123 movdqu(xmm0, src);
4124 } else {
4125 movdqu(src, xmm0);
4126 movss(xmm0, nds);
4127 vandps(xmm0, xmm0, negate_field, vector_len);
4128 movss(dst, xmm0);
4129 movdqu(xmm0, src);
4130 }
4131 }
4132
4133 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4134 int dst_enc = dst->encoding();
4135 int nds_enc = nds->encoding();
4136 int src_enc = src->encoding();
4137 if ((dst_enc < 16) && (nds_enc < 16)) {
4138 vandpd(dst, nds, negate_field, vector_len);
4139 } else if ((src_enc < 16) && (dst_enc < 16)) {
4140 movsd(src, nds);
4141 vandpd(dst, src, negate_field, vector_len);
4142 } else if (src_enc < 16) {
4143 movsd(src, nds);
4144 vandpd(src, src, negate_field, vector_len);
4145 movsd(dst, src);
4146 } else if (dst_enc < 16) {
4147 movdqu(src, xmm0);
4148 movsd(xmm0, nds);
4149 vandpd(dst, xmm0, negate_field, vector_len);
4150 movdqu(xmm0, src);
4151 } else if (nds_enc < 16) {
4152 movdqu(src, xmm0);
4153 vandpd(xmm0, nds, negate_field, vector_len);
4154 movsd(dst, xmm0);
4155 movdqu(xmm0, src);
4156 } else {
4157 movdqu(src, xmm0);
4158 movsd(xmm0, nds);
4159 vandpd(xmm0, xmm0, negate_field, vector_len);
4160 movsd(dst, xmm0);
4161 movdqu(xmm0, src);
4162 }
4163 }
4164
4165 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4166 int dst_enc = dst->encoding();
4167 int nds_enc = nds->encoding();
4168 int src_enc = src->encoding();
4169 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4170 Assembler::vpaddb(dst, nds, src, vector_len);
4171 } else if ((dst_enc < 16) && (src_enc < 16)) {
4172 Assembler::vpaddb(dst, dst, src, vector_len);
4173 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4174 // use nds as scratch for src
4175 evmovdqul(nds, src, Assembler::AVX_512bit);
4176 Assembler::vpaddb(dst, dst, nds, vector_len);
4177 } else if ((src_enc < 16) && (nds_enc < 16)) {
4178 // use nds as scratch for dst
4179 evmovdqul(nds, dst, Assembler::AVX_512bit);
4180 Assembler::vpaddb(nds, nds, src, vector_len);
4181 evmovdqul(dst, nds, Assembler::AVX_512bit);
4182 } else if (dst_enc < 16) {
4183 // use nds as scatch for xmm0 to hold src
4184 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4185 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4186 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4187 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4188 } else {
4189 // worse case scenario, all regs are in the upper bank
4190 subptr(rsp, 64);
4191 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4192 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4193 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4194 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4195 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4196 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4197 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4198 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4199 addptr(rsp, 64);
4200 }
4201 }
4202
4203 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4204 int dst_enc = dst->encoding();
4205 int nds_enc = nds->encoding();
4206 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4207 Assembler::vpaddb(dst, nds, src, vector_len);
4208 } else if (dst_enc < 16) {
4209 Assembler::vpaddb(dst, dst, src, vector_len);
4210 } else if (nds_enc < 16) {
4211 // implies dst_enc in upper bank with src as scratch
4212 evmovdqul(nds, dst, Assembler::AVX_512bit);
4213 Assembler::vpaddb(nds, nds, src, vector_len);
4214 evmovdqul(dst, nds, Assembler::AVX_512bit);
4215 } else {
4216 // worse case scenario, all regs in upper bank
4217 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4218 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4219 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4220 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4221 }
4222 }
4223
4224 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4225 int dst_enc = dst->encoding();
4226 int nds_enc = nds->encoding();
4227 int src_enc = src->encoding();
4228 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4229 Assembler::vpaddw(dst, nds, src, vector_len);
4230 } else if ((dst_enc < 16) && (src_enc < 16)) {
4231 Assembler::vpaddw(dst, dst, src, vector_len);
4232 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4233 // use nds as scratch for src
4234 evmovdqul(nds, src, Assembler::AVX_512bit);
4235 Assembler::vpaddw(dst, dst, nds, vector_len);
4236 } else if ((src_enc < 16) && (nds_enc < 16)) {
4237 // use nds as scratch for dst
4238 evmovdqul(nds, dst, Assembler::AVX_512bit);
4239 Assembler::vpaddw(nds, nds, src, vector_len);
4240 evmovdqul(dst, nds, Assembler::AVX_512bit);
4241 } else if (dst_enc < 16) {
4242 // use nds as scatch for xmm0 to hold src
4243 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4244 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4245 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4246 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4247 } else {
4248 // worse case scenario, all regs are in the upper bank
4249 subptr(rsp, 64);
4250 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4251 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4252 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4253 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4254 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4255 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4256 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4257 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4258 addptr(rsp, 64);
4259 }
4260 }
4261
4262 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4263 int dst_enc = dst->encoding();
4264 int nds_enc = nds->encoding();
4265 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4266 Assembler::vpaddw(dst, nds, src, vector_len);
4267 } else if (dst_enc < 16) {
4268 Assembler::vpaddw(dst, dst, src, vector_len);
4269 } else if (nds_enc < 16) {
4270 // implies dst_enc in upper bank with src as scratch
4271 evmovdqul(nds, dst, Assembler::AVX_512bit);
4272 Assembler::vpaddw(nds, nds, src, vector_len);
4273 evmovdqul(dst, nds, Assembler::AVX_512bit);
4274 } else {
4275 // worse case scenario, all regs in upper bank
4276 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4277 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4278 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4279 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4280 }
4281 }
4282
4283 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4284 int dst_enc = dst->encoding();
4285 int src_enc = src->encoding();
4286 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4287 Assembler::vpbroadcastw(dst, src);
4288 } else if ((dst_enc < 16) && (src_enc < 16)) {
4289 Assembler::vpbroadcastw(dst, src);
4290 } else if (src_enc < 16) {
4291 subptr(rsp, 64);
4292 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4293 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4294 Assembler::vpbroadcastw(xmm0, src);
4295 movdqu(dst, xmm0);
4296 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4297 addptr(rsp, 64);
4298 } else if (dst_enc < 16) {
4299 subptr(rsp, 64);
4300 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4301 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4302 Assembler::vpbroadcastw(dst, xmm0);
4303 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4304 addptr(rsp, 64);
4305 } else {
4306 subptr(rsp, 64);
4307 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4308 subptr(rsp, 64);
4309 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4310 movdqu(xmm0, src);
4311 movdqu(xmm1, dst);
4312 Assembler::vpbroadcastw(xmm1, xmm0);
4313 movdqu(dst, xmm1);
4314 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4315 addptr(rsp, 64);
4316 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4317 addptr(rsp, 64);
4318 }
4319 }
4320
4321 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4322 int dst_enc = dst->encoding();
4323 int nds_enc = nds->encoding();
4324 int src_enc = src->encoding();
4325 assert(dst_enc == nds_enc, "");
4326 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4327 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4328 } else if ((dst_enc < 16) && (src_enc < 16)) {
4329 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4330 } else if (src_enc < 16) {
4331 subptr(rsp, 64);
4332 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4333 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4334 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4335 movdqu(dst, xmm0);
4336 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4337 addptr(rsp, 64);
4338 } else if (dst_enc < 16) {
4339 subptr(rsp, 64);
4340 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4341 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4342 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4343 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4344 addptr(rsp, 64);
4345 } else {
4346 subptr(rsp, 64);
4347 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4348 subptr(rsp, 64);
4349 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4350 movdqu(xmm0, src);
4351 movdqu(xmm1, dst);
4352 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4353 movdqu(dst, xmm1);
4354 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4355 addptr(rsp, 64);
4356 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4357 addptr(rsp, 64);
4358 }
4359 }
4360
4361 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4362 int dst_enc = dst->encoding();
4363 int nds_enc = nds->encoding();
4364 int src_enc = src->encoding();
4365 assert(dst_enc == nds_enc, "");
4366 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4367 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4368 } else if ((dst_enc < 16) && (src_enc < 16)) {
4369 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4370 } else if (src_enc < 16) {
4371 subptr(rsp, 64);
4372 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4373 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4374 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4375 movdqu(dst, xmm0);
4376 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4377 addptr(rsp, 64);
4378 } else if (dst_enc < 16) {
4379 subptr(rsp, 64);
4380 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4381 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4382 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4383 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4384 addptr(rsp, 64);
4385 } else {
4386 subptr(rsp, 64);
4387 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4388 subptr(rsp, 64);
4389 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4390 movdqu(xmm0, src);
4391 movdqu(xmm1, dst);
4392 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4393 movdqu(dst, xmm1);
4394 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4395 addptr(rsp, 64);
4396 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4397 addptr(rsp, 64);
4398 }
4399 }
4400
4401 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4402 int dst_enc = dst->encoding();
4403 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4404 Assembler::vpmovzxbw(dst, src, vector_len);
4405 } else if (dst_enc < 16) {
4406 Assembler::vpmovzxbw(dst, src, vector_len);
4407 } else {
4408 subptr(rsp, 64);
4409 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4410 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4411 Assembler::vpmovzxbw(xmm0, src, vector_len);
4412 movdqu(dst, xmm0);
4413 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4414 addptr(rsp, 64);
4415 }
4416 }
4417
4418 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4419 int src_enc = src->encoding();
4420 if (src_enc < 16) {
4421 Assembler::vpmovmskb(dst, src);
4422 } else {
4423 subptr(rsp, 64);
4424 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4425 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4426 Assembler::vpmovmskb(dst, xmm0);
4427 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4428 addptr(rsp, 64);
4429 }
4430 }
4431
4432 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4433 int dst_enc = dst->encoding();
4434 int nds_enc = nds->encoding();
4435 int src_enc = src->encoding();
4436 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4437 Assembler::vpmullw(dst, nds, src, vector_len);
4438 } else if ((dst_enc < 16) && (src_enc < 16)) {
4439 Assembler::vpmullw(dst, dst, src, vector_len);
4440 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4441 // use nds as scratch for src
4442 evmovdqul(nds, src, Assembler::AVX_512bit);
4443 Assembler::vpmullw(dst, dst, nds, vector_len);
4444 } else if ((src_enc < 16) && (nds_enc < 16)) {
4445 // use nds as scratch for dst
4446 evmovdqul(nds, dst, Assembler::AVX_512bit);
4447 Assembler::vpmullw(nds, nds, src, vector_len);
4448 evmovdqul(dst, nds, Assembler::AVX_512bit);
4449 } else if (dst_enc < 16) {
4450 // use nds as scatch for xmm0 to hold src
4451 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4452 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4453 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4454 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4455 } else {
4456 // worse case scenario, all regs are in the upper bank
4457 subptr(rsp, 64);
4458 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4459 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4460 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4461 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4462 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4463 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4464 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4465 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4466 addptr(rsp, 64);
4467 }
4468 }
4469
4470 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4471 int dst_enc = dst->encoding();
4472 int nds_enc = nds->encoding();
4473 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4474 Assembler::vpmullw(dst, nds, src, vector_len);
4475 } else if (dst_enc < 16) {
4476 Assembler::vpmullw(dst, dst, src, vector_len);
4477 } else if (nds_enc < 16) {
4478 // implies dst_enc in upper bank with src as scratch
4479 evmovdqul(nds, dst, Assembler::AVX_512bit);
4480 Assembler::vpmullw(nds, nds, src, vector_len);
4481 evmovdqul(dst, nds, Assembler::AVX_512bit);
4482 } else {
4483 // worse case scenario, all regs in upper bank
4484 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4485 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4486 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4487 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4488 }
4489 }
4490
4491 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4492 int dst_enc = dst->encoding();
4493 int nds_enc = nds->encoding();
4494 int src_enc = src->encoding();
4495 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4496 Assembler::vpsubb(dst, nds, src, vector_len);
4497 } else if ((dst_enc < 16) && (src_enc < 16)) {
4498 Assembler::vpsubb(dst, dst, src, vector_len);
4499 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4500 // use nds as scratch for src
4501 evmovdqul(nds, src, Assembler::AVX_512bit);
4502 Assembler::vpsubb(dst, dst, nds, vector_len);
4503 } else if ((src_enc < 16) && (nds_enc < 16)) {
4504 // use nds as scratch for dst
4505 evmovdqul(nds, dst, Assembler::AVX_512bit);
4506 Assembler::vpsubb(nds, nds, src, vector_len);
4507 evmovdqul(dst, nds, Assembler::AVX_512bit);
4508 } else if (dst_enc < 16) {
4509 // use nds as scatch for xmm0 to hold src
4510 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4511 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4512 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4513 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4514 } else {
4515 // worse case scenario, all regs are in the upper bank
4516 subptr(rsp, 64);
4517 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4518 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4519 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4520 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4521 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4522 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4523 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4524 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4525 addptr(rsp, 64);
4526 }
4527 }
4528
4529 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4530 int dst_enc = dst->encoding();
4531 int nds_enc = nds->encoding();
4532 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4533 Assembler::vpsubb(dst, nds, src, vector_len);
4534 } else if (dst_enc < 16) {
4535 Assembler::vpsubb(dst, dst, src, vector_len);
4536 } else if (nds_enc < 16) {
4537 // implies dst_enc in upper bank with src as scratch
4538 evmovdqul(nds, dst, Assembler::AVX_512bit);
4539 Assembler::vpsubb(nds, nds, src, vector_len);
4540 evmovdqul(dst, nds, Assembler::AVX_512bit);
4541 } else {
4542 // worse case scenario, all regs in upper bank
4543 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4544 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4545 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4546 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4547 }
4548 }
4549
4550 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4551 int dst_enc = dst->encoding();
4552 int nds_enc = nds->encoding();
4553 int src_enc = src->encoding();
4554 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4555 Assembler::vpsubw(dst, nds, src, vector_len);
4556 } else if ((dst_enc < 16) && (src_enc < 16)) {
4557 Assembler::vpsubw(dst, dst, src, vector_len);
4558 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4559 // use nds as scratch for src
4560 evmovdqul(nds, src, Assembler::AVX_512bit);
4561 Assembler::vpsubw(dst, dst, nds, vector_len);
4562 } else if ((src_enc < 16) && (nds_enc < 16)) {
4563 // use nds as scratch for dst
4564 evmovdqul(nds, dst, Assembler::AVX_512bit);
4565 Assembler::vpsubw(nds, nds, src, vector_len);
4566 evmovdqul(dst, nds, Assembler::AVX_512bit);
4567 } else if (dst_enc < 16) {
4568 // use nds as scatch for xmm0 to hold src
4569 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4570 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4571 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4572 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4573 } else {
4574 // worse case scenario, all regs are in the upper bank
4575 subptr(rsp, 64);
4576 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4577 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4578 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4579 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4580 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4581 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4582 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4583 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4584 addptr(rsp, 64);
4585 }
4586 }
4587
4588 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4589 int dst_enc = dst->encoding();
4590 int nds_enc = nds->encoding();
4591 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4592 Assembler::vpsubw(dst, nds, src, vector_len);
4593 } else if (dst_enc < 16) {
4594 Assembler::vpsubw(dst, dst, src, vector_len);
4595 } else if (nds_enc < 16) {
4596 // implies dst_enc in upper bank with src as scratch
4597 evmovdqul(nds, dst, Assembler::AVX_512bit);
4598 Assembler::vpsubw(nds, nds, src, vector_len);
4599 evmovdqul(dst, nds, Assembler::AVX_512bit);
4600 } else {
4601 // worse case scenario, all regs in upper bank
4602 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4603 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4604 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4605 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4606 }
4607 }
4608
4609 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4610 int dst_enc = dst->encoding();
4611 int nds_enc = nds->encoding();
4612 int shift_enc = shift->encoding();
4613 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4614 Assembler::vpsraw(dst, nds, shift, vector_len);
4615 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4616 Assembler::vpsraw(dst, dst, shift, vector_len);
4617 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4618 // use nds_enc as scratch with shift
4619 evmovdqul(nds, shift, Assembler::AVX_512bit);
4620 Assembler::vpsraw(dst, dst, nds, vector_len);
4621 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4622 // use nds as scratch with dst
4623 evmovdqul(nds, dst, Assembler::AVX_512bit);
4624 Assembler::vpsraw(nds, nds, shift, vector_len);
4625 evmovdqul(dst, nds, Assembler::AVX_512bit);
4626 } else if (dst_enc < 16) {
4627 // use nds to save a copy of xmm0 and hold shift
4628 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4629 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4630 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4631 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4632 } else if (nds_enc < 16) {
4633 // use nds as dest as temps
4634 evmovdqul(nds, dst, Assembler::AVX_512bit);
4635 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4636 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4637 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4638 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4639 evmovdqul(dst, nds, Assembler::AVX_512bit);
4640 } else {
4641 // worse case scenario, all regs are in the upper bank
4642 subptr(rsp, 64);
4643 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4644 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4645 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4646 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4647 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4648 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4649 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4650 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4651 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4652 addptr(rsp, 64);
4653 }
4654 }
4655
4656 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4657 int dst_enc = dst->encoding();
4658 int nds_enc = nds->encoding();
4659 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4660 Assembler::vpsraw(dst, nds, shift, vector_len);
4661 } else if (dst_enc < 16) {
4662 Assembler::vpsraw(dst, dst, shift, vector_len);
4663 } else if (nds_enc < 16) {
4664 // use nds as scratch
4665 evmovdqul(nds, dst, Assembler::AVX_512bit);
4666 Assembler::vpsraw(nds, nds, shift, vector_len);
4667 evmovdqul(dst, nds, Assembler::AVX_512bit);
4668 } else {
4669 // use nds as scratch for xmm0
4670 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4671 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4672 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4673 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4674 }
4675 }
4676
4677 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4678 int dst_enc = dst->encoding();
4679 int nds_enc = nds->encoding();
4680 int shift_enc = shift->encoding();
4681 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4682 Assembler::vpsrlw(dst, nds, shift, vector_len);
4683 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4684 Assembler::vpsrlw(dst, dst, shift, vector_len);
4685 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4686 // use nds_enc as scratch with shift
4687 evmovdqul(nds, shift, Assembler::AVX_512bit);
4688 Assembler::vpsrlw(dst, dst, nds, vector_len);
4689 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4690 // use nds as scratch with dst
4691 evmovdqul(nds, dst, Assembler::AVX_512bit);
4692 Assembler::vpsrlw(nds, nds, shift, vector_len);
4693 evmovdqul(dst, nds, Assembler::AVX_512bit);
4694 } else if (dst_enc < 16) {
4695 // use nds to save a copy of xmm0 and hold shift
4696 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4697 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4698 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4699 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4700 } else if (nds_enc < 16) {
4701 // use nds as dest as temps
4702 evmovdqul(nds, dst, Assembler::AVX_512bit);
4703 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4704 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4705 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4706 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4707 evmovdqul(dst, nds, Assembler::AVX_512bit);
4708 } else {
4709 // worse case scenario, all regs are in the upper bank
4710 subptr(rsp, 64);
4711 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4712 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4713 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4714 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4715 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4716 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4717 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4718 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4719 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4720 addptr(rsp, 64);
4721 }
4722 }
4723
4724 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4725 int dst_enc = dst->encoding();
4726 int nds_enc = nds->encoding();
4727 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4728 Assembler::vpsrlw(dst, nds, shift, vector_len);
4729 } else if (dst_enc < 16) {
4730 Assembler::vpsrlw(dst, dst, shift, vector_len);
4731 } else if (nds_enc < 16) {
4732 // use nds as scratch
4733 evmovdqul(nds, dst, Assembler::AVX_512bit);
4734 Assembler::vpsrlw(nds, nds, shift, vector_len);
4735 evmovdqul(dst, nds, Assembler::AVX_512bit);
4736 } else {
4737 // use nds as scratch for xmm0
4738 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4739 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4740 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4741 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4742 }
4743 }
4744
4745 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4746 int dst_enc = dst->encoding();
4747 int nds_enc = nds->encoding();
4748 int shift_enc = shift->encoding();
4749 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4750 Assembler::vpsllw(dst, nds, shift, vector_len);
4751 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4752 Assembler::vpsllw(dst, dst, shift, vector_len);
4753 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4754 // use nds_enc as scratch with shift
4755 evmovdqul(nds, shift, Assembler::AVX_512bit);
4756 Assembler::vpsllw(dst, dst, nds, vector_len);
4757 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4758 // use nds as scratch with dst
4759 evmovdqul(nds, dst, Assembler::AVX_512bit);
4760 Assembler::vpsllw(nds, nds, shift, vector_len);
4761 evmovdqul(dst, nds, Assembler::AVX_512bit);
4762 } else if (dst_enc < 16) {
4763 // use nds to save a copy of xmm0 and hold shift
4764 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4765 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4766 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4767 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4768 } else if (nds_enc < 16) {
4769 // use nds as dest as temps
4770 evmovdqul(nds, dst, Assembler::AVX_512bit);
4771 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4772 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4773 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4774 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4775 evmovdqul(dst, nds, Assembler::AVX_512bit);
4776 } else {
4777 // worse case scenario, all regs are in the upper bank
4778 subptr(rsp, 64);
4779 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4780 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4781 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4782 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4783 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4784 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4785 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4786 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4787 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4788 addptr(rsp, 64);
4789 }
4790 }
4791
4792 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4793 int dst_enc = dst->encoding();
4794 int nds_enc = nds->encoding();
4795 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4796 Assembler::vpsllw(dst, nds, shift, vector_len);
4797 } else if (dst_enc < 16) {
4798 Assembler::vpsllw(dst, dst, shift, vector_len);
4799 } else if (nds_enc < 16) {
4800 // use nds as scratch
4801 evmovdqul(nds, dst, Assembler::AVX_512bit);
4802 Assembler::vpsllw(nds, nds, shift, vector_len);
4803 evmovdqul(dst, nds, Assembler::AVX_512bit);
4804 } else {
4805 // use nds as scratch for xmm0
4806 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4807 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4808 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4809 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4810 }
4811 }
4812
4813 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4814 int dst_enc = dst->encoding();
4815 int src_enc = src->encoding();
4816 if ((dst_enc < 16) && (src_enc < 16)) {
4817 Assembler::vptest(dst, src);
4818 } else if (src_enc < 16) {
4819 subptr(rsp, 64);
4820 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4821 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4822 Assembler::vptest(xmm0, src);
4823 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4824 addptr(rsp, 64);
4825 } else if (dst_enc < 16) {
4826 subptr(rsp, 64);
4827 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4828 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4829 Assembler::vptest(dst, xmm0);
4830 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4831 addptr(rsp, 64);
4832 } else {
4833 subptr(rsp, 64);
4834 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4835 subptr(rsp, 64);
4836 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4837 movdqu(xmm0, src);
4838 movdqu(xmm1, dst);
4839 Assembler::vptest(xmm1, xmm0);
4840 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4841 addptr(rsp, 64);
4842 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4843 addptr(rsp, 64);
4844 }
4845 }
4846
4847 // This instruction exists within macros, ergo we cannot control its input
4848 // when emitted through those patterns.
4849 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4850 if (VM_Version::supports_avx512nobw()) {
4851 int dst_enc = dst->encoding();
4852 int src_enc = src->encoding();
4853 if (dst_enc == src_enc) {
4854 if (dst_enc < 16) {
4855 Assembler::punpcklbw(dst, src);
4856 } else {
4857 subptr(rsp, 64);
4858 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4859 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4860 Assembler::punpcklbw(xmm0, xmm0);
4861 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4862 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4863 addptr(rsp, 64);
4864 }
4865 } else {
4866 if ((src_enc < 16) && (dst_enc < 16)) {
4867 Assembler::punpcklbw(dst, src);
4868 } else if (src_enc < 16) {
4869 subptr(rsp, 64);
4870 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4871 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4872 Assembler::punpcklbw(xmm0, src);
4873 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4874 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4875 addptr(rsp, 64);
4876 } else if (dst_enc < 16) {
4877 subptr(rsp, 64);
4878 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4879 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4880 Assembler::punpcklbw(dst, xmm0);
4881 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4882 addptr(rsp, 64);
4883 } else {
4884 subptr(rsp, 64);
4885 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4886 subptr(rsp, 64);
4887 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4888 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4889 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4890 Assembler::punpcklbw(xmm0, xmm1);
4891 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4892 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4893 addptr(rsp, 64);
4894 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4895 addptr(rsp, 64);
4896 }
4897 }
4898 } else {
4899 Assembler::punpcklbw(dst, src);
4900 }
4901 }
4902
4903 // This instruction exists within macros, ergo we cannot control its input
4904 // when emitted through those patterns.
4905 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4906 if (VM_Version::supports_avx512nobw()) {
4907 int dst_enc = dst->encoding();
4908 int src_enc = src->encoding();
4909 if (dst_enc == src_enc) {
4910 if (dst_enc < 16) {
4911 Assembler::pshuflw(dst, src, mode);
4912 } else {
4913 subptr(rsp, 64);
4914 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4915 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4916 Assembler::pshuflw(xmm0, xmm0, mode);
4917 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4918 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4919 addptr(rsp, 64);
4920 }
4921 } else {
4922 if ((src_enc < 16) && (dst_enc < 16)) {
4923 Assembler::pshuflw(dst, src, mode);
4924 } else if (src_enc < 16) {
4925 subptr(rsp, 64);
4926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4927 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4928 Assembler::pshuflw(xmm0, src, mode);
4929 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4930 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4931 addptr(rsp, 64);
4932 } else if (dst_enc < 16) {
4933 subptr(rsp, 64);
4934 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4935 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4936 Assembler::pshuflw(dst, xmm0, mode);
4937 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4938 addptr(rsp, 64);
4939 } else {
4940 subptr(rsp, 64);
4941 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4942 subptr(rsp, 64);
4943 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4944 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4945 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4946 Assembler::pshuflw(xmm0, xmm1, mode);
4947 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4948 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4949 addptr(rsp, 64);
4950 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4951 addptr(rsp, 64);
4952 }
4953 }
4954 } else {
4955 Assembler::pshuflw(dst, src, mode);
4956 }
4957 }
4958
4959 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4960 if (reachable(src)) {
4961 vandpd(dst, nds, as_Address(src), vector_len);
4962 } else {
4963 lea(rscratch1, src);
4964 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
4965 }
4966 }
4967
4968 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4969 if (reachable(src)) {
4970 vandps(dst, nds, as_Address(src), vector_len);
4971 } else {
4972 lea(rscratch1, src);
4973 vandps(dst, nds, Address(rscratch1, 0), vector_len);
4974 }
4975 }
4976
4977 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4978 if (reachable(src)) {
4979 vdivsd(dst, nds, as_Address(src));
4980 } else {
4981 lea(rscratch1, src);
4982 vdivsd(dst, nds, Address(rscratch1, 0));
4983 }
4984 }
4985
4986 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4987 if (reachable(src)) {
4988 vdivss(dst, nds, as_Address(src));
4989 } else {
4990 lea(rscratch1, src);
4991 vdivss(dst, nds, Address(rscratch1, 0));
4992 }
4993 }
4994
4995 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4996 if (reachable(src)) {
4997 vmulsd(dst, nds, as_Address(src));
4998 } else {
4999 lea(rscratch1, src);
5000 vmulsd(dst, nds, Address(rscratch1, 0));
5001 }
5002 }
5003
5004 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5005 if (reachable(src)) {
5006 vmulss(dst, nds, as_Address(src));
5007 } else {
5008 lea(rscratch1, src);
5009 vmulss(dst, nds, Address(rscratch1, 0));
5010 }
5011 }
5012
5013 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5014 if (reachable(src)) {
5015 vsubsd(dst, nds, as_Address(src));
5016 } else {
5017 lea(rscratch1, src);
5018 vsubsd(dst, nds, Address(rscratch1, 0));
5019 }
5020 }
5021
5022 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5023 if (reachable(src)) {
5024 vsubss(dst, nds, as_Address(src));
5025 } else {
5026 lea(rscratch1, src);
5027 vsubss(dst, nds, Address(rscratch1, 0));
5028 }
5029 }
5030
5031 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5032 int nds_enc = nds->encoding();
5033 int dst_enc = dst->encoding();
5034 bool dst_upper_bank = (dst_enc > 15);
5035 bool nds_upper_bank = (nds_enc > 15);
5036 if (VM_Version::supports_avx512novl() &&
5037 (nds_upper_bank || dst_upper_bank)) {
5038 if (dst_upper_bank) {
5039 subptr(rsp, 64);
5040 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5041 movflt(xmm0, nds);
5042 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5043 movflt(dst, xmm0);
5044 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5045 addptr(rsp, 64);
5046 } else {
5047 movflt(dst, nds);
5048 vxorps(dst, dst, src, Assembler::AVX_128bit);
5049 }
5050 } else {
5051 vxorps(dst, nds, src, Assembler::AVX_128bit);
5052 }
5053 }
5054
5055 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5056 int nds_enc = nds->encoding();
5057 int dst_enc = dst->encoding();
5058 bool dst_upper_bank = (dst_enc > 15);
5059 bool nds_upper_bank = (nds_enc > 15);
5060 if (VM_Version::supports_avx512novl() &&
5061 (nds_upper_bank || dst_upper_bank)) {
5062 if (dst_upper_bank) {
5063 subptr(rsp, 64);
5064 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5065 movdbl(xmm0, nds);
5066 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5067 movdbl(dst, xmm0);
5068 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5069 addptr(rsp, 64);
5070 } else {
5071 movdbl(dst, nds);
5072 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5073 }
5074 } else {
5075 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5076 }
5077 }
5078
5079 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5080 if (reachable(src)) {
5081 vxorpd(dst, nds, as_Address(src), vector_len);
5082 } else {
5083 lea(rscratch1, src);
5084 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5085 }
5086 }
5087
5088 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5089 if (reachable(src)) {
5090 vxorps(dst, nds, as_Address(src), vector_len);
5091 } else {
5092 lea(rscratch1, src);
5093 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5094 }
5095 }
5096
5097
5098 //////////////////////////////////////////////////////////////////////////////////
5099 #if INCLUDE_ALL_GCS
5100
5101 void MacroAssembler::g1_write_barrier_pre(Register obj,
5102 Register pre_val,
5103 Register thread,
5104 Register tmp,
5105 bool tosca_live,
5106 bool expand_call) {
5107
5108 // If expand_call is true then we expand the call_VM_leaf macro
5109 // directly to skip generating the check by
5110 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5111
5112 #ifdef _LP64
5113 assert(thread == r15_thread, "must be");
5114 #endif // _LP64
5115
5116 Label done;
5117 Label runtime;
5118
5119 assert(pre_val != noreg, "check this code");
5120
5121 if (obj != noreg) {
5122 assert_different_registers(obj, pre_val, tmp);
5123 assert(pre_val != rax, "check this code");
5124 }
5125
5126 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5127 SATBMarkQueue::byte_offset_of_active()));
5128 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5129 SATBMarkQueue::byte_offset_of_index()));
5130 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5131 SATBMarkQueue::byte_offset_of_buf()));
5132
5133
5134 // Is marking active?
5135 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5136 cmpl(in_progress, 0);
5137 } else {
5138 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5139 cmpb(in_progress, 0);
5140 }
5141 jcc(Assembler::equal, done);
5142
5143 // Do we need to load the previous value?
5144 if (obj != noreg) {
5145 load_heap_oop(pre_val, Address(obj, 0));
5146 }
5147
5148 // Is the previous value null?
5149 cmpptr(pre_val, (int32_t) NULL_WORD);
5150 jcc(Assembler::equal, done);
5151
5152 // Can we store original value in the thread's buffer?
5153 // Is index == 0?
5154 // (The index field is typed as size_t.)
5155
5156 movptr(tmp, index); // tmp := *index_adr
5157 cmpptr(tmp, 0); // tmp == 0?
5158 jcc(Assembler::equal, runtime); // If yes, goto runtime
5159
5160 subptr(tmp, wordSize); // tmp := tmp - wordSize
5161 movptr(index, tmp); // *index_adr := tmp
5162 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5163
5164 // Record the previous value
5165 movptr(Address(tmp, 0), pre_val);
5166 jmp(done);
5167
5168 bind(runtime);
5169 // save the live input values
5170 if(tosca_live) push(rax);
5171
5172 if (obj != noreg && obj != rax)
5173 push(obj);
5174
5175 if (pre_val != rax)
5176 push(pre_val);
5177
5178 // Calling the runtime using the regular call_VM_leaf mechanism generates
5179 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5180 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5181 //
5182 // If we care generating the pre-barrier without a frame (e.g. in the
5183 // intrinsified Reference.get() routine) then ebp might be pointing to
5184 // the caller frame and so this check will most likely fail at runtime.
5185 //
5186 // Expanding the call directly bypasses the generation of the check.
5187 // So when we do not have have a full interpreter frame on the stack
5188 // expand_call should be passed true.
5189
5190 NOT_LP64( push(thread); )
5191
5192 if (expand_call) {
5193 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5194 pass_arg1(this, thread);
5195 pass_arg0(this, pre_val);
5196 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5197 } else {
5198 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5199 }
5200
5201 NOT_LP64( pop(thread); )
5202
5203 // save the live input values
5204 if (pre_val != rax)
5205 pop(pre_val);
5206
5207 if (obj != noreg && obj != rax)
5208 pop(obj);
5209
5210 if(tosca_live) pop(rax);
5211
5212 bind(done);
5213 }
5214
5215 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5216 Register new_val,
5217 Register thread,
5218 Register tmp,
5219 Register tmp2) {
5220 #ifdef _LP64
5221 assert(thread == r15_thread, "must be");
5222 #endif // _LP64
5223
5224 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5225 DirtyCardQueue::byte_offset_of_index()));
5226 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5227 DirtyCardQueue::byte_offset_of_buf()));
5228
5229 CardTableModRefBS* ct =
5230 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5231 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5232
5233 Label done;
5234 Label runtime;
5235
5236 // Does store cross heap regions?
5237
5238 movptr(tmp, store_addr);
5239 xorptr(tmp, new_val);
5240 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5241 jcc(Assembler::equal, done);
5242
5243 // crosses regions, storing NULL?
5244
5245 cmpptr(new_val, (int32_t) NULL_WORD);
5246 jcc(Assembler::equal, done);
5247
5248 // storing region crossing non-NULL, is card already dirty?
5249
5250 const Register card_addr = tmp;
5251 const Register cardtable = tmp2;
5252
5253 movptr(card_addr, store_addr);
5254 shrptr(card_addr, CardTableModRefBS::card_shift);
5255 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5256 // a valid address and therefore is not properly handled by the relocation code.
5257 movptr(cardtable, (intptr_t)ct->byte_map_base);
5258 addptr(card_addr, cardtable);
5259
5260 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5261 jcc(Assembler::equal, done);
5262
5263 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5264 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5265 jcc(Assembler::equal, done);
5266
5267
5268 // storing a region crossing, non-NULL oop, card is clean.
5269 // dirty card and log.
5270
5271 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5272
5273 cmpl(queue_index, 0);
5274 jcc(Assembler::equal, runtime);
5275 subl(queue_index, wordSize);
5276 movptr(tmp2, buffer);
5277 #ifdef _LP64
5278 movslq(rscratch1, queue_index);
5279 addq(tmp2, rscratch1);
5280 movq(Address(tmp2, 0), card_addr);
5281 #else
5282 addl(tmp2, queue_index);
5283 movl(Address(tmp2, 0), card_addr);
5284 #endif
5285 jmp(done);
5286
5287 bind(runtime);
5288 // save the live input values
5289 push(store_addr);
5290 push(new_val);
5291 #ifdef _LP64
5292 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5293 #else
5294 push(thread);
5295 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5296 pop(thread);
5297 #endif
5298 pop(new_val);
5299 pop(store_addr);
5300
5301 bind(done);
5302 }
5303
5304 #endif // INCLUDE_ALL_GCS
5305 //////////////////////////////////////////////////////////////////////////////////
5306
5307
5308 void MacroAssembler::store_check(Register obj, Address dst) {
5309 store_check(obj);
5310 }
5311
5312 void MacroAssembler::store_check(Register obj) {
5313 // Does a store check for the oop in register obj. The content of
5314 // register obj is destroyed afterwards.
5315 BarrierSet* bs = Universe::heap()->barrier_set();
5316 assert(bs->kind() == BarrierSet::CardTableForRS ||
5317 bs->kind() == BarrierSet::CardTableExtension,
5318 "Wrong barrier set kind");
5319
5320 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5321 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5322
5323 shrptr(obj, CardTableModRefBS::card_shift);
5324
5325 Address card_addr;
5326
5327 // The calculation for byte_map_base is as follows:
5328 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5329 // So this essentially converts an address to a displacement and it will
5330 // never need to be relocated. On 64bit however the value may be too
5331 // large for a 32bit displacement.
5332 intptr_t disp = (intptr_t) ct->byte_map_base;
5333 if (is_simm32(disp)) {
5334 card_addr = Address(noreg, obj, Address::times_1, disp);
5335 } else {
5336 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5337 // displacement and done in a single instruction given favorable mapping and a
5338 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5339 // entry and that entry is not properly handled by the relocation code.
5340 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5341 Address index(noreg, obj, Address::times_1);
5342 card_addr = as_Address(ArrayAddress(cardtable, index));
5343 }
5344
5345 int dirty = CardTableModRefBS::dirty_card_val();
5346 if (UseCondCardMark) {
5347 Label L_already_dirty;
5348 if (UseConcMarkSweepGC) {
5349 membar(Assembler::StoreLoad);
5350 }
5351 cmpb(card_addr, dirty);
5352 jcc(Assembler::equal, L_already_dirty);
5353 movb(card_addr, dirty);
5354 bind(L_already_dirty);
5355 } else {
5356 movb(card_addr, dirty);
5357 }
5358 }
5359
5360 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5361 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5362 }
5363
5364 // Force generation of a 4 byte immediate value even if it fits into 8bit
5365 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5366 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5367 }
5368
5369 void MacroAssembler::subptr(Register dst, Register src) {
5370 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5371 }
5372
5373 // C++ bool manipulation
5374 void MacroAssembler::testbool(Register dst) {
5375 if(sizeof(bool) == 1)
5376 testb(dst, 0xff);
5377 else if(sizeof(bool) == 2) {
5378 // testw implementation needed for two byte bools
5379 ShouldNotReachHere();
5380 } else if(sizeof(bool) == 4)
5381 testl(dst, dst);
5382 else
5383 // unsupported
5384 ShouldNotReachHere();
5385 }
5386
5387 void MacroAssembler::testptr(Register dst, Register src) {
5388 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5389 }
5390
5391 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5392 void MacroAssembler::tlab_allocate(Register obj,
5393 Register var_size_in_bytes,
5394 int con_size_in_bytes,
5395 Register t1,
5396 Register t2,
5397 Label& slow_case) {
5398 assert_different_registers(obj, t1, t2);
5399 assert_different_registers(obj, var_size_in_bytes, t1);
5400 Register end = t2;
5401 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5402
5403 verify_tlab();
5404
5405 NOT_LP64(get_thread(thread));
5406
5407 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5408 if (var_size_in_bytes == noreg) {
5409 lea(end, Address(obj, con_size_in_bytes));
5410 } else {
5411 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5412 }
5413 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5414 jcc(Assembler::above, slow_case);
5415
5416 // update the tlab top pointer
5417 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5418
5419 // recover var_size_in_bytes if necessary
5420 if (var_size_in_bytes == end) {
5421 subptr(var_size_in_bytes, obj);
5422 }
5423 verify_tlab();
5424 }
5425
5426 // Preserves rbx, and rdx.
5427 Register MacroAssembler::tlab_refill(Label& retry,
5428 Label& try_eden,
5429 Label& slow_case) {
5430 Register top = rax;
5431 Register t1 = rcx; // object size
5432 Register t2 = rsi;
5433 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5434 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5435 Label do_refill, discard_tlab;
5436
5437 if (!Universe::heap()->supports_inline_contig_alloc()) {
5438 // No allocation in the shared eden.
5439 jmp(slow_case);
5440 }
5441
5442 NOT_LP64(get_thread(thread_reg));
5443
5444 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5445 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5446
5447 // calculate amount of free space
5448 subptr(t1, top);
5449 shrptr(t1, LogHeapWordSize);
5450
5451 // Retain tlab and allocate object in shared space if
5452 // the amount free in the tlab is too large to discard.
5453 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5454 jcc(Assembler::lessEqual, discard_tlab);
5455
5456 // Retain
5457 // %%% yuck as movptr...
5458 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5459 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5460 if (TLABStats) {
5461 // increment number of slow_allocations
5462 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5463 }
5464 jmp(try_eden);
5465
5466 bind(discard_tlab);
5467 if (TLABStats) {
5468 // increment number of refills
5469 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5470 // accumulate wastage -- t1 is amount free in tlab
5471 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5472 }
5473
5474 // if tlab is currently allocated (top or end != null) then
5475 // fill [top, end + alignment_reserve) with array object
5476 testptr(top, top);
5477 jcc(Assembler::zero, do_refill);
5478
5479 // set up the mark word
5480 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5481 // set the length to the remaining space
5482 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5483 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5484 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5485 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5486 // set klass to intArrayKlass
5487 // dubious reloc why not an oop reloc?
5488 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5489 // store klass last. concurrent gcs assumes klass length is valid if
5490 // klass field is not null.
5491 store_klass(top, t1);
5492
5493 movptr(t1, top);
5494 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5495 incr_allocated_bytes(thread_reg, t1, 0);
5496
5497 // refill the tlab with an eden allocation
5498 bind(do_refill);
5499 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5500 shlptr(t1, LogHeapWordSize);
5501 // allocate new tlab, address returned in top
5502 eden_allocate(top, t1, 0, t2, slow_case);
5503
5504 // Check that t1 was preserved in eden_allocate.
5505 #ifdef ASSERT
5506 if (UseTLAB) {
5507 Label ok;
5508 Register tsize = rsi;
5509 assert_different_registers(tsize, thread_reg, t1);
5510 push(tsize);
5511 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5512 shlptr(tsize, LogHeapWordSize);
5513 cmpptr(t1, tsize);
5514 jcc(Assembler::equal, ok);
5515 STOP("assert(t1 != tlab size)");
5516 should_not_reach_here();
5517
5518 bind(ok);
5519 pop(tsize);
5520 }
5521 #endif
5522 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5523 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5524 addptr(top, t1);
5525 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5526 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5527
5528 if (ZeroTLAB) {
5529 // This is a fast TLAB refill, therefore the GC is not notified of it.
5530 // So compiled code must fill the new TLAB with zeroes.
5531 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5532 zero_memory(top, t1, 0, t2);
5533 }
5534
5535 verify_tlab();
5536 jmp(retry);
5537
5538 return thread_reg; // for use by caller
5539 }
5540
5541 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5542 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5543 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5544 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5545 Label done;
5546
5547 testptr(length_in_bytes, length_in_bytes);
5548 jcc(Assembler::zero, done);
5549
5550 // initialize topmost word, divide index by 2, check if odd and test if zero
5551 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5552 #ifdef ASSERT
5553 {
5554 Label L;
5555 testptr(length_in_bytes, BytesPerWord - 1);
5556 jcc(Assembler::zero, L);
5557 stop("length must be a multiple of BytesPerWord");
5558 bind(L);
5559 }
5560 #endif
5561 Register index = length_in_bytes;
5562 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5563 if (UseIncDec) {
5564 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5565 } else {
5566 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5567 shrptr(index, 1);
5568 }
5569 #ifndef _LP64
5570 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5571 {
5572 Label even;
5573 // note: if index was a multiple of 8, then it cannot
5574 // be 0 now otherwise it must have been 0 before
5575 // => if it is even, we don't need to check for 0 again
5576 jcc(Assembler::carryClear, even);
5577 // clear topmost word (no jump would be needed if conditional assignment worked here)
5578 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5579 // index could be 0 now, must check again
5580 jcc(Assembler::zero, done);
5581 bind(even);
5582 }
5583 #endif // !_LP64
5584 // initialize remaining object fields: index is a multiple of 2 now
5585 {
5586 Label loop;
5587 bind(loop);
5588 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5589 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5590 decrement(index);
5591 jcc(Assembler::notZero, loop);
5592 }
5593
5594 bind(done);
5595 }
5596
5597 void MacroAssembler::incr_allocated_bytes(Register thread,
5598 Register var_size_in_bytes,
5599 int con_size_in_bytes,
5600 Register t1) {
5601 if (!thread->is_valid()) {
5602 #ifdef _LP64
5603 thread = r15_thread;
5604 #else
5605 assert(t1->is_valid(), "need temp reg");
5606 thread = t1;
5607 get_thread(thread);
5608 #endif
5609 }
5610
5611 #ifdef _LP64
5612 if (var_size_in_bytes->is_valid()) {
5613 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5614 } else {
5615 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5616 }
5617 #else
5618 if (var_size_in_bytes->is_valid()) {
5619 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5620 } else {
5621 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5622 }
5623 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5624 #endif
5625 }
5626
5627 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) {
5628 pusha();
5629
5630 // if we are coming from c1, xmm registers may be live
5631 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8);
5632 if (UseAVX > 2) {
5633 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8);
5634 }
5635
5636 if (UseSSE == 1) {
5637 subptr(rsp, sizeof(jdouble)*8);
5638 for (int n = 0; n < 8; n++) {
5639 movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n));
5640 }
5641 } else if (UseSSE >= 2) {
5642 if (UseAVX > 2) {
5643 push(rbx);
5644 movl(rbx, 0xffff);
5645 kmovwl(k1, rbx);
5646 pop(rbx);
5647 }
5648 #ifdef COMPILER2
5649 if (MaxVectorSize > 16) {
5650 if(UseAVX > 2) {
5651 // Save upper half of ZMM registers
5652 subptr(rsp, 32*num_xmm_regs);
5653 for (int n = 0; n < num_xmm_regs; n++) {
5654 vextractf64x4h(Address(rsp, n*32), as_XMMRegister(n), 1);
5655 }
5656 }
5657 assert(UseAVX > 0, "256 bit vectors are supported only with AVX");
5658 // Save upper half of YMM registers
5659 subptr(rsp, 16*num_xmm_regs);
5660 for (int n = 0; n < num_xmm_regs; n++) {
5661 vextractf128h(Address(rsp, n*16), as_XMMRegister(n));
5662 }
5663 }
5664 #endif
5665 // Save whole 128bit (16 bytes) XMM registers
5666 subptr(rsp, 16*num_xmm_regs);
5667 #ifdef _LP64
5668 if (VM_Version::supports_evex()) {
5669 for (int n = 0; n < num_xmm_regs; n++) {
5670 vextractf32x4h(Address(rsp, n*16), as_XMMRegister(n), 0);
5671 }
5672 } else {
5673 for (int n = 0; n < num_xmm_regs; n++) {
5674 movdqu(Address(rsp, n*16), as_XMMRegister(n));
5675 }
5676 }
5677 #else
5678 for (int n = 0; n < num_xmm_regs; n++) {
5679 movdqu(Address(rsp, n*16), as_XMMRegister(n));
5680 }
5681 #endif
5682 }
5683
5684 // Preserve registers across runtime call
5685 int incoming_argument_and_return_value_offset = -1;
5686 if (num_fpu_regs_in_use > 1) {
5687 // Must preserve all other FPU regs (could alternatively convert
5688 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash
5689 // FPU state, but can not trust C compiler)
5690 NEEDS_CLEANUP;
5691 // NOTE that in this case we also push the incoming argument(s) to
5692 // the stack and restore it later; we also use this stack slot to
5693 // hold the return value from dsin, dcos etc.
5694 for (int i = 0; i < num_fpu_regs_in_use; i++) {
5695 subptr(rsp, sizeof(jdouble));
5696 fstp_d(Address(rsp, 0));
5697 }
5698 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1);
5699 for (int i = nb_args-1; i >= 0; i--) {
5700 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble)));
5701 }
5702 }
5703
5704 subptr(rsp, nb_args*sizeof(jdouble));
5705 for (int i = 0; i < nb_args; i++) {
5706 fstp_d(Address(rsp, i*sizeof(jdouble)));
5707 }
5708
5709 #ifdef _LP64
5710 if (nb_args > 0) {
5711 movdbl(xmm0, Address(rsp, 0));
5712 }
5713 if (nb_args > 1) {
5714 movdbl(xmm1, Address(rsp, sizeof(jdouble)));
5715 }
5716 assert(nb_args <= 2, "unsupported number of args");
5717 #endif // _LP64
5718
5719 // NOTE: we must not use call_VM_leaf here because that requires a
5720 // complete interpreter frame in debug mode -- same bug as 4387334
5721 // MacroAssembler::call_VM_leaf_base is perfectly safe and will
5722 // do proper 64bit abi
5723
5724 NEEDS_CLEANUP;
5725 // Need to add stack banging before this runtime call if it needs to
5726 // be taken; however, there is no generic stack banging routine at
5727 // the MacroAssembler level
5728
5729 MacroAssembler::call_VM_leaf_base(runtime_entry, 0);
5730
5731 #ifdef _LP64
5732 movsd(Address(rsp, 0), xmm0);
5733 fld_d(Address(rsp, 0));
5734 #endif // _LP64
5735 addptr(rsp, sizeof(jdouble)*nb_args);
5736 if (num_fpu_regs_in_use > 1) {
5737 // Must save return value to stack and then restore entire FPU
5738 // stack except incoming arguments
5739 fstp_d(Address(rsp, incoming_argument_and_return_value_offset));
5740 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) {
5741 fld_d(Address(rsp, 0));
5742 addptr(rsp, sizeof(jdouble));
5743 }
5744 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble)));
5745 addptr(rsp, sizeof(jdouble)*nb_args);
5746 }
5747
5748 if (UseSSE == 1) {
5749 for (int n = 0; n < 8; n++) {
5750 movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble)));
5751 }
5752 addptr(rsp, sizeof(jdouble)*8);
5753 } else if (UseSSE >= 2) {
5754 // Restore whole 128bit (16 bytes) XMM registers
5755 #ifdef _LP64
5756 if (VM_Version::supports_evex()) {
5757 for (int n = 0; n < num_xmm_regs; n++) {
5758 vinsertf32x4h(as_XMMRegister(n), Address(rsp, n*16), 0);
5759 }
5760 } else {
5761 for (int n = 0; n < num_xmm_regs; n++) {
5762 movdqu(as_XMMRegister(n), Address(rsp, n*16));
5763 }
5764 }
5765 #else
5766 for (int n = 0; n < num_xmm_regs; n++) {
5767 movdqu(as_XMMRegister(n), Address(rsp, n*16));
5768 }
5769 #endif
5770 addptr(rsp, 16*num_xmm_regs);
5771
5772 #ifdef COMPILER2
5773 if (MaxVectorSize > 16) {
5774 // Restore upper half of YMM registers.
5775 for (int n = 0; n < num_xmm_regs; n++) {
5776 vinsertf128h(as_XMMRegister(n), Address(rsp, n*16));
5777 }
5778 addptr(rsp, 16*num_xmm_regs);
5779 if(UseAVX > 2) {
5780 for (int n = 0; n < num_xmm_regs; n++) {
5781 vinsertf64x4h(as_XMMRegister(n), Address(rsp, n*32), 1);
5782 }
5783 addptr(rsp, 32*num_xmm_regs);
5784 }
5785 }
5786 #endif
5787 }
5788 popa();
5789 }
5790
5791 static const double pi_4 = 0.7853981633974483;
5792
5793 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) {
5794 // A hand-coded argument reduction for values in fabs(pi/4, pi/2)
5795 // was attempted in this code; unfortunately it appears that the
5796 // switch to 80-bit precision and back causes this to be
5797 // unprofitable compared with simply performing a runtime call if
5798 // the argument is out of the (-pi/4, pi/4) range.
5799
5800 Register tmp = noreg;
5801 if (!VM_Version::supports_cmov()) {
5802 // fcmp needs a temporary so preserve rbx,
5803 tmp = rbx;
5804 push(tmp);
5805 }
5806
5807 Label slow_case, done;
5808 if (trig == 't') {
5809 ExternalAddress pi4_adr = (address)&pi_4;
5810 if (reachable(pi4_adr)) {
5811 // x ?<= pi/4
5812 fld_d(pi4_adr);
5813 fld_s(1); // Stack: X PI/4 X
5814 fabs(); // Stack: |X| PI/4 X
5815 fcmp(tmp);
5816 jcc(Assembler::above, slow_case);
5817
5818 // fastest case: -pi/4 <= x <= pi/4
5819 ftan();
5820
5821 jmp(done);
5822 }
5823 }
5824 // slow case: runtime call
5825 bind(slow_case);
5826
5827 switch(trig) {
5828 case 's':
5829 {
5830 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use);
5831 }
5832 break;
5833 case 'c':
5834 {
5835 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use);
5836 }
5837 break;
5838 case 't':
5839 {
5840 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use);
5841 }
5842 break;
5843 default:
5844 assert(false, "bad intrinsic");
5845 break;
5846 }
5847
5848 // Come here with result in F-TOS
5849 bind(done);
5850
5851 if (tmp != noreg) {
5852 pop(tmp);
5853 }
5854 }
5855
5856 // Look up the method for a megamorphic invokeinterface call.
5857 // The target method is determined by <intf_klass, itable_index>.
5858 // The receiver klass is in recv_klass.
5859 // On success, the result will be in method_result, and execution falls through.
5860 // On failure, execution transfers to the given label.
5861 void MacroAssembler::lookup_interface_method(Register recv_klass,
5862 Register intf_klass,
5863 RegisterOrConstant itable_index,
5864 Register method_result,
5865 Register scan_temp,
5866 Label& L_no_such_interface) {
5867 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5868 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5869 "caller must use same register for non-constant itable index as for method");
5870
5871 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5872 int vtable_base = InstanceKlass::vtable_start_offset() * wordSize;
5873 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5874 int scan_step = itableOffsetEntry::size() * wordSize;
5875 int vte_size = vtableEntry::size() * wordSize;
5876 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5877 assert(vte_size == wordSize, "else adjust times_vte_scale");
5878
5879 movl(scan_temp, Address(recv_klass, InstanceKlass::vtable_length_offset() * wordSize));
5880
5881 // %%% Could store the aligned, prescaled offset in the klassoop.
5882 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5883 if (HeapWordsPerLong > 1) {
5884 // Round up to align_object_offset boundary
5885 // see code for InstanceKlass::start_of_itable!
5886 round_to(scan_temp, BytesPerLong);
5887 }
5888
5889 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5890 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5891 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5892
5893 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5894 // if (scan->interface() == intf) {
5895 // result = (klass + scan->offset() + itable_index);
5896 // }
5897 // }
5898 Label search, found_method;
5899
5900 for (int peel = 1; peel >= 0; peel--) {
5901 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5902 cmpptr(intf_klass, method_result);
5903
5904 if (peel) {
5905 jccb(Assembler::equal, found_method);
5906 } else {
5907 jccb(Assembler::notEqual, search);
5908 // (invert the test to fall through to found_method...)
5909 }
5910
5911 if (!peel) break;
5912
5913 bind(search);
5914
5915 // Check that the previous entry is non-null. A null entry means that
5916 // the receiver class doesn't implement the interface, and wasn't the
5917 // same as when the caller was compiled.
5918 testptr(method_result, method_result);
5919 jcc(Assembler::zero, L_no_such_interface);
5920 addptr(scan_temp, scan_step);
5921 }
5922
5923 bind(found_method);
5924
5925 // Got a hit.
5926 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5927 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5928 }
5929
5930
5931 // virtual method calling
5932 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5933 RegisterOrConstant vtable_index,
5934 Register method_result) {
5935 const int base = InstanceKlass::vtable_start_offset() * wordSize;
5936 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5937 Address vtable_entry_addr(recv_klass,
5938 vtable_index, Address::times_ptr,
5939 base + vtableEntry::method_offset_in_bytes());
5940 movptr(method_result, vtable_entry_addr);
5941 }
5942
5943
5944 void MacroAssembler::check_klass_subtype(Register sub_klass,
5945 Register super_klass,
5946 Register temp_reg,
5947 Label& L_success) {
5948 Label L_failure;
5949 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5950 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5951 bind(L_failure);
5952 }
5953
5954
5955 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5956 Register super_klass,
5957 Register temp_reg,
5958 Label* L_success,
5959 Label* L_failure,
5960 Label* L_slow_path,
5961 RegisterOrConstant super_check_offset) {
5962 assert_different_registers(sub_klass, super_klass, temp_reg);
5963 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5964 if (super_check_offset.is_register()) {
5965 assert_different_registers(sub_klass, super_klass,
5966 super_check_offset.as_register());
5967 } else if (must_load_sco) {
5968 assert(temp_reg != noreg, "supply either a temp or a register offset");
5969 }
5970
5971 Label L_fallthrough;
5972 int label_nulls = 0;
5973 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5974 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5975 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5976 assert(label_nulls <= 1, "at most one NULL in the batch");
5977
5978 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5979 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5980 Address super_check_offset_addr(super_klass, sco_offset);
5981
5982 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5983 // range of a jccb. If this routine grows larger, reconsider at
5984 // least some of these.
5985 #define local_jcc(assembler_cond, label) \
5986 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5987 else jcc( assembler_cond, label) /*omit semi*/
5988
5989 // Hacked jmp, which may only be used just before L_fallthrough.
5990 #define final_jmp(label) \
5991 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5992 else jmp(label) /*omit semi*/
5993
5994 // If the pointers are equal, we are done (e.g., String[] elements).
5995 // This self-check enables sharing of secondary supertype arrays among
5996 // non-primary types such as array-of-interface. Otherwise, each such
5997 // type would need its own customized SSA.
5998 // We move this check to the front of the fast path because many
5999 // type checks are in fact trivially successful in this manner,
6000 // so we get a nicely predicted branch right at the start of the check.
6001 cmpptr(sub_klass, super_klass);
6002 local_jcc(Assembler::equal, *L_success);
6003
6004 // Check the supertype display:
6005 if (must_load_sco) {
6006 // Positive movl does right thing on LP64.
6007 movl(temp_reg, super_check_offset_addr);
6008 super_check_offset = RegisterOrConstant(temp_reg);
6009 }
6010 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
6011 cmpptr(super_klass, super_check_addr); // load displayed supertype
6012
6013 // This check has worked decisively for primary supers.
6014 // Secondary supers are sought in the super_cache ('super_cache_addr').
6015 // (Secondary supers are interfaces and very deeply nested subtypes.)
6016 // This works in the same check above because of a tricky aliasing
6017 // between the super_cache and the primary super display elements.
6018 // (The 'super_check_addr' can address either, as the case requires.)
6019 // Note that the cache is updated below if it does not help us find
6020 // what we need immediately.
6021 // So if it was a primary super, we can just fail immediately.
6022 // Otherwise, it's the slow path for us (no success at this point).
6023
6024 if (super_check_offset.is_register()) {
6025 local_jcc(Assembler::equal, *L_success);
6026 cmpl(super_check_offset.as_register(), sc_offset);
6027 if (L_failure == &L_fallthrough) {
6028 local_jcc(Assembler::equal, *L_slow_path);
6029 } else {
6030 local_jcc(Assembler::notEqual, *L_failure);
6031 final_jmp(*L_slow_path);
6032 }
6033 } else if (super_check_offset.as_constant() == sc_offset) {
6034 // Need a slow path; fast failure is impossible.
6035 if (L_slow_path == &L_fallthrough) {
6036 local_jcc(Assembler::equal, *L_success);
6037 } else {
6038 local_jcc(Assembler::notEqual, *L_slow_path);
6039 final_jmp(*L_success);
6040 }
6041 } else {
6042 // No slow path; it's a fast decision.
6043 if (L_failure == &L_fallthrough) {
6044 local_jcc(Assembler::equal, *L_success);
6045 } else {
6046 local_jcc(Assembler::notEqual, *L_failure);
6047 final_jmp(*L_success);
6048 }
6049 }
6050
6051 bind(L_fallthrough);
6052
6053 #undef local_jcc
6054 #undef final_jmp
6055 }
6056
6057
6058 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
6059 Register super_klass,
6060 Register temp_reg,
6061 Register temp2_reg,
6062 Label* L_success,
6063 Label* L_failure,
6064 bool set_cond_codes) {
6065 assert_different_registers(sub_klass, super_klass, temp_reg);
6066 if (temp2_reg != noreg)
6067 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
6068 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
6069
6070 Label L_fallthrough;
6071 int label_nulls = 0;
6072 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
6073 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
6074 assert(label_nulls <= 1, "at most one NULL in the batch");
6075
6076 // a couple of useful fields in sub_klass:
6077 int ss_offset = in_bytes(Klass::secondary_supers_offset());
6078 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
6079 Address secondary_supers_addr(sub_klass, ss_offset);
6080 Address super_cache_addr( sub_klass, sc_offset);
6081
6082 // Do a linear scan of the secondary super-klass chain.
6083 // This code is rarely used, so simplicity is a virtue here.
6084 // The repne_scan instruction uses fixed registers, which we must spill.
6085 // Don't worry too much about pre-existing connections with the input regs.
6086
6087 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
6088 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
6089
6090 // Get super_klass value into rax (even if it was in rdi or rcx).
6091 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
6092 if (super_klass != rax || UseCompressedOops) {
6093 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
6094 mov(rax, super_klass);
6095 }
6096 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
6097 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
6098
6099 #ifndef PRODUCT
6100 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
6101 ExternalAddress pst_counter_addr((address) pst_counter);
6102 NOT_LP64( incrementl(pst_counter_addr) );
6103 LP64_ONLY( lea(rcx, pst_counter_addr) );
6104 LP64_ONLY( incrementl(Address(rcx, 0)) );
6105 #endif //PRODUCT
6106
6107 // We will consult the secondary-super array.
6108 movptr(rdi, secondary_supers_addr);
6109 // Load the array length. (Positive movl does right thing on LP64.)
6110 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
6111 // Skip to start of data.
6112 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
6113
6114 // Scan RCX words at [RDI] for an occurrence of RAX.
6115 // Set NZ/Z based on last compare.
6116 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
6117 // not change flags (only scas instruction which is repeated sets flags).
6118 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
6119
6120 testptr(rax,rax); // Set Z = 0
6121 repne_scan();
6122
6123 // Unspill the temp. registers:
6124 if (pushed_rdi) pop(rdi);
6125 if (pushed_rcx) pop(rcx);
6126 if (pushed_rax) pop(rax);
6127
6128 if (set_cond_codes) {
6129 // Special hack for the AD files: rdi is guaranteed non-zero.
6130 assert(!pushed_rdi, "rdi must be left non-NULL");
6131 // Also, the condition codes are properly set Z/NZ on succeed/failure.
6132 }
6133
6134 if (L_failure == &L_fallthrough)
6135 jccb(Assembler::notEqual, *L_failure);
6136 else jcc(Assembler::notEqual, *L_failure);
6137
6138 // Success. Cache the super we found and proceed in triumph.
6139 movptr(super_cache_addr, super_klass);
6140
6141 if (L_success != &L_fallthrough) {
6142 jmp(*L_success);
6143 }
6144
6145 #undef IS_A_TEMP
6146
6147 bind(L_fallthrough);
6148 }
6149
6150
6151 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6152 if (VM_Version::supports_cmov()) {
6153 cmovl(cc, dst, src);
6154 } else {
6155 Label L;
6156 jccb(negate_condition(cc), L);
6157 movl(dst, src);
6158 bind(L);
6159 }
6160 }
6161
6162 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6163 if (VM_Version::supports_cmov()) {
6164 cmovl(cc, dst, src);
6165 } else {
6166 Label L;
6167 jccb(negate_condition(cc), L);
6168 movl(dst, src);
6169 bind(L);
6170 }
6171 }
6172
6173 void MacroAssembler::verify_oop(Register reg, const char* s) {
6174 if (!VerifyOops) return;
6175
6176 // Pass register number to verify_oop_subroutine
6177 const char* b = NULL;
6178 {
6179 ResourceMark rm;
6180 stringStream ss;
6181 ss.print("verify_oop: %s: %s", reg->name(), s);
6182 b = code_string(ss.as_string());
6183 }
6184 BLOCK_COMMENT("verify_oop {");
6185 #ifdef _LP64
6186 push(rscratch1); // save r10, trashed by movptr()
6187 #endif
6188 push(rax); // save rax,
6189 push(reg); // pass register argument
6190 ExternalAddress buffer((address) b);
6191 // avoid using pushptr, as it modifies scratch registers
6192 // and our contract is not to modify anything
6193 movptr(rax, buffer.addr());
6194 push(rax);
6195 // call indirectly to solve generation ordering problem
6196 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6197 call(rax);
6198 // Caller pops the arguments (oop, message) and restores rax, r10
6199 BLOCK_COMMENT("} verify_oop");
6200 }
6201
6202
6203 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6204 Register tmp,
6205 int offset) {
6206 intptr_t value = *delayed_value_addr;
6207 if (value != 0)
6208 return RegisterOrConstant(value + offset);
6209
6210 // load indirectly to solve generation ordering problem
6211 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6212
6213 #ifdef ASSERT
6214 { Label L;
6215 testptr(tmp, tmp);
6216 if (WizardMode) {
6217 const char* buf = NULL;
6218 {
6219 ResourceMark rm;
6220 stringStream ss;
6221 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6222 buf = code_string(ss.as_string());
6223 }
6224 jcc(Assembler::notZero, L);
6225 STOP(buf);
6226 } else {
6227 jccb(Assembler::notZero, L);
6228 hlt();
6229 }
6230 bind(L);
6231 }
6232 #endif
6233
6234 if (offset != 0)
6235 addptr(tmp, offset);
6236
6237 return RegisterOrConstant(tmp);
6238 }
6239
6240
6241 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6242 int extra_slot_offset) {
6243 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6244 int stackElementSize = Interpreter::stackElementSize;
6245 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6246 #ifdef ASSERT
6247 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6248 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6249 #endif
6250 Register scale_reg = noreg;
6251 Address::ScaleFactor scale_factor = Address::no_scale;
6252 if (arg_slot.is_constant()) {
6253 offset += arg_slot.as_constant() * stackElementSize;
6254 } else {
6255 scale_reg = arg_slot.as_register();
6256 scale_factor = Address::times(stackElementSize);
6257 }
6258 offset += wordSize; // return PC is on stack
6259 return Address(rsp, scale_reg, scale_factor, offset);
6260 }
6261
6262
6263 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6264 if (!VerifyOops) return;
6265
6266 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6267 // Pass register number to verify_oop_subroutine
6268 const char* b = NULL;
6269 {
6270 ResourceMark rm;
6271 stringStream ss;
6272 ss.print("verify_oop_addr: %s", s);
6273 b = code_string(ss.as_string());
6274 }
6275 #ifdef _LP64
6276 push(rscratch1); // save r10, trashed by movptr()
6277 #endif
6278 push(rax); // save rax,
6279 // addr may contain rsp so we will have to adjust it based on the push
6280 // we just did (and on 64 bit we do two pushes)
6281 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6282 // stores rax into addr which is backwards of what was intended.
6283 if (addr.uses(rsp)) {
6284 lea(rax, addr);
6285 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6286 } else {
6287 pushptr(addr);
6288 }
6289
6290 ExternalAddress buffer((address) b);
6291 // pass msg argument
6292 // avoid using pushptr, as it modifies scratch registers
6293 // and our contract is not to modify anything
6294 movptr(rax, buffer.addr());
6295 push(rax);
6296
6297 // call indirectly to solve generation ordering problem
6298 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6299 call(rax);
6300 // Caller pops the arguments (addr, message) and restores rax, r10.
6301 }
6302
6303 void MacroAssembler::verify_tlab() {
6304 #ifdef ASSERT
6305 if (UseTLAB && VerifyOops) {
6306 Label next, ok;
6307 Register t1 = rsi;
6308 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6309
6310 push(t1);
6311 NOT_LP64(push(thread_reg));
6312 NOT_LP64(get_thread(thread_reg));
6313
6314 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6315 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6316 jcc(Assembler::aboveEqual, next);
6317 STOP("assert(top >= start)");
6318 should_not_reach_here();
6319
6320 bind(next);
6321 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6322 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6323 jcc(Assembler::aboveEqual, ok);
6324 STOP("assert(top <= end)");
6325 should_not_reach_here();
6326
6327 bind(ok);
6328 NOT_LP64(pop(thread_reg));
6329 pop(t1);
6330 }
6331 #endif
6332 }
6333
6334 class ControlWord {
6335 public:
6336 int32_t _value;
6337
6338 int rounding_control() const { return (_value >> 10) & 3 ; }
6339 int precision_control() const { return (_value >> 8) & 3 ; }
6340 bool precision() const { return ((_value >> 5) & 1) != 0; }
6341 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6342 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6343 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6344 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6345 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6346
6347 void print() const {
6348 // rounding control
6349 const char* rc;
6350 switch (rounding_control()) {
6351 case 0: rc = "round near"; break;
6352 case 1: rc = "round down"; break;
6353 case 2: rc = "round up "; break;
6354 case 3: rc = "chop "; break;
6355 };
6356 // precision control
6357 const char* pc;
6358 switch (precision_control()) {
6359 case 0: pc = "24 bits "; break;
6360 case 1: pc = "reserved"; break;
6361 case 2: pc = "53 bits "; break;
6362 case 3: pc = "64 bits "; break;
6363 };
6364 // flags
6365 char f[9];
6366 f[0] = ' ';
6367 f[1] = ' ';
6368 f[2] = (precision ()) ? 'P' : 'p';
6369 f[3] = (underflow ()) ? 'U' : 'u';
6370 f[4] = (overflow ()) ? 'O' : 'o';
6371 f[5] = (zero_divide ()) ? 'Z' : 'z';
6372 f[6] = (denormalized()) ? 'D' : 'd';
6373 f[7] = (invalid ()) ? 'I' : 'i';
6374 f[8] = '\x0';
6375 // output
6376 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6377 }
6378
6379 };
6380
6381 class StatusWord {
6382 public:
6383 int32_t _value;
6384
6385 bool busy() const { return ((_value >> 15) & 1) != 0; }
6386 bool C3() const { return ((_value >> 14) & 1) != 0; }
6387 bool C2() const { return ((_value >> 10) & 1) != 0; }
6388 bool C1() const { return ((_value >> 9) & 1) != 0; }
6389 bool C0() const { return ((_value >> 8) & 1) != 0; }
6390 int top() const { return (_value >> 11) & 7 ; }
6391 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6392 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6393 bool precision() const { return ((_value >> 5) & 1) != 0; }
6394 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6395 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6396 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6397 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6398 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6399
6400 void print() const {
6401 // condition codes
6402 char c[5];
6403 c[0] = (C3()) ? '3' : '-';
6404 c[1] = (C2()) ? '2' : '-';
6405 c[2] = (C1()) ? '1' : '-';
6406 c[3] = (C0()) ? '0' : '-';
6407 c[4] = '\x0';
6408 // flags
6409 char f[9];
6410 f[0] = (error_status()) ? 'E' : '-';
6411 f[1] = (stack_fault ()) ? 'S' : '-';
6412 f[2] = (precision ()) ? 'P' : '-';
6413 f[3] = (underflow ()) ? 'U' : '-';
6414 f[4] = (overflow ()) ? 'O' : '-';
6415 f[5] = (zero_divide ()) ? 'Z' : '-';
6416 f[6] = (denormalized()) ? 'D' : '-';
6417 f[7] = (invalid ()) ? 'I' : '-';
6418 f[8] = '\x0';
6419 // output
6420 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6421 }
6422
6423 };
6424
6425 class TagWord {
6426 public:
6427 int32_t _value;
6428
6429 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6430
6431 void print() const {
6432 printf("%04x", _value & 0xFFFF);
6433 }
6434
6435 };
6436
6437 class FPU_Register {
6438 public:
6439 int32_t _m0;
6440 int32_t _m1;
6441 int16_t _ex;
6442
6443 bool is_indefinite() const {
6444 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6445 }
6446
6447 void print() const {
6448 char sign = (_ex < 0) ? '-' : '+';
6449 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6450 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6451 };
6452
6453 };
6454
6455 class FPU_State {
6456 public:
6457 enum {
6458 register_size = 10,
6459 number_of_registers = 8,
6460 register_mask = 7
6461 };
6462
6463 ControlWord _control_word;
6464 StatusWord _status_word;
6465 TagWord _tag_word;
6466 int32_t _error_offset;
6467 int32_t _error_selector;
6468 int32_t _data_offset;
6469 int32_t _data_selector;
6470 int8_t _register[register_size * number_of_registers];
6471
6472 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6473 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6474
6475 const char* tag_as_string(int tag) const {
6476 switch (tag) {
6477 case 0: return "valid";
6478 case 1: return "zero";
6479 case 2: return "special";
6480 case 3: return "empty";
6481 }
6482 ShouldNotReachHere();
6483 return NULL;
6484 }
6485
6486 void print() const {
6487 // print computation registers
6488 { int t = _status_word.top();
6489 for (int i = 0; i < number_of_registers; i++) {
6490 int j = (i - t) & register_mask;
6491 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6492 st(j)->print();
6493 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6494 }
6495 }
6496 printf("\n");
6497 // print control registers
6498 printf("ctrl = "); _control_word.print(); printf("\n");
6499 printf("stat = "); _status_word .print(); printf("\n");
6500 printf("tags = "); _tag_word .print(); printf("\n");
6501 }
6502
6503 };
6504
6505 class Flag_Register {
6506 public:
6507 int32_t _value;
6508
6509 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6510 bool direction() const { return ((_value >> 10) & 1) != 0; }
6511 bool sign() const { return ((_value >> 7) & 1) != 0; }
6512 bool zero() const { return ((_value >> 6) & 1) != 0; }
6513 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6514 bool parity() const { return ((_value >> 2) & 1) != 0; }
6515 bool carry() const { return ((_value >> 0) & 1) != 0; }
6516
6517 void print() const {
6518 // flags
6519 char f[8];
6520 f[0] = (overflow ()) ? 'O' : '-';
6521 f[1] = (direction ()) ? 'D' : '-';
6522 f[2] = (sign ()) ? 'S' : '-';
6523 f[3] = (zero ()) ? 'Z' : '-';
6524 f[4] = (auxiliary_carry()) ? 'A' : '-';
6525 f[5] = (parity ()) ? 'P' : '-';
6526 f[6] = (carry ()) ? 'C' : '-';
6527 f[7] = '\x0';
6528 // output
6529 printf("%08x flags = %s", _value, f);
6530 }
6531
6532 };
6533
6534 class IU_Register {
6535 public:
6536 int32_t _value;
6537
6538 void print() const {
6539 printf("%08x %11d", _value, _value);
6540 }
6541
6542 };
6543
6544 class IU_State {
6545 public:
6546 Flag_Register _eflags;
6547 IU_Register _rdi;
6548 IU_Register _rsi;
6549 IU_Register _rbp;
6550 IU_Register _rsp;
6551 IU_Register _rbx;
6552 IU_Register _rdx;
6553 IU_Register _rcx;
6554 IU_Register _rax;
6555
6556 void print() const {
6557 // computation registers
6558 printf("rax, = "); _rax.print(); printf("\n");
6559 printf("rbx, = "); _rbx.print(); printf("\n");
6560 printf("rcx = "); _rcx.print(); printf("\n");
6561 printf("rdx = "); _rdx.print(); printf("\n");
6562 printf("rdi = "); _rdi.print(); printf("\n");
6563 printf("rsi = "); _rsi.print(); printf("\n");
6564 printf("rbp, = "); _rbp.print(); printf("\n");
6565 printf("rsp = "); _rsp.print(); printf("\n");
6566 printf("\n");
6567 // control registers
6568 printf("flgs = "); _eflags.print(); printf("\n");
6569 }
6570 };
6571
6572
6573 class CPU_State {
6574 public:
6575 FPU_State _fpu_state;
6576 IU_State _iu_state;
6577
6578 void print() const {
6579 printf("--------------------------------------------------\n");
6580 _iu_state .print();
6581 printf("\n");
6582 _fpu_state.print();
6583 printf("--------------------------------------------------\n");
6584 }
6585
6586 };
6587
6588
6589 static void _print_CPU_state(CPU_State* state) {
6590 state->print();
6591 };
6592
6593
6594 void MacroAssembler::print_CPU_state() {
6595 push_CPU_state();
6596 push(rsp); // pass CPU state
6597 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6598 addptr(rsp, wordSize); // discard argument
6599 pop_CPU_state();
6600 }
6601
6602
6603 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6604 static int counter = 0;
6605 FPU_State* fs = &state->_fpu_state;
6606 counter++;
6607 // For leaf calls, only verify that the top few elements remain empty.
6608 // We only need 1 empty at the top for C2 code.
6609 if( stack_depth < 0 ) {
6610 if( fs->tag_for_st(7) != 3 ) {
6611 printf("FPR7 not empty\n");
6612 state->print();
6613 assert(false, "error");
6614 return false;
6615 }
6616 return true; // All other stack states do not matter
6617 }
6618
6619 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6620 "bad FPU control word");
6621
6622 // compute stack depth
6623 int i = 0;
6624 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6625 int d = i;
6626 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6627 // verify findings
6628 if (i != FPU_State::number_of_registers) {
6629 // stack not contiguous
6630 printf("%s: stack not contiguous at ST%d\n", s, i);
6631 state->print();
6632 assert(false, "error");
6633 return false;
6634 }
6635 // check if computed stack depth corresponds to expected stack depth
6636 if (stack_depth < 0) {
6637 // expected stack depth is -stack_depth or less
6638 if (d > -stack_depth) {
6639 // too many elements on the stack
6640 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6641 state->print();
6642 assert(false, "error");
6643 return false;
6644 }
6645 } else {
6646 // expected stack depth is stack_depth
6647 if (d != stack_depth) {
6648 // wrong stack depth
6649 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6650 state->print();
6651 assert(false, "error");
6652 return false;
6653 }
6654 }
6655 // everything is cool
6656 return true;
6657 }
6658
6659
6660 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6661 if (!VerifyFPU) return;
6662 push_CPU_state();
6663 push(rsp); // pass CPU state
6664 ExternalAddress msg((address) s);
6665 // pass message string s
6666 pushptr(msg.addr());
6667 push(stack_depth); // pass stack depth
6668 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6669 addptr(rsp, 3 * wordSize); // discard arguments
6670 // check for error
6671 { Label L;
6672 testl(rax, rax);
6673 jcc(Assembler::notZero, L);
6674 int3(); // break if error condition
6675 bind(L);
6676 }
6677 pop_CPU_state();
6678 }
6679
6680 void MacroAssembler::restore_cpu_control_state_after_jni() {
6681 // Either restore the MXCSR register after returning from the JNI Call
6682 // or verify that it wasn't changed (with -Xcheck:jni flag).
6683 if (VM_Version::supports_sse()) {
6684 if (RestoreMXCSROnJNICalls) {
6685 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6686 } else if (CheckJNICalls) {
6687 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6688 }
6689 }
6690 if (VM_Version::supports_avx()) {
6691 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6692 vzeroupper();
6693 }
6694
6695 #ifndef _LP64
6696 // Either restore the x87 floating pointer control word after returning
6697 // from the JNI call or verify that it wasn't changed.
6698 if (CheckJNICalls) {
6699 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6700 }
6701 #endif // _LP64
6702 }
6703
6704
6705 void MacroAssembler::load_klass(Register dst, Register src) {
6706 #ifdef _LP64
6707 if (UseCompressedClassPointers) {
6708 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6709 decode_klass_not_null(dst);
6710 } else
6711 #endif
6712 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6713 }
6714
6715 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6716 load_klass(dst, src);
6717 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6718 }
6719
6720 void MacroAssembler::store_klass(Register dst, Register src) {
6721 #ifdef _LP64
6722 if (UseCompressedClassPointers) {
6723 encode_klass_not_null(src);
6724 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6725 } else
6726 #endif
6727 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6728 }
6729
6730 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6731 #ifdef _LP64
6732 // FIXME: Must change all places where we try to load the klass.
6733 if (UseCompressedOops) {
6734 movl(dst, src);
6735 decode_heap_oop(dst);
6736 } else
6737 #endif
6738 movptr(dst, src);
6739 }
6740
6741 // Doesn't do verfication, generates fixed size code
6742 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6743 #ifdef _LP64
6744 if (UseCompressedOops) {
6745 movl(dst, src);
6746 decode_heap_oop_not_null(dst);
6747 } else
6748 #endif
6749 movptr(dst, src);
6750 }
6751
6752 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6753 #ifdef _LP64
6754 if (UseCompressedOops) {
6755 assert(!dst.uses(src), "not enough registers");
6756 encode_heap_oop(src);
6757 movl(dst, src);
6758 } else
6759 #endif
6760 movptr(dst, src);
6761 }
6762
6763 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6764 assert_different_registers(src1, tmp);
6765 #ifdef _LP64
6766 if (UseCompressedOops) {
6767 bool did_push = false;
6768 if (tmp == noreg) {
6769 tmp = rax;
6770 push(tmp);
6771 did_push = true;
6772 assert(!src2.uses(rsp), "can't push");
6773 }
6774 load_heap_oop(tmp, src2);
6775 cmpptr(src1, tmp);
6776 if (did_push) pop(tmp);
6777 } else
6778 #endif
6779 cmpptr(src1, src2);
6780 }
6781
6782 // Used for storing NULLs.
6783 void MacroAssembler::store_heap_oop_null(Address dst) {
6784 #ifdef _LP64
6785 if (UseCompressedOops) {
6786 movl(dst, (int32_t)NULL_WORD);
6787 } else {
6788 movslq(dst, (int32_t)NULL_WORD);
6789 }
6790 #else
6791 movl(dst, (int32_t)NULL_WORD);
6792 #endif
6793 }
6794
6795 #ifdef _LP64
6796 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6797 if (UseCompressedClassPointers) {
6798 // Store to klass gap in destination
6799 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6800 }
6801 }
6802
6803 #ifdef ASSERT
6804 void MacroAssembler::verify_heapbase(const char* msg) {
6805 assert (UseCompressedOops, "should be compressed");
6806 assert (Universe::heap() != NULL, "java heap should be initialized");
6807 if (CheckCompressedOops) {
6808 Label ok;
6809 push(rscratch1); // cmpptr trashes rscratch1
6810 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6811 jcc(Assembler::equal, ok);
6812 STOP(msg);
6813 bind(ok);
6814 pop(rscratch1);
6815 }
6816 }
6817 #endif
6818
6819 // Algorithm must match oop.inline.hpp encode_heap_oop.
6820 void MacroAssembler::encode_heap_oop(Register r) {
6821 #ifdef ASSERT
6822 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6823 #endif
6824 verify_oop(r, "broken oop in encode_heap_oop");
6825 if (Universe::narrow_oop_base() == NULL) {
6826 if (Universe::narrow_oop_shift() != 0) {
6827 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6828 shrq(r, LogMinObjAlignmentInBytes);
6829 }
6830 return;
6831 }
6832 testq(r, r);
6833 cmovq(Assembler::equal, r, r12_heapbase);
6834 subq(r, r12_heapbase);
6835 shrq(r, LogMinObjAlignmentInBytes);
6836 }
6837
6838 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6839 #ifdef ASSERT
6840 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6841 if (CheckCompressedOops) {
6842 Label ok;
6843 testq(r, r);
6844 jcc(Assembler::notEqual, ok);
6845 STOP("null oop passed to encode_heap_oop_not_null");
6846 bind(ok);
6847 }
6848 #endif
6849 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6850 if (Universe::narrow_oop_base() != NULL) {
6851 subq(r, r12_heapbase);
6852 }
6853 if (Universe::narrow_oop_shift() != 0) {
6854 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6855 shrq(r, LogMinObjAlignmentInBytes);
6856 }
6857 }
6858
6859 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6860 #ifdef ASSERT
6861 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6862 if (CheckCompressedOops) {
6863 Label ok;
6864 testq(src, src);
6865 jcc(Assembler::notEqual, ok);
6866 STOP("null oop passed to encode_heap_oop_not_null2");
6867 bind(ok);
6868 }
6869 #endif
6870 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6871 if (dst != src) {
6872 movq(dst, src);
6873 }
6874 if (Universe::narrow_oop_base() != NULL) {
6875 subq(dst, r12_heapbase);
6876 }
6877 if (Universe::narrow_oop_shift() != 0) {
6878 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6879 shrq(dst, LogMinObjAlignmentInBytes);
6880 }
6881 }
6882
6883 void MacroAssembler::decode_heap_oop(Register r) {
6884 #ifdef ASSERT
6885 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6886 #endif
6887 if (Universe::narrow_oop_base() == NULL) {
6888 if (Universe::narrow_oop_shift() != 0) {
6889 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6890 shlq(r, LogMinObjAlignmentInBytes);
6891 }
6892 } else {
6893 Label done;
6894 shlq(r, LogMinObjAlignmentInBytes);
6895 jccb(Assembler::equal, done);
6896 addq(r, r12_heapbase);
6897 bind(done);
6898 }
6899 verify_oop(r, "broken oop in decode_heap_oop");
6900 }
6901
6902 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6903 // Note: it will change flags
6904 assert (UseCompressedOops, "should only be used for compressed headers");
6905 assert (Universe::heap() != NULL, "java heap should be initialized");
6906 // Cannot assert, unverified entry point counts instructions (see .ad file)
6907 // vtableStubs also counts instructions in pd_code_size_limit.
6908 // Also do not verify_oop as this is called by verify_oop.
6909 if (Universe::narrow_oop_shift() != 0) {
6910 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6911 shlq(r, LogMinObjAlignmentInBytes);
6912 if (Universe::narrow_oop_base() != NULL) {
6913 addq(r, r12_heapbase);
6914 }
6915 } else {
6916 assert (Universe::narrow_oop_base() == NULL, "sanity");
6917 }
6918 }
6919
6920 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6921 // Note: it will change flags
6922 assert (UseCompressedOops, "should only be used for compressed headers");
6923 assert (Universe::heap() != NULL, "java heap should be initialized");
6924 // Cannot assert, unverified entry point counts instructions (see .ad file)
6925 // vtableStubs also counts instructions in pd_code_size_limit.
6926 // Also do not verify_oop as this is called by verify_oop.
6927 if (Universe::narrow_oop_shift() != 0) {
6928 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6929 if (LogMinObjAlignmentInBytes == Address::times_8) {
6930 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6931 } else {
6932 if (dst != src) {
6933 movq(dst, src);
6934 }
6935 shlq(dst, LogMinObjAlignmentInBytes);
6936 if (Universe::narrow_oop_base() != NULL) {
6937 addq(dst, r12_heapbase);
6938 }
6939 }
6940 } else {
6941 assert (Universe::narrow_oop_base() == NULL, "sanity");
6942 if (dst != src) {
6943 movq(dst, src);
6944 }
6945 }
6946 }
6947
6948 void MacroAssembler::encode_klass_not_null(Register r) {
6949 if (Universe::narrow_klass_base() != NULL) {
6950 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6951 assert(r != r12_heapbase, "Encoding a klass in r12");
6952 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6953 subq(r, r12_heapbase);
6954 }
6955 if (Universe::narrow_klass_shift() != 0) {
6956 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6957 shrq(r, LogKlassAlignmentInBytes);
6958 }
6959 if (Universe::narrow_klass_base() != NULL) {
6960 reinit_heapbase();
6961 }
6962 }
6963
6964 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6965 if (dst == src) {
6966 encode_klass_not_null(src);
6967 } else {
6968 if (Universe::narrow_klass_base() != NULL) {
6969 mov64(dst, (int64_t)Universe::narrow_klass_base());
6970 negq(dst);
6971 addq(dst, src);
6972 } else {
6973 movptr(dst, src);
6974 }
6975 if (Universe::narrow_klass_shift() != 0) {
6976 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6977 shrq(dst, LogKlassAlignmentInBytes);
6978 }
6979 }
6980 }
6981
6982 // Function instr_size_for_decode_klass_not_null() counts the instructions
6983 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6984 // when (Universe::heap() != NULL). Hence, if the instructions they
6985 // generate change, then this method needs to be updated.
6986 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6987 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6988 if (Universe::narrow_klass_base() != NULL) {
6989 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6990 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6991 } else {
6992 // longest load decode klass function, mov64, leaq
6993 return 16;
6994 }
6995 }
6996
6997 // !!! If the instructions that get generated here change then function
6998 // instr_size_for_decode_klass_not_null() needs to get updated.
6999 void MacroAssembler::decode_klass_not_null(Register r) {
7000 // Note: it will change flags
7001 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7002 assert(r != r12_heapbase, "Decoding a klass in r12");
7003 // Cannot assert, unverified entry point counts instructions (see .ad file)
7004 // vtableStubs also counts instructions in pd_code_size_limit.
7005 // Also do not verify_oop as this is called by verify_oop.
7006 if (Universe::narrow_klass_shift() != 0) {
7007 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
7008 shlq(r, LogKlassAlignmentInBytes);
7009 }
7010 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
7011 if (Universe::narrow_klass_base() != NULL) {
7012 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
7013 addq(r, r12_heapbase);
7014 reinit_heapbase();
7015 }
7016 }
7017
7018 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
7019 // Note: it will change flags
7020 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7021 if (dst == src) {
7022 decode_klass_not_null(dst);
7023 } else {
7024 // Cannot assert, unverified entry point counts instructions (see .ad file)
7025 // vtableStubs also counts instructions in pd_code_size_limit.
7026 // Also do not verify_oop as this is called by verify_oop.
7027 mov64(dst, (int64_t)Universe::narrow_klass_base());
7028 if (Universe::narrow_klass_shift() != 0) {
7029 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
7030 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
7031 leaq(dst, Address(dst, src, Address::times_8, 0));
7032 } else {
7033 addq(dst, src);
7034 }
7035 }
7036 }
7037
7038 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
7039 assert (UseCompressedOops, "should only be used for compressed headers");
7040 assert (Universe::heap() != NULL, "java heap should be initialized");
7041 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7042 int oop_index = oop_recorder()->find_index(obj);
7043 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7044 mov_narrow_oop(dst, oop_index, rspec);
7045 }
7046
7047 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
7048 assert (UseCompressedOops, "should only be used for compressed headers");
7049 assert (Universe::heap() != NULL, "java heap should be initialized");
7050 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7051 int oop_index = oop_recorder()->find_index(obj);
7052 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7053 mov_narrow_oop(dst, oop_index, rspec);
7054 }
7055
7056 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
7057 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7058 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7059 int klass_index = oop_recorder()->find_index(k);
7060 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7061 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7062 }
7063
7064 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
7065 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7066 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7067 int klass_index = oop_recorder()->find_index(k);
7068 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7069 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
7070 }
7071
7072 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
7073 assert (UseCompressedOops, "should only be used for compressed headers");
7074 assert (Universe::heap() != NULL, "java heap should be initialized");
7075 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7076 int oop_index = oop_recorder()->find_index(obj);
7077 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7078 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7079 }
7080
7081 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
7082 assert (UseCompressedOops, "should only be used for compressed headers");
7083 assert (Universe::heap() != NULL, "java heap should be initialized");
7084 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7085 int oop_index = oop_recorder()->find_index(obj);
7086 RelocationHolder rspec = oop_Relocation::spec(oop_index);
7087 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
7088 }
7089
7090 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
7091 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7092 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7093 int klass_index = oop_recorder()->find_index(k);
7094 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7095 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7096 }
7097
7098 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
7099 assert (UseCompressedClassPointers, "should only be used for compressed headers");
7100 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
7101 int klass_index = oop_recorder()->find_index(k);
7102 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
7103 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
7104 }
7105
7106 void MacroAssembler::reinit_heapbase() {
7107 if (UseCompressedOops || UseCompressedClassPointers) {
7108 if (Universe::heap() != NULL) {
7109 if (Universe::narrow_oop_base() == NULL) {
7110 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
7111 } else {
7112 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
7113 }
7114 } else {
7115 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
7116 }
7117 }
7118 }
7119
7120 #endif // _LP64
7121
7122
7123 // C2 compiled method's prolog code.
7124 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
7125
7126 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7127 // NativeJump::patch_verified_entry will be able to patch out the entry
7128 // code safely. The push to verify stack depth is ok at 5 bytes,
7129 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7130 // stack bang then we must use the 6 byte frame allocation even if
7131 // we have no frame. :-(
7132 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7133
7134 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7135 // Remove word for return addr
7136 framesize -= wordSize;
7137 stack_bang_size -= wordSize;
7138
7139 // Calls to C2R adapters often do not accept exceptional returns.
7140 // We require that their callers must bang for them. But be careful, because
7141 // some VM calls (such as call site linkage) can use several kilobytes of
7142 // stack. But the stack safety zone should account for that.
7143 // See bugs 4446381, 4468289, 4497237.
7144 if (stack_bang_size > 0) {
7145 generate_stack_overflow_check(stack_bang_size);
7146
7147 // We always push rbp, so that on return to interpreter rbp, will be
7148 // restored correctly and we can correct the stack.
7149 push(rbp);
7150 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7151 if (PreserveFramePointer) {
7152 mov(rbp, rsp);
7153 }
7154 // Remove word for ebp
7155 framesize -= wordSize;
7156
7157 // Create frame
7158 if (framesize) {
7159 subptr(rsp, framesize);
7160 }
7161 } else {
7162 // Create frame (force generation of a 4 byte immediate value)
7163 subptr_imm32(rsp, framesize);
7164
7165 // Save RBP register now.
7166 framesize -= wordSize;
7167 movptr(Address(rsp, framesize), rbp);
7168 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7169 if (PreserveFramePointer) {
7170 movptr(rbp, rsp);
7171 if (framesize > 0) {
7172 addptr(rbp, framesize);
7173 }
7174 }
7175 }
7176
7177 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7178 framesize -= wordSize;
7179 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7180 }
7181
7182 #ifndef _LP64
7183 // If method sets FPU control word do it now
7184 if (fp_mode_24b) {
7185 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7186 }
7187 if (UseSSE >= 2 && VerifyFPU) {
7188 verify_FPU(0, "FPU stack must be clean on entry");
7189 }
7190 #endif
7191
7192 #ifdef ASSERT
7193 if (VerifyStackAtCalls) {
7194 Label L;
7195 push(rax);
7196 mov(rax, rsp);
7197 andptr(rax, StackAlignmentInBytes-1);
7198 cmpptr(rax, StackAlignmentInBytes-wordSize);
7199 pop(rax);
7200 jcc(Assembler::equal, L);
7201 STOP("Stack is not properly aligned!");
7202 bind(L);
7203 }
7204 #endif
7205
7206 }
7207
7208 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp) {
7209 // cnt - number of qwords (8-byte words).
7210 // base - start address, qword aligned.
7211 assert(base==rdi, "base register must be edi for rep stos");
7212 assert(tmp==rax, "tmp register must be eax for rep stos");
7213 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7214
7215 xorptr(tmp, tmp);
7216 if (UseFastStosb) {
7217 shlptr(cnt,3); // convert to number of bytes
7218 rep_stosb();
7219 } else {
7220 NOT_LP64(shlptr(cnt,1);) // convert to number of dwords for 32-bit VM
7221 rep_stos();
7222 }
7223 }
7224
7225 #ifdef COMPILER2
7226
7227 // IndexOf for constant substrings with size >= 8 chars
7228 // which don't need to be loaded through stack.
7229 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7230 Register cnt1, Register cnt2,
7231 int int_cnt2, Register result,
7232 XMMRegister vec, Register tmp,
7233 int ae) {
7234 ShortBranchVerifier sbv(this);
7235 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7236 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7237 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7238
7239 // This method uses the pcmpestri instruction with bound registers
7240 // inputs:
7241 // xmm - substring
7242 // rax - substring length (elements count)
7243 // mem - scanned string
7244 // rdx - string length (elements count)
7245 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7246 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7247 // outputs:
7248 // rcx - matched index in string
7249 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7250 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7251 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7252 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7253 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7254
7255 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7256 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7257 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7258
7259 // Note, inline_string_indexOf() generates checks:
7260 // if (substr.count > string.count) return -1;
7261 // if (substr.count == 0) return 0;
7262 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7263
7264 // Load substring.
7265 if (ae == StrIntrinsicNode::UL) {
7266 pmovzxbw(vec, Address(str2, 0));
7267 } else {
7268 movdqu(vec, Address(str2, 0));
7269 }
7270 movl(cnt2, int_cnt2);
7271 movptr(result, str1); // string addr
7272
7273 if (int_cnt2 > stride) {
7274 jmpb(SCAN_TO_SUBSTR);
7275
7276 // Reload substr for rescan, this code
7277 // is executed only for large substrings (> 8 chars)
7278 bind(RELOAD_SUBSTR);
7279 if (ae == StrIntrinsicNode::UL) {
7280 pmovzxbw(vec, Address(str2, 0));
7281 } else {
7282 movdqu(vec, Address(str2, 0));
7283 }
7284 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7285
7286 bind(RELOAD_STR);
7287 // We came here after the beginning of the substring was
7288 // matched but the rest of it was not so we need to search
7289 // again. Start from the next element after the previous match.
7290
7291 // cnt2 is number of substring reminding elements and
7292 // cnt1 is number of string reminding elements when cmp failed.
7293 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7294 subl(cnt1, cnt2);
7295 addl(cnt1, int_cnt2);
7296 movl(cnt2, int_cnt2); // Now restore cnt2
7297
7298 decrementl(cnt1); // Shift to next element
7299 cmpl(cnt1, cnt2);
7300 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7301
7302 addptr(result, (1<<scale1));
7303
7304 } // (int_cnt2 > 8)
7305
7306 // Scan string for start of substr in 16-byte vectors
7307 bind(SCAN_TO_SUBSTR);
7308 pcmpestri(vec, Address(result, 0), mode);
7309 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7310 subl(cnt1, stride);
7311 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7312 cmpl(cnt1, cnt2);
7313 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7314 addptr(result, 16);
7315 jmpb(SCAN_TO_SUBSTR);
7316
7317 // Found a potential substr
7318 bind(FOUND_CANDIDATE);
7319 // Matched whole vector if first element matched (tmp(rcx) == 0).
7320 if (int_cnt2 == stride) {
7321 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7322 } else { // int_cnt2 > 8
7323 jccb(Assembler::overflow, FOUND_SUBSTR);
7324 }
7325 // After pcmpestri tmp(rcx) contains matched element index
7326 // Compute start addr of substr
7327 lea(result, Address(result, tmp, scale1));
7328
7329 // Make sure string is still long enough
7330 subl(cnt1, tmp);
7331 cmpl(cnt1, cnt2);
7332 if (int_cnt2 == stride) {
7333 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7334 } else { // int_cnt2 > 8
7335 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7336 }
7337 // Left less then substring.
7338
7339 bind(RET_NOT_FOUND);
7340 movl(result, -1);
7341 jmpb(EXIT);
7342
7343 if (int_cnt2 > stride) {
7344 // This code is optimized for the case when whole substring
7345 // is matched if its head is matched.
7346 bind(MATCH_SUBSTR_HEAD);
7347 pcmpestri(vec, Address(result, 0), mode);
7348 // Reload only string if does not match
7349 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0
7350
7351 Label CONT_SCAN_SUBSTR;
7352 // Compare the rest of substring (> 8 chars).
7353 bind(FOUND_SUBSTR);
7354 // First 8 chars are already matched.
7355 negptr(cnt2);
7356 addptr(cnt2, stride);
7357
7358 bind(SCAN_SUBSTR);
7359 subl(cnt1, stride);
7360 cmpl(cnt2, -stride); // Do not read beyond substring
7361 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7362 // Back-up strings to avoid reading beyond substring:
7363 // cnt1 = cnt1 - cnt2 + 8
7364 addl(cnt1, cnt2); // cnt2 is negative
7365 addl(cnt1, stride);
7366 movl(cnt2, stride); negptr(cnt2);
7367 bind(CONT_SCAN_SUBSTR);
7368 if (int_cnt2 < (int)G) {
7369 int tail_off1 = int_cnt2<<scale1;
7370 int tail_off2 = int_cnt2<<scale2;
7371 if (ae == StrIntrinsicNode::UL) {
7372 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7373 } else {
7374 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7375 }
7376 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7377 } else {
7378 // calculate index in register to avoid integer overflow (int_cnt2*2)
7379 movl(tmp, int_cnt2);
7380 addptr(tmp, cnt2);
7381 if (ae == StrIntrinsicNode::UL) {
7382 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7383 } else {
7384 movdqu(vec, Address(str2, tmp, scale2, 0));
7385 }
7386 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7387 }
7388 // Need to reload strings pointers if not matched whole vector
7389 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7390 addptr(cnt2, stride);
7391 jcc(Assembler::negative, SCAN_SUBSTR);
7392 // Fall through if found full substring
7393
7394 } // (int_cnt2 > 8)
7395
7396 bind(RET_FOUND);
7397 // Found result if we matched full small substring.
7398 // Compute substr offset
7399 subptr(result, str1);
7400 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7401 shrl(result, 1); // index
7402 }
7403 bind(EXIT);
7404
7405 } // string_indexofC8
7406
7407 // Small strings are loaded through stack if they cross page boundary.
7408 void MacroAssembler::string_indexof(Register str1, Register str2,
7409 Register cnt1, Register cnt2,
7410 int int_cnt2, Register result,
7411 XMMRegister vec, Register tmp,
7412 int ae) {
7413 ShortBranchVerifier sbv(this);
7414 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7415 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7416 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7417
7418 //
7419 // int_cnt2 is length of small (< 8 chars) constant substring
7420 // or (-1) for non constant substring in which case its length
7421 // is in cnt2 register.
7422 //
7423 // Note, inline_string_indexOf() generates checks:
7424 // if (substr.count > string.count) return -1;
7425 // if (substr.count == 0) return 0;
7426 //
7427 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7428 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7429 // This method uses the pcmpestri instruction with bound registers
7430 // inputs:
7431 // xmm - substring
7432 // rax - substring length (elements count)
7433 // mem - scanned string
7434 // rdx - string length (elements count)
7435 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7436 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7437 // outputs:
7438 // rcx - matched index in string
7439 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7440 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7441 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7442 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7443
7444 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7445 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7446 FOUND_CANDIDATE;
7447
7448 { //========================================================
7449 // We don't know where these strings are located
7450 // and we can't read beyond them. Load them through stack.
7451 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7452
7453 movptr(tmp, rsp); // save old SP
7454
7455 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7456 if (int_cnt2 == (1>>scale2)) { // One byte
7457 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7458 load_unsigned_byte(result, Address(str2, 0));
7459 movdl(vec, result); // move 32 bits
7460 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7461 // Not enough header space in 32-bit VM: 12+3 = 15.
7462 movl(result, Address(str2, -1));
7463 shrl(result, 8);
7464 movdl(vec, result); // move 32 bits
7465 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7466 load_unsigned_short(result, Address(str2, 0));
7467 movdl(vec, result); // move 32 bits
7468 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7469 movdl(vec, Address(str2, 0)); // move 32 bits
7470 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7471 movq(vec, Address(str2, 0)); // move 64 bits
7472 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7473 // Array header size is 12 bytes in 32-bit VM
7474 // + 6 bytes for 3 chars == 18 bytes,
7475 // enough space to load vec and shift.
7476 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7477 if (ae == StrIntrinsicNode::UL) {
7478 int tail_off = int_cnt2-8;
7479 pmovzxbw(vec, Address(str2, tail_off));
7480 psrldq(vec, -2*tail_off);
7481 }
7482 else {
7483 int tail_off = int_cnt2*(1<<scale2);
7484 movdqu(vec, Address(str2, tail_off-16));
7485 psrldq(vec, 16-tail_off);
7486 }
7487 }
7488 } else { // not constant substring
7489 cmpl(cnt2, stride);
7490 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7491
7492 // We can read beyond string if srt+16 does not cross page boundary
7493 // since heaps are aligned and mapped by pages.
7494 assert(os::vm_page_size() < (int)G, "default page should be small");
7495 movl(result, str2); // We need only low 32 bits
7496 andl(result, (os::vm_page_size()-1));
7497 cmpl(result, (os::vm_page_size()-16));
7498 jccb(Assembler::belowEqual, CHECK_STR);
7499
7500 // Move small strings to stack to allow load 16 bytes into vec.
7501 subptr(rsp, 16);
7502 int stk_offset = wordSize-(1<<scale2);
7503 push(cnt2);
7504
7505 bind(COPY_SUBSTR);
7506 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7507 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7508 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7509 } else if (ae == StrIntrinsicNode::UU) {
7510 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7511 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7512 }
7513 decrement(cnt2);
7514 jccb(Assembler::notZero, COPY_SUBSTR);
7515
7516 pop(cnt2);
7517 movptr(str2, rsp); // New substring address
7518 } // non constant
7519
7520 bind(CHECK_STR);
7521 cmpl(cnt1, stride);
7522 jccb(Assembler::aboveEqual, BIG_STRINGS);
7523
7524 // Check cross page boundary.
7525 movl(result, str1); // We need only low 32 bits
7526 andl(result, (os::vm_page_size()-1));
7527 cmpl(result, (os::vm_page_size()-16));
7528 jccb(Assembler::belowEqual, BIG_STRINGS);
7529
7530 subptr(rsp, 16);
7531 int stk_offset = -(1<<scale1);
7532 if (int_cnt2 < 0) { // not constant
7533 push(cnt2);
7534 stk_offset += wordSize;
7535 }
7536 movl(cnt2, cnt1);
7537
7538 bind(COPY_STR);
7539 if (ae == StrIntrinsicNode::LL) {
7540 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7541 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7542 } else {
7543 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7544 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7545 }
7546 decrement(cnt2);
7547 jccb(Assembler::notZero, COPY_STR);
7548
7549 if (int_cnt2 < 0) { // not constant
7550 pop(cnt2);
7551 }
7552 movptr(str1, rsp); // New string address
7553
7554 bind(BIG_STRINGS);
7555 // Load substring.
7556 if (int_cnt2 < 0) { // -1
7557 if (ae == StrIntrinsicNode::UL) {
7558 pmovzxbw(vec, Address(str2, 0));
7559 } else {
7560 movdqu(vec, Address(str2, 0));
7561 }
7562 push(cnt2); // substr count
7563 push(str2); // substr addr
7564 push(str1); // string addr
7565 } else {
7566 // Small (< 8 chars) constant substrings are loaded already.
7567 movl(cnt2, int_cnt2);
7568 }
7569 push(tmp); // original SP
7570
7571 } // Finished loading
7572
7573 //========================================================
7574 // Start search
7575 //
7576
7577 movptr(result, str1); // string addr
7578
7579 if (int_cnt2 < 0) { // Only for non constant substring
7580 jmpb(SCAN_TO_SUBSTR);
7581
7582 // SP saved at sp+0
7583 // String saved at sp+1*wordSize
7584 // Substr saved at sp+2*wordSize
7585 // Substr count saved at sp+3*wordSize
7586
7587 // Reload substr for rescan, this code
7588 // is executed only for large substrings (> 8 chars)
7589 bind(RELOAD_SUBSTR);
7590 movptr(str2, Address(rsp, 2*wordSize));
7591 movl(cnt2, Address(rsp, 3*wordSize));
7592 if (ae == StrIntrinsicNode::UL) {
7593 pmovzxbw(vec, Address(str2, 0));
7594 } else {
7595 movdqu(vec, Address(str2, 0));
7596 }
7597 // We came here after the beginning of the substring was
7598 // matched but the rest of it was not so we need to search
7599 // again. Start from the next element after the previous match.
7600 subptr(str1, result); // Restore counter
7601 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7602 shrl(str1, 1);
7603 }
7604 addl(cnt1, str1);
7605 decrementl(cnt1); // Shift to next element
7606 cmpl(cnt1, cnt2);
7607 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7608
7609 addptr(result, (1<<scale1));
7610 } // non constant
7611
7612 // Scan string for start of substr in 16-byte vectors
7613 bind(SCAN_TO_SUBSTR);
7614 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7615 pcmpestri(vec, Address(result, 0), mode);
7616 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7617 subl(cnt1, stride);
7618 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7619 cmpl(cnt1, cnt2);
7620 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7621 addptr(result, 16);
7622
7623 bind(ADJUST_STR);
7624 cmpl(cnt1, stride); // Do not read beyond string
7625 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7626 // Back-up string to avoid reading beyond string.
7627 lea(result, Address(result, cnt1, scale1, -16));
7628 movl(cnt1, stride);
7629 jmpb(SCAN_TO_SUBSTR);
7630
7631 // Found a potential substr
7632 bind(FOUND_CANDIDATE);
7633 // After pcmpestri tmp(rcx) contains matched element index
7634
7635 // Make sure string is still long enough
7636 subl(cnt1, tmp);
7637 cmpl(cnt1, cnt2);
7638 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7639 // Left less then substring.
7640
7641 bind(RET_NOT_FOUND);
7642 movl(result, -1);
7643 jmpb(CLEANUP);
7644
7645 bind(FOUND_SUBSTR);
7646 // Compute start addr of substr
7647 lea(result, Address(result, tmp, scale1));
7648 if (int_cnt2 > 0) { // Constant substring
7649 // Repeat search for small substring (< 8 chars)
7650 // from new point without reloading substring.
7651 // Have to check that we don't read beyond string.
7652 cmpl(tmp, stride-int_cnt2);
7653 jccb(Assembler::greater, ADJUST_STR);
7654 // Fall through if matched whole substring.
7655 } else { // non constant
7656 assert(int_cnt2 == -1, "should be != 0");
7657
7658 addl(tmp, cnt2);
7659 // Found result if we matched whole substring.
7660 cmpl(tmp, stride);
7661 jccb(Assembler::lessEqual, RET_FOUND);
7662
7663 // Repeat search for small substring (<= 8 chars)
7664 // from new point 'str1' without reloading substring.
7665 cmpl(cnt2, stride);
7666 // Have to check that we don't read beyond string.
7667 jccb(Assembler::lessEqual, ADJUST_STR);
7668
7669 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7670 // Compare the rest of substring (> 8 chars).
7671 movptr(str1, result);
7672
7673 cmpl(tmp, cnt2);
7674 // First 8 chars are already matched.
7675 jccb(Assembler::equal, CHECK_NEXT);
7676
7677 bind(SCAN_SUBSTR);
7678 pcmpestri(vec, Address(str1, 0), mode);
7679 // Need to reload strings pointers if not matched whole vector
7680 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7681
7682 bind(CHECK_NEXT);
7683 subl(cnt2, stride);
7684 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7685 addptr(str1, 16);
7686 if (ae == StrIntrinsicNode::UL) {
7687 addptr(str2, 8);
7688 } else {
7689 addptr(str2, 16);
7690 }
7691 subl(cnt1, stride);
7692 cmpl(cnt2, stride); // Do not read beyond substring
7693 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7694 // Back-up strings to avoid reading beyond substring.
7695
7696 if (ae == StrIntrinsicNode::UL) {
7697 lea(str2, Address(str2, cnt2, scale2, -8));
7698 lea(str1, Address(str1, cnt2, scale1, -16));
7699 } else {
7700 lea(str2, Address(str2, cnt2, scale2, -16));
7701 lea(str1, Address(str1, cnt2, scale1, -16));
7702 }
7703 subl(cnt1, cnt2);
7704 movl(cnt2, stride);
7705 addl(cnt1, stride);
7706 bind(CONT_SCAN_SUBSTR);
7707 if (ae == StrIntrinsicNode::UL) {
7708 pmovzxbw(vec, Address(str2, 0));
7709 } else {
7710 movdqu(vec, Address(str2, 0));
7711 }
7712 jmpb(SCAN_SUBSTR);
7713
7714 bind(RET_FOUND_LONG);
7715 movptr(str1, Address(rsp, wordSize));
7716 } // non constant
7717
7718 bind(RET_FOUND);
7719 // Compute substr offset
7720 subptr(result, str1);
7721 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7722 shrl(result, 1); // index
7723 }
7724 bind(CLEANUP);
7725 pop(rsp); // restore SP
7726
7727 } // string_indexof
7728
7729 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7730 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7731 ShortBranchVerifier sbv(this);
7732 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7733 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7734
7735 int stride = 8;
7736
7737 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7738 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7739 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7740 FOUND_SEQ_CHAR, DONE_LABEL;
7741
7742 movptr(result, str1);
7743 if (UseAVX >= 2) {
7744 cmpl(cnt1, stride);
7745 jccb(Assembler::less, SCAN_TO_CHAR_LOOP);
7746 cmpl(cnt1, 2*stride);
7747 jccb(Assembler::less, SCAN_TO_8_CHAR_INIT);
7748 movdl(vec1, ch);
7749 vpbroadcastw(vec1, vec1);
7750 vpxor(vec2, vec2);
7751 movl(tmp, cnt1);
7752 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7753 andl(cnt1,0x0000000F); //tail count (in chars)
7754
7755 bind(SCAN_TO_16_CHAR_LOOP);
7756 vmovdqu(vec3, Address(result, 0));
7757 vpcmpeqw(vec3, vec3, vec1, 1);
7758 vptest(vec2, vec3);
7759 jcc(Assembler::carryClear, FOUND_CHAR);
7760 addptr(result, 32);
7761 subl(tmp, 2*stride);
7762 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7763 jmp(SCAN_TO_8_CHAR);
7764 bind(SCAN_TO_8_CHAR_INIT);
7765 movdl(vec1, ch);
7766 pshuflw(vec1, vec1, 0x00);
7767 pshufd(vec1, vec1, 0);
7768 pxor(vec2, vec2);
7769 }
7770 bind(SCAN_TO_8_CHAR);
7771 cmpl(cnt1, stride);
7772 if (UseAVX >= 2) {
7773 jccb(Assembler::less, SCAN_TO_CHAR);
7774 } else {
7775 jccb(Assembler::less, SCAN_TO_CHAR_LOOP);
7776 movdl(vec1, ch);
7777 pshuflw(vec1, vec1, 0x00);
7778 pshufd(vec1, vec1, 0);
7779 pxor(vec2, vec2);
7780 }
7781 movl(tmp, cnt1);
7782 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7783 andl(cnt1,0x00000007); //tail count (in chars)
7784
7785 bind(SCAN_TO_8_CHAR_LOOP);
7786 movdqu(vec3, Address(result, 0));
7787 pcmpeqw(vec3, vec1);
7788 ptest(vec2, vec3);
7789 jcc(Assembler::carryClear, FOUND_CHAR);
7790 addptr(result, 16);
7791 subl(tmp, stride);
7792 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7793 bind(SCAN_TO_CHAR);
7794 testl(cnt1, cnt1);
7795 jcc(Assembler::zero, RET_NOT_FOUND);
7796 bind(SCAN_TO_CHAR_LOOP);
7797 load_unsigned_short(tmp, Address(result, 0));
7798 cmpl(ch, tmp);
7799 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7800 addptr(result, 2);
7801 subl(cnt1, 1);
7802 jccb(Assembler::zero, RET_NOT_FOUND);
7803 jmp(SCAN_TO_CHAR_LOOP);
7804
7805 bind(RET_NOT_FOUND);
7806 movl(result, -1);
7807 jmpb(DONE_LABEL);
7808
7809 bind(FOUND_CHAR);
7810 if (UseAVX >= 2) {
7811 vpmovmskb(tmp, vec3);
7812 } else {
7813 pmovmskb(tmp, vec3);
7814 }
7815 bsfl(ch, tmp);
7816 addl(result, ch);
7817
7818 bind(FOUND_SEQ_CHAR);
7819 subptr(result, str1);
7820 shrl(result, 1);
7821
7822 bind(DONE_LABEL);
7823 } // string_indexof_char
7824
7825 // helper function for string_compare
7826 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7827 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7828 Address::ScaleFactor scale2, Register index, int ae) {
7829 if (ae == StrIntrinsicNode::LL) {
7830 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7831 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7832 } else if (ae == StrIntrinsicNode::UU) {
7833 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7834 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7835 } else {
7836 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7837 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7838 }
7839 }
7840
7841 // Compare strings, used for char[] and byte[].
7842 void MacroAssembler::string_compare(Register str1, Register str2,
7843 Register cnt1, Register cnt2, Register result,
7844 XMMRegister vec1, int ae) {
7845 ShortBranchVerifier sbv(this);
7846 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7847 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7848 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7849 int stride2x2 = 0x40;
7850 Address::ScaleFactor scale, scale1, scale2;
7851
7852 if (ae != StrIntrinsicNode::LL) {
7853 stride2x2 = 0x20;
7854 }
7855
7856 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7857 shrl(cnt2, 1);
7858 }
7859 // Compute the minimum of the string lengths and the
7860 // difference of the string lengths (stack).
7861 // Do the conditional move stuff
7862 movl(result, cnt1);
7863 subl(cnt1, cnt2);
7864 push(cnt1);
7865 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7866
7867 // Is the minimum length zero?
7868 testl(cnt2, cnt2);
7869 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7870 if (ae == StrIntrinsicNode::LL) {
7871 // Load first bytes
7872 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7873 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7874 } else if (ae == StrIntrinsicNode::UU) {
7875 // Load first characters
7876 load_unsigned_short(result, Address(str1, 0));
7877 load_unsigned_short(cnt1, Address(str2, 0));
7878 } else {
7879 load_unsigned_byte(result, Address(str1, 0));
7880 load_unsigned_short(cnt1, Address(str2, 0));
7881 }
7882 subl(result, cnt1);
7883 jcc(Assembler::notZero, POP_LABEL);
7884
7885 if (ae == StrIntrinsicNode::UU) {
7886 // Divide length by 2 to get number of chars
7887 shrl(cnt2, 1);
7888 }
7889 cmpl(cnt2, 1);
7890 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7891
7892 // Check if the strings start at the same location and setup scale and stride
7893 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7894 cmpptr(str1, str2);
7895 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7896 if (ae == StrIntrinsicNode::LL) {
7897 scale = Address::times_1;
7898 stride = 16;
7899 } else {
7900 scale = Address::times_2;
7901 stride = 8;
7902 }
7903 } else {
7904 scale = Address::no_scale; // not used
7905 scale1 = Address::times_1;
7906 scale2 = Address::times_2;
7907 stride = 8;
7908 }
7909
7910 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7911 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
7912 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7913 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7914 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7915 Label COMPARE_TAIL_LONG;
7916 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7917
7918 int pcmpmask = 0x19;
7919 if (ae == StrIntrinsicNode::LL) {
7920 pcmpmask &= ~0x01;
7921 }
7922
7923 // Setup to compare 16-chars (32-bytes) vectors,
7924 // start from first character again because it has aligned address.
7925 if (ae == StrIntrinsicNode::LL) {
7926 stride2 = 32;
7927 } else {
7928 stride2 = 16;
7929 }
7930 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7931 adr_stride = stride << scale;
7932 } else {
7933 adr_stride1 = 8; //stride << scale1;
7934 adr_stride2 = 16; //stride << scale2;
7935 }
7936
7937 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7938 // rax and rdx are used by pcmpestri as elements counters
7939 movl(result, cnt2);
7940 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7941 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7942
7943 // fast path : compare first 2 8-char vectors.
7944 bind(COMPARE_16_CHARS);
7945 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7946 movdqu(vec1, Address(str1, 0));
7947 } else {
7948 pmovzxbw(vec1, Address(str1, 0));
7949 }
7950 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7951 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7952
7953 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7954 movdqu(vec1, Address(str1, adr_stride));
7955 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7956 } else {
7957 pmovzxbw(vec1, Address(str1, adr_stride1));
7958 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7959 }
7960 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7961 addl(cnt1, stride);
7962
7963 // Compare the characters at index in cnt1
7964 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7965 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7966 subl(result, cnt2);
7967 jmp(POP_LABEL);
7968
7969 // Setup the registers to start vector comparison loop
7970 bind(COMPARE_WIDE_VECTORS);
7971 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7972 lea(str1, Address(str1, result, scale));
7973 lea(str2, Address(str2, result, scale));
7974 } else {
7975 lea(str1, Address(str1, result, scale1));
7976 lea(str2, Address(str2, result, scale2));
7977 }
7978 subl(result, stride2);
7979 subl(cnt2, stride2);
7980 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7981 negptr(result);
7982
7983 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7984 bind(COMPARE_WIDE_VECTORS_LOOP);
7985
7986 #ifdef _LP64
7987 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7988 cmpl(cnt2, stride2x2);
7989 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7990 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7991 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7992
7993 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7994 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7995 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7996 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7997 } else {
7998 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7999 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
8000 }
8001 kortestql(k7, k7);
8002 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
8003 addptr(result, stride2x2); // update since we already compared at this addr
8004 subl(cnt2, stride2x2); // and sub the size too
8005 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8006
8007 vpxor(vec1, vec1);
8008 jmpb(COMPARE_WIDE_TAIL);
8009 }//if (VM_Version::supports_avx512vlbw())
8010 #endif // _LP64
8011
8012
8013 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8014 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8015 vmovdqu(vec1, Address(str1, result, scale));
8016 vpxor(vec1, Address(str2, result, scale));
8017 } else {
8018 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
8019 vpxor(vec1, Address(str2, result, scale2));
8020 }
8021 vptest(vec1, vec1);
8022 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
8023 addptr(result, stride2);
8024 subl(cnt2, stride2);
8025 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
8026 // clean upper bits of YMM registers
8027 vpxor(vec1, vec1);
8028
8029 // compare wide vectors tail
8030 bind(COMPARE_WIDE_TAIL);
8031 testptr(result, result);
8032 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8033
8034 movl(result, stride2);
8035 movl(cnt2, result);
8036 negptr(result);
8037 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8038
8039 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
8040 bind(VECTOR_NOT_EQUAL);
8041 // clean upper bits of YMM registers
8042 vpxor(vec1, vec1);
8043 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8044 lea(str1, Address(str1, result, scale));
8045 lea(str2, Address(str2, result, scale));
8046 } else {
8047 lea(str1, Address(str1, result, scale1));
8048 lea(str2, Address(str2, result, scale2));
8049 }
8050 jmp(COMPARE_16_CHARS);
8051
8052 // Compare tail chars, length between 1 to 15 chars
8053 bind(COMPARE_TAIL_LONG);
8054 movl(cnt2, result);
8055 cmpl(cnt2, stride);
8056 jccb(Assembler::less, COMPARE_SMALL_STR);
8057
8058 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8059 movdqu(vec1, Address(str1, 0));
8060 } else {
8061 pmovzxbw(vec1, Address(str1, 0));
8062 }
8063 pcmpestri(vec1, Address(str2, 0), pcmpmask);
8064 jcc(Assembler::below, COMPARE_INDEX_CHAR);
8065 subptr(cnt2, stride);
8066 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8067 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8068 lea(str1, Address(str1, result, scale));
8069 lea(str2, Address(str2, result, scale));
8070 } else {
8071 lea(str1, Address(str1, result, scale1));
8072 lea(str2, Address(str2, result, scale2));
8073 }
8074 negptr(cnt2);
8075 jmpb(WHILE_HEAD_LABEL);
8076
8077 bind(COMPARE_SMALL_STR);
8078 } else if (UseSSE42Intrinsics) {
8079 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8080 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
8081 int pcmpmask = 0x19;
8082 // Setup to compare 8-char (16-byte) vectors,
8083 // start from first character again because it has aligned address.
8084 movl(result, cnt2);
8085 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
8086 if (ae == StrIntrinsicNode::LL) {
8087 pcmpmask &= ~0x01;
8088 }
8089 jccb(Assembler::zero, COMPARE_TAIL);
8090 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8091 lea(str1, Address(str1, result, scale));
8092 lea(str2, Address(str2, result, scale));
8093 } else {
8094 lea(str1, Address(str1, result, scale1));
8095 lea(str2, Address(str2, result, scale2));
8096 }
8097 negptr(result);
8098
8099 // pcmpestri
8100 // inputs:
8101 // vec1- substring
8102 // rax - negative string length (elements count)
8103 // mem - scanned string
8104 // rdx - string length (elements count)
8105 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8106 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8107 // outputs:
8108 // rcx - first mismatched element index
8109 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8110
8111 bind(COMPARE_WIDE_VECTORS);
8112 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8113 movdqu(vec1, Address(str1, result, scale));
8114 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8115 } else {
8116 pmovzxbw(vec1, Address(str1, result, scale1));
8117 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8118 }
8119 // After pcmpestri cnt1(rcx) contains mismatched element index
8120
8121 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8122 addptr(result, stride);
8123 subptr(cnt2, stride);
8124 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8125
8126 // compare wide vectors tail
8127 testptr(result, result);
8128 jccb(Assembler::zero, LENGTH_DIFF_LABEL);
8129
8130 movl(cnt2, stride);
8131 movl(result, stride);
8132 negptr(result);
8133 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8134 movdqu(vec1, Address(str1, result, scale));
8135 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8136 } else {
8137 pmovzxbw(vec1, Address(str1, result, scale1));
8138 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8139 }
8140 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8141
8142 // Mismatched characters in the vectors
8143 bind(VECTOR_NOT_EQUAL);
8144 addptr(cnt1, result);
8145 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8146 subl(result, cnt2);
8147 jmpb(POP_LABEL);
8148
8149 bind(COMPARE_TAIL); // limit is zero
8150 movl(cnt2, result);
8151 // Fallthru to tail compare
8152 }
8153 // Shift str2 and str1 to the end of the arrays, negate min
8154 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8155 lea(str1, Address(str1, cnt2, scale));
8156 lea(str2, Address(str2, cnt2, scale));
8157 } else {
8158 lea(str1, Address(str1, cnt2, scale1));
8159 lea(str2, Address(str2, cnt2, scale2));
8160 }
8161 decrementl(cnt2); // first character was compared already
8162 negptr(cnt2);
8163
8164 // Compare the rest of the elements
8165 bind(WHILE_HEAD_LABEL);
8166 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8167 subl(result, cnt1);
8168 jccb(Assembler::notZero, POP_LABEL);
8169 increment(cnt2);
8170 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8171
8172 // Strings are equal up to min length. Return the length difference.
8173 bind(LENGTH_DIFF_LABEL);
8174 pop(result);
8175 if (ae == StrIntrinsicNode::UU) {
8176 // Divide diff by 2 to get number of chars
8177 sarl(result, 1);
8178 }
8179 jmpb(DONE_LABEL);
8180
8181 #ifdef _LP64
8182 if (VM_Version::supports_avx512vlbw()) {
8183
8184 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8185
8186 kmovql(cnt1, k7);
8187 notq(cnt1);
8188 bsfq(cnt2, cnt1);
8189 if (ae != StrIntrinsicNode::LL) {
8190 // Divide diff by 2 to get number of chars
8191 sarl(cnt2, 1);
8192 }
8193 addq(result, cnt2);
8194 if (ae == StrIntrinsicNode::LL) {
8195 load_unsigned_byte(cnt1, Address(str2, result));
8196 load_unsigned_byte(result, Address(str1, result));
8197 } else if (ae == StrIntrinsicNode::UU) {
8198 load_unsigned_short(cnt1, Address(str2, result, scale));
8199 load_unsigned_short(result, Address(str1, result, scale));
8200 } else {
8201 load_unsigned_short(cnt1, Address(str2, result, scale2));
8202 load_unsigned_byte(result, Address(str1, result, scale1));
8203 }
8204 subl(result, cnt1);
8205 jmpb(POP_LABEL);
8206 }//if (VM_Version::supports_avx512vlbw())
8207 #endif // _LP64
8208
8209 // Discard the stored length difference
8210 bind(POP_LABEL);
8211 pop(cnt1);
8212
8213 // That's it
8214 bind(DONE_LABEL);
8215 if(ae == StrIntrinsicNode::UL) {
8216 negl(result);
8217 }
8218
8219 }
8220
8221 // Search for Non-ASCII character (Negative byte value) in a byte array,
8222 // return true if it has any and false otherwise.
8223 void MacroAssembler::has_negatives(Register ary1, Register len,
8224 Register result, Register tmp1,
8225 XMMRegister vec1, XMMRegister vec2) {
8226
8227 // rsi: byte array
8228 // rcx: len
8229 // rax: result
8230 ShortBranchVerifier sbv(this);
8231 assert_different_registers(ary1, len, result, tmp1);
8232 assert_different_registers(vec1, vec2);
8233 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8234
8235 // len == 0
8236 testl(len, len);
8237 jcc(Assembler::zero, FALSE_LABEL);
8238
8239 movl(result, len); // copy
8240
8241 if (UseAVX >= 2 && UseSSE >= 2) {
8242 // With AVX2, use 32-byte vector compare
8243 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8244
8245 // Compare 32-byte vectors
8246 andl(result, 0x0000001f); // tail count (in bytes)
8247 andl(len, 0xffffffe0); // vector count (in bytes)
8248 jccb(Assembler::zero, COMPARE_TAIL);
8249
8250 lea(ary1, Address(ary1, len, Address::times_1));
8251 negptr(len);
8252
8253 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8254 movdl(vec2, tmp1);
8255 vpbroadcastd(vec2, vec2);
8256
8257 bind(COMPARE_WIDE_VECTORS);
8258 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8259 vptest(vec1, vec2);
8260 jccb(Assembler::notZero, TRUE_LABEL);
8261 addptr(len, 32);
8262 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8263
8264 testl(result, result);
8265 jccb(Assembler::zero, FALSE_LABEL);
8266
8267 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8268 vptest(vec1, vec2);
8269 jccb(Assembler::notZero, TRUE_LABEL);
8270 jmpb(FALSE_LABEL);
8271
8272 bind(COMPARE_TAIL); // len is zero
8273 movl(len, result);
8274 // Fallthru to tail compare
8275 } else if (UseSSE42Intrinsics) {
8276 assert(UseSSE >= 4, "SSE4 must be for SSE4.2 intrinsics to be available");
8277 // With SSE4.2, use double quad vector compare
8278 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8279
8280 // Compare 16-byte vectors
8281 andl(result, 0x0000000f); // tail count (in bytes)
8282 andl(len, 0xfffffff0); // vector count (in bytes)
8283 jccb(Assembler::zero, COMPARE_TAIL);
8284
8285 lea(ary1, Address(ary1, len, Address::times_1));
8286 negptr(len);
8287
8288 movl(tmp1, 0x80808080);
8289 movdl(vec2, tmp1);
8290 pshufd(vec2, vec2, 0);
8291
8292 bind(COMPARE_WIDE_VECTORS);
8293 movdqu(vec1, Address(ary1, len, Address::times_1));
8294 ptest(vec1, vec2);
8295 jccb(Assembler::notZero, TRUE_LABEL);
8296 addptr(len, 16);
8297 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8298
8299 testl(result, result);
8300 jccb(Assembler::zero, FALSE_LABEL);
8301
8302 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8303 ptest(vec1, vec2);
8304 jccb(Assembler::notZero, TRUE_LABEL);
8305 jmpb(FALSE_LABEL);
8306
8307 bind(COMPARE_TAIL); // len is zero
8308 movl(len, result);
8309 // Fallthru to tail compare
8310 }
8311
8312 // Compare 4-byte vectors
8313 andl(len, 0xfffffffc); // vector count (in bytes)
8314 jccb(Assembler::zero, COMPARE_CHAR);
8315
8316 lea(ary1, Address(ary1, len, Address::times_1));
8317 negptr(len);
8318
8319 bind(COMPARE_VECTORS);
8320 movl(tmp1, Address(ary1, len, Address::times_1));
8321 andl(tmp1, 0x80808080);
8322 jccb(Assembler::notZero, TRUE_LABEL);
8323 addptr(len, 4);
8324 jcc(Assembler::notZero, COMPARE_VECTORS);
8325
8326 // Compare trailing char (final 2 bytes), if any
8327 bind(COMPARE_CHAR);
8328 testl(result, 0x2); // tail char
8329 jccb(Assembler::zero, COMPARE_BYTE);
8330 load_unsigned_short(tmp1, Address(ary1, 0));
8331 andl(tmp1, 0x00008080);
8332 jccb(Assembler::notZero, TRUE_LABEL);
8333 subptr(result, 2);
8334 lea(ary1, Address(ary1, 2));
8335
8336 bind(COMPARE_BYTE);
8337 testl(result, 0x1); // tail byte
8338 jccb(Assembler::zero, FALSE_LABEL);
8339 load_unsigned_byte(tmp1, Address(ary1, 0));
8340 andl(tmp1, 0x00000080);
8341 jccb(Assembler::notEqual, TRUE_LABEL);
8342 jmpb(FALSE_LABEL);
8343
8344 bind(TRUE_LABEL);
8345 movl(result, 1); // return true
8346 jmpb(DONE);
8347
8348 bind(FALSE_LABEL);
8349 xorl(result, result); // return false
8350
8351 // That's it
8352 bind(DONE);
8353 if (UseAVX >= 2 && UseSSE >= 2) {
8354 // clean upper bits of YMM registers
8355 vpxor(vec1, vec1);
8356 vpxor(vec2, vec2);
8357 }
8358 }
8359
8360 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8361 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8362 Register limit, Register result, Register chr,
8363 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8364 ShortBranchVerifier sbv(this);
8365 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8366
8367 int length_offset = arrayOopDesc::length_offset_in_bytes();
8368 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8369
8370 if (is_array_equ) {
8371 // Check the input args
8372 cmpptr(ary1, ary2);
8373 jcc(Assembler::equal, TRUE_LABEL);
8374
8375 // Need additional checks for arrays_equals.
8376 testptr(ary1, ary1);
8377 jcc(Assembler::zero, FALSE_LABEL);
8378 testptr(ary2, ary2);
8379 jcc(Assembler::zero, FALSE_LABEL);
8380
8381 // Check the lengths
8382 movl(limit, Address(ary1, length_offset));
8383 cmpl(limit, Address(ary2, length_offset));
8384 jcc(Assembler::notEqual, FALSE_LABEL);
8385 }
8386
8387 // count == 0
8388 testl(limit, limit);
8389 jcc(Assembler::zero, TRUE_LABEL);
8390
8391 if (is_array_equ) {
8392 // Load array address
8393 lea(ary1, Address(ary1, base_offset));
8394 lea(ary2, Address(ary2, base_offset));
8395 }
8396
8397 if (is_array_equ && is_char) {
8398 // arrays_equals when used for char[].
8399 shll(limit, 1); // byte count != 0
8400 }
8401 movl(result, limit); // copy
8402
8403 if (UseAVX >= 2) {
8404 // With AVX2, use 32-byte vector compare
8405 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8406
8407 // Compare 32-byte vectors
8408 andl(result, 0x0000001f); // tail count (in bytes)
8409 andl(limit, 0xffffffe0); // vector count (in bytes)
8410 jcc(Assembler::zero, COMPARE_TAIL);
8411
8412 lea(ary1, Address(ary1, limit, Address::times_1));
8413 lea(ary2, Address(ary2, limit, Address::times_1));
8414 negptr(limit);
8415
8416 bind(COMPARE_WIDE_VECTORS);
8417
8418 #ifdef _LP64
8419 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8420 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8421
8422 cmpl(limit, -64);
8423 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8424
8425 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8426
8427 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8428 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8429 kortestql(k7, k7);
8430 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8431 addptr(limit, 64); // update since we already compared at this addr
8432 cmpl(limit, -64);
8433 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8434
8435 // At this point we may still need to compare -limit+result bytes.
8436 // We could execute the next two instruction and just continue via non-wide path:
8437 // cmpl(limit, 0);
8438 // jcc(Assembler::equal, COMPARE_TAIL); // true
8439 // But since we stopped at the points ary{1,2}+limit which are
8440 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8441 // (|limit| <= 32 and result < 32),
8442 // we may just compare the last 64 bytes.
8443 //
8444 addptr(result, -64); // it is safe, bc we just came from this area
8445 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8446 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8447 kortestql(k7, k7);
8448 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8449
8450 jmp(TRUE_LABEL);
8451
8452 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8453
8454 }//if (VM_Version::supports_avx512vlbw())
8455 #endif //_LP64
8456
8457 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8458 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8459 vpxor(vec1, vec2);
8460
8461 vptest(vec1, vec1);
8462 jccb(Assembler::notZero, FALSE_LABEL);
8463 addptr(limit, 32);
8464 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8465
8466 testl(result, result);
8467 jccb(Assembler::zero, TRUE_LABEL);
8468
8469 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8470 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8471 vpxor(vec1, vec2);
8472
8473 vptest(vec1, vec1);
8474 jccb(Assembler::notZero, FALSE_LABEL);
8475 jmpb(TRUE_LABEL);
8476
8477 bind(COMPARE_TAIL); // limit is zero
8478 movl(limit, result);
8479 // Fallthru to tail compare
8480 } else if (UseSSE42Intrinsics) {
8481 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8482 // With SSE4.2, use double quad vector compare
8483 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8484
8485 // Compare 16-byte vectors
8486 andl(result, 0x0000000f); // tail count (in bytes)
8487 andl(limit, 0xfffffff0); // vector count (in bytes)
8488 jccb(Assembler::zero, COMPARE_TAIL);
8489
8490 lea(ary1, Address(ary1, limit, Address::times_1));
8491 lea(ary2, Address(ary2, limit, Address::times_1));
8492 negptr(limit);
8493
8494 bind(COMPARE_WIDE_VECTORS);
8495 movdqu(vec1, Address(ary1, limit, Address::times_1));
8496 movdqu(vec2, Address(ary2, limit, Address::times_1));
8497 pxor(vec1, vec2);
8498
8499 ptest(vec1, vec1);
8500 jccb(Assembler::notZero, FALSE_LABEL);
8501 addptr(limit, 16);
8502 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8503
8504 testl(result, result);
8505 jccb(Assembler::zero, TRUE_LABEL);
8506
8507 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8508 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8509 pxor(vec1, vec2);
8510
8511 ptest(vec1, vec1);
8512 jccb(Assembler::notZero, FALSE_LABEL);
8513 jmpb(TRUE_LABEL);
8514
8515 bind(COMPARE_TAIL); // limit is zero
8516 movl(limit, result);
8517 // Fallthru to tail compare
8518 }
8519
8520 // Compare 4-byte vectors
8521 andl(limit, 0xfffffffc); // vector count (in bytes)
8522 jccb(Assembler::zero, COMPARE_CHAR);
8523
8524 lea(ary1, Address(ary1, limit, Address::times_1));
8525 lea(ary2, Address(ary2, limit, Address::times_1));
8526 negptr(limit);
8527
8528 bind(COMPARE_VECTORS);
8529 movl(chr, Address(ary1, limit, Address::times_1));
8530 cmpl(chr, Address(ary2, limit, Address::times_1));
8531 jccb(Assembler::notEqual, FALSE_LABEL);
8532 addptr(limit, 4);
8533 jcc(Assembler::notZero, COMPARE_VECTORS);
8534
8535 // Compare trailing char (final 2 bytes), if any
8536 bind(COMPARE_CHAR);
8537 testl(result, 0x2); // tail char
8538 jccb(Assembler::zero, COMPARE_BYTE);
8539 load_unsigned_short(chr, Address(ary1, 0));
8540 load_unsigned_short(limit, Address(ary2, 0));
8541 cmpl(chr, limit);
8542 jccb(Assembler::notEqual, FALSE_LABEL);
8543
8544 if (is_array_equ && is_char) {
8545 bind(COMPARE_BYTE);
8546 } else {
8547 lea(ary1, Address(ary1, 2));
8548 lea(ary2, Address(ary2, 2));
8549
8550 bind(COMPARE_BYTE);
8551 testl(result, 0x1); // tail byte
8552 jccb(Assembler::zero, TRUE_LABEL);
8553 load_unsigned_byte(chr, Address(ary1, 0));
8554 load_unsigned_byte(limit, Address(ary2, 0));
8555 cmpl(chr, limit);
8556 jccb(Assembler::notEqual, FALSE_LABEL);
8557 }
8558 bind(TRUE_LABEL);
8559 movl(result, 1); // return true
8560 jmpb(DONE);
8561
8562 bind(FALSE_LABEL);
8563 xorl(result, result); // return false
8564
8565 // That's it
8566 bind(DONE);
8567 if (UseAVX >= 2) {
8568 // clean upper bits of YMM registers
8569 vpxor(vec1, vec1);
8570 vpxor(vec2, vec2);
8571 }
8572 }
8573
8574 #endif
8575
8576 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8577 Register to, Register value, Register count,
8578 Register rtmp, XMMRegister xtmp) {
8579 ShortBranchVerifier sbv(this);
8580 assert_different_registers(to, value, count, rtmp);
8581 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8582 Label L_fill_2_bytes, L_fill_4_bytes;
8583
8584 int shift = -1;
8585 switch (t) {
8586 case T_BYTE:
8587 shift = 2;
8588 break;
8589 case T_SHORT:
8590 shift = 1;
8591 break;
8592 case T_INT:
8593 shift = 0;
8594 break;
8595 default: ShouldNotReachHere();
8596 }
8597
8598 if (t == T_BYTE) {
8599 andl(value, 0xff);
8600 movl(rtmp, value);
8601 shll(rtmp, 8);
8602 orl(value, rtmp);
8603 }
8604 if (t == T_SHORT) {
8605 andl(value, 0xffff);
8606 }
8607 if (t == T_BYTE || t == T_SHORT) {
8608 movl(rtmp, value);
8609 shll(rtmp, 16);
8610 orl(value, rtmp);
8611 }
8612
8613 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8614 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8615 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8616 // align source address at 4 bytes address boundary
8617 if (t == T_BYTE) {
8618 // One byte misalignment happens only for byte arrays
8619 testptr(to, 1);
8620 jccb(Assembler::zero, L_skip_align1);
8621 movb(Address(to, 0), value);
8622 increment(to);
8623 decrement(count);
8624 BIND(L_skip_align1);
8625 }
8626 // Two bytes misalignment happens only for byte and short (char) arrays
8627 testptr(to, 2);
8628 jccb(Assembler::zero, L_skip_align2);
8629 movw(Address(to, 0), value);
8630 addptr(to, 2);
8631 subl(count, 1<<(shift-1));
8632 BIND(L_skip_align2);
8633 }
8634 if (UseSSE < 2) {
8635 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8636 // Fill 32-byte chunks
8637 subl(count, 8 << shift);
8638 jcc(Assembler::less, L_check_fill_8_bytes);
8639 align(16);
8640
8641 BIND(L_fill_32_bytes_loop);
8642
8643 for (int i = 0; i < 32; i += 4) {
8644 movl(Address(to, i), value);
8645 }
8646
8647 addptr(to, 32);
8648 subl(count, 8 << shift);
8649 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8650 BIND(L_check_fill_8_bytes);
8651 addl(count, 8 << shift);
8652 jccb(Assembler::zero, L_exit);
8653 jmpb(L_fill_8_bytes);
8654
8655 //
8656 // length is too short, just fill qwords
8657 //
8658 BIND(L_fill_8_bytes_loop);
8659 movl(Address(to, 0), value);
8660 movl(Address(to, 4), value);
8661 addptr(to, 8);
8662 BIND(L_fill_8_bytes);
8663 subl(count, 1 << (shift + 1));
8664 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8665 // fall through to fill 4 bytes
8666 } else {
8667 Label L_fill_32_bytes;
8668 if (!UseUnalignedLoadStores) {
8669 // align to 8 bytes, we know we are 4 byte aligned to start
8670 testptr(to, 4);
8671 jccb(Assembler::zero, L_fill_32_bytes);
8672 movl(Address(to, 0), value);
8673 addptr(to, 4);
8674 subl(count, 1<<shift);
8675 }
8676 BIND(L_fill_32_bytes);
8677 {
8678 assert( UseSSE >= 2, "supported cpu only" );
8679 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8680 if (UseAVX > 2) {
8681 movl(rtmp, 0xffff);
8682 kmovwl(k1, rtmp);
8683 }
8684 movdl(xtmp, value);
8685 if (UseAVX > 2 && UseUnalignedLoadStores) {
8686 // Fill 64-byte chunks
8687 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8688 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8689
8690 subl(count, 16 << shift);
8691 jcc(Assembler::less, L_check_fill_32_bytes);
8692 align(16);
8693
8694 BIND(L_fill_64_bytes_loop);
8695 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8696 addptr(to, 64);
8697 subl(count, 16 << shift);
8698 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8699
8700 BIND(L_check_fill_32_bytes);
8701 addl(count, 8 << shift);
8702 jccb(Assembler::less, L_check_fill_8_bytes);
8703 vmovdqu(Address(to, 0), xtmp);
8704 addptr(to, 32);
8705 subl(count, 8 << shift);
8706
8707 BIND(L_check_fill_8_bytes);
8708 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8709 // Fill 64-byte chunks
8710 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8711 vpbroadcastd(xtmp, xtmp);
8712
8713 subl(count, 16 << shift);
8714 jcc(Assembler::less, L_check_fill_32_bytes);
8715 align(16);
8716
8717 BIND(L_fill_64_bytes_loop);
8718 vmovdqu(Address(to, 0), xtmp);
8719 vmovdqu(Address(to, 32), xtmp);
8720 addptr(to, 64);
8721 subl(count, 16 << shift);
8722 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8723
8724 BIND(L_check_fill_32_bytes);
8725 addl(count, 8 << shift);
8726 jccb(Assembler::less, L_check_fill_8_bytes);
8727 vmovdqu(Address(to, 0), xtmp);
8728 addptr(to, 32);
8729 subl(count, 8 << shift);
8730
8731 BIND(L_check_fill_8_bytes);
8732 // clean upper bits of YMM registers
8733 movdl(xtmp, value);
8734 pshufd(xtmp, xtmp, 0);
8735 } else {
8736 // Fill 32-byte chunks
8737 pshufd(xtmp, xtmp, 0);
8738
8739 subl(count, 8 << shift);
8740 jcc(Assembler::less, L_check_fill_8_bytes);
8741 align(16);
8742
8743 BIND(L_fill_32_bytes_loop);
8744
8745 if (UseUnalignedLoadStores) {
8746 movdqu(Address(to, 0), xtmp);
8747 movdqu(Address(to, 16), xtmp);
8748 } else {
8749 movq(Address(to, 0), xtmp);
8750 movq(Address(to, 8), xtmp);
8751 movq(Address(to, 16), xtmp);
8752 movq(Address(to, 24), xtmp);
8753 }
8754
8755 addptr(to, 32);
8756 subl(count, 8 << shift);
8757 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8758
8759 BIND(L_check_fill_8_bytes);
8760 }
8761 addl(count, 8 << shift);
8762 jccb(Assembler::zero, L_exit);
8763 jmpb(L_fill_8_bytes);
8764
8765 //
8766 // length is too short, just fill qwords
8767 //
8768 BIND(L_fill_8_bytes_loop);
8769 movq(Address(to, 0), xtmp);
8770 addptr(to, 8);
8771 BIND(L_fill_8_bytes);
8772 subl(count, 1 << (shift + 1));
8773 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8774 }
8775 }
8776 // fill trailing 4 bytes
8777 BIND(L_fill_4_bytes);
8778 testl(count, 1<<shift);
8779 jccb(Assembler::zero, L_fill_2_bytes);
8780 movl(Address(to, 0), value);
8781 if (t == T_BYTE || t == T_SHORT) {
8782 addptr(to, 4);
8783 BIND(L_fill_2_bytes);
8784 // fill trailing 2 bytes
8785 testl(count, 1<<(shift-1));
8786 jccb(Assembler::zero, L_fill_byte);
8787 movw(Address(to, 0), value);
8788 if (t == T_BYTE) {
8789 addptr(to, 2);
8790 BIND(L_fill_byte);
8791 // fill trailing byte
8792 testl(count, 1);
8793 jccb(Assembler::zero, L_exit);
8794 movb(Address(to, 0), value);
8795 } else {
8796 BIND(L_fill_byte);
8797 }
8798 } else {
8799 BIND(L_fill_2_bytes);
8800 }
8801 BIND(L_exit);
8802 }
8803
8804 // encode char[] to byte[] in ISO_8859_1
8805 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8806 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8807 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8808 Register tmp5, Register result) {
8809 // rsi: src
8810 // rdi: dst
8811 // rdx: len
8812 // rcx: tmp5
8813 // rax: result
8814 ShortBranchVerifier sbv(this);
8815 assert_different_registers(src, dst, len, tmp5, result);
8816 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8817
8818 // set result
8819 xorl(result, result);
8820 // check for zero length
8821 testl(len, len);
8822 jcc(Assembler::zero, L_done);
8823 movl(result, len);
8824
8825 // Setup pointers
8826 lea(src, Address(src, len, Address::times_2)); // char[]
8827 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8828 negptr(len);
8829
8830 if (UseSSE42Intrinsics || UseAVX >= 2) {
8831 assert(UseSSE42Intrinsics ? UseSSE >= 4 : true, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
8832 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8833 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8834
8835 if (UseAVX >= 2) {
8836 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8837 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8838 movdl(tmp1Reg, tmp5);
8839 vpbroadcastd(tmp1Reg, tmp1Reg);
8840 jmpb(L_chars_32_check);
8841
8842 bind(L_copy_32_chars);
8843 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8844 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8845 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8846 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8847 jccb(Assembler::notZero, L_copy_32_chars_exit);
8848 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8849 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8850 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8851
8852 bind(L_chars_32_check);
8853 addptr(len, 32);
8854 jccb(Assembler::lessEqual, L_copy_32_chars);
8855
8856 bind(L_copy_32_chars_exit);
8857 subptr(len, 16);
8858 jccb(Assembler::greater, L_copy_16_chars_exit);
8859
8860 } else if (UseSSE42Intrinsics) {
8861 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8862 movdl(tmp1Reg, tmp5);
8863 pshufd(tmp1Reg, tmp1Reg, 0);
8864 jmpb(L_chars_16_check);
8865 }
8866
8867 bind(L_copy_16_chars);
8868 if (UseAVX >= 2) {
8869 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8870 vptest(tmp2Reg, tmp1Reg);
8871 jccb(Assembler::notZero, L_copy_16_chars_exit);
8872 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8873 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8874 } else {
8875 if (UseAVX > 0) {
8876 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8877 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8878 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8879 } else {
8880 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8881 por(tmp2Reg, tmp3Reg);
8882 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8883 por(tmp2Reg, tmp4Reg);
8884 }
8885 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8886 jccb(Assembler::notZero, L_copy_16_chars_exit);
8887 packuswb(tmp3Reg, tmp4Reg);
8888 }
8889 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8890
8891 bind(L_chars_16_check);
8892 addptr(len, 16);
8893 jccb(Assembler::lessEqual, L_copy_16_chars);
8894
8895 bind(L_copy_16_chars_exit);
8896 if (UseAVX >= 2) {
8897 // clean upper bits of YMM registers
8898 vpxor(tmp2Reg, tmp2Reg);
8899 vpxor(tmp3Reg, tmp3Reg);
8900 vpxor(tmp4Reg, tmp4Reg);
8901 movdl(tmp1Reg, tmp5);
8902 pshufd(tmp1Reg, tmp1Reg, 0);
8903 }
8904 subptr(len, 8);
8905 jccb(Assembler::greater, L_copy_8_chars_exit);
8906
8907 bind(L_copy_8_chars);
8908 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8909 ptest(tmp3Reg, tmp1Reg);
8910 jccb(Assembler::notZero, L_copy_8_chars_exit);
8911 packuswb(tmp3Reg, tmp1Reg);
8912 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8913 addptr(len, 8);
8914 jccb(Assembler::lessEqual, L_copy_8_chars);
8915
8916 bind(L_copy_8_chars_exit);
8917 subptr(len, 8);
8918 jccb(Assembler::zero, L_done);
8919 }
8920
8921 bind(L_copy_1_char);
8922 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8923 testl(tmp5, 0xff00); // check if Unicode char
8924 jccb(Assembler::notZero, L_copy_1_char_exit);
8925 movb(Address(dst, len, Address::times_1, 0), tmp5);
8926 addptr(len, 1);
8927 jccb(Assembler::less, L_copy_1_char);
8928
8929 bind(L_copy_1_char_exit);
8930 addptr(result, len); // len is negative count of not processed elements
8931 bind(L_done);
8932 }
8933
8934 #ifdef _LP64
8935 /**
8936 * Helper for multiply_to_len().
8937 */
8938 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8939 addq(dest_lo, src1);
8940 adcq(dest_hi, 0);
8941 addq(dest_lo, src2);
8942 adcq(dest_hi, 0);
8943 }
8944
8945 /**
8946 * Multiply 64 bit by 64 bit first loop.
8947 */
8948 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8949 Register y, Register y_idx, Register z,
8950 Register carry, Register product,
8951 Register idx, Register kdx) {
8952 //
8953 // jlong carry, x[], y[], z[];
8954 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8955 // huge_128 product = y[idx] * x[xstart] + carry;
8956 // z[kdx] = (jlong)product;
8957 // carry = (jlong)(product >>> 64);
8958 // }
8959 // z[xstart] = carry;
8960 //
8961
8962 Label L_first_loop, L_first_loop_exit;
8963 Label L_one_x, L_one_y, L_multiply;
8964
8965 decrementl(xstart);
8966 jcc(Assembler::negative, L_one_x);
8967
8968 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8969 rorq(x_xstart, 32); // convert big-endian to little-endian
8970
8971 bind(L_first_loop);
8972 decrementl(idx);
8973 jcc(Assembler::negative, L_first_loop_exit);
8974 decrementl(idx);
8975 jcc(Assembler::negative, L_one_y);
8976 movq(y_idx, Address(y, idx, Address::times_4, 0));
8977 rorq(y_idx, 32); // convert big-endian to little-endian
8978 bind(L_multiply);
8979 movq(product, x_xstart);
8980 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8981 addq(product, carry);
8982 adcq(rdx, 0);
8983 subl(kdx, 2);
8984 movl(Address(z, kdx, Address::times_4, 4), product);
8985 shrq(product, 32);
8986 movl(Address(z, kdx, Address::times_4, 0), product);
8987 movq(carry, rdx);
8988 jmp(L_first_loop);
8989
8990 bind(L_one_y);
8991 movl(y_idx, Address(y, 0));
8992 jmp(L_multiply);
8993
8994 bind(L_one_x);
8995 movl(x_xstart, Address(x, 0));
8996 jmp(L_first_loop);
8997
8998 bind(L_first_loop_exit);
8999 }
9000
9001 /**
9002 * Multiply 64 bit by 64 bit and add 128 bit.
9003 */
9004 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9005 Register yz_idx, Register idx,
9006 Register carry, Register product, int offset) {
9007 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9008 // z[kdx] = (jlong)product;
9009
9010 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9011 rorq(yz_idx, 32); // convert big-endian to little-endian
9012 movq(product, x_xstart);
9013 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9014 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9015 rorq(yz_idx, 32); // convert big-endian to little-endian
9016
9017 add2_with_carry(rdx, product, carry, yz_idx);
9018
9019 movl(Address(z, idx, Address::times_4, offset+4), product);
9020 shrq(product, 32);
9021 movl(Address(z, idx, Address::times_4, offset), product);
9022
9023 }
9024
9025 /**
9026 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9027 */
9028 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9029 Register yz_idx, Register idx, Register jdx,
9030 Register carry, Register product,
9031 Register carry2) {
9032 // jlong carry, x[], y[], z[];
9033 // int kdx = ystart+1;
9034 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9035 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9036 // z[kdx+idx+1] = (jlong)product;
9037 // jlong carry2 = (jlong)(product >>> 64);
9038 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9039 // z[kdx+idx] = (jlong)product;
9040 // carry = (jlong)(product >>> 64);
9041 // }
9042 // idx += 2;
9043 // if (idx > 0) {
9044 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9045 // z[kdx+idx] = (jlong)product;
9046 // carry = (jlong)(product >>> 64);
9047 // }
9048 //
9049
9050 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9051
9052 movl(jdx, idx);
9053 andl(jdx, 0xFFFFFFFC);
9054 shrl(jdx, 2);
9055
9056 bind(L_third_loop);
9057 subl(jdx, 1);
9058 jcc(Assembler::negative, L_third_loop_exit);
9059 subl(idx, 4);
9060
9061 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9062 movq(carry2, rdx);
9063
9064 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9065 movq(carry, rdx);
9066 jmp(L_third_loop);
9067
9068 bind (L_third_loop_exit);
9069
9070 andl (idx, 0x3);
9071 jcc(Assembler::zero, L_post_third_loop_done);
9072
9073 Label L_check_1;
9074 subl(idx, 2);
9075 jcc(Assembler::negative, L_check_1);
9076
9077 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9078 movq(carry, rdx);
9079
9080 bind (L_check_1);
9081 addl (idx, 0x2);
9082 andl (idx, 0x1);
9083 subl(idx, 1);
9084 jcc(Assembler::negative, L_post_third_loop_done);
9085
9086 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9087 movq(product, x_xstart);
9088 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9089 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9090
9091 add2_with_carry(rdx, product, yz_idx, carry);
9092
9093 movl(Address(z, idx, Address::times_4, 0), product);
9094 shrq(product, 32);
9095
9096 shlq(rdx, 32);
9097 orq(product, rdx);
9098 movq(carry, product);
9099
9100 bind(L_post_third_loop_done);
9101 }
9102
9103 /**
9104 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9105 *
9106 */
9107 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9108 Register carry, Register carry2,
9109 Register idx, Register jdx,
9110 Register yz_idx1, Register yz_idx2,
9111 Register tmp, Register tmp3, Register tmp4) {
9112 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9113
9114 // jlong carry, x[], y[], z[];
9115 // int kdx = ystart+1;
9116 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9117 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9118 // jlong carry2 = (jlong)(tmp3 >>> 64);
9119 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9120 // carry = (jlong)(tmp4 >>> 64);
9121 // z[kdx+idx+1] = (jlong)tmp3;
9122 // z[kdx+idx] = (jlong)tmp4;
9123 // }
9124 // idx += 2;
9125 // if (idx > 0) {
9126 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9127 // z[kdx+idx] = (jlong)yz_idx1;
9128 // carry = (jlong)(yz_idx1 >>> 64);
9129 // }
9130 //
9131
9132 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9133
9134 movl(jdx, idx);
9135 andl(jdx, 0xFFFFFFFC);
9136 shrl(jdx, 2);
9137
9138 bind(L_third_loop);
9139 subl(jdx, 1);
9140 jcc(Assembler::negative, L_third_loop_exit);
9141 subl(idx, 4);
9142
9143 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9144 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9145 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9146 rorxq(yz_idx2, yz_idx2, 32);
9147
9148 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9149 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9150
9151 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9152 rorxq(yz_idx1, yz_idx1, 32);
9153 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9154 rorxq(yz_idx2, yz_idx2, 32);
9155
9156 if (VM_Version::supports_adx()) {
9157 adcxq(tmp3, carry);
9158 adoxq(tmp3, yz_idx1);
9159
9160 adcxq(tmp4, tmp);
9161 adoxq(tmp4, yz_idx2);
9162
9163 movl(carry, 0); // does not affect flags
9164 adcxq(carry2, carry);
9165 adoxq(carry2, carry);
9166 } else {
9167 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9168 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9169 }
9170 movq(carry, carry2);
9171
9172 movl(Address(z, idx, Address::times_4, 12), tmp3);
9173 shrq(tmp3, 32);
9174 movl(Address(z, idx, Address::times_4, 8), tmp3);
9175
9176 movl(Address(z, idx, Address::times_4, 4), tmp4);
9177 shrq(tmp4, 32);
9178 movl(Address(z, idx, Address::times_4, 0), tmp4);
9179
9180 jmp(L_third_loop);
9181
9182 bind (L_third_loop_exit);
9183
9184 andl (idx, 0x3);
9185 jcc(Assembler::zero, L_post_third_loop_done);
9186
9187 Label L_check_1;
9188 subl(idx, 2);
9189 jcc(Assembler::negative, L_check_1);
9190
9191 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9192 rorxq(yz_idx1, yz_idx1, 32);
9193 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9194 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9195 rorxq(yz_idx2, yz_idx2, 32);
9196
9197 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9198
9199 movl(Address(z, idx, Address::times_4, 4), tmp3);
9200 shrq(tmp3, 32);
9201 movl(Address(z, idx, Address::times_4, 0), tmp3);
9202 movq(carry, tmp4);
9203
9204 bind (L_check_1);
9205 addl (idx, 0x2);
9206 andl (idx, 0x1);
9207 subl(idx, 1);
9208 jcc(Assembler::negative, L_post_third_loop_done);
9209 movl(tmp4, Address(y, idx, Address::times_4, 0));
9210 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9211 movl(tmp4, Address(z, idx, Address::times_4, 0));
9212
9213 add2_with_carry(carry2, tmp3, tmp4, carry);
9214
9215 movl(Address(z, idx, Address::times_4, 0), tmp3);
9216 shrq(tmp3, 32);
9217
9218 shlq(carry2, 32);
9219 orq(tmp3, carry2);
9220 movq(carry, tmp3);
9221
9222 bind(L_post_third_loop_done);
9223 }
9224
9225 /**
9226 * Code for BigInteger::multiplyToLen() instrinsic.
9227 *
9228 * rdi: x
9229 * rax: xlen
9230 * rsi: y
9231 * rcx: ylen
9232 * r8: z
9233 * r11: zlen
9234 * r12: tmp1
9235 * r13: tmp2
9236 * r14: tmp3
9237 * r15: tmp4
9238 * rbx: tmp5
9239 *
9240 */
9241 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9242 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9243 ShortBranchVerifier sbv(this);
9244 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9245
9246 push(tmp1);
9247 push(tmp2);
9248 push(tmp3);
9249 push(tmp4);
9250 push(tmp5);
9251
9252 push(xlen);
9253 push(zlen);
9254
9255 const Register idx = tmp1;
9256 const Register kdx = tmp2;
9257 const Register xstart = tmp3;
9258
9259 const Register y_idx = tmp4;
9260 const Register carry = tmp5;
9261 const Register product = xlen;
9262 const Register x_xstart = zlen; // reuse register
9263
9264 // First Loop.
9265 //
9266 // final static long LONG_MASK = 0xffffffffL;
9267 // int xstart = xlen - 1;
9268 // int ystart = ylen - 1;
9269 // long carry = 0;
9270 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9271 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9272 // z[kdx] = (int)product;
9273 // carry = product >>> 32;
9274 // }
9275 // z[xstart] = (int)carry;
9276 //
9277
9278 movl(idx, ylen); // idx = ylen;
9279 movl(kdx, zlen); // kdx = xlen+ylen;
9280 xorq(carry, carry); // carry = 0;
9281
9282 Label L_done;
9283
9284 movl(xstart, xlen);
9285 decrementl(xstart);
9286 jcc(Assembler::negative, L_done);
9287
9288 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9289
9290 Label L_second_loop;
9291 testl(kdx, kdx);
9292 jcc(Assembler::zero, L_second_loop);
9293
9294 Label L_carry;
9295 subl(kdx, 1);
9296 jcc(Assembler::zero, L_carry);
9297
9298 movl(Address(z, kdx, Address::times_4, 0), carry);
9299 shrq(carry, 32);
9300 subl(kdx, 1);
9301
9302 bind(L_carry);
9303 movl(Address(z, kdx, Address::times_4, 0), carry);
9304
9305 // Second and third (nested) loops.
9306 //
9307 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9308 // carry = 0;
9309 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9310 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9311 // (z[k] & LONG_MASK) + carry;
9312 // z[k] = (int)product;
9313 // carry = product >>> 32;
9314 // }
9315 // z[i] = (int)carry;
9316 // }
9317 //
9318 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9319
9320 const Register jdx = tmp1;
9321
9322 bind(L_second_loop);
9323 xorl(carry, carry); // carry = 0;
9324 movl(jdx, ylen); // j = ystart+1
9325
9326 subl(xstart, 1); // i = xstart-1;
9327 jcc(Assembler::negative, L_done);
9328
9329 push (z);
9330
9331 Label L_last_x;
9332 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9333 subl(xstart, 1); // i = xstart-1;
9334 jcc(Assembler::negative, L_last_x);
9335
9336 if (UseBMI2Instructions) {
9337 movq(rdx, Address(x, xstart, Address::times_4, 0));
9338 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9339 } else {
9340 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9341 rorq(x_xstart, 32); // convert big-endian to little-endian
9342 }
9343
9344 Label L_third_loop_prologue;
9345 bind(L_third_loop_prologue);
9346
9347 push (x);
9348 push (xstart);
9349 push (ylen);
9350
9351
9352 if (UseBMI2Instructions) {
9353 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9354 } else { // !UseBMI2Instructions
9355 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9356 }
9357
9358 pop(ylen);
9359 pop(xlen);
9360 pop(x);
9361 pop(z);
9362
9363 movl(tmp3, xlen);
9364 addl(tmp3, 1);
9365 movl(Address(z, tmp3, Address::times_4, 0), carry);
9366 subl(tmp3, 1);
9367 jccb(Assembler::negative, L_done);
9368
9369 shrq(carry, 32);
9370 movl(Address(z, tmp3, Address::times_4, 0), carry);
9371 jmp(L_second_loop);
9372
9373 // Next infrequent code is moved outside loops.
9374 bind(L_last_x);
9375 if (UseBMI2Instructions) {
9376 movl(rdx, Address(x, 0));
9377 } else {
9378 movl(x_xstart, Address(x, 0));
9379 }
9380 jmp(L_third_loop_prologue);
9381
9382 bind(L_done);
9383
9384 pop(zlen);
9385 pop(xlen);
9386
9387 pop(tmp5);
9388 pop(tmp4);
9389 pop(tmp3);
9390 pop(tmp2);
9391 pop(tmp1);
9392 }
9393
9394 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9395 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9396 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9397 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9398 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9399 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9400 Label SAME_TILL_END, DONE;
9401 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9402
9403 //scale is in rcx in both Win64 and Unix
9404 ShortBranchVerifier sbv(this);
9405
9406 shlq(length);
9407 xorq(result, result);
9408
9409 cmpq(length, 8);
9410 jcc(Assembler::equal, VECTOR8_LOOP);
9411 jcc(Assembler::less, VECTOR4_TAIL);
9412
9413 if (UseAVX >= 2){
9414
9415 cmpq(length, 16);
9416 jcc(Assembler::equal, VECTOR16_LOOP);
9417 jcc(Assembler::less, VECTOR8_LOOP);
9418
9419 cmpq(length, 32);
9420 jccb(Assembler::less, VECTOR16_TAIL);
9421
9422 subq(length, 32);
9423 bind(VECTOR32_LOOP);
9424 vmovdqu(rymm0, Address(obja, result));
9425 vmovdqu(rymm1, Address(objb, result));
9426 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9427 vptest(rymm2, rymm2);
9428 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9429 addq(result, 32);
9430 subq(length, 32);
9431 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9432 addq(length, 32);
9433 jcc(Assembler::equal, SAME_TILL_END);
9434 //falling through if less than 32 bytes left //close the branch here.
9435
9436 bind(VECTOR16_TAIL);
9437 cmpq(length, 16);
9438 jccb(Assembler::less, VECTOR8_TAIL);
9439 bind(VECTOR16_LOOP);
9440 movdqu(rymm0, Address(obja, result));
9441 movdqu(rymm1, Address(objb, result));
9442 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9443 ptest(rymm2, rymm2);
9444 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9445 addq(result, 16);
9446 subq(length, 16);
9447 jcc(Assembler::equal, SAME_TILL_END);
9448 //falling through if less than 16 bytes left
9449 } else {//regular intrinsics
9450
9451 cmpq(length, 16);
9452 jccb(Assembler::less, VECTOR8_TAIL);
9453
9454 subq(length, 16);
9455 bind(VECTOR16_LOOP);
9456 movdqu(rymm0, Address(obja, result));
9457 movdqu(rymm1, Address(objb, result));
9458 pxor(rymm0, rymm1);
9459 ptest(rymm0, rymm0);
9460 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9461 addq(result, 16);
9462 subq(length, 16);
9463 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9464 addq(length, 16);
9465 jcc(Assembler::equal, SAME_TILL_END);
9466 //falling through if less than 16 bytes left
9467 }
9468
9469 bind(VECTOR8_TAIL);
9470 cmpq(length, 8);
9471 jccb(Assembler::less, VECTOR4_TAIL);
9472 bind(VECTOR8_LOOP);
9473 movq(tmp1, Address(obja, result));
9474 movq(tmp2, Address(objb, result));
9475 xorq(tmp1, tmp2);
9476 testq(tmp1, tmp1);
9477 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9478 addq(result, 8);
9479 subq(length, 8);
9480 jcc(Assembler::equal, SAME_TILL_END);
9481 //falling through if less than 8 bytes left
9482
9483 bind(VECTOR4_TAIL);
9484 cmpq(length, 4);
9485 jccb(Assembler::less, BYTES_TAIL);
9486 bind(VECTOR4_LOOP);
9487 movl(tmp1, Address(obja, result));
9488 xorl(tmp1, Address(objb, result));
9489 testl(tmp1, tmp1);
9490 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9491 addq(result, 4);
9492 subq(length, 4);
9493 jcc(Assembler::equal, SAME_TILL_END);
9494 //falling through if less than 4 bytes left
9495
9496 bind(BYTES_TAIL);
9497 bind(BYTES_LOOP);
9498 load_unsigned_byte(tmp1, Address(obja, result));
9499 load_unsigned_byte(tmp2, Address(objb, result));
9500 xorl(tmp1, tmp2);
9501 testl(tmp1, tmp1);
9502 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9503 decq(length);
9504 jccb(Assembler::zero, SAME_TILL_END);
9505 incq(result);
9506 load_unsigned_byte(tmp1, Address(obja, result));
9507 load_unsigned_byte(tmp2, Address(objb, result));
9508 xorl(tmp1, tmp2);
9509 testl(tmp1, tmp1);
9510 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9511 decq(length);
9512 jccb(Assembler::zero, SAME_TILL_END);
9513 incq(result);
9514 load_unsigned_byte(tmp1, Address(obja, result));
9515 load_unsigned_byte(tmp2, Address(objb, result));
9516 xorl(tmp1, tmp2);
9517 testl(tmp1, tmp1);
9518 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9519 jmpb(SAME_TILL_END);
9520
9521 if (UseAVX >= 2){
9522 bind(VECTOR32_NOT_EQUAL);
9523 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9524 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9525 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9526 vpmovmskb(tmp1, rymm0);
9527 bsfq(tmp1, tmp1);
9528 addq(result, tmp1);
9529 shrq(result);
9530 jmpb(DONE);
9531 }
9532
9533 bind(VECTOR16_NOT_EQUAL);
9534 if (UseAVX >= 2){
9535 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9536 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9537 pxor(rymm0, rymm2);
9538 } else {
9539 pcmpeqb(rymm2, rymm2);
9540 pxor(rymm0, rymm1);
9541 pcmpeqb(rymm0, rymm1);
9542 pxor(rymm0, rymm2);
9543 }
9544 pmovmskb(tmp1, rymm0);
9545 bsfq(tmp1, tmp1);
9546 addq(result, tmp1);
9547 shrq(result);
9548 jmpb(DONE);
9549
9550 bind(VECTOR8_NOT_EQUAL);
9551 bind(VECTOR4_NOT_EQUAL);
9552 bsfq(tmp1, tmp1);
9553 shrq(tmp1, 3);
9554 addq(result, tmp1);
9555 bind(BYTES_NOT_EQUAL);
9556 shrq(result);
9557 jmpb(DONE);
9558
9559 bind(SAME_TILL_END);
9560 mov64(result, -1);
9561
9562 bind(DONE);
9563 }
9564
9565
9566 //Helper functions for square_to_len()
9567
9568 /**
9569 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9570 * Preserves x and z and modifies rest of the registers.
9571 */
9572 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9573 // Perform square and right shift by 1
9574 // Handle odd xlen case first, then for even xlen do the following
9575 // jlong carry = 0;
9576 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9577 // huge_128 product = x[j:j+1] * x[j:j+1];
9578 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9579 // z[i+2:i+3] = (jlong)(product >>> 1);
9580 // carry = (jlong)product;
9581 // }
9582
9583 xorq(tmp5, tmp5); // carry
9584 xorq(rdxReg, rdxReg);
9585 xorl(tmp1, tmp1); // index for x
9586 xorl(tmp4, tmp4); // index for z
9587
9588 Label L_first_loop, L_first_loop_exit;
9589
9590 testl(xlen, 1);
9591 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9592
9593 // Square and right shift by 1 the odd element using 32 bit multiply
9594 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9595 imulq(raxReg, raxReg);
9596 shrq(raxReg, 1);
9597 adcq(tmp5, 0);
9598 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9599 incrementl(tmp1);
9600 addl(tmp4, 2);
9601
9602 // Square and right shift by 1 the rest using 64 bit multiply
9603 bind(L_first_loop);
9604 cmpptr(tmp1, xlen);
9605 jccb(Assembler::equal, L_first_loop_exit);
9606
9607 // Square
9608 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9609 rorq(raxReg, 32); // convert big-endian to little-endian
9610 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9611
9612 // Right shift by 1 and save carry
9613 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9614 rcrq(rdxReg, 1);
9615 rcrq(raxReg, 1);
9616 adcq(tmp5, 0);
9617
9618 // Store result in z
9619 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9620 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9621
9622 // Update indices for x and z
9623 addl(tmp1, 2);
9624 addl(tmp4, 4);
9625 jmp(L_first_loop);
9626
9627 bind(L_first_loop_exit);
9628 }
9629
9630
9631 /**
9632 * Perform the following multiply add operation using BMI2 instructions
9633 * carry:sum = sum + op1*op2 + carry
9634 * op2 should be in rdx
9635 * op2 is preserved, all other registers are modified
9636 */
9637 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9638 // assert op2 is rdx
9639 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9640 addq(sum, carry);
9641 adcq(tmp2, 0);
9642 addq(sum, op1);
9643 adcq(tmp2, 0);
9644 movq(carry, tmp2);
9645 }
9646
9647 /**
9648 * Perform the following multiply add operation:
9649 * carry:sum = sum + op1*op2 + carry
9650 * Preserves op1, op2 and modifies rest of registers
9651 */
9652 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9653 // rdx:rax = op1 * op2
9654 movq(raxReg, op2);
9655 mulq(op1);
9656
9657 // rdx:rax = sum + carry + rdx:rax
9658 addq(sum, carry);
9659 adcq(rdxReg, 0);
9660 addq(sum, raxReg);
9661 adcq(rdxReg, 0);
9662
9663 // carry:sum = rdx:sum
9664 movq(carry, rdxReg);
9665 }
9666
9667 /**
9668 * Add 64 bit long carry into z[] with carry propogation.
9669 * Preserves z and carry register values and modifies rest of registers.
9670 *
9671 */
9672 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9673 Label L_fourth_loop, L_fourth_loop_exit;
9674
9675 movl(tmp1, 1);
9676 subl(zlen, 2);
9677 addq(Address(z, zlen, Address::times_4, 0), carry);
9678
9679 bind(L_fourth_loop);
9680 jccb(Assembler::carryClear, L_fourth_loop_exit);
9681 subl(zlen, 2);
9682 jccb(Assembler::negative, L_fourth_loop_exit);
9683 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9684 jmp(L_fourth_loop);
9685 bind(L_fourth_loop_exit);
9686 }
9687
9688 /**
9689 * Shift z[] left by 1 bit.
9690 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9691 *
9692 */
9693 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9694
9695 Label L_fifth_loop, L_fifth_loop_exit;
9696
9697 // Fifth loop
9698 // Perform primitiveLeftShift(z, zlen, 1)
9699
9700 const Register prev_carry = tmp1;
9701 const Register new_carry = tmp4;
9702 const Register value = tmp2;
9703 const Register zidx = tmp3;
9704
9705 // int zidx, carry;
9706 // long value;
9707 // carry = 0;
9708 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9709 // (carry:value) = (z[i] << 1) | carry ;
9710 // z[i] = value;
9711 // }
9712
9713 movl(zidx, zlen);
9714 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9715
9716 bind(L_fifth_loop);
9717 decl(zidx); // Use decl to preserve carry flag
9718 decl(zidx);
9719 jccb(Assembler::negative, L_fifth_loop_exit);
9720
9721 if (UseBMI2Instructions) {
9722 movq(value, Address(z, zidx, Address::times_4, 0));
9723 rclq(value, 1);
9724 rorxq(value, value, 32);
9725 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9726 }
9727 else {
9728 // clear new_carry
9729 xorl(new_carry, new_carry);
9730
9731 // Shift z[i] by 1, or in previous carry and save new carry
9732 movq(value, Address(z, zidx, Address::times_4, 0));
9733 shlq(value, 1);
9734 adcl(new_carry, 0);
9735
9736 orq(value, prev_carry);
9737 rorq(value, 0x20);
9738 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9739
9740 // Set previous carry = new carry
9741 movl(prev_carry, new_carry);
9742 }
9743 jmp(L_fifth_loop);
9744
9745 bind(L_fifth_loop_exit);
9746 }
9747
9748
9749 /**
9750 * Code for BigInteger::squareToLen() intrinsic
9751 *
9752 * rdi: x
9753 * rsi: len
9754 * r8: z
9755 * rcx: zlen
9756 * r12: tmp1
9757 * r13: tmp2
9758 * r14: tmp3
9759 * r15: tmp4
9760 * rbx: tmp5
9761 *
9762 */
9763 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9764
9765 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9766 push(tmp1);
9767 push(tmp2);
9768 push(tmp3);
9769 push(tmp4);
9770 push(tmp5);
9771
9772 // First loop
9773 // Store the squares, right shifted one bit (i.e., divided by 2).
9774 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9775
9776 // Add in off-diagonal sums.
9777 //
9778 // Second, third (nested) and fourth loops.
9779 // zlen +=2;
9780 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9781 // carry = 0;
9782 // long op2 = x[xidx:xidx+1];
9783 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9784 // k -= 2;
9785 // long op1 = x[j:j+1];
9786 // long sum = z[k:k+1];
9787 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9788 // z[k:k+1] = sum;
9789 // }
9790 // add_one_64(z, k, carry, tmp_regs);
9791 // }
9792
9793 const Register carry = tmp5;
9794 const Register sum = tmp3;
9795 const Register op1 = tmp4;
9796 Register op2 = tmp2;
9797
9798 push(zlen);
9799 push(len);
9800 addl(zlen,2);
9801 bind(L_second_loop);
9802 xorq(carry, carry);
9803 subl(zlen, 4);
9804 subl(len, 2);
9805 push(zlen);
9806 push(len);
9807 cmpl(len, 0);
9808 jccb(Assembler::lessEqual, L_second_loop_exit);
9809
9810 // Multiply an array by one 64 bit long.
9811 if (UseBMI2Instructions) {
9812 op2 = rdxReg;
9813 movq(op2, Address(x, len, Address::times_4, 0));
9814 rorxq(op2, op2, 32);
9815 }
9816 else {
9817 movq(op2, Address(x, len, Address::times_4, 0));
9818 rorq(op2, 32);
9819 }
9820
9821 bind(L_third_loop);
9822 decrementl(len);
9823 jccb(Assembler::negative, L_third_loop_exit);
9824 decrementl(len);
9825 jccb(Assembler::negative, L_last_x);
9826
9827 movq(op1, Address(x, len, Address::times_4, 0));
9828 rorq(op1, 32);
9829
9830 bind(L_multiply);
9831 subl(zlen, 2);
9832 movq(sum, Address(z, zlen, Address::times_4, 0));
9833
9834 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9835 if (UseBMI2Instructions) {
9836 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9837 }
9838 else {
9839 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9840 }
9841
9842 movq(Address(z, zlen, Address::times_4, 0), sum);
9843
9844 jmp(L_third_loop);
9845 bind(L_third_loop_exit);
9846
9847 // Fourth loop
9848 // Add 64 bit long carry into z with carry propogation.
9849 // Uses offsetted zlen.
9850 add_one_64(z, zlen, carry, tmp1);
9851
9852 pop(len);
9853 pop(zlen);
9854 jmp(L_second_loop);
9855
9856 // Next infrequent code is moved outside loops.
9857 bind(L_last_x);
9858 movl(op1, Address(x, 0));
9859 jmp(L_multiply);
9860
9861 bind(L_second_loop_exit);
9862 pop(len);
9863 pop(zlen);
9864 pop(len);
9865 pop(zlen);
9866
9867 // Fifth loop
9868 // Shift z left 1 bit.
9869 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9870
9871 // z[zlen-1] |= x[len-1] & 1;
9872 movl(tmp3, Address(x, len, Address::times_4, -4));
9873 andl(tmp3, 1);
9874 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9875
9876 pop(tmp5);
9877 pop(tmp4);
9878 pop(tmp3);
9879 pop(tmp2);
9880 pop(tmp1);
9881 }
9882
9883 /**
9884 * Helper function for mul_add()
9885 * Multiply the in[] by int k and add to out[] starting at offset offs using
9886 * 128 bit by 32 bit multiply and return the carry in tmp5.
9887 * Only quad int aligned length of in[] is operated on in this function.
9888 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9889 * This function preserves out, in and k registers.
9890 * len and offset point to the appropriate index in "in" & "out" correspondingly
9891 * tmp5 has the carry.
9892 * other registers are temporary and are modified.
9893 *
9894 */
9895 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9896 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9897 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9898
9899 Label L_first_loop, L_first_loop_exit;
9900
9901 movl(tmp1, len);
9902 shrl(tmp1, 2);
9903
9904 bind(L_first_loop);
9905 subl(tmp1, 1);
9906 jccb(Assembler::negative, L_first_loop_exit);
9907
9908 subl(len, 4);
9909 subl(offset, 4);
9910
9911 Register op2 = tmp2;
9912 const Register sum = tmp3;
9913 const Register op1 = tmp4;
9914 const Register carry = tmp5;
9915
9916 if (UseBMI2Instructions) {
9917 op2 = rdxReg;
9918 }
9919
9920 movq(op1, Address(in, len, Address::times_4, 8));
9921 rorq(op1, 32);
9922 movq(sum, Address(out, offset, Address::times_4, 8));
9923 rorq(sum, 32);
9924 if (UseBMI2Instructions) {
9925 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9926 }
9927 else {
9928 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9929 }
9930 // Store back in big endian from little endian
9931 rorq(sum, 0x20);
9932 movq(Address(out, offset, Address::times_4, 8), sum);
9933
9934 movq(op1, Address(in, len, Address::times_4, 0));
9935 rorq(op1, 32);
9936 movq(sum, Address(out, offset, Address::times_4, 0));
9937 rorq(sum, 32);
9938 if (UseBMI2Instructions) {
9939 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9940 }
9941 else {
9942 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9943 }
9944 // Store back in big endian from little endian
9945 rorq(sum, 0x20);
9946 movq(Address(out, offset, Address::times_4, 0), sum);
9947
9948 jmp(L_first_loop);
9949 bind(L_first_loop_exit);
9950 }
9951
9952 /**
9953 * Code for BigInteger::mulAdd() intrinsic
9954 *
9955 * rdi: out
9956 * rsi: in
9957 * r11: offs (out.length - offset)
9958 * rcx: len
9959 * r8: k
9960 * r12: tmp1
9961 * r13: tmp2
9962 * r14: tmp3
9963 * r15: tmp4
9964 * rbx: tmp5
9965 * Multiply the in[] by word k and add to out[], return the carry in rax
9966 */
9967 void MacroAssembler::mul_add(Register out, Register in, Register offs,
9968 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
9969 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9970
9971 Label L_carry, L_last_in, L_done;
9972
9973 // carry = 0;
9974 // for (int j=len-1; j >= 0; j--) {
9975 // long product = (in[j] & LONG_MASK) * kLong +
9976 // (out[offs] & LONG_MASK) + carry;
9977 // out[offs--] = (int)product;
9978 // carry = product >>> 32;
9979 // }
9980 //
9981 push(tmp1);
9982 push(tmp2);
9983 push(tmp3);
9984 push(tmp4);
9985 push(tmp5);
9986
9987 Register op2 = tmp2;
9988 const Register sum = tmp3;
9989 const Register op1 = tmp4;
9990 const Register carry = tmp5;
9991
9992 if (UseBMI2Instructions) {
9993 op2 = rdxReg;
9994 movl(op2, k);
9995 }
9996 else {
9997 movl(op2, k);
9998 }
9999
10000 xorq(carry, carry);
10001
10002 //First loop
10003
10004 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10005 //The carry is in tmp5
10006 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10007
10008 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10009 decrementl(len);
10010 jccb(Assembler::negative, L_carry);
10011 decrementl(len);
10012 jccb(Assembler::negative, L_last_in);
10013
10014 movq(op1, Address(in, len, Address::times_4, 0));
10015 rorq(op1, 32);
10016
10017 subl(offs, 2);
10018 movq(sum, Address(out, offs, Address::times_4, 0));
10019 rorq(sum, 32);
10020
10021 if (UseBMI2Instructions) {
10022 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10023 }
10024 else {
10025 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10026 }
10027
10028 // Store back in big endian from little endian
10029 rorq(sum, 0x20);
10030 movq(Address(out, offs, Address::times_4, 0), sum);
10031
10032 testl(len, len);
10033 jccb(Assembler::zero, L_carry);
10034
10035 //Multiply the last in[] entry, if any
10036 bind(L_last_in);
10037 movl(op1, Address(in, 0));
10038 movl(sum, Address(out, offs, Address::times_4, -4));
10039
10040 movl(raxReg, k);
10041 mull(op1); //tmp4 * eax -> edx:eax
10042 addl(sum, carry);
10043 adcl(rdxReg, 0);
10044 addl(sum, raxReg);
10045 adcl(rdxReg, 0);
10046 movl(carry, rdxReg);
10047
10048 movl(Address(out, offs, Address::times_4, -4), sum);
10049
10050 bind(L_carry);
10051 //return tmp5/carry as carry in rax
10052 movl(rax, carry);
10053
10054 bind(L_done);
10055 pop(tmp5);
10056 pop(tmp4);
10057 pop(tmp3);
10058 pop(tmp2);
10059 pop(tmp1);
10060 }
10061 #endif
10062
10063 /**
10064 * Emits code to update CRC-32 with a byte value according to constants in table
10065 *
10066 * @param [in,out]crc Register containing the crc.
10067 * @param [in]val Register containing the byte to fold into the CRC.
10068 * @param [in]table Register containing the table of crc constants.
10069 *
10070 * uint32_t crc;
10071 * val = crc_table[(val ^ crc) & 0xFF];
10072 * crc = val ^ (crc >> 8);
10073 *
10074 */
10075 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10076 xorl(val, crc);
10077 andl(val, 0xFF);
10078 shrl(crc, 8); // unsigned shift
10079 xorl(crc, Address(table, val, Address::times_4, 0));
10080 }
10081
10082 /**
10083 * Fold 128-bit data chunk
10084 */
10085 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10086 if (UseAVX > 0) {
10087 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10088 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10089 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10090 pxor(xcrc, xtmp);
10091 } else {
10092 movdqa(xtmp, xcrc);
10093 pclmulhdq(xtmp, xK); // [123:64]
10094 pclmulldq(xcrc, xK); // [63:0]
10095 pxor(xcrc, xtmp);
10096 movdqu(xtmp, Address(buf, offset));
10097 pxor(xcrc, xtmp);
10098 }
10099 }
10100
10101 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10102 if (UseAVX > 0) {
10103 vpclmulhdq(xtmp, xK, xcrc);
10104 vpclmulldq(xcrc, xK, xcrc);
10105 pxor(xcrc, xbuf);
10106 pxor(xcrc, xtmp);
10107 } else {
10108 movdqa(xtmp, xcrc);
10109 pclmulhdq(xtmp, xK);
10110 pclmulldq(xcrc, xK);
10111 pxor(xcrc, xbuf);
10112 pxor(xcrc, xtmp);
10113 }
10114 }
10115
10116 /**
10117 * 8-bit folds to compute 32-bit CRC
10118 *
10119 * uint64_t xcrc;
10120 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10121 */
10122 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10123 movdl(tmp, xcrc);
10124 andl(tmp, 0xFF);
10125 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10126 psrldq(xcrc, 1); // unsigned shift one byte
10127 pxor(xcrc, xtmp);
10128 }
10129
10130 /**
10131 * uint32_t crc;
10132 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10133 */
10134 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10135 movl(tmp, crc);
10136 andl(tmp, 0xFF);
10137 shrl(crc, 8);
10138 xorl(crc, Address(table, tmp, Address::times_4, 0));
10139 }
10140
10141 /**
10142 * @param crc register containing existing CRC (32-bit)
10143 * @param buf register pointing to input byte buffer (byte*)
10144 * @param len register containing number of bytes
10145 * @param table register that will contain address of CRC table
10146 * @param tmp scratch register
10147 */
10148 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10149 assert_different_registers(crc, buf, len, table, tmp, rax);
10150
10151 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10152 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10153
10154 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10155 // context for the registers used, where all instructions below are using 128-bit mode
10156 // On EVEX without VL and BW, these instructions will all be AVX.
10157 if (VM_Version::supports_avx512vlbw()) {
10158 movl(tmp, 0xffff);
10159 kmovwl(k1, tmp);
10160 }
10161
10162 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10163 notl(crc); // ~crc
10164 cmpl(len, 16);
10165 jcc(Assembler::less, L_tail);
10166
10167 // Align buffer to 16 bytes
10168 movl(tmp, buf);
10169 andl(tmp, 0xF);
10170 jccb(Assembler::zero, L_aligned);
10171 subl(tmp, 16);
10172 addl(len, tmp);
10173
10174 align(4);
10175 BIND(L_align_loop);
10176 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10177 update_byte_crc32(crc, rax, table);
10178 increment(buf);
10179 incrementl(tmp);
10180 jccb(Assembler::less, L_align_loop);
10181
10182 BIND(L_aligned);
10183 movl(tmp, len); // save
10184 shrl(len, 4);
10185 jcc(Assembler::zero, L_tail_restore);
10186
10187 // Fold crc into first bytes of vector
10188 movdqa(xmm1, Address(buf, 0));
10189 movdl(rax, xmm1);
10190 xorl(crc, rax);
10191 pinsrd(xmm1, crc, 0);
10192 addptr(buf, 16);
10193 subl(len, 4); // len > 0
10194 jcc(Assembler::less, L_fold_tail);
10195
10196 movdqa(xmm2, Address(buf, 0));
10197 movdqa(xmm3, Address(buf, 16));
10198 movdqa(xmm4, Address(buf, 32));
10199 addptr(buf, 48);
10200 subl(len, 3);
10201 jcc(Assembler::lessEqual, L_fold_512b);
10202
10203 // Fold total 512 bits of polynomial on each iteration,
10204 // 128 bits per each of 4 parallel streams.
10205 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10206
10207 align(32);
10208 BIND(L_fold_512b_loop);
10209 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10210 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10211 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10212 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10213 addptr(buf, 64);
10214 subl(len, 4);
10215 jcc(Assembler::greater, L_fold_512b_loop);
10216
10217 // Fold 512 bits to 128 bits.
10218 BIND(L_fold_512b);
10219 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10220 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10221 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10222 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10223
10224 // Fold the rest of 128 bits data chunks
10225 BIND(L_fold_tail);
10226 addl(len, 3);
10227 jccb(Assembler::lessEqual, L_fold_128b);
10228 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10229
10230 BIND(L_fold_tail_loop);
10231 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10232 addptr(buf, 16);
10233 decrementl(len);
10234 jccb(Assembler::greater, L_fold_tail_loop);
10235
10236 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10237 BIND(L_fold_128b);
10238 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10239 if (UseAVX > 0) {
10240 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10241 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10242 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10243 } else {
10244 movdqa(xmm2, xmm0);
10245 pclmulqdq(xmm2, xmm1, 0x1);
10246 movdqa(xmm3, xmm0);
10247 pand(xmm3, xmm2);
10248 pclmulqdq(xmm0, xmm3, 0x1);
10249 }
10250 psrldq(xmm1, 8);
10251 psrldq(xmm2, 4);
10252 pxor(xmm0, xmm1);
10253 pxor(xmm0, xmm2);
10254
10255 // 8 8-bit folds to compute 32-bit CRC.
10256 for (int j = 0; j < 4; j++) {
10257 fold_8bit_crc32(xmm0, table, xmm1, rax);
10258 }
10259 movdl(crc, xmm0); // mov 32 bits to general register
10260 for (int j = 0; j < 4; j++) {
10261 fold_8bit_crc32(crc, table, rax);
10262 }
10263
10264 BIND(L_tail_restore);
10265 movl(len, tmp); // restore
10266 BIND(L_tail);
10267 andl(len, 0xf);
10268 jccb(Assembler::zero, L_exit);
10269
10270 // Fold the rest of bytes
10271 align(4);
10272 BIND(L_tail_loop);
10273 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10274 update_byte_crc32(crc, rax, table);
10275 increment(buf);
10276 decrementl(len);
10277 jccb(Assembler::greater, L_tail_loop);
10278
10279 BIND(L_exit);
10280 notl(crc); // ~c
10281 }
10282
10283 #ifdef _LP64
10284 // S. Gueron / Information Processing Letters 112 (2012) 184
10285 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10286 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10287 // Output: the 64-bit carry-less product of B * CONST
10288 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10289 Register tmp1, Register tmp2, Register tmp3) {
10290 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10291 if (n > 0) {
10292 addq(tmp3, n * 256 * 8);
10293 }
10294 // Q1 = TABLEExt[n][B & 0xFF];
10295 movl(tmp1, in);
10296 andl(tmp1, 0x000000FF);
10297 shll(tmp1, 3);
10298 addq(tmp1, tmp3);
10299 movq(tmp1, Address(tmp1, 0));
10300
10301 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10302 movl(tmp2, in);
10303 shrl(tmp2, 8);
10304 andl(tmp2, 0x000000FF);
10305 shll(tmp2, 3);
10306 addq(tmp2, tmp3);
10307 movq(tmp2, Address(tmp2, 0));
10308
10309 shlq(tmp2, 8);
10310 xorq(tmp1, tmp2);
10311
10312 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10313 movl(tmp2, in);
10314 shrl(tmp2, 16);
10315 andl(tmp2, 0x000000FF);
10316 shll(tmp2, 3);
10317 addq(tmp2, tmp3);
10318 movq(tmp2, Address(tmp2, 0));
10319
10320 shlq(tmp2, 16);
10321 xorq(tmp1, tmp2);
10322
10323 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10324 shrl(in, 24);
10325 andl(in, 0x000000FF);
10326 shll(in, 3);
10327 addq(in, tmp3);
10328 movq(in, Address(in, 0));
10329
10330 shlq(in, 24);
10331 xorq(in, tmp1);
10332 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10333 }
10334
10335 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10336 Register in_out,
10337 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10338 XMMRegister w_xtmp2,
10339 Register tmp1,
10340 Register n_tmp2, Register n_tmp3) {
10341 if (is_pclmulqdq_supported) {
10342 movdl(w_xtmp1, in_out); // modified blindly
10343
10344 movl(tmp1, const_or_pre_comp_const_index);
10345 movdl(w_xtmp2, tmp1);
10346 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10347
10348 movdq(in_out, w_xtmp1);
10349 } else {
10350 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10351 }
10352 }
10353
10354 // Recombination Alternative 2: No bit-reflections
10355 // T1 = (CRC_A * U1) << 1
10356 // T2 = (CRC_B * U2) << 1
10357 // C1 = T1 >> 32
10358 // C2 = T2 >> 32
10359 // T1 = T1 & 0xFFFFFFFF
10360 // T2 = T2 & 0xFFFFFFFF
10361 // T1 = CRC32(0, T1)
10362 // T2 = CRC32(0, T2)
10363 // C1 = C1 ^ T1
10364 // C2 = C2 ^ T2
10365 // CRC = C1 ^ C2 ^ CRC_C
10366 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10367 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10368 Register tmp1, Register tmp2,
10369 Register n_tmp3) {
10370 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10371 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10372 shlq(in_out, 1);
10373 movl(tmp1, in_out);
10374 shrq(in_out, 32);
10375 xorl(tmp2, tmp2);
10376 crc32(tmp2, tmp1, 4);
10377 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10378 shlq(in1, 1);
10379 movl(tmp1, in1);
10380 shrq(in1, 32);
10381 xorl(tmp2, tmp2);
10382 crc32(tmp2, tmp1, 4);
10383 xorl(in1, tmp2);
10384 xorl(in_out, in1);
10385 xorl(in_out, in2);
10386 }
10387
10388 // Set N to predefined value
10389 // Subtract from a lenght of a buffer
10390 // execute in a loop:
10391 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10392 // for i = 1 to N do
10393 // CRC_A = CRC32(CRC_A, A[i])
10394 // CRC_B = CRC32(CRC_B, B[i])
10395 // CRC_C = CRC32(CRC_C, C[i])
10396 // end for
10397 // Recombine
10398 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10399 Register in_out1, Register in_out2, Register in_out3,
10400 Register tmp1, Register tmp2, Register tmp3,
10401 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10402 Register tmp4, Register tmp5,
10403 Register n_tmp6) {
10404 Label L_processPartitions;
10405 Label L_processPartition;
10406 Label L_exit;
10407
10408 bind(L_processPartitions);
10409 cmpl(in_out1, 3 * size);
10410 jcc(Assembler::less, L_exit);
10411 xorl(tmp1, tmp1);
10412 xorl(tmp2, tmp2);
10413 movq(tmp3, in_out2);
10414 addq(tmp3, size);
10415
10416 bind(L_processPartition);
10417 crc32(in_out3, Address(in_out2, 0), 8);
10418 crc32(tmp1, Address(in_out2, size), 8);
10419 crc32(tmp2, Address(in_out2, size * 2), 8);
10420 addq(in_out2, 8);
10421 cmpq(in_out2, tmp3);
10422 jcc(Assembler::less, L_processPartition);
10423 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10424 w_xtmp1, w_xtmp2, w_xtmp3,
10425 tmp4, tmp5,
10426 n_tmp6);
10427 addq(in_out2, 2 * size);
10428 subl(in_out1, 3 * size);
10429 jmp(L_processPartitions);
10430
10431 bind(L_exit);
10432 }
10433 #else
10434 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10435 Register tmp1, Register tmp2, Register tmp3,
10436 XMMRegister xtmp1, XMMRegister xtmp2) {
10437 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10438 if (n > 0) {
10439 addl(tmp3, n * 256 * 8);
10440 }
10441 // Q1 = TABLEExt[n][B & 0xFF];
10442 movl(tmp1, in_out);
10443 andl(tmp1, 0x000000FF);
10444 shll(tmp1, 3);
10445 addl(tmp1, tmp3);
10446 movq(xtmp1, Address(tmp1, 0));
10447
10448 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10449 movl(tmp2, in_out);
10450 shrl(tmp2, 8);
10451 andl(tmp2, 0x000000FF);
10452 shll(tmp2, 3);
10453 addl(tmp2, tmp3);
10454 movq(xtmp2, Address(tmp2, 0));
10455
10456 psllq(xtmp2, 8);
10457 pxor(xtmp1, xtmp2);
10458
10459 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10460 movl(tmp2, in_out);
10461 shrl(tmp2, 16);
10462 andl(tmp2, 0x000000FF);
10463 shll(tmp2, 3);
10464 addl(tmp2, tmp3);
10465 movq(xtmp2, Address(tmp2, 0));
10466
10467 psllq(xtmp2, 16);
10468 pxor(xtmp1, xtmp2);
10469
10470 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10471 shrl(in_out, 24);
10472 andl(in_out, 0x000000FF);
10473 shll(in_out, 3);
10474 addl(in_out, tmp3);
10475 movq(xtmp2, Address(in_out, 0));
10476
10477 psllq(xtmp2, 24);
10478 pxor(xtmp1, xtmp2); // Result in CXMM
10479 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10480 }
10481
10482 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10483 Register in_out,
10484 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10485 XMMRegister w_xtmp2,
10486 Register tmp1,
10487 Register n_tmp2, Register n_tmp3) {
10488 if (is_pclmulqdq_supported) {
10489 movdl(w_xtmp1, in_out);
10490
10491 movl(tmp1, const_or_pre_comp_const_index);
10492 movdl(w_xtmp2, tmp1);
10493 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10494 // Keep result in XMM since GPR is 32 bit in length
10495 } else {
10496 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10497 }
10498 }
10499
10500 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10501 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10502 Register tmp1, Register tmp2,
10503 Register n_tmp3) {
10504 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10505 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10506
10507 psllq(w_xtmp1, 1);
10508 movdl(tmp1, w_xtmp1);
10509 psrlq(w_xtmp1, 32);
10510 movdl(in_out, w_xtmp1);
10511
10512 xorl(tmp2, tmp2);
10513 crc32(tmp2, tmp1, 4);
10514 xorl(in_out, tmp2);
10515
10516 psllq(w_xtmp2, 1);
10517 movdl(tmp1, w_xtmp2);
10518 psrlq(w_xtmp2, 32);
10519 movdl(in1, w_xtmp2);
10520
10521 xorl(tmp2, tmp2);
10522 crc32(tmp2, tmp1, 4);
10523 xorl(in1, tmp2);
10524 xorl(in_out, in1);
10525 xorl(in_out, in2);
10526 }
10527
10528 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10529 Register in_out1, Register in_out2, Register in_out3,
10530 Register tmp1, Register tmp2, Register tmp3,
10531 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10532 Register tmp4, Register tmp5,
10533 Register n_tmp6) {
10534 Label L_processPartitions;
10535 Label L_processPartition;
10536 Label L_exit;
10537
10538 bind(L_processPartitions);
10539 cmpl(in_out1, 3 * size);
10540 jcc(Assembler::less, L_exit);
10541 xorl(tmp1, tmp1);
10542 xorl(tmp2, tmp2);
10543 movl(tmp3, in_out2);
10544 addl(tmp3, size);
10545
10546 bind(L_processPartition);
10547 crc32(in_out3, Address(in_out2, 0), 4);
10548 crc32(tmp1, Address(in_out2, size), 4);
10549 crc32(tmp2, Address(in_out2, size*2), 4);
10550 crc32(in_out3, Address(in_out2, 0+4), 4);
10551 crc32(tmp1, Address(in_out2, size+4), 4);
10552 crc32(tmp2, Address(in_out2, size*2+4), 4);
10553 addl(in_out2, 8);
10554 cmpl(in_out2, tmp3);
10555 jcc(Assembler::less, L_processPartition);
10556
10557 push(tmp3);
10558 push(in_out1);
10559 push(in_out2);
10560 tmp4 = tmp3;
10561 tmp5 = in_out1;
10562 n_tmp6 = in_out2;
10563
10564 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10565 w_xtmp1, w_xtmp2, w_xtmp3,
10566 tmp4, tmp5,
10567 n_tmp6);
10568
10569 pop(in_out2);
10570 pop(in_out1);
10571 pop(tmp3);
10572
10573 addl(in_out2, 2 * size);
10574 subl(in_out1, 3 * size);
10575 jmp(L_processPartitions);
10576
10577 bind(L_exit);
10578 }
10579 #endif //LP64
10580
10581 #ifdef _LP64
10582 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10583 // Input: A buffer I of L bytes.
10584 // Output: the CRC32C value of the buffer.
10585 // Notations:
10586 // Write L = 24N + r, with N = floor (L/24).
10587 // r = L mod 24 (0 <= r < 24).
10588 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10589 // N quadwords, and R consists of r bytes.
10590 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10591 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10592 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10593 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10594 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10595 Register tmp1, Register tmp2, Register tmp3,
10596 Register tmp4, Register tmp5, Register tmp6,
10597 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10598 bool is_pclmulqdq_supported) {
10599 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10600 Label L_wordByWord;
10601 Label L_byteByByteProlog;
10602 Label L_byteByByte;
10603 Label L_exit;
10604
10605 if (is_pclmulqdq_supported ) {
10606 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10607 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10608
10609 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10610 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10611
10612 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10613 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10614 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10615 } else {
10616 const_or_pre_comp_const_index[0] = 1;
10617 const_or_pre_comp_const_index[1] = 0;
10618
10619 const_or_pre_comp_const_index[2] = 3;
10620 const_or_pre_comp_const_index[3] = 2;
10621
10622 const_or_pre_comp_const_index[4] = 5;
10623 const_or_pre_comp_const_index[5] = 4;
10624 }
10625 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10626 in2, in1, in_out,
10627 tmp1, tmp2, tmp3,
10628 w_xtmp1, w_xtmp2, w_xtmp3,
10629 tmp4, tmp5,
10630 tmp6);
10631 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10632 in2, in1, in_out,
10633 tmp1, tmp2, tmp3,
10634 w_xtmp1, w_xtmp2, w_xtmp3,
10635 tmp4, tmp5,
10636 tmp6);
10637 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10638 in2, in1, in_out,
10639 tmp1, tmp2, tmp3,
10640 w_xtmp1, w_xtmp2, w_xtmp3,
10641 tmp4, tmp5,
10642 tmp6);
10643 movl(tmp1, in2);
10644 andl(tmp1, 0x00000007);
10645 negl(tmp1);
10646 addl(tmp1, in2);
10647 addq(tmp1, in1);
10648
10649 BIND(L_wordByWord);
10650 cmpq(in1, tmp1);
10651 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10652 crc32(in_out, Address(in1, 0), 4);
10653 addq(in1, 4);
10654 jmp(L_wordByWord);
10655
10656 BIND(L_byteByByteProlog);
10657 andl(in2, 0x00000007);
10658 movl(tmp2, 1);
10659
10660 BIND(L_byteByByte);
10661 cmpl(tmp2, in2);
10662 jccb(Assembler::greater, L_exit);
10663 crc32(in_out, Address(in1, 0), 1);
10664 incq(in1);
10665 incl(tmp2);
10666 jmp(L_byteByByte);
10667
10668 BIND(L_exit);
10669 }
10670 #else
10671 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10672 Register tmp1, Register tmp2, Register tmp3,
10673 Register tmp4, Register tmp5, Register tmp6,
10674 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10675 bool is_pclmulqdq_supported) {
10676 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10677 Label L_wordByWord;
10678 Label L_byteByByteProlog;
10679 Label L_byteByByte;
10680 Label L_exit;
10681
10682 if (is_pclmulqdq_supported) {
10683 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10684 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10685
10686 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10687 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10688
10689 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10690 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10691 } else {
10692 const_or_pre_comp_const_index[0] = 1;
10693 const_or_pre_comp_const_index[1] = 0;
10694
10695 const_or_pre_comp_const_index[2] = 3;
10696 const_or_pre_comp_const_index[3] = 2;
10697
10698 const_or_pre_comp_const_index[4] = 5;
10699 const_or_pre_comp_const_index[5] = 4;
10700 }
10701 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10702 in2, in1, in_out,
10703 tmp1, tmp2, tmp3,
10704 w_xtmp1, w_xtmp2, w_xtmp3,
10705 tmp4, tmp5,
10706 tmp6);
10707 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10708 in2, in1, in_out,
10709 tmp1, tmp2, tmp3,
10710 w_xtmp1, w_xtmp2, w_xtmp3,
10711 tmp4, tmp5,
10712 tmp6);
10713 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10714 in2, in1, in_out,
10715 tmp1, tmp2, tmp3,
10716 w_xtmp1, w_xtmp2, w_xtmp3,
10717 tmp4, tmp5,
10718 tmp6);
10719 movl(tmp1, in2);
10720 andl(tmp1, 0x00000007);
10721 negl(tmp1);
10722 addl(tmp1, in2);
10723 addl(tmp1, in1);
10724
10725 BIND(L_wordByWord);
10726 cmpl(in1, tmp1);
10727 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10728 crc32(in_out, Address(in1,0), 4);
10729 addl(in1, 4);
10730 jmp(L_wordByWord);
10731
10732 BIND(L_byteByByteProlog);
10733 andl(in2, 0x00000007);
10734 movl(tmp2, 1);
10735
10736 BIND(L_byteByByte);
10737 cmpl(tmp2, in2);
10738 jccb(Assembler::greater, L_exit);
10739 movb(tmp1, Address(in1, 0));
10740 crc32(in_out, tmp1, 1);
10741 incl(in1);
10742 incl(tmp2);
10743 jmp(L_byteByByte);
10744
10745 BIND(L_exit);
10746 }
10747 #endif // LP64
10748 #undef BIND
10749 #undef BLOCK_COMMENT
10750
10751
10752 // Compress char[] array to byte[].
10753 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10754 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10755 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10756 Register tmp5, Register result) {
10757 Label copy_chars_loop, return_length, return_zero, done;
10758
10759 // rsi: src
10760 // rdi: dst
10761 // rdx: len
10762 // rcx: tmp5
10763 // rax: result
10764
10765 // rsi holds start addr of source char[] to be compressed
10766 // rdi holds start addr of destination byte[]
10767 // rdx holds length
10768
10769 assert(len != result, "");
10770
10771 // save length for return
10772 push(len);
10773
10774 if (UseSSE42Intrinsics) {
10775 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
10776 Label copy_32_loop, copy_16, copy_tail;
10777
10778 movl(result, len);
10779 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10780
10781 // vectored compression
10782 andl(len, 0xfffffff0); // vector count (in chars)
10783 andl(result, 0x0000000f); // tail count (in chars)
10784 testl(len, len);
10785 jccb(Assembler::zero, copy_16);
10786
10787 // compress 16 chars per iter
10788 movdl(tmp1Reg, tmp5);
10789 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10790 pxor(tmp4Reg, tmp4Reg);
10791
10792 lea(src, Address(src, len, Address::times_2));
10793 lea(dst, Address(dst, len, Address::times_1));
10794 negptr(len);
10795
10796 bind(copy_32_loop);
10797 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10798 por(tmp4Reg, tmp2Reg);
10799 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10800 por(tmp4Reg, tmp3Reg);
10801 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10802 jcc(Assembler::notZero, return_zero);
10803 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10804 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10805 addptr(len, 16);
10806 jcc(Assembler::notZero, copy_32_loop);
10807
10808 // compress next vector of 8 chars (if any)
10809 bind(copy_16);
10810 movl(len, result);
10811 andl(len, 0xfffffff8); // vector count (in chars)
10812 andl(result, 0x00000007); // tail count (in chars)
10813 testl(len, len);
10814 jccb(Assembler::zero, copy_tail);
10815
10816 movdl(tmp1Reg, tmp5);
10817 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10818 pxor(tmp3Reg, tmp3Reg);
10819
10820 movdqu(tmp2Reg, Address(src, 0));
10821 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
10822 jccb(Assembler::notZero, return_zero);
10823 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
10824 movq(Address(dst, 0), tmp2Reg);
10825 addptr(src, 16);
10826 addptr(dst, 8);
10827
10828 bind(copy_tail);
10829 movl(len, result);
10830 }
10831 // compress 1 char per iter
10832 testl(len, len);
10833 jccb(Assembler::zero, return_length);
10834 lea(src, Address(src, len, Address::times_2));
10835 lea(dst, Address(dst, len, Address::times_1));
10836 negptr(len);
10837
10838 bind(copy_chars_loop);
10839 load_unsigned_short(result, Address(src, len, Address::times_2));
10840 testl(result, 0xff00); // check if Unicode char
10841 jccb(Assembler::notZero, return_zero);
10842 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
10843 increment(len);
10844 jcc(Assembler::notZero, copy_chars_loop);
10845
10846 // if compression succeeded, return length
10847 bind(return_length);
10848 pop(result);
10849 jmpb(done);
10850
10851 // if compression failed, return 0
10852 bind(return_zero);
10853 xorl(result, result);
10854 addptr(rsp, wordSize);
10855
10856 bind(done);
10857 }
10858
10859 // Inflate byte[] array to char[].
10860 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
10861 XMMRegister tmp1, Register tmp2) {
10862 Label copy_chars_loop, done;
10863
10864 // rsi: src
10865 // rdi: dst
10866 // rdx: len
10867 // rcx: tmp2
10868
10869 // rsi holds start addr of source byte[] to be inflated
10870 // rdi holds start addr of destination char[]
10871 // rdx holds length
10872 assert_different_registers(src, dst, len, tmp2);
10873
10874 if (UseSSE42Intrinsics) {
10875 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available");
10876 Label copy_8_loop, copy_bytes, copy_tail;
10877
10878 movl(tmp2, len);
10879 andl(tmp2, 0x00000007); // tail count (in chars)
10880 andl(len, 0xfffffff8); // vector count (in chars)
10881 jccb(Assembler::zero, copy_tail);
10882
10883 // vectored inflation
10884 lea(src, Address(src, len, Address::times_1));
10885 lea(dst, Address(dst, len, Address::times_2));
10886 negptr(len);
10887
10888 // inflate 8 chars per iter
10889 bind(copy_8_loop);
10890 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10891 movdqu(Address(dst, len, Address::times_2), tmp1);
10892 addptr(len, 8);
10893 jcc(Assembler::notZero, copy_8_loop);
10894
10895 bind(copy_tail);
10896 movl(len, tmp2);
10897
10898 cmpl(len, 4);
10899 jccb(Assembler::less, copy_bytes);
10900
10901 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10902 pmovzxbw(tmp1, tmp1);
10903 movq(Address(dst, 0), tmp1);
10904 subptr(len, 4);
10905 addptr(src, 4);
10906 addptr(dst, 8);
10907
10908 bind(copy_bytes);
10909 }
10910 testl(len, len);
10911 jccb(Assembler::zero, done);
10912 lea(src, Address(src, len, Address::times_1));
10913 lea(dst, Address(dst, len, Address::times_2));
10914 negptr(len);
10915
10916 // inflate 1 char per iter
10917 bind(copy_chars_loop);
10918 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10919 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10920 increment(len);
10921 jcc(Assembler::notZero, copy_chars_loop);
10922
10923 bind(done);
10924 }
10925
10926
10927 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10928 switch (cond) {
10929 // Note some conditions are synonyms for others
10930 case Assembler::zero: return Assembler::notZero;
10931 case Assembler::notZero: return Assembler::zero;
10932 case Assembler::less: return Assembler::greaterEqual;
10933 case Assembler::lessEqual: return Assembler::greater;
10934 case Assembler::greater: return Assembler::lessEqual;
10935 case Assembler::greaterEqual: return Assembler::less;
10936 case Assembler::below: return Assembler::aboveEqual;
10937 case Assembler::belowEqual: return Assembler::above;
10938 case Assembler::above: return Assembler::belowEqual;
10939 case Assembler::aboveEqual: return Assembler::below;
10940 case Assembler::overflow: return Assembler::noOverflow;
10941 case Assembler::noOverflow: return Assembler::overflow;
10942 case Assembler::negative: return Assembler::positive;
10943 case Assembler::positive: return Assembler::negative;
10944 case Assembler::parity: return Assembler::noParity;
10945 case Assembler::noParity: return Assembler::parity;
10946 }
10947 ShouldNotReachHere(); return Assembler::overflow;
10948 }
10949
10950 SkipIfEqual::SkipIfEqual(
10951 MacroAssembler* masm, const bool* flag_addr, bool value) {
10952 _masm = masm;
10953 _masm->cmp8(ExternalAddress((address)flag_addr), value);
10954 _masm->jcc(Assembler::equal, _label);
10955 }
10956
10957 SkipIfEqual::~SkipIfEqual() {
10958 _masm->bind(_label);
10959 }
10960
10961 // 32-bit Windows has its own fast-path implementation
10962 // of get_thread
10963 #if !defined(WIN32) || defined(_LP64)
10964
10965 // This is simply a call to Thread::current()
10966 void MacroAssembler::get_thread(Register thread) {
10967 if (thread != rax) {
10968 push(rax);
10969 }
10970 LP64_ONLY(push(rdi);)
10971 LP64_ONLY(push(rsi);)
10972 push(rdx);
10973 push(rcx);
10974 #ifdef _LP64
10975 push(r8);
10976 push(r9);
10977 push(r10);
10978 push(r11);
10979 #endif
10980
10981 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10982
10983 #ifdef _LP64
10984 pop(r11);
10985 pop(r10);
10986 pop(r9);
10987 pop(r8);
10988 #endif
10989 pop(rcx);
10990 pop(rdx);
10991 LP64_ONLY(pop(rsi);)
10992 LP64_ONLY(pop(rdi);)
10993 if (thread != rax) {
10994 mov(thread, rax);
10995 pop(rax);
10996 }
10997 }
10998
10999 #endif