312 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
313 }
314
315 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
316 if (has_sha1() || has_sha256() || has_sha512()) {
317 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
318 if (FLAG_IS_DEFAULT(UseSHA)) {
319 FLAG_SET_DEFAULT(UseSHA, true);
320 }
321 } else {
322 if (UseSHA) {
323 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
324 FLAG_SET_DEFAULT(UseSHA, false);
325 }
326 }
327 } else if (UseSHA) {
328 warning("SHA instructions are not available on this CPU");
329 FLAG_SET_DEFAULT(UseSHA, false);
330 }
331
332 if (!UseSHA) {
333 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
334 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
335 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
336 } else {
337 if (has_sha1()) {
338 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
339 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
340 }
341 } else if (UseSHA1Intrinsics) {
342 warning("SHA1 instruction is not available on this CPU.");
343 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
344 }
345 if (has_sha256()) {
346 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
347 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
348 }
349 } else if (UseSHA256Intrinsics) {
350 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
351 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
352 }
353
354 if (has_sha512()) {
355 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
356 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
357 }
358 } else if (UseSHA512Intrinsics) {
359 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
360 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
361 }
362 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
363 FLAG_SET_DEFAULT(UseSHA, false);
364 }
365 }
366
367 // SPARC T4 and above should have support for CRC32C instruction
368 if (has_crc32c()) {
369 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
370 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
371 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
372 }
373 } else {
374 if (UseCRC32CIntrinsics) {
375 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
376 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
377 }
378 }
379 } else if (UseCRC32CIntrinsics) {
380 warning("CRC32C instruction is not available on this CPU");
381 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
382 }
383
384 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
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312 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
313 }
314
315 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
316 if (has_sha1() || has_sha256() || has_sha512()) {
317 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
318 if (FLAG_IS_DEFAULT(UseSHA)) {
319 FLAG_SET_DEFAULT(UseSHA, true);
320 }
321 } else {
322 if (UseSHA) {
323 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
324 FLAG_SET_DEFAULT(UseSHA, false);
325 }
326 }
327 } else if (UseSHA) {
328 warning("SHA instructions are not available on this CPU");
329 FLAG_SET_DEFAULT(UseSHA, false);
330 }
331
332 if (UseSHA && has_sha1()) {
333 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
334 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
335 }
336 } else if (UseSHA1Intrinsics) {
337 warning("Intrinsics for SHA-1 crypto hash functions not available.");
338 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
339 }
340
341 if (UseSHA && has_sha256()) {
342 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
343 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
344 }
345 } else if (UseSHA256Intrinsics) {
346 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available.");
347 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
348 }
349
350 if (UseSHA && has_sha512()) {
351 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
352 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
353 }
354 } else if (UseSHA512Intrinsics) {
355 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available.");
356 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
357 }
358
359 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
360 FLAG_SET_DEFAULT(UseSHA, false);
361 }
362
363 // SPARC T4 and above should have support for CRC32C instruction
364 if (has_crc32c()) {
365 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
366 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
367 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
368 }
369 } else {
370 if (UseCRC32CIntrinsics) {
371 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
372 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
373 }
374 }
375 } else if (UseCRC32CIntrinsics) {
376 warning("CRC32C instruction is not available on this CPU");
377 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
378 }
379
380 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
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