1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "memory/resourceArea.hpp"
  29 #include "runtime/java.hpp"
  30 #include "runtime/os.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "vm_version_x86.hpp"
  33 
  34 
  35 int VM_Version::_cpu;
  36 int VM_Version::_model;
  37 int VM_Version::_stepping;
  38 uint64_t VM_Version::_cpuFeatures;
  39 const char*           VM_Version::_features_str = "";
  40 VM_Version::CpuidInfo VM_Version::_cpuid_info   = { 0, };
  41 
  42 // Address of instruction which causes SEGV
  43 address VM_Version::_cpuinfo_segv_addr = 0;
  44 // Address of instruction after the one which causes SEGV
  45 address VM_Version::_cpuinfo_cont_addr = 0;
  46 
  47 static BufferBlob* stub_blob;
  48 static const int stub_size = 1000;
  49 
  50 extern "C" {
  51   typedef void (*get_cpu_info_stub_t)(void*);
  52 }
  53 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  54 
  55 
  56 class VM_Version_StubGenerator: public StubCodeGenerator {
  57  public:
  58 
  59   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  60 
  61   address generate_get_cpu_info() {
  62     // Flags to test CPU type.
  63     const uint32_t HS_EFL_AC = 0x40000;
  64     const uint32_t HS_EFL_ID = 0x200000;
  65     // Values for when we don't have a CPUID instruction.
  66     const int      CPU_FAMILY_SHIFT = 8;
  67     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
  68     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
  69 
  70     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
  71     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup;
  72     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
  73 
  74     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
  75 #   define __ _masm->
  76 
  77     address start = __ pc();
  78 
  79     //
  80     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
  81     //
  82     // LP64: rcx and rdx are first and second argument registers on windows
  83 
  84     __ push(rbp);
  85 #ifdef _LP64
  86     __ mov(rbp, c_rarg0); // cpuid_info address
  87 #else
  88     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
  89 #endif
  90     __ push(rbx);
  91     __ push(rsi);
  92     __ pushf();          // preserve rbx, and flags
  93     __ pop(rax);
  94     __ push(rax);
  95     __ mov(rcx, rax);
  96     //
  97     // if we are unable to change the AC flag, we have a 386
  98     //
  99     __ xorl(rax, HS_EFL_AC);
 100     __ push(rax);
 101     __ popf();
 102     __ pushf();
 103     __ pop(rax);
 104     __ cmpptr(rax, rcx);
 105     __ jccb(Assembler::notEqual, detect_486);
 106 
 107     __ movl(rax, CPU_FAMILY_386);
 108     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 109     __ jmp(done);
 110 
 111     //
 112     // If we are unable to change the ID flag, we have a 486 which does
 113     // not support the "cpuid" instruction.
 114     //
 115     __ bind(detect_486);
 116     __ mov(rax, rcx);
 117     __ xorl(rax, HS_EFL_ID);
 118     __ push(rax);
 119     __ popf();
 120     __ pushf();
 121     __ pop(rax);
 122     __ cmpptr(rcx, rax);
 123     __ jccb(Assembler::notEqual, detect_586);
 124 
 125     __ bind(cpu486);
 126     __ movl(rax, CPU_FAMILY_486);
 127     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 128     __ jmp(done);
 129 
 130     //
 131     // At this point, we have a chip which supports the "cpuid" instruction
 132     //
 133     __ bind(detect_586);
 134     __ xorl(rax, rax);
 135     __ cpuid();
 136     __ orl(rax, rax);
 137     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 138                                         // value of at least 1, we give up and
 139                                         // assume a 486
 140     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 141     __ movl(Address(rsi, 0), rax);
 142     __ movl(Address(rsi, 4), rbx);
 143     __ movl(Address(rsi, 8), rcx);
 144     __ movl(Address(rsi,12), rdx);
 145 
 146     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 147     __ jccb(Assembler::belowEqual, std_cpuid4);
 148 
 149     //
 150     // cpuid(0xB) Processor Topology
 151     //
 152     __ movl(rax, 0xb);
 153     __ xorl(rcx, rcx);   // Threads level
 154     __ cpuid();
 155 
 156     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 157     __ movl(Address(rsi, 0), rax);
 158     __ movl(Address(rsi, 4), rbx);
 159     __ movl(Address(rsi, 8), rcx);
 160     __ movl(Address(rsi,12), rdx);
 161 
 162     __ movl(rax, 0xb);
 163     __ movl(rcx, 1);     // Cores level
 164     __ cpuid();
 165     __ push(rax);
 166     __ andl(rax, 0x1f);  // Determine if valid topology level
 167     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 168     __ andl(rax, 0xffff);
 169     __ pop(rax);
 170     __ jccb(Assembler::equal, std_cpuid4);
 171 
 172     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 173     __ movl(Address(rsi, 0), rax);
 174     __ movl(Address(rsi, 4), rbx);
 175     __ movl(Address(rsi, 8), rcx);
 176     __ movl(Address(rsi,12), rdx);
 177 
 178     __ movl(rax, 0xb);
 179     __ movl(rcx, 2);     // Packages level
 180     __ cpuid();
 181     __ push(rax);
 182     __ andl(rax, 0x1f);  // Determine if valid topology level
 183     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 184     __ andl(rax, 0xffff);
 185     __ pop(rax);
 186     __ jccb(Assembler::equal, std_cpuid4);
 187 
 188     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 189     __ movl(Address(rsi, 0), rax);
 190     __ movl(Address(rsi, 4), rbx);
 191     __ movl(Address(rsi, 8), rcx);
 192     __ movl(Address(rsi,12), rdx);
 193 
 194     //
 195     // cpuid(0x4) Deterministic cache params
 196     //
 197     __ bind(std_cpuid4);
 198     __ movl(rax, 4);
 199     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 200     __ jccb(Assembler::greater, std_cpuid1);
 201 
 202     __ xorl(rcx, rcx);   // L1 cache
 203     __ cpuid();
 204     __ push(rax);
 205     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 206     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 207     __ pop(rax);
 208     __ jccb(Assembler::equal, std_cpuid1);
 209 
 210     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 211     __ movl(Address(rsi, 0), rax);
 212     __ movl(Address(rsi, 4), rbx);
 213     __ movl(Address(rsi, 8), rcx);
 214     __ movl(Address(rsi,12), rdx);
 215 
 216     //
 217     // Standard cpuid(0x1)
 218     //
 219     __ bind(std_cpuid1);
 220     __ movl(rax, 1);
 221     __ cpuid();
 222     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 223     __ movl(Address(rsi, 0), rax);
 224     __ movl(Address(rsi, 4), rbx);
 225     __ movl(Address(rsi, 8), rcx);
 226     __ movl(Address(rsi,12), rdx);
 227 
 228     //
 229     // Check if OS has enabled XGETBV instruction to access XCR0
 230     // (OSXSAVE feature flag) and CPU supports AVX
 231     //
 232     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 233     __ cmpl(rcx, 0x18000000);
 234     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 235 
 236     //
 237     // XCR0, XFEATURE_ENABLED_MASK register
 238     //
 239     __ xorl(rcx, rcx);   // zero for XCR0 register
 240     __ xgetbv();
 241     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 242     __ movl(Address(rsi, 0), rax);
 243     __ movl(Address(rsi, 4), rdx);
 244 
 245     //
 246     // cpuid(0x7) Structured Extended Features
 247     //
 248     __ bind(sef_cpuid);
 249     __ movl(rax, 7);
 250     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 251     __ jccb(Assembler::greater, ext_cpuid);
 252 
 253     __ xorl(rcx, rcx);
 254     __ cpuid();
 255     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 256     __ movl(Address(rsi, 0), rax);
 257     __ movl(Address(rsi, 4), rbx);
 258 
 259     //
 260     // Extended cpuid(0x80000000)
 261     //
 262     __ bind(ext_cpuid);
 263     __ movl(rax, 0x80000000);
 264     __ cpuid();
 265     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 266     __ jcc(Assembler::belowEqual, done);
 267     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 268     __ jccb(Assembler::belowEqual, ext_cpuid1);
 269     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 270     __ jccb(Assembler::belowEqual, ext_cpuid5);
 271     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 272     __ jccb(Assembler::belowEqual, ext_cpuid7);
 273     //
 274     // Extended cpuid(0x80000008)
 275     //
 276     __ movl(rax, 0x80000008);
 277     __ cpuid();
 278     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 279     __ movl(Address(rsi, 0), rax);
 280     __ movl(Address(rsi, 4), rbx);
 281     __ movl(Address(rsi, 8), rcx);
 282     __ movl(Address(rsi,12), rdx);
 283 
 284     //
 285     // Extended cpuid(0x80000007)
 286     //
 287     __ bind(ext_cpuid7);
 288     __ movl(rax, 0x80000007);
 289     __ cpuid();
 290     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 291     __ movl(Address(rsi, 0), rax);
 292     __ movl(Address(rsi, 4), rbx);
 293     __ movl(Address(rsi, 8), rcx);
 294     __ movl(Address(rsi,12), rdx);
 295 
 296     //
 297     // Extended cpuid(0x80000005)
 298     //
 299     __ bind(ext_cpuid5);
 300     __ movl(rax, 0x80000005);
 301     __ cpuid();
 302     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 303     __ movl(Address(rsi, 0), rax);
 304     __ movl(Address(rsi, 4), rbx);
 305     __ movl(Address(rsi, 8), rcx);
 306     __ movl(Address(rsi,12), rdx);
 307 
 308     //
 309     // Extended cpuid(0x80000001)
 310     //
 311     __ bind(ext_cpuid1);
 312     __ movl(rax, 0x80000001);
 313     __ cpuid();
 314     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 315     __ movl(Address(rsi, 0), rax);
 316     __ movl(Address(rsi, 4), rbx);
 317     __ movl(Address(rsi, 8), rcx);
 318     __ movl(Address(rsi,12), rdx);
 319 
 320     //
 321     // Check if OS has enabled XGETBV instruction to access XCR0
 322     // (OSXSAVE feature flag) and CPU supports AVX
 323     //
 324     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 325     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 326     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 327     __ cmpl(rcx, 0x18000000);
 328     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 329 
 330     __ movl(rax, 0x6);
 331     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 332     __ cmpl(rax, 0x6);
 333     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 334 
 335     // we need to bridge farther than imm8, so we use this island as a thunk
 336     __ bind(done);
 337     __ jmp(wrapup);
 338 
 339     __ bind(start_simd_check);
 340     //
 341     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 342     // registers are not restored after a signal processing.
 343     // Generate SEGV here (reference through NULL)
 344     // and check upper YMM/ZMM bits after it.
 345     //
 346     intx saved_useavx = UseAVX;
 347     intx saved_usesse = UseSSE;
 348     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 349     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 350     __ movl(rax, 0x10000);
 351     __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 352     __ cmpl(rax, 0x10000);
 353     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 354     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 355     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 356     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 357     __ movl(rax, 0xE0);
 358     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 359     __ cmpl(rax, 0xE0);
 360     __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 361 
 362     // EVEX setup: run in lowest evex mode
 363     VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 364     UseAVX = 3;
 365     UseSSE = 2;
 366     // load value into all 64 bytes of zmm7 register
 367     __ movl(rcx, VM_Version::ymm_test_value());
 368     __ movdl(xmm0, rcx);
 369     __ movl(rcx, 0xffff);
 370     __ kmovwl(k1, rcx);
 371     __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 372     __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 373 #ifdef _LP64
 374     __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 375     __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 376 #endif
 377     VM_Version::clean_cpuFeatures();
 378     __ jmp(save_restore_except);
 379 
 380     __ bind(legacy_setup);
 381     // AVX setup
 382     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 383     UseAVX = 1;
 384     UseSSE = 2;
 385     // load value into all 32 bytes of ymm7 register
 386     __ movl(rcx, VM_Version::ymm_test_value());
 387 
 388     __ movdl(xmm0, rcx);
 389     __ pshufd(xmm0, xmm0, 0x00);
 390     __ vinsertf128h(xmm0, xmm0, xmm0);
 391     __ vmovdqu(xmm7, xmm0);
 392 #ifdef _LP64
 393     __ vmovdqu(xmm8, xmm0);
 394     __ vmovdqu(xmm15, xmm0);
 395 #endif
 396     VM_Version::clean_cpuFeatures();
 397 
 398     __ bind(save_restore_except);
 399     __ xorl(rsi, rsi);
 400     VM_Version::set_cpuinfo_segv_addr(__ pc());
 401     // Generate SEGV
 402     __ movl(rax, Address(rsi, 0));
 403 
 404     VM_Version::set_cpuinfo_cont_addr(__ pc());
 405     // Returns here after signal. Save xmm0 to check it later.
 406 
 407     // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 408     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 409     __ movl(rax, 0x10000);
 410     __ andl(rax, Address(rsi, 4));
 411     __ cmpl(rax, 0x10000);
 412     __ jccb(Assembler::notEqual, legacy_save_restore);
 413     // check _cpuid_info.xem_xcr0_eax.bits.opmask
 414     // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 415     // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 416     __ movl(rax, 0xE0);
 417     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 418     __ cmpl(rax, 0xE0);
 419     __ jccb(Assembler::notEqual, legacy_save_restore);
 420 
 421     // EVEX check: run in lowest evex mode
 422     VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 423     UseAVX = 3;
 424     UseSSE = 2;
 425     __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 426     __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 427     __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 428 #ifdef _LP64
 429     __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 430     __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 431 #endif
 432     VM_Version::clean_cpuFeatures();
 433     UseAVX = saved_useavx;
 434     UseSSE = saved_usesse;
 435     __ jmp(wrapup);
 436 
 437     __ bind(legacy_save_restore);
 438     // AVX check
 439     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 440     UseAVX = 1;
 441     UseSSE = 2;
 442     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 443     __ vmovdqu(Address(rsi, 0), xmm0);
 444     __ vmovdqu(Address(rsi, 32), xmm7);
 445 #ifdef _LP64
 446     __ vmovdqu(Address(rsi, 64), xmm8);
 447     __ vmovdqu(Address(rsi, 96), xmm15);
 448 #endif
 449     VM_Version::clean_cpuFeatures();
 450     UseAVX = saved_useavx;
 451     UseSSE = saved_usesse;
 452 
 453     __ bind(wrapup);
 454     __ popf();
 455     __ pop(rsi);
 456     __ pop(rbx);
 457     __ pop(rbp);
 458     __ ret(0);
 459 
 460 #   undef __
 461 
 462     return start;
 463   };
 464 };
 465 
 466 void VM_Version::get_processor_features() {
 467 
 468   _cpu = 4; // 486 by default
 469   _model = 0;
 470   _stepping = 0;
 471   _cpuFeatures = 0;
 472   _logical_processors_per_package = 1;
 473   // i486 internal cache is both I&D and has a 16-byte line size
 474   _L1_data_cache_line_size = 16;
 475 
 476   if (!Use486InstrsOnly) {
 477     // Get raw processor info
 478 
 479     get_cpu_info_stub(&_cpuid_info);
 480 
 481     assert_is_initialized();
 482     _cpu = extended_cpu_family();
 483     _model = extended_cpu_model();
 484     _stepping = cpu_stepping();
 485 
 486     if (cpu_family() > 4) { // it supports CPUID
 487       _cpuFeatures = feature_flags();
 488       // Logical processors are only available on P4s and above,
 489       // and only if hyperthreading is available.
 490       _logical_processors_per_package = logical_processor_count();
 491       _L1_data_cache_line_size = L1_line_size();
 492     }
 493   }
 494 
 495   _supports_cx8 = supports_cmpxchg8();
 496   // xchg and xadd instructions
 497   _supports_atomic_getset4 = true;
 498   _supports_atomic_getadd4 = true;
 499   LP64_ONLY(_supports_atomic_getset8 = true);
 500   LP64_ONLY(_supports_atomic_getadd8 = true);
 501 
 502 #ifdef _LP64
 503   // OS should support SSE for x64 and hardware should support at least SSE2.
 504   if (!VM_Version::supports_sse2()) {
 505     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 506   }
 507   // in 64 bit the use of SSE2 is the minimum
 508   if (UseSSE < 2) UseSSE = 2;
 509 #endif
 510 
 511 #ifdef AMD64
 512   // flush_icache_stub have to be generated first.
 513   // That is why Icache line size is hard coded in ICache class,
 514   // see icache_x86.hpp. It is also the reason why we can't use
 515   // clflush instruction in 32-bit VM since it could be running
 516   // on CPU which does not support it.
 517   //
 518   // The only thing we can do is to verify that flushed
 519   // ICache::line_size has correct value.
 520   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 521   // clflush_size is size in quadwords (8 bytes).
 522   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 523 #endif
 524 
 525   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 526   if (!os::supports_sse())
 527     _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 528 
 529   if (UseSSE < 4) {
 530     _cpuFeatures &= ~CPU_SSE4_1;
 531     _cpuFeatures &= ~CPU_SSE4_2;
 532   }
 533 
 534   if (UseSSE < 3) {
 535     _cpuFeatures &= ~CPU_SSE3;
 536     _cpuFeatures &= ~CPU_SSSE3;
 537     _cpuFeatures &= ~CPU_SSE4A;
 538   }
 539 
 540   if (UseSSE < 2)
 541     _cpuFeatures &= ~CPU_SSE2;
 542 
 543   if (UseSSE < 1)
 544     _cpuFeatures &= ~CPU_SSE;
 545 
 546   // first try initial setting and detect what we can support
 547   if (UseAVX > 0) {
 548     if (UseAVX > 2 && supports_evex()) {
 549       UseAVX = 3;
 550     } else if (UseAVX > 1 && supports_avx2()) {
 551       UseAVX = 2;
 552     } else if (UseAVX > 0 && supports_avx()) {
 553       UseAVX = 1;
 554     } else {
 555       UseAVX = 0;
 556     }
 557   } else if (UseAVX < 0) {
 558     UseAVX = 0;
 559   }
 560 
 561   if (UseAVX < 3) {
 562     _cpuFeatures &= ~CPU_AVX512F;
 563     _cpuFeatures &= ~CPU_AVX512DQ;
 564     _cpuFeatures &= ~CPU_AVX512CD;
 565     _cpuFeatures &= ~CPU_AVX512BW;
 566     _cpuFeatures &= ~CPU_AVX512VL;
 567   }
 568 
 569   if (UseAVX < 2)
 570     _cpuFeatures &= ~CPU_AVX2;
 571 
 572   if (UseAVX < 1)
 573     _cpuFeatures &= ~CPU_AVX;
 574 
 575   if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
 576     _cpuFeatures &= ~CPU_AES;
 577 
 578   if (logical_processors_per_package() == 1) {
 579     // HT processor could be installed on a system which doesn't support HT.
 580     _cpuFeatures &= ~CPU_HT;
 581   }
 582 
 583   char buf[256];
 584   jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 585                cores_per_cpu(), threads_per_core(),
 586                cpu_family(), _model, _stepping,
 587                (supports_cmov() ? ", cmov" : ""),
 588                (supports_cmpxchg8() ? ", cx8" : ""),
 589                (supports_fxsr() ? ", fxsr" : ""),
 590                (supports_mmx()  ? ", mmx"  : ""),
 591                (supports_sse()  ? ", sse"  : ""),
 592                (supports_sse2() ? ", sse2" : ""),
 593                (supports_sse3() ? ", sse3" : ""),
 594                (supports_ssse3()? ", ssse3": ""),
 595                (supports_sse4_1() ? ", sse4.1" : ""),
 596                (supports_sse4_2() ? ", sse4.2" : ""),
 597                (supports_popcnt() ? ", popcnt" : ""),
 598                (supports_avx()    ? ", avx" : ""),
 599                (supports_avx2()   ? ", avx2" : ""),
 600                (supports_aes()    ? ", aes" : ""),
 601                (supports_clmul()  ? ", clmul" : ""),
 602                (supports_erms()   ? ", erms" : ""),
 603                (supports_rtm()    ? ", rtm" : ""),
 604                (supports_mmx_ext() ? ", mmxext" : ""),
 605                (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
 606                (supports_lzcnt()   ? ", lzcnt": ""),
 607                (supports_sse4a()   ? ", sse4a": ""),
 608                (supports_ht() ? ", ht": ""),
 609                (supports_tsc() ? ", tsc": ""),
 610                (supports_tscinv_bit() ? ", tscinvbit": ""),
 611                (supports_tscinv() ? ", tscinv": ""),
 612                (supports_bmi1() ? ", bmi1" : ""),
 613                (supports_bmi2() ? ", bmi2" : ""),
 614                (supports_adx() ? ", adx" : ""),
 615                (supports_evex() ? ", evex" : ""));
 616   _features_str = os::strdup(buf);
 617 
 618   // UseSSE is set to the smaller of what hardware supports and what
 619   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 620   // older Pentiums which do not support it.
 621   if (UseSSE > 4) UseSSE=4;
 622   if (UseSSE < 0) UseSSE=0;
 623   if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
 624     UseSSE = MIN2((intx)3,UseSSE);
 625   if (!supports_sse3()) // Drop to 2 if no SSE3 support
 626     UseSSE = MIN2((intx)2,UseSSE);
 627   if (!supports_sse2()) // Drop to 1 if no SSE2 support
 628     UseSSE = MIN2((intx)1,UseSSE);
 629   if (!supports_sse ()) // Drop to 0 if no SSE  support
 630     UseSSE = 0;
 631 
 632   // Use AES instructions if available.
 633   if (supports_aes()) {
 634     if (FLAG_IS_DEFAULT(UseAES)) {
 635       FLAG_SET_DEFAULT(UseAES, true);
 636     }
 637     if (!UseAES) {
 638       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 639         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
 640       }
 641       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 642     } else {
 643       if (UseSSE > 2) {
 644         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 645           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
 646         }
 647       } else {
 648         // The AES intrinsic stubs require AES instruction support (of course)
 649         // but also require sse3 mode or higher for instructions it use.
 650         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 651           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
 652         }
 653         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 654       }
 655     }
 656   } else if (UseAES || UseAESIntrinsics) {
 657     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
 658       warning("AES instructions are not available on this CPU");
 659       FLAG_SET_DEFAULT(UseAES, false);
 660     }
 661     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 662       warning("AES intrinsics are not available on this CPU");
 663       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 664     }
 665   }
 666 
 667   // Use CLMUL instructions if available.
 668   if (supports_clmul()) {
 669     if (FLAG_IS_DEFAULT(UseCLMUL)) {
 670       UseCLMUL = true;
 671     }
 672   } else if (UseCLMUL) {
 673     if (!FLAG_IS_DEFAULT(UseCLMUL))
 674       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
 675     FLAG_SET_DEFAULT(UseCLMUL, false);
 676   }
 677 
 678   if (UseCLMUL && (UseSSE > 2)) {
 679     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 680       UseCRC32Intrinsics = true;
 681     }
 682   } else if (UseCRC32Intrinsics) {
 683     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
 684       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
 685     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
 686   }
 687 
 688   if (supports_sse4_2()) {
 689     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 690       UseCRC32CIntrinsics = true;
 691     }
 692   }
 693   else if (UseCRC32CIntrinsics) {
 694     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 695       warning("CRC32C intrinsics are not available on this CPU");
 696     }
 697     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 698   }
 699 
 700   // GHASH/GCM intrinsics
 701   if (UseCLMUL && (UseSSE > 2)) {
 702     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 703       UseGHASHIntrinsics = true;
 704     }
 705   } else if (UseGHASHIntrinsics) {
 706     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
 707       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
 708     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 709   }
 710 
 711   if (UseSHA) {
 712     warning("SHA instructions are not available on this CPU");
 713     FLAG_SET_DEFAULT(UseSHA, false);
 714   }
 715 
 716   if (UseSHA1Intrinsics) {
 717     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 718     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 719   }
 720 
 721   if (UseSHA256Intrinsics) {
 722     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 723     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 724   }
 725 
 726   if (UseSHA512Intrinsics) {
 727     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 728     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 729   }
 730 
 731   if (UseAdler32Intrinsics) {
 732     warning("Adler32Intrinsics not available on this CPU.");
 733     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 734   }
 735 
 736   // Adjust RTM (Restricted Transactional Memory) flags
 737   if (!supports_rtm() && UseRTMLocking) {
 738     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 739     // setting during arguments processing. See use_biased_locking().
 740     // VM_Version_init() is executed after UseBiasedLocking is used
 741     // in Thread::allocate().
 742     vm_exit_during_initialization("RTM instructions are not available on this CPU");
 743   }
 744 
 745 #if INCLUDE_RTM_OPT
 746   if (UseRTMLocking) {
 747     if (is_intel_family_core()) {
 748       if ((_model == CPU_MODEL_HASWELL_E3) ||
 749           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
 750           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
 751         // currently a collision between SKL and HSW_E3
 752         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
 753           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 754         } else {
 755           warning("UseRTMLocking is only available as experimental option on this platform.");
 756         }
 757       }
 758     }
 759     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 760       // RTM locking should be used only for applications with
 761       // high lock contention. For now we do not use it by default.
 762       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 763     }
 764     if (!is_power_of_2(RTMTotalCountIncrRate)) {
 765       warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
 766       FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
 767     }
 768     if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
 769       warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
 770       FLAG_SET_DEFAULT(RTMAbortRatio, 50);
 771     }
 772   } else { // !UseRTMLocking
 773     if (UseRTMForStackLocks) {
 774       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 775         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 776       }
 777       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 778     }
 779     if (UseRTMDeopt) {
 780       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 781     }
 782     if (PrintPreciseRTMLockingStatistics) {
 783       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 784     }
 785   }
 786 #else
 787   if (UseRTMLocking) {
 788     // Only C2 does RTM locking optimization.
 789     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 790     // setting during arguments processing. See use_biased_locking().
 791     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 792   }
 793 #endif
 794 
 795 #ifdef COMPILER2
 796   if (UseFPUForSpilling) {
 797     if (UseSSE < 2) {
 798       // Only supported with SSE2+
 799       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
 800     }
 801   }
 802 #endif
 803 #if defined(COMPILER2) || INCLUDE_JVMCI
 804   if (MaxVectorSize > 0) {
 805     if (!is_power_of_2(MaxVectorSize)) {
 806       warning("MaxVectorSize must be a power of 2");
 807       FLAG_SET_DEFAULT(MaxVectorSize, 64);
 808     }
 809     if (MaxVectorSize > 64) {
 810       FLAG_SET_DEFAULT(MaxVectorSize, 64);
 811     }
 812     if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
 813       // 32 bytes vectors (in YMM) are only supported with AVX+
 814       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 815     }
 816     if (UseSSE < 2) {
 817       // Vectors (in XMM) are only supported with SSE2+
 818       FLAG_SET_DEFAULT(MaxVectorSize, 0);
 819     }
 820 #if defined(COMPILER2) && defined(ASSERT)
 821     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
 822       tty->print_cr("State of YMM registers after signal handle:");
 823       int nreg = 2 LP64_ONLY(+2);
 824       const char* ymm_name[4] = {"0", "7", "8", "15"};
 825       for (int i = 0; i < nreg; i++) {
 826         tty->print("YMM%s:", ymm_name[i]);
 827         for (int j = 7; j >=0; j--) {
 828           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
 829         }
 830         tty->cr();
 831       }
 832     }
 833 #endif // COMPILER2 && ASSERT
 834   }
 835 #endif // COMPILER2 || INCLUDE_JVMCI
 836 
 837 #ifdef COMPILER2
 838 #ifdef _LP64
 839   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 840     UseMultiplyToLenIntrinsic = true;
 841   }
 842   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 843     UseSquareToLenIntrinsic = true;
 844   }
 845   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 846     UseMulAddIntrinsic = true;
 847   }
 848   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 849     UseMontgomeryMultiplyIntrinsic = true;
 850   }
 851   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 852     UseMontgomerySquareIntrinsic = true;
 853   }
 854 #else
 855   if (UseMultiplyToLenIntrinsic) {
 856     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 857       warning("multiplyToLen intrinsic is not available in 32-bit VM");
 858     }
 859     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
 860   }
 861   if (UseMontgomeryMultiplyIntrinsic) {
 862     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 863       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
 864     }
 865     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
 866   }
 867   if (UseMontgomerySquareIntrinsic) {
 868     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 869       warning("montgomerySquare intrinsic is not available in 32-bit VM");
 870     }
 871     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
 872   }
 873   if (UseSquareToLenIntrinsic) {
 874     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
 875       warning("squareToLen intrinsic is not available in 32-bit VM");
 876     }
 877     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
 878   }
 879   if (UseMulAddIntrinsic) {
 880     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
 881       warning("mulAdd intrinsic is not available in 32-bit VM");
 882     }
 883     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
 884   }
 885 #endif
 886 #endif // COMPILER2
 887 
 888   // On new cpus instructions which update whole XMM register should be used
 889   // to prevent partial register stall due to dependencies on high half.
 890   //
 891   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
 892   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
 893   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
 894   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
 895 
 896   if( is_amd() ) { // AMD cpus specific settings
 897     if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
 898       // Use it on new AMD cpus starting from Opteron.
 899       UseAddressNop = true;
 900     }
 901     if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
 902       // Use it on new AMD cpus starting from Opteron.
 903       UseNewLongLShift = true;
 904     }
 905     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 906       if (supports_sse4a()) {
 907         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
 908       } else {
 909         UseXmmLoadAndClearUpper = false;
 910       }
 911     }
 912     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 913       if( supports_sse4a() ) {
 914         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
 915       } else {
 916         UseXmmRegToRegMoveAll = false;
 917       }
 918     }
 919     if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
 920       if( supports_sse4a() ) {
 921         UseXmmI2F = true;
 922       } else {
 923         UseXmmI2F = false;
 924       }
 925     }
 926     if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
 927       if( supports_sse4a() ) {
 928         UseXmmI2D = true;
 929       } else {
 930         UseXmmI2D = false;
 931       }
 932     }
 933     if (supports_sse4_2() && UseSSE >= 4) {
 934       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
 935         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
 936       }
 937     } else {
 938       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 939         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
 940       }
 941       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
 942     }
 943 
 944     // some defaults for AMD family 15h
 945     if ( cpu_family() == 0x15 ) {
 946       // On family 15h processors default is no sw prefetch
 947       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
 948         AllocatePrefetchStyle = 0;
 949       }
 950       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
 951       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
 952         AllocatePrefetchInstr = 3;
 953       }
 954       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
 955       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
 956         UseXMMForArrayCopy = true;
 957       }
 958       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
 959         UseUnalignedLoadStores = true;
 960       }
 961     }
 962 
 963 #ifdef COMPILER2
 964     if (MaxVectorSize > 16) {
 965       // Limit vectors size to 16 bytes on current AMD cpus.
 966       FLAG_SET_DEFAULT(MaxVectorSize, 16);
 967     }
 968 #endif // COMPILER2
 969   }
 970 
 971   if( is_intel() ) { // Intel cpus specific settings
 972     if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
 973       UseStoreImmI16 = false; // don't use it on Intel cpus
 974     }
 975     if( cpu_family() == 6 || cpu_family() == 15 ) {
 976       if( FLAG_IS_DEFAULT(UseAddressNop) ) {
 977         // Use it on all Intel cpus starting from PentiumPro
 978         UseAddressNop = true;
 979       }
 980     }
 981     if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
 982       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
 983     }
 984     if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
 985       if( supports_sse3() ) {
 986         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
 987       } else {
 988         UseXmmRegToRegMoveAll = false;
 989       }
 990     }
 991     if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
 992 #ifdef COMPILER2
 993       if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
 994         // For new Intel cpus do the next optimization:
 995         // don't align the beginning of a loop if there are enough instructions
 996         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
 997         // in current fetch line (OptoLoopAlignment) or the padding
 998         // is big (> MaxLoopPad).
 999         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1000         // generated NOP instructions. 11 is the largest size of one
1001         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1002         MaxLoopPad = 11;
1003       }
1004 #endif // COMPILER2
1005       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1006         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1007       }
1008       if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus
1009         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1010           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1011         }
1012       }
1013       if (supports_sse4_2() && UseSSE >= 4) {
1014         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1015           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1016         }
1017       } else {
1018         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1019           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1020         }
1021         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1022       }
1023     }
1024     if ((cpu_family() == 0x06) &&
1025         ((extended_cpu_model() == 0x36) || // Centerton
1026          (extended_cpu_model() == 0x37) || // Silvermont
1027          (extended_cpu_model() == 0x4D))) {
1028 #ifdef COMPILER2
1029       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1030         OptoScheduling = true;
1031       }
1032 #endif
1033       if (supports_sse4_2()) { // Silvermont
1034         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1035           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1036         }
1037       }
1038     }
1039     if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1040       AllocatePrefetchInstr = 3;
1041     }
1042   }
1043 
1044   // Use count leading zeros count instruction if available.
1045   if (supports_lzcnt()) {
1046     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1047       UseCountLeadingZerosInstruction = true;
1048     }
1049    } else if (UseCountLeadingZerosInstruction) {
1050     warning("lzcnt instruction is not available on this CPU");
1051     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1052   }
1053 
1054   // Use count trailing zeros instruction if available
1055   if (supports_bmi1()) {
1056     // tzcnt does not require VEX prefix
1057     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1058       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1059         // Don't use tzcnt if BMI1 is switched off on command line.
1060         UseCountTrailingZerosInstruction = false;
1061       } else {
1062         UseCountTrailingZerosInstruction = true;
1063       }
1064     }
1065   } else if (UseCountTrailingZerosInstruction) {
1066     warning("tzcnt instruction is not available on this CPU");
1067     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1068   }
1069 
1070   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1071   // VEX prefix is generated only when AVX > 0.
1072   if (supports_bmi1() && supports_avx()) {
1073     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1074       UseBMI1Instructions = true;
1075     }
1076   } else if (UseBMI1Instructions) {
1077     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1078     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1079   }
1080 
1081   if (supports_bmi2() && supports_avx()) {
1082     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1083       UseBMI2Instructions = true;
1084     }
1085   } else if (UseBMI2Instructions) {
1086     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1087     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1088   }
1089 
1090   // Use population count instruction if available.
1091   if (supports_popcnt()) {
1092     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1093       UsePopCountInstruction = true;
1094     }
1095   } else if (UsePopCountInstruction) {
1096     warning("POPCNT instruction is not available on this CPU");
1097     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1098   }
1099 
1100   // Use fast-string operations if available.
1101   if (supports_erms()) {
1102     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1103       UseFastStosb = true;
1104     }
1105   } else if (UseFastStosb) {
1106     warning("fast-string operations are not available on this CPU");
1107     FLAG_SET_DEFAULT(UseFastStosb, false);
1108   }
1109 
1110 #ifdef COMPILER2
1111   if (FLAG_IS_DEFAULT(AlignVector)) {
1112     // Modern processors allow misaligned memory operations for vectors.
1113     AlignVector = !UseUnalignedLoadStores;
1114   }
1115 #endif // COMPILER2
1116 
1117   if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
1118   if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
1119 
1120   // Allocation prefetch settings
1121   intx cache_line_size = prefetch_data_size();
1122   if( cache_line_size > AllocatePrefetchStepSize )
1123     AllocatePrefetchStepSize = cache_line_size;
1124 
1125   assert(AllocatePrefetchLines > 0, "invalid value");
1126   if( AllocatePrefetchLines < 1 )     // set valid value in product VM
1127     AllocatePrefetchLines = 3;
1128   assert(AllocateInstancePrefetchLines > 0, "invalid value");
1129   if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
1130     AllocateInstancePrefetchLines = 1;
1131 
1132   AllocatePrefetchDistance = allocate_prefetch_distance();
1133   AllocatePrefetchStyle    = allocate_prefetch_style();
1134 
1135   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1136     if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core
1137 #ifdef _LP64
1138       AllocatePrefetchDistance = 384;
1139 #else
1140       AllocatePrefetchDistance = 320;
1141 #endif
1142     }
1143     if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1144       AllocatePrefetchDistance = 192;
1145       AllocatePrefetchLines = 4;
1146     }
1147 #ifdef COMPILER2
1148     if (supports_sse4_2()) {
1149       if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1150         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1151       }
1152     }
1153 #endif
1154   }
1155 
1156 #ifdef _LP64
1157   // Prefetch settings
1158   PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
1159   PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
1160   PrefetchFieldsAhead         = prefetch_fields_ahead();
1161 #endif
1162 
1163   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1164      (cache_line_size > ContendedPaddingWidth))
1165      ContendedPaddingWidth = cache_line_size;
1166 
1167   // This machine allows unaligned memory accesses
1168   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1169     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1170   }
1171 
1172 #ifndef PRODUCT
1173   if (PrintMiscellaneous && Verbose) {
1174     tty->print_cr("Logical CPUs per core: %u",
1175                   logical_processors_per_package());
1176     tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1177     tty->print("UseSSE=%d", (int) UseSSE);
1178     if (UseAVX > 0) {
1179       tty->print("  UseAVX=%d", (int) UseAVX);
1180     }
1181     if (UseAES) {
1182       tty->print("  UseAES=1");
1183     }
1184 #ifdef COMPILER2
1185     if (MaxVectorSize > 0) {
1186       tty->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1187     }
1188 #endif
1189     tty->cr();
1190     tty->print("Allocation");
1191     if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
1192       tty->print_cr(": no prefetching");
1193     } else {
1194       tty->print(" prefetching: ");
1195       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1196         tty->print("PREFETCHW");
1197       } else if (UseSSE >= 1) {
1198         if (AllocatePrefetchInstr == 0) {
1199           tty->print("PREFETCHNTA");
1200         } else if (AllocatePrefetchInstr == 1) {
1201           tty->print("PREFETCHT0");
1202         } else if (AllocatePrefetchInstr == 2) {
1203           tty->print("PREFETCHT2");
1204         } else if (AllocatePrefetchInstr == 3) {
1205           tty->print("PREFETCHW");
1206         }
1207       }
1208       if (AllocatePrefetchLines > 1) {
1209         tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1210       } else {
1211         tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1212       }
1213     }
1214 
1215     if (PrefetchCopyIntervalInBytes > 0) {
1216       tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1217     }
1218     if (PrefetchScanIntervalInBytes > 0) {
1219       tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1220     }
1221     if (PrefetchFieldsAhead > 0) {
1222       tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1223     }
1224     if (ContendedPaddingWidth > 0) {
1225       tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1226     }
1227   }
1228 #endif // !PRODUCT
1229 }
1230 
1231 bool VM_Version::use_biased_locking() {
1232 #if INCLUDE_RTM_OPT
1233   // RTM locking is most useful when there is high lock contention and
1234   // low data contention.  With high lock contention the lock is usually
1235   // inflated and biased locking is not suitable for that case.
1236   // RTM locking code requires that biased locking is off.
1237   // Note: we can't switch off UseBiasedLocking in get_processor_features()
1238   // because it is used by Thread::allocate() which is called before
1239   // VM_Version::initialize().
1240   if (UseRTMLocking && UseBiasedLocking) {
1241     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
1242       FLAG_SET_DEFAULT(UseBiasedLocking, false);
1243     } else {
1244       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
1245       UseBiasedLocking = false;
1246     }
1247   }
1248 #endif
1249   return UseBiasedLocking;
1250 }
1251 
1252 void VM_Version::initialize() {
1253   ResourceMark rm;
1254   // Making this stub must be FIRST use of assembler
1255 
1256   stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size);
1257   if (stub_blob == NULL) {
1258     vm_exit_during_initialization("Unable to allocate get_cpu_info_stub");
1259   }
1260   CodeBuffer c(stub_blob);
1261   VM_Version_StubGenerator g(&c);
1262   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1263                                      g.generate_get_cpu_info());
1264 
1265   get_processor_features();
1266 }