1 /* 2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "memory/resourceArea.hpp" 28 #include "runtime/java.hpp" 29 #include "runtime/os.hpp" 30 #include "runtime/stubCodeGenerator.hpp" 31 #include "vm_version_sparc.hpp" 32 33 unsigned int VM_Version::_L2_data_cache_line_size = 0; 34 35 void VM_Version::initialize() { 36 assert(_features != 0, "System pre-initialization is not complete."); 37 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 38 39 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 40 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 41 PrefetchFieldsAhead = prefetch_fields_ahead(); 42 43 // Allocation prefetch settings 44 intx cache_line_size = prefetch_data_size(); 45 if( cache_line_size > AllocatePrefetchStepSize ) 46 AllocatePrefetchStepSize = cache_line_size; 47 48 assert(AllocatePrefetchLines > 0, "invalid value"); 49 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 50 AllocatePrefetchLines = 3; 51 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 52 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 53 AllocateInstancePrefetchLines = 1; 54 55 AllocatePrefetchDistance = allocate_prefetch_distance(); 56 AllocatePrefetchStyle = allocate_prefetch_style(); 57 58 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 59 warning("BIS instructions are not available on this CPU"); 60 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 61 } 62 63 UseSSE = 0; // Only on x86 and x64 64 65 _supports_cx8 = has_v9(); 66 _supports_atomic_getset4 = true; // swap instruction 67 68 if (is_niagara()) { 69 // Indirect branch is the same cost as direct 70 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 71 FLAG_SET_DEFAULT(UseInlineCaches, false); 72 } 73 // Align loops on a single instruction boundary. 74 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 75 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); 76 } 77 #ifdef _LP64 78 // 32-bit oops don't make sense for the 64-bit VM on sparc 79 // since the 32-bit VM has the same registers and smaller objects. 80 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); 81 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); 82 #endif // _LP64 83 #ifdef COMPILER2 84 // Indirect branch is the same cost as direct 85 if (FLAG_IS_DEFAULT(UseJumpTables)) { 86 FLAG_SET_DEFAULT(UseJumpTables, true); 87 } 88 // Single-issue, so entry and loop tops are 89 // aligned on a single instruction boundary 90 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 91 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 92 } 93 if (is_niagara_plus()) { 94 if (has_blk_init() && UseTLAB && 95 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 96 // Use BIS instruction for TLAB allocation prefetch. 97 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); 98 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 99 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); 100 } 101 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 102 // Use smaller prefetch distance with BIS 103 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 104 } 105 } 106 if (is_T4()) { 107 // Double number of prefetched cache lines on T4 108 // since L2 cache line size is smaller (32 bytes). 109 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 110 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); 111 } 112 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 113 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); 114 } 115 } 116 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 117 // Use different prefetch distance without BIS 118 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 119 } 120 if (AllocatePrefetchInstr == 1) { 121 // Need a space at the end of TLAB for BIS since it 122 // will fault when accessing memory outside of heap. 123 124 // +1 for rounding up to next cache line, +1 to be safe 125 int lines = AllocatePrefetchLines + 2; 126 int step_size = AllocatePrefetchStepSize; 127 int distance = AllocatePrefetchDistance; 128 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; 129 } 130 } 131 #endif 132 } 133 134 // Use hardware population count instruction if available. 135 if (has_hardware_popc()) { 136 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 137 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 138 } 139 } else if (UsePopCountInstruction) { 140 warning("POPC instruction is not available on this CPU"); 141 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 142 } 143 144 // T4 and newer Sparc cpus have new compare and branch instruction. 145 if (has_cbcond()) { 146 if (FLAG_IS_DEFAULT(UseCBCond)) { 147 FLAG_SET_DEFAULT(UseCBCond, true); 148 } 149 } else if (UseCBCond) { 150 warning("CBCOND instruction is not available on this CPU"); 151 FLAG_SET_DEFAULT(UseCBCond, false); 152 } 153 154 assert(BlockZeroingLowLimit > 0, "invalid value"); 155 if (has_block_zeroing() && cache_line_size > 0) { 156 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 157 FLAG_SET_DEFAULT(UseBlockZeroing, true); 158 } 159 } else if (UseBlockZeroing) { 160 warning("BIS zeroing instructions are not available on this CPU"); 161 FLAG_SET_DEFAULT(UseBlockZeroing, false); 162 } 163 164 assert(BlockCopyLowLimit > 0, "invalid value"); 165 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache 166 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 167 FLAG_SET_DEFAULT(UseBlockCopy, true); 168 } 169 } else if (UseBlockCopy) { 170 warning("BIS instructions are not available or expensive on this CPU"); 171 FLAG_SET_DEFAULT(UseBlockCopy, false); 172 } 173 174 #ifdef COMPILER2 175 // T4 and newer Sparc cpus have fast RDPC. 176 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 177 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 178 } 179 180 // Currently not supported anywhere. 181 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 182 183 MaxVectorSize = 8; 184 185 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 186 #endif 187 188 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 189 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 190 191 char buf[512]; 192 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 193 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 194 (has_hardware_popc() ? ", popc" : ""), 195 (has_vis1() ? ", vis1" : ""), 196 (has_vis2() ? ", vis2" : ""), 197 (has_vis3() ? ", vis3" : ""), 198 (has_blk_init() ? ", blk_init" : ""), 199 (has_cbcond() ? ", cbcond" : ""), 200 (has_aes() ? ", aes" : ""), 201 (has_sha1() ? ", sha1" : ""), 202 (has_sha256() ? ", sha256" : ""), 203 (has_sha512() ? ", sha512" : ""), 204 (has_crc32c() ? ", crc32c" : ""), 205 (is_ultra3() ? ", ultra3" : ""), 206 (is_sun4v() ? ", sun4v" : ""), 207 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 208 (is_sparc64() ? ", sparc64" : ""), 209 (!has_hardware_mul32() ? ", no-mul32" : ""), 210 (!has_hardware_div32() ? ", no-div32" : ""), 211 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); 212 213 // buf is started with ", " or is empty 214 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf); 215 216 // UseVIS is set to the smallest of what hardware supports and what 217 // the command line requires. I.e., you cannot set UseVIS to 3 on 218 // older UltraSparc which do not support it. 219 if (UseVIS > 3) UseVIS=3; 220 if (UseVIS < 0) UseVIS=0; 221 if (!has_vis3()) // Drop to 2 if no VIS3 support 222 UseVIS = MIN2((intx)2,UseVIS); 223 if (!has_vis2()) // Drop to 1 if no VIS2 support 224 UseVIS = MIN2((intx)1,UseVIS); 225 if (!has_vis1()) // Drop to 0 if no VIS1 support 226 UseVIS = 0; 227 228 // SPARC T4 and above should have support for AES instructions 229 if (has_aes()) { 230 if (FLAG_IS_DEFAULT(UseAES)) { 231 FLAG_SET_DEFAULT(UseAES, true); 232 } 233 if (!UseAES) { 234 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 235 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 236 } 237 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 238 } else { 239 // The AES intrinsic stubs require AES instruction support (of course) 240 // but also require VIS3 mode or higher for instructions it use. 241 if (UseVIS > 2) { 242 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 243 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 244 } 245 } else { 246 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 247 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); 248 } 249 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 250 } 251 } 252 } else if (UseAES || UseAESIntrinsics) { 253 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 254 warning("AES instructions are not available on this CPU"); 255 FLAG_SET_DEFAULT(UseAES, false); 256 } 257 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 258 warning("AES intrinsics are not available on this CPU"); 259 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 260 } 261 } 262 263 if (UseAESCTRIntrinsics) { 264 warning("AES/CTR intrinsics are not available on this CPU"); 265 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 266 } 267 268 // GHASH/GCM intrinsics 269 if (has_vis3() && (UseVIS > 2)) { 270 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 271 UseGHASHIntrinsics = true; 272 } 273 } else if (UseGHASHIntrinsics) { 274 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 275 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); 276 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 277 } 278 279 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times 280 if (has_sha1() || has_sha256() || has_sha512()) { 281 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 282 if (FLAG_IS_DEFAULT(UseSHA)) { 283 FLAG_SET_DEFAULT(UseSHA, true); 284 } 285 } else { 286 if (UseSHA) { 287 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 288 FLAG_SET_DEFAULT(UseSHA, false); 289 } 290 } 291 } else if (UseSHA) { 292 warning("SHA instructions are not available on this CPU"); 293 FLAG_SET_DEFAULT(UseSHA, false); 294 } 295 296 if (UseSHA && has_sha1()) { 297 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 298 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 299 } 300 } else if (UseSHA1Intrinsics) { 301 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 302 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 303 } 304 305 if (UseSHA && has_sha256()) { 306 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 307 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 308 } 309 } else if (UseSHA256Intrinsics) { 310 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 311 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 312 } 313 314 if (UseSHA && has_sha512()) { 315 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 316 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 317 } 318 } else if (UseSHA512Intrinsics) { 319 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 320 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 321 } 322 323 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 324 FLAG_SET_DEFAULT(UseSHA, false); 325 } 326 327 // SPARC T4 and above should have support for CRC32C instruction 328 if (has_crc32c()) { 329 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions 330 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 331 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 332 } 333 } else { 334 if (UseCRC32CIntrinsics) { 335 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 336 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 337 } 338 } 339 } else if (UseCRC32CIntrinsics) { 340 warning("CRC32C instruction is not available on this CPU"); 341 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 342 } 343 344 if (UseVIS > 2) { 345 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 346 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 347 } 348 } else if (UseAdler32Intrinsics) { 349 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 350 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 351 } 352 353 if (UseVIS > 2) { 354 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 355 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 356 } 357 } else if (UseCRC32Intrinsics) { 358 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled"); 359 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 360 } 361 362 if (UseVectorizedMismatchIntrinsic) { 363 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 364 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 365 } 366 367 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 368 (cache_line_size > ContendedPaddingWidth)) 369 ContendedPaddingWidth = cache_line_size; 370 371 // This machine does not allow unaligned memory accesses 372 if (UseUnalignedAccesses) { 373 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) 374 warning("Unaligned memory access is not available on this CPU"); 375 FLAG_SET_DEFAULT(UseUnalignedAccesses, false); 376 } 377 378 if (PrintMiscellaneous && Verbose) { 379 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 380 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 381 tty->print("Allocation"); 382 if (AllocatePrefetchStyle <= 0) { 383 tty->print_cr(": no prefetching"); 384 } else { 385 tty->print(" prefetching: "); 386 if (AllocatePrefetchInstr == 0) { 387 tty->print("PREFETCH"); 388 } else if (AllocatePrefetchInstr == 1) { 389 tty->print("BIS"); 390 } 391 if (AllocatePrefetchLines > 1) { 392 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 393 } else { 394 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 395 } 396 } 397 if (PrefetchCopyIntervalInBytes > 0) { 398 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 399 } 400 if (PrefetchScanIntervalInBytes > 0) { 401 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 402 } 403 if (PrefetchFieldsAhead > 0) { 404 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 405 } 406 if (ContendedPaddingWidth > 0) { 407 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 408 } 409 } 410 } 411 412 void VM_Version::print_features() { 413 tty->print_cr("Version:%s", _features); 414 } 415 416 int VM_Version::determine_features() { 417 if (UseV8InstrsOnly) { 418 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-V8"); } 419 return generic_v8_m; 420 } 421 422 int features = platform_features(unknown_m); // platform_features() is os_arch specific 423 424 if (features == unknown_m) { 425 features = generic_v9_m; 426 warning("Cannot recognize SPARC version. Default to V9"); 427 } 428 429 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); 430 if (UseNiagaraInstrs) { // Force code generation for Niagara 431 if (is_T_family(features)) { 432 // Happy to accomodate... 433 } else { 434 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Niagara"); } 435 features |= T_family_m; 436 } 437 } else { 438 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { 439 if (PrintMiscellaneous && Verbose) { tty->print_cr("Version is Forced-Not-Niagara"); } 440 features &= ~(T_family_m | T1_model_m); 441 } else { 442 // Happy to accomodate... 443 } 444 } 445 446 return features; 447 } 448 449 static uint64_t saved_features = 0; 450 451 void VM_Version::allow_all() { 452 saved_features = _features; 453 _features = all_features_m; 454 } 455 456 void VM_Version::revert() { 457 _features = saved_features; 458 } 459 460 unsigned int VM_Version::calc_parallel_worker_threads() { 461 unsigned int result; 462 if (is_M_series()) { 463 // for now, use same gc thread calculation for M-series as for niagara-plus 464 // in future, we may want to tweak parameters for nof_parallel_worker_thread 465 result = nof_parallel_worker_threads(5, 16, 8); 466 } else if (is_niagara_plus()) { 467 result = nof_parallel_worker_threads(5, 16, 8); 468 } else { 469 result = nof_parallel_worker_threads(5, 8, 8); 470 } 471 return result; 472 }