28 #include "runtime/java.hpp" 29 #include "runtime/os.hpp" 30 #include "runtime/stubCodeGenerator.hpp" 31 #include "vm_version_sparc.hpp" 32 33 unsigned int VM_Version::_L2_data_cache_line_size = 0; 34 35 void VM_Version::initialize() { 36 assert(_features != 0, "System pre-initialization is not complete."); 37 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 38 39 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 40 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 41 PrefetchFieldsAhead = prefetch_fields_ahead(); 42 43 // Allocation prefetch settings 44 intx cache_line_size = prefetch_data_size(); 45 if( cache_line_size > AllocatePrefetchStepSize ) 46 AllocatePrefetchStepSize = cache_line_size; 47 48 assert(AllocatePrefetchLines > 0, "invalid value"); 49 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 50 AllocatePrefetchLines = 3; 51 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 52 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 53 AllocateInstancePrefetchLines = 1; 54 55 AllocatePrefetchDistance = allocate_prefetch_distance(); 56 AllocatePrefetchStyle = allocate_prefetch_style(); 57 58 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 59 warning("BIS instructions are not available on this CPU"); 60 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 61 } 62 63 UseSSE = 0; // Only on x86 and x64 64 65 _supports_cx8 = has_v9(); 66 _supports_atomic_getset4 = true; // swap instruction 67 68 if (is_niagara()) { 69 // Indirect branch is the same cost as direct 70 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 71 FLAG_SET_DEFAULT(UseInlineCaches, false); 72 } 73 // Align loops on a single instruction boundary. 74 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { | 28 #include "runtime/java.hpp" 29 #include "runtime/os.hpp" 30 #include "runtime/stubCodeGenerator.hpp" 31 #include "vm_version_sparc.hpp" 32 33 unsigned int VM_Version::_L2_data_cache_line_size = 0; 34 35 void VM_Version::initialize() { 36 assert(_features != 0, "System pre-initialization is not complete."); 37 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 38 39 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 40 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 41 PrefetchFieldsAhead = prefetch_fields_ahead(); 42 43 // Allocation prefetch settings 44 intx cache_line_size = prefetch_data_size(); 45 if( cache_line_size > AllocatePrefetchStepSize ) 46 AllocatePrefetchStepSize = cache_line_size; 47 48 AllocatePrefetchDistance = allocate_prefetch_distance(); 49 AllocatePrefetchStyle = allocate_prefetch_style(); 50 51 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 52 warning("BIS instructions are not available on this CPU"); 53 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 54 } 55 56 UseSSE = 0; // Only on x86 and x64 57 58 _supports_cx8 = has_v9(); 59 _supports_atomic_getset4 = true; // swap instruction 60 61 if (is_niagara()) { 62 // Indirect branch is the same cost as direct 63 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 64 FLAG_SET_DEFAULT(UseInlineCaches, false); 65 } 66 // Align loops on a single instruction boundary. 67 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { |