1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "logging/log.hpp"
28 #include "memory/resourceArea.hpp"
29 #include "runtime/java.hpp"
30 #include "runtime/os.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_sparc.hpp"
33
34 unsigned int VM_Version::_L2_data_cache_line_size = 0;
35
36 void VM_Version::initialize() {
37 assert(_features != 0, "System pre-initialization is not complete.");
38 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
39
40 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
41 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
42 PrefetchFieldsAhead = prefetch_fields_ahead();
43
44 // Allocation prefetch settings
45 intx cache_line_size = prefetch_data_size();
46 if( cache_line_size > AllocatePrefetchStepSize )
47 AllocatePrefetchStepSize = cache_line_size;
48
49 AllocatePrefetchDistance = allocate_prefetch_distance();
50 AllocatePrefetchStyle = allocate_prefetch_style();
51
52 if (AllocatePrefetchStyle == 3 && !has_blk_init()) {
53 warning("BIS instructions are not available on this CPU");
54 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
55 }
56
57 UseSSE = 0; // Only on x86 and x64
58
59 _supports_cx8 = has_v9();
60 _supports_atomic_getset4 = true; // swap instruction
61
62 if (is_niagara()) {
63 // Indirect branch is the same cost as direct
64 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
65 FLAG_SET_DEFAULT(UseInlineCaches, false);
66 }
67 // Align loops on a single instruction boundary.
68 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
69 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
70 }
71 #ifdef _LP64
72 // 32-bit oops don't make sense for the 64-bit VM on sparc
73 // since the 32-bit VM has the same registers and smaller objects.
74 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
75 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
76 #endif // _LP64
77 #ifdef COMPILER2
78 // Indirect branch is the same cost as direct
79 if (FLAG_IS_DEFAULT(UseJumpTables)) {
80 FLAG_SET_DEFAULT(UseJumpTables, true);
81 }
82 // Single-issue, so entry and loop tops are
83 // aligned on a single instruction boundary
84 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
85 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
86 }
87 if (is_niagara_plus()) {
88 if (has_blk_init() && UseTLAB &&
89 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
90 // Use BIS instruction for TLAB allocation prefetch.
91 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
92 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
93 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
94 }
95 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
96 // Use smaller prefetch distance with BIS
97 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
98 }
99 }
100 if (is_T4()) {
101 // Double number of prefetched cache lines on T4
102 // since L2 cache line size is smaller (32 bytes).
103 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
104 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
105 }
106 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
107 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
108 }
109 }
110 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
111 // Use different prefetch distance without BIS
112 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
113 }
114 if (AllocatePrefetchInstr == 1) {
115 // Need a space at the end of TLAB for BIS since it
116 // will fault when accessing memory outside of heap.
117
118 // +1 for rounding up to next cache line, +1 to be safe
119 int lines = AllocatePrefetchLines + 2;
120 int step_size = AllocatePrefetchStepSize;
121 int distance = AllocatePrefetchDistance;
122 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
123 }
124 }
125 #endif
126 }
127
128 // Use hardware population count instruction if available.
129 if (has_hardware_popc()) {
130 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
131 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
132 }
133 } else if (UsePopCountInstruction) {
134 warning("POPC instruction is not available on this CPU");
135 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
136 }
137
138 // T4 and newer Sparc cpus have new compare and branch instruction.
139 if (has_cbcond()) {
140 if (FLAG_IS_DEFAULT(UseCBCond)) {
141 FLAG_SET_DEFAULT(UseCBCond, true);
142 }
143 } else if (UseCBCond) {
144 warning("CBCOND instruction is not available on this CPU");
145 FLAG_SET_DEFAULT(UseCBCond, false);
146 }
147
148 assert(BlockZeroingLowLimit > 0, "invalid value");
149 if (has_block_zeroing() && cache_line_size > 0) {
150 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
151 FLAG_SET_DEFAULT(UseBlockZeroing, true);
152 }
153 } else if (UseBlockZeroing) {
154 warning("BIS zeroing instructions are not available on this CPU");
155 FLAG_SET_DEFAULT(UseBlockZeroing, false);
156 }
157
158 assert(BlockCopyLowLimit > 0, "invalid value");
159 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
160 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
161 FLAG_SET_DEFAULT(UseBlockCopy, true);
162 }
163 } else if (UseBlockCopy) {
164 warning("BIS instructions are not available or expensive on this CPU");
165 FLAG_SET_DEFAULT(UseBlockCopy, false);
166 }
167
168 #ifdef COMPILER2
169 // T4 and newer Sparc cpus have fast RDPC.
170 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
171 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
172 }
173
174 // Currently not supported anywhere.
175 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
176
177 MaxVectorSize = 8;
178
179 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
180 #endif
181
182 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
183 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
184
185 char buf[512];
186 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
187 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
188 (has_hardware_popc() ? ", popc" : ""),
189 (has_vis1() ? ", vis1" : ""),
190 (has_vis2() ? ", vis2" : ""),
191 (has_vis3() ? ", vis3" : ""),
192 (has_blk_init() ? ", blk_init" : ""),
193 (has_cbcond() ? ", cbcond" : ""),
194 (has_aes() ? ", aes" : ""),
195 (has_sha1() ? ", sha1" : ""),
196 (has_sha256() ? ", sha256" : ""),
197 (has_sha512() ? ", sha512" : ""),
198 (has_crc32c() ? ", crc32c" : ""),
199 (is_ultra3() ? ", ultra3" : ""),
200 (is_sun4v() ? ", sun4v" : ""),
201 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
202 (is_sparc64() ? ", sparc64" : ""),
203 (!has_hardware_mul32() ? ", no-mul32" : ""),
204 (!has_hardware_div32() ? ", no-div32" : ""),
205 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
206
207 // buf is started with ", " or is empty
208 _features_string = os::strdup(strlen(buf) > 2 ? buf + 2 : buf);
209
210 // UseVIS is set to the smallest of what hardware supports and what
211 // the command line requires. I.e., you cannot set UseVIS to 3 on
212 // older UltraSparc which do not support it.
213 if (UseVIS > 3) UseVIS=3;
214 if (UseVIS < 0) UseVIS=0;
215 if (!has_vis3()) // Drop to 2 if no VIS3 support
216 UseVIS = MIN2((intx)2,UseVIS);
217 if (!has_vis2()) // Drop to 1 if no VIS2 support
218 UseVIS = MIN2((intx)1,UseVIS);
219 if (!has_vis1()) // Drop to 0 if no VIS1 support
220 UseVIS = 0;
221
222 // SPARC T4 and above should have support for AES instructions
223 if (has_aes()) {
224 if (FLAG_IS_DEFAULT(UseAES)) {
225 FLAG_SET_DEFAULT(UseAES, true);
226 }
227 if (!UseAES) {
228 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
229 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
230 }
231 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
232 } else {
233 // The AES intrinsic stubs require AES instruction support (of course)
234 // but also require VIS3 mode or higher for instructions it use.
235 if (UseVIS > 2) {
236 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
237 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
238 }
239 } else {
240 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
241 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
242 }
243 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
244 }
245 }
246 } else if (UseAES || UseAESIntrinsics) {
247 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
248 warning("AES instructions are not available on this CPU");
249 FLAG_SET_DEFAULT(UseAES, false);
250 }
251 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
252 warning("AES intrinsics are not available on this CPU");
253 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
254 }
255 }
256
257 if (UseAESCTRIntrinsics) {
258 warning("AES/CTR intrinsics are not available on this CPU");
259 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
260 }
261
262 // GHASH/GCM intrinsics
263 if (has_vis3() && (UseVIS > 2)) {
264 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
265 UseGHASHIntrinsics = true;
266 }
267 } else if (UseGHASHIntrinsics) {
268 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
269 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled");
270 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
271 }
272
273 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
274 if (has_sha1() || has_sha256() || has_sha512()) {
275 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
276 if (FLAG_IS_DEFAULT(UseSHA)) {
277 FLAG_SET_DEFAULT(UseSHA, true);
278 }
279 } else {
280 if (UseSHA) {
281 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
282 FLAG_SET_DEFAULT(UseSHA, false);
283 }
284 }
285 } else if (UseSHA) {
286 warning("SHA instructions are not available on this CPU");
287 FLAG_SET_DEFAULT(UseSHA, false);
288 }
289
290 if (UseSHA && has_sha1()) {
291 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
292 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
293 }
294 } else if (UseSHA1Intrinsics) {
295 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
296 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
297 }
298
299 if (UseSHA && has_sha256()) {
300 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
301 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
302 }
303 } else if (UseSHA256Intrinsics) {
304 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
305 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
306 }
307
308 if (UseSHA && has_sha512()) {
309 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
310 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
311 }
312 } else if (UseSHA512Intrinsics) {
313 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
314 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
315 }
316
317 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
318 FLAG_SET_DEFAULT(UseSHA, false);
319 }
320
321 // SPARC T4 and above should have support for CRC32C instruction
322 if (has_crc32c()) {
323 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions
324 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
325 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
326 }
327 } else {
328 if (UseCRC32CIntrinsics) {
329 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
330 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
331 }
332 }
333 } else if (UseCRC32CIntrinsics) {
334 warning("CRC32C instruction is not available on this CPU");
335 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
336 }
337
338 if (UseVIS > 2) {
339 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
340 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
341 }
342 } else if (UseAdler32Intrinsics) {
343 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
344 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
345 }
346
347 if (UseVIS > 2) {
348 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
349 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
350 }
351 } else if (UseCRC32Intrinsics) {
352 warning("SPARC CRC32 intrinsics require VIS3 insructions support. Intriniscs will be disabled");
353 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
354 }
355
356 if (UseVectorizedMismatchIntrinsic) {
357 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
358 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
359 }
360
361 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
362 (cache_line_size > ContendedPaddingWidth))
363 ContendedPaddingWidth = cache_line_size;
364
365 // This machine does not allow unaligned memory accesses
366 if (UseUnalignedAccesses) {
367 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
368 warning("Unaligned memory access is not available on this CPU");
369 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
370 }
371
372 if (log_is_enabled(Info, os, cpu)) {
373 ResourceMark rm;
374 outputStream* log = Log(os, cpu)::info_stream();
375 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
376 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
377 log->print("Allocation");
378 if (AllocatePrefetchStyle <= 0) {
379 log->print(": no prefetching");
380 } else {
381 log->print(" prefetching: ");
382 if (AllocatePrefetchInstr == 0) {
383 log->print("PREFETCH");
384 } else if (AllocatePrefetchInstr == 1) {
385 log->print("BIS");
386 }
387 if (AllocatePrefetchLines > 1) {
388 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
389 } else {
390 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
391 }
392 }
393 if (PrefetchCopyIntervalInBytes > 0) {
394 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
395 }
396 if (PrefetchScanIntervalInBytes > 0) {
397 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
398 }
399 if (PrefetchFieldsAhead > 0) {
400 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
401 }
402 if (ContendedPaddingWidth > 0) {
403 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
404 }
405 }
406 }
407
408 void VM_Version::print_features() {
409 tty->print_cr("Version:%s", _features);
410 }
411
412 int VM_Version::determine_features() {
413 if (UseV8InstrsOnly) {
414 log_info(os, cpu)("Version is Forced-V8");
415 return generic_v8_m;
416 }
417
418 int features = platform_features(unknown_m); // platform_features() is os_arch specific
419
420 if (features == unknown_m) {
421 features = generic_v9_m;
422 log_info(os)("Cannot recognize SPARC version. Default to V9");
423 }
424
425 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
426 if (UseNiagaraInstrs) { // Force code generation for Niagara
427 if (is_T_family(features)) {
428 // Happy to accomodate...
429 } else {
430 log_info(os, cpu)("Version is Forced-Niagara");
431 features |= T_family_m;
432 }
433 } else {
434 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
435 log_info(os, cpu)("Version is Forced-Not-Niagara");
436 features &= ~(T_family_m | T1_model_m);
437 } else {
438 // Happy to accomodate...
439 }
440 }
441
442 return features;
443 }
444
445 static uint64_t saved_features = 0;
446
447 void VM_Version::allow_all() {
448 saved_features = _features;
449 _features = all_features_m;
450 }
451
452 void VM_Version::revert() {
453 _features = saved_features;
454 }
455
456 unsigned int VM_Version::calc_parallel_worker_threads() {
457 unsigned int result;
458 if (is_M_series()) {
459 // for now, use same gc thread calculation for M-series as for niagara-plus
460 // in future, we may want to tweak parameters for nof_parallel_worker_thread
461 result = nof_parallel_worker_threads(5, 16, 8);
462 } else if (is_niagara_plus()) {
463 result = nof_parallel_worker_threads(5, 16, 8);
464 } else {
465 result = nof_parallel_worker_threads(5, 8, 8);
466 }
467 return result;
468 }
469
470
471 int VM_Version::parse_features(const char* implementation) {
472 int features = unknown_m;
473 // Convert to UPPER case before compare.
474 char* impl = os::strdup_check_oom(implementation);
475
476 for (int i = 0; impl[i] != 0; i++)
477 impl[i] = (char)toupper((uint)impl[i]);
478
479 if (strstr(impl, "SPARC64") != NULL) {
480 features |= sparc64_family_m;
481 } else if (strstr(impl, "SPARC-M") != NULL) {
482 // M-series SPARC is based on T-series.
483 features |= (M_family_m | T_family_m);
484 } else if (strstr(impl, "SPARC-T") != NULL) {
485 features |= T_family_m;
486 if (strstr(impl, "SPARC-T1") != NULL) {
487 features |= T1_model_m;
488 }
489 } else {
490 if (strstr(impl, "SPARC") == NULL) {
491 #ifndef PRODUCT
492 // kstat on Solaris 8 virtual machines (branded zones)
493 // returns "(unsupported)" implementation. Solaris 8 is not
494 // supported anymore, but include this check to be on the
495 // safe side.
496 warning("Can't parse CPU implementation = '%s', assume generic SPARC", impl);
497 #endif
498 }
499 }
500 os::free((void*)impl);
501 return features;
502 }