1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "assembler_x86.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_x86.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37 #ifdef TARGET_OS_FAMILY_windows
38 # include "os_windows.inline.hpp"
39 #endif
40 #ifdef TARGET_OS_FAMILY_bsd
41 # include "os_bsd.inline.hpp"
42 #endif
43
44
45 int VM_Version::_cpu;
46 int VM_Version::_model;
47 int VM_Version::_stepping;
48 int VM_Version::_cpuFeatures;
49 const char* VM_Version::_features_str = "";
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
51
52 static BufferBlob* stub_blob;
53 static const int stub_size = 550;
54
55 extern "C" {
56 typedef void (*getPsrInfo_stub_t)(void*);
57 }
58 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
59
60
61 class VM_Version_StubGenerator: public StubCodeGenerator {
62 public:
63
64 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
65
66 address generate_getPsrInfo() {
67 // Flags to test CPU type.
68 const uint32_t HS_EFL_AC = 0x40000;
69 const uint32_t HS_EFL_ID = 0x200000;
70 // Values for when we don't have a CPUID instruction.
71 const int CPU_FAMILY_SHIFT = 8;
72 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
73 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
74
75 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
76 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done;
77
78 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
79 # define __ _masm->
80
81 address start = __ pc();
82
83 //
84 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
85 //
86 // LP64: rcx and rdx are first and second argument registers on windows
87
88 __ push(rbp);
89 #ifdef _LP64
90 __ mov(rbp, c_rarg0); // cpuid_info address
91 #else
92 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
93 #endif
94 __ push(rbx);
95 __ push(rsi);
96 __ pushf(); // preserve rbx, and flags
97 __ pop(rax);
98 __ push(rax);
99 __ mov(rcx, rax);
100 //
101 // if we are unable to change the AC flag, we have a 386
102 //
103 __ xorl(rax, HS_EFL_AC);
104 __ push(rax);
105 __ popf();
106 __ pushf();
107 __ pop(rax);
108 __ cmpptr(rax, rcx);
109 __ jccb(Assembler::notEqual, detect_486);
110
111 __ movl(rax, CPU_FAMILY_386);
112 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
113 __ jmp(done);
114
115 //
116 // If we are unable to change the ID flag, we have a 486 which does
117 // not support the "cpuid" instruction.
118 //
119 __ bind(detect_486);
120 __ mov(rax, rcx);
121 __ xorl(rax, HS_EFL_ID);
122 __ push(rax);
123 __ popf();
124 __ pushf();
125 __ pop(rax);
126 __ cmpptr(rcx, rax);
127 __ jccb(Assembler::notEqual, detect_586);
128
129 __ bind(cpu486);
130 __ movl(rax, CPU_FAMILY_486);
131 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
132 __ jmp(done);
133
134 //
135 // At this point, we have a chip which supports the "cpuid" instruction
136 //
137 __ bind(detect_586);
138 __ xorl(rax, rax);
139 __ cpuid();
140 __ orl(rax, rax);
141 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
142 // value of at least 1, we give up and
143 // assume a 486
144 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
145 __ movl(Address(rsi, 0), rax);
146 __ movl(Address(rsi, 4), rbx);
147 __ movl(Address(rsi, 8), rcx);
148 __ movl(Address(rsi,12), rdx);
149
150 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
151 __ jccb(Assembler::belowEqual, std_cpuid4);
152
153 //
154 // cpuid(0xB) Processor Topology
155 //
156 __ movl(rax, 0xb);
157 __ xorl(rcx, rcx); // Threads level
158 __ cpuid();
159
160 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
161 __ movl(Address(rsi, 0), rax);
162 __ movl(Address(rsi, 4), rbx);
163 __ movl(Address(rsi, 8), rcx);
164 __ movl(Address(rsi,12), rdx);
165
166 __ movl(rax, 0xb);
167 __ movl(rcx, 1); // Cores level
168 __ cpuid();
169 __ push(rax);
170 __ andl(rax, 0x1f); // Determine if valid topology level
171 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
172 __ andl(rax, 0xffff);
173 __ pop(rax);
174 __ jccb(Assembler::equal, std_cpuid4);
175
176 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
177 __ movl(Address(rsi, 0), rax);
178 __ movl(Address(rsi, 4), rbx);
179 __ movl(Address(rsi, 8), rcx);
180 __ movl(Address(rsi,12), rdx);
181
182 __ movl(rax, 0xb);
183 __ movl(rcx, 2); // Packages level
184 __ cpuid();
185 __ push(rax);
186 __ andl(rax, 0x1f); // Determine if valid topology level
187 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
188 __ andl(rax, 0xffff);
189 __ pop(rax);
190 __ jccb(Assembler::equal, std_cpuid4);
191
192 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
193 __ movl(Address(rsi, 0), rax);
194 __ movl(Address(rsi, 4), rbx);
195 __ movl(Address(rsi, 8), rcx);
196 __ movl(Address(rsi,12), rdx);
197
198 //
199 // cpuid(0x4) Deterministic cache params
200 //
201 __ bind(std_cpuid4);
202 __ movl(rax, 4);
203 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
204 __ jccb(Assembler::greater, std_cpuid1);
205
206 __ xorl(rcx, rcx); // L1 cache
207 __ cpuid();
208 __ push(rax);
209 __ andl(rax, 0x1f); // Determine if valid cache parameters used
210 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
211 __ pop(rax);
212 __ jccb(Assembler::equal, std_cpuid1);
213
214 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
215 __ movl(Address(rsi, 0), rax);
216 __ movl(Address(rsi, 4), rbx);
217 __ movl(Address(rsi, 8), rcx);
218 __ movl(Address(rsi,12), rdx);
219
220 //
221 // Standard cpuid(0x1)
222 //
223 __ bind(std_cpuid1);
224 __ movl(rax, 1);
225 __ cpuid();
226 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
227 __ movl(Address(rsi, 0), rax);
228 __ movl(Address(rsi, 4), rbx);
229 __ movl(Address(rsi, 8), rcx);
230 __ movl(Address(rsi,12), rdx);
231
232 //
233 // Check if OS has enabled XGETBV instruction to access XCR0
234 // (OSXSAVE feature flag) and CPU supports AVX
235 //
236 __ andl(rcx, 0x18000000);
237 __ cmpl(rcx, 0x18000000);
238 __ jccb(Assembler::notEqual, sef_cpuid);
239
240 //
241 // XCR0, XFEATURE_ENABLED_MASK register
242 //
243 __ xorl(rcx, rcx); // zero for XCR0 register
244 __ xgetbv();
245 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
246 __ movl(Address(rsi, 0), rax);
247 __ movl(Address(rsi, 4), rdx);
248
249 //
250 // cpuid(0x7) Structured Extended Features
251 //
252 __ bind(sef_cpuid);
253 __ movl(rax, 7);
254 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
255 __ jccb(Assembler::greater, ext_cpuid);
256
257 __ xorl(rcx, rcx);
258 __ cpuid();
259 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
260 __ movl(Address(rsi, 0), rax);
261 __ movl(Address(rsi, 4), rbx);
262
263 //
264 // Extended cpuid(0x80000000)
265 //
266 __ bind(ext_cpuid);
267 __ movl(rax, 0x80000000);
268 __ cpuid();
269 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
270 __ jcc(Assembler::belowEqual, done);
271 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
272 __ jccb(Assembler::belowEqual, ext_cpuid1);
273 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
274 __ jccb(Assembler::belowEqual, ext_cpuid5);
275 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
276 __ jccb(Assembler::belowEqual, ext_cpuid7);
277 //
278 // Extended cpuid(0x80000008)
279 //
280 __ movl(rax, 0x80000008);
281 __ cpuid();
282 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
283 __ movl(Address(rsi, 0), rax);
284 __ movl(Address(rsi, 4), rbx);
285 __ movl(Address(rsi, 8), rcx);
286 __ movl(Address(rsi,12), rdx);
287
288 //
289 // Extended cpuid(0x80000007)
290 //
291 __ bind(ext_cpuid7);
292 __ movl(rax, 0x80000007);
293 __ cpuid();
294 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
295 __ movl(Address(rsi, 0), rax);
296 __ movl(Address(rsi, 4), rbx);
297 __ movl(Address(rsi, 8), rcx);
298 __ movl(Address(rsi,12), rdx);
299
300 //
301 // Extended cpuid(0x80000005)
302 //
303 __ bind(ext_cpuid5);
304 __ movl(rax, 0x80000005);
305 __ cpuid();
306 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
307 __ movl(Address(rsi, 0), rax);
308 __ movl(Address(rsi, 4), rbx);
309 __ movl(Address(rsi, 8), rcx);
310 __ movl(Address(rsi,12), rdx);
311
312 //
313 // Extended cpuid(0x80000001)
314 //
315 __ bind(ext_cpuid1);
316 __ movl(rax, 0x80000001);
317 __ cpuid();
318 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
319 __ movl(Address(rsi, 0), rax);
320 __ movl(Address(rsi, 4), rbx);
321 __ movl(Address(rsi, 8), rcx);
322 __ movl(Address(rsi,12), rdx);
323
324 //
325 // return
326 //
327 __ bind(done);
328 __ popf();
329 __ pop(rsi);
330 __ pop(rbx);
331 __ pop(rbp);
332 __ ret(0);
333
334 # undef __
335
336 return start;
337 };
338 };
339
340
341 void VM_Version::get_processor_features() {
342
343 _cpu = 4; // 486 by default
344 _model = 0;
345 _stepping = 0;
346 _cpuFeatures = 0;
347 _logical_processors_per_package = 1;
348
349 if (!Use486InstrsOnly) {
350 // Get raw processor info
351 getPsrInfo_stub(&_cpuid_info);
352 assert_is_initialized();
353 _cpu = extended_cpu_family();
354 _model = extended_cpu_model();
355 _stepping = cpu_stepping();
356
357 if (cpu_family() > 4) { // it supports CPUID
358 _cpuFeatures = feature_flags();
359 // Logical processors are only available on P4s and above,
360 // and only if hyperthreading is available.
361 _logical_processors_per_package = logical_processor_count();
362 }
363 }
364
365 _supports_cx8 = supports_cmpxchg8();
366
367 #ifdef _LP64
368 // OS should support SSE for x64 and hardware should support at least SSE2.
369 if (!VM_Version::supports_sse2()) {
370 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
371 }
372 // in 64 bit the use of SSE2 is the minimum
373 if (UseSSE < 2) UseSSE = 2;
374 #endif
375
376 #ifdef AMD64
377 // flush_icache_stub have to be generated first.
378 // That is why Icache line size is hard coded in ICache class,
379 // see icache_x86.hpp. It is also the reason why we can't use
380 // clflush instruction in 32-bit VM since it could be running
381 // on CPU which does not support it.
382 //
383 // The only thing we can do is to verify that flushed
384 // ICache::line_size has correct value.
385 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
386 // clflush_size is size in quadwords (8 bytes).
387 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
388 #endif
389
390 // If the OS doesn't support SSE, we can't use this feature even if the HW does
391 if (!os::supports_sse())
392 _cpuFeatures &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
393
394 if (UseSSE < 4) {
395 _cpuFeatures &= ~CPU_SSE4_1;
396 _cpuFeatures &= ~CPU_SSE4_2;
397 }
398
399 if (UseSSE < 3) {
400 _cpuFeatures &= ~CPU_SSE3;
401 _cpuFeatures &= ~CPU_SSSE3;
402 _cpuFeatures &= ~CPU_SSE4A;
403 }
404
405 if (UseSSE < 2)
406 _cpuFeatures &= ~CPU_SSE2;
407
408 if (UseSSE < 1)
409 _cpuFeatures &= ~CPU_SSE;
410
411 if (UseAVX < 2)
412 _cpuFeatures &= ~CPU_AVX2;
413
414 if (UseAVX < 1)
415 _cpuFeatures &= ~CPU_AVX;
416
417 if (logical_processors_per_package() == 1) {
418 // HT processor could be installed on a system which doesn't support HT.
419 _cpuFeatures &= ~CPU_HT;
420 }
421
422 char buf[256];
423 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
424 cores_per_cpu(), threads_per_core(),
425 cpu_family(), _model, _stepping,
426 (supports_cmov() ? ", cmov" : ""),
427 (supports_cmpxchg8() ? ", cx8" : ""),
428 (supports_fxsr() ? ", fxsr" : ""),
429 (supports_mmx() ? ", mmx" : ""),
430 (supports_sse() ? ", sse" : ""),
431 (supports_sse2() ? ", sse2" : ""),
432 (supports_sse3() ? ", sse3" : ""),
433 (supports_ssse3()? ", ssse3": ""),
434 (supports_sse4_1() ? ", sse4.1" : ""),
435 (supports_sse4_2() ? ", sse4.2" : ""),
436 (supports_popcnt() ? ", popcnt" : ""),
437 (supports_avx() ? ", avx" : ""),
438 (supports_avx2() ? ", avx2" : ""),
439 (supports_mmx_ext() ? ", mmxext" : ""),
440 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""),
441 (supports_lzcnt() ? ", lzcnt": ""),
442 (supports_sse4a() ? ", sse4a": ""),
443 (supports_ht() ? ", ht": ""),
444 (supports_tsc() ? ", tsc": ""),
445 (supports_tscinv_bit() ? ", tscinvbit": ""),
446 (supports_tscinv() ? ", tscinv": ""));
447 _features_str = strdup(buf);
448
449 // UseSSE is set to the smaller of what hardware supports and what
450 // the command line requires. I.e., you cannot set UseSSE to 2 on
451 // older Pentiums which do not support it.
452 if (UseSSE > 4) UseSSE=4;
453 if (UseSSE < 0) UseSSE=0;
454 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support
455 UseSSE = MIN2((intx)3,UseSSE);
456 if (!supports_sse3()) // Drop to 2 if no SSE3 support
457 UseSSE = MIN2((intx)2,UseSSE);
458 if (!supports_sse2()) // Drop to 1 if no SSE2 support
459 UseSSE = MIN2((intx)1,UseSSE);
460 if (!supports_sse ()) // Drop to 0 if no SSE support
461 UseSSE = 0;
462
463 if (UseAVX > 2) UseAVX=2;
464 if (UseAVX < 0) UseAVX=0;
465 if (!supports_avx2()) // Drop to 1 if no AVX2 support
466 UseAVX = MIN2((intx)1,UseAVX);
467 if (!supports_avx ()) // Drop to 0 if no AVX support
468 UseAVX = 0;
469
470 // On new cpus instructions which update whole XMM register should be used
471 // to prevent partial register stall due to dependencies on high half.
472 //
473 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
474 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
475 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
476 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
477
478 if( is_amd() ) { // AMD cpus specific settings
479 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) {
480 // Use it on new AMD cpus starting from Opteron.
481 UseAddressNop = true;
482 }
483 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) {
484 // Use it on new AMD cpus starting from Opteron.
485 UseNewLongLShift = true;
486 }
487 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
488 if( supports_sse4a() ) {
489 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
490 } else {
491 UseXmmLoadAndClearUpper = false;
492 }
493 }
494 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
495 if( supports_sse4a() ) {
496 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
497 } else {
498 UseXmmRegToRegMoveAll = false;
499 }
500 }
501 if( FLAG_IS_DEFAULT(UseXmmI2F) ) {
502 if( supports_sse4a() ) {
503 UseXmmI2F = true;
504 } else {
505 UseXmmI2F = false;
506 }
507 }
508 if( FLAG_IS_DEFAULT(UseXmmI2D) ) {
509 if( supports_sse4a() ) {
510 UseXmmI2D = true;
511 } else {
512 UseXmmI2D = false;
513 }
514 }
515 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics) ) {
516 if( supports_sse4_2() && UseSSE >= 4 ) {
517 UseSSE42Intrinsics = true;
518 }
519 }
520
521 // Use count leading zeros count instruction if available.
522 if (supports_lzcnt()) {
523 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
524 UseCountLeadingZerosInstruction = true;
525 }
526 }
527
528 // some defaults for AMD family 15h
529 if ( cpu_family() == 0x15 ) {
530 // On family 15h processors default is no sw prefetch
531 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
532 AllocatePrefetchStyle = 0;
533 }
534 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
535 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
536 AllocatePrefetchInstr = 3;
537 }
538 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
539 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
540 UseXMMForArrayCopy = true;
541 }
542 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
543 UseUnalignedLoadStores = true;
544 }
545 }
546
547 }
548
549 if( is_intel() ) { // Intel cpus specific settings
550 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) {
551 UseStoreImmI16 = false; // don't use it on Intel cpus
552 }
553 if( cpu_family() == 6 || cpu_family() == 15 ) {
554 if( FLAG_IS_DEFAULT(UseAddressNop) ) {
555 // Use it on all Intel cpus starting from PentiumPro
556 UseAddressNop = true;
557 }
558 }
559 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) {
560 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
561 }
562 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) {
563 if( supports_sse3() ) {
564 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
565 } else {
566 UseXmmRegToRegMoveAll = false;
567 }
568 }
569 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus
570 #ifdef COMPILER2
571 if( FLAG_IS_DEFAULT(MaxLoopPad) ) {
572 // For new Intel cpus do the next optimization:
573 // don't align the beginning of a loop if there are enough instructions
574 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
575 // in current fetch line (OptoLoopAlignment) or the padding
576 // is big (> MaxLoopPad).
577 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
578 // generated NOP instructions. 11 is the largest size of one
579 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
580 MaxLoopPad = 11;
581 }
582 #endif // COMPILER2
583 if( FLAG_IS_DEFAULT(UseXMMForArrayCopy) ) {
584 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
585 }
586 if( supports_sse4_2() && supports_ht() ) { // Newest Intel cpus
587 if( FLAG_IS_DEFAULT(UseUnalignedLoadStores) && UseXMMForArrayCopy ) {
588 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
589 }
590 }
591 if( supports_sse4_2() && UseSSE >= 4 ) {
592 if( FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
593 UseSSE42Intrinsics = true;
594 }
595 }
596 }
597 }
598
599 // Use population count instruction if available.
600 if (supports_popcnt()) {
601 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
602 UsePopCountInstruction = true;
603 }
604 } else if (UsePopCountInstruction) {
605 warning("POPCNT instruction is not available on this CPU");
606 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
607 }
608
609 #ifdef COMPILER2
610 if (UseFPUForSpilling) {
611 if (UseSSE < 2) {
612 // Only supported with SSE2+
613 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
614 }
615 }
616 #endif
617
618 assert(0 <= ReadPrefetchInstr && ReadPrefetchInstr <= 3, "invalid value");
619 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 3, "invalid value");
620
621 // set valid Prefetch instruction
622 if( ReadPrefetchInstr < 0 ) ReadPrefetchInstr = 0;
623 if( ReadPrefetchInstr > 3 ) ReadPrefetchInstr = 3;
624 if( ReadPrefetchInstr == 3 && !supports_3dnow_prefetch() ) ReadPrefetchInstr = 0;
625 if( !supports_sse() && supports_3dnow_prefetch() ) ReadPrefetchInstr = 3;
626
627 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
628 if( AllocatePrefetchInstr > 3 ) AllocatePrefetchInstr = 3;
629 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0;
630 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3;
631
632 // Allocation prefetch settings
633 intx cache_line_size = prefetch_data_size();
634 if( cache_line_size > AllocatePrefetchStepSize )
635 AllocatePrefetchStepSize = cache_line_size;
636
637 assert(AllocatePrefetchLines > 0, "invalid value");
638 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
639 AllocatePrefetchLines = 3;
640 assert(AllocateInstancePrefetchLines > 0, "invalid value");
641 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
642 AllocateInstancePrefetchLines = 1;
643
644 AllocatePrefetchDistance = allocate_prefetch_distance();
645 AllocatePrefetchStyle = allocate_prefetch_style();
646
647 if( is_intel() && cpu_family() == 6 && supports_sse3() ) {
648 if( AllocatePrefetchStyle == 2 ) { // watermark prefetching on Core
649 #ifdef _LP64
650 AllocatePrefetchDistance = 384;
651 #else
652 AllocatePrefetchDistance = 320;
653 #endif
654 }
655 if( supports_sse4_2() && supports_ht() ) { // Nehalem based cpus
656 AllocatePrefetchDistance = 192;
657 AllocatePrefetchLines = 4;
658 #ifdef COMPILER2
659 if (AggressiveOpts && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
660 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
661 }
662 #endif
663 }
664 }
665 assert(AllocatePrefetchDistance % AllocatePrefetchStepSize == 0, "invalid value");
666
667 #ifdef _LP64
668 // Prefetch settings
669 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
670 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
671 PrefetchFieldsAhead = prefetch_fields_ahead();
672 #endif
673
674 #ifndef PRODUCT
675 if (PrintMiscellaneous && Verbose) {
676 tty->print_cr("Logical CPUs per core: %u",
677 logical_processors_per_package());
678 tty->print("UseSSE=%d",UseSSE);
679 if (UseAVX > 0) {
680 tty->print(" UseAVX=%d",UseAVX);
681 }
682 tty->cr();
683 tty->print("Allocation");
684 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) {
685 tty->print_cr(": no prefetching");
686 } else {
687 tty->print(" prefetching: ");
688 if (UseSSE == 0 && supports_3dnow_prefetch()) {
689 tty->print("PREFETCHW");
690 } else if (UseSSE >= 1) {
691 if (AllocatePrefetchInstr == 0) {
692 tty->print("PREFETCHNTA");
693 } else if (AllocatePrefetchInstr == 1) {
694 tty->print("PREFETCHT0");
695 } else if (AllocatePrefetchInstr == 2) {
696 tty->print("PREFETCHT2");
697 } else if (AllocatePrefetchInstr == 3) {
698 tty->print("PREFETCHW");
699 }
700 }
701 if (AllocatePrefetchLines > 1) {
702 tty->print_cr(" at distance %d, %d lines of %d bytes", AllocatePrefetchDistance, AllocatePrefetchLines, AllocatePrefetchStepSize);
703 } else {
704 tty->print_cr(" at distance %d, one line of %d bytes", AllocatePrefetchDistance, AllocatePrefetchStepSize);
705 }
706 }
707
708 if (PrefetchCopyIntervalInBytes > 0) {
709 tty->print_cr("PrefetchCopyIntervalInBytes %d", PrefetchCopyIntervalInBytes);
710 }
711 if (PrefetchScanIntervalInBytes > 0) {
712 tty->print_cr("PrefetchScanIntervalInBytes %d", PrefetchScanIntervalInBytes);
713 }
714 if (PrefetchFieldsAhead > 0) {
715 tty->print_cr("PrefetchFieldsAhead %d", PrefetchFieldsAhead);
716 }
717 }
718 #endif // !PRODUCT
719 }
720
721 void VM_Version::initialize() {
722 ResourceMark rm;
723 // Making this stub must be FIRST use of assembler
724
725 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
726 if (stub_blob == NULL) {
727 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
728 }
729 CodeBuffer c(stub_blob);
730 VM_Version_StubGenerator g(&c);
731 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
732 g.generate_getPsrInfo());
733
734 get_processor_features();
735 }