8409 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8410 emit_int8((unsigned char)0xF3);
8411 emit_int8((unsigned char)(0xC0 | encode));
8412 }
8413
8414 void Assembler::blsrq(Register dst, Address src) {
8415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8416 InstructionMark im(this);
8417 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8418 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8419 emit_int8((unsigned char)0xF3);
8420 emit_operand(rcx, src);
8421 }
8422
8423 void Assembler::cdqq() {
8424 prefix(REX_W);
8425 emit_int8((unsigned char)0x99);
8426 }
8427
8428 void Assembler::clflush(Address adr) {
8429 prefix(adr);
8430 emit_int8(0x0F);
8431 emit_int8((unsigned char)0xAE);
8432 emit_operand(rdi, adr);
8433 }
8434
8435 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8436 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8437 emit_int8(0x0F);
8438 emit_int8(0x40 | cc);
8439 emit_int8((unsigned char)(0xC0 | encode));
8440 }
8441
8442 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8443 InstructionMark im(this);
8444 prefixq(src, dst);
8445 emit_int8(0x0F);
8446 emit_int8(0x40 | cc);
8447 emit_operand(dst, src);
8448 }
8449
8450 void Assembler::cmpq(Address dst, int32_t imm32) {
8451 InstructionMark im(this);
8452 prefixq(dst);
8453 emit_int8((unsigned char)0x81);
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8409 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8410 emit_int8((unsigned char)0xF3);
8411 emit_int8((unsigned char)(0xC0 | encode));
8412 }
8413
8414 void Assembler::blsrq(Register dst, Address src) {
8415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8416 InstructionMark im(this);
8417 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8418 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8419 emit_int8((unsigned char)0xF3);
8420 emit_operand(rcx, src);
8421 }
8422
8423 void Assembler::cdqq() {
8424 prefix(REX_W);
8425 emit_int8((unsigned char)0x99);
8426 }
8427
8428 void Assembler::clflush(Address adr) {
8429 assert(VM_Version::supports_clflush(), "should do");
8430 prefix(adr);
8431 emit_int8(0x0F);
8432 emit_int8((unsigned char)0xAE);
8433 emit_operand(rdi, adr);
8434 }
8435
8436 #ifdef _LP64
8437 void Assembler::clflushopt(Address adr) {
8438 assert(VM_Version::supports_clflushopt(), "should do!");
8439 // adr should be base reg only with no index or offset
8440 assert(adr.index() == noreg, "index should be noreg");
8441 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8442 assert(adr.disp() == 0, "displacement should be 0");
8443 // prefix is 0x66
8444 emit_int8(0x66);
8445 // opcode family is 0x0f 0xAE
8446 emit_int8(0x0F);
8447 emit_int8((unsigned char)0xAE);
8448 // extended opcode byte is 7 == rdi
8449 emit_operand(rdi, adr);
8450 }
8451
8452 void Assembler::clwb(Address adr) {
8453 assert(VM_Version::supports_clwb(), "should do!");
8454 // adr should be base reg only with no index or offset
8455 assert(adr.index() == noreg, "index should be noreg");
8456 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
8457 assert(adr.disp() == 0, "displacement should be 0");
8458 // prefix is 0x66
8459 emit_int8(0x66);
8460 // opcode family is 0x0f 0xAE
8461 emit_int8(0x0F);
8462 emit_int8((unsigned char)0xAE);
8463 // extended opcode byte is 6 == rsi
8464 emit_operand(rsi, adr);
8465 }
8466 #endif
8467
8468 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8469 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8470 emit_int8(0x0F);
8471 emit_int8(0x40 | cc);
8472 emit_int8((unsigned char)(0xC0 | encode));
8473 }
8474
8475 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8476 InstructionMark im(this);
8477 prefixq(src, dst);
8478 emit_int8(0x0F);
8479 emit_int8(0x40 | cc);
8480 emit_operand(dst, src);
8481 }
8482
8483 void Assembler::cmpq(Address dst, int32_t imm32) {
8484 InstructionMark im(this);
8485 prefixq(dst);
8486 emit_int8((unsigned char)0x81);
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