< prev index next >

src/hotspot/cpu/x86/assembler_x86.cpp

Print this page

        

@@ -2190,10 +2190,18 @@
   emit_int8(0x0F);
   emit_int8((unsigned char)0xAE);
   emit_int8((unsigned char)0xF0);
 }
 
+// Emit sfence instruction
+void Assembler::sfence() {
+  NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
+  emit_int8(0x0F);
+  emit_int8((unsigned char)0xAE);
+  emit_int8((unsigned char)0xF8);
+}
+
 void Assembler::mov(Register dst, Register src) {
   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
 }
 
 void Assembler::movapd(XMMRegister dst, XMMRegister src) {

@@ -8424,16 +8432,51 @@
   prefix(REX_W);
   emit_int8((unsigned char)0x99);
 }
 
 void Assembler::clflush(Address adr) {
+  assert(VM_Version::supports_clflush(), "should do");
+  prefix(adr);
+  emit_int8(0x0F);
+  emit_int8((unsigned char)0xAE);
+  emit_operand(rdi, adr);
+}
+
+#ifdef _LP64
+void Assembler::clflushopt(Address adr) {
+  assert(VM_Version::supports_clflushopt(), "should do!");
+  // adr should be base reg only with no index or offset
+  assert(adr.index() == noreg, "index should be noreg");
+  assert(adr.scale() == Address::no_scale, "scale should be no_scale");
+  assert(adr.disp() == 0, "displacement should be 0");
+  // instruction prefix is 0x66
+  emit_int8(0x66);
   prefix(adr);
+  // opcode family is 0x0f 0xAE
   emit_int8(0x0F);
   emit_int8((unsigned char)0xAE);
+  // extended opcode byte is 7 == rdi
   emit_operand(rdi, adr);
 }
 
+void Assembler::clwb(Address adr) {
+  assert(VM_Version::supports_clwb(), "should do!");
+  // adr should be base reg only with no index or offset
+  assert(adr.index() == noreg, "index should be noreg");
+  assert(adr.scale() == Address::no_scale, "scale should be no_scale");
+  assert(adr.disp() == 0, "displacement should be 0");
+  // instruction prefix is 0x66
+  emit_int8(0x66);
+  prefix(adr);
+  // opcode family is 0x0f 0xAE
+  emit_int8(0x0F);
+  emit_int8((unsigned char)0xAE);
+  // extended opcode byte is 6 == rsi
+  emit_operand(rsi, adr);
+}
+#endif
+
 void Assembler::cmovq(Condition cc, Register dst, Register src) {
   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
   emit_int8(0x0F);
   emit_int8(0x40 | cc);
   emit_int8((unsigned char)(0xC0 | encode));
< prev index next >