1 /*
2 * Copyright (c) 2008, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "nativeInst_arm.hpp"
33 #include "oops/compiledICHolder.hpp"
34 #include "oops/oop.inline.hpp"
35 #include "prims/jvmtiExport.hpp"
36 #include "register_arm.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/signature.hpp"
39 #include "runtime/vframeArray.hpp"
40 #include "vmreg_arm.inline.hpp"
41 #if INCLUDE_ALL_GCS
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #endif
44
45 // Note: Rtemp usage is this file should not impact C2 and should be
46 // correct as long as it is not implicitly used in lower layers (the
47 // arm [macro]assembler) and used with care in the other C1 specific
48 // files.
49
50 // Implementation of StubAssembler
51
52 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
53 mov(R0, Rthread);
54
55 int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
56
57 call(entry);
58 if (call_offset == -1) { // PC not saved
59 call_offset = offset();
60 }
61 reset_last_Java_frame(Rtemp);
62
63 assert(frame_size() != no_frame_size, "frame must be fixed");
64 if (_stub_id != Runtime1::forward_exception_id) {
65 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
66 }
67
68 if (oop_result1->is_valid()) {
69 assert_different_registers(oop_result1, R3, Rtemp);
70 get_vm_result(oop_result1, Rtemp);
71 }
72 if (metadata_result->is_valid()) {
73 assert_different_registers(metadata_result, R3, Rtemp);
74 get_vm_result_2(metadata_result, Rtemp);
75 }
76
77 // Check for pending exception
78 // unpack_with_exception_in_tls path is taken through
79 // Runtime1::exception_handler_for_pc
80 if (_stub_id != Runtime1::forward_exception_id) {
81 assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
82 #ifdef AARCH64
83 Label skip;
84 cbz(R3, skip);
85 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
86 bind(skip);
87 #else
88 cmp(R3, 0);
89 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
90 #endif // AARCH64
91 } else {
92 #ifdef ASSERT
93 // Should not have pending exception in forward_exception stub
94 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
95 cmp(R3, 0);
96 breakpoint(ne);
97 #endif // ASSERT
98 }
99 return call_offset;
100 }
101
102
103 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
104 if (arg1 != R1) {
105 mov(R1, arg1);
106 }
107 return call_RT(oop_result1, metadata_result, entry, 1);
108 }
109
110
111 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
112 assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
113 return call_RT(oop_result1, metadata_result, entry, 2);
114 }
115
116
117 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
118 assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
119 return call_RT(oop_result1, metadata_result, entry, 3);
120 }
121
122
123 #define __ sasm->
124
125 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
126 #ifdef AARCH64
127
128 //
129 // On AArch64 registers save area has the following layout:
130 //
131 // |---------------------|
132 // | return address (LR) |
133 // | FP |
134 // |---------------------|
135 // | D31 |
136 // | ... |
137 // | D0 |
138 // |---------------------|
139 // | padding |
140 // |---------------------|
141 // | R28 |
142 // | ... |
143 // | R0 |
144 // |---------------------| <-- SP
145 //
146
147 enum RegisterLayout {
148 number_of_saved_gprs = 29,
149 number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
150
151 R0_offset = 0,
152 D0_offset = R0_offset + number_of_saved_gprs + 1,
153 FP_offset = D0_offset + number_of_saved_fprs,
154 LR_offset = FP_offset + 1,
155
156 reg_save_size = LR_offset + 1,
157
158 arg1_offset = reg_save_size * wordSize,
159 arg2_offset = (reg_save_size + 1) * wordSize
160 };
161
162 #else
163
164 enum RegisterLayout {
165 fpu_save_size = pd_nof_fpu_regs_reg_alloc,
166 #ifndef __SOFTFP__
167 D0_offset = 0,
168 #endif
169 R0_offset = fpu_save_size,
170 R1_offset,
171 R2_offset,
172 R3_offset,
173 R4_offset,
174 R5_offset,
175 R6_offset,
176 #if (FP_REG_NUM != 7)
177 R7_offset,
178 #endif
179 R8_offset,
180 R9_offset,
181 R10_offset,
182 #if (FP_REG_NUM != 11)
183 R11_offset,
184 #endif
185 R12_offset,
186 FP_offset,
187 LR_offset,
188 reg_save_size,
189 arg1_offset = reg_save_size * wordSize,
190 arg2_offset = (reg_save_size + 1) * wordSize
191 };
192
193 #endif // AARCH64
194
195 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
196 sasm->set_frame_size(reg_save_size /* in words */);
197
198 // Record saved value locations in an OopMap.
199 // Locations are offsets from sp after runtime call.
200 OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
201
202 #ifdef AARCH64
203 for (int i = 0; i < number_of_saved_gprs; i++) {
204 map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
205 }
206 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
207 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
208
209 if (save_fpu_registers) {
210 for (int i = 0; i < number_of_saved_fprs; i++) {
211 map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
212 }
213 }
214 #else
215 int j=0;
216 for (int i = R0_offset; i < R10_offset; i++) {
217 if (j == FP_REG_NUM) {
218 // skip the FP register, saved below
219 j++;
220 }
221 map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
222 j++;
223 }
224 assert(j == R10->encoding(), "must be");
225 #if (FP_REG_NUM != 11)
226 // add R11, if not saved as FP
227 map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
228 #endif
229 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
230 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
231
232 if (save_fpu_registers) {
233 for (int i = 0; i < fpu_save_size; i++) {
234 map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
235 }
236 }
237 #endif // AARCH64
238
239 return map;
240 }
241
242 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
243 __ block_comment("save_live_registers");
244 sasm->set_frame_size(reg_save_size /* in words */);
245
246 #ifdef AARCH64
247 assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
248
249 __ raw_push(FP, LR);
250
251 __ sub(SP, SP, (reg_save_size - 2) * wordSize);
252
253 for (int i = 0; i < round_down(number_of_saved_gprs, 2); i += 2) {
254 __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
255 }
256
257 if (is_odd(number_of_saved_gprs)) {
258 int i = number_of_saved_gprs - 1;
259 __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
260 }
261
262 if (save_fpu_registers) {
263 assert (is_even(number_of_saved_fprs), "adjust this code");
264 for (int i = 0; i < number_of_saved_fprs; i += 2) {
265 __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
266 }
267 }
268 #else
269 __ push(RegisterSet(FP) | RegisterSet(LR));
270 __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
271 if (save_fpu_registers) {
272 __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
273 } else {
274 __ sub(SP, SP, fpu_save_size * wordSize);
275 }
276 #endif // AARCH64
277
278 return generate_oop_map(sasm, save_fpu_registers);
279 }
280
281
282 static void restore_live_registers(StubAssembler* sasm,
283 bool restore_R0,
284 bool restore_FP_LR,
285 bool do_return,
286 bool restore_fpu_registers = HaveVFP) {
287 __ block_comment("restore_live_registers");
288
289 #ifdef AARCH64
290 if (restore_R0) {
291 __ ldr(R0, Address(SP, R0_offset * wordSize));
292 }
293
294 assert(is_odd(number_of_saved_gprs), "adjust this code");
295 for (int i = 1; i < number_of_saved_gprs; i += 2) {
296 __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
297 }
298
299 if (restore_fpu_registers) {
300 assert (is_even(number_of_saved_fprs), "adjust this code");
301 for (int i = 0; i < number_of_saved_fprs; i += 2) {
302 __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
303 }
304 }
305
306 __ add(SP, SP, (reg_save_size - 2) * wordSize);
307
308 if (restore_FP_LR) {
309 __ raw_pop(FP, LR);
310 if (do_return) {
311 __ ret();
312 }
313 } else {
314 assert (!do_return, "return without restoring FP/LR");
315 }
316 #else
317 if (restore_fpu_registers) {
318 __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
319 if (!restore_R0) {
320 __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
321 }
322 } else {
323 __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
324 }
325 __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
326 if (restore_FP_LR) {
327 __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
328 } else {
329 assert (!do_return, "return without restoring FP/LR");
330 }
331 #endif // AARCH64
332 }
333
334
335 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
336 restore_live_registers(sasm, false, true, true, restore_fpu_registers);
337 }
338
339 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
340 restore_live_registers(sasm, true, true, true, restore_fpu_registers);
341 }
342
343 #ifndef AARCH64
344 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
345 restore_live_registers(sasm, true, false, false, restore_fpu_registers);
346 }
347 #endif // !AARCH64
348
349 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
350 restore_live_registers(sasm, true, true, false, restore_fpu_registers);
351 }
352
353
354 void Runtime1::initialize_pd() {
355 }
356
357
358 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
359 OopMap* oop_map = save_live_registers(sasm);
360
361 if (has_argument) {
362 __ ldr(R1, Address(SP, arg1_offset));
363 }
364
365 int call_offset = __ call_RT(noreg, noreg, target);
366 OopMapSet* oop_maps = new OopMapSet();
367 oop_maps->add_gc_map(call_offset, oop_map);
368
369 DEBUG_ONLY(STOP("generate_exception_throw");) // Should not reach here
370 return oop_maps;
371 }
372
373
374 static void restore_sp_for_method_handle(StubAssembler* sasm) {
375 // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
376 __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
377 #ifdef AARCH64
378 Label skip;
379 __ cbz(Rtemp, skip);
380 __ mov(SP, Rmh_SP_save);
381 __ bind(skip);
382 #else
383 __ cmp(Rtemp, 0);
384 __ mov(SP, Rmh_SP_save, ne);
385 #endif // AARCH64
386 }
387
388
389 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
390 __ block_comment("generate_handle_exception");
391
392 bool save_fpu_registers = false;
393
394 // Save registers, if required.
395 OopMapSet* oop_maps = new OopMapSet();
396 OopMap* oop_map = NULL;
397
398 switch (id) {
399 case forward_exception_id: {
400 save_fpu_registers = HaveVFP;
401 oop_map = generate_oop_map(sasm);
402 __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
403 __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
404 Register zero = __ zero_register(Rtemp);
405 __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
406 break;
407 }
408 case handle_exception_id:
409 save_fpu_registers = HaveVFP;
410 // fall-through
411 case handle_exception_nofpu_id:
412 // At this point all registers MAY be live.
413 oop_map = save_live_registers(sasm, save_fpu_registers);
414 break;
415 case handle_exception_from_callee_id:
416 // At this point all registers except exception oop (R4/R19) and
417 // exception pc (R5/R20) are dead.
418 oop_map = save_live_registers(sasm); // TODO it's not required to save all registers
419 break;
420 default: ShouldNotReachHere();
421 }
422
423 __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
424 __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
425
426 __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
427
428 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
429 oop_maps->add_gc_map(call_offset, oop_map);
430
431 // Exception handler found
432 __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
433
434 // Restore the registers that were saved at the beginning, remove
435 // frame and jump to the exception handler.
436 switch (id) {
437 case forward_exception_id:
438 case handle_exception_nofpu_id:
439 case handle_exception_id:
440 restore_live_registers(sasm, save_fpu_registers);
441 // Note: the restore live registers includes the jump to LR (patched to R0)
442 break;
443 case handle_exception_from_callee_id:
444 restore_live_registers_without_return(sasm); // must not jump immediatly to handler
445 restore_sp_for_method_handle(sasm);
446 __ ret();
447 break;
448 default: ShouldNotReachHere();
449 }
450
451 DEBUG_ONLY(STOP("generate_handle_exception");) // Should not reach here
452
453 return oop_maps;
454 }
455
456
457 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
458 // FP no longer used to find the frame start
459 // on entry, remove_frame() has already been called (restoring FP and LR)
460
461 // search the exception handler address of the caller (using the return address)
462 __ mov(c_rarg0, Rthread);
463 __ mov(Rexception_pc, LR);
464 __ mov(c_rarg1, LR);
465 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
466
467 // Exception oop should be still in Rexception_obj and pc in Rexception_pc
468 // Jump to handler
469 __ verify_not_null_oop(Rexception_obj);
470
471 // JSR292 extension
472 restore_sp_for_method_handle(sasm);
473
474 __ jump(R0);
475 }
476
477
478 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
479 OopMap* oop_map = save_live_registers(sasm);
480
481 // call the runtime patching routine, returns non-zero if nmethod got deopted.
482 int call_offset = __ call_RT(noreg, noreg, target);
483 OopMapSet* oop_maps = new OopMapSet();
484 oop_maps->add_gc_map(call_offset, oop_map);
485
486 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
487 assert(deopt_blob != NULL, "deoptimization blob must have been created");
488
489 __ cmp_32(R0, 0);
490
491 #ifdef AARCH64
492 Label call_deopt;
493
494 restore_live_registers_without_return(sasm);
495 __ b(call_deopt, ne);
496 __ ret();
497
498 __ bind(call_deopt);
499 #else
500 restore_live_registers_except_FP_LR(sasm);
501 __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
502
503 // Deoptimization needed
504 // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
505 __ pop(RegisterSet(FP) | RegisterSet(LR));
506 #endif // AARCH64
507
508 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
509
510 DEBUG_ONLY(STOP("generate_patching");) // Should not reach here
511 return oop_maps;
512 }
513
514
515 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
516 const bool must_gc_arguments = true;
517 const bool dont_gc_arguments = false;
518
519 OopMapSet* oop_maps = NULL;
520 bool save_fpu_registers = HaveVFP;
521
522 switch (id) {
523 case forward_exception_id:
524 {
525 oop_maps = generate_handle_exception(id, sasm);
526 // does not return on ARM
527 }
528 break;
529
530 #if INCLUDE_ALL_GCS
531 case g1_pre_barrier_slow_id:
532 case g1_pre_barrier_slow_with_recheck_id:
533 {
534 // Input:
535 // - pre_val pushed on the stack
536
537 if (id == g1_pre_barrier_slow_id) {
538 __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
539 } else {
540 __ set_info("g1_pre_barrier_slow_with_recheck_id", dont_gc_arguments);
541 }
542
543 // save at least the registers that need saving if the runtime is called
544 #ifdef AARCH64
545 __ raw_push(R0, R1);
546 __ raw_push(R2, R3);
547 const int nb_saved_regs = 4;
548 #else // AARCH64
549 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
550 const int nb_saved_regs = 6;
551 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
552 __ push(saved_regs);
553 #endif // AARCH64
554
555 const Register r_pre_val_0 = R0; // must be R0, to be ready for the runtime call
556 const Register r_index_1 = R1;
557 const Register r_buffer_2 = R2;
558
559 Address queue_active(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
560 SATBMarkQueue::byte_offset_of_active()));
561 Address queue_index(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
562 SATBMarkQueue::byte_offset_of_index()));
563 Address buffer(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
564 SATBMarkQueue::byte_offset_of_buf()));
565
566 Label done;
567 Label runtime;
568
569 if (id == g1_pre_barrier_slow_with_recheck_id) {
570 // Is marking still active?
571 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "adjust this code");
572 __ ldrb(R1, queue_active);
573 __ cbz(R1, done);
574 }
575
576 __ ldr(r_index_1, queue_index);
577 __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
578 __ ldr(r_buffer_2, buffer);
579
580 __ subs(r_index_1, r_index_1, wordSize);
581 __ b(runtime, lt);
582
583 __ str(r_index_1, queue_index);
584 __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
585
586 __ bind(done);
587
588 #ifdef AARCH64
589 __ raw_pop(R2, R3);
590 __ raw_pop(R0, R1);
591 #else // AARCH64
592 __ pop(saved_regs);
593 #endif // AARCH64
594
595 __ ret();
596
597 __ bind(runtime);
598
599 save_live_registers(sasm);
600
601 assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
602 __ mov(c_rarg1, Rthread);
603 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
604
605 restore_live_registers_without_return(sasm);
606
607 __ b(done);
608 }
609 break;
610 case g1_post_barrier_slow_id:
611 {
612 // Input:
613 // - store_addr, pushed on the stack
614
615 __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
616
617 BarrierSet* bs = Universe::heap()->barrier_set();
618 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
619 Label done;
620 Label recheck;
621 Label runtime;
622
623 Address queue_index(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
624 DirtyCardQueue::byte_offset_of_index()));
625 Address buffer(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
626 DirtyCardQueue::byte_offset_of_buf()));
627
628 AddressLiteral cardtable((address)ct->byte_map_base);
629 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
630
631 // save at least the registers that need saving if the runtime is called
632 #ifdef AARCH64
633 __ raw_push(R0, R1);
634 __ raw_push(R2, R3);
635 const int nb_saved_regs = 4;
636 #else // AARCH64
637 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
638 const int nb_saved_regs = 6;
639 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
640 __ push(saved_regs);
641 #endif // AARCH64
642
643 const Register r_card_addr_0 = R0; // must be R0 for the slow case
644 const Register r_obj_0 = R0;
645 const Register r_card_base_1 = R1;
646 const Register r_tmp2 = R2;
647 const Register r_index_2 = R2;
648 const Register r_buffer_3 = R3;
649 const Register tmp1 = Rtemp;
650
651 __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
652 // Note: there is a comment in x86 code about not using
653 // ExternalAddress / lea, due to relocation not working
654 // properly for that address. Should be OK for arm, where we
655 // explicitly specify that 'cartable' has a relocInfo::none
656 // type.
657 __ lea(r_card_base_1, cardtable);
658 __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTableModRefBS::card_shift));
659
660 // first quick check without barrier
661 __ ldrb(r_tmp2, Address(r_card_addr_0));
662
663 __ cmp(r_tmp2, (int)G1SATBCardTableModRefBS::g1_young_card_val());
664 __ b(recheck, ne);
665
666 __ bind(done);
667
668 #ifdef AARCH64
669 __ raw_pop(R2, R3);
670 __ raw_pop(R0, R1);
671 #else // AARCH64
672 __ pop(saved_regs);
673 #endif // AARCH64
674
675 __ ret();
676
677 __ bind(recheck);
678
679 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
680
681 // reload card state after the barrier that ensures the stored oop was visible
682 __ ldrb(r_tmp2, Address(r_card_addr_0));
683
684 assert(CardTableModRefBS::dirty_card_val() == 0, "adjust this code");
685 __ cbz(r_tmp2, done);
686
687 // storing region crossing non-NULL, card is clean.
688 // dirty card and log.
689
690 assert(0 == (int)CardTableModRefBS::dirty_card_val(), "adjust this code");
691 if (((intptr_t)ct->byte_map_base & 0xff) == 0) {
692 // Card table is aligned so the lowest byte of the table address base is zero.
693 __ strb(r_card_base_1, Address(r_card_addr_0));
694 } else {
695 __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
696 }
697
698 __ ldr(r_index_2, queue_index);
699 __ ldr(r_buffer_3, buffer);
700
701 __ subs(r_index_2, r_index_2, wordSize);
702 __ b(runtime, lt); // go to runtime if now negative
703
704 __ str(r_index_2, queue_index);
705
706 __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
707
708 __ b(done);
709
710 __ bind(runtime);
711
712 save_live_registers(sasm);
713
714 assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
715 __ mov(c_rarg1, Rthread);
716 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
717
718 restore_live_registers_without_return(sasm);
719
720 __ b(done);
721 }
722 break;
723 #endif // INCLUDE_ALL_GCS
724 case new_instance_id:
725 case fast_new_instance_id:
726 case fast_new_instance_init_check_id:
727 {
728 const Register result = R0;
729 const Register klass = R1;
730
731 if (UseTLAB && FastTLABRefill && id != new_instance_id) {
732 // We come here when TLAB allocation failed.
733 // In this case we either refill TLAB or allocate directly from eden.
734 Label retry_tlab, try_eden, slow_case, slow_case_no_pop;
735
736 // Make sure the class is fully initialized
737 if (id == fast_new_instance_init_check_id) {
738 __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
739 __ cmp(result, InstanceKlass::fully_initialized);
740 __ b(slow_case_no_pop, ne);
741 }
742
743 // Free some temporary registers
744 const Register obj_size = R4;
745 const Register tmp1 = R5;
746 const Register tmp2 = LR;
747 const Register obj_end = Rtemp;
748
749 __ raw_push(R4, R5, LR);
750
751 __ tlab_refill(result, obj_size, tmp1, tmp2, obj_end, try_eden, slow_case);
752
753 __ bind(retry_tlab);
754 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
755 __ tlab_allocate(result, obj_end, tmp1, obj_size, slow_case); // initializes result and obj_end
756 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
757 instanceOopDesc::header_size() * HeapWordSize, -1,
758 /* is_tlab_allocated */ true);
759 __ raw_pop_and_ret(R4, R5);
760
761 __ bind(try_eden);
762 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
763 __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case); // initializes result and obj_end
764 __ incr_allocated_bytes(obj_size, tmp2);
765 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
766 instanceOopDesc::header_size() * HeapWordSize, -1,
767 /* is_tlab_allocated */ false);
768 __ raw_pop_and_ret(R4, R5);
769
770 __ bind(slow_case);
771 __ raw_pop(R4, R5, LR);
772
773 __ bind(slow_case_no_pop);
774 }
775
776 OopMap* map = save_live_registers(sasm);
777 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
778 oop_maps = new OopMapSet();
779 oop_maps->add_gc_map(call_offset, map);
780
781 // MacroAssembler::StoreStore useless (included in the runtime exit path)
782
783 restore_live_registers_except_R0(sasm);
784 }
785 break;
786
787 case counter_overflow_id:
788 {
789 OopMap* oop_map = save_live_registers(sasm);
790 __ ldr(R1, Address(SP, arg1_offset));
791 __ ldr(R2, Address(SP, arg2_offset));
792 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
793 oop_maps = new OopMapSet();
794 oop_maps->add_gc_map(call_offset, oop_map);
795 restore_live_registers(sasm);
796 }
797 break;
798
799 case new_type_array_id:
800 case new_object_array_id:
801 {
802 if (id == new_type_array_id) {
803 __ set_info("new_type_array", dont_gc_arguments);
804 } else {
805 __ set_info("new_object_array", dont_gc_arguments);
806 }
807
808 const Register result = R0;
809 const Register klass = R1;
810 const Register length = R2;
811
812 if (UseTLAB && FastTLABRefill) {
813 // We come here when TLAB allocation failed.
814 // In this case we either refill TLAB or allocate directly from eden.
815 Label retry_tlab, try_eden, slow_case, slow_case_no_pop;
816
817 #ifdef AARCH64
818 __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
819 __ cmp_32(length, Rtemp);
820 #else
821 __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
822 #endif // AARCH64
823 __ b(slow_case_no_pop, hs);
824
825 // Free some temporary registers
826 const Register arr_size = R4;
827 const Register tmp1 = R5;
828 const Register tmp2 = LR;
829 const Register tmp3 = Rtemp;
830 const Register obj_end = tmp3;
831
832 __ raw_push(R4, R5, LR);
833
834 __ tlab_refill(result, arr_size, tmp1, tmp2, tmp3, try_eden, slow_case);
835
836 __ bind(retry_tlab);
837 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
838 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
839 __ mov(arr_size, MinObjAlignmentInBytesMask);
840 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
841
842 #ifdef AARCH64
843 __ lslv_w(tmp3, length, tmp1);
844 __ add(arr_size, arr_size, tmp3);
845 #else
846 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
847 #endif // AARCH64
848
849 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
850 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
851
852 // tlab_allocate initializes result and obj_end, and preserves tmp2 which contains header_size
853 __ tlab_allocate(result, obj_end, tmp1, arr_size, slow_case);
854
855 assert_different_registers(result, obj_end, klass, length, tmp1, tmp2);
856 __ initialize_header(result, klass, length, tmp1);
857
858 __ add(tmp2, result, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
859 if (!ZeroTLAB) {
860 __ initialize_body(tmp2, obj_end, tmp1);
861 }
862
863 __ membar(MacroAssembler::StoreStore, tmp1);
864
865 __ raw_pop_and_ret(R4, R5);
866
867 __ bind(try_eden);
868 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
869 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
870 __ mov(arr_size, MinObjAlignmentInBytesMask);
871 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
872
873 #ifdef AARCH64
874 __ lslv_w(tmp3, length, tmp1);
875 __ add(arr_size, arr_size, tmp3);
876 #else
877 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
878 #endif // AARCH64
879
880 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
881 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
882
883 // eden_allocate destroys tmp2, so reload header_size after allocation
884 // eden_allocate initializes result and obj_end
885 __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
886 __ incr_allocated_bytes(arr_size, tmp2);
887 __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
888 Klass::_lh_header_size_shift / BitsPerByte));
889 __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
890 __ raw_pop_and_ret(R4, R5);
891
892 __ bind(slow_case);
893 __ raw_pop(R4, R5, LR);
894 __ bind(slow_case_no_pop);
895 }
896
897 OopMap* map = save_live_registers(sasm);
898 int call_offset;
899 if (id == new_type_array_id) {
900 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
901 } else {
902 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
903 }
904 oop_maps = new OopMapSet();
905 oop_maps->add_gc_map(call_offset, map);
906
907 // MacroAssembler::StoreStore useless (included in the runtime exit path)
908
909 restore_live_registers_except_R0(sasm);
910 }
911 break;
912
913 case new_multi_array_id:
914 {
915 __ set_info("new_multi_array", dont_gc_arguments);
916
917 // R0: klass
918 // R2: rank
919 // SP: address of 1st dimension
920 const Register result = R0;
921 OopMap* map = save_live_registers(sasm);
922
923 __ mov(R1, R0);
924 __ add(R3, SP, arg1_offset);
925 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
926
927 oop_maps = new OopMapSet();
928 oop_maps->add_gc_map(call_offset, map);
929
930 // MacroAssembler::StoreStore useless (included in the runtime exit path)
931
932 restore_live_registers_except_R0(sasm);
933 }
934 break;
935
936 case register_finalizer_id:
937 {
938 __ set_info("register_finalizer", dont_gc_arguments);
939
940 // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
941 __ load_klass(Rtemp, R0);
942 __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
943
944 #ifdef AARCH64
945 Label L;
946 __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
947 __ ret();
948 __ bind(L);
949 #else
950 __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
951 __ bx(LR, eq);
952 #endif // AARCH64
953
954 // Call VM
955 OopMap* map = save_live_registers(sasm);
956 oop_maps = new OopMapSet();
957 int call_offset = __ call_RT(noreg, noreg,
958 CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
959 oop_maps->add_gc_map(call_offset, map);
960 restore_live_registers(sasm);
961 }
962 break;
963
964 case throw_range_check_failed_id:
965 {
966 __ set_info("range_check_failed", dont_gc_arguments);
967 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
968 }
969 break;
970
971 case throw_index_exception_id:
972 {
973 __ set_info("index_range_check_failed", dont_gc_arguments);
974 #ifdef AARCH64
975 __ NOT_TESTED();
976 #endif
977 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
978 }
979 break;
980
981 case throw_div0_exception_id:
982 {
983 __ set_info("throw_div0_exception", dont_gc_arguments);
984 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
985 }
986 break;
987
988 case throw_null_pointer_exception_id:
989 {
990 __ set_info("throw_null_pointer_exception", dont_gc_arguments);
991 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
992 }
993 break;
994
995 case handle_exception_nofpu_id:
996 case handle_exception_id:
997 {
998 __ set_info("handle_exception", dont_gc_arguments);
999 oop_maps = generate_handle_exception(id, sasm);
1000 }
1001 break;
1002
1003 case handle_exception_from_callee_id:
1004 {
1005 __ set_info("handle_exception_from_callee", dont_gc_arguments);
1006 oop_maps = generate_handle_exception(id, sasm);
1007 }
1008 break;
1009
1010 case unwind_exception_id:
1011 {
1012 __ set_info("unwind_exception", dont_gc_arguments);
1013 generate_unwind_exception(sasm);
1014 }
1015 break;
1016
1017 case throw_array_store_exception_id:
1018 {
1019 __ set_info("throw_array_store_exception", dont_gc_arguments);
1020 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
1021 }
1022 break;
1023
1024 case throw_class_cast_exception_id:
1025 {
1026 __ set_info("throw_class_cast_exception", dont_gc_arguments);
1027 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
1028 }
1029 break;
1030
1031 case throw_incompatible_class_change_error_id:
1032 {
1033 __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
1034 #ifdef AARCH64
1035 __ NOT_TESTED();
1036 #endif
1037 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1038 }
1039 break;
1040
1041 case slow_subtype_check_id:
1042 {
1043 // (in) R0 - sub, destroyed,
1044 // (in) R1 - super, not changed
1045 // (out) R0 - result: 1 if check passed, 0 otherwise
1046 __ raw_push(R2, R3, LR);
1047
1048 // Load an array of secondary_supers
1049 __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
1050 // Length goes to R3
1051 __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
1052 __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
1053
1054 Label loop, miss;
1055 __ bind(loop);
1056 __ cbz(R3, miss);
1057 __ ldr(LR, Address(R2, wordSize, post_indexed));
1058 __ sub(R3, R3, 1);
1059 __ cmp(LR, R1);
1060 __ b(loop, ne);
1061
1062 // We get here if an equal cache entry is found
1063 __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
1064 __ mov(R0, 1);
1065 __ raw_pop_and_ret(R2, R3);
1066
1067 // A cache entry not found - return false
1068 __ bind(miss);
1069 __ mov(R0, 0);
1070 __ raw_pop_and_ret(R2, R3);
1071 }
1072 break;
1073
1074 case monitorenter_nofpu_id:
1075 save_fpu_registers = false;
1076 // fall through
1077 case monitorenter_id:
1078 {
1079 __ set_info("monitorenter", dont_gc_arguments);
1080 const Register obj = R1;
1081 const Register lock = R2;
1082 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1083 __ ldr(obj, Address(SP, arg1_offset));
1084 __ ldr(lock, Address(SP, arg2_offset));
1085 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
1086 oop_maps = new OopMapSet();
1087 oop_maps->add_gc_map(call_offset, map);
1088 restore_live_registers(sasm, save_fpu_registers);
1089 }
1090 break;
1091
1092 case monitorexit_nofpu_id:
1093 save_fpu_registers = false;
1094 // fall through
1095 case monitorexit_id:
1096 {
1097 __ set_info("monitorexit", dont_gc_arguments);
1098 const Register lock = R1;
1099 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1100 __ ldr(lock, Address(SP, arg1_offset));
1101 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
1102 oop_maps = new OopMapSet();
1103 oop_maps->add_gc_map(call_offset, map);
1104 restore_live_registers(sasm, save_fpu_registers);
1105 }
1106 break;
1107
1108 case deoptimize_id:
1109 {
1110 __ set_info("deoptimize", dont_gc_arguments);
1111 OopMap* oop_map = save_live_registers(sasm);
1112 const Register trap_request = R1;
1113 __ ldr(trap_request, Address(SP, arg1_offset));
1114 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
1115 oop_maps = new OopMapSet();
1116 oop_maps->add_gc_map(call_offset, oop_map);
1117 restore_live_registers_without_return(sasm);
1118 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1119 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1120 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
1121 }
1122 break;
1123
1124 case access_field_patching_id:
1125 {
1126 __ set_info("access_field_patching", dont_gc_arguments);
1127 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1128 }
1129 break;
1130
1131 case load_klass_patching_id:
1132 {
1133 __ set_info("load_klass_patching", dont_gc_arguments);
1134 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1135 }
1136 break;
1137
1138 case load_appendix_patching_id:
1139 {
1140 __ set_info("load_appendix_patching", dont_gc_arguments);
1141 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1142 }
1143 break;
1144
1145 case load_mirror_patching_id:
1146 {
1147 __ set_info("load_mirror_patching", dont_gc_arguments);
1148 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1149 }
1150 break;
1151
1152 case predicate_failed_trap_id:
1153 {
1154 __ set_info("predicate_failed_trap", dont_gc_arguments);
1155
1156 OopMap* oop_map = save_live_registers(sasm);
1157 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1158
1159 oop_maps = new OopMapSet();
1160 oop_maps->add_gc_map(call_offset, oop_map);
1161
1162 restore_live_registers_without_return(sasm);
1163
1164 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1165 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1166 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
1167 }
1168 break;
1169
1170 default:
1171 {
1172 __ set_info("unimplemented entry", dont_gc_arguments);
1173 STOP("unimplemented entry");
1174 }
1175 break;
1176 }
1177 return oop_maps;
1178 }
1179
1180 #undef __
1181
1182 #ifdef __SOFTFP__
1183 const char *Runtime1::pd_name_for_address(address entry) {
1184
1185 #define FUNCTION_CASE(a, f) \
1186 if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f)) return #f
1187
1188 FUNCTION_CASE(entry, __aeabi_fadd_glibc);
1189 FUNCTION_CASE(entry, __aeabi_fmul);
1190 FUNCTION_CASE(entry, __aeabi_fsub_glibc);
1191 FUNCTION_CASE(entry, __aeabi_fdiv);
1192
1193 // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
1194 FUNCTION_CASE(entry, __aeabi_dadd_glibc);
1195 FUNCTION_CASE(entry, __aeabi_dmul);
1196 FUNCTION_CASE(entry, __aeabi_dsub_glibc);
1197 FUNCTION_CASE(entry, __aeabi_ddiv);
1198
1199 FUNCTION_CASE(entry, __aeabi_f2d);
1200 FUNCTION_CASE(entry, __aeabi_d2f);
1201 FUNCTION_CASE(entry, __aeabi_i2f);
1202 FUNCTION_CASE(entry, __aeabi_i2d);
1203 FUNCTION_CASE(entry, __aeabi_f2iz);
1204
1205 FUNCTION_CASE(entry, SharedRuntime::fcmpl);
1206 FUNCTION_CASE(entry, SharedRuntime::fcmpg);
1207 FUNCTION_CASE(entry, SharedRuntime::dcmpl);
1208 FUNCTION_CASE(entry, SharedRuntime::dcmpg);
1209
1210 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
1211 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
1212 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
1213 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
1214 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
1215 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
1216 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
1217 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
1218
1219 FUNCTION_CASE(entry, SharedRuntime::fneg);
1220 FUNCTION_CASE(entry, SharedRuntime::dneg);
1221
1222 FUNCTION_CASE(entry, __aeabi_fcmpeq);
1223 FUNCTION_CASE(entry, __aeabi_fcmplt);
1224 FUNCTION_CASE(entry, __aeabi_fcmple);
1225 FUNCTION_CASE(entry, __aeabi_fcmpge);
1226 FUNCTION_CASE(entry, __aeabi_fcmpgt);
1227
1228 FUNCTION_CASE(entry, __aeabi_dcmpeq);
1229 FUNCTION_CASE(entry, __aeabi_dcmplt);
1230 FUNCTION_CASE(entry, __aeabi_dcmple);
1231 FUNCTION_CASE(entry, __aeabi_dcmpge);
1232 FUNCTION_CASE(entry, __aeabi_dcmpgt);
1233 #undef FUNCTION_CASE
1234 return "";
1235 }
1236 #else // __SOFTFP__
1237 const char *Runtime1::pd_name_for_address(address entry) {
1238 return "<unknown function>";
1239 }
1240 #endif // __SOFTFP__