1 /*
   2  * Copyright (c) 2013, Red Hat Inc.
   3  * Copyright (c) 2000, 2010, Oracle and/or its affiliates.
   4  * All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
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  25  */
  26 
  27 #ifndef CPU_AARCH64_VM_C1_DEFS_AARCH64_HPP
  28 #define CPU_AARCH64_VM_C1_DEFS_AARCH64_HPP
  29 
  30 // native word offsets from memory address (little endian)
  31 enum {
  32   pd_lo_word_offset_in_bytes = 0,
  33   pd_hi_word_offset_in_bytes = BytesPerWord
  34 };
  35 
  36 // explicit rounding operations are required to implement the strictFP mode
  37 enum {
  38   pd_strict_fp_requires_explicit_rounding = false
  39 };
  40 
  41 // FIXME: There are no callee-saved
  42 
  43 // registers
  44 enum {
  45   pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers,       // number of registers used during code emission
  46   pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers,  // number of registers used during code emission
  47 
  48   pd_nof_caller_save_cpu_regs_frame_map = 19 - 2,  // number of registers killed by calls
  49   pd_nof_caller_save_fpu_regs_frame_map = 32,  // number of registers killed by calls
  50 
  51   pd_first_callee_saved_reg = 19 - 2,
  52   pd_last_callee_saved_reg = 26 - 2,
  53 
  54   pd_last_allocatable_cpu_reg = 16,
  55 
  56   pd_nof_cpu_regs_reg_alloc
  57     = pd_last_allocatable_cpu_reg + 1,  // number of registers that are visible to register allocator
  58   pd_nof_fpu_regs_reg_alloc = 8,  // number of registers that are visible to register allocator
  59 
  60   pd_nof_cpu_regs_linearscan = 32, // number of registers visible to linear scan
  61   pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan
  62   pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these 
  63   pd_first_cpu_reg = 0,
  64   pd_last_cpu_reg = 16,
  65   pd_first_byte_reg = 0,
  66   pd_last_byte_reg = 16,
  67   pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
  68   pd_last_fpu_reg =  pd_first_fpu_reg + 31,
  69 
  70   pd_first_callee_saved_fpu_reg = 8 + pd_first_fpu_reg,
  71   pd_last_callee_saved_fpu_reg = 15 + pd_first_fpu_reg,
  72 };
  73 
  74 
  75 // Encoding of float value in debug info.  This is true on x86 where
  76 // floats are extended to doubles when stored in the stack, false for
  77 // AArch64 where floats and doubles are stored in their native form.
  78 enum {
  79   pd_float_saved_as_double = false
  80 };
  81 
  82 #endif // CPU_AARCH64_VM_C1_DEFS_AARCH64_HPP