1 /* 2 * Copyright (c) 2013, Red Hat Inc. 3 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. 4 * All rights reserved. 5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 6 * 7 * This code is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 only, as 9 * published by the Free Software Foundation. 10 * 11 * This code is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 * version 2 for more details (a copy is included in the LICENSE file that 15 * accompanied this code). 16 * 17 * You should have received a copy of the GNU General Public License version 18 * 2 along with this work; if not, write to the Free Software Foundation, 19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 20 * 21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 22 * or visit www.oracle.com if you need additional information or have any 23 * questions. 24 * 25 */ 26 27 #ifndef CPU_AARCH64_VM_ICACHE_AARCH64_HPP 28 #define CPU_AARCH64_VM_ICACHE_AARCH64_HPP 29 30 // Interface for updating the instruction cache. Whenever the VM 31 // modifies code, part of the processor instruction cache potentially 32 // has to be flushed. 33 34 class ICache : public AbstractICache { 35 public: 36 static void initialize(); 37 static void invalidate_word(address addr) { 38 __clear_cache((char *)addr, (char *)(addr + 3)); 39 } 40 static void invalidate_range(address start, int nbytes) { 41 __clear_cache((char *)start, (char *)(start + nbytes)); 42 } 43 }; 44 45 #endif // CPU_AARCH64_VM_ICACHE_AARCH64_HPP