1 /*
   2  * Copyright (c) 2013, Red Hat Inc.
   3  * Copyright (c) 1997, 2012, Oracle and/or its affiliates.
   4  * All rights reserved.
   5  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   6  *
   7  * This code is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 only, as
   9  * published by the Free Software Foundation.
  10  *
  11  * This code is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * version 2 for more details (a copy is included in the LICENSE file that
  15  * accompanied this code).
  16  *
  17  * You should have received a copy of the GNU General Public License version
  18  * 2 along with this work; if not, write to the Free Software Foundation,
  19  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  20  *
  21  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  22  * or visit www.oracle.com if you need additional information or have any
  23  * questions.
  24  *
  25  */
  26 
  27 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  29 
  30 #include "asm/assembler.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39 
  40  public:
  41   using Assembler::mov;
  42   using Assembler::movi;
  43 
  44  protected:
  45 
  46   // Support for VM calls
  47   //
  48   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  49   // may customize this version by overriding it for its purposes (e.g., to save/restore
  50   // additional registers when doing a VM call).
  51 #ifdef CC_INTERP
  52   // c++ interpreter never wants to use interp_masm version of call_VM
  53   #define VIRTUAL
  54 #else
  55   #define VIRTUAL virtual
  56 #endif
  57 
  58   VIRTUAL void call_VM_leaf_base(
  59     address entry_point,               // the entry point
  60     int     number_of_arguments,        // the number of arguments to pop after the call
  61     Label *retaddr = NULL
  62   );
  63 
  64   VIRTUAL void call_VM_leaf_base(
  65     address entry_point,               // the entry point
  66     int     number_of_arguments,        // the number of arguments to pop after the call
  67     Label &retaddr) {
  68     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  69   }
  70 
  71   // This is the base routine called by the different versions of call_VM. The interpreter
  72   // may customize this version by overriding it for its purposes (e.g., to save/restore
  73   // additional registers when doing a VM call).
  74   //
  75   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  76   // returns the register which contains the thread upon return. If a thread register has been
  77   // specified, the return value will correspond to that register. If no last_java_sp is specified
  78   // (noreg) than rsp will be used instead.
  79   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
  80     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  81     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  82     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  83     address  entry_point,              // the entry point
  84     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  85     bool     check_exceptions          // whether to check for pending exceptions after return
  86   );
  87 
  88   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  89   // The implementation is only non-empty for the InterpreterMacroAssembler,
  90   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  91   virtual void check_and_handle_popframe(Register java_thread);
  92   virtual void check_and_handle_earlyret(Register java_thread);
  93 
  94   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  95 
  96   // Maximum size of class area in Metaspace when compressed
  97   uint64_t use_XOR_for_compressed_class_base;
  98 
  99  public:
 100   MacroAssembler(CodeBuffer* code) : Assembler(code) {
 101     use_XOR_for_compressed_class_base
 102       = (operand_valid_for_logical_immediate(false /*is32*/,
 103                                              (uint64_t)Universe::narrow_klass_base())
 104          && ((uint64_t)Universe::narrow_klass_base()
 105              > (1u << log2_intptr(CompressedClassSpaceSize))));
 106   }
 107 
 108   // Biased locking support
 109   // lock_reg and obj_reg must be loaded up with the appropriate values.
 110   // swap_reg is killed.
 111   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 112   // Optional slow case is for implementations (interpreter and C1) which branch to
 113   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 114   // Returns offset of first potentially-faulting instruction for null
 115   // check info (currently consumed only by C1). If
 116   // swap_reg_contains_mark is true then returns -1 as it is assumed
 117   // the calling code has already passed any potential faults.
 118   int biased_locking_enter(Register lock_reg, Register obj_reg,
 119                            Register swap_reg, Register tmp_reg,
 120                            bool swap_reg_contains_mark,
 121                            Label& done, Label* slow_case = NULL,
 122                            BiasedLockingCounters* counters = NULL);
 123   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 124 
 125 
 126   // Helper functions for statistics gathering.
 127   // Unconditional atomic increment.
 128   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 129   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 130     lea(tmp1, counter_addr);
 131     atomic_incw(tmp1, tmp2, tmp3);
 132   }
 133   // Load Effective Address
 134   void lea(Register r, const Address &a) {
 135     InstructionMark im(this);
 136     code_section()->relocate(inst_mark(), a.rspec());
 137     a.lea(this, r);
 138   }
 139 
 140   void addmw(Address a, Register incr, Register scratch) {
 141     ldrw(scratch, a);
 142     addw(scratch, scratch, incr);
 143     strw(scratch, a);
 144   }
 145 
 146   // Add constant to memory word
 147   void addmw(Address a, int imm, Register scratch) {
 148     ldrw(scratch, a);
 149     if (imm > 0)
 150       addw(scratch, scratch, (unsigned)imm);
 151     else
 152       subw(scratch, scratch, (unsigned)-imm);
 153     strw(scratch, a);
 154   }
 155 
 156   // Frame creation and destruction shared between JITs.
 157   void build_frame(int framesize);
 158   void remove_frame(int framesize);
 159 
 160   virtual void _call_Unimplemented(address call_site) {
 161     mov(rscratch2, call_site);
 162   }
 163 
 164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 165 
 166   // aliases defined in AARCH64 spec
 167 
 168   template<class T>
 169   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 170   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 171 
 172   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 173   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 174 
 175   void cset(Register Rd, Assembler::Condition cond) {
 176     csinc(Rd, zr, zr, ~cond);
 177   }
 178   void csetw(Register Rd, Assembler::Condition cond) {
 179     csincw(Rd, zr, zr, ~cond);
 180   }
 181 
 182   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 183     csneg(Rd, Rn, Rn, ~cond);
 184   }
 185   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 186     csnegw(Rd, Rn, Rn, ~cond);
 187   }
 188 
 189   inline void movw(Register Rd, Register Rn) {
 190     if (Rd == sp || Rn == sp) {
 191       addw(Rd, Rn, 0U);
 192     } else {
 193       orrw(Rd, zr, Rn);
 194     }
 195   }
 196   inline void mov(Register Rd, Register Rn) {
 197     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 198     if (Rd == Rn) {
 199     } else if (Rd == sp || Rn == sp) {
 200       add(Rd, Rn, 0U);
 201     } else {
 202       orr(Rd, zr, Rn);
 203     }
 204   }
 205 
 206   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 207   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 208 
 209   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 210   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 211 
 212   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 213   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 214 
 215   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 216     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 217   }
 218   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 219     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 220   }
 221 
 222   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 223     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 224   }
 225   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 226     bfm(Rd, Rn, lsb , (lsb + width - 1));
 227   }
 228 
 229   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 230     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 231   }
 232   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 233     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 234   }
 235 
 236   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 237     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 238   }
 239   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 240     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 241   }
 242 
 243   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 244     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 245   }
 246   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 247     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 248   }
 249 
 250   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 251     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 252   }
 253   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 254     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 255   }
 256 
 257   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 258     sbfmw(Rd, Rn, imm, 31);
 259   }
 260 
 261   inline void asr(Register Rd, Register Rn, unsigned imm) {
 262     sbfm(Rd, Rn, imm, 63);
 263   }
 264 
 265   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 266     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 267   }
 268 
 269   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 270     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 271   }
 272 
 273   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 274     ubfmw(Rd, Rn, imm, 31);
 275   }
 276 
 277   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 278     ubfm(Rd, Rn, imm, 63);
 279   }
 280 
 281   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 282     extrw(Rd, Rn, Rn, imm);
 283   }
 284 
 285   inline void ror(Register Rd, Register Rn, unsigned imm) {
 286     extr(Rd, Rn, Rn, imm);
 287   }
 288 
 289   inline void sxtbw(Register Rd, Register Rn) {
 290     sbfmw(Rd, Rn, 0, 7);
 291   }
 292   inline void sxthw(Register Rd, Register Rn) {
 293     sbfmw(Rd, Rn, 0, 15);
 294   }
 295   inline void sxtb(Register Rd, Register Rn) {
 296     sbfm(Rd, Rn, 0, 7);
 297   }
 298   inline void sxth(Register Rd, Register Rn) {
 299     sbfm(Rd, Rn, 0, 15);
 300   }
 301   inline void sxtw(Register Rd, Register Rn) {
 302     sbfm(Rd, Rn, 0, 31);
 303   }
 304 
 305   inline void uxtbw(Register Rd, Register Rn) {
 306     ubfmw(Rd, Rn, 0, 7);
 307   }
 308   inline void uxthw(Register Rd, Register Rn) {
 309     ubfmw(Rd, Rn, 0, 15);
 310   }
 311   inline void uxtb(Register Rd, Register Rn) {
 312     ubfm(Rd, Rn, 0, 7);
 313   }
 314   inline void uxth(Register Rd, Register Rn) {
 315     ubfm(Rd, Rn, 0, 15);
 316   }
 317   inline void uxtw(Register Rd, Register Rn) {
 318     ubfm(Rd, Rn, 0, 31);
 319   }
 320 
 321   inline void cmnw(Register Rn, Register Rm) {
 322     addsw(zr, Rn, Rm);
 323   }
 324   inline void cmn(Register Rn, Register Rm) {
 325     adds(zr, Rn, Rm);
 326   }
 327 
 328   inline void cmpw(Register Rn, Register Rm) {
 329     subsw(zr, Rn, Rm);
 330   }
 331   inline void cmp(Register Rn, Register Rm) {
 332     subs(zr, Rn, Rm);
 333   }
 334 
 335   inline void negw(Register Rd, Register Rn) {
 336     subw(Rd, zr, Rn);
 337   }
 338 
 339   inline void neg(Register Rd, Register Rn) {
 340     sub(Rd, zr, Rn);
 341   }
 342 
 343   inline void negsw(Register Rd, Register Rn) {
 344     subsw(Rd, zr, Rn);
 345   }
 346 
 347   inline void negs(Register Rd, Register Rn) {
 348     subs(Rd, zr, Rn);
 349   }
 350 
 351   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 352     addsw(zr, Rn, Rm, kind, shift);
 353   }
 354   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 355     adds(zr, Rn, Rm, kind, shift);
 356   }
 357 
 358   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 359     subsw(zr, Rn, Rm, kind, shift);
 360   }
 361   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 362     subs(zr, Rn, Rm, kind, shift);
 363   }
 364 
 365   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 366     subw(Rd, zr, Rn, kind, shift);
 367   }
 368 
 369   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 370     sub(Rd, zr, Rn, kind, shift);
 371   }
 372 
 373   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 374     subsw(Rd, zr, Rn, kind, shift);
 375   }
 376 
 377   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 378     subs(Rd, zr, Rn, kind, shift);
 379   }
 380 
 381   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 382     msubw(Rd, Rn, Rm, zr);
 383   }
 384   inline void mneg(Register Rd, Register Rn, Register Rm) {
 385     msub(Rd, Rn, Rm, zr);
 386   }
 387 
 388   inline void mulw(Register Rd, Register Rn, Register Rm) {
 389     maddw(Rd, Rn, Rm, zr);
 390   }
 391   inline void mul(Register Rd, Register Rn, Register Rm) {
 392     madd(Rd, Rn, Rm, zr);
 393   }
 394 
 395   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 396     smsubl(Rd, Rn, Rm, zr);
 397   }
 398   inline void smull(Register Rd, Register Rn, Register Rm) {
 399     smaddl(Rd, Rn, Rm, zr);
 400   }
 401 
 402   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 403     umsubl(Rd, Rn, Rm, zr);
 404   }
 405   inline void umull(Register Rd, Register Rn, Register Rm) {
 406     umaddl(Rd, Rn, Rm, zr);
 407   }
 408 
 409 #define WRAP(INSN)                                                            \
 410   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 411     if ((VM_Version::cpu_cpuFeatures() & VM_Version::CPU_A53MAC) && Ra != zr) \
 412       nop();                                                                  \
 413     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 414   }
 415 
 416   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 417   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 418 #undef WRAP
 419 
 420   // macro assembly operations needed for aarch64
 421 
 422   // first two private routines for loading 32 bit or 64 bit constants
 423 private:
 424 
 425   void mov_immediate64(Register dst, u_int64_t imm64);
 426   void mov_immediate32(Register dst, u_int32_t imm32);
 427 
 428   int push(unsigned int bitset, Register stack);
 429   int pop(unsigned int bitset, Register stack);
 430 
 431   void mov(Register dst, Address a);
 432 
 433 public:
 434   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 435   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 436 
 437   // Push and pop everything that might be clobbered by a native
 438   // runtime call except rscratch1 and rscratch2.  (They are always
 439   // scratch, so we don't have to protect them.)  Only save the lower
 440   // 64 bits of each vector register.
 441   void push_call_clobbered_registers();
 442   void pop_call_clobbered_registers();
 443 
 444   // now mov instructions for loading absolute addresses and 32 or
 445   // 64 bit integers
 446 
 447   inline void mov(Register dst, address addr)
 448   {
 449     mov_immediate64(dst, (u_int64_t)addr);
 450   }
 451 
 452   inline void mov(Register dst, u_int64_t imm64)
 453   {
 454     mov_immediate64(dst, imm64);
 455   }
 456 
 457   inline void movw(Register dst, u_int32_t imm32)
 458   {
 459     mov_immediate32(dst, imm32);
 460   }
 461 
 462   inline void mov(Register dst, long l)
 463   {
 464     mov(dst, (u_int64_t)l);
 465   }
 466 
 467   inline void mov(Register dst, int i)
 468   {
 469     mov(dst, (long)i);
 470   }
 471 
 472   void mov(Register dst, RegisterOrConstant src) {
 473     if (src.is_register())
 474       mov(dst, src.as_register());
 475     else
 476       mov(dst, src.as_constant());
 477   }
 478 
 479   void movptr(Register r, uintptr_t imm64);
 480 
 481   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 482 
 483   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 484     orr(Vd, T, Vn, Vn);
 485   }
 486 
 487 public:
 488 
 489   // Generalized Test Bit And Branch, including a "far" variety which
 490   // spans more than 32KiB.
 491   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 492     assert(cond == EQ || cond == NE, "must be");
 493 
 494     if (far)
 495       cond = ~cond;
 496 
 497     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 498     if (cond == Assembler::EQ)
 499       branch = &Assembler::tbz;
 500     else
 501       branch = &Assembler::tbnz;
 502 
 503     if (far) {
 504       Label L;
 505       (this->*branch)(Rt, bitpos, L);
 506       b(dest);
 507       bind(L);
 508     } else {
 509       (this->*branch)(Rt, bitpos, dest);
 510     }
 511   }
 512 
 513   // macro instructions for accessing and updating floating point
 514   // status register
 515   //
 516   // FPSR : op1 == 011
 517   //        CRn == 0100
 518   //        CRm == 0100
 519   //        op2 == 001
 520 
 521   inline void get_fpsr(Register reg)
 522   {
 523     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 524   }
 525 
 526   inline void set_fpsr(Register reg)
 527   {
 528     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 529   }
 530 
 531   inline void clear_fpsr()
 532   {
 533     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 534   }
 535 
 536   // DCZID_EL0: op1 == 011
 537   //            CRn == 0000
 538   //            CRm == 0000
 539   //            op2 == 111
 540   inline void get_dczid_el0(Register reg)
 541   {
 542     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 543   }
 544 
 545   // CTR_EL0:   op1 == 011
 546   //            CRn == 0000
 547   //            CRm == 0000
 548   //            op2 == 001
 549   inline void get_ctr_el0(Register reg)
 550   {
 551     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 552   }
 553 
 554   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 555   int corrected_idivl(Register result, Register ra, Register rb,
 556                       bool want_remainder, Register tmp = rscratch1);
 557   int corrected_idivq(Register result, Register ra, Register rb,
 558                       bool want_remainder, Register tmp = rscratch1);
 559 
 560   // Support for NULL-checks
 561   //
 562   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 563   // If the accessed location is M[reg + offset] and the offset is known, provide the
 564   // offset. No explicit code generation is needed if the offset is within a certain
 565   // range (0 <= offset <= page_size).
 566 
 567   virtual void null_check(Register reg, int offset = -1);
 568   static bool needs_explicit_null_check(intptr_t offset);
 569 
 570   static address target_addr_for_insn(address insn_addr, unsigned insn);
 571   static address target_addr_for_insn(address insn_addr) {
 572     unsigned insn = *(unsigned*)insn_addr;
 573     return target_addr_for_insn(insn_addr, insn);
 574   }
 575   
 576   // Required platform-specific helpers for Label::patch_instructions.
 577   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 578   static int pd_patch_instruction_size(address branch, address target);
 579   static void pd_patch_instruction(address branch, address target) {
 580     pd_patch_instruction_size(branch, target);
 581   }
 582   static address pd_call_destination(address branch) {
 583     return target_addr_for_insn(branch);
 584   }
 585 #ifndef PRODUCT
 586   static void pd_print_patched_instruction(address branch);
 587 #endif
 588 
 589   static int patch_oop(address insn_addr, address o);
 590 
 591   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 592 
 593   // The following 4 methods return the offset of the appropriate move instruction
 594 
 595   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 596   int load_unsigned_byte(Register dst, Address src);
 597   int load_unsigned_short(Register dst, Address src);
 598 
 599   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 600   int load_signed_byte(Register dst, Address src);
 601   int load_signed_short(Register dst, Address src);
 602 
 603   int load_signed_byte32(Register dst, Address src);
 604   int load_signed_short32(Register dst, Address src);
 605 
 606   // Support for sign-extension (hi:lo = extend_sign(lo))
 607   void extend_sign(Register hi, Register lo);
 608 
 609   // Load and store values by size and signed-ness
 610   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 611   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 612 
 613   // Support for inc/dec with optimal instruction selection depending on value
 614 
 615   // x86_64 aliases an unqualified register/address increment and
 616   // decrement to call incrementq and decrementq but also supports
 617   // explicitly sized calls to incrementq/decrementq or
 618   // incrementl/decrementl
 619 
 620   // for aarch64 the proper convention would be to use
 621   // increment/decrement for 64 bit operatons and
 622   // incrementw/decrementw for 32 bit operations. so when porting
 623   // x86_64 code we can leave calls to increment/decrement as is,
 624   // replace incrementq/decrementq with increment/decrement and
 625   // replace incrementl/decrementl with incrementw/decrementw.
 626 
 627   // n.b. increment/decrement calls with an Address destination will
 628   // need to use a scratch register to load the value to be
 629   // incremented. increment/decrement calls which add or subtract a
 630   // constant value greater than 2^12 will need to use a 2nd scratch
 631   // register to hold the constant. so, a register increment/decrement
 632   // may trash rscratch2 and an address increment/decrement trash
 633   // rscratch and rscratch2
 634 
 635   void decrementw(Address dst, int value = 1);
 636   void decrementw(Register reg, int value = 1);
 637 
 638   void decrement(Register reg, int value = 1);
 639   void decrement(Address dst, int value = 1);
 640 
 641   void incrementw(Address dst, int value = 1);
 642   void incrementw(Register reg, int value = 1);
 643 
 644   void increment(Register reg, int value = 1);
 645   void increment(Address dst, int value = 1);
 646 
 647 
 648   // Alignment
 649   void align(int modulus);
 650 
 651   // Stack frame creation/removal
 652   void enter()
 653   {
 654     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 655     mov(rfp, sp);
 656   }
 657   void leave()
 658   {
 659     mov(sp, rfp);
 660     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 661   }
 662 
 663   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 664   // The pointer will be loaded into the thread register.
 665   void get_thread(Register thread);
 666 
 667 
 668   // Support for VM calls
 669   //
 670   // It is imperative that all calls into the VM are handled via the call_VM macros.
 671   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 672   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 673 
 674 
 675   void call_VM(Register oop_result,
 676                address entry_point,
 677                bool check_exceptions = true);
 678   void call_VM(Register oop_result,
 679                address entry_point,
 680                Register arg_1,
 681                bool check_exceptions = true);
 682   void call_VM(Register oop_result,
 683                address entry_point,
 684                Register arg_1, Register arg_2,
 685                bool check_exceptions = true);
 686   void call_VM(Register oop_result,
 687                address entry_point,
 688                Register arg_1, Register arg_2, Register arg_3,
 689                bool check_exceptions = true);
 690 
 691   // Overloadings with last_Java_sp
 692   void call_VM(Register oop_result,
 693                Register last_java_sp,
 694                address entry_point,
 695                int number_of_arguments = 0,
 696                bool check_exceptions = true);
 697   void call_VM(Register oop_result,
 698                Register last_java_sp,
 699                address entry_point,
 700                Register arg_1, bool
 701                check_exceptions = true);
 702   void call_VM(Register oop_result,
 703                Register last_java_sp,
 704                address entry_point,
 705                Register arg_1, Register arg_2,
 706                bool check_exceptions = true);
 707   void call_VM(Register oop_result,
 708                Register last_java_sp,
 709                address entry_point,
 710                Register arg_1, Register arg_2, Register arg_3,
 711                bool check_exceptions = true);
 712 
 713   void get_vm_result  (Register oop_result, Register thread);
 714   void get_vm_result_2(Register metadata_result, Register thread);
 715 
 716   // These always tightly bind to MacroAssembler::call_VM_base
 717   // bypassing the virtual implementation
 718   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 719   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 720   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 721   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 722   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 723 
 724   void call_VM_leaf(address entry_point,
 725                     int number_of_arguments = 0);
 726   void call_VM_leaf(address entry_point,
 727                     Register arg_1);
 728   void call_VM_leaf(address entry_point,
 729                     Register arg_1, Register arg_2);
 730   void call_VM_leaf(address entry_point,
 731                     Register arg_1, Register arg_2, Register arg_3);
 732 
 733   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 734   // bypassing the virtual implementation
 735   void super_call_VM_leaf(address entry_point);
 736   void super_call_VM_leaf(address entry_point, Register arg_1);
 737   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 738   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 739   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 740 
 741   // last Java Frame (fills frame anchor)
 742   void set_last_Java_frame(Register last_java_sp,
 743                            Register last_java_fp,
 744                            address last_java_pc,
 745                            Register scratch);
 746 
 747   void set_last_Java_frame(Register last_java_sp,
 748                            Register last_java_fp,
 749                            Label &last_java_pc,
 750                            Register scratch);
 751 
 752   void set_last_Java_frame(Register last_java_sp,
 753                            Register last_java_fp,
 754                            Register last_java_pc,
 755                            Register scratch);
 756 
 757   void reset_last_Java_frame(Register thread);
 758 
 759   // thread in the default location (rthread)
 760   void reset_last_Java_frame(bool clear_fp);
 761 
 762   // Stores
 763   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 764   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 765 
 766 #if INCLUDE_ALL_GCS
 767 
 768   void g1_write_barrier_pre(Register obj,
 769                             Register pre_val,
 770                             Register thread,
 771                             Register tmp,
 772                             bool tosca_live,
 773                             bool expand_call);
 774 
 775   void g1_write_barrier_post(Register store_addr,
 776                              Register new_val,
 777                              Register thread,
 778                              Register tmp,
 779                              Register tmp2);
 780 
 781 #endif // INCLUDE_ALL_GCS
 782 
 783   // split store_check(Register obj) to enhance instruction interleaving
 784   void store_check_part_1(Register obj);
 785   void store_check_part_2(Register obj);
 786 
 787   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 788   void c2bool(Register x);
 789 
 790   // oop manipulations
 791   void load_klass(Register dst, Register src);
 792   void store_klass(Register dst, Register src);
 793   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 794 
 795   void load_heap_oop(Register dst, Address src);
 796 
 797   void load_heap_oop_not_null(Register dst, Address src);
 798   void store_heap_oop(Address dst, Register src);
 799 
 800   // currently unimplemented
 801   // Used for storing NULL. All other oop constants should be
 802   // stored using routines that take a jobject.
 803   void store_heap_oop_null(Address dst);
 804 
 805   void load_prototype_header(Register dst, Register src);
 806 
 807   void store_klass_gap(Register dst, Register src);
 808 
 809   // This dummy is to prevent a call to store_heap_oop from
 810   // converting a zero (like NULL) into a Register by giving
 811   // the compiler two choices it can't resolve
 812 
 813   void store_heap_oop(Address dst, void* dummy);
 814 
 815   void encode_heap_oop(Register d, Register s);
 816   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 817   void decode_heap_oop(Register d, Register s);
 818   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 819   void encode_heap_oop_not_null(Register r);
 820   void decode_heap_oop_not_null(Register r);
 821   void encode_heap_oop_not_null(Register dst, Register src);
 822   void decode_heap_oop_not_null(Register dst, Register src);
 823 
 824   void set_narrow_oop(Register dst, jobject obj);
 825 
 826   void encode_klass_not_null(Register r);
 827   void decode_klass_not_null(Register r);
 828   void encode_klass_not_null(Register dst, Register src);
 829   void decode_klass_not_null(Register dst, Register src);
 830 
 831   void set_narrow_klass(Register dst, Klass* k);
 832 
 833   // if heap base register is used - reinit it with the correct value
 834   void reinit_heapbase();
 835 
 836   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 837 
 838   void push_CPU_state(bool save_vectors = false);
 839   void pop_CPU_state(bool restore_vectors = false) ;
 840 
 841   // Round up to a power of two
 842   void round_to(Register reg, int modulus);
 843 
 844   // allocation
 845   void eden_allocate(
 846     Register obj,                      // result: pointer to object after successful allocation
 847     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 848     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 849     Register t1,                       // temp register
 850     Label&   slow_case                 // continuation point if fast allocation fails
 851   );
 852   void tlab_allocate(
 853     Register obj,                      // result: pointer to object after successful allocation
 854     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 855     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 856     Register t1,                       // temp register
 857     Register t2,                       // temp register
 858     Label&   slow_case                 // continuation point if fast allocation fails
 859   );
 860   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 861   void verify_tlab();
 862 
 863   void incr_allocated_bytes(Register thread,
 864                             Register var_size_in_bytes, int con_size_in_bytes,
 865                             Register t1 = noreg);
 866 
 867   // interface method calling
 868   void lookup_interface_method(Register recv_klass,
 869                                Register intf_klass,
 870                                RegisterOrConstant itable_index,
 871                                Register method_result,
 872                                Register scan_temp,
 873                                Label& no_such_interface,
 874                                bool return_method = true);
 875 
 876   // virtual method calling
 877   // n.b. x86 allows RegisterOrConstant for vtable_index
 878   void lookup_virtual_method(Register recv_klass,
 879                              RegisterOrConstant vtable_index,
 880                              Register method_result);
 881 
 882   // Test sub_klass against super_klass, with fast and slow paths.
 883 
 884   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 885   // One of the three labels can be NULL, meaning take the fall-through.
 886   // If super_check_offset is -1, the value is loaded up from super_klass.
 887   // No registers are killed, except temp_reg.
 888   void check_klass_subtype_fast_path(Register sub_klass,
 889                                      Register super_klass,
 890                                      Register temp_reg,
 891                                      Label* L_success,
 892                                      Label* L_failure,
 893                                      Label* L_slow_path,
 894                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 895 
 896   // The rest of the type check; must be wired to a corresponding fast path.
 897   // It does not repeat the fast path logic, so don't use it standalone.
 898   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 899   // Updates the sub's secondary super cache as necessary.
 900   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 901   void check_klass_subtype_slow_path(Register sub_klass,
 902                                      Register super_klass,
 903                                      Register temp_reg,
 904                                      Register temp2_reg,
 905                                      Label* L_success,
 906                                      Label* L_failure,
 907                                      bool set_cond_codes = false);
 908 
 909   // Simplified, combined version, good for typical uses.
 910   // Falls through on failure.
 911   void check_klass_subtype(Register sub_klass,
 912                            Register super_klass,
 913                            Register temp_reg,
 914                            Label& L_success);
 915 
 916   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 917 
 918 
 919   // Debugging
 920 
 921   // only if +VerifyOops
 922   void verify_oop(Register reg, const char* s = "broken oop");
 923   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 924 
 925 // TODO: verify method and klass metadata (compare against vptr?)
 926   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 927   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 928 
 929 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 930 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 931 
 932   // only if +VerifyFPU
 933   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 934 
 935   // prints msg, dumps registers and stops execution
 936   void stop(const char* msg);
 937 
 938   // prints msg and continues
 939   void warn(const char* msg);
 940 
 941   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 942 
 943   void untested()                                { stop("untested"); }
 944 
 945   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 946 
 947   void should_not_reach_here()                   { stop("should not reach here"); }
 948 
 949   // Stack overflow checking
 950   void bang_stack_with_offset(int offset) {
 951     // stack grows down, caller passes positive offset
 952     assert(offset > 0, "must bang with negative offset");
 953     mov(rscratch2, -offset);
 954     str(zr, Address(sp, rscratch2));
 955   }
 956 
 957   // Writes to stack successive pages until offset reached to check for
 958   // stack overflow + shadow pages.  Also, clobbers tmp
 959   void bang_stack_size(Register size, Register tmp);
 960 
 961   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 962                                                 Register tmp,
 963                                                 int offset);
 964 
 965   // Support for serializing memory accesses between threads
 966   void serialize_memory(Register thread, Register tmp);
 967 
 968   // Arithmetics
 969 
 970   void addptr(const Address &dst, int32_t src);
 971   void cmpptr(Register src1, Address src2);
 972 
 973   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 974                   Label &suceed, Label *fail);
 975 
 976   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 977                   Label &suceed, Label *fail);
 978 
 979   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 980   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 981   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 982   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 983 
 984   void atomic_xchg(Register prev, Register newv, Register addr);
 985   void atomic_xchgw(Register prev, Register newv, Register addr);
 986   void atomic_xchgal(Register prev, Register newv, Register addr);
 987   void atomic_xchgalw(Register prev, Register newv, Register addr);
 988 
 989   void orptr(Address adr, RegisterOrConstant src) {
 990     ldr(rscratch2, adr);
 991     if (src.is_register())
 992       orr(rscratch2, rscratch2, src.as_register());
 993     else
 994       orr(rscratch2, rscratch2, src.as_constant());
 995     str(rscratch2, adr);
 996   }
 997 
 998   // A generic CAS; success or failure is in the EQ flag.
 999   void cmpxchg(Register addr, Register expected, Register new_val,
1000                enum operand_size size,
1001                bool acquire, bool release,
1002                Register tmp = rscratch1);
1003 
1004   // Calls
1005 
1006   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1007 
1008   static bool far_branches() {
1009     return ReservedCodeCacheSize > branch_range;
1010   }
1011 
1012   // Jumps that can reach anywhere in the code cache.
1013   // Trashes tmp.
1014   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1015   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1016 
1017   static int far_branch_size() {
1018     if (far_branches()) {
1019       return 3 * 4;  // adrp, add, br
1020     } else {
1021       return 4;
1022     }
1023   }
1024 
1025   // Emit the CompiledIC call idiom
1026   address ic_call(address entry);
1027 
1028 public:
1029 
1030   // Data
1031 
1032   void mov_metadata(Register dst, Metadata* obj);
1033   Address allocate_metadata_address(Metadata* obj);
1034   Address constant_oop_address(jobject obj);
1035 
1036   void movoop(Register dst, jobject obj, bool immediate = false);
1037 
1038   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1039   void kernel_crc32(Register crc, Register buf, Register len,
1040         Register table0, Register table1, Register table2, Register table3,
1041         Register tmp, Register tmp2, Register tmp3);
1042 
1043 #undef VIRTUAL
1044 
1045   // Stack push and pop individual 64 bit registers
1046   void push(Register src);
1047   void pop(Register dst);
1048 
1049   // push all registers onto the stack
1050   void pusha();
1051   void popa();
1052 
1053   void repne_scan(Register addr, Register value, Register count,
1054                   Register scratch);
1055   void repne_scanw(Register addr, Register value, Register count,
1056                    Register scratch);
1057 
1058   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1059   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1060 
1061   // If a constant does not fit in an immediate field, generate some
1062   // number of MOV instructions and then perform the operation
1063   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1064                              add_sub_imm_insn insn1,
1065                              add_sub_reg_insn insn2);
1066   // Seperate vsn which sets the flags
1067   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1068                              add_sub_imm_insn insn1,
1069                              add_sub_reg_insn insn2);
1070 
1071 #define WRAP(INSN)                                                      \
1072   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1073     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1074   }                                                                     \
1075                                                                         \
1076   void INSN(Register Rd, Register Rn, Register Rm,                      \
1077              enum shift_kind kind, unsigned shift = 0) {                \
1078     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1079   }                                                                     \
1080                                                                         \
1081   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1082     Assembler::INSN(Rd, Rn, Rm);                                        \
1083   }                                                                     \
1084                                                                         \
1085   void INSN(Register Rd, Register Rn, Register Rm,                      \
1086            ext::operation option, int amount = 0) {                     \
1087     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1088   }
1089 
1090   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1091 
1092 #undef WRAP
1093 #define WRAP(INSN)                                                      \
1094   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1095     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1096   }                                                                     \
1097                                                                         \
1098   void INSN(Register Rd, Register Rn, Register Rm,                      \
1099              enum shift_kind kind, unsigned shift = 0) {                \
1100     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1101   }                                                                     \
1102                                                                         \
1103   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1104     Assembler::INSN(Rd, Rn, Rm);                                        \
1105   }                                                                     \
1106                                                                         \
1107   void INSN(Register Rd, Register Rn, Register Rm,                      \
1108            ext::operation option, int amount = 0) {                     \
1109     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1110   }
1111 
1112   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1113 
1114   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1115   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1116   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1117   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1118 
1119   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1120 
1121   void tableswitch(Register index, jint lowbound, jint highbound,
1122                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1123     adr(rscratch1, jumptable);
1124     subsw(rscratch2, index, lowbound);
1125     subsw(zr, rscratch2, highbound - lowbound);
1126     br(Assembler::HS, jumptable_end);
1127     add(rscratch1, rscratch1, rscratch2,
1128         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1129     br(rscratch1);
1130   }
1131 
1132   // Form an address from base + offset in Rd.  Rd may or may not
1133   // actually be used: you must use the Address that is returned.  It
1134   // is up to you to ensure that the shift provided matches the size
1135   // of your data.
1136   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1137 
1138   // Return true iff an address is within the 48-bit AArch64 address
1139   // space.
1140   bool is_valid_AArch64_address(address a) {
1141     return ((uint64_t)a >> 48) == 0;
1142   }
1143 
1144   // Load the base of the cardtable byte map into reg.
1145   void load_byte_map_base(Register reg);
1146 
1147   // Prolog generator routines to support switch between x86 code and
1148   // generated ARM code
1149 
1150   // routine to generate an x86 prolog for a stub function which
1151   // bootstraps into the generated ARM code which directly follows the
1152   // stub
1153   //
1154 
1155   public:
1156 
1157   void ldr_constant(Register dest, const Address &const_addr) {
1158     if (NearCpool) {
1159       ldr(dest, const_addr);
1160     } else {
1161       unsigned long offset;
1162       adrp(dest, InternalAddress(const_addr.target()), offset);
1163       ldr(dest, Address(dest, offset));
1164     }
1165   }
1166 
1167   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1168   address read_polling_page(Register r, relocInfo::relocType rtype);
1169 
1170   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1171   void update_byte_crc32(Register crc, Register val, Register table);
1172   void update_word_crc32(Register crc, Register v, Register tmp,
1173         Register table0, Register table1, Register table2, Register table3,
1174         bool upper = false);
1175 
1176   void string_compare(Register str1, Register str2,
1177                       Register cnt1, Register cnt2, Register result,
1178                       Register tmp1);
1179   void string_equals(Register str1, Register str2,
1180                      Register cnt, Register result,
1181                      Register tmp1);
1182   void char_arrays_equals(Register ary1, Register ary2,
1183                           Register result, Register tmp1);
1184   void fill_words(Register base, Register cnt, Register value);
1185   void zero_words(Register base, u_int64_t cnt);
1186   void zero_words(Register base, Register cnt);
1187   void block_zero(Register base, Register cnt, bool is_large = false);
1188 
1189   void encode_iso_array(Register src, Register dst,
1190                         Register len, Register result,
1191                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1192                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1193   void string_indexof(Register str1, Register str2,
1194                       Register cnt1, Register cnt2,
1195                       Register tmp1, Register tmp2,
1196                       Register tmp3, Register tmp4,
1197                       int int_cnt1, Register result);
1198 private:
1199   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1200                        Register src1, Register src2);
1201   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1202     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1203   }
1204   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1205                              Register y, Register y_idx, Register z,
1206                              Register carry, Register product,
1207                              Register idx, Register kdx);
1208   void multiply_128_x_128_loop(Register y, Register z,
1209                                Register carry, Register carry2,
1210                                Register idx, Register jdx,
1211                                Register yz_idx1, Register yz_idx2,
1212                                Register tmp, Register tmp3, Register tmp4,
1213                                Register tmp7, Register product_hi);
1214 public:
1215   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1216                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1217                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1218   // ISB may be needed because of a safepoint
1219   void maybe_isb() { isb(); }
1220 
1221 private:
1222   // Return the effective address r + (r1 << ext) + offset.
1223   // Uses rscratch2.
1224   Address offsetted_address(Register r, Register r1, Address::extend ext,
1225                             int offset, int size);
1226 
1227 private:
1228   // Returns an address on the stack which is reachable with a ldr/str of size
1229   // Uses rscratch2 if the address is not directly reachable
1230   Address spill_address(int size, int offset, Register tmp=rscratch2);
1231 
1232 public:
1233   void spill(Register Rx, bool is64, int offset) {
1234     if (is64) {
1235       str(Rx, spill_address(8, offset));
1236     } else {
1237       strw(Rx, spill_address(4, offset));
1238     }
1239   }
1240   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1241     str(Vx, T, spill_address(1 << (int)T, offset));
1242   }
1243   void unspill(Register Rx, bool is64, int offset) {
1244     if (is64) {
1245       ldr(Rx, spill_address(8, offset));
1246     } else {
1247       ldrw(Rx, spill_address(4, offset));
1248     }
1249   }
1250   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1251     ldr(Vx, T, spill_address(1 << (int)T, offset));
1252   }
1253   void spill_copy128(int src_offset, int dst_offset,
1254                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1255     if (src_offset < 512 && (src_offset & 7) == 0 &&
1256         dst_offset < 512 && (dst_offset & 7) == 0) {
1257       ldp(tmp1, tmp2, Address(sp, src_offset));
1258       stp(tmp1, tmp2, Address(sp, dst_offset));
1259     } else {
1260       unspill(tmp1, true, src_offset);
1261       spill(tmp1, true, dst_offset);
1262       unspill(tmp1, true, src_offset+8);
1263       spill(tmp1, true, dst_offset+8);
1264     }
1265   }
1266 };
1267 
1268 #ifdef ASSERT
1269 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1270 #endif
1271 
1272 /**
1273  * class SkipIfEqual:
1274  *
1275  * Instantiating this class will result in assembly code being output that will
1276  * jump around any code emitted between the creation of the instance and it's
1277  * automatic destruction at the end of a scope block, depending on the value of
1278  * the flag passed to the constructor, which will be checked at run-time.
1279  */
1280 class SkipIfEqual {
1281  private:
1282   MacroAssembler* _masm;
1283   Label _label;
1284 
1285  public:
1286    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1287    ~SkipIfEqual();
1288 };
1289 
1290 struct tableswitch {
1291   Register _reg;
1292   int _insn_index; jint _first_key; jint _last_key;
1293   Label _after;
1294   Label _branches;
1295 };
1296 
1297 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP