1 /*
2 * Copyright (c) 2013, Red Hat Inc.
3 * Copyright (c) 1997, 2011, Oracle and/or its affiliates.
4 * All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
28 #define CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP
29
30 #include "asm/assembler.hpp"
31 #include "memory/allocation.hpp"
32 #include "runtime/icache.hpp"
33 #include "runtime/os.hpp"
34 #include "utilities/top.hpp"
35
36 // We have interfaces for the following instructions:
37 // - NativeInstruction
38 // - - NativeCall
39 // - - NativeMovConstReg
40 // - - NativeMovConstRegPatching
41 // - - NativeMovRegMem
42 // - - NativeMovRegMemPatching
43 // - - NativeJump
44 // - - NativeIllegalOpCode
45 // - - NativeGeneralJump
46 // - - NativeReturn
47 // - - NativeReturnX (return with argument)
48 // - - NativePushConst
49 // - - NativeTstRegMem
50
51 // The base class for different kinds of native instruction abstractions.
52 // Provides the primitive operations to manipulate code relative to this.
53
54 class NativeInstruction VALUE_OBJ_CLASS_SPEC {
55 friend class Relocation;
56 friend bool is_NativeCallTrampolineStub_at(address);
57 public:
58 enum { instruction_size = 4 };
59 inline bool is_nop();
60 bool is_dtrace_trap();
61 inline bool is_illegal();
62 inline bool is_return();
63 bool is_jump();
64 inline bool is_jump_or_nop();
65 inline bool is_cond_jump();
66 bool is_safepoint_poll();
67 inline bool is_mov_literal64();
68 bool is_movz();
69 bool is_movk();
70 bool is_sigill_zombie_not_entrant();
71
72 protected:
73 address addr_at(int offset) const { return address(this) + offset; }
74
75 s_char sbyte_at(int offset) const { return *(s_char*) addr_at(offset); }
76 u_char ubyte_at(int offset) const { return *(u_char*) addr_at(offset); }
77
78 jint int_at(int offset) const { return *(jint*) addr_at(offset); }
79 juint uint_at(int offset) const { return *(juint*) addr_at(offset); }
80
81 address ptr_at(int offset) const { return *(address*) addr_at(offset); }
82
83 oop oop_at (int offset) const { return *(oop*) addr_at(offset); }
84
85
86 void set_char_at(int offset, char c) { *addr_at(offset) = (u_char)c; }
87 void set_int_at(int offset, jint i) { *(jint*)addr_at(offset) = i; }
88 void set_uint_at(int offset, jint i) { *(juint*)addr_at(offset) = i; }
89 void set_ptr_at (int offset, address ptr) { *(address*) addr_at(offset) = ptr; }
90 void set_oop_at (int offset, oop o) { *(oop*) addr_at(offset) = o; }
91
92 public:
93
94 // unit test stuff
95 static void test() {} // override for testing
96
97 inline friend NativeInstruction* nativeInstruction_at(address address);
98
99 static bool is_adrp_at(address instr);
100 static bool is_ldr_literal_at(address instr);
101 static bool is_ldrw_to_zr(address instr);
102
103 static bool maybe_cpool_ref(address instr) {
104 return is_adrp_at(instr) || is_ldr_literal_at(instr);
105 }
106 };
107
108 inline NativeInstruction* nativeInstruction_at(address address) {
109 return (NativeInstruction*)address;
110 }
111
112 // The natural type of an AArch64 instruction is uint32_t
113 inline NativeInstruction* nativeInstruction_at(uint32_t *address) {
114 return (NativeInstruction*)address;
115 }
116
117 inline NativeCall* nativeCall_at(address address);
118 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
119 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
120
121 class NativeCall: public NativeInstruction {
122 public:
123 enum Aarch64_specific_constants {
124 instruction_size = 4,
125 instruction_offset = 0,
126 displacement_offset = 0,
127 return_address_offset = 4
128 };
129
130 enum { cache_line_size = BytesPerWord }; // conservative estimate!
131 address instruction_address() const { return addr_at(instruction_offset); }
132 address next_instruction_address() const { return addr_at(return_address_offset); }
133 int displacement() const { return (int_at(displacement_offset) << 6) >> 4; }
134 address displacement_address() const { return addr_at(displacement_offset); }
135 address return_address() const { return addr_at(return_address_offset); }
136 address destination() const;
137 void set_destination(address dest) {
138 int offset = dest - instruction_address();
139 unsigned int insn = 0b100101 << 26;
140 assert((offset & 3) == 0, "should be");
141 offset >>= 2;
142 offset &= (1 << 26) - 1; // mask off insn part
143 insn |= offset;
144 set_int_at(displacement_offset, insn);
145 }
146
147 void verify_alignment() { ; }
148 void verify();
149 void print();
150
151 // Creation
152 inline friend NativeCall* nativeCall_at(address address);
153 inline friend NativeCall* nativeCall_before(address return_address);
154
155 static bool is_call_at(address instr) {
156 const uint32_t insn = (*(uint32_t*)instr);
157 return (insn >> 26) == 0b100101;
158 }
159
160 static bool is_call_before(address return_address) {
161 return is_call_at(return_address - NativeCall::return_address_offset);
162 }
163
164 // MT-safe patching of a call instruction.
165 static void insert(address code_pos, address entry);
166
167 static void replace_mt_safe(address instr_addr, address code_buffer);
168
169 // Similar to replace_mt_safe, but just changes the destination. The
170 // important thing is that free-running threads are able to execute
171 // this call instruction at all times. If the call is an immediate BL
172 // instruction we can simply rely on atomicity of 32-bit writes to
173 // make sure other threads will see no intermediate states.
174
175 // We cannot rely on locks here, since the free-running threads must run at
176 // full speed.
177 //
178 // Used in the runtime linkage of calls; see class CompiledIC.
179 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
180
181 // The parameter assert_lock disables the assertion during code generation.
182 void set_destination_mt_safe(address dest, bool assert_lock = true);
183
184 address get_trampoline();
185 };
186
187 inline NativeCall* nativeCall_at(address address) {
188 NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
189 #ifdef ASSERT
190 call->verify();
191 #endif
192 return call;
193 }
194
195 inline NativeCall* nativeCall_before(address return_address) {
196 NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
197 #ifdef ASSERT
198 call->verify();
199 #endif
200 return call;
201 }
202
203 // An interface for accessing/manipulating native mov reg, imm instructions.
204 // (used to manipulate inlined 64-bit data calls, etc.)
205 class NativeMovConstReg: public NativeInstruction {
206 public:
207 enum Aarch64_specific_constants {
208 instruction_size = 3 * 4, // movz, movk, movk. See movptr().
209 instruction_offset = 0,
210 displacement_offset = 0,
211 };
212
213 address instruction_address() const { return addr_at(instruction_offset); }
214 address next_instruction_address() const {
215 if (nativeInstruction_at(instruction_address())->is_movz())
216 // Assume movz, movk, movk
217 return addr_at(instruction_size);
218 else if (is_adrp_at(instruction_address()))
219 return addr_at(2*4);
220 else if (is_ldr_literal_at(instruction_address()))
221 return(addr_at(4));
222 assert(false, "Unknown instruction in NativeMovConstReg");
223 return NULL;
224 }
225
226 intptr_t data() const;
227 void set_data(intptr_t x);
228
229 void flush() {
230 if (! maybe_cpool_ref(instruction_address())) {
231 ICache::invalidate_range(instruction_address(), instruction_size);
232 }
233 }
234
235 void verify();
236 void print();
237
238 // unit test stuff
239 static void test() {}
240
241 // Creation
242 inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
243 inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
244 };
245
246 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
247 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
248 #ifdef ASSERT
249 test->verify();
250 #endif
251 return test;
252 }
253
254 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
255 NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
256 #ifdef ASSERT
257 test->verify();
258 #endif
259 return test;
260 }
261
262 class NativeMovConstRegPatching: public NativeMovConstReg {
263 private:
264 friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
265 NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
266 #ifdef ASSERT
267 test->verify();
268 #endif
269 return test;
270 }
271 };
272
273 // An interface for accessing/manipulating native moves of the form:
274 // mov[b/w/l/q] [reg + offset], reg (instruction_code_reg2mem)
275 // mov[b/w/l/q] reg, [reg+offset] (instruction_code_mem2reg
276 // mov[s/z]x[w/b/q] [reg + offset], reg
277 // fld_s [reg+offset]
278 // fld_d [reg+offset]
279 // fstp_s [reg + offset]
280 // fstp_d [reg + offset]
281 // mov_literal64 scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
282 //
283 // Warning: These routines must be able to handle any instruction sequences
284 // that are generated as a result of the load/store byte,word,long
285 // macros. For example: The load_unsigned_byte instruction generates
286 // an xor reg,reg inst prior to generating the movb instruction. This
287 // class must skip the xor instruction.
288
289 class NativeMovRegMem: public NativeInstruction {
290 enum AArch64_specific_constants {
291 instruction_size = 4,
292 instruction_offset = 0,
293 data_offset = 0,
294 next_instruction_offset = 4
295 };
296
297 public:
298 // helper
299 int instruction_start() const;
300
301 address instruction_address() const;
302
303 address next_instruction_address() const;
304
305 int offset() const;
306
307 void set_offset(int x);
308
309 void add_offset_in_bytes(int add_offset) { set_offset ( ( offset() + add_offset ) ); }
310
311 void verify();
312 void print ();
313
314 // unit test stuff
315 static void test() {}
316
317 private:
318 inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
319 };
320
321 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
322 NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
323 #ifdef ASSERT
324 test->verify();
325 #endif
326 return test;
327 }
328
329 class NativeMovRegMemPatching: public NativeMovRegMem {
330 private:
331 friend NativeMovRegMemPatching* nativeMovRegMemPatching_at (address address) {Unimplemented(); return 0; }
332 };
333
334 // An interface for accessing/manipulating native leal instruction of form:
335 // leal reg, [reg + offset]
336
337 class NativeLoadAddress: public NativeMovRegMem {
338 static const bool has_rex = true;
339 static const int rex_size = 1;
340 public:
341
342 void verify();
343 void print ();
344
345 // unit test stuff
346 static void test() {}
347 };
348
349 class NativeJump: public NativeInstruction {
350 public:
351 enum AArch64_specific_constants {
352 instruction_size = 4,
353 instruction_offset = 0,
354 data_offset = 0,
355 next_instruction_offset = 4
356 };
357
358 address instruction_address() const { return addr_at(instruction_offset); }
359 address next_instruction_address() const { return addr_at(instruction_size); }
360 address jump_destination() const;
361 void set_jump_destination(address dest);
362
363 // Creation
364 inline friend NativeJump* nativeJump_at(address address);
365
366 void verify();
367
368 // Unit testing stuff
369 static void test() {}
370
371 // Insertion of native jump instruction
372 static void insert(address code_pos, address entry);
373 // MT-safe insertion of native jump at verified method entry
374 static void check_verified_entry_alignment(address entry, address verified_entry);
375 static void patch_verified_entry(address entry, address verified_entry, address dest);
376 };
377
378 inline NativeJump* nativeJump_at(address address) {
379 NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
380 #ifdef ASSERT
381 jump->verify();
382 #endif
383 return jump;
384 }
385
386 class NativeGeneralJump: public NativeJump {
387 public:
388 enum AArch64_specific_constants {
389 instruction_size = 4 * 4,
390 instruction_offset = 0,
391 data_offset = 0,
392 next_instruction_offset = 4 * 4
393 };
394 static void insert_unconditional(address code_pos, address entry);
395 static void replace_mt_safe(address instr_addr, address code_buffer);
396 static void verify();
397 };
398
399 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
400 NativeGeneralJump* jump = (NativeGeneralJump*)(address);
401 debug_only(jump->verify();)
402 return jump;
403 }
404
405 class NativePopReg : public NativeInstruction {
406 public:
407 // Insert a pop instruction
408 static void insert(address code_pos, Register reg);
409 };
410
411
412 class NativeIllegalInstruction: public NativeInstruction {
413 public:
414 // Insert illegal opcode as specific address
415 static void insert(address code_pos);
416 };
417
418 // return instruction that does not pop values of the stack
419 class NativeReturn: public NativeInstruction {
420 public:
421 };
422
423 // return instruction that does pop values of the stack
424 class NativeReturnX: public NativeInstruction {
425 public:
426 };
427
428 // Simple test vs memory
429 class NativeTstRegMem: public NativeInstruction {
430 public:
431 };
432
433 inline bool NativeInstruction::is_nop() {
434 uint32_t insn = *(uint32_t*)addr_at(0);
435 return insn == 0xd503201f;
436 }
437
438 inline bool NativeInstruction::is_jump() {
439 uint32_t insn = *(uint32_t*)addr_at(0);
440
441 if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
442 // Unconditional branch (immediate)
443 return true;
444 } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
445 // Conditional branch (immediate)
446 return true;
447 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
448 // Compare & branch (immediate)
449 return true;
450 } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
451 // Test & branch (immediate)
452 return true;
453 } else
454 return false;
455 }
456
457 inline bool NativeInstruction::is_jump_or_nop() {
458 return is_nop() || is_jump();
459 }
460
461 // Call trampoline stubs.
462 class NativeCallTrampolineStub : public NativeInstruction {
463 public:
464
465 enum AArch64_specific_constants {
466 instruction_size = 4 * 4,
467 instruction_offset = 0,
468 data_offset = 2 * 4,
469 next_instruction_offset = 4 * 4
470 };
471
472 address destination(nmethod *nm = NULL) const;
473 void set_destination(address new_destination);
474 ptrdiff_t destination_offset() const;
475 };
476
477 inline bool is_NativeCallTrampolineStub_at(address addr) {
478 // Ensure that the stub is exactly
479 // ldr xscratch1, L
480 // br xscratch1
481 // L:
482 uint32_t *i = (uint32_t *)addr;
483 return i[0] == 0x58000048 && i[1] == 0xd61f0100;
484 }
485
486 inline NativeCallTrampolineStub* nativeCallTrampolineStub_at(address addr) {
487 assert(is_NativeCallTrampolineStub_at(addr), "no call trampoline found");
488 return (NativeCallTrampolineStub*)addr;
489 }
490
491 #endif // CPU_AARCH64_VM_NATIVEINST_AARCH64_HPP