1 /*
2 * Copyright (c) 2013, Red Hat Inc.
3 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_aarch64.hpp"
33 #ifdef TARGET_OS_FAMILY_linux
34 # include "os_linux.inline.hpp"
35 #endif
36
37 #include <sys/auxv.h>
38 #include <asm/hwcap.h>
39
40 #ifndef HWCAP_AES
41 #define HWCAP_AES (1<<3)
42 #endif
43
44 #ifndef HWCAP_SHA1
45 #define HWCAP_SHA1 (1<<5)
46 #endif
47
48 #ifndef HWCAP_SHA2
49 #define HWCAP_SHA2 (1<<6)
50 #endif
51
52 #ifndef HWCAP_CRC32
53 #define HWCAP_CRC32 (1<<7)
54 #endif
55
56 #ifndef HWCAP_ATOMICS
57 #define HWCAP_ATOMICS (1<<8)
58 #endif
59
60 int VM_Version::_cpu;
61 int VM_Version::_model;
62 int VM_Version::_model2;
63 int VM_Version::_variant;
64 int VM_Version::_revision;
65 int VM_Version::_stepping;
66 int VM_Version::_cpuFeatures;
67 const char* VM_Version::_features_str = "";
68 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
69
70 static BufferBlob* stub_blob;
71 static const int stub_size = 550;
72
73 extern "C" {
74 typedef void (*getPsrInfo_stub_t)(void*);
75 }
76 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
77
78
79 class VM_Version_StubGenerator: public StubCodeGenerator {
80 public:
81
82 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
83
84 address generate_getPsrInfo() {
85 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
86 # define __ _masm->
87 address start = __ pc();
88
89 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
90
91 address entry = __ pc();
92
93 __ enter();
94
95 __ get_dczid_el0(rscratch1);
96 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
97
98 __ get_ctr_el0(rscratch1);
99 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
100
101 __ leave();
102 __ ret(lr);
103
104 # undef __
105
106 return start;
107 }
108 };
109
110
111 void VM_Version::get_processor_features() {
112 _supports_cx8 = true;
113 _supports_atomic_getset4 = true;
114 _supports_atomic_getadd4 = true;
115 _supports_atomic_getset8 = true;
116 _supports_atomic_getadd8 = true;
117
118 getPsrInfo_stub(&_psr_info);
119
120 int dcache_line = VM_Version::dcache_line_size();
121
122 // Limit AllocatePrefetchDistance so that it does not exceed the
123 // constraint in AllocatePrefetchDistanceConstraintFunc.
124 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
125 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
126
127 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
128 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
129 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
130 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
131 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
132 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
133
134 if (PrefetchCopyIntervalInBytes != -1 &&
135 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
136 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
137 PrefetchCopyIntervalInBytes &= ~7;
138 if (PrefetchCopyIntervalInBytes >= 32768)
139 PrefetchCopyIntervalInBytes = 32760;
140 }
141 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
142
143 unsigned long auxv = getauxval(AT_HWCAP);
144
145 char buf[512];
146
147 strcpy(buf, "simd");
148 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
149 if (auxv & HWCAP_AES) strcat(buf, ", aes");
150 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
151 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
152 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
153
154 _features_str = strdup(buf);
155 _cpuFeatures = auxv;
156
157 int cpu_lines = 0;
158 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
159 char buf[128], *p;
160 while (fgets(buf, sizeof (buf), f) != NULL) {
161 if ((p = strchr(buf, ':')) != NULL) {
162 long v = strtol(p+1, NULL, 0);
163 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
164 _cpu = v;
165 cpu_lines++;
166 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
167 _variant = v;
168 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
169 if (_model != v) _model2 = _model;
170 _model = v;
171 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
172 _revision = v;
173 }
174 }
175 }
176 fclose(f);
177 }
178
179 // Enable vendor specific features
180 if (_cpu == CPU_CAVIUM) {
181 if (_variant == 0) _cpuFeatures |= CPU_DMB_ATOMICS;
182 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
183 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
184 }
185 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
186 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
187 }
188 }
189 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _cpuFeatures |= CPU_A53MAC;
190 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _cpuFeatures |= CPU_STXR_PREFETCH;
191 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
192 // we assume the worst and assume we could be on a big little system and have
193 // undisclosed A53 cores which we could be swapped to at any stage
194 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _cpuFeatures |= CPU_A53MAC;
195
196 if (FLAG_IS_DEFAULT(UseCRC32)) {
197 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
198 }
199 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
200 warning("UseCRC32 specified, but not supported on this CPU");
201 }
202
203 if (auxv & HWCAP_ATOMICS) {
204 if (FLAG_IS_DEFAULT(UseLSE))
205 FLAG_SET_DEFAULT(UseLSE, true);
206 } else {
207 if (UseLSE) {
208 warning("UseLSE specified, but not supported on this CPU");
209 }
210 }
211
212 if (auxv & HWCAP_AES) {
213 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
214 UseAESIntrinsics =
215 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
216 if (UseAESIntrinsics && !UseAES) {
217 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
218 UseAES = true;
219 }
220 } else {
221 if (UseAES) {
222 warning("UseAES specified, but not supported on this CPU");
223 }
224 if (UseAESIntrinsics) {
225 warning("UseAESIntrinsics specified, but not supported on this CPU");
226 }
227 }
228
229 if (UseGHASHIntrinsics) {
230 warning("GHASH intrinsics are not available on this CPU");
231 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
232 }
233
234 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
235 UseCRC32Intrinsics = true;
236 }
237
238 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
239 if (FLAG_IS_DEFAULT(UseSHA)) {
240 FLAG_SET_DEFAULT(UseSHA, true);
241 }
242 } else if (UseSHA) {
243 warning("SHA instructions are not available on this CPU");
244 FLAG_SET_DEFAULT(UseSHA, false);
245 }
246
247 if (!UseSHA) {
248 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
249 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
250 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
251 } else {
252 if (auxv & HWCAP_SHA1) {
253 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
254 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
255 }
256 } else if (UseSHA1Intrinsics) {
257 warning("SHA1 instruction is not available on this CPU.");
258 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
259 }
260 if (auxv & HWCAP_SHA2) {
261 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
262 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
263 }
264 } else if (UseSHA256Intrinsics) {
265 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
266 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
267 }
268 if (UseSHA512Intrinsics) {
269 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
270 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
271 }
272 }
273
274 if (is_zva_enabled()) {
275 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
276 FLAG_SET_DEFAULT(UseBlockZeroing, true);
277 }
278 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
279 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
280 }
281 } else if (UseBlockZeroing) {
282 warning("DC ZVA is not available on this CPU");
283 FLAG_SET_DEFAULT(UseBlockZeroing, false);
284 }
285
286 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
287 UseMultiplyToLenIntrinsic = true;
288 }
289
290 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
291 UseBarriersForVolatile = (_cpuFeatures & CPU_DMB_ATOMICS) != 0;
292 }
293
294 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
295 UsePopCountInstruction = true;
296 }
297
298 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
299 UseMontgomeryMultiplyIntrinsic = true;
300 }
301 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
302 UseMontgomerySquareIntrinsic = true;
303 }
304
305 #ifdef COMPILER2
306 if (FLAG_IS_DEFAULT(OptoScheduling)) {
307 OptoScheduling = true;
308 }
309 #else
310 if (ReservedCodeCacheSize > 128*M) {
311 vm_exit_during_initialization("client compiler does not support ReservedCodeCacheSize > 128M");
312 }
313 #endif
314 }
315
316 void VM_Version::initialize() {
317 ResourceMark rm;
318
319 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
320 if (stub_blob == NULL) {
321 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
322 }
323
324 CodeBuffer c(stub_blob);
325 VM_Version_StubGenerator g(&c);
326 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
327 g.generate_getPsrInfo());
328
329 get_processor_features();
330 }