1 /* 2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_InstructionPrinter.hpp" 27 #include "c1/c1_LIR.hpp" 28 #include "c1/c1_LIRAssembler.hpp" 29 #include "c1/c1_ValueStack.hpp" 30 #include "ci/ciInstance.hpp" 31 #include "runtime/sharedRuntime.hpp" 32 33 Register LIR_OprDesc::as_register() const { 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); 35 } 36 37 Register LIR_OprDesc::as_register_lo() const { 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 39 } 40 41 Register LIR_OprDesc::as_register_hi() const { 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 43 } 44 45 #if defined(X86) 46 47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 48 return FrameMap::nr2xmmreg(xmm_regnr()); 49 } 50 51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); 54 } 55 56 #endif // X86 57 58 #if defined(SPARC) || defined(PPC) 59 60 FloatRegister LIR_OprDesc::as_float_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnr()); 62 } 63 64 FloatRegister LIR_OprDesc::as_double_reg() const { 65 return FrameMap::nr2floatreg(fpu_regnrHi()); 66 } 67 68 #endif 69 70 #ifdef ARM 71 72 FloatRegister LIR_OprDesc::as_float_reg() const { 73 return as_FloatRegister(fpu_regnr()); 74 } 75 76 FloatRegister LIR_OprDesc::as_double_reg() const { 77 return as_FloatRegister(fpu_regnrLo()); 78 } 79 80 #endif 81 82 83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 84 85 LIR_Opr LIR_OprFact::value_type(ValueType* type) { 86 ValueTag tag = type->tag(); 87 switch (tag) { 88 case metaDataTag : { 89 ClassConstant* c = type->as_ClassConstant(); 90 if (c != NULL && !c->value()->is_loaded()) { 91 return LIR_OprFact::metadataConst(NULL); 92 } else if (c != NULL) { 93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); 94 } else { 95 MethodConstant* m = type->as_MethodConstant(); 96 assert (m != NULL, "not a class or a method?"); 97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); 98 } 99 } 100 case objectTag : { 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 102 } 103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 109 } 110 } 111 112 113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 114 switch (type->tag()) { 115 case objectTag: return LIR_OprFact::oopConst(NULL); 116 case addressTag:return LIR_OprFact::addressConst(0); 117 case intTag: return LIR_OprFact::intConst(0); 118 case floatTag: return LIR_OprFact::floatConst(0.0); 119 case longTag: return LIR_OprFact::longConst(0); 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 122 } 123 return illegalOpr; 124 } 125 126 127 128 //--------------------------------------------------- 129 130 131 LIR_Address::Scale LIR_Address::scale(BasicType type) { 132 int elem_size = type2aelembytes(type); 133 switch (elem_size) { 134 case 1: return LIR_Address::times_1; 135 case 2: return LIR_Address::times_2; 136 case 4: return LIR_Address::times_4; 137 case 8: return LIR_Address::times_8; 138 } 139 ShouldNotReachHere(); 140 return LIR_Address::times_1; 141 } 142 143 144 #ifndef PRODUCT 145 void LIR_Address::verify0() const { 146 #if defined(SPARC) || defined(PPC) 147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 149 #endif 150 #ifdef _LP64 151 assert(base()->is_cpu_register(), "wrong base operand"); 152 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 153 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 154 "wrong type for addresses"); 155 #else 156 assert(base()->is_single_cpu(), "wrong base operand"); 157 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 158 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 159 "wrong type for addresses"); 160 #endif 161 } 162 #endif 163 164 165 //--------------------------------------------------- 166 167 char LIR_OprDesc::type_char(BasicType t) { 168 switch (t) { 169 case T_ARRAY: 170 t = T_OBJECT; 171 case T_BOOLEAN: 172 case T_CHAR: 173 case T_FLOAT: 174 case T_DOUBLE: 175 case T_BYTE: 176 case T_SHORT: 177 case T_INT: 178 case T_LONG: 179 case T_OBJECT: 180 case T_ADDRESS: 181 case T_VOID: 182 return ::type2char(t); 183 case T_METADATA: 184 return 'M'; 185 case T_ILLEGAL: 186 return '?'; 187 188 default: 189 ShouldNotReachHere(); 190 return '?'; 191 } 192 } 193 194 #ifndef PRODUCT 195 void LIR_OprDesc::validate_type() const { 196 197 #ifdef ASSERT 198 if (!is_pointer() && !is_illegal()) { 199 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 200 switch (as_BasicType(type_field())) { 201 case T_LONG: 202 assert((kindfield == cpu_register || kindfield == stack_value) && 203 size_field() == double_size, "must match"); 204 break; 205 case T_FLOAT: 206 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 207 assert((kindfield == fpu_register || kindfield == stack_value 208 ARM_ONLY(|| kindfield == cpu_register) 209 PPC_ONLY(|| kindfield == cpu_register) ) && 210 size_field() == single_size, "must match"); 211 break; 212 case T_DOUBLE: 213 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 214 assert((kindfield == fpu_register || kindfield == stack_value 215 ARM_ONLY(|| kindfield == cpu_register) 216 PPC_ONLY(|| kindfield == cpu_register) ) && 217 size_field() == double_size, "must match"); 218 break; 219 case T_BOOLEAN: 220 case T_CHAR: 221 case T_BYTE: 222 case T_SHORT: 223 case T_INT: 224 case T_ADDRESS: 225 case T_OBJECT: 226 case T_METADATA: 227 case T_ARRAY: 228 assert((kindfield == cpu_register || kindfield == stack_value) && 229 size_field() == single_size, "must match"); 230 break; 231 232 case T_ILLEGAL: 233 // XXX TKR also means unknown right now 234 // assert(is_illegal(), "must match"); 235 break; 236 237 default: 238 ShouldNotReachHere(); 239 } 240 } 241 #endif 242 243 } 244 #endif // PRODUCT 245 246 247 bool LIR_OprDesc::is_oop() const { 248 if (is_pointer()) { 249 return pointer()->is_oop_pointer(); 250 } else { 251 OprType t= type_field(); 252 assert(t != unknown_type, "not set"); 253 return t == object_type; 254 } 255 } 256 257 258 259 void LIR_Op2::verify() const { 260 #ifdef ASSERT 261 switch (code()) { 262 case lir_cmove: 263 case lir_xchg: 264 break; 265 266 default: 267 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 268 "can't produce oops from arith"); 269 } 270 271 if (TwoOperandLIRForm) { 272 switch (code()) { 273 case lir_add: 274 case lir_sub: 275 case lir_mul: 276 case lir_mul_strictfp: 277 case lir_div: 278 case lir_div_strictfp: 279 case lir_rem: 280 case lir_logic_and: 281 case lir_logic_or: 282 case lir_logic_xor: 283 case lir_shl: 284 case lir_shr: 285 assert(in_opr1() == result_opr(), "opr1 and result must match"); 286 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 287 break; 288 289 // special handling for lir_ushr because of write barriers 290 case lir_ushr: 291 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 292 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 293 break; 294 295 } 296 } 297 #endif 298 } 299 300 301 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 302 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 303 , _cond(cond) 304 , _type(type) 305 , _label(block->label()) 306 , _block(block) 307 , _ublock(NULL) 308 , _stub(NULL) { 309 } 310 311 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 312 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 313 , _cond(cond) 314 , _type(type) 315 , _label(stub->entry()) 316 , _block(NULL) 317 , _ublock(NULL) 318 , _stub(stub) { 319 } 320 321 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 322 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 323 , _cond(cond) 324 , _type(type) 325 , _label(block->label()) 326 , _block(block) 327 , _ublock(ublock) 328 , _stub(NULL) 329 { 330 } 331 332 void LIR_OpBranch::change_block(BlockBegin* b) { 333 assert(_block != NULL, "must have old block"); 334 assert(_block->label() == label(), "must be equal"); 335 336 _block = b; 337 _label = b->label(); 338 } 339 340 void LIR_OpBranch::change_ublock(BlockBegin* b) { 341 assert(_ublock != NULL, "must have old block"); 342 _ublock = b; 343 } 344 345 void LIR_OpBranch::negate_cond() { 346 switch (_cond) { 347 case lir_cond_equal: _cond = lir_cond_notEqual; break; 348 case lir_cond_notEqual: _cond = lir_cond_equal; break; 349 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 350 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 351 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 352 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 353 default: ShouldNotReachHere(); 354 } 355 } 356 357 358 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 359 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 360 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 361 CodeStub* stub) 362 363 : LIR_Op(code, result, NULL) 364 , _object(object) 365 , _array(LIR_OprFact::illegalOpr) 366 , _klass(klass) 367 , _tmp1(tmp1) 368 , _tmp2(tmp2) 369 , _tmp3(tmp3) 370 , _fast_check(fast_check) 371 , _stub(stub) 372 , _info_for_patch(info_for_patch) 373 , _info_for_exception(info_for_exception) 374 , _profiled_method(NULL) 375 , _profiled_bci(-1) 376 , _should_profile(false) 377 { 378 if (code == lir_checkcast) { 379 assert(info_for_exception != NULL, "checkcast throws exceptions"); 380 } else if (code == lir_instanceof) { 381 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 382 } else { 383 ShouldNotReachHere(); 384 } 385 } 386 387 388 389 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 390 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 391 , _object(object) 392 , _array(array) 393 , _klass(NULL) 394 , _tmp1(tmp1) 395 , _tmp2(tmp2) 396 , _tmp3(tmp3) 397 , _fast_check(false) 398 , _stub(NULL) 399 , _info_for_patch(NULL) 400 , _info_for_exception(info_for_exception) 401 , _profiled_method(NULL) 402 , _profiled_bci(-1) 403 , _should_profile(false) 404 { 405 if (code == lir_store_check) { 406 _stub = new ArrayStoreExceptionStub(object, info_for_exception); 407 assert(info_for_exception != NULL, "store_check throws exceptions"); 408 } else { 409 ShouldNotReachHere(); 410 } 411 } 412 413 414 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 415 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 416 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 417 , _tmp(tmp) 418 , _src(src) 419 , _src_pos(src_pos) 420 , _dst(dst) 421 , _dst_pos(dst_pos) 422 , _flags(flags) 423 , _expected_type(expected_type) 424 , _length(length) { 425 _stub = new ArrayCopyStub(this); 426 } 427 428 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) 429 : LIR_Op(lir_updatecrc32, res, NULL) 430 , _crc(crc) 431 , _val(val) { 432 } 433 434 //-------------------verify-------------------------- 435 436 void LIR_Op1::verify() const { 437 switch(code()) { 438 case lir_move: 439 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 440 break; 441 case lir_null_check: 442 assert(in_opr()->is_register(), "must be"); 443 break; 444 case lir_return: 445 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 446 break; 447 } 448 } 449 450 void LIR_OpRTCall::verify() const { 451 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 452 } 453 454 //-------------------visits-------------------------- 455 456 // complete rework of LIR instruction visitor. 457 // The virtual call for each instruction type is replaced by a big 458 // switch that adds the operands for each instruction 459 460 void LIR_OpVisitState::visit(LIR_Op* op) { 461 // copy information from the LIR_Op 462 reset(); 463 set_op(op); 464 465 switch (op->code()) { 466 467 // LIR_Op0 468 case lir_word_align: // result and info always invalid 469 case lir_backwardbranch_target: // result and info always invalid 470 case lir_build_frame: // result and info always invalid 471 case lir_fpop_raw: // result and info always invalid 472 case lir_24bit_FPU: // result and info always invalid 473 case lir_reset_FPU: // result and info always invalid 474 case lir_breakpoint: // result and info always invalid 475 case lir_membar: // result and info always invalid 476 case lir_membar_acquire: // result and info always invalid 477 case lir_membar_release: // result and info always invalid 478 case lir_membar_loadload: // result and info always invalid 479 case lir_membar_storestore: // result and info always invalid 480 case lir_membar_loadstore: // result and info always invalid 481 case lir_membar_storeload: // result and info always invalid 482 { 483 assert(op->as_Op0() != NULL, "must be"); 484 assert(op->_info == NULL, "info not used by this instruction"); 485 assert(op->_result->is_illegal(), "not used"); 486 break; 487 } 488 489 case lir_nop: // may have info, result always invalid 490 case lir_std_entry: // may have result, info always invalid 491 case lir_osr_entry: // may have result, info always invalid 492 case lir_get_thread: // may have result, info always invalid 493 { 494 assert(op->as_Op0() != NULL, "must be"); 495 if (op->_info != NULL) do_info(op->_info); 496 if (op->_result->is_valid()) do_output(op->_result); 497 break; 498 } 499 500 501 // LIR_OpLabel 502 case lir_label: // result and info always invalid 503 { 504 assert(op->as_OpLabel() != NULL, "must be"); 505 assert(op->_info == NULL, "info not used by this instruction"); 506 assert(op->_result->is_illegal(), "not used"); 507 break; 508 } 509 510 511 // LIR_Op1 512 case lir_fxch: // input always valid, result and info always invalid 513 case lir_fld: // input always valid, result and info always invalid 514 case lir_ffree: // input always valid, result and info always invalid 515 case lir_push: // input always valid, result and info always invalid 516 case lir_pop: // input always valid, result and info always invalid 517 case lir_return: // input always valid, result and info always invalid 518 case lir_leal: // input and result always valid, info always invalid 519 case lir_neg: // input and result always valid, info always invalid 520 case lir_monaddr: // input and result always valid, info always invalid 521 case lir_null_check: // input and info always valid, result always invalid 522 case lir_move: // input and result always valid, may have info 523 case lir_pack64: // input and result always valid 524 case lir_unpack64: // input and result always valid 525 case lir_prefetchr: // input always valid, result and info always invalid 526 case lir_prefetchw: // input always valid, result and info always invalid 527 { 528 assert(op->as_Op1() != NULL, "must be"); 529 LIR_Op1* op1 = (LIR_Op1*)op; 530 531 if (op1->_info) do_info(op1->_info); 532 if (op1->_opr->is_valid()) do_input(op1->_opr); 533 if (op1->_result->is_valid()) do_output(op1->_result); 534 535 break; 536 } 537 538 case lir_safepoint: 539 { 540 assert(op->as_Op1() != NULL, "must be"); 541 LIR_Op1* op1 = (LIR_Op1*)op; 542 543 assert(op1->_info != NULL, ""); do_info(op1->_info); 544 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 545 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 546 547 break; 548 } 549 550 // LIR_OpConvert; 551 case lir_convert: // input and result always valid, info always invalid 552 { 553 assert(op->as_OpConvert() != NULL, "must be"); 554 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 555 556 assert(opConvert->_info == NULL, "must be"); 557 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 558 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 559 #ifdef PPC 560 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 561 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 562 #endif 563 do_stub(opConvert->_stub); 564 565 break; 566 } 567 568 // LIR_OpBranch; 569 case lir_branch: // may have info, input and result register always invalid 570 case lir_cond_float_branch: // may have info, input and result register always invalid 571 { 572 assert(op->as_OpBranch() != NULL, "must be"); 573 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 574 575 if (opBranch->_info != NULL) do_info(opBranch->_info); 576 assert(opBranch->_result->is_illegal(), "not used"); 577 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 578 579 break; 580 } 581 582 583 // LIR_OpAllocObj 584 case lir_alloc_object: 585 { 586 assert(op->as_OpAllocObj() != NULL, "must be"); 587 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 588 589 if (opAllocObj->_info) do_info(opAllocObj->_info); 590 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 591 do_temp(opAllocObj->_opr); 592 } 593 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 594 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 595 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 596 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 597 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 598 do_stub(opAllocObj->_stub); 599 break; 600 } 601 602 603 // LIR_OpRoundFP; 604 case lir_roundfp: { 605 assert(op->as_OpRoundFP() != NULL, "must be"); 606 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 607 608 assert(op->_info == NULL, "info not used by this instruction"); 609 assert(opRoundFP->_tmp->is_illegal(), "not used"); 610 do_input(opRoundFP->_opr); 611 do_output(opRoundFP->_result); 612 613 break; 614 } 615 616 617 // LIR_Op2 618 case lir_cmp: 619 case lir_cmp_l2i: 620 case lir_ucmp_fd2i: 621 case lir_cmp_fd2i: 622 case lir_add: 623 case lir_sub: 624 case lir_mul: 625 case lir_div: 626 case lir_rem: 627 case lir_sqrt: 628 case lir_abs: 629 case lir_logic_and: 630 case lir_logic_or: 631 case lir_logic_xor: 632 case lir_shl: 633 case lir_shr: 634 case lir_ushr: 635 case lir_xadd: 636 case lir_xchg: 637 case lir_assert: 638 { 639 assert(op->as_Op2() != NULL, "must be"); 640 LIR_Op2* op2 = (LIR_Op2*)op; 641 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 642 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 643 644 if (op2->_info) do_info(op2->_info); 645 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 646 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 647 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 648 if (op2->_result->is_valid()) do_output(op2->_result); 649 if (op->code() == lir_xchg || op->code() == lir_xadd) { 650 // on ARM and PPC, return value is loaded first so could 651 // destroy inputs. On other platforms that implement those 652 // (x86, sparc), the extra constrainsts are harmless. 653 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 654 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 655 } 656 657 break; 658 } 659 660 // special handling for cmove: right input operand must not be equal 661 // to the result operand, otherwise the backend fails 662 case lir_cmove: 663 { 664 assert(op->as_Op2() != NULL, "must be"); 665 LIR_Op2* op2 = (LIR_Op2*)op; 666 667 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && 668 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 669 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 670 671 do_input(op2->_opr1); 672 do_input(op2->_opr2); 673 do_temp(op2->_opr2); 674 do_output(op2->_result); 675 676 break; 677 } 678 679 // vspecial handling for strict operations: register input operands 680 // as temp to guarantee that they do not overlap with other 681 // registers 682 case lir_mul_strictfp: 683 case lir_div_strictfp: 684 { 685 assert(op->as_Op2() != NULL, "must be"); 686 LIR_Op2* op2 = (LIR_Op2*)op; 687 688 assert(op2->_info == NULL, "not used"); 689 assert(op2->_opr1->is_valid(), "used"); 690 assert(op2->_opr2->is_valid(), "used"); 691 assert(op2->_result->is_valid(), "used"); 692 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 693 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 694 695 do_input(op2->_opr1); do_temp(op2->_opr1); 696 do_input(op2->_opr2); do_temp(op2->_opr2); 697 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 698 do_output(op2->_result); 699 700 break; 701 } 702 703 case lir_throw: { 704 assert(op->as_Op2() != NULL, "must be"); 705 LIR_Op2* op2 = (LIR_Op2*)op; 706 707 if (op2->_info) do_info(op2->_info); 708 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 709 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 710 assert(op2->_result->is_illegal(), "no result"); 711 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 712 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 713 714 break; 715 } 716 717 case lir_unwind: { 718 assert(op->as_Op1() != NULL, "must be"); 719 LIR_Op1* op1 = (LIR_Op1*)op; 720 721 assert(op1->_info == NULL, "no info"); 722 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 723 assert(op1->_result->is_illegal(), "no result"); 724 725 break; 726 } 727 728 729 case lir_tan: 730 case lir_sin: 731 case lir_cos: 732 case lir_log: 733 case lir_log10: 734 case lir_exp: { 735 assert(op->as_Op2() != NULL, "must be"); 736 LIR_Op2* op2 = (LIR_Op2*)op; 737 738 // On x86 tan/sin/cos need two temporary fpu stack slots and 739 // log/log10 need one so handle opr2 and tmp as temp inputs. 740 // Register input operand as temp to guarantee that it doesn't 741 // overlap with the input. 742 assert(op2->_info == NULL, "not used"); 743 assert(op2->_tmp5->is_illegal(), "not used"); 744 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); 745 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); 746 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); 747 assert(op2->_opr1->is_valid(), "used"); 748 do_input(op2->_opr1); do_temp(op2->_opr1); 749 750 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 751 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 752 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); 753 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); 754 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); 755 if (op2->_result->is_valid()) do_output(op2->_result); 756 757 break; 758 } 759 760 case lir_pow: { 761 assert(op->as_Op2() != NULL, "must be"); 762 LIR_Op2* op2 = (LIR_Op2*)op; 763 764 // On x86 pow needs two temporary fpu stack slots: tmp1 and 765 // tmp2. Register input operands as temps to guarantee that it 766 // doesn't overlap with the temporary slots. 767 assert(op2->_info == NULL, "not used"); 768 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); 769 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() 770 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); 771 assert(op2->_result->is_valid(), "used"); 772 773 do_input(op2->_opr1); do_temp(op2->_opr1); 774 do_input(op2->_opr2); do_temp(op2->_opr2); 775 do_temp(op2->_tmp1); 776 do_temp(op2->_tmp2); 777 do_temp(op2->_tmp3); 778 do_temp(op2->_tmp4); 779 do_temp(op2->_tmp5); 780 do_output(op2->_result); 781 782 break; 783 } 784 785 // LIR_Op3 786 case lir_idiv: 787 case lir_irem: { 788 assert(op->as_Op3() != NULL, "must be"); 789 LIR_Op3* op3= (LIR_Op3*)op; 790 791 if (op3->_info) do_info(op3->_info); 792 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 793 794 // second operand is input and temp, so ensure that second operand 795 // and third operand get not the same register 796 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 797 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 798 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 799 800 if (op3->_result->is_valid()) do_output(op3->_result); 801 802 break; 803 } 804 805 806 // LIR_OpJavaCall 807 case lir_static_call: 808 case lir_optvirtual_call: 809 case lir_icvirtual_call: 810 case lir_virtual_call: 811 case lir_dynamic_call: { 812 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 813 assert(opJavaCall != NULL, "must be"); 814 815 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 816 817 // only visit register parameters 818 int n = opJavaCall->_arguments->length(); 819 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { 820 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 821 do_input(*opJavaCall->_arguments->adr_at(i)); 822 } 823 } 824 825 if (opJavaCall->_info) do_info(opJavaCall->_info); 826 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr && 827 opJavaCall->is_method_handle_invoke()) { 828 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 829 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 830 } 831 do_call(); 832 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 833 834 break; 835 } 836 837 838 // LIR_OpRTCall 839 case lir_rtcall: { 840 assert(op->as_OpRTCall() != NULL, "must be"); 841 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 842 843 // only visit register parameters 844 int n = opRTCall->_arguments->length(); 845 for (int i = 0; i < n; i++) { 846 if (!opRTCall->_arguments->at(i)->is_pointer()) { 847 do_input(*opRTCall->_arguments->adr_at(i)); 848 } 849 } 850 if (opRTCall->_info) do_info(opRTCall->_info); 851 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 852 do_call(); 853 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 854 855 break; 856 } 857 858 859 // LIR_OpArrayCopy 860 case lir_arraycopy: { 861 assert(op->as_OpArrayCopy() != NULL, "must be"); 862 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 863 864 assert(opArrayCopy->_result->is_illegal(), "unused"); 865 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 866 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 867 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 868 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 869 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 870 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 871 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 872 873 // the implementation of arraycopy always has a call into the runtime 874 do_call(); 875 876 break; 877 } 878 879 880 // LIR_OpUpdateCRC32 881 case lir_updatecrc32: { 882 assert(op->as_OpUpdateCRC32() != NULL, "must be"); 883 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; 884 885 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); 886 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); 887 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); 888 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); 889 890 break; 891 } 892 893 894 // LIR_OpLock 895 case lir_lock: 896 case lir_unlock: { 897 assert(op->as_OpLock() != NULL, "must be"); 898 LIR_OpLock* opLock = (LIR_OpLock*)op; 899 900 if (opLock->_info) do_info(opLock->_info); 901 902 // TODO: check if these operands really have to be temp 903 // (or if input is sufficient). This may have influence on the oop map! 904 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 905 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 906 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 907 908 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 909 assert(opLock->_result->is_illegal(), "unused"); 910 911 do_stub(opLock->_stub); 912 913 break; 914 } 915 916 917 // LIR_OpDelay 918 case lir_delay_slot: { 919 assert(op->as_OpDelay() != NULL, "must be"); 920 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 921 922 visit(opDelay->delay_op()); 923 break; 924 } 925 926 // LIR_OpTypeCheck 927 case lir_instanceof: 928 case lir_checkcast: 929 case lir_store_check: { 930 assert(op->as_OpTypeCheck() != NULL, "must be"); 931 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 932 933 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 934 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 935 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 936 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { 937 do_temp(opTypeCheck->_object); 938 } 939 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 940 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 941 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 942 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 943 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 944 do_stub(opTypeCheck->_stub); 945 break; 946 } 947 948 // LIR_OpCompareAndSwap 949 case lir_cas_long: 950 case lir_cas_obj: 951 case lir_cas_int: { 952 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 953 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 954 955 assert(opCompareAndSwap->_addr->is_valid(), "used"); 956 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 957 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 958 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 959 do_input(opCompareAndSwap->_addr); 960 do_temp(opCompareAndSwap->_addr); 961 do_input(opCompareAndSwap->_cmp_value); 962 do_temp(opCompareAndSwap->_cmp_value); 963 do_input(opCompareAndSwap->_new_value); 964 do_temp(opCompareAndSwap->_new_value); 965 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 966 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 967 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 968 969 break; 970 } 971 972 973 // LIR_OpAllocArray; 974 case lir_alloc_array: { 975 assert(op->as_OpAllocArray() != NULL, "must be"); 976 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 977 978 if (opAllocArray->_info) do_info(opAllocArray->_info); 979 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 980 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 981 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 982 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 983 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 984 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 985 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 986 do_stub(opAllocArray->_stub); 987 break; 988 } 989 990 // LIR_OpProfileCall: 991 case lir_profile_call: { 992 assert(op->as_OpProfileCall() != NULL, "must be"); 993 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 994 995 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 996 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 997 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 998 break; 999 } 1000 1001 // LIR_OpProfileType: 1002 case lir_profile_type: { 1003 assert(op->as_OpProfileType() != NULL, "must be"); 1004 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; 1005 1006 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); 1007 do_input(opProfileType->_obj); 1008 do_temp(opProfileType->_tmp); 1009 break; 1010 } 1011 default: 1012 ShouldNotReachHere(); 1013 } 1014 } 1015 1016 1017 void LIR_OpVisitState::do_stub(CodeStub* stub) { 1018 if (stub != NULL) { 1019 stub->visit(this); 1020 } 1021 } 1022 1023 XHandlers* LIR_OpVisitState::all_xhandler() { 1024 XHandlers* result = NULL; 1025 1026 int i; 1027 for (i = 0; i < info_count(); i++) { 1028 if (info_at(i)->exception_handlers() != NULL) { 1029 result = info_at(i)->exception_handlers(); 1030 break; 1031 } 1032 } 1033 1034 #ifdef ASSERT 1035 for (i = 0; i < info_count(); i++) { 1036 assert(info_at(i)->exception_handlers() == NULL || 1037 info_at(i)->exception_handlers() == result, 1038 "only one xhandler list allowed per LIR-operation"); 1039 } 1040 #endif 1041 1042 if (result != NULL) { 1043 return result; 1044 } else { 1045 return new XHandlers(); 1046 } 1047 1048 return result; 1049 } 1050 1051 1052 #ifdef ASSERT 1053 bool LIR_OpVisitState::no_operands(LIR_Op* op) { 1054 visit(op); 1055 1056 return opr_count(inputMode) == 0 && 1057 opr_count(outputMode) == 0 && 1058 opr_count(tempMode) == 0 && 1059 info_count() == 0 && 1060 !has_call() && 1061 !has_slow_case(); 1062 } 1063 #endif 1064 1065 //--------------------------------------------------- 1066 1067 1068 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 1069 masm->emit_call(this); 1070 } 1071 1072 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 1073 masm->emit_rtcall(this); 1074 } 1075 1076 void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 1077 masm->emit_opLabel(this); 1078 } 1079 1080 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 1081 masm->emit_arraycopy(this); 1082 masm->append_code_stub(stub()); 1083 } 1084 1085 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { 1086 masm->emit_updatecrc32(this); 1087 } 1088 1089 void LIR_Op0::emit_code(LIR_Assembler* masm) { 1090 masm->emit_op0(this); 1091 } 1092 1093 void LIR_Op1::emit_code(LIR_Assembler* masm) { 1094 masm->emit_op1(this); 1095 } 1096 1097 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 1098 masm->emit_alloc_obj(this); 1099 masm->append_code_stub(stub()); 1100 } 1101 1102 void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 1103 masm->emit_opBranch(this); 1104 if (stub()) { 1105 masm->append_code_stub(stub()); 1106 } 1107 } 1108 1109 void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1110 masm->emit_opConvert(this); 1111 if (stub() != NULL) { 1112 masm->append_code_stub(stub()); 1113 } 1114 } 1115 1116 void LIR_Op2::emit_code(LIR_Assembler* masm) { 1117 masm->emit_op2(this); 1118 } 1119 1120 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1121 masm->emit_alloc_array(this); 1122 masm->append_code_stub(stub()); 1123 } 1124 1125 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1126 masm->emit_opTypeCheck(this); 1127 if (stub()) { 1128 masm->append_code_stub(stub()); 1129 } 1130 } 1131 1132 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1133 masm->emit_compare_and_swap(this); 1134 } 1135 1136 void LIR_Op3::emit_code(LIR_Assembler* masm) { 1137 masm->emit_op3(this); 1138 } 1139 1140 void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1141 masm->emit_lock(this); 1142 if (stub()) { 1143 masm->append_code_stub(stub()); 1144 } 1145 } 1146 1147 #ifdef ASSERT 1148 void LIR_OpAssert::emit_code(LIR_Assembler* masm) { 1149 masm->emit_assert(this); 1150 } 1151 #endif 1152 1153 void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1154 masm->emit_delay(this); 1155 } 1156 1157 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1158 masm->emit_profile_call(this); 1159 } 1160 1161 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { 1162 masm->emit_profile_type(this); 1163 } 1164 1165 // LIR_List 1166 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1167 : _operations(8) 1168 , _compilation(compilation) 1169 #ifndef PRODUCT 1170 , _block(block) 1171 #endif 1172 #ifdef ASSERT 1173 , _file(NULL) 1174 , _line(0) 1175 #endif 1176 { } 1177 1178 1179 #ifdef ASSERT 1180 void LIR_List::set_file_and_line(const char * file, int line) { 1181 const char * f = strrchr(file, '/'); 1182 if (f == NULL) f = strrchr(file, '\\'); 1183 if (f == NULL) { 1184 f = file; 1185 } else { 1186 f++; 1187 } 1188 _file = f; 1189 _line = line; 1190 } 1191 #endif 1192 1193 1194 void LIR_List::append(LIR_InsertionBuffer* buffer) { 1195 assert(this == buffer->lir_list(), "wrong lir list"); 1196 const int n = _operations.length(); 1197 1198 if (buffer->number_of_ops() > 0) { 1199 // increase size of instructions list 1200 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1201 // insert ops from buffer into instructions list 1202 int op_index = buffer->number_of_ops() - 1; 1203 int ip_index = buffer->number_of_insertion_points() - 1; 1204 int from_index = n - 1; 1205 int to_index = _operations.length() - 1; 1206 for (; ip_index >= 0; ip_index --) { 1207 int index = buffer->index_at(ip_index); 1208 // make room after insertion point 1209 while (index < from_index) { 1210 _operations.at_put(to_index --, _operations.at(from_index --)); 1211 } 1212 // insert ops from buffer 1213 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1214 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1215 } 1216 } 1217 } 1218 1219 buffer->finish(); 1220 } 1221 1222 1223 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1224 assert(reg->type() == T_OBJECT, "bad reg"); 1225 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1226 } 1227 1228 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { 1229 assert(reg->type() == T_METADATA, "bad reg"); 1230 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); 1231 } 1232 1233 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1234 append(new LIR_Op1( 1235 lir_move, 1236 LIR_OprFact::address(addr), 1237 src, 1238 addr->type(), 1239 patch_code, 1240 info)); 1241 } 1242 1243 1244 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1245 append(new LIR_Op1( 1246 lir_move, 1247 LIR_OprFact::address(address), 1248 dst, 1249 address->type(), 1250 patch_code, 1251 info, lir_move_volatile)); 1252 } 1253 1254 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1255 append(new LIR_Op1( 1256 lir_move, 1257 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1258 dst, 1259 type, 1260 patch_code, 1261 info, lir_move_volatile)); 1262 } 1263 1264 1265 void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1266 append(new LIR_Op1( 1267 is_store ? lir_prefetchw : lir_prefetchr, 1268 LIR_OprFact::address(addr))); 1269 } 1270 1271 1272 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1273 append(new LIR_Op1( 1274 lir_move, 1275 LIR_OprFact::intConst(v), 1276 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1277 type, 1278 patch_code, 1279 info)); 1280 } 1281 1282 1283 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1284 append(new LIR_Op1( 1285 lir_move, 1286 LIR_OprFact::oopConst(o), 1287 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1288 type, 1289 patch_code, 1290 info)); 1291 } 1292 1293 1294 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1295 append(new LIR_Op1( 1296 lir_move, 1297 src, 1298 LIR_OprFact::address(addr), 1299 addr->type(), 1300 patch_code, 1301 info)); 1302 } 1303 1304 1305 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1306 append(new LIR_Op1( 1307 lir_move, 1308 src, 1309 LIR_OprFact::address(addr), 1310 addr->type(), 1311 patch_code, 1312 info, 1313 lir_move_volatile)); 1314 } 1315 1316 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1317 append(new LIR_Op1( 1318 lir_move, 1319 src, 1320 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1321 type, 1322 patch_code, 1323 info, lir_move_volatile)); 1324 } 1325 1326 1327 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1328 append(new LIR_Op3( 1329 lir_idiv, 1330 left, 1331 right, 1332 tmp, 1333 res, 1334 info)); 1335 } 1336 1337 1338 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1339 append(new LIR_Op3( 1340 lir_idiv, 1341 left, 1342 LIR_OprFact::intConst(right), 1343 tmp, 1344 res, 1345 info)); 1346 } 1347 1348 1349 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1350 append(new LIR_Op3( 1351 lir_irem, 1352 left, 1353 right, 1354 tmp, 1355 res, 1356 info)); 1357 } 1358 1359 1360 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1361 append(new LIR_Op3( 1362 lir_irem, 1363 left, 1364 LIR_OprFact::intConst(right), 1365 tmp, 1366 res, 1367 info)); 1368 } 1369 1370 1371 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1372 append(new LIR_Op2( 1373 lir_cmp, 1374 condition, 1375 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1376 LIR_OprFact::intConst(c), 1377 info)); 1378 } 1379 1380 1381 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1382 append(new LIR_Op2( 1383 lir_cmp, 1384 condition, 1385 reg, 1386 LIR_OprFact::address(addr), 1387 info)); 1388 } 1389 1390 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1391 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1392 append(new LIR_OpAllocObj( 1393 klass, 1394 dst, 1395 t1, 1396 t2, 1397 t3, 1398 t4, 1399 header_size, 1400 object_size, 1401 init_check, 1402 stub)); 1403 } 1404 1405 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1406 append(new LIR_OpAllocArray( 1407 klass, 1408 len, 1409 dst, 1410 t1, 1411 t2, 1412 t3, 1413 t4, 1414 type, 1415 stub)); 1416 } 1417 1418 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1419 append(new LIR_Op2( 1420 lir_shl, 1421 value, 1422 count, 1423 dst, 1424 tmp)); 1425 } 1426 1427 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1428 append(new LIR_Op2( 1429 lir_shr, 1430 value, 1431 count, 1432 dst, 1433 tmp)); 1434 } 1435 1436 1437 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1438 append(new LIR_Op2( 1439 lir_ushr, 1440 value, 1441 count, 1442 dst, 1443 tmp)); 1444 } 1445 1446 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1447 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1448 left, 1449 right, 1450 dst)); 1451 } 1452 1453 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1454 append(new LIR_OpLock( 1455 lir_lock, 1456 hdr, 1457 obj, 1458 lock, 1459 scratch, 1460 stub, 1461 info)); 1462 } 1463 1464 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1465 append(new LIR_OpLock( 1466 lir_unlock, 1467 hdr, 1468 obj, 1469 lock, 1470 scratch, 1471 stub, 1472 NULL)); 1473 } 1474 1475 1476 void check_LIR() { 1477 // cannot do the proper checking as PRODUCT and other modes return different results 1478 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1479 } 1480 1481 1482 1483 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1484 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1485 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1486 ciMethod* profiled_method, int profiled_bci) { 1487 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1488 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1489 if (profiled_method != NULL) { 1490 c->set_profiled_method(profiled_method); 1491 c->set_profiled_bci(profiled_bci); 1492 c->set_should_profile(true); 1493 } 1494 append(c); 1495 } 1496 1497 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1498 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1499 if (profiled_method != NULL) { 1500 c->set_profiled_method(profiled_method); 1501 c->set_profiled_bci(profiled_bci); 1502 c->set_should_profile(true); 1503 } 1504 append(c); 1505 } 1506 1507 1508 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1509 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1510 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1511 if (profiled_method != NULL) { 1512 c->set_profiled_method(profiled_method); 1513 c->set_profiled_bci(profiled_bci); 1514 c->set_should_profile(true); 1515 } 1516 append(c); 1517 } 1518 1519 void LIR_List::null_check(LIR_Opr opr, CodeEmitInfo* info, bool deoptimize_on_null) { 1520 if (deoptimize_on_null) { 1521 // Emit an explicit null check and deoptimize if opr is null 1522 CodeStub* deopt = new DeoptimizeStub(info); 1523 cmp(lir_cond_equal, opr, LIR_OprFact::oopConst(NULL)); 1524 branch(lir_cond_equal, T_OBJECT, deopt); 1525 } else { 1526 // Emit an implicit null check 1527 append(new LIR_Op1(lir_null_check, opr, info)); 1528 } 1529 } 1530 1531 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1532 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1533 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1534 } 1535 1536 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1537 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1538 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1539 } 1540 1541 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1542 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1543 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1544 } 1545 1546 1547 #ifdef PRODUCT 1548 1549 void print_LIR(BlockList* blocks) { 1550 } 1551 1552 #else 1553 // LIR_OprDesc 1554 void LIR_OprDesc::print() const { 1555 print(tty); 1556 } 1557 1558 void LIR_OprDesc::print(outputStream* out) const { 1559 if (is_illegal()) { 1560 return; 1561 } 1562 1563 out->print("["); 1564 if (is_pointer()) { 1565 pointer()->print_value_on(out); 1566 } else if (is_single_stack()) { 1567 out->print("stack:%d", single_stack_ix()); 1568 } else if (is_double_stack()) { 1569 out->print("dbl_stack:%d",double_stack_ix()); 1570 } else if (is_virtual()) { 1571 out->print("R%d", vreg_number()); 1572 } else if (is_single_cpu()) { 1573 out->print("%s", as_register()->name()); 1574 } else if (is_double_cpu()) { 1575 out->print("%s", as_register_hi()->name()); 1576 out->print("%s", as_register_lo()->name()); 1577 #if defined(X86) 1578 } else if (is_single_xmm()) { 1579 out->print("%s", as_xmm_float_reg()->name()); 1580 } else if (is_double_xmm()) { 1581 out->print("%s", as_xmm_double_reg()->name()); 1582 } else if (is_single_fpu()) { 1583 out->print("fpu%d", fpu_regnr()); 1584 } else if (is_double_fpu()) { 1585 out->print("fpu%d", fpu_regnrLo()); 1586 #elif defined(ARM) 1587 } else if (is_single_fpu()) { 1588 out->print("s%d", fpu_regnr()); 1589 } else if (is_double_fpu()) { 1590 out->print("d%d", fpu_regnrLo() >> 1); 1591 #else 1592 } else if (is_single_fpu()) { 1593 out->print("%s", as_float_reg()->name()); 1594 } else if (is_double_fpu()) { 1595 out->print("%s", as_double_reg()->name()); 1596 #endif 1597 1598 } else if (is_illegal()) { 1599 out->print("-"); 1600 } else { 1601 out->print("Unknown Operand"); 1602 } 1603 if (!is_illegal()) { 1604 out->print("|%c", type_char()); 1605 } 1606 if (is_register() && is_last_use()) { 1607 out->print("(last_use)"); 1608 } 1609 out->print("]"); 1610 } 1611 1612 1613 // LIR_Address 1614 void LIR_Const::print_value_on(outputStream* out) const { 1615 switch (type()) { 1616 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1617 case T_INT: out->print("int:%d", as_jint()); break; 1618 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; 1619 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1620 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1621 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; 1622 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; 1623 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; 1624 } 1625 } 1626 1627 // LIR_Address 1628 void LIR_Address::print_value_on(outputStream* out) const { 1629 out->print("Base:"); _base->print(out); 1630 if (!_index->is_illegal()) { 1631 out->print(" Index:"); _index->print(out); 1632 switch (scale()) { 1633 case times_1: break; 1634 case times_2: out->print(" * 2"); break; 1635 case times_4: out->print(" * 4"); break; 1636 case times_8: out->print(" * 8"); break; 1637 } 1638 } 1639 out->print(" Disp: " INTX_FORMAT, _disp); 1640 } 1641 1642 // debug output of block header without InstructionPrinter 1643 // (because phi functions are not necessary for LIR) 1644 static void print_block(BlockBegin* x) { 1645 // print block id 1646 BlockEnd* end = x->end(); 1647 tty->print("B%d ", x->block_id()); 1648 1649 // print flags 1650 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1651 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1652 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1653 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1654 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1655 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1656 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1657 1658 // print block bci range 1659 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); 1660 1661 // print predecessors and successors 1662 if (x->number_of_preds() > 0) { 1663 tty->print("preds: "); 1664 for (int i = 0; i < x->number_of_preds(); i ++) { 1665 tty->print("B%d ", x->pred_at(i)->block_id()); 1666 } 1667 } 1668 1669 if (x->number_of_sux() > 0) { 1670 tty->print("sux: "); 1671 for (int i = 0; i < x->number_of_sux(); i ++) { 1672 tty->print("B%d ", x->sux_at(i)->block_id()); 1673 } 1674 } 1675 1676 // print exception handlers 1677 if (x->number_of_exception_handlers() > 0) { 1678 tty->print("xhandler: "); 1679 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1680 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1681 } 1682 } 1683 1684 tty->cr(); 1685 } 1686 1687 void print_LIR(BlockList* blocks) { 1688 tty->print_cr("LIR:"); 1689 int i; 1690 for (i = 0; i < blocks->length(); i++) { 1691 BlockBegin* bb = blocks->at(i); 1692 print_block(bb); 1693 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1694 bb->lir()->print_instructions(); 1695 } 1696 } 1697 1698 void LIR_List::print_instructions() { 1699 for (int i = 0; i < _operations.length(); i++) { 1700 _operations.at(i)->print(); tty->cr(); 1701 } 1702 tty->cr(); 1703 } 1704 1705 // LIR_Ops printing routines 1706 // LIR_Op 1707 void LIR_Op::print_on(outputStream* out) const { 1708 if (id() != -1 || PrintCFGToFile) { 1709 out->print("%4d ", id()); 1710 } else { 1711 out->print(" "); 1712 } 1713 out->print("%s ", name()); 1714 print_instr(out); 1715 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); 1716 #ifdef ASSERT 1717 if (Verbose && _file != NULL) { 1718 out->print(" (%s:%d)", _file, _line); 1719 } 1720 #endif 1721 } 1722 1723 const char * LIR_Op::name() const { 1724 const char* s = NULL; 1725 switch(code()) { 1726 // LIR_Op0 1727 case lir_membar: s = "membar"; break; 1728 case lir_membar_acquire: s = "membar_acquire"; break; 1729 case lir_membar_release: s = "membar_release"; break; 1730 case lir_membar_loadload: s = "membar_loadload"; break; 1731 case lir_membar_storestore: s = "membar_storestore"; break; 1732 case lir_membar_loadstore: s = "membar_loadstore"; break; 1733 case lir_membar_storeload: s = "membar_storeload"; break; 1734 case lir_word_align: s = "word_align"; break; 1735 case lir_label: s = "label"; break; 1736 case lir_nop: s = "nop"; break; 1737 case lir_backwardbranch_target: s = "backbranch"; break; 1738 case lir_std_entry: s = "std_entry"; break; 1739 case lir_osr_entry: s = "osr_entry"; break; 1740 case lir_build_frame: s = "build_frm"; break; 1741 case lir_fpop_raw: s = "fpop_raw"; break; 1742 case lir_24bit_FPU: s = "24bit_FPU"; break; 1743 case lir_reset_FPU: s = "reset_FPU"; break; 1744 case lir_breakpoint: s = "breakpoint"; break; 1745 case lir_get_thread: s = "get_thread"; break; 1746 // LIR_Op1 1747 case lir_fxch: s = "fxch"; break; 1748 case lir_fld: s = "fld"; break; 1749 case lir_ffree: s = "ffree"; break; 1750 case lir_push: s = "push"; break; 1751 case lir_pop: s = "pop"; break; 1752 case lir_null_check: s = "null_check"; break; 1753 case lir_return: s = "return"; break; 1754 case lir_safepoint: s = "safepoint"; break; 1755 case lir_neg: s = "neg"; break; 1756 case lir_leal: s = "leal"; break; 1757 case lir_branch: s = "branch"; break; 1758 case lir_cond_float_branch: s = "flt_cond_br"; break; 1759 case lir_move: s = "move"; break; 1760 case lir_roundfp: s = "roundfp"; break; 1761 case lir_rtcall: s = "rtcall"; break; 1762 case lir_throw: s = "throw"; break; 1763 case lir_unwind: s = "unwind"; break; 1764 case lir_convert: s = "convert"; break; 1765 case lir_alloc_object: s = "alloc_obj"; break; 1766 case lir_monaddr: s = "mon_addr"; break; 1767 case lir_pack64: s = "pack64"; break; 1768 case lir_unpack64: s = "unpack64"; break; 1769 // LIR_Op2 1770 case lir_cmp: s = "cmp"; break; 1771 case lir_cmp_l2i: s = "cmp_l2i"; break; 1772 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1773 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1774 case lir_cmove: s = "cmove"; break; 1775 case lir_add: s = "add"; break; 1776 case lir_sub: s = "sub"; break; 1777 case lir_mul: s = "mul"; break; 1778 case lir_mul_strictfp: s = "mul_strictfp"; break; 1779 case lir_div: s = "div"; break; 1780 case lir_div_strictfp: s = "div_strictfp"; break; 1781 case lir_rem: s = "rem"; break; 1782 case lir_abs: s = "abs"; break; 1783 case lir_sqrt: s = "sqrt"; break; 1784 case lir_sin: s = "sin"; break; 1785 case lir_cos: s = "cos"; break; 1786 case lir_tan: s = "tan"; break; 1787 case lir_log: s = "log"; break; 1788 case lir_log10: s = "log10"; break; 1789 case lir_exp: s = "exp"; break; 1790 case lir_pow: s = "pow"; break; 1791 case lir_logic_and: s = "logic_and"; break; 1792 case lir_logic_or: s = "logic_or"; break; 1793 case lir_logic_xor: s = "logic_xor"; break; 1794 case lir_shl: s = "shift_left"; break; 1795 case lir_shr: s = "shift_right"; break; 1796 case lir_ushr: s = "ushift_right"; break; 1797 case lir_alloc_array: s = "alloc_array"; break; 1798 case lir_xadd: s = "xadd"; break; 1799 case lir_xchg: s = "xchg"; break; 1800 // LIR_Op3 1801 case lir_idiv: s = "idiv"; break; 1802 case lir_irem: s = "irem"; break; 1803 // LIR_OpJavaCall 1804 case lir_static_call: s = "static"; break; 1805 case lir_optvirtual_call: s = "optvirtual"; break; 1806 case lir_icvirtual_call: s = "icvirtual"; break; 1807 case lir_virtual_call: s = "virtual"; break; 1808 case lir_dynamic_call: s = "dynamic"; break; 1809 // LIR_OpArrayCopy 1810 case lir_arraycopy: s = "arraycopy"; break; 1811 // LIR_OpUpdateCRC32 1812 case lir_updatecrc32: s = "updatecrc32"; break; 1813 // LIR_OpLock 1814 case lir_lock: s = "lock"; break; 1815 case lir_unlock: s = "unlock"; break; 1816 // LIR_OpDelay 1817 case lir_delay_slot: s = "delay"; break; 1818 // LIR_OpTypeCheck 1819 case lir_instanceof: s = "instanceof"; break; 1820 case lir_checkcast: s = "checkcast"; break; 1821 case lir_store_check: s = "store_check"; break; 1822 // LIR_OpCompareAndSwap 1823 case lir_cas_long: s = "cas_long"; break; 1824 case lir_cas_obj: s = "cas_obj"; break; 1825 case lir_cas_int: s = "cas_int"; break; 1826 // LIR_OpProfileCall 1827 case lir_profile_call: s = "profile_call"; break; 1828 // LIR_OpProfileType 1829 case lir_profile_type: s = "profile_type"; break; 1830 // LIR_OpAssert 1831 #ifdef ASSERT 1832 case lir_assert: s = "assert"; break; 1833 #endif 1834 case lir_none: ShouldNotReachHere();break; 1835 default: s = "illegal_op"; break; 1836 } 1837 return s; 1838 } 1839 1840 // LIR_OpJavaCall 1841 void LIR_OpJavaCall::print_instr(outputStream* out) const { 1842 out->print("call: "); 1843 out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); 1844 if (receiver()->is_valid()) { 1845 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1846 } 1847 if (result_opr()->is_valid()) { 1848 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1849 } 1850 } 1851 1852 // LIR_OpLabel 1853 void LIR_OpLabel::print_instr(outputStream* out) const { 1854 out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); 1855 } 1856 1857 // LIR_OpArrayCopy 1858 void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1859 src()->print(out); out->print(" "); 1860 src_pos()->print(out); out->print(" "); 1861 dst()->print(out); out->print(" "); 1862 dst_pos()->print(out); out->print(" "); 1863 length()->print(out); out->print(" "); 1864 tmp()->print(out); out->print(" "); 1865 } 1866 1867 // LIR_OpUpdateCRC32 1868 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { 1869 crc()->print(out); out->print(" "); 1870 val()->print(out); out->print(" "); 1871 result_opr()->print(out); out->print(" "); 1872 } 1873 1874 // LIR_OpCompareAndSwap 1875 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1876 addr()->print(out); out->print(" "); 1877 cmp_value()->print(out); out->print(" "); 1878 new_value()->print(out); out->print(" "); 1879 tmp1()->print(out); out->print(" "); 1880 tmp2()->print(out); out->print(" "); 1881 1882 } 1883 1884 // LIR_Op0 1885 void LIR_Op0::print_instr(outputStream* out) const { 1886 result_opr()->print(out); 1887 } 1888 1889 // LIR_Op1 1890 const char * LIR_Op1::name() const { 1891 if (code() == lir_move) { 1892 switch (move_kind()) { 1893 case lir_move_normal: 1894 return "move"; 1895 case lir_move_unaligned: 1896 return "unaligned move"; 1897 case lir_move_volatile: 1898 return "volatile_move"; 1899 case lir_move_wide: 1900 return "wide_move"; 1901 default: 1902 ShouldNotReachHere(); 1903 return "illegal_op"; 1904 } 1905 } else { 1906 return LIR_Op::name(); 1907 } 1908 } 1909 1910 1911 void LIR_Op1::print_instr(outputStream* out) const { 1912 _opr->print(out); out->print(" "); 1913 result_opr()->print(out); out->print(" "); 1914 print_patch_code(out, patch_code()); 1915 } 1916 1917 1918 // LIR_Op1 1919 void LIR_OpRTCall::print_instr(outputStream* out) const { 1920 intx a = (intx)addr(); 1921 out->print("%s", Runtime1::name_for_address(addr())); 1922 out->print(" "); 1923 tmp()->print(out); 1924 } 1925 1926 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1927 switch(code) { 1928 case lir_patch_none: break; 1929 case lir_patch_low: out->print("[patch_low]"); break; 1930 case lir_patch_high: out->print("[patch_high]"); break; 1931 case lir_patch_normal: out->print("[patch_normal]"); break; 1932 default: ShouldNotReachHere(); 1933 } 1934 } 1935 1936 // LIR_OpBranch 1937 void LIR_OpBranch::print_instr(outputStream* out) const { 1938 print_condition(out, cond()); out->print(" "); 1939 if (block() != NULL) { 1940 out->print("[B%d] ", block()->block_id()); 1941 } else if (stub() != NULL) { 1942 out->print("["); 1943 stub()->print_name(out); 1944 out->print(": " INTPTR_FORMAT "]", p2i(stub())); 1945 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); 1946 } else { 1947 out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); 1948 } 1949 if (ublock() != NULL) { 1950 out->print("unordered: [B%d] ", ublock()->block_id()); 1951 } 1952 } 1953 1954 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1955 switch(cond) { 1956 case lir_cond_equal: out->print("[EQ]"); break; 1957 case lir_cond_notEqual: out->print("[NE]"); break; 1958 case lir_cond_less: out->print("[LT]"); break; 1959 case lir_cond_lessEqual: out->print("[LE]"); break; 1960 case lir_cond_greaterEqual: out->print("[GE]"); break; 1961 case lir_cond_greater: out->print("[GT]"); break; 1962 case lir_cond_belowEqual: out->print("[BE]"); break; 1963 case lir_cond_aboveEqual: out->print("[AE]"); break; 1964 case lir_cond_always: out->print("[AL]"); break; 1965 default: out->print("[%d]",cond); break; 1966 } 1967 } 1968 1969 // LIR_OpConvert 1970 void LIR_OpConvert::print_instr(outputStream* out) const { 1971 print_bytecode(out, bytecode()); 1972 in_opr()->print(out); out->print(" "); 1973 result_opr()->print(out); out->print(" "); 1974 #ifdef PPC 1975 if(tmp1()->is_valid()) { 1976 tmp1()->print(out); out->print(" "); 1977 tmp2()->print(out); out->print(" "); 1978 } 1979 #endif 1980 } 1981 1982 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1983 switch(code) { 1984 case Bytecodes::_d2f: out->print("[d2f] "); break; 1985 case Bytecodes::_d2i: out->print("[d2i] "); break; 1986 case Bytecodes::_d2l: out->print("[d2l] "); break; 1987 case Bytecodes::_f2d: out->print("[f2d] "); break; 1988 case Bytecodes::_f2i: out->print("[f2i] "); break; 1989 case Bytecodes::_f2l: out->print("[f2l] "); break; 1990 case Bytecodes::_i2b: out->print("[i2b] "); break; 1991 case Bytecodes::_i2c: out->print("[i2c] "); break; 1992 case Bytecodes::_i2d: out->print("[i2d] "); break; 1993 case Bytecodes::_i2f: out->print("[i2f] "); break; 1994 case Bytecodes::_i2l: out->print("[i2l] "); break; 1995 case Bytecodes::_i2s: out->print("[i2s] "); break; 1996 case Bytecodes::_l2i: out->print("[l2i] "); break; 1997 case Bytecodes::_l2f: out->print("[l2f] "); break; 1998 case Bytecodes::_l2d: out->print("[l2d] "); break; 1999 default: 2000 out->print("[?%d]",code); 2001 break; 2002 } 2003 } 2004 2005 void LIR_OpAllocObj::print_instr(outputStream* out) const { 2006 klass()->print(out); out->print(" "); 2007 obj()->print(out); out->print(" "); 2008 tmp1()->print(out); out->print(" "); 2009 tmp2()->print(out); out->print(" "); 2010 tmp3()->print(out); out->print(" "); 2011 tmp4()->print(out); out->print(" "); 2012 out->print("[hdr:%d]", header_size()); out->print(" "); 2013 out->print("[obj:%d]", object_size()); out->print(" "); 2014 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2015 } 2016 2017 void LIR_OpRoundFP::print_instr(outputStream* out) const { 2018 _opr->print(out); out->print(" "); 2019 tmp()->print(out); out->print(" "); 2020 result_opr()->print(out); out->print(" "); 2021 } 2022 2023 // LIR_Op2 2024 void LIR_Op2::print_instr(outputStream* out) const { 2025 if (code() == lir_cmove) { 2026 print_condition(out, condition()); out->print(" "); 2027 } 2028 in_opr1()->print(out); out->print(" "); 2029 in_opr2()->print(out); out->print(" "); 2030 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 2031 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 2032 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 2033 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } 2034 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } 2035 result_opr()->print(out); 2036 } 2037 2038 void LIR_OpAllocArray::print_instr(outputStream* out) const { 2039 klass()->print(out); out->print(" "); 2040 len()->print(out); out->print(" "); 2041 obj()->print(out); out->print(" "); 2042 tmp1()->print(out); out->print(" "); 2043 tmp2()->print(out); out->print(" "); 2044 tmp3()->print(out); out->print(" "); 2045 tmp4()->print(out); out->print(" "); 2046 out->print("[type:0x%x]", type()); out->print(" "); 2047 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2048 } 2049 2050 2051 void LIR_OpTypeCheck::print_instr(outputStream* out) const { 2052 object()->print(out); out->print(" "); 2053 if (code() == lir_store_check) { 2054 array()->print(out); out->print(" "); 2055 } 2056 if (code() != lir_store_check) { 2057 klass()->print_name_on(out); out->print(" "); 2058 if (fast_check()) out->print("fast_check "); 2059 } 2060 tmp1()->print(out); out->print(" "); 2061 tmp2()->print(out); out->print(" "); 2062 tmp3()->print(out); out->print(" "); 2063 result_opr()->print(out); out->print(" "); 2064 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); 2065 } 2066 2067 2068 // LIR_Op3 2069 void LIR_Op3::print_instr(outputStream* out) const { 2070 in_opr1()->print(out); out->print(" "); 2071 in_opr2()->print(out); out->print(" "); 2072 in_opr3()->print(out); out->print(" "); 2073 result_opr()->print(out); 2074 } 2075 2076 2077 void LIR_OpLock::print_instr(outputStream* out) const { 2078 hdr_opr()->print(out); out->print(" "); 2079 obj_opr()->print(out); out->print(" "); 2080 lock_opr()->print(out); out->print(" "); 2081 if (_scratch->is_valid()) { 2082 _scratch->print(out); out->print(" "); 2083 } 2084 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2085 } 2086 2087 #ifdef ASSERT 2088 void LIR_OpAssert::print_instr(outputStream* out) const { 2089 print_condition(out, condition()); out->print(" "); 2090 in_opr1()->print(out); out->print(" "); 2091 in_opr2()->print(out); out->print(", \""); 2092 out->print("%s", msg()); out->print("\""); 2093 } 2094 #endif 2095 2096 2097 void LIR_OpDelay::print_instr(outputStream* out) const { 2098 _op->print_on(out); 2099 } 2100 2101 2102 // LIR_OpProfileCall 2103 void LIR_OpProfileCall::print_instr(outputStream* out) const { 2104 profiled_method()->name()->print_symbol_on(out); 2105 out->print("."); 2106 profiled_method()->holder()->name()->print_symbol_on(out); 2107 out->print(" @ %d ", profiled_bci()); 2108 mdo()->print(out); out->print(" "); 2109 recv()->print(out); out->print(" "); 2110 tmp1()->print(out); out->print(" "); 2111 } 2112 2113 // LIR_OpProfileType 2114 void LIR_OpProfileType::print_instr(outputStream* out) const { 2115 out->print("exact = "); 2116 if (exact_klass() == NULL) { 2117 out->print("unknown"); 2118 } else { 2119 exact_klass()->print_name_on(out); 2120 } 2121 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass()); 2122 out->print(" "); 2123 mdp()->print(out); out->print(" "); 2124 obj()->print(out); out->print(" "); 2125 tmp()->print(out); out->print(" "); 2126 } 2127 2128 #endif // PRODUCT 2129 2130 // Implementation of LIR_InsertionBuffer 2131 2132 void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 2133 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 2134 2135 int i = number_of_insertion_points() - 1; 2136 if (i < 0 || index_at(i) < index) { 2137 append_new(index, 1); 2138 } else { 2139 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 2140 assert(count_at(i) > 0, "check"); 2141 set_count_at(i, count_at(i) + 1); 2142 } 2143 _ops.push(op); 2144 2145 DEBUG_ONLY(verify()); 2146 } 2147 2148 #ifdef ASSERT 2149 void LIR_InsertionBuffer::verify() { 2150 int sum = 0; 2151 int prev_idx = -1; 2152 2153 for (int i = 0; i < number_of_insertion_points(); i++) { 2154 assert(prev_idx < index_at(i), "index must be ordered ascending"); 2155 sum += count_at(i); 2156 } 2157 assert(sum == number_of_ops(), "wrong total sum"); 2158 } 2159 #endif