1590 if (!address->index()->is_valid() && address->disp() == 0) {
1591 __ move(address->base(), ptr);
1592 } else {
1593 assert(address->disp() != max_jint, "lea doesn't support patched addresses!");
1594 __ leal(addr, ptr);
1595 }
1596 addr = ptr;
1597 }
1598 assert(addr->is_register(), "must be a register at this point");
1599
1600 #ifdef CARDTABLEMODREF_POST_BARRIER_HELPER
1601 CardTableModRef_post_barrier_helper(addr, card_table_base);
1602 #else
1603 LIR_Opr tmp = new_pointer_register();
1604 if (TwoOperandLIRForm) {
1605 __ move(addr, tmp);
1606 __ unsigned_shift_right(tmp, CardTableModRefBS::card_shift, tmp);
1607 } else {
1608 __ unsigned_shift_right(addr, CardTableModRefBS::card_shift, tmp);
1609 }
1610 if (can_inline_as_constant(card_table_base)) {
1611 __ move(LIR_OprFact::intConst(0),
1612 new LIR_Address(tmp, card_table_base->as_jint(), T_BYTE));
1613 } else {
1614 __ move(LIR_OprFact::intConst(0),
1615 new LIR_Address(tmp, load_constant(card_table_base),
1616 T_BYTE));
1617 }
1618 #endif
1619 }
1620
1621
1622 //------------------------field access--------------------------------------
1623
1624 // Comment copied form templateTable_i486.cpp
1625 // ----------------------------------------------------------------------------
1626 // Volatile variables demand their effects be made known to all CPU's in
1627 // order. Store buffers on most chips allow reads & writes to reorder; the
1628 // JMM's ReadAfterWrite.java test fails in -Xint mode without some kind of
1629 // memory barrier (i.e., it's not sufficient that the interpreter does not
2088 }
2089 }
2090 // At this point base is a long non-constant
2091 // Index is a long register or a int constant.
2092 // We allow the constant to stay an int because that would allow us a more compact encoding by
2093 // embedding an immediate offset in the address expression. If we have a long constant, we have to
2094 // move it into a register first.
2095 assert(base_op->type() == T_LONG && !base_op->is_constant(), "base must be a long non-constant");
2096 assert(!x->has_index() || (index_op->type() == T_INT && index_op->is_constant()) ||
2097 (index_op->type() == T_LONG && !index_op->is_constant()), "unexpected index type");
2098 #endif
2099
2100 BasicType dst_type = x->basic_type();
2101
2102 LIR_Address* addr;
2103 if (index_op->is_constant()) {
2104 assert(log2_scale == 0, "must not have a scale");
2105 assert(index_op->type() == T_INT, "only int constants supported");
2106 addr = new LIR_Address(base_op, index_op->as_jint(), dst_type);
2107 } else {
2108 #ifdef X86
2109 addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
2110 #elif defined(GENERATE_ADDRESS_IS_PREFERRED)
2111 addr = generate_address(base_op, index_op, log2_scale, 0, dst_type);
2112 #else
2113 if (index_op->is_illegal() || log2_scale == 0) {
2114 addr = new LIR_Address(base_op, index_op, dst_type);
2115 } else {
2116 LIR_Opr tmp = new_pointer_register();
2117 __ shift_left(index_op, log2_scale, tmp);
2118 addr = new LIR_Address(base_op, tmp, dst_type);
2119 }
2120 #endif
2121 }
2122
2123 if (x->may_be_unaligned() && (dst_type == T_LONG || dst_type == T_DOUBLE)) {
2124 __ unaligned_move(addr, reg);
2125 } else {
2126 if (dst_type == T_OBJECT && x->is_wide()) {
2127 __ move_wide(addr, reg);
2128 } else {
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1590 if (!address->index()->is_valid() && address->disp() == 0) {
1591 __ move(address->base(), ptr);
1592 } else {
1593 assert(address->disp() != max_jint, "lea doesn't support patched addresses!");
1594 __ leal(addr, ptr);
1595 }
1596 addr = ptr;
1597 }
1598 assert(addr->is_register(), "must be a register at this point");
1599
1600 #ifdef CARDTABLEMODREF_POST_BARRIER_HELPER
1601 CardTableModRef_post_barrier_helper(addr, card_table_base);
1602 #else
1603 LIR_Opr tmp = new_pointer_register();
1604 if (TwoOperandLIRForm) {
1605 __ move(addr, tmp);
1606 __ unsigned_shift_right(tmp, CardTableModRefBS::card_shift, tmp);
1607 } else {
1608 __ unsigned_shift_right(addr, CardTableModRefBS::card_shift, tmp);
1609 }
1610
1611 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) {
1612 __ membar_storestore();
1613 }
1614
1615 if (can_inline_as_constant(card_table_base)) {
1616 __ move(LIR_OprFact::intConst(0),
1617 new LIR_Address(tmp, card_table_base->as_jint(), T_BYTE));
1618 } else {
1619 __ move(LIR_OprFact::intConst(0),
1620 new LIR_Address(tmp, load_constant(card_table_base),
1621 T_BYTE));
1622 }
1623 #endif
1624 }
1625
1626
1627 //------------------------field access--------------------------------------
1628
1629 // Comment copied form templateTable_i486.cpp
1630 // ----------------------------------------------------------------------------
1631 // Volatile variables demand their effects be made known to all CPU's in
1632 // order. Store buffers on most chips allow reads & writes to reorder; the
1633 // JMM's ReadAfterWrite.java test fails in -Xint mode without some kind of
1634 // memory barrier (i.e., it's not sufficient that the interpreter does not
2093 }
2094 }
2095 // At this point base is a long non-constant
2096 // Index is a long register or a int constant.
2097 // We allow the constant to stay an int because that would allow us a more compact encoding by
2098 // embedding an immediate offset in the address expression. If we have a long constant, we have to
2099 // move it into a register first.
2100 assert(base_op->type() == T_LONG && !base_op->is_constant(), "base must be a long non-constant");
2101 assert(!x->has_index() || (index_op->type() == T_INT && index_op->is_constant()) ||
2102 (index_op->type() == T_LONG && !index_op->is_constant()), "unexpected index type");
2103 #endif
2104
2105 BasicType dst_type = x->basic_type();
2106
2107 LIR_Address* addr;
2108 if (index_op->is_constant()) {
2109 assert(log2_scale == 0, "must not have a scale");
2110 assert(index_op->type() == T_INT, "only int constants supported");
2111 addr = new LIR_Address(base_op, index_op->as_jint(), dst_type);
2112 } else {
2113 #if defined(X86) || defined(AARCH64)
2114 addr = new LIR_Address(base_op, index_op, LIR_Address::Scale(log2_scale), 0, dst_type);
2115 #elif defined(GENERATE_ADDRESS_IS_PREFERRED)
2116 addr = generate_address(base_op, index_op, log2_scale, 0, dst_type);
2117 #else
2118 if (index_op->is_illegal() || log2_scale == 0) {
2119 addr = new LIR_Address(base_op, index_op, dst_type);
2120 } else {
2121 LIR_Opr tmp = new_pointer_register();
2122 __ shift_left(index_op, log2_scale, tmp);
2123 addr = new LIR_Address(base_op, tmp, dst_type);
2124 }
2125 #endif
2126 }
2127
2128 if (x->may_be_unaligned() && (dst_type == T_LONG || dst_type == T_DOUBLE)) {
2129 __ unaligned_move(addr, reg);
2130 } else {
2131 if (dst_type == T_OBJECT && x->is_wide()) {
2132 __ move_wide(addr, reg);
2133 } else {
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