src/share/vm/opto/compile.cpp

*** 71,80 ****
--- 71,82 ----
  # include AD_MD_HPP
  #elif defined TARGET_ARCH_MODEL_x86_32
  # include "adfiles/ad_x86_32.hpp"
  #elif defined TARGET_ARCH_MODEL_x86_64
  # include "adfiles/ad_x86_64.hpp"
+ #elif defined TARGET_ARCH_MODEL_aarch64
+ # include "adfiles/ad_aarch64.hpp"
  #elif defined TARGET_ARCH_MODEL_sparc
  # include "adfiles/ad_sparc.hpp"
  #elif defined TARGET_ARCH_MODEL_zero
  # include "adfiles/ad_zero.hpp"
  #elif defined TARGET_ARCH_MODEL_ppc_64
*** 2671,2680 ****
--- 2673,2693 ----
              // oop will be recorded in oop map if load crosses safepoint
              n->is_Load() && (n->as_Load()->bottom_type()->isa_oopptr() ||
                               LoadNode::is_immutable_value(n->in(MemNode::Address))),
              "raw memory operations should have control edge");
    }
+   if (n->is_MemBar()) {
+     MemBarNode* mb = n->as_MemBar();
+     if (mb->trailing_store() || mb->trailing_load_store()) {
+       assert(mb->leading_membar()->trailing_membar() == mb, "bad membar pair");
+       Node* mem = mb->in(MemBarNode::Precedent);
+       assert((mb->trailing_store() && mem->is_Store() && mem->as_Store()->is_release()) ||
+              (mb->trailing_load_store() && mem->is_LoadStore()), "missing mem op");
+     } else if (mb->leading()) {
+       assert(mb->trailing_membar()->leading_membar() == mb, "bad membar pair");
+     }
+   }
  #endif
    // Count FPU ops and common calls, implements item (3)
    switch( nop ) {
    // Count all float operations that may use FPU
    case Op_AddF: