1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/addnode.hpp"
28 #include "opto/callnode.hpp"
29 #include "opto/connode.hpp"
30 #include "opto/idealGraphPrinter.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/memnode.hpp"
33 #include "opto/opcodes.hpp"
34 #include "opto/regmask.hpp"
35 #include "opto/rootnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "opto/type.hpp"
38 #include "opto/vectornode.hpp"
39 #include "runtime/atomic.hpp"
40 #include "runtime/os.hpp"
41 #if defined AD_MD_HPP
42 # include AD_MD_HPP
43 #elif defined TARGET_ARCH_MODEL_x86_32
44 # include "adfiles/ad_x86_32.hpp"
45 #elif defined TARGET_ARCH_MODEL_x86_64
46 # include "adfiles/ad_x86_64.hpp"
47 #elif defined TARGET_ARCH_MODEL_aarch64
48 # include "adfiles/ad_aarch64.hpp"
49 #elif defined TARGET_ARCH_MODEL_sparc
50 # include "adfiles/ad_sparc.hpp"
51 #elif defined TARGET_ARCH_MODEL_zero
52 # include "adfiles/ad_zero.hpp"
53 #elif defined TARGET_ARCH_MODEL_ppc_64
54 # include "adfiles/ad_ppc_64.hpp"
55 #endif
56
57 OptoReg::Name OptoReg::c_frame_pointer;
58
59 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
60 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
61 RegMask Matcher::STACK_ONLY_mask;
62 RegMask Matcher::c_frame_ptr_mask;
63 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
64 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
65
66 //---------------------------Matcher-------------------------------------------
67 Matcher::Matcher()
68 : PhaseTransform( Phase::Ins_Select ),
69 #ifdef ASSERT
70 _old2new_map(C->comp_arena()),
71 _new2old_map(C->comp_arena()),
72 #endif
73 _shared_nodes(C->comp_arena()),
74 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
75 _swallowed(swallowed),
76 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
77 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
78 _must_clone(must_clone),
79 _register_save_policy(register_save_policy),
80 _c_reg_save_policy(c_reg_save_policy),
81 _register_save_type(register_save_type),
82 _ruleName(ruleName),
83 _allocation_started(false),
84 _states_arena(Chunk::medium_size, mtCompiler),
85 _visited(&_states_arena),
86 _shared(&_states_arena),
87 _dontcare(&_states_arena) {
88 C->set_matcher(this);
89
90 idealreg2spillmask [Op_RegI] = NULL;
91 idealreg2spillmask [Op_RegN] = NULL;
92 idealreg2spillmask [Op_RegL] = NULL;
93 idealreg2spillmask [Op_RegF] = NULL;
94 idealreg2spillmask [Op_RegD] = NULL;
95 idealreg2spillmask [Op_RegP] = NULL;
96 idealreg2spillmask [Op_VecS] = NULL;
97 idealreg2spillmask [Op_VecD] = NULL;
98 idealreg2spillmask [Op_VecX] = NULL;
99 idealreg2spillmask [Op_VecY] = NULL;
100 idealreg2spillmask [Op_RegFlags] = NULL;
101
102 idealreg2debugmask [Op_RegI] = NULL;
103 idealreg2debugmask [Op_RegN] = NULL;
104 idealreg2debugmask [Op_RegL] = NULL;
105 idealreg2debugmask [Op_RegF] = NULL;
106 idealreg2debugmask [Op_RegD] = NULL;
107 idealreg2debugmask [Op_RegP] = NULL;
108 idealreg2debugmask [Op_VecS] = NULL;
109 idealreg2debugmask [Op_VecD] = NULL;
110 idealreg2debugmask [Op_VecX] = NULL;
111 idealreg2debugmask [Op_VecY] = NULL;
112 idealreg2debugmask [Op_RegFlags] = NULL;
113
114 idealreg2mhdebugmask[Op_RegI] = NULL;
115 idealreg2mhdebugmask[Op_RegN] = NULL;
116 idealreg2mhdebugmask[Op_RegL] = NULL;
117 idealreg2mhdebugmask[Op_RegF] = NULL;
118 idealreg2mhdebugmask[Op_RegD] = NULL;
119 idealreg2mhdebugmask[Op_RegP] = NULL;
120 idealreg2mhdebugmask[Op_VecS] = NULL;
121 idealreg2mhdebugmask[Op_VecD] = NULL;
122 idealreg2mhdebugmask[Op_VecX] = NULL;
123 idealreg2mhdebugmask[Op_VecY] = NULL;
124 idealreg2mhdebugmask[Op_RegFlags] = NULL;
125
126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
127 }
128
129 //------------------------------warp_incoming_stk_arg------------------------
130 // This warps a VMReg into an OptoReg::Name
131 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
132 OptoReg::Name warped;
133 if( reg->is_stack() ) { // Stack slot argument?
134 warped = OptoReg::add(_old_SP, reg->reg2stack() );
135 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
136 if( warped >= _in_arg_limit )
137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
138 if (!RegMask::can_represent_arg(warped)) {
139 // the compiler cannot represent this method's calling sequence
140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence");
141 return OptoReg::Bad;
142 }
143 return warped;
144 }
145 return OptoReg::as_OptoReg(reg);
146 }
147
148 //---------------------------compute_old_SP------------------------------------
149 OptoReg::Name Compile::compute_old_SP() {
150 int fixed = fixed_slots();
151 int preserve = in_preserve_stack_slots();
152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots()));
153 }
154
155
156
157 #ifdef ASSERT
158 void Matcher::verify_new_nodes_only(Node* xroot) {
159 // Make sure that the new graph only references new nodes
160 ResourceMark rm;
161 Unique_Node_List worklist;
162 VectorSet visited(Thread::current()->resource_area());
163 worklist.push(xroot);
164 while (worklist.size() > 0) {
165 Node* n = worklist.pop();
166 visited <<= n->_idx;
167 assert(C->node_arena()->contains(n), "dead node");
168 for (uint j = 0; j < n->req(); j++) {
169 Node* in = n->in(j);
170 if (in != NULL) {
171 assert(C->node_arena()->contains(in), "dead node");
172 if (!visited.test(in->_idx)) {
173 worklist.push(in);
174 }
175 }
176 }
177 }
178 }
179 #endif
180
181
182 //---------------------------match---------------------------------------------
183 void Matcher::match( ) {
184 if( MaxLabelRootDepth < 100 ) { // Too small?
185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
186 MaxLabelRootDepth = 100;
187 }
188 // One-time initialization of some register masks.
189 init_spill_mask( C->root()->in(1) );
190 _return_addr_mask = return_addr();
191 #ifdef _LP64
192 // Pointers take 2 slots in 64-bit land
193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
194 #endif
195
196 // Map a Java-signature return type into return register-value
197 // machine registers for 0, 1 and 2 returned values.
198 const TypeTuple *range = C->tf()->range();
199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
200 // Get ideal-register return type
201 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
202 // Get machine return register
203 uint sop = C->start()->Opcode();
204 OptoRegPair regs = return_value(ireg, false);
205
206 // And mask for same
207 _return_value_mask = RegMask(regs.first());
208 if( OptoReg::is_valid(regs.second()) )
209 _return_value_mask.Insert(regs.second());
210 }
211
212 // ---------------
213 // Frame Layout
214
215 // Need the method signature to determine the incoming argument types,
216 // because the types determine which registers the incoming arguments are
217 // in, and this affects the matched code.
218 const TypeTuple *domain = C->tf()->domain();
219 uint argcnt = domain->cnt() - TypeFunc::Parms;
220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
224 uint i;
225 for( i = 0; i<argcnt; i++ ) {
226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
227 }
228
229 // Pass array of ideal registers and length to USER code (from the AD file)
230 // that will convert this to an array of register numbers.
231 const StartNode *start = C->start();
232 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
233 #ifdef ASSERT
234 // Sanity check users' calling convention. Real handy while trying to
235 // get the initial port correct.
236 { for (uint i = 0; i<argcnt; i++) {
237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
239 _parm_regs[i].set_bad();
240 continue;
241 }
242 VMReg parm_reg = vm_parm_regs[i].first();
243 assert(parm_reg->is_valid(), "invalid arg?");
244 if (parm_reg->is_reg()) {
245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
246 assert(can_be_java_arg(opto_parm_reg) ||
247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
248 opto_parm_reg == inline_cache_reg(),
249 "parameters in register must be preserved by runtime stubs");
250 }
251 for (uint j = 0; j < i; j++) {
252 assert(parm_reg != vm_parm_regs[j].first(),
253 "calling conv. must produce distinct regs");
254 }
255 }
256 }
257 #endif
258
259 // Do some initial frame layout.
260
261 // Compute the old incoming SP (may be called FP) as
262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
263 _old_SP = C->compute_old_SP();
264 assert( is_even(_old_SP), "must be even" );
265
266 // Compute highest incoming stack argument as
267 // _old_SP + out_preserve_stack_slots + incoming argument size.
268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
269 assert( is_even(_in_arg_limit), "out_preserve must be even" );
270 for( i = 0; i < argcnt; i++ ) {
271 // Permit args to have no register
272 _calling_convention_mask[i].Clear();
273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
274 continue;
275 }
276 // calling_convention returns stack arguments as a count of
277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
278 // the allocators point of view, taking into account all the
279 // preserve area, locks & pad2.
280
281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
282 if( OptoReg::is_valid(reg1))
283 _calling_convention_mask[i].Insert(reg1);
284
285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
286 if( OptoReg::is_valid(reg2))
287 _calling_convention_mask[i].Insert(reg2);
288
289 // Saved biased stack-slot register number
290 _parm_regs[i].set_pair(reg2, reg1);
291 }
292
293 // Finally, make sure the incoming arguments take up an even number of
294 // words, in case the arguments or locals need to contain doubleword stack
295 // slots. The rest of the system assumes that stack slot pairs (in
296 // particular, in the spill area) which look aligned will in fact be
297 // aligned relative to the stack pointer in the target machine. Double
298 // stack slots will always be allocated aligned.
299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong));
300
301 // Compute highest outgoing stack argument as
302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
304 assert( is_even(_out_arg_limit), "out_preserve must be even" );
305
306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
307 // the compiler cannot represent this method's calling sequence
308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
309 }
310
311 if (C->failing()) return; // bailed out on incoming arg failure
312
313 // ---------------
314 // Collect roots of matcher trees. Every node for which
315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
316 // can be a valid interior of some tree.
317 find_shared( C->root() );
318 find_shared( C->top() );
319
320 C->print_method(PHASE_BEFORE_MATCHING);
321
322 // Create new ideal node ConP #NULL even if it does exist in old space
323 // to avoid false sharing if the corresponding mach node is not used.
324 // The corresponding mach node is only used in rare cases for derived
325 // pointers.
326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR);
327
328 // Swap out to old-space; emptying new-space
329 Arena *old = C->node_arena()->move_contents(C->old_arena());
330
331 // Save debug and profile information for nodes in old space:
332 _old_node_note_array = C->node_note_array();
333 if (_old_node_note_array != NULL) {
334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
335 (C->comp_arena(), _old_node_note_array->length(),
336 0, NULL));
337 }
338
339 // Pre-size the new_node table to avoid the need for range checks.
340 grow_new_node_array(C->unique());
341
342 // Reset node counter so MachNodes start with _idx at 0
343 int live_nodes = C->live_nodes();
344 C->set_unique(0);
345 C->reset_dead_node_list();
346
347 // Recursively match trees from old space into new space.
348 // Correct leaves of new-space Nodes; they point to old-space.
349 _visited.Clear(); // Clear visit bits for xform call
350 C->set_cached_top_node(xform( C->top(), live_nodes));
351 if (!C->failing()) {
352 Node* xroot = xform( C->root(), 1 );
353 if (xroot == NULL) {
354 Matcher::soft_match_failure(); // recursive matching process failed
355 C->record_method_not_compilable("instruction match failed");
356 } else {
357 // During matching shared constants were attached to C->root()
358 // because xroot wasn't available yet, so transfer the uses to
359 // the xroot.
360 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
361 Node* n = C->root()->fast_out(j);
362 if (C->node_arena()->contains(n)) {
363 assert(n->in(0) == C->root(), "should be control user");
364 n->set_req(0, xroot);
365 --j;
366 --jmax;
367 }
368 }
369
370 // Generate new mach node for ConP #NULL
371 assert(new_ideal_null != NULL, "sanity");
372 _mach_null = match_tree(new_ideal_null);
373 // Don't set control, it will confuse GCM since there are no uses.
374 // The control will be set when this node is used first time
375 // in find_base_for_derived().
376 assert(_mach_null != NULL, "");
377
378 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
379
380 #ifdef ASSERT
381 verify_new_nodes_only(xroot);
382 #endif
383 }
384 }
385 if (C->top() == NULL || C->root() == NULL) {
386 C->record_method_not_compilable("graph lost"); // %%% cannot happen?
387 }
388 if (C->failing()) {
389 // delete old;
390 old->destruct_contents();
391 return;
392 }
393 assert( C->top(), "" );
394 assert( C->root(), "" );
395 validate_null_checks();
396
397 // Now smoke old-space
398 NOT_DEBUG( old->destruct_contents() );
399
400 // ------------------------
401 // Set up save-on-entry registers
402 Fixup_Save_On_Entry( );
403 }
404
405
406 //------------------------------Fixup_Save_On_Entry----------------------------
407 // The stated purpose of this routine is to take care of save-on-entry
408 // registers. However, the overall goal of the Match phase is to convert into
409 // machine-specific instructions which have RegMasks to guide allocation.
410 // So what this procedure really does is put a valid RegMask on each input
411 // to the machine-specific variations of all Return, TailCall and Halt
412 // instructions. It also adds edgs to define the save-on-entry values (and of
413 // course gives them a mask).
414
415 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
416 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
417 // Do all the pre-defined register masks
418 rms[TypeFunc::Control ] = RegMask::Empty;
419 rms[TypeFunc::I_O ] = RegMask::Empty;
420 rms[TypeFunc::Memory ] = RegMask::Empty;
421 rms[TypeFunc::ReturnAdr] = ret_adr;
422 rms[TypeFunc::FramePtr ] = fp;
423 return rms;
424 }
425
426 //---------------------------init_first_stack_mask-----------------------------
427 // Create the initial stack mask used by values spilling to the stack.
428 // Disallow any debug info in outgoing argument areas by setting the
429 // initial mask accordingly.
430 void Matcher::init_first_stack_mask() {
431
432 // Allocate storage for spill masks as masks for the appropriate load type.
433 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4));
434
435 idealreg2spillmask [Op_RegN] = &rms[0];
436 idealreg2spillmask [Op_RegI] = &rms[1];
437 idealreg2spillmask [Op_RegL] = &rms[2];
438 idealreg2spillmask [Op_RegF] = &rms[3];
439 idealreg2spillmask [Op_RegD] = &rms[4];
440 idealreg2spillmask [Op_RegP] = &rms[5];
441
442 idealreg2debugmask [Op_RegN] = &rms[6];
443 idealreg2debugmask [Op_RegI] = &rms[7];
444 idealreg2debugmask [Op_RegL] = &rms[8];
445 idealreg2debugmask [Op_RegF] = &rms[9];
446 idealreg2debugmask [Op_RegD] = &rms[10];
447 idealreg2debugmask [Op_RegP] = &rms[11];
448
449 idealreg2mhdebugmask[Op_RegN] = &rms[12];
450 idealreg2mhdebugmask[Op_RegI] = &rms[13];
451 idealreg2mhdebugmask[Op_RegL] = &rms[14];
452 idealreg2mhdebugmask[Op_RegF] = &rms[15];
453 idealreg2mhdebugmask[Op_RegD] = &rms[16];
454 idealreg2mhdebugmask[Op_RegP] = &rms[17];
455
456 idealreg2spillmask [Op_VecS] = &rms[18];
457 idealreg2spillmask [Op_VecD] = &rms[19];
458 idealreg2spillmask [Op_VecX] = &rms[20];
459 idealreg2spillmask [Op_VecY] = &rms[21];
460
461 OptoReg::Name i;
462
463 // At first, start with the empty mask
464 C->FIRST_STACK_mask().Clear();
465
466 // Add in the incoming argument area
467 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
468 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
469 C->FIRST_STACK_mask().Insert(i);
470 }
471 // Add in all bits past the outgoing argument area
472 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
473 "must be able to represent all call arguments in reg mask");
474 OptoReg::Name init = _out_arg_limit;
475 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
476 C->FIRST_STACK_mask().Insert(i);
477 }
478 // Finally, set the "infinite stack" bit.
479 C->FIRST_STACK_mask().set_AllStack();
480
481 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
482 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
483 // Keep spill masks aligned.
484 aligned_stack_mask.clear_to_pairs();
485 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
486
487 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
488 #ifdef _LP64
489 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
490 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
491 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
492 #else
493 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
494 #endif
495 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
496 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
497 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
498 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
499 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
500 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
501 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
502 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
503
504 if (Matcher::vector_size_supported(T_BYTE,4)) {
505 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
506 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
507 }
508 if (Matcher::vector_size_supported(T_FLOAT,2)) {
509 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
510 // RA guarantees such alignment since it is needed for Double and Long values.
511 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
512 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
513 }
514 if (Matcher::vector_size_supported(T_FLOAT,4)) {
515 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
516 //
517 // RA can use input arguments stack slots for spills but until RA
518 // we don't know frame size and offset of input arg stack slots.
519 //
520 // Exclude last input arg stack slots to avoid spilling vectors there
521 // otherwise vector spills could stomp over stack slots in caller frame.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
530 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,8)) {
533 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
542 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
550 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
551 #ifdef _LP64
552 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
554 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
556 #else
557 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
562 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
571 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
572 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
573 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
574 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
575 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
576
577 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [Op_RegN]->Remove(i);
594 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
596 idealreg2debugmask [Op_RegF]->Remove(i); // masks
597 idealreg2debugmask [Op_RegD]->Remove(i);
598 idealreg2debugmask [Op_RegP]->Remove(i);
599
600 idealreg2mhdebugmask[Op_RegN]->Remove(i);
601 idealreg2mhdebugmask[Op_RegI]->Remove(i);
602 idealreg2mhdebugmask[Op_RegL]->Remove(i);
603 idealreg2mhdebugmask[Op_RegF]->Remove(i);
604 idealreg2mhdebugmask[Op_RegD]->Remove(i);
605 idealreg2mhdebugmask[Op_RegP]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
638 // Find the procedure Start Node
639 StartNode *start = C->start();
640 assert( start, "Expect a start node" );
641
642 // Save argument registers in the trampolining stubs
643 if( C->save_argument_registers() )
644 for( i = 0; i < _last_Mach_Reg; i++ )
645 if( is_spillable_arg(i) )
646 soe_cnt++;
647
648 // Input RegMask array shared by all Returns.
649 // The type for doubles and longs has a count of 2, but
650 // there is only 1 returned value
651 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
652 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
653 // Returns have 0 or 1 returned values depending on call signature.
654 // Return register is specified by return_value in the AD file.
655 if (ret_edge_cnt > TypeFunc::Parms)
656 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
657
658 // Input RegMask array shared by all Rethrows.
659 uint reth_edge_cnt = TypeFunc::Parms+1;
660 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
661 // Rethrow takes exception oop only, but in the argument 0 slot.
662 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)];
663 #ifdef _LP64
664 // Need two slots for ptrs in 64-bit land
665 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1));
666 #endif
667
668 // Input RegMask array shared by all TailCalls
669 uint tail_call_edge_cnt = TypeFunc::Parms+2;
670 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
671
672 // Input RegMask array shared by all TailJumps
673 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
674 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
675
676 // TailCalls have 2 returned values (target & moop), whose masks come
677 // from the usual MachNode/MachOper mechanism. Find a sample
678 // TailCall to extract these masks and put the correct masks into
679 // the tail_call_rms array.
680 for( i=1; i < root->req(); i++ ) {
681 MachReturnNode *m = root->in(i)->as_MachReturn();
682 if( m->ideal_Opcode() == Op_TailCall ) {
683 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
684 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
685 break;
686 }
687 }
688
689 // TailJumps have 2 returned values (target & ex_oop), whose masks come
690 // from the usual MachNode/MachOper mechanism. Find a sample
691 // TailJump to extract these masks and put the correct masks into
692 // the tail_jump_rms array.
693 for( i=1; i < root->req(); i++ ) {
694 MachReturnNode *m = root->in(i)->as_MachReturn();
695 if( m->ideal_Opcode() == Op_TailJump ) {
696 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
697 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
698 break;
699 }
700 }
701
702 // Input RegMask array shared by all Halts
703 uint halt_edge_cnt = TypeFunc::Parms;
704 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
705
706 // Capture the return input masks into each exit flavor
707 for( i=1; i < root->req(); i++ ) {
708 MachReturnNode *exit = root->in(i)->as_MachReturn();
709 switch( exit->ideal_Opcode() ) {
710 case Op_Return : exit->_in_rms = ret_rms; break;
711 case Op_Rethrow : exit->_in_rms = reth_rms; break;
712 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
713 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
714 case Op_Halt : exit->_in_rms = halt_rms; break;
715 default : ShouldNotReachHere();
716 }
717 }
718
719 // Next unused projection number from Start.
720 int proj_cnt = C->tf()->domain()->cnt();
721
722 // Do all the save-on-entry registers. Make projections from Start for
723 // them, and give them a use at the exit points. To the allocator, they
724 // look like incoming register arguments.
725 for( i = 0; i < _last_Mach_Reg; i++ ) {
726 if( is_save_on_entry(i) ) {
727
728 // Add the save-on-entry to the mask array
729 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
730 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
731 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
732 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
733 // Halts need the SOE registers, but only in the stack as debug info.
734 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
735 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
736
737 Node *mproj;
738
739 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
740 // into a single RegD.
741 if( (i&1) == 0 &&
742 _register_save_type[i ] == Op_RegF &&
743 _register_save_type[i+1] == Op_RegF &&
744 is_save_on_entry(i+1) ) {
745 // Add other bit for double
746 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
747 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
748 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
749 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
750 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
751 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
752 proj_cnt += 2; // Skip 2 for doubles
753 }
754 else if( (i&1) == 1 && // Else check for high half of double
755 _register_save_type[i-1] == Op_RegF &&
756 _register_save_type[i ] == Op_RegF &&
757 is_save_on_entry(i-1) ) {
758 ret_rms [ ret_edge_cnt] = RegMask::Empty;
759 reth_rms [ reth_edge_cnt] = RegMask::Empty;
760 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
761 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
762 halt_rms [ halt_edge_cnt] = RegMask::Empty;
763 mproj = C->top();
764 }
765 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
766 // into a single RegL.
767 else if( (i&1) == 0 &&
768 _register_save_type[i ] == Op_RegI &&
769 _register_save_type[i+1] == Op_RegI &&
770 is_save_on_entry(i+1) ) {
771 // Add other bit for long
772 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
773 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
774 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
775 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
776 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
777 mproj = new (C) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
778 proj_cnt += 2; // Skip 2 for longs
779 }
780 else if( (i&1) == 1 && // Else check for high half of long
781 _register_save_type[i-1] == Op_RegI &&
782 _register_save_type[i ] == Op_RegI &&
783 is_save_on_entry(i-1) ) {
784 ret_rms [ ret_edge_cnt] = RegMask::Empty;
785 reth_rms [ reth_edge_cnt] = RegMask::Empty;
786 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
787 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
788 halt_rms [ halt_edge_cnt] = RegMask::Empty;
789 mproj = C->top();
790 } else {
791 // Make a projection for it off the Start
792 mproj = new (C) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
793 }
794
795 ret_edge_cnt ++;
796 reth_edge_cnt ++;
797 tail_call_edge_cnt ++;
798 tail_jump_edge_cnt ++;
799 halt_edge_cnt ++;
800
801 // Add a use of the SOE register to all exit paths
802 for( uint j=1; j < root->req(); j++ )
803 root->in(j)->add_req(mproj);
804 } // End of if a save-on-entry register
805 } // End of for all machine registers
806 }
807
808 //------------------------------init_spill_mask--------------------------------
809 void Matcher::init_spill_mask( Node *ret ) {
810 if( idealreg2regmask[Op_RegI] ) return; // One time only init
811
812 OptoReg::c_frame_pointer = c_frame_pointer();
813 c_frame_ptr_mask = c_frame_pointer();
814 #ifdef _LP64
815 // pointers are twice as big
816 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
817 #endif
818
819 // Start at OptoReg::stack0()
820 STACK_ONLY_mask.Clear();
821 OptoReg::Name init = OptoReg::stack2reg(0);
822 // STACK_ONLY_mask is all stack bits
823 OptoReg::Name i;
824 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
825 STACK_ONLY_mask.Insert(i);
826 // Also set the "infinite stack" bit.
827 STACK_ONLY_mask.set_AllStack();
828
829 // Copy the register names over into the shared world
830 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
831 // SharedInfo::regName[i] = regName[i];
832 // Handy RegMasks per machine register
833 mreg2regmask[i].Insert(i);
834 }
835
836 // Grab the Frame Pointer
837 Node *fp = ret->in(TypeFunc::FramePtr);
838 Node *mem = ret->in(TypeFunc::Memory);
839 const TypePtr* atp = TypePtr::BOTTOM;
840 // Share frame pointer while making spill ops
841 set_shared(fp);
842
843 // Compute generic short-offset Loads
844 #ifdef _LP64
845 MachNode *spillCP = match_tree(new (C) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
846 #endif
847 MachNode *spillI = match_tree(new (C) LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
848 MachNode *spillL = match_tree(new (C) LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest,false));
849 MachNode *spillF = match_tree(new (C) LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
850 MachNode *spillD = match_tree(new (C) LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
851 MachNode *spillP = match_tree(new (C) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
852 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
853 spillD != NULL && spillP != NULL, "");
854 // Get the ADLC notion of the right regmask, for each basic type.
855 #ifdef _LP64
856 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
857 #endif
858 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
859 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
860 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
861 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
862 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
863
864 // Vector regmasks.
865 if (Matcher::vector_size_supported(T_BYTE,4)) {
866 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
867 MachNode *spillVectS = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
868 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
869 }
870 if (Matcher::vector_size_supported(T_FLOAT,2)) {
871 MachNode *spillVectD = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
872 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
873 }
874 if (Matcher::vector_size_supported(T_FLOAT,4)) {
875 MachNode *spillVectX = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
876 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
877 }
878 if (Matcher::vector_size_supported(T_FLOAT,8)) {
879 MachNode *spillVectY = match_tree(new (C) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
880 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
881 }
882 }
883
884 #ifdef ASSERT
885 static void match_alias_type(Compile* C, Node* n, Node* m) {
886 if (!VerifyAliases) return; // do not go looking for trouble by default
887 const TypePtr* nat = n->adr_type();
888 const TypePtr* mat = m->adr_type();
889 int nidx = C->get_alias_index(nat);
890 int midx = C->get_alias_index(mat);
891 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
892 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
893 for (uint i = 1; i < n->req(); i++) {
894 Node* n1 = n->in(i);
895 const TypePtr* n1at = n1->adr_type();
896 if (n1at != NULL) {
897 nat = n1at;
898 nidx = C->get_alias_index(n1at);
899 }
900 }
901 }
902 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
903 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
904 switch (n->Opcode()) {
905 case Op_PrefetchRead:
906 case Op_PrefetchWrite:
907 case Op_PrefetchAllocation:
908 nidx = Compile::AliasIdxRaw;
909 nat = TypeRawPtr::BOTTOM;
910 break;
911 }
912 }
913 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
914 switch (n->Opcode()) {
915 case Op_ClearArray:
916 midx = Compile::AliasIdxRaw;
917 mat = TypeRawPtr::BOTTOM;
918 break;
919 }
920 }
921 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
922 switch (n->Opcode()) {
923 case Op_Return:
924 case Op_Rethrow:
925 case Op_Halt:
926 case Op_TailCall:
927 case Op_TailJump:
928 nidx = Compile::AliasIdxBot;
929 nat = TypePtr::BOTTOM;
930 break;
931 }
932 }
933 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
934 switch (n->Opcode()) {
935 case Op_StrComp:
936 case Op_StrEquals:
937 case Op_StrIndexOf:
938 case Op_AryEq:
939 case Op_MemBarVolatile:
940 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
941 case Op_EncodeISOArray:
942 nidx = Compile::AliasIdxTop;
943 nat = NULL;
944 break;
945 }
946 }
947 if (nidx != midx) {
948 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
949 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
950 n->dump();
951 m->dump();
952 }
953 assert(C->subsume_loads() && C->must_alias(nat, midx),
954 "must not lose alias info when matching");
955 }
956 }
957 #endif
958
959
960 //------------------------------MStack-----------------------------------------
961 // State and MStack class used in xform() and find_shared() iterative methods.
962 enum Node_State { Pre_Visit, // node has to be pre-visited
963 Visit, // visit node
964 Post_Visit, // post-visit node
965 Alt_Post_Visit // alternative post-visit path
966 };
967
968 class MStack: public Node_Stack {
969 public:
970 MStack(int size) : Node_Stack(size) { }
971
972 void push(Node *n, Node_State ns) {
973 Node_Stack::push(n, (uint)ns);
974 }
975 void push(Node *n, Node_State ns, Node *parent, int indx) {
976 ++_inode_top;
977 if ((_inode_top + 1) >= _inode_max) grow();
978 _inode_top->node = parent;
979 _inode_top->indx = (uint)indx;
980 ++_inode_top;
981 _inode_top->node = n;
982 _inode_top->indx = (uint)ns;
983 }
984 Node *parent() {
985 pop();
986 return node();
987 }
988 Node_State state() const {
989 return (Node_State)index();
990 }
991 void set_state(Node_State ns) {
992 set_index((uint)ns);
993 }
994 };
995
996
997 //------------------------------xform------------------------------------------
998 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
999 // Node in new-space. Given a new-space Node, recursively walk his children.
1000 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1001 Node *Matcher::xform( Node *n, int max_stack ) {
1002 // Use one stack to keep both: child's node/state and parent's node/index
1003 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1004 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root
1005
1006 while (mstack.is_nonempty()) {
1007 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1008 if (C->failing()) return NULL;
1009 n = mstack.node(); // Leave node on stack
1010 Node_State nstate = mstack.state();
1011 if (nstate == Visit) {
1012 mstack.set_state(Post_Visit);
1013 Node *oldn = n;
1014 // Old-space or new-space check
1015 if (!C->node_arena()->contains(n)) {
1016 // Old space!
1017 Node* m;
1018 if (has_new_node(n)) { // Not yet Label/Reduced
1019 m = new_node(n);
1020 } else {
1021 if (!is_dontcare(n)) { // Matcher can match this guy
1022 // Calls match special. They match alone with no children.
1023 // Their children, the incoming arguments, match normally.
1024 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1025 if (C->failing()) return NULL;
1026 if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1027 } else { // Nothing the matcher cares about
1028 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections?
1029 // Convert to machine-dependent projection
1030 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1031 #ifdef ASSERT
1032 _new2old_map.map(m->_idx, n);
1033 #endif
1034 if (m->in(0) != NULL) // m might be top
1035 collect_null_checks(m, n);
1036 } else { // Else just a regular 'ol guy
1037 m = n->clone(); // So just clone into new-space
1038 #ifdef ASSERT
1039 _new2old_map.map(m->_idx, n);
1040 #endif
1041 // Def-Use edges will be added incrementally as Uses
1042 // of this node are matched.
1043 assert(m->outcnt() == 0, "no Uses of this clone yet");
1044 }
1045 }
1046
1047 set_new_node(n, m); // Map old to new
1048 if (_old_node_note_array != NULL) {
1049 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1050 n->_idx);
1051 C->set_node_notes_at(m->_idx, nn);
1052 }
1053 debug_only(match_alias_type(C, n, m));
1054 }
1055 n = m; // n is now a new-space node
1056 mstack.set_node(n);
1057 }
1058
1059 // New space!
1060 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1061
1062 int i;
1063 // Put precedence edges on stack first (match them last).
1064 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1065 Node *m = oldn->in(i);
1066 if (m == NULL) break;
1067 // set -1 to call add_prec() instead of set_req() during Step1
1068 mstack.push(m, Visit, n, -1);
1069 }
1070
1071 // For constant debug info, I'd rather have unmatched constants.
1072 int cnt = n->req();
1073 JVMState* jvms = n->jvms();
1074 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1075
1076 // Now do only debug info. Clone constants rather than matching.
1077 // Constants are represented directly in the debug info without
1078 // the need for executable machine instructions.
1079 // Monitor boxes are also represented directly.
1080 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1081 Node *m = n->in(i); // Get input
1082 int op = m->Opcode();
1083 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1084 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1085 op == Op_ConF || op == Op_ConD || op == Op_ConL
1086 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1087 ) {
1088 m = m->clone();
1089 #ifdef ASSERT
1090 _new2old_map.map(m->_idx, n);
1091 #endif
1092 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1093 mstack.push(m->in(0), Visit, m, 0);
1094 } else {
1095 mstack.push(m, Visit, n, i);
1096 }
1097 }
1098
1099 // And now walk his children, and convert his inputs to new-space.
1100 for( ; i >= 0; --i ) { // For all normal inputs do
1101 Node *m = n->in(i); // Get input
1102 if(m != NULL)
1103 mstack.push(m, Visit, n, i);
1104 }
1105
1106 }
1107 else if (nstate == Post_Visit) {
1108 // Set xformed input
1109 Node *p = mstack.parent();
1110 if (p != NULL) { // root doesn't have parent
1111 int i = (int)mstack.index();
1112 if (i >= 0)
1113 p->set_req(i, n); // required input
1114 else if (i == -1)
1115 p->add_prec(n); // precedence input
1116 else
1117 ShouldNotReachHere();
1118 }
1119 mstack.pop(); // remove processed node from stack
1120 }
1121 else {
1122 ShouldNotReachHere();
1123 }
1124 } // while (mstack.is_nonempty())
1125 return n; // Return new-space Node
1126 }
1127
1128 //------------------------------warp_outgoing_stk_arg------------------------
1129 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1130 // Convert outgoing argument location to a pre-biased stack offset
1131 if (reg->is_stack()) {
1132 OptoReg::Name warped = reg->reg2stack();
1133 // Adjust the stack slot offset to be the register number used
1134 // by the allocator.
1135 warped = OptoReg::add(begin_out_arg_area, warped);
1136 // Keep track of the largest numbered stack slot used for an arg.
1137 // Largest used slot per call-site indicates the amount of stack
1138 // that is killed by the call.
1139 if( warped >= out_arg_limit_per_call )
1140 out_arg_limit_per_call = OptoReg::add(warped,1);
1141 if (!RegMask::can_represent_arg(warped)) {
1142 C->record_method_not_compilable_all_tiers("unsupported calling sequence");
1143 return OptoReg::Bad;
1144 }
1145 return warped;
1146 }
1147 return OptoReg::as_OptoReg(reg);
1148 }
1149
1150
1151 //------------------------------match_sfpt-------------------------------------
1152 // Helper function to match call instructions. Calls match special.
1153 // They match alone with no children. Their children, the incoming
1154 // arguments, match normally.
1155 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1156 MachSafePointNode *msfpt = NULL;
1157 MachCallNode *mcall = NULL;
1158 uint cnt;
1159 // Split out case for SafePoint vs Call
1160 CallNode *call;
1161 const TypeTuple *domain;
1162 ciMethod* method = NULL;
1163 bool is_method_handle_invoke = false; // for special kill effects
1164 if( sfpt->is_Call() ) {
1165 call = sfpt->as_Call();
1166 domain = call->tf()->domain();
1167 cnt = domain->cnt();
1168
1169 // Match just the call, nothing else
1170 MachNode *m = match_tree(call);
1171 if (C->failing()) return NULL;
1172 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1173
1174 // Copy data from the Ideal SafePoint to the machine version
1175 mcall = m->as_MachCall();
1176
1177 mcall->set_tf( call->tf());
1178 mcall->set_entry_point(call->entry_point());
1179 mcall->set_cnt( call->cnt());
1180
1181 if( mcall->is_MachCallJava() ) {
1182 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1183 const CallJavaNode *call_java = call->as_CallJava();
1184 method = call_java->method();
1185 mcall_java->_method = method;
1186 mcall_java->_bci = call_java->_bci;
1187 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1188 is_method_handle_invoke = call_java->is_method_handle_invoke();
1189 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1190 if (is_method_handle_invoke) {
1191 C->set_has_method_handle_invokes(true);
1192 }
1193 if( mcall_java->is_MachCallStaticJava() )
1194 mcall_java->as_MachCallStaticJava()->_name =
1195 call_java->as_CallStaticJava()->_name;
1196 if( mcall_java->is_MachCallDynamicJava() )
1197 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1198 call_java->as_CallDynamicJava()->_vtable_index;
1199 }
1200 else if( mcall->is_MachCallRuntime() ) {
1201 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1202 }
1203 msfpt = mcall;
1204 }
1205 // This is a non-call safepoint
1206 else {
1207 call = NULL;
1208 domain = NULL;
1209 MachNode *mn = match_tree(sfpt);
1210 if (C->failing()) return NULL;
1211 msfpt = mn->as_MachSafePoint();
1212 cnt = TypeFunc::Parms;
1213 }
1214
1215 // Advertise the correct memory effects (for anti-dependence computation).
1216 msfpt->set_adr_type(sfpt->adr_type());
1217
1218 // Allocate a private array of RegMasks. These RegMasks are not shared.
1219 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1220 // Empty them all.
1221 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt );
1222
1223 // Do all the pre-defined non-Empty register masks
1224 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1225 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1226
1227 // Place first outgoing argument can possibly be put.
1228 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1229 assert( is_even(begin_out_arg_area), "" );
1230 // Compute max outgoing register number per call site.
1231 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1232 // Calls to C may hammer extra stack slots above and beyond any arguments.
1233 // These are usually backing store for register arguments for varargs.
1234 if( call != NULL && call->is_CallRuntime() )
1235 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1236
1237
1238 // Do the normal argument list (parameters) register masks
1239 int argcnt = cnt - TypeFunc::Parms;
1240 if( argcnt > 0 ) { // Skip it all if we have no args
1241 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1242 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1243 int i;
1244 for( i = 0; i < argcnt; i++ ) {
1245 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1246 }
1247 // V-call to pick proper calling convention
1248 call->calling_convention( sig_bt, parm_regs, argcnt );
1249
1250 #ifdef ASSERT
1251 // Sanity check users' calling convention. Really handy during
1252 // the initial porting effort. Fairly expensive otherwise.
1253 { for (int i = 0; i<argcnt; i++) {
1254 if( !parm_regs[i].first()->is_valid() &&
1255 !parm_regs[i].second()->is_valid() ) continue;
1256 VMReg reg1 = parm_regs[i].first();
1257 VMReg reg2 = parm_regs[i].second();
1258 for (int j = 0; j < i; j++) {
1259 if( !parm_regs[j].first()->is_valid() &&
1260 !parm_regs[j].second()->is_valid() ) continue;
1261 VMReg reg3 = parm_regs[j].first();
1262 VMReg reg4 = parm_regs[j].second();
1263 if( !reg1->is_valid() ) {
1264 assert( !reg2->is_valid(), "valid halvsies" );
1265 } else if( !reg3->is_valid() ) {
1266 assert( !reg4->is_valid(), "valid halvsies" );
1267 } else {
1268 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1269 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1270 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1271 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1272 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1273 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1274 }
1275 }
1276 }
1277 }
1278 #endif
1279
1280 // Visit each argument. Compute its outgoing register mask.
1281 // Return results now can have 2 bits returned.
1282 // Compute max over all outgoing arguments both per call-site
1283 // and over the entire method.
1284 for( i = 0; i < argcnt; i++ ) {
1285 // Address of incoming argument mask to fill in
1286 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1287 if( !parm_regs[i].first()->is_valid() &&
1288 !parm_regs[i].second()->is_valid() ) {
1289 continue; // Avoid Halves
1290 }
1291 // Grab first register, adjust stack slots and insert in mask.
1292 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1293 if (OptoReg::is_valid(reg1))
1294 rm->Insert( reg1 );
1295 // Grab second register (if any), adjust stack slots and insert in mask.
1296 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1297 if (OptoReg::is_valid(reg2))
1298 rm->Insert( reg2 );
1299 } // End of for all arguments
1300
1301 // Compute number of stack slots needed to restore stack in case of
1302 // Pascal-style argument popping.
1303 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1304 }
1305
1306 // Compute the max stack slot killed by any call. These will not be
1307 // available for debug info, and will be used to adjust FIRST_STACK_mask
1308 // after all call sites have been visited.
1309 if( _out_arg_limit < out_arg_limit_per_call)
1310 _out_arg_limit = out_arg_limit_per_call;
1311
1312 if (mcall) {
1313 // Kill the outgoing argument area, including any non-argument holes and
1314 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1315 // Since the max-per-method covers the max-per-call-site and debug info
1316 // is excluded on the max-per-method basis, debug info cannot land in
1317 // this killed area.
1318 uint r_cnt = mcall->tf()->range()->cnt();
1319 MachProjNode *proj = new (C) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1320 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1321 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence");
1322 } else {
1323 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1324 proj->_rout.Insert(OptoReg::Name(i));
1325 }
1326 if (proj->_rout.is_NotEmpty()) {
1327 push_projection(proj);
1328 }
1329 }
1330 // Transfer the safepoint information from the call to the mcall
1331 // Move the JVMState list
1332 msfpt->set_jvms(sfpt->jvms());
1333 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1334 jvms->set_map(sfpt);
1335 }
1336
1337 // Debug inputs begin just after the last incoming parameter
1338 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1339 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1340
1341 // Move the OopMap
1342 msfpt->_oop_map = sfpt->_oop_map;
1343
1344 // Add additional edges.
1345 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1346 // For these calls we can not add MachConstantBase in expand(), as the
1347 // ins are not complete then.
1348 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1349 if (msfpt->jvms() &&
1350 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1351 // We added an edge before jvms, so we must adapt the position of the ins.
1352 msfpt->jvms()->adapt_position(+1);
1353 }
1354 }
1355
1356 // Registers killed by the call are set in the local scheduling pass
1357 // of Global Code Motion.
1358 return msfpt;
1359 }
1360
1361 //---------------------------match_tree----------------------------------------
1362 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1363 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1364 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1365 // a Load's result RegMask for memoization in idealreg2regmask[]
1366 MachNode *Matcher::match_tree( const Node *n ) {
1367 assert( n->Opcode() != Op_Phi, "cannot match" );
1368 assert( !n->is_block_start(), "cannot match" );
1369 // Set the mark for all locally allocated State objects.
1370 // When this call returns, the _states_arena arena will be reset
1371 // freeing all State objects.
1372 ResourceMark rm( &_states_arena );
1373
1374 LabelRootDepth = 0;
1375
1376 // StoreNodes require their Memory input to match any LoadNodes
1377 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1378 #ifdef ASSERT
1379 Node* save_mem_node = _mem_node;
1380 _mem_node = n->is_Store() ? (Node*)n : NULL;
1381 #endif
1382 // State object for root node of match tree
1383 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1384 State *s = new (&_states_arena) State;
1385 s->_kids[0] = NULL;
1386 s->_kids[1] = NULL;
1387 s->_leaf = (Node*)n;
1388 // Label the input tree, allocating labels from top-level arena
1389 Label_Root( n, s, n->in(0), mem );
1390 if (C->failing()) return NULL;
1391
1392 // The minimum cost match for the whole tree is found at the root State
1393 uint mincost = max_juint;
1394 uint cost = max_juint;
1395 uint i;
1396 for( i = 0; i < NUM_OPERANDS; i++ ) {
1397 if( s->valid(i) && // valid entry and
1398 s->_cost[i] < cost && // low cost and
1399 s->_rule[i] >= NUM_OPERANDS ) // not an operand
1400 cost = s->_cost[mincost=i];
1401 }
1402 if (mincost == max_juint) {
1403 #ifndef PRODUCT
1404 tty->print("No matching rule for:");
1405 s->dump();
1406 #endif
1407 Matcher::soft_match_failure();
1408 return NULL;
1409 }
1410 // Reduce input tree based upon the state labels to machine Nodes
1411 MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1412 #ifdef ASSERT
1413 _old2new_map.map(n->_idx, m);
1414 _new2old_map.map(m->_idx, (Node*)n);
1415 #endif
1416
1417 // Add any Matcher-ignored edges
1418 uint cnt = n->req();
1419 uint start = 1;
1420 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1421 if( n->is_AddP() ) {
1422 assert( mem == (Node*)1, "" );
1423 start = AddPNode::Base+1;
1424 }
1425 for( i = start; i < cnt; i++ ) {
1426 if( !n->match_edge(i) ) {
1427 if( i < m->req() )
1428 m->ins_req( i, n->in(i) );
1429 else
1430 m->add_req( n->in(i) );
1431 }
1432 }
1433
1434 debug_only( _mem_node = save_mem_node; )
1435 return m;
1436 }
1437
1438
1439 //------------------------------match_into_reg---------------------------------
1440 // Choose to either match this Node in a register or part of the current
1441 // match tree. Return true for requiring a register and false for matching
1442 // as part of the current match tree.
1443 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1444
1445 const Type *t = m->bottom_type();
1446
1447 if (t->singleton()) {
1448 // Never force constants into registers. Allow them to match as
1449 // constants or registers. Copies of the same value will share
1450 // the same register. See find_shared_node.
1451 return false;
1452 } else { // Not a constant
1453 // Stop recursion if they have different Controls.
1454 Node* m_control = m->in(0);
1455 // Control of load's memory can post-dominates load's control.
1456 // So use it since load can't float above its memory.
1457 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1458 if (control && m_control && control != m_control && control != mem_control) {
1459
1460 // Actually, we can live with the most conservative control we
1461 // find, if it post-dominates the others. This allows us to
1462 // pick up load/op/store trees where the load can float a little
1463 // above the store.
1464 Node *x = control;
1465 const uint max_scan = 6; // Arbitrary scan cutoff
1466 uint j;
1467 for (j=0; j<max_scan; j++) {
1468 if (x->is_Region()) // Bail out at merge points
1469 return true;
1470 x = x->in(0);
1471 if (x == m_control) // Does 'control' post-dominate
1472 break; // m->in(0)? If so, we can use it
1473 if (x == mem_control) // Does 'control' post-dominate
1474 break; // mem_control? If so, we can use it
1475 }
1476 if (j == max_scan) // No post-domination before scan end?
1477 return true; // Then break the match tree up
1478 }
1479 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1480 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1481 // These are commonly used in address expressions and can
1482 // efficiently fold into them on X64 in some cases.
1483 return false;
1484 }
1485 }
1486
1487 // Not forceable cloning. If shared, put it into a register.
1488 return shared;
1489 }
1490
1491
1492 //------------------------------Instruction Selection--------------------------
1493 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1494 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1495 // things the Matcher does not match (e.g., Memory), and things with different
1496 // Controls (hence forced into different blocks). We pass in the Control
1497 // selected for this entire State tree.
1498
1499 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1500 // Store and the Load must have identical Memories (as well as identical
1501 // pointers). Since the Matcher does not have anything for Memory (and
1502 // does not handle DAGs), I have to match the Memory input myself. If the
1503 // Tree root is a Store, I require all Loads to have the identical memory.
1504 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1505 // Since Label_Root is a recursive function, its possible that we might run
1506 // out of stack space. See bugs 6272980 & 6227033 for more info.
1507 LabelRootDepth++;
1508 if (LabelRootDepth > MaxLabelRootDepth) {
1509 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth");
1510 return NULL;
1511 }
1512 uint care = 0; // Edges matcher cares about
1513 uint cnt = n->req();
1514 uint i = 0;
1515
1516 // Examine children for memory state
1517 // Can only subsume a child into your match-tree if that child's memory state
1518 // is not modified along the path to another input.
1519 // It is unsafe even if the other inputs are separate roots.
1520 Node *input_mem = NULL;
1521 for( i = 1; i < cnt; i++ ) {
1522 if( !n->match_edge(i) ) continue;
1523 Node *m = n->in(i); // Get ith input
1524 assert( m, "expect non-null children" );
1525 if( m->is_Load() ) {
1526 if( input_mem == NULL ) {
1527 input_mem = m->in(MemNode::Memory);
1528 } else if( input_mem != m->in(MemNode::Memory) ) {
1529 input_mem = NodeSentinel;
1530 }
1531 }
1532 }
1533
1534 for( i = 1; i < cnt; i++ ){// For my children
1535 if( !n->match_edge(i) ) continue;
1536 Node *m = n->in(i); // Get ith input
1537 // Allocate states out of a private arena
1538 State *s = new (&_states_arena) State;
1539 svec->_kids[care++] = s;
1540 assert( care <= 2, "binary only for now" );
1541
1542 // Recursively label the State tree.
1543 s->_kids[0] = NULL;
1544 s->_kids[1] = NULL;
1545 s->_leaf = m;
1546
1547 // Check for leaves of the State Tree; things that cannot be a part of
1548 // the current tree. If it finds any, that value is matched as a
1549 // register operand. If not, then the normal matching is used.
1550 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1551 //
1552 // Stop recursion if this is LoadNode and the root of this tree is a
1553 // StoreNode and the load & store have different memories.
1554 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1555 // Can NOT include the match of a subtree when its memory state
1556 // is used by any of the other subtrees
1557 (input_mem == NodeSentinel) ) {
1558 #ifndef PRODUCT
1559 // Print when we exclude matching due to different memory states at input-loads
1560 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1561 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) {
1562 tty->print_cr("invalid input_mem");
1563 }
1564 #endif
1565 // Switch to a register-only opcode; this value must be in a register
1566 // and cannot be subsumed as part of a larger instruction.
1567 s->DFA( m->ideal_reg(), m );
1568
1569 } else {
1570 // If match tree has no control and we do, adopt it for entire tree
1571 if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1572 control = m->in(0); // Pick up control
1573 // Else match as a normal part of the match tree.
1574 control = Label_Root(m,s,control,mem);
1575 if (C->failing()) return NULL;
1576 }
1577 }
1578
1579
1580 // Call DFA to match this node, and return
1581 svec->DFA( n->Opcode(), n );
1582
1583 #ifdef ASSERT
1584 uint x;
1585 for( x = 0; x < _LAST_MACH_OPER; x++ )
1586 if( svec->valid(x) )
1587 break;
1588
1589 if (x >= _LAST_MACH_OPER) {
1590 n->dump();
1591 svec->dump();
1592 assert( false, "bad AD file" );
1593 }
1594 #endif
1595 return control;
1596 }
1597
1598
1599 // Con nodes reduced using the same rule can share their MachNode
1600 // which reduces the number of copies of a constant in the final
1601 // program. The register allocator is free to split uses later to
1602 // split live ranges.
1603 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1604 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1605
1606 // See if this Con has already been reduced using this rule.
1607 if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1608 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1609 if (last != NULL && rule == last->rule()) {
1610 // Don't expect control change for DecodeN
1611 if (leaf->is_DecodeNarrowPtr())
1612 return last;
1613 // Get the new space root.
1614 Node* xroot = new_node(C->root());
1615 if (xroot == NULL) {
1616 // This shouldn't happen give the order of matching.
1617 return NULL;
1618 }
1619
1620 // Shared constants need to have their control be root so they
1621 // can be scheduled properly.
1622 Node* control = last->in(0);
1623 if (control != xroot) {
1624 if (control == NULL || control == C->root()) {
1625 last->set_req(0, xroot);
1626 } else {
1627 assert(false, "unexpected control");
1628 return NULL;
1629 }
1630 }
1631 return last;
1632 }
1633 return NULL;
1634 }
1635
1636
1637 //------------------------------ReduceInst-------------------------------------
1638 // Reduce a State tree (with given Control) into a tree of MachNodes.
1639 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1640 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1641 // Each MachNode has a number of complicated MachOper operands; each
1642 // MachOper also covers a further tree of Ideal Nodes.
1643
1644 // The root of the Ideal match tree is always an instruction, so we enter
1645 // the recursion here. After building the MachNode, we need to recurse
1646 // the tree checking for these cases:
1647 // (1) Child is an instruction -
1648 // Build the instruction (recursively), add it as an edge.
1649 // Build a simple operand (register) to hold the result of the instruction.
1650 // (2) Child is an interior part of an instruction -
1651 // Skip over it (do nothing)
1652 // (3) Child is the start of a operand -
1653 // Build the operand, place it inside the instruction
1654 // Call ReduceOper.
1655 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1656 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1657
1658 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1659 if (shared_node != NULL) {
1660 return shared_node;
1661 }
1662
1663 // Build the object to represent this state & prepare for recursive calls
1664 MachNode *mach = s->MachNodeGenerator( rule, C );
1665 guarantee(mach != NULL, "Missing MachNode");
1666 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C );
1667 assert( mach->_opnds[0] != NULL, "Missing result operand" );
1668 Node *leaf = s->_leaf;
1669 // Check for instruction or instruction chain rule
1670 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1671 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1672 "duplicating node that's already been matched");
1673 // Instruction
1674 mach->add_req( leaf->in(0) ); // Set initial control
1675 // Reduce interior of complex instruction
1676 ReduceInst_Interior( s, rule, mem, mach, 1 );
1677 } else {
1678 // Instruction chain rules are data-dependent on their inputs
1679 mach->add_req(0); // Set initial control to none
1680 ReduceInst_Chain_Rule( s, rule, mem, mach );
1681 }
1682
1683 // If a Memory was used, insert a Memory edge
1684 if( mem != (Node*)1 ) {
1685 mach->ins_req(MemNode::Memory,mem);
1686 #ifdef ASSERT
1687 // Verify adr type after matching memory operation
1688 const MachOper* oper = mach->memory_operand();
1689 if (oper != NULL && oper != (MachOper*)-1) {
1690 // It has a unique memory operand. Find corresponding ideal mem node.
1691 Node* m = NULL;
1692 if (leaf->is_Mem()) {
1693 m = leaf;
1694 } else {
1695 m = _mem_node;
1696 assert(m != NULL && m->is_Mem(), "expecting memory node");
1697 }
1698 const Type* mach_at = mach->adr_type();
1699 // DecodeN node consumed by an address may have different type
1700 // then its input. Don't compare types for such case.
1701 if (m->adr_type() != mach_at &&
1702 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1703 m->in(MemNode::Address)->is_AddP() &&
1704 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() ||
1705 m->in(MemNode::Address)->is_AddP() &&
1706 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1707 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) {
1708 mach_at = m->adr_type();
1709 }
1710 if (m->adr_type() != mach_at) {
1711 m->dump();
1712 tty->print_cr("mach:");
1713 mach->dump(1);
1714 }
1715 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1716 }
1717 #endif
1718 }
1719
1720 // If the _leaf is an AddP, insert the base edge
1721 if (leaf->is_AddP()) {
1722 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1723 }
1724
1725 uint number_of_projections_prior = number_of_projections();
1726
1727 // Perform any 1-to-many expansions required
1728 MachNode *ex = mach->Expand(s, _projection_list, mem);
1729 if (ex != mach) {
1730 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1731 if( ex->in(1)->is_Con() )
1732 ex->in(1)->set_req(0, C->root());
1733 // Remove old node from the graph
1734 for( uint i=0; i<mach->req(); i++ ) {
1735 mach->set_req(i,NULL);
1736 }
1737 #ifdef ASSERT
1738 _new2old_map.map(ex->_idx, s->_leaf);
1739 #endif
1740 }
1741
1742 // PhaseChaitin::fixup_spills will sometimes generate spill code
1743 // via the matcher. By the time, nodes have been wired into the CFG,
1744 // and any further nodes generated by expand rules will be left hanging
1745 // in space, and will not get emitted as output code. Catch this.
1746 // Also, catch any new register allocation constraints ("projections")
1747 // generated belatedly during spill code generation.
1748 if (_allocation_started) {
1749 guarantee(ex == mach, "no expand rules during spill generation");
1750 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1751 }
1752
1753 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1754 // Record the con for sharing
1755 _shared_nodes.map(leaf->_idx, ex);
1756 }
1757
1758 return ex;
1759 }
1760
1761 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1762 // 'op' is what I am expecting to receive
1763 int op = _leftOp[rule];
1764 // Operand type to catch childs result
1765 // This is what my child will give me.
1766 int opnd_class_instance = s->_rule[op];
1767 // Choose between operand class or not.
1768 // This is what I will receive.
1769 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1770 // New rule for child. Chase operand classes to get the actual rule.
1771 int newrule = s->_rule[catch_op];
1772
1773 if( newrule < NUM_OPERANDS ) {
1774 // Chain from operand or operand class, may be output of shared node
1775 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1776 "Bad AD file: Instruction chain rule must chain from operand");
1777 // Insert operand into array of operands for this instruction
1778 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C );
1779
1780 ReduceOper( s, newrule, mem, mach );
1781 } else {
1782 // Chain from the result of an instruction
1783 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1784 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C );
1785 Node *mem1 = (Node*)1;
1786 debug_only(Node *save_mem_node = _mem_node;)
1787 mach->add_req( ReduceInst(s, newrule, mem1) );
1788 debug_only(_mem_node = save_mem_node;)
1789 }
1790 return;
1791 }
1792
1793
1794 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1795 if( s->_leaf->is_Load() ) {
1796 Node *mem2 = s->_leaf->in(MemNode::Memory);
1797 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1798 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1799 mem = mem2;
1800 }
1801 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1802 if( mach->in(0) == NULL )
1803 mach->set_req(0, s->_leaf->in(0));
1804 }
1805
1806 // Now recursively walk the state tree & add operand list.
1807 for( uint i=0; i<2; i++ ) { // binary tree
1808 State *newstate = s->_kids[i];
1809 if( newstate == NULL ) break; // Might only have 1 child
1810 // 'op' is what I am expecting to receive
1811 int op;
1812 if( i == 0 ) {
1813 op = _leftOp[rule];
1814 } else {
1815 op = _rightOp[rule];
1816 }
1817 // Operand type to catch childs result
1818 // This is what my child will give me.
1819 int opnd_class_instance = newstate->_rule[op];
1820 // Choose between operand class or not.
1821 // This is what I will receive.
1822 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1823 // New rule for child. Chase operand classes to get the actual rule.
1824 int newrule = newstate->_rule[catch_op];
1825
1826 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1827 // Operand/operandClass
1828 // Insert operand into array of operands for this instruction
1829 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C );
1830 ReduceOper( newstate, newrule, mem, mach );
1831
1832 } else { // Child is internal operand or new instruction
1833 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1834 // internal operand --> call ReduceInst_Interior
1835 // Interior of complex instruction. Do nothing but recurse.
1836 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1837 } else {
1838 // instruction --> call build operand( ) to catch result
1839 // --> ReduceInst( newrule )
1840 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C );
1841 Node *mem1 = (Node*)1;
1842 debug_only(Node *save_mem_node = _mem_node;)
1843 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1844 debug_only(_mem_node = save_mem_node;)
1845 }
1846 }
1847 assert( mach->_opnds[num_opnds-1], "" );
1848 }
1849 return num_opnds;
1850 }
1851
1852 // This routine walks the interior of possible complex operands.
1853 // At each point we check our children in the match tree:
1854 // (1) No children -
1855 // We are a leaf; add _leaf field as an input to the MachNode
1856 // (2) Child is an internal operand -
1857 // Skip over it ( do nothing )
1858 // (3) Child is an instruction -
1859 // Call ReduceInst recursively and
1860 // and instruction as an input to the MachNode
1861 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1862 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1863 State *kid = s->_kids[0];
1864 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1865
1866 // Leaf? And not subsumed?
1867 if( kid == NULL && !_swallowed[rule] ) {
1868 mach->add_req( s->_leaf ); // Add leaf pointer
1869 return; // Bail out
1870 }
1871
1872 if( s->_leaf->is_Load() ) {
1873 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1874 mem = s->_leaf->in(MemNode::Memory);
1875 debug_only(_mem_node = s->_leaf;)
1876 }
1877 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1878 if( !mach->in(0) )
1879 mach->set_req(0,s->_leaf->in(0));
1880 else {
1881 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1882 }
1883 }
1884
1885 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree
1886 int newrule;
1887 if( i == 0)
1888 newrule = kid->_rule[_leftOp[rule]];
1889 else
1890 newrule = kid->_rule[_rightOp[rule]];
1891
1892 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1893 // Internal operand; recurse but do nothing else
1894 ReduceOper( kid, newrule, mem, mach );
1895
1896 } else { // Child is a new instruction
1897 // Reduce the instruction, and add a direct pointer from this
1898 // machine instruction to the newly reduced one.
1899 Node *mem1 = (Node*)1;
1900 debug_only(Node *save_mem_node = _mem_node;)
1901 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1902 debug_only(_mem_node = save_mem_node;)
1903 }
1904 }
1905 }
1906
1907
1908 // -------------------------------------------------------------------------
1909 // Java-Java calling convention
1910 // (what you use when Java calls Java)
1911
1912 //------------------------------find_receiver----------------------------------
1913 // For a given signature, return the OptoReg for parameter 0.
1914 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1915 VMRegPair regs;
1916 BasicType sig_bt = T_OBJECT;
1917 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1918 // Return argument 0 register. In the LP64 build pointers
1919 // take 2 registers, but the VM wants only the 'main' name.
1920 return OptoReg::as_OptoReg(regs.first());
1921 }
1922
1923 // This function identifies sub-graphs in which a 'load' node is
1924 // input to two different nodes, and such that it can be matched
1925 // with BMI instructions like blsi, blsr, etc.
1926 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1927 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1928 // refers to the same node.
1929 #ifdef X86
1930 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1931 // This is a temporary solution until we make DAGs expressible in ADL.
1932 template<typename ConType>
1933 class FusedPatternMatcher {
1934 Node* _op1_node;
1935 Node* _mop_node;
1936 int _con_op;
1937
1938 static int match_next(Node* n, int next_op, int next_op_idx) {
1939 if (n->in(1) == NULL || n->in(2) == NULL) {
1940 return -1;
1941 }
1942
1943 if (next_op_idx == -1) { // n is commutative, try rotations
1944 if (n->in(1)->Opcode() == next_op) {
1945 return 1;
1946 } else if (n->in(2)->Opcode() == next_op) {
1947 return 2;
1948 }
1949 } else {
1950 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1951 if (n->in(next_op_idx)->Opcode() == next_op) {
1952 return next_op_idx;
1953 }
1954 }
1955 return -1;
1956 }
1957 public:
1958 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1959 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1960
1961 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1962 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1963 typename ConType::NativeType con_value) {
1964 if (_op1_node->Opcode() != op1) {
1965 return false;
1966 }
1967 if (_mop_node->outcnt() > 2) {
1968 return false;
1969 }
1970 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1971 if (op1_op2_idx == -1) {
1972 return false;
1973 }
1974 // Memory operation must be the other edge
1975 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1976
1977 // Check that the mop node is really what we want
1978 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1979 Node *op2_node = _op1_node->in(op1_op2_idx);
1980 if (op2_node->outcnt() > 1) {
1981 return false;
1982 }
1983 assert(op2_node->Opcode() == op2, "Should be");
1984 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
1985 if (op2_con_idx == -1) {
1986 return false;
1987 }
1988 // Memory operation must be the other edge
1989 int op2_mop_idx = (op2_con_idx & 1) + 1;
1990 // Check that the memory operation is the same node
1991 if (op2_node->in(op2_mop_idx) == _mop_node) {
1992 // Now check the constant
1993 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1994 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1995 return true;
1996 }
1997 }
1998 }
1999 return false;
2000 }
2001 };
2002
2003
2004 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2005 if (n != NULL && m != NULL) {
2006 if (m->Opcode() == Op_LoadI) {
2007 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2008 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2009 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2010 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2011 } else if (m->Opcode() == Op_LoadL) {
2012 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2013 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2014 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2015 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2016 }
2017 }
2018 return false;
2019 }
2020 #endif // X86
2021
2022 // A method-klass-holder may be passed in the inline_cache_reg
2023 // and then expanded into the inline_cache_reg and a method_oop register
2024 // defined in ad_<arch>.cpp
2025
2026
2027 //------------------------------find_shared------------------------------------
2028 // Set bits if Node is shared or otherwise a root
2029 void Matcher::find_shared( Node *n ) {
2030 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2031 MStack mstack(C->live_nodes() * 2);
2032 // Mark nodes as address_visited if they are inputs to an address expression
2033 VectorSet address_visited(Thread::current()->resource_area());
2034 mstack.push(n, Visit); // Don't need to pre-visit root node
2035 while (mstack.is_nonempty()) {
2036 n = mstack.node(); // Leave node on stack
2037 Node_State nstate = mstack.state();
2038 uint nop = n->Opcode();
2039 if (nstate == Pre_Visit) {
2040 if (address_visited.test(n->_idx)) { // Visited in address already?
2041 // Flag as visited and shared now.
2042 set_visited(n);
2043 }
2044 if (is_visited(n)) { // Visited already?
2045 // Node is shared and has no reason to clone. Flag it as shared.
2046 // This causes it to match into a register for the sharing.
2047 set_shared(n); // Flag as shared and
2048 if (n->is_DecodeNarrowPtr()) {
2049 // Oop field/array element loads must be shared but since
2050 // they are shared through a DecodeN they may appear to have
2051 // a single use so force sharing here.
2052 set_shared(n->in(1));
2053 }
2054 mstack.pop(); // remove node from stack
2055 continue;
2056 }
2057 nstate = Visit; // Not already visited; so visit now
2058 }
2059 if (nstate == Visit) {
2060 mstack.set_state(Post_Visit);
2061 set_visited(n); // Flag as visited now
2062 bool mem_op = false;
2063
2064 switch( nop ) { // Handle some opcodes special
2065 case Op_Phi: // Treat Phis as shared roots
2066 case Op_Parm:
2067 case Op_Proj: // All handled specially during matching
2068 case Op_SafePointScalarObject:
2069 set_shared(n);
2070 set_dontcare(n);
2071 break;
2072 case Op_If:
2073 case Op_CountedLoopEnd:
2074 mstack.set_state(Alt_Post_Visit); // Alternative way
2075 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2076 // with matching cmp/branch in 1 instruction. The Matcher needs the
2077 // Bool and CmpX side-by-side, because it can only get at constants
2078 // that are at the leaves of Match trees, and the Bool's condition acts
2079 // as a constant here.
2080 mstack.push(n->in(1), Visit); // Clone the Bool
2081 mstack.push(n->in(0), Pre_Visit); // Visit control input
2082 continue; // while (mstack.is_nonempty())
2083 case Op_ConvI2D: // These forms efficiently match with a prior
2084 case Op_ConvI2F: // Load but not a following Store
2085 if( n->in(1)->is_Load() && // Prior load
2086 n->outcnt() == 1 && // Not already shared
2087 n->unique_out()->is_Store() ) // Following store
2088 set_shared(n); // Force it to be a root
2089 break;
2090 case Op_ReverseBytesI:
2091 case Op_ReverseBytesL:
2092 if( n->in(1)->is_Load() && // Prior load
2093 n->outcnt() == 1 ) // Not already shared
2094 set_shared(n); // Force it to be a root
2095 break;
2096 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2097 case Op_IfFalse:
2098 case Op_IfTrue:
2099 case Op_MachProj:
2100 case Op_MergeMem:
2101 case Op_Catch:
2102 case Op_CatchProj:
2103 case Op_CProj:
2104 case Op_JumpProj:
2105 case Op_JProj:
2106 case Op_NeverBranch:
2107 set_dontcare(n);
2108 break;
2109 case Op_Jump:
2110 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2111 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2112 continue; // while (mstack.is_nonempty())
2113 case Op_StrComp:
2114 case Op_StrEquals:
2115 case Op_StrIndexOf:
2116 case Op_AryEq:
2117 case Op_EncodeISOArray:
2118 set_shared(n); // Force result into register (it will be anyways)
2119 break;
2120 case Op_ConP: { // Convert pointers above the centerline to NUL
2121 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2122 const TypePtr* tp = tn->type()->is_ptr();
2123 if (tp->_ptr == TypePtr::AnyNull) {
2124 tn->set_type(TypePtr::NULL_PTR);
2125 }
2126 break;
2127 }
2128 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2129 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2130 const TypePtr* tp = tn->type()->make_ptr();
2131 if (tp && tp->_ptr == TypePtr::AnyNull) {
2132 tn->set_type(TypeNarrowOop::NULL_PTR);
2133 }
2134 break;
2135 }
2136 case Op_Binary: // These are introduced in the Post_Visit state.
2137 ShouldNotReachHere();
2138 break;
2139 case Op_ClearArray:
2140 case Op_SafePoint:
2141 mem_op = true;
2142 break;
2143 default:
2144 if( n->is_Store() ) {
2145 // Do match stores, despite no ideal reg
2146 mem_op = true;
2147 break;
2148 }
2149 if( n->is_Mem() ) { // Loads and LoadStores
2150 mem_op = true;
2151 // Loads must be root of match tree due to prior load conflict
2152 if( C->subsume_loads() == false )
2153 set_shared(n);
2154 }
2155 // Fall into default case
2156 if( !n->ideal_reg() )
2157 set_dontcare(n); // Unmatchable Nodes
2158 } // end_switch
2159
2160 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2161 Node *m = n->in(i); // Get ith input
2162 if (m == NULL) continue; // Ignore NULLs
2163 uint mop = m->Opcode();
2164
2165 // Must clone all producers of flags, or we will not match correctly.
2166 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2167 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2168 // are also there, so we may match a float-branch to int-flags and
2169 // expect the allocator to haul the flags from the int-side to the
2170 // fp-side. No can do.
2171 if( _must_clone[mop] ) {
2172 mstack.push(m, Visit);
2173 continue; // for(int i = ...)
2174 }
2175
2176 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2177 #ifdef X86
2178 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2179 mstack.push(m, Visit);
2180 continue;
2181 }
2182 #endif
2183
2184 // Clone addressing expressions as they are "free" in memory access instructions
2185 if( mem_op && i == MemNode::Address && mop == Op_AddP ) {
2186 // Some inputs for address expression are not put on stack
2187 // to avoid marking them as shared and forcing them into register
2188 // if they are used only in address expressions.
2189 // But they should be marked as shared if there are other uses
2190 // besides address expressions.
2191
2192 Node *off = m->in(AddPNode::Offset);
2193 if( off->is_Con() &&
2194 // When there are other uses besides address expressions
2195 // put it on stack and mark as shared.
2196 !is_visited(m) ) {
2197 address_visited.test_set(m->_idx); // Flag as address_visited
2198 Node *adr = m->in(AddPNode::Address);
2199
2200 // Intel, ARM and friends can handle 2 adds in addressing mode
2201 if( clone_shift_expressions && adr->is_AddP() &&
2202 // AtomicAdd is not an addressing expression.
2203 // Cheap to find it by looking for screwy base.
2204 !adr->in(AddPNode::Base)->is_top() &&
2205 // Are there other uses besides address expressions?
2206 !is_visited(adr) ) {
2207 address_visited.set(adr->_idx); // Flag as address_visited
2208 Node *shift = adr->in(AddPNode::Offset);
2209 // Check for shift by small constant as well
2210 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() &&
2211 shift->in(2)->get_int() <= 3 &&
2212 // Are there other uses besides address expressions?
2213 !is_visited(shift) ) {
2214 address_visited.set(shift->_idx); // Flag as address_visited
2215 mstack.push(shift->in(2), Visit);
2216 Node *conv = shift->in(1);
2217 #ifdef _LP64
2218 // Allow Matcher to match the rule which bypass
2219 // ConvI2L operation for an array index on LP64
2220 // if the index value is positive.
2221 if( conv->Opcode() == Op_ConvI2L &&
2222 conv->as_Type()->type()->is_long()->_lo >= 0 &&
2223 // Are there other uses besides address expressions?
2224 !is_visited(conv) ) {
2225 address_visited.set(conv->_idx); // Flag as address_visited
2226 mstack.push(conv->in(1), Pre_Visit);
2227 } else
2228 #endif
2229 mstack.push(conv, Pre_Visit);
2230 } else {
2231 mstack.push(shift, Pre_Visit);
2232 }
2233 mstack.push(adr->in(AddPNode::Address), Pre_Visit);
2234 mstack.push(adr->in(AddPNode::Base), Pre_Visit);
2235 } else { // Sparc, Alpha, PPC and friends
2236 mstack.push(adr, Pre_Visit);
2237 }
2238
2239 // Clone X+offset as it also folds into most addressing expressions
2240 mstack.push(off, Visit);
2241 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2242 continue; // for(int i = ...)
2243 } // if( off->is_Con() )
2244 } // if( mem_op &&
2245 mstack.push(m, Pre_Visit);
2246 } // for(int i = ...)
2247 }
2248 else if (nstate == Alt_Post_Visit) {
2249 mstack.pop(); // Remove node from stack
2250 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2251 // shared and all users of the Bool need to move the Cmp in parallel.
2252 // This leaves both the Bool and the If pointing at the Cmp. To
2253 // prevent the Matcher from trying to Match the Cmp along both paths
2254 // BoolNode::match_edge always returns a zero.
2255
2256 // We reorder the Op_If in a pre-order manner, so we can visit without
2257 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2258 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2259 }
2260 else if (nstate == Post_Visit) {
2261 mstack.pop(); // Remove node from stack
2262
2263 // Now hack a few special opcodes
2264 switch( n->Opcode() ) { // Handle some opcodes special
2265 case Op_StorePConditional:
2266 case Op_StoreIConditional:
2267 case Op_StoreLConditional:
2268 case Op_CompareAndSwapI:
2269 case Op_CompareAndSwapL:
2270 case Op_CompareAndSwapP:
2271 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2272 Node *newval = n->in(MemNode::ValueIn );
2273 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2274 Node *pair = new (C) BinaryNode( oldval, newval );
2275 n->set_req(MemNode::ValueIn,pair);
2276 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2277 break;
2278 }
2279 case Op_CMoveD: // Convert trinary to binary-tree
2280 case Op_CMoveF:
2281 case Op_CMoveI:
2282 case Op_CMoveL:
2283 case Op_CMoveN:
2284 case Op_CMoveP: {
2285 // Restructure into a binary tree for Matching. It's possible that
2286 // we could move this code up next to the graph reshaping for IfNodes
2287 // or vice-versa, but I do not want to debug this for Ladybird.
2288 // 10/2/2000 CNC.
2289 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(1)->in(1));
2290 n->set_req(1,pair1);
2291 Node *pair2 = new (C) BinaryNode(n->in(2),n->in(3));
2292 n->set_req(2,pair2);
2293 n->del_req(3);
2294 break;
2295 }
2296 case Op_LoopLimit: {
2297 Node *pair1 = new (C) BinaryNode(n->in(1),n->in(2));
2298 n->set_req(1,pair1);
2299 n->set_req(2,n->in(3));
2300 n->del_req(3);
2301 break;
2302 }
2303 case Op_StrEquals: {
2304 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2305 n->set_req(2,pair1);
2306 n->set_req(3,n->in(4));
2307 n->del_req(4);
2308 break;
2309 }
2310 case Op_StrComp:
2311 case Op_StrIndexOf: {
2312 Node *pair1 = new (C) BinaryNode(n->in(2),n->in(3));
2313 n->set_req(2,pair1);
2314 Node *pair2 = new (C) BinaryNode(n->in(4),n->in(5));
2315 n->set_req(3,pair2);
2316 n->del_req(5);
2317 n->del_req(4);
2318 break;
2319 }
2320 case Op_EncodeISOArray: {
2321 // Restructure into a binary tree for Matching.
2322 Node* pair = new (C) BinaryNode(n->in(3), n->in(4));
2323 n->set_req(3, pair);
2324 n->del_req(4);
2325 break;
2326 }
2327 default:
2328 break;
2329 }
2330 }
2331 else {
2332 ShouldNotReachHere();
2333 }
2334 } // end of while (mstack.is_nonempty())
2335 }
2336
2337 #ifdef ASSERT
2338 // machine-independent root to machine-dependent root
2339 void Matcher::dump_old2new_map() {
2340 _old2new_map.dump();
2341 }
2342 #endif
2343
2344 //---------------------------collect_null_checks-------------------------------
2345 // Find null checks in the ideal graph; write a machine-specific node for
2346 // it. Used by later implicit-null-check handling. Actually collects
2347 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2348 // value being tested.
2349 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2350 Node *iff = proj->in(0);
2351 if( iff->Opcode() == Op_If ) {
2352 // During matching If's have Bool & Cmp side-by-side
2353 BoolNode *b = iff->in(1)->as_Bool();
2354 Node *cmp = iff->in(2);
2355 int opc = cmp->Opcode();
2356 if (opc != Op_CmpP && opc != Op_CmpN) return;
2357
2358 const Type* ct = cmp->in(2)->bottom_type();
2359 if (ct == TypePtr::NULL_PTR ||
2360 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2361
2362 bool push_it = false;
2363 if( proj->Opcode() == Op_IfTrue ) {
2364 extern int all_null_checks_found;
2365 all_null_checks_found++;
2366 if( b->_test._test == BoolTest::ne ) {
2367 push_it = true;
2368 }
2369 } else {
2370 assert( proj->Opcode() == Op_IfFalse, "" );
2371 if( b->_test._test == BoolTest::eq ) {
2372 push_it = true;
2373 }
2374 }
2375 if( push_it ) {
2376 _null_check_tests.push(proj);
2377 Node* val = cmp->in(1);
2378 #ifdef _LP64
2379 if (val->bottom_type()->isa_narrowoop() &&
2380 !Matcher::narrow_oop_use_complex_address()) {
2381 //
2382 // Look for DecodeN node which should be pinned to orig_proj.
2383 // On platforms (Sparc) which can not handle 2 adds
2384 // in addressing mode we have to keep a DecodeN node and
2385 // use it to do implicit NULL check in address.
2386 //
2387 // DecodeN node was pinned to non-null path (orig_proj) during
2388 // CastPP transformation in final_graph_reshaping_impl().
2389 //
2390 uint cnt = orig_proj->outcnt();
2391 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2392 Node* d = orig_proj->raw_out(i);
2393 if (d->is_DecodeN() && d->in(1) == val) {
2394 val = d;
2395 val->set_req(0, NULL); // Unpin now.
2396 // Mark this as special case to distinguish from
2397 // a regular case: CmpP(DecodeN, NULL).
2398 val = (Node*)(((intptr_t)val) | 1);
2399 break;
2400 }
2401 }
2402 }
2403 #endif
2404 _null_check_tests.push(val);
2405 }
2406 }
2407 }
2408 }
2409
2410 //---------------------------validate_null_checks------------------------------
2411 // Its possible that the value being NULL checked is not the root of a match
2412 // tree. If so, I cannot use the value in an implicit null check.
2413 void Matcher::validate_null_checks( ) {
2414 uint cnt = _null_check_tests.size();
2415 for( uint i=0; i < cnt; i+=2 ) {
2416 Node *test = _null_check_tests[i];
2417 Node *val = _null_check_tests[i+1];
2418 bool is_decoden = ((intptr_t)val) & 1;
2419 val = (Node*)(((intptr_t)val) & ~1);
2420 if (has_new_node(val)) {
2421 Node* new_val = new_node(val);
2422 if (is_decoden) {
2423 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2424 // Note: new_val may have a control edge if
2425 // the original ideal node DecodeN was matched before
2426 // it was unpinned in Matcher::collect_null_checks().
2427 // Unpin the mach node and mark it.
2428 new_val->set_req(0, NULL);
2429 new_val = (Node*)(((intptr_t)new_val) | 1);
2430 }
2431 // Is a match-tree root, so replace with the matched value
2432 _null_check_tests.map(i+1, new_val);
2433 } else {
2434 // Yank from candidate list
2435 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2436 _null_check_tests.map(i,_null_check_tests[--cnt]);
2437 _null_check_tests.pop();
2438 _null_check_tests.pop();
2439 i-=2;
2440 }
2441 }
2442 }
2443
2444 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2445 // atomic instruction acting as a store_load barrier without any
2446 // intervening volatile load, and thus we don't need a barrier here.
2447 // We retain the Node to act as a compiler ordering barrier.
2448 bool Matcher::post_store_load_barrier(const Node* vmb) {
2449 Compile* C = Compile::current();
2450 assert(vmb->is_MemBar(), "");
2451 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2452 const MemBarNode* membar = vmb->as_MemBar();
2453
2454 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2455 Node* ctrl = NULL;
2456 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2457 Node* p = membar->fast_out(i);
2458 assert(p->is_Proj(), "only projections here");
2459 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2460 !C->node_arena()->contains(p)) { // Unmatched old-space only
2461 ctrl = p;
2462 break;
2463 }
2464 }
2465 assert((ctrl != NULL), "missing control projection");
2466
2467 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2468 Node *x = ctrl->fast_out(j);
2469 int xop = x->Opcode();
2470
2471 // We don't need current barrier if we see another or a lock
2472 // before seeing volatile load.
2473 //
2474 // Op_Fastunlock previously appeared in the Op_* list below.
2475 // With the advent of 1-0 lock operations we're no longer guaranteed
2476 // that a monitor exit operation contains a serializing instruction.
2477
2478 if (xop == Op_MemBarVolatile ||
2479 xop == Op_CompareAndSwapL ||
2480 xop == Op_CompareAndSwapP ||
2481 xop == Op_CompareAndSwapN ||
2482 xop == Op_CompareAndSwapI) {
2483 return true;
2484 }
2485
2486 // Op_FastLock previously appeared in the Op_* list above.
2487 // With biased locking we're no longer guaranteed that a monitor
2488 // enter operation contains a serializing instruction.
2489 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2490 return true;
2491 }
2492
2493 if (x->is_MemBar()) {
2494 // We must retain this membar if there is an upcoming volatile
2495 // load, which will be followed by acquire membar.
2496 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2497 return false;
2498 } else {
2499 // For other kinds of barriers, check by pretending we
2500 // are them, and seeing if we can be removed.
2501 return post_store_load_barrier(x->as_MemBar());
2502 }
2503 }
2504
2505 // probably not necessary to check for these
2506 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2507 return false;
2508 }
2509 }
2510 return false;
2511 }
2512
2513 // Check whether node n is a branch to an uncommon trap that we could
2514 // optimize as test with very high branch costs in case of going to
2515 // the uncommon trap. The code must be able to be recompiled to use
2516 // a cheaper test.
2517 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2518 // Don't do it for natives, adapters, or runtime stubs
2519 Compile *C = Compile::current();
2520 if (!C->is_method_compilation()) return false;
2521
2522 assert(n->is_If(), "You should only call this on if nodes.");
2523 IfNode *ifn = n->as_If();
2524
2525 Node *ifFalse = NULL;
2526 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2527 if (ifn->fast_out(i)->is_IfFalse()) {
2528 ifFalse = ifn->fast_out(i);
2529 break;
2530 }
2531 }
2532 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2533
2534 Node *reg = ifFalse;
2535 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2536 // Alternatively use visited set? Seems too expensive.
2537 while (reg != NULL && cnt > 0) {
2538 CallNode *call = NULL;
2539 RegionNode *nxt_reg = NULL;
2540 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2541 Node *o = reg->fast_out(i);
2542 if (o->is_Call()) {
2543 call = o->as_Call();
2544 }
2545 if (o->is_Region()) {
2546 nxt_reg = o->as_Region();
2547 }
2548 }
2549
2550 if (call &&
2551 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2552 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2553 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2554 jint tr_con = trtype->is_int()->get_con();
2555 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2556 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2557 assert((int)reason < (int)BitsPerInt, "recode bit map");
2558
2559 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2560 && action != Deoptimization::Action_none) {
2561 // This uncommon trap is sure to recompile, eventually.
2562 // When that happens, C->too_many_traps will prevent
2563 // this transformation from happening again.
2564 return true;
2565 }
2566 }
2567 }
2568
2569 reg = nxt_reg;
2570 cnt--;
2571 }
2572
2573 return false;
2574 }
2575
2576 //=============================================================================
2577 //---------------------------State---------------------------------------------
2578 State::State(void) {
2579 #ifdef ASSERT
2580 _id = 0;
2581 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2582 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2583 //memset(_cost, -1, sizeof(_cost));
2584 //memset(_rule, -1, sizeof(_rule));
2585 #endif
2586 memset(_valid, 0, sizeof(_valid));
2587 }
2588
2589 #ifdef ASSERT
2590 State::~State() {
2591 _id = 99;
2592 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2593 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2594 memset(_cost, -3, sizeof(_cost));
2595 memset(_rule, -3, sizeof(_rule));
2596 }
2597 #endif
2598
2599 #ifndef PRODUCT
2600 //---------------------------dump----------------------------------------------
2601 void State::dump() {
2602 tty->print("\n");
2603 dump(0);
2604 }
2605
2606 void State::dump(int depth) {
2607 for( int j = 0; j < depth; j++ )
2608 tty->print(" ");
2609 tty->print("--N: ");
2610 _leaf->dump();
2611 uint i;
2612 for( i = 0; i < _LAST_MACH_OPER; i++ )
2613 // Check for valid entry
2614 if( valid(i) ) {
2615 for( int j = 0; j < depth; j++ )
2616 tty->print(" ");
2617 assert(_cost[i] != max_juint, "cost must be a valid value");
2618 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2619 tty->print_cr("%s %d %s",
2620 ruleName[i], _cost[i], ruleName[_rule[i]] );
2621 }
2622 tty->cr();
2623
2624 for( i=0; i<2; i++ )
2625 if( _kids[i] )
2626 _kids[i]->dump(depth+1);
2627 }
2628 #endif