3128           inst->remove_at(start_insn);
3129         }
3130         // Insert the tableswitch instruction
3131         inst->insert_before(start_insn,
3132                             new LIR_Op2(lir_cmp, lir_cond_always,
3133                                         LIR_OprFact::intConst(tableswitch_count),
3134                                         reg_opr));
3135         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3136         tableswitch_count++;
3137       }
3138       reg = noreg;
3139       last_key = -2147483648;
3140     }
3141   next_state:
3142     ;
3143   }
3144 #endif
3145 }
3146 
3147 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3148   Address addr = as_Address(src->as_address_ptr(), noreg);
3149   BasicType type = src->type();
3150   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3151 
3152   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3153   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3154 
3155   switch(type) {
3156   case T_INT:
3157     xchg = &MacroAssembler::atomic_xchgalw;
3158     add = &MacroAssembler::atomic_addalw;
3159     break;
3160   case T_LONG:
3161     xchg = &MacroAssembler::atomic_xchgal;
3162     add = &MacroAssembler::atomic_addal;
3163     break;
3164   case T_OBJECT:
3165   case T_ARRAY:
3166     if (UseCompressedOops) {
3167       xchg = &MacroAssembler::atomic_xchgalw;
3168       add = &MacroAssembler::atomic_addalw;

3128           inst->remove_at(start_insn);
3129         }
3130         // Insert the tableswitch instruction
3131         inst->insert_before(start_insn,
3132                             new LIR_Op2(lir_cmp, lir_cond_always,
3133                                         LIR_OprFact::intConst(tableswitch_count),
3134                                         reg_opr));
3135         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3136         tableswitch_count++;
3137       }
3138       reg = noreg;
3139       last_key = -2147483648;
3140     }
3141   next_state:
3142     ;
3143   }
3144 #endif
3145 }
3146 
3147 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3148   Address addr = as_Address(src->as_address_ptr());
3149   BasicType type = src->type();
3150   bool is_oop = type == T_OBJECT || type == T_ARRAY;
3151 
3152   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3153   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3154 
3155   switch(type) {
3156   case T_INT:
3157     xchg = &MacroAssembler::atomic_xchgalw;
3158     add = &MacroAssembler::atomic_addalw;
3159     break;
3160   case T_LONG:
3161     xchg = &MacroAssembler::atomic_xchgal;
3162     add = &MacroAssembler::atomic_addal;
3163     break;
3164   case T_OBJECT:
3165   case T_ARRAY:
3166     if (UseCompressedOops) {
3167       xchg = &MacroAssembler::atomic_xchgalw;
3168       add = &MacroAssembler::atomic_addalw;