1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.hpp"
30
31 // MacroAssembler extends Assembler by frequently used macros.
32 //
33 // Instructions for which a 'better' code sequence exists depending
34 // on arguments should also go in here.
35
36 class MacroAssembler: public Assembler {
37 friend class LIR_Assembler;
38
39 public:
40 using Assembler::mov;
41 using Assembler::movi;
42
43 protected:
44
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50 virtual void call_VM_leaf_base(
51 address entry_point, // the entry point
52 int number_of_arguments, // the number of arguments to pop after the call
53 Label *retaddr = NULL
54 );
55
56 virtual void call_VM_leaf_base(
57 address entry_point, // the entry point
58 int number_of_arguments, // the number of arguments to pop after the call
59 Label &retaddr) {
60 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
61 }
62
63 // This is the base routine called by the different versions of call_VM. The interpreter
64 // may customize this version by overriding it for its purposes (e.g., to save/restore
65 // additional registers when doing a VM call).
66 //
67 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
68 // returns the register which contains the thread upon return. If a thread register has been
69 // specified, the return value will correspond to that register. If no last_java_sp is specified
70 // (noreg) than rsp will be used instead.
71 virtual void call_VM_base( // returns the register containing the thread upon return
72 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
73 Register java_thread, // the thread if computed before ; use noreg otherwise
74 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
75 address entry_point, // the entry point
76 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
77 bool check_exceptions // whether to check for pending exceptions after return
78 );
79
80 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
81 // The implementation is only non-empty for the InterpreterMacroAssembler,
82 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
83 virtual void check_and_handle_popframe(Register java_thread);
84 virtual void check_and_handle_earlyret(Register java_thread);
85
86 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
87
88 // Maximum size of class area in Metaspace when compressed
89 uint64_t use_XOR_for_compressed_class_base;
90
91 public:
92 MacroAssembler(CodeBuffer* code) : Assembler(code) {
93 use_XOR_for_compressed_class_base
94 = (operand_valid_for_logical_immediate(false /*is32*/,
95 (uint64_t)Universe::narrow_klass_base())
96 && ((uint64_t)Universe::narrow_klass_base()
97 > (1u << log2_intptr(CompressedClassSpaceSize))));
98 }
99
100 // Biased locking support
101 // lock_reg and obj_reg must be loaded up with the appropriate values.
102 // swap_reg is killed.
103 // tmp_reg must be supplied and must not be rscratch1 or rscratch2
104 // Optional slow case is for implementations (interpreter and C1) which branch to
105 // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
106 // Returns offset of first potentially-faulting instruction for null
107 // check info (currently consumed only by C1). If
108 // swap_reg_contains_mark is true then returns -1 as it is assumed
109 // the calling code has already passed any potential faults.
110 int biased_locking_enter(Register lock_reg, Register obj_reg,
111 Register swap_reg, Register tmp_reg,
112 bool swap_reg_contains_mark,
113 Label& done, Label* slow_case = NULL,
114 BiasedLockingCounters* counters = NULL);
115 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
116
117
118 // Helper functions for statistics gathering.
119 // Unconditional atomic increment.
120 void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
121 void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
122 lea(tmp1, counter_addr);
123 atomic_incw(tmp1, tmp2, tmp3);
124 }
125 // Load Effective Address
126 void lea(Register r, const Address &a) {
127 InstructionMark im(this);
128 code_section()->relocate(inst_mark(), a.rspec());
129 a.lea(this, r);
130 }
131
132 void addmw(Address a, Register incr, Register scratch) {
133 ldrw(scratch, a);
134 addw(scratch, scratch, incr);
135 strw(scratch, a);
136 }
137
138 // Add constant to memory word
139 void addmw(Address a, int imm, Register scratch) {
140 ldrw(scratch, a);
141 if (imm > 0)
142 addw(scratch, scratch, (unsigned)imm);
143 else
144 subw(scratch, scratch, (unsigned)-imm);
145 strw(scratch, a);
146 }
147
148 void bind(Label& L) {
149 Assembler::bind(L);
150 code()->clear_last_membar();
151 }
152
153 void membar(Membar_mask_bits order_constraint);
154
155 // Frame creation and destruction shared between JITs.
156 void build_frame(int framesize);
157 void remove_frame(int framesize);
158
159 virtual void _call_Unimplemented(address call_site) {
160 mov(rscratch2, call_site);
161 haltsim();
162 }
163
164 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
165
166 virtual void notify(int type);
167
168 // aliases defined in AARCH64 spec
169
170 template<class T>
171 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
172 inline void cmp(Register Rd, unsigned imm) { subs(zr, Rd, imm); }
173
174 inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
175 inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
176
177 void cset(Register Rd, Assembler::Condition cond) {
178 csinc(Rd, zr, zr, ~cond);
179 }
180 void csetw(Register Rd, Assembler::Condition cond) {
181 csincw(Rd, zr, zr, ~cond);
182 }
183
184 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
185 csneg(Rd, Rn, Rn, ~cond);
186 }
187 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
188 csnegw(Rd, Rn, Rn, ~cond);
189 }
190
191 inline void movw(Register Rd, Register Rn) {
192 if (Rd == sp || Rn == sp) {
193 addw(Rd, Rn, 0U);
194 } else {
195 orrw(Rd, zr, Rn);
196 }
197 }
198 inline void mov(Register Rd, Register Rn) {
199 assert(Rd != r31_sp && Rn != r31_sp, "should be");
200 if (Rd == Rn) {
201 } else if (Rd == sp || Rn == sp) {
202 add(Rd, Rn, 0U);
203 } else {
204 orr(Rd, zr, Rn);
205 }
206 }
207
208 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
209 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
210
211 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
212 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
213
214 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
215 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
216
217 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
218 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
219 }
220 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
221 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
222 }
223
224 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
225 bfmw(Rd, Rn, lsb, (lsb + width - 1));
226 }
227 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
228 bfm(Rd, Rn, lsb , (lsb + width - 1));
229 }
230
231 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
232 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
233 }
234 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
235 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
236 }
237
238 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
239 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
240 }
241 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
242 sbfm(Rd, Rn, lsb , (lsb + width - 1));
243 }
244
245 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
246 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
247 }
248 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
249 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
250 }
251
252 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
253 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
254 }
255 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
256 ubfm(Rd, Rn, lsb , (lsb + width - 1));
257 }
258
259 inline void asrw(Register Rd, Register Rn, unsigned imm) {
260 sbfmw(Rd, Rn, imm, 31);
261 }
262
263 inline void asr(Register Rd, Register Rn, unsigned imm) {
264 sbfm(Rd, Rn, imm, 63);
265 }
266
267 inline void lslw(Register Rd, Register Rn, unsigned imm) {
268 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
269 }
270
271 inline void lsl(Register Rd, Register Rn, unsigned imm) {
272 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
273 }
274
275 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
276 ubfmw(Rd, Rn, imm, 31);
277 }
278
279 inline void lsr(Register Rd, Register Rn, unsigned imm) {
280 ubfm(Rd, Rn, imm, 63);
281 }
282
283 inline void rorw(Register Rd, Register Rn, unsigned imm) {
284 extrw(Rd, Rn, Rn, imm);
285 }
286
287 inline void ror(Register Rd, Register Rn, unsigned imm) {
288 extr(Rd, Rn, Rn, imm);
289 }
290
291 inline void sxtbw(Register Rd, Register Rn) {
292 sbfmw(Rd, Rn, 0, 7);
293 }
294 inline void sxthw(Register Rd, Register Rn) {
295 sbfmw(Rd, Rn, 0, 15);
296 }
297 inline void sxtb(Register Rd, Register Rn) {
298 sbfm(Rd, Rn, 0, 7);
299 }
300 inline void sxth(Register Rd, Register Rn) {
301 sbfm(Rd, Rn, 0, 15);
302 }
303 inline void sxtw(Register Rd, Register Rn) {
304 sbfm(Rd, Rn, 0, 31);
305 }
306
307 inline void uxtbw(Register Rd, Register Rn) {
308 ubfmw(Rd, Rn, 0, 7);
309 }
310 inline void uxthw(Register Rd, Register Rn) {
311 ubfmw(Rd, Rn, 0, 15);
312 }
313 inline void uxtb(Register Rd, Register Rn) {
314 ubfm(Rd, Rn, 0, 7);
315 }
316 inline void uxth(Register Rd, Register Rn) {
317 ubfm(Rd, Rn, 0, 15);
318 }
319 inline void uxtw(Register Rd, Register Rn) {
320 ubfm(Rd, Rn, 0, 31);
321 }
322
323 inline void cmnw(Register Rn, Register Rm) {
324 addsw(zr, Rn, Rm);
325 }
326 inline void cmn(Register Rn, Register Rm) {
327 adds(zr, Rn, Rm);
328 }
329
330 inline void cmpw(Register Rn, Register Rm) {
331 subsw(zr, Rn, Rm);
332 }
333 inline void cmp(Register Rn, Register Rm) {
334 subs(zr, Rn, Rm);
335 }
336
337 inline void negw(Register Rd, Register Rn) {
338 subw(Rd, zr, Rn);
339 }
340
341 inline void neg(Register Rd, Register Rn) {
342 sub(Rd, zr, Rn);
343 }
344
345 inline void negsw(Register Rd, Register Rn) {
346 subsw(Rd, zr, Rn);
347 }
348
349 inline void negs(Register Rd, Register Rn) {
350 subs(Rd, zr, Rn);
351 }
352
353 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
354 addsw(zr, Rn, Rm, kind, shift);
355 }
356 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
357 adds(zr, Rn, Rm, kind, shift);
358 }
359
360 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
361 subsw(zr, Rn, Rm, kind, shift);
362 }
363 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
364 subs(zr, Rn, Rm, kind, shift);
365 }
366
367 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
368 subw(Rd, zr, Rn, kind, shift);
369 }
370
371 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
372 sub(Rd, zr, Rn, kind, shift);
373 }
374
375 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
376 subsw(Rd, zr, Rn, kind, shift);
377 }
378
379 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
380 subs(Rd, zr, Rn, kind, shift);
381 }
382
383 inline void mnegw(Register Rd, Register Rn, Register Rm) {
384 msubw(Rd, Rn, Rm, zr);
385 }
386 inline void mneg(Register Rd, Register Rn, Register Rm) {
387 msub(Rd, Rn, Rm, zr);
388 }
389
390 inline void mulw(Register Rd, Register Rn, Register Rm) {
391 maddw(Rd, Rn, Rm, zr);
392 }
393 inline void mul(Register Rd, Register Rn, Register Rm) {
394 madd(Rd, Rn, Rm, zr);
395 }
396
397 inline void smnegl(Register Rd, Register Rn, Register Rm) {
398 smsubl(Rd, Rn, Rm, zr);
399 }
400 inline void smull(Register Rd, Register Rn, Register Rm) {
401 smaddl(Rd, Rn, Rm, zr);
402 }
403
404 inline void umnegl(Register Rd, Register Rn, Register Rm) {
405 umsubl(Rd, Rn, Rm, zr);
406 }
407 inline void umull(Register Rd, Register Rn, Register Rm) {
408 umaddl(Rd, Rn, Rm, zr);
409 }
410
411 #define WRAP(INSN) \
412 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
413 if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr) \
414 nop(); \
415 Assembler::INSN(Rd, Rn, Rm, Ra); \
416 }
417
418 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
419 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
420 #undef WRAP
421
422
423 // macro assembly operations needed for aarch64
424
425 // first two private routines for loading 32 bit or 64 bit constants
426 private:
427
428 void mov_immediate64(Register dst, u_int64_t imm64);
429 void mov_immediate32(Register dst, u_int32_t imm32);
430
431 int push(unsigned int bitset, Register stack);
432 int pop(unsigned int bitset, Register stack);
433
434 void mov(Register dst, Address a);
435
436 public:
437 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
438 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
439
440 // Push and pop everything that might be clobbered by a native
441 // runtime call except rscratch1 and rscratch2. (They are always
442 // scratch, so we don't have to protect them.) Only save the lower
443 // 64 bits of each vector register.
444 void push_call_clobbered_registers();
445 void pop_call_clobbered_registers();
446
447 // now mov instructions for loading absolute addresses and 32 or
448 // 64 bit integers
449
450 inline void mov(Register dst, address addr)
451 {
452 mov_immediate64(dst, (u_int64_t)addr);
453 }
454
455 inline void mov(Register dst, u_int64_t imm64)
456 {
457 mov_immediate64(dst, imm64);
458 }
459
460 inline void movw(Register dst, u_int32_t imm32)
461 {
462 mov_immediate32(dst, imm32);
463 }
464
465 inline void mov(Register dst, long l)
466 {
467 mov(dst, (u_int64_t)l);
468 }
469
470 inline void mov(Register dst, int i)
471 {
472 mov(dst, (long)i);
473 }
474
475 void mov(Register dst, RegisterOrConstant src) {
476 if (src.is_register())
477 mov(dst, src.as_register());
478 else
479 mov(dst, src.as_constant());
480 }
481
482 void movptr(Register r, uintptr_t imm64);
483
484 void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
485
486 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
487 orr(Vd, T, Vn, Vn);
488 }
489
490 public:
491
492 // Generalized Test Bit And Branch, including a "far" variety which
493 // spans more than 32KiB.
494 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
495 assert(cond == EQ || cond == NE, "must be");
496
497 if (far)
498 cond = ~cond;
499
500 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
501 if (cond == Assembler::EQ)
502 branch = &Assembler::tbz;
503 else
504 branch = &Assembler::tbnz;
505
506 if (far) {
507 Label L;
508 (this->*branch)(Rt, bitpos, L);
509 b(dest);
510 bind(L);
511 } else {
512 (this->*branch)(Rt, bitpos, dest);
513 }
514 }
515
516 // macro instructions for accessing and updating floating point
517 // status register
518 //
519 // FPSR : op1 == 011
520 // CRn == 0100
521 // CRm == 0100
522 // op2 == 001
523
524 inline void get_fpsr(Register reg)
525 {
526 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
527 }
528
529 inline void set_fpsr(Register reg)
530 {
531 msr(0b011, 0b0100, 0b0100, 0b001, reg);
532 }
533
534 inline void clear_fpsr()
535 {
536 msr(0b011, 0b0100, 0b0100, 0b001, zr);
537 }
538
539 // DCZID_EL0: op1 == 011
540 // CRn == 0000
541 // CRm == 0000
542 // op2 == 111
543 inline void get_dczid_el0(Register reg)
544 {
545 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
546 }
547
548 // CTR_EL0: op1 == 011
549 // CRn == 0000
550 // CRm == 0000
551 // op2 == 001
552 inline void get_ctr_el0(Register reg)
553 {
554 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
555 }
556
557 // idiv variant which deals with MINLONG as dividend and -1 as divisor
558 int corrected_idivl(Register result, Register ra, Register rb,
559 bool want_remainder, Register tmp = rscratch1);
560 int corrected_idivq(Register result, Register ra, Register rb,
561 bool want_remainder, Register tmp = rscratch1);
562
563 // Support for NULL-checks
564 //
565 // Generates code that causes a NULL OS exception if the content of reg is NULL.
566 // If the accessed location is M[reg + offset] and the offset is known, provide the
567 // offset. No explicit code generation is needed if the offset is within a certain
568 // range (0 <= offset <= page_size).
569
570 virtual void null_check(Register reg, int offset = -1);
571 static bool needs_explicit_null_check(intptr_t offset);
572
573 static address target_addr_for_insn(address insn_addr, unsigned insn);
574 static address target_addr_for_insn(address insn_addr) {
575 unsigned insn = *(unsigned*)insn_addr;
576 return target_addr_for_insn(insn_addr, insn);
577 }
578
579 // Required platform-specific helpers for Label::patch_instructions.
580 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
581 static int pd_patch_instruction_size(address branch, address target);
582 static void pd_patch_instruction(address branch, address target) {
583 pd_patch_instruction_size(branch, target);
584 }
585 static address pd_call_destination(address branch) {
586 return target_addr_for_insn(branch);
587 }
588 #ifndef PRODUCT
589 static void pd_print_patched_instruction(address branch);
590 #endif
591
592 static int patch_oop(address insn_addr, address o);
593
594 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
595
596 // The following 4 methods return the offset of the appropriate move instruction
597
598 // Support for fast byte/short loading with zero extension (depending on particular CPU)
599 int load_unsigned_byte(Register dst, Address src);
600 int load_unsigned_short(Register dst, Address src);
601
602 // Support for fast byte/short loading with sign extension (depending on particular CPU)
603 int load_signed_byte(Register dst, Address src);
604 int load_signed_short(Register dst, Address src);
605
606 int load_signed_byte32(Register dst, Address src);
607 int load_signed_short32(Register dst, Address src);
608
609 // Support for sign-extension (hi:lo = extend_sign(lo))
610 void extend_sign(Register hi, Register lo);
611
612 // Load and store values by size and signed-ness
613 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
614 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
615
616 // Support for inc/dec with optimal instruction selection depending on value
617
618 // x86_64 aliases an unqualified register/address increment and
619 // decrement to call incrementq and decrementq but also supports
620 // explicitly sized calls to incrementq/decrementq or
621 // incrementl/decrementl
622
623 // for aarch64 the proper convention would be to use
624 // increment/decrement for 64 bit operatons and
625 // incrementw/decrementw for 32 bit operations. so when porting
626 // x86_64 code we can leave calls to increment/decrement as is,
627 // replace incrementq/decrementq with increment/decrement and
628 // replace incrementl/decrementl with incrementw/decrementw.
629
630 // n.b. increment/decrement calls with an Address destination will
631 // need to use a scratch register to load the value to be
632 // incremented. increment/decrement calls which add or subtract a
633 // constant value greater than 2^12 will need to use a 2nd scratch
634 // register to hold the constant. so, a register increment/decrement
635 // may trash rscratch2 and an address increment/decrement trash
636 // rscratch and rscratch2
637
638 void decrementw(Address dst, int value = 1);
639 void decrementw(Register reg, int value = 1);
640
641 void decrement(Register reg, int value = 1);
642 void decrement(Address dst, int value = 1);
643
644 void incrementw(Address dst, int value = 1);
645 void incrementw(Register reg, int value = 1);
646
647 void increment(Register reg, int value = 1);
648 void increment(Address dst, int value = 1);
649
650
651 // Alignment
652 void align(int modulus);
653
654 // Stack frame creation/removal
655 void enter()
656 {
657 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
658 mov(rfp, sp);
659 }
660 void leave()
661 {
662 mov(sp, rfp);
663 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
664 }
665
666 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
667 // The pointer will be loaded into the thread register.
668 void get_thread(Register thread);
669
670
671 // Support for VM calls
672 //
673 // It is imperative that all calls into the VM are handled via the call_VM macros.
674 // They make sure that the stack linkage is setup correctly. call_VM's correspond
675 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
676
677
678 void call_VM(Register oop_result,
679 address entry_point,
680 bool check_exceptions = true);
681 void call_VM(Register oop_result,
682 address entry_point,
683 Register arg_1,
684 bool check_exceptions = true);
685 void call_VM(Register oop_result,
686 address entry_point,
687 Register arg_1, Register arg_2,
688 bool check_exceptions = true);
689 void call_VM(Register oop_result,
690 address entry_point,
691 Register arg_1, Register arg_2, Register arg_3,
692 bool check_exceptions = true);
693
694 // Overloadings with last_Java_sp
695 void call_VM(Register oop_result,
696 Register last_java_sp,
697 address entry_point,
698 int number_of_arguments = 0,
699 bool check_exceptions = true);
700 void call_VM(Register oop_result,
701 Register last_java_sp,
702 address entry_point,
703 Register arg_1, bool
704 check_exceptions = true);
705 void call_VM(Register oop_result,
706 Register last_java_sp,
707 address entry_point,
708 Register arg_1, Register arg_2,
709 bool check_exceptions = true);
710 void call_VM(Register oop_result,
711 Register last_java_sp,
712 address entry_point,
713 Register arg_1, Register arg_2, Register arg_3,
714 bool check_exceptions = true);
715
716 void get_vm_result (Register oop_result, Register thread);
717 void get_vm_result_2(Register metadata_result, Register thread);
718
719 // These always tightly bind to MacroAssembler::call_VM_base
720 // bypassing the virtual implementation
721 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
722 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
723 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
724 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
725 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
726
727 void call_VM_leaf(address entry_point,
728 int number_of_arguments = 0);
729 void call_VM_leaf(address entry_point,
730 Register arg_1);
731 void call_VM_leaf(address entry_point,
732 Register arg_1, Register arg_2);
733 void call_VM_leaf(address entry_point,
734 Register arg_1, Register arg_2, Register arg_3);
735
736 // These always tightly bind to MacroAssembler::call_VM_leaf_base
737 // bypassing the virtual implementation
738 void super_call_VM_leaf(address entry_point);
739 void super_call_VM_leaf(address entry_point, Register arg_1);
740 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
741 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
742 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
743
744 // last Java Frame (fills frame anchor)
745 void set_last_Java_frame(Register last_java_sp,
746 Register last_java_fp,
747 address last_java_pc,
748 Register scratch);
749
750 void set_last_Java_frame(Register last_java_sp,
751 Register last_java_fp,
752 Label &last_java_pc,
753 Register scratch);
754
755 void set_last_Java_frame(Register last_java_sp,
756 Register last_java_fp,
757 Register last_java_pc,
758 Register scratch);
759
760 void reset_last_Java_frame(Register thread);
761
762 // thread in the default location (rthread)
763 void reset_last_Java_frame(bool clear_fp);
764
765 // Stores
766 void store_check(Register obj); // store check for obj - register is destroyed afterwards
767 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
768
769 #if INCLUDE_ALL_GCS
770
771 void g1_write_barrier_pre(Register obj,
772 Register pre_val,
773 Register thread,
774 Register tmp,
775 bool tosca_live,
776 bool expand_call);
777
778 void g1_write_barrier_post(Register store_addr,
779 Register new_val,
780 Register thread,
781 Register tmp,
782 Register tmp2);
783
784 #endif // INCLUDE_ALL_GCS
785
786 // oop manipulations
787 void load_klass(Register dst, Register src);
788 void store_klass(Register dst, Register src);
789 void cmp_klass(Register oop, Register trial_klass, Register tmp);
790
791 void load_mirror(Register dst, Register method);
792
793 void load_heap_oop(Register dst, Address src);
794
795 void load_heap_oop_not_null(Register dst, Address src);
796 void store_heap_oop(Address dst, Register src);
797
798 // currently unimplemented
799 // Used for storing NULL. All other oop constants should be
800 // stored using routines that take a jobject.
801 void store_heap_oop_null(Address dst);
802
803 void load_prototype_header(Register dst, Register src);
804
805 void store_klass_gap(Register dst, Register src);
806
807 // This dummy is to prevent a call to store_heap_oop from
808 // converting a zero (like NULL) into a Register by giving
809 // the compiler two choices it can't resolve
810
811 void store_heap_oop(Address dst, void* dummy);
812
813 void encode_heap_oop(Register d, Register s);
814 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
815 void decode_heap_oop(Register d, Register s);
816 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
817 void encode_heap_oop_not_null(Register r);
818 void decode_heap_oop_not_null(Register r);
819 void encode_heap_oop_not_null(Register dst, Register src);
820 void decode_heap_oop_not_null(Register dst, Register src);
821
822 void set_narrow_oop(Register dst, jobject obj);
823
824 void encode_klass_not_null(Register r);
825 void decode_klass_not_null(Register r);
826 void encode_klass_not_null(Register dst, Register src);
827 void decode_klass_not_null(Register dst, Register src);
828
829 void set_narrow_klass(Register dst, Klass* k);
830
831 // if heap base register is used - reinit it with the correct value
832 void reinit_heapbase();
833
834 DEBUG_ONLY(void verify_heapbase(const char* msg);)
835
836 void push_CPU_state(bool save_vectors = false);
837 void pop_CPU_state(bool restore_vectors = false) ;
838
839 // Round up to a power of two
840 void round_to(Register reg, int modulus);
841
842 // allocation
843 void eden_allocate(
844 Register obj, // result: pointer to object after successful allocation
845 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
846 int con_size_in_bytes, // object size in bytes if known at compile time
847 Register t1, // temp register
848 Label& slow_case // continuation point if fast allocation fails
849 );
850 void tlab_allocate(
851 Register obj, // result: pointer to object after successful allocation
852 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
853 int con_size_in_bytes, // object size in bytes if known at compile time
854 Register t1, // temp register
855 Register t2, // temp register
856 Label& slow_case // continuation point if fast allocation fails
857 );
858 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
859 void verify_tlab();
860
861 void incr_allocated_bytes(Register thread,
862 Register var_size_in_bytes, int con_size_in_bytes,
863 Register t1 = noreg);
864
865 // interface method calling
866 void lookup_interface_method(Register recv_klass,
867 Register intf_klass,
868 RegisterOrConstant itable_index,
869 Register method_result,
870 Register scan_temp,
871 Label& no_such_interface);
872
873 // virtual method calling
874 // n.b. x86 allows RegisterOrConstant for vtable_index
875 void lookup_virtual_method(Register recv_klass,
876 RegisterOrConstant vtable_index,
877 Register method_result);
878
879 // Test sub_klass against super_klass, with fast and slow paths.
880
881 // The fast path produces a tri-state answer: yes / no / maybe-slow.
882 // One of the three labels can be NULL, meaning take the fall-through.
883 // If super_check_offset is -1, the value is loaded up from super_klass.
884 // No registers are killed, except temp_reg.
885 void check_klass_subtype_fast_path(Register sub_klass,
886 Register super_klass,
887 Register temp_reg,
888 Label* L_success,
889 Label* L_failure,
890 Label* L_slow_path,
891 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
892
893 // The rest of the type check; must be wired to a corresponding fast path.
894 // It does not repeat the fast path logic, so don't use it standalone.
895 // The temp_reg and temp2_reg can be noreg, if no temps are available.
896 // Updates the sub's secondary super cache as necessary.
897 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
898 void check_klass_subtype_slow_path(Register sub_klass,
899 Register super_klass,
900 Register temp_reg,
901 Register temp2_reg,
902 Label* L_success,
903 Label* L_failure,
904 bool set_cond_codes = false);
905
906 // Simplified, combined version, good for typical uses.
907 // Falls through on failure.
908 void check_klass_subtype(Register sub_klass,
909 Register super_klass,
910 Register temp_reg,
911 Label& L_success);
912
913 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
914
915
916 // Debugging
917
918 // only if +VerifyOops
919 void verify_oop(Register reg, const char* s = "broken oop");
920 void verify_oop_addr(Address addr, const char * s = "broken oop addr");
921
922 // TODO: verify method and klass metadata (compare against vptr?)
923 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
924 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
925
926 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
927 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
928
929 // only if +VerifyFPU
930 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
931
932 // prints msg, dumps registers and stops execution
933 void stop(const char* msg);
934
935 // prints msg and continues
936 void warn(const char* msg);
937
938 static void debug64(char* msg, int64_t pc, int64_t regs[]);
939
940 void untested() { stop("untested"); }
941
942 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); }
943
944 void should_not_reach_here() { stop("should not reach here"); }
945
946 // Stack overflow checking
947 void bang_stack_with_offset(int offset) {
948 // stack grows down, caller passes positive offset
949 assert(offset > 0, "must bang with negative offset");
950 mov(rscratch2, -offset);
951 str(zr, Address(sp, rscratch2));
952 }
953
954 // Writes to stack successive pages until offset reached to check for
955 // stack overflow + shadow pages. Also, clobbers tmp
956 void bang_stack_size(Register size, Register tmp);
957
958 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
959 Register tmp,
960 int offset);
961
962 // Support for serializing memory accesses between threads
963 void serialize_memory(Register thread, Register tmp);
964
965 // Arithmetics
966
967 void addptr(const Address &dst, int32_t src);
968 void cmpptr(Register src1, Address src2);
969
970 // Various forms of CAS
971
972 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
973 Label &suceed, Label *fail);
974
975 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
976 Label &suceed, Label *fail);
977
978 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
979 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
980 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
981 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
982
983 void atomic_xchg(Register prev, Register newv, Register addr);
984 void atomic_xchgw(Register prev, Register newv, Register addr);
985 void atomic_xchgal(Register prev, Register newv, Register addr);
986 void atomic_xchgalw(Register prev, Register newv, Register addr);
987
988 void orptr(Address adr, RegisterOrConstant src) {
989 ldr(rscratch2, adr);
990 if (src.is_register())
991 orr(rscratch2, rscratch2, src.as_register());
992 else
993 orr(rscratch2, rscratch2, src.as_constant());
994 str(rscratch2, adr);
995 }
996
997 // A generic CAS; success or failure is in the EQ flag.
998 // Clobbers rscratch1
999 void cmpxchg(Register addr, Register expected, Register new_val,
1000 enum operand_size size,
1001 bool acquire, bool release, bool weak,
1002 Register result);
1003
1004 // Calls
1005
1006 address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1007
1008 static bool far_branches() {
1009 return ReservedCodeCacheSize > branch_range;
1010 }
1011
1012 // Jumps that can reach anywhere in the code cache.
1013 // Trashes tmp.
1014 void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1015 void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1016
1017 static int far_branch_size() {
1018 if (far_branches()) {
1019 return 3 * 4; // adrp, add, br
1020 } else {
1021 return 4;
1022 }
1023 }
1024
1025 // Emit the CompiledIC call idiom
1026 address ic_call(address entry, jint method_index = 0);
1027
1028 public:
1029
1030 // Data
1031
1032 void mov_metadata(Register dst, Metadata* obj);
1033 Address allocate_metadata_address(Metadata* obj);
1034 Address constant_oop_address(jobject obj);
1035
1036 void movoop(Register dst, jobject obj, bool immediate = false);
1037
1038 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1039 void kernel_crc32(Register crc, Register buf, Register len,
1040 Register table0, Register table1, Register table2, Register table3,
1041 Register tmp, Register tmp2, Register tmp3);
1042 // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1043 void kernel_crc32c(Register crc, Register buf, Register len,
1044 Register table0, Register table1, Register table2, Register table3,
1045 Register tmp, Register tmp2, Register tmp3);
1046
1047 // Stack push and pop individual 64 bit registers
1048 void push(Register src);
1049 void pop(Register dst);
1050
1051 // push all registers onto the stack
1052 void pusha();
1053 void popa();
1054
1055 void repne_scan(Register addr, Register value, Register count,
1056 Register scratch);
1057 void repne_scanw(Register addr, Register value, Register count,
1058 Register scratch);
1059
1060 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1061 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1062
1063 // If a constant does not fit in an immediate field, generate some
1064 // number of MOV instructions and then perform the operation
1065 void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1066 add_sub_imm_insn insn1,
1067 add_sub_reg_insn insn2);
1068 // Seperate vsn which sets the flags
1069 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1070 add_sub_imm_insn insn1,
1071 add_sub_reg_insn insn2);
1072
1073 #define WRAP(INSN) \
1074 void INSN(Register Rd, Register Rn, unsigned imm) { \
1075 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1076 } \
1077 \
1078 void INSN(Register Rd, Register Rn, Register Rm, \
1079 enum shift_kind kind, unsigned shift = 0) { \
1080 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1081 } \
1082 \
1083 void INSN(Register Rd, Register Rn, Register Rm) { \
1084 Assembler::INSN(Rd, Rn, Rm); \
1085 } \
1086 \
1087 void INSN(Register Rd, Register Rn, Register Rm, \
1088 ext::operation option, int amount = 0) { \
1089 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1090 }
1091
1092 WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1093
1094 #undef WRAP
1095 #define WRAP(INSN) \
1096 void INSN(Register Rd, Register Rn, unsigned imm) { \
1097 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1098 } \
1099 \
1100 void INSN(Register Rd, Register Rn, Register Rm, \
1101 enum shift_kind kind, unsigned shift = 0) { \
1102 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1103 } \
1104 \
1105 void INSN(Register Rd, Register Rn, Register Rm) { \
1106 Assembler::INSN(Rd, Rn, Rm); \
1107 } \
1108 \
1109 void INSN(Register Rd, Register Rn, Register Rm, \
1110 ext::operation option, int amount = 0) { \
1111 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1112 }
1113
1114 WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1115
1116 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1117 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1118 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1119 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1120
1121 void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1122
1123 void tableswitch(Register index, jint lowbound, jint highbound,
1124 Label &jumptable, Label &jumptable_end, int stride = 1) {
1125 adr(rscratch1, jumptable);
1126 subsw(rscratch2, index, lowbound);
1127 subsw(zr, rscratch2, highbound - lowbound);
1128 br(Assembler::HS, jumptable_end);
1129 add(rscratch1, rscratch1, rscratch2,
1130 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1131 br(rscratch1);
1132 }
1133
1134 // Form an address from base + offset in Rd. Rd may or may not
1135 // actually be used: you must use the Address that is returned. It
1136 // is up to you to ensure that the shift provided matches the size
1137 // of your data.
1138 Address form_address(Register Rd, Register base, long byte_offset, int shift);
1139
1140 // Return true iff an address is within the 48-bit AArch64 address
1141 // space.
1142 bool is_valid_AArch64_address(address a) {
1143 return ((uint64_t)a >> 48) == 0;
1144 }
1145
1146 // Load the base of the cardtable byte map into reg.
1147 void load_byte_map_base(Register reg);
1148
1149 // Prolog generator routines to support switch between x86 code and
1150 // generated ARM code
1151
1152 // routine to generate an x86 prolog for a stub function which
1153 // bootstraps into the generated ARM code which directly follows the
1154 // stub
1155 //
1156
1157 public:
1158 // enum used for aarch64--x86 linkage to define return type of x86 function
1159 enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1160
1161 #ifdef BUILTIN_SIM
1162 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1163 #else
1164 void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1165 #endif
1166
1167 // special version of call_VM_leaf_base needed for aarch64 simulator
1168 // where we need to specify both the gp and fp arg counts and the
1169 // return type so that the linkage routine from aarch64 to x86 and
1170 // back knows which aarch64 registers to copy to x86 registers and
1171 // which x86 result register to copy back to an aarch64 register
1172
1173 void call_VM_leaf_base1(
1174 address entry_point, // the entry point
1175 int number_of_gp_arguments, // the number of gp reg arguments to pass
1176 int number_of_fp_arguments, // the number of fp reg arguments to pass
1177 ret_type type, // the return type for the call
1178 Label* retaddr = NULL
1179 );
1180
1181 void ldr_constant(Register dest, const Address &const_addr) {
1182 if (NearCpool) {
1183 ldr(dest, const_addr);
1184 } else {
1185 unsigned long offset;
1186 adrp(dest, InternalAddress(const_addr.target()), offset);
1187 ldr(dest, Address(dest, offset));
1188 }
1189 }
1190
1191 address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1192 address read_polling_page(Register r, relocInfo::relocType rtype);
1193
1194 // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1195 void update_byte_crc32(Register crc, Register val, Register table);
1196 void update_word_crc32(Register crc, Register v, Register tmp,
1197 Register table0, Register table1, Register table2, Register table3,
1198 bool upper = false);
1199
1200 void string_compare(Register str1, Register str2,
1201 Register cnt1, Register cnt2, Register result,
1202 Register tmp1,
1203 FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1204
1205 void arrays_equals(Register a1, Register a2,
1206 Register result, Register cnt1,
1207 int elem_size, bool is_string);
1208
1209 void fill_words(Register base, Register cnt, Register value);
1210 void zero_words(Register base, u_int64_t cnt);
1211 void zero_words(Register base, Register cnt);
1212 void block_zero(Register base, Register cnt, bool is_large = false);
1213
1214 void byte_array_inflate(Register src, Register dst, Register len,
1215 FloatRegister vtmp1, FloatRegister vtmp2,
1216 FloatRegister vtmp3, Register tmp4);
1217
1218 void char_array_compress(Register src, Register dst, Register len,
1219 FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1220 FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1221 Register result);
1222
1223 void encode_iso_array(Register src, Register dst,
1224 Register len, Register result,
1225 FloatRegister Vtmp1, FloatRegister Vtmp2,
1226 FloatRegister Vtmp3, FloatRegister Vtmp4);
1227 void string_indexof(Register str1, Register str2,
1228 Register cnt1, Register cnt2,
1229 Register tmp1, Register tmp2,
1230 Register tmp3, Register tmp4,
1231 int int_cnt1, Register result, int ae);
1232 private:
1233 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1234 Register src1, Register src2);
1235 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1236 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1237 }
1238 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1239 Register y, Register y_idx, Register z,
1240 Register carry, Register product,
1241 Register idx, Register kdx);
1242 void multiply_128_x_128_loop(Register y, Register z,
1243 Register carry, Register carry2,
1244 Register idx, Register jdx,
1245 Register yz_idx1, Register yz_idx2,
1246 Register tmp, Register tmp3, Register tmp4,
1247 Register tmp7, Register product_hi);
1248 public:
1249 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1250 Register zlen, Register tmp1, Register tmp2, Register tmp3,
1251 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1252 // ISB may be needed because of a safepoint
1253 void maybe_isb() { isb(); }
1254
1255 private:
1256 // Return the effective address r + (r1 << ext) + offset.
1257 // Uses rscratch2.
1258 Address offsetted_address(Register r, Register r1, Address::extend ext,
1259 int offset, int size);
1260
1261 private:
1262 // Returns an address on the stack which is reachable with a ldr/str of size
1263 // Uses rscratch2 if the address is not directly reachable
1264 Address spill_address(int size, int offset, Register tmp=rscratch2);
1265
1266 public:
1267 void spill(Register Rx, bool is64, int offset) {
1268 if (is64) {
1269 str(Rx, spill_address(8, offset));
1270 } else {
1271 strw(Rx, spill_address(4, offset));
1272 }
1273 }
1274 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1275 str(Vx, T, spill_address(1 << (int)T, offset));
1276 }
1277 void unspill(Register Rx, bool is64, int offset) {
1278 if (is64) {
1279 ldr(Rx, spill_address(8, offset));
1280 } else {
1281 ldrw(Rx, spill_address(4, offset));
1282 }
1283 }
1284 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1285 ldr(Vx, T, spill_address(1 << (int)T, offset));
1286 }
1287 void spill_copy128(int src_offset, int dst_offset,
1288 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1289 if (src_offset < 512 && (src_offset & 7) == 0 &&
1290 dst_offset < 512 && (dst_offset & 7) == 0) {
1291 ldp(tmp1, tmp2, Address(sp, src_offset));
1292 stp(tmp1, tmp2, Address(sp, dst_offset));
1293 } else {
1294 unspill(tmp1, true, src_offset);
1295 spill(tmp1, true, dst_offset);
1296 unspill(tmp1, true, src_offset+8);
1297 spill(tmp1, true, dst_offset+8);
1298 }
1299 }
1300 };
1301
1302 #ifdef ASSERT
1303 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1304 #endif
1305
1306 /**
1307 * class SkipIfEqual:
1308 *
1309 * Instantiating this class will result in assembly code being output that will
1310 * jump around any code emitted between the creation of the instance and it's
1311 * automatic destruction at the end of a scope block, depending on the value of
1312 * the flag passed to the constructor, which will be checked at run-time.
1313 */
1314 class SkipIfEqual {
1315 private:
1316 MacroAssembler* _masm;
1317 Label _label;
1318
1319 public:
1320 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1321 ~SkipIfEqual();
1322 };
1323
1324 struct tableswitch {
1325 Register _reg;
1326 int _insn_index; jint _first_key; jint _last_key;
1327 Label _after;
1328 Label _branches;
1329 };
1330
1331 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP