1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39
40 #ifdef PRODUCT
41 #define BLOCK_COMMENT(str) /* nothing */
42 #define STOP(error) stop(error)
43 #else
44 #define BLOCK_COMMENT(str) block_comment(str)
45 #define STOP(error) block_comment(error); stop(error)
46 #endif
47
48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
49 // Implementation of AddressLiteral
50
51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
53 // -----------------Table 4.5 -------------------- //
54 16, 32, 64, // EVEX_FV(0)
55 4, 4, 4, // EVEX_FV(1) - with Evex.b
56 16, 32, 64, // EVEX_FV(2) - with Evex.w
57 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
58 8, 16, 32, // EVEX_HV(0)
59 4, 4, 4, // EVEX_HV(1) - with Evex.b
60 // -----------------Table 4.6 -------------------- //
61 16, 32, 64, // EVEX_FVM(0)
62 1, 1, 1, // EVEX_T1S(0)
63 2, 2, 2, // EVEX_T1S(1)
64 4, 4, 4, // EVEX_T1S(2)
65 8, 8, 8, // EVEX_T1S(3)
66 4, 4, 4, // EVEX_T1F(0)
67 8, 8, 8, // EVEX_T1F(1)
68 8, 8, 8, // EVEX_T2(0)
69 0, 16, 16, // EVEX_T2(1)
70 0, 16, 16, // EVEX_T4(0)
71 0, 0, 32, // EVEX_T4(1)
72 0, 0, 32, // EVEX_T8(0)
73 8, 16, 32, // EVEX_HVM(0)
74 4, 8, 16, // EVEX_QVM(0)
75 2, 4, 8, // EVEX_OVM(0)
76 16, 16, 16, // EVEX_M128(0)
77 8, 32, 64, // EVEX_DUP(0)
78 0, 0, 0 // EVEX_NTUP
79 };
80
81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
82 _is_lval = false;
83 _target = target;
84 switch (rtype) {
85 case relocInfo::oop_type:
86 case relocInfo::metadata_type:
87 // Oops are a special case. Normally they would be their own section
88 // but in cases like icBuffer they are literals in the code stream that
89 // we don't have a section for. We use none so that we get a literal address
90 // which is always patchable.
91 break;
92 case relocInfo::external_word_type:
93 _rspec = external_word_Relocation::spec(target);
94 break;
95 case relocInfo::internal_word_type:
96 _rspec = internal_word_Relocation::spec(target);
97 break;
98 case relocInfo::opt_virtual_call_type:
99 _rspec = opt_virtual_call_Relocation::spec();
100 break;
101 case relocInfo::static_call_type:
102 _rspec = static_call_Relocation::spec();
103 break;
104 case relocInfo::runtime_call_type:
105 _rspec = runtime_call_Relocation::spec();
106 break;
107 case relocInfo::poll_type:
108 case relocInfo::poll_return_type:
109 _rspec = Relocation::spec_simple(rtype);
110 break;
111 case relocInfo::none:
112 break;
113 default:
114 ShouldNotReachHere();
115 break;
116 }
117 }
118
119 // Implementation of Address
120
121 #ifdef _LP64
122
123 Address Address::make_array(ArrayAddress adr) {
124 // Not implementable on 64bit machines
125 // Should have been handled higher up the call chain.
126 ShouldNotReachHere();
127 return Address();
128 }
129
130 // exceedingly dangerous constructor
131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
132 _base = noreg;
133 _index = noreg;
134 _scale = no_scale;
135 _disp = disp;
136 _xmmindex = xnoreg;
137 _isxmmindex = false;
138 switch (rtype) {
139 case relocInfo::external_word_type:
140 _rspec = external_word_Relocation::spec(loc);
141 break;
142 case relocInfo::internal_word_type:
143 _rspec = internal_word_Relocation::spec(loc);
144 break;
145 case relocInfo::runtime_call_type:
146 // HMM
147 _rspec = runtime_call_Relocation::spec();
148 break;
149 case relocInfo::poll_type:
150 case relocInfo::poll_return_type:
151 _rspec = Relocation::spec_simple(rtype);
152 break;
153 case relocInfo::none:
154 break;
155 default:
156 ShouldNotReachHere();
157 }
158 }
159 #else // LP64
160
161 Address Address::make_array(ArrayAddress adr) {
162 AddressLiteral base = adr.base();
163 Address index = adr.index();
164 assert(index._disp == 0, "must not have disp"); // maybe it can?
165 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
166 array._rspec = base._rspec;
167 return array;
168 }
169
170 // exceedingly dangerous constructor
171 Address::Address(address loc, RelocationHolder spec) {
172 _base = noreg;
173 _index = noreg;
174 _scale = no_scale;
175 _disp = (intptr_t) loc;
176 _rspec = spec;
177 _xmmindex = xnoreg;
178 _isxmmindex = false;
179 }
180
181 #endif // _LP64
182
183
184
185 // Convert the raw encoding form into the form expected by the constructor for
186 // Address. An index of 4 (rsp) corresponds to having no index, so convert
187 // that to noreg for the Address constructor.
188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
189 RelocationHolder rspec;
190 if (disp_reloc != relocInfo::none) {
191 rspec = Relocation::spec_simple(disp_reloc);
192 }
193 bool valid_index = index != rsp->encoding();
194 if (valid_index) {
195 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
196 madr._rspec = rspec;
197 return madr;
198 } else {
199 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
200 madr._rspec = rspec;
201 return madr;
202 }
203 }
204
205 // Implementation of Assembler
206
207 int AbstractAssembler::code_fill_byte() {
208 return (u_char)'\xF4'; // hlt
209 }
210
211 // make this go away someday
212 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
213 if (rtype == relocInfo::none)
214 emit_int32(data);
215 else
216 emit_data(data, Relocation::spec_simple(rtype), format);
217 }
218
219 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
220 assert(imm_operand == 0, "default format must be immediate in this file");
221 assert(inst_mark() != NULL, "must be inside InstructionMark");
222 if (rspec.type() != relocInfo::none) {
223 #ifdef ASSERT
224 check_relocation(rspec, format);
225 #endif
226 // Do not use AbstractAssembler::relocate, which is not intended for
227 // embedded words. Instead, relocate to the enclosing instruction.
228
229 // hack. call32 is too wide for mask so use disp32
230 if (format == call32_operand)
231 code_section()->relocate(inst_mark(), rspec, disp32_operand);
232 else
233 code_section()->relocate(inst_mark(), rspec, format);
234 }
235 emit_int32(data);
236 }
237
238 static int encode(Register r) {
239 int enc = r->encoding();
240 if (enc >= 8) {
241 enc -= 8;
242 }
243 return enc;
244 }
245
246 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
247 assert(dst->has_byte_register(), "must have byte register");
248 assert(isByte(op1) && isByte(op2), "wrong opcode");
249 assert(isByte(imm8), "not a byte");
250 assert((op1 & 0x01) == 0, "should be 8bit operation");
251 emit_int8(op1);
252 emit_int8(op2 | encode(dst));
253 emit_int8(imm8);
254 }
255
256
257 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
258 assert(isByte(op1) && isByte(op2), "wrong opcode");
259 assert((op1 & 0x01) == 1, "should be 32bit operation");
260 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
261 if (is8bit(imm32)) {
262 emit_int8(op1 | 0x02); // set sign bit
263 emit_int8(op2 | encode(dst));
264 emit_int8(imm32 & 0xFF);
265 } else {
266 emit_int8(op1);
267 emit_int8(op2 | encode(dst));
268 emit_int32(imm32);
269 }
270 }
271
272 // Force generation of a 4 byte immediate value even if it fits into 8bit
273 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
274 assert(isByte(op1) && isByte(op2), "wrong opcode");
275 assert((op1 & 0x01) == 1, "should be 32bit operation");
276 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
277 emit_int8(op1);
278 emit_int8(op2 | encode(dst));
279 emit_int32(imm32);
280 }
281
282 // immediate-to-memory forms
283 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
284 assert((op1 & 0x01) == 1, "should be 32bit operation");
285 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
286 if (is8bit(imm32)) {
287 emit_int8(op1 | 0x02); // set sign bit
288 emit_operand(rm, adr, 1);
289 emit_int8(imm32 & 0xFF);
290 } else {
291 emit_int8(op1);
292 emit_operand(rm, adr, 4);
293 emit_int32(imm32);
294 }
295 }
296
297
298 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
299 assert(isByte(op1) && isByte(op2), "wrong opcode");
300 emit_int8(op1);
301 emit_int8(op2 | encode(dst) << 3 | encode(src));
302 }
303
304
305 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
306 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
307 int mod_idx = 0;
308 // We will test if the displacement fits the compressed format and if so
309 // apply the compression to the displacment iff the result is8bit.
310 if (VM_Version::supports_evex() && is_evex_inst) {
311 switch (cur_tuple_type) {
312 case EVEX_FV:
313 if ((cur_encoding & VEX_W) == VEX_W) {
314 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
315 } else {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
317 }
318 break;
319
320 case EVEX_HV:
321 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
322 break;
323
324 case EVEX_FVM:
325 break;
326
327 case EVEX_T1S:
328 switch (in_size_in_bits) {
329 case EVEX_8bit:
330 break;
331
332 case EVEX_16bit:
333 mod_idx = 1;
334 break;
335
336 case EVEX_32bit:
337 mod_idx = 2;
338 break;
339
340 case EVEX_64bit:
341 mod_idx = 3;
342 break;
343 }
344 break;
345
346 case EVEX_T1F:
347 case EVEX_T2:
348 case EVEX_T4:
349 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
350 break;
351
352 case EVEX_T8:
353 break;
354
355 case EVEX_HVM:
356 break;
357
358 case EVEX_QVM:
359 break;
360
361 case EVEX_OVM:
362 break;
363
364 case EVEX_M128:
365 break;
366
367 case EVEX_DUP:
368 break;
369
370 default:
371 assert(0, "no valid evex tuple_table entry");
372 break;
373 }
374
375 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
376 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
377 if ((disp % disp_factor) == 0) {
378 int new_disp = disp / disp_factor;
379 if ((-0x80 <= new_disp && new_disp < 0x80)) {
380 disp = new_disp;
381 }
382 } else {
383 return false;
384 }
385 }
386 }
387 return (-0x80 <= disp && disp < 0x80);
388 }
389
390
391 bool Assembler::emit_compressed_disp_byte(int &disp) {
392 int mod_idx = 0;
393 // We will test if the displacement fits the compressed format and if so
394 // apply the compression to the displacment iff the result is8bit.
395 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
396 int evex_encoding = _attributes->get_evex_encoding();
397 int tuple_type = _attributes->get_tuple_type();
398 switch (tuple_type) {
399 case EVEX_FV:
400 if ((evex_encoding & VEX_W) == VEX_W) {
401 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
402 } else {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
404 }
405 break;
406
407 case EVEX_HV:
408 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
409 break;
410
411 case EVEX_FVM:
412 break;
413
414 case EVEX_T1S:
415 switch (_attributes->get_input_size()) {
416 case EVEX_8bit:
417 break;
418
419 case EVEX_16bit:
420 mod_idx = 1;
421 break;
422
423 case EVEX_32bit:
424 mod_idx = 2;
425 break;
426
427 case EVEX_64bit:
428 mod_idx = 3;
429 break;
430 }
431 break;
432
433 case EVEX_T1F:
434 case EVEX_T2:
435 case EVEX_T4:
436 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
437 break;
438
439 case EVEX_T8:
440 break;
441
442 case EVEX_HVM:
443 break;
444
445 case EVEX_QVM:
446 break;
447
448 case EVEX_OVM:
449 break;
450
451 case EVEX_M128:
452 break;
453
454 case EVEX_DUP:
455 break;
456
457 default:
458 assert(0, "no valid evex tuple_table entry");
459 break;
460 }
461
462 int vector_len = _attributes->get_vector_len();
463 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
464 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
465 if ((disp % disp_factor) == 0) {
466 int new_disp = disp / disp_factor;
467 if (is8bit(new_disp)) {
468 disp = new_disp;
469 }
470 } else {
471 return false;
472 }
473 }
474 }
475 return is8bit(disp);
476 }
477
478
479 void Assembler::emit_operand(Register reg, Register base, Register index,
480 Address::ScaleFactor scale, int disp,
481 RelocationHolder const& rspec,
482 int rip_relative_correction) {
483 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
484
485 // Encode the registers as needed in the fields they are used in
486
487 int regenc = encode(reg) << 3;
488 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
489 int baseenc = base->is_valid() ? encode(base) : 0;
490
491 if (base->is_valid()) {
492 if (index->is_valid()) {
493 assert(scale != Address::no_scale, "inconsistent address");
494 // [base + index*scale + disp]
495 if (disp == 0 && rtype == relocInfo::none &&
496 base != rbp LP64_ONLY(&& base != r13)) {
497 // [base + index*scale]
498 // [00 reg 100][ss index base]
499 assert(index != rsp, "illegal addressing mode");
500 emit_int8(0x04 | regenc);
501 emit_int8(scale << 6 | indexenc | baseenc);
502 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
503 // [base + index*scale + imm8]
504 // [01 reg 100][ss index base] imm8
505 assert(index != rsp, "illegal addressing mode");
506 emit_int8(0x44 | regenc);
507 emit_int8(scale << 6 | indexenc | baseenc);
508 emit_int8(disp & 0xFF);
509 } else {
510 // [base + index*scale + disp32]
511 // [10 reg 100][ss index base] disp32
512 assert(index != rsp, "illegal addressing mode");
513 emit_int8(0x84 | regenc);
514 emit_int8(scale << 6 | indexenc | baseenc);
515 emit_data(disp, rspec, disp32_operand);
516 }
517 } else if (base == rsp LP64_ONLY(|| base == r12)) {
518 // [rsp + disp]
519 if (disp == 0 && rtype == relocInfo::none) {
520 // [rsp]
521 // [00 reg 100][00 100 100]
522 emit_int8(0x04 | regenc);
523 emit_int8(0x24);
524 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
525 // [rsp + imm8]
526 // [01 reg 100][00 100 100] disp8
527 emit_int8(0x44 | regenc);
528 emit_int8(0x24);
529 emit_int8(disp & 0xFF);
530 } else {
531 // [rsp + imm32]
532 // [10 reg 100][00 100 100] disp32
533 emit_int8(0x84 | regenc);
534 emit_int8(0x24);
535 emit_data(disp, rspec, disp32_operand);
536 }
537 } else {
538 // [base + disp]
539 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
540 if (disp == 0 && rtype == relocInfo::none &&
541 base != rbp LP64_ONLY(&& base != r13)) {
542 // [base]
543 // [00 reg base]
544 emit_int8(0x00 | regenc | baseenc);
545 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
546 // [base + disp8]
547 // [01 reg base] disp8
548 emit_int8(0x40 | regenc | baseenc);
549 emit_int8(disp & 0xFF);
550 } else {
551 // [base + disp32]
552 // [10 reg base] disp32
553 emit_int8(0x80 | regenc | baseenc);
554 emit_data(disp, rspec, disp32_operand);
555 }
556 }
557 } else {
558 if (index->is_valid()) {
559 assert(scale != Address::no_scale, "inconsistent address");
560 // [index*scale + disp]
561 // [00 reg 100][ss index 101] disp32
562 assert(index != rsp, "illegal addressing mode");
563 emit_int8(0x04 | regenc);
564 emit_int8(scale << 6 | indexenc | 0x05);
565 emit_data(disp, rspec, disp32_operand);
566 } else if (rtype != relocInfo::none ) {
567 // [disp] (64bit) RIP-RELATIVE (32bit) abs
568 // [00 000 101] disp32
569
570 emit_int8(0x05 | regenc);
571 // Note that the RIP-rel. correction applies to the generated
572 // disp field, but _not_ to the target address in the rspec.
573
574 // disp was created by converting the target address minus the pc
575 // at the start of the instruction. That needs more correction here.
576 // intptr_t disp = target - next_ip;
577 assert(inst_mark() != NULL, "must be inside InstructionMark");
578 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
579 int64_t adjusted = disp;
580 // Do rip-rel adjustment for 64bit
581 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
582 assert(is_simm32(adjusted),
583 "must be 32bit offset (RIP relative address)");
584 emit_data((int32_t) adjusted, rspec, disp32_operand);
585
586 } else {
587 // 32bit never did this, did everything as the rip-rel/disp code above
588 // [disp] ABSOLUTE
589 // [00 reg 100][00 100 101] disp32
590 emit_int8(0x04 | regenc);
591 emit_int8(0x25);
592 emit_data(disp, rspec, disp32_operand);
593 }
594 }
595 }
596
597 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
598 Address::ScaleFactor scale, int disp,
599 RelocationHolder const& rspec) {
600 if (UseAVX > 2) {
601 int xreg_enc = reg->encoding();
602 if (xreg_enc > 15) {
603 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
604 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
605 return;
606 }
607 }
608 emit_operand((Register)reg, base, index, scale, disp, rspec);
609 }
610
611 void Assembler::emit_operand(XMMRegister reg, Register base, XMMRegister index,
612 Address::ScaleFactor scale, int disp,
613 RelocationHolder const& rspec) {
614 if (UseAVX > 2) {
615 int xreg_enc = reg->encoding();
616 int xmmindex_enc = index->encoding();
617 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
618 XMMRegister new_index = as_XMMRegister(xmmindex_enc & 0xf);
619 emit_operand((Register)new_reg, base, (Register)new_index, scale, disp, rspec);
620 } else {
621 emit_operand((Register)reg, base, (Register)index, scale, disp, rspec);
622 }
623 }
624
625
626 // Secret local extension to Assembler::WhichOperand:
627 #define end_pc_operand (_WhichOperand_limit)
628
629 address Assembler::locate_operand(address inst, WhichOperand which) {
630 // Decode the given instruction, and return the address of
631 // an embedded 32-bit operand word.
632
633 // If "which" is disp32_operand, selects the displacement portion
634 // of an effective address specifier.
635 // If "which" is imm64_operand, selects the trailing immediate constant.
636 // If "which" is call32_operand, selects the displacement of a call or jump.
637 // Caller is responsible for ensuring that there is such an operand,
638 // and that it is 32/64 bits wide.
639
640 // If "which" is end_pc_operand, find the end of the instruction.
641
642 address ip = inst;
643 bool is_64bit = false;
644
645 debug_only(bool has_disp32 = false);
646 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
647
648 again_after_prefix:
649 switch (0xFF & *ip++) {
650
651 // These convenience macros generate groups of "case" labels for the switch.
652 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
653 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
654 case (x)+4: case (x)+5: case (x)+6: case (x)+7
655 #define REP16(x) REP8((x)+0): \
656 case REP8((x)+8)
657
658 case CS_segment:
659 case SS_segment:
660 case DS_segment:
661 case ES_segment:
662 case FS_segment:
663 case GS_segment:
664 // Seems dubious
665 LP64_ONLY(assert(false, "shouldn't have that prefix"));
666 assert(ip == inst+1, "only one prefix allowed");
667 goto again_after_prefix;
668
669 case 0x67:
670 case REX:
671 case REX_B:
672 case REX_X:
673 case REX_XB:
674 case REX_R:
675 case REX_RB:
676 case REX_RX:
677 case REX_RXB:
678 NOT_LP64(assert(false, "64bit prefixes"));
679 goto again_after_prefix;
680
681 case REX_W:
682 case REX_WB:
683 case REX_WX:
684 case REX_WXB:
685 case REX_WR:
686 case REX_WRB:
687 case REX_WRX:
688 case REX_WRXB:
689 NOT_LP64(assert(false, "64bit prefixes"));
690 is_64bit = true;
691 goto again_after_prefix;
692
693 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
694 case 0x88: // movb a, r
695 case 0x89: // movl a, r
696 case 0x8A: // movb r, a
697 case 0x8B: // movl r, a
698 case 0x8F: // popl a
699 debug_only(has_disp32 = true);
700 break;
701
702 case 0x68: // pushq #32
703 if (which == end_pc_operand) {
704 return ip + 4;
705 }
706 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
707 return ip; // not produced by emit_operand
708
709 case 0x66: // movw ... (size prefix)
710 again_after_size_prefix2:
711 switch (0xFF & *ip++) {
712 case REX:
713 case REX_B:
714 case REX_X:
715 case REX_XB:
716 case REX_R:
717 case REX_RB:
718 case REX_RX:
719 case REX_RXB:
720 case REX_W:
721 case REX_WB:
722 case REX_WX:
723 case REX_WXB:
724 case REX_WR:
725 case REX_WRB:
726 case REX_WRX:
727 case REX_WRXB:
728 NOT_LP64(assert(false, "64bit prefix found"));
729 goto again_after_size_prefix2;
730 case 0x8B: // movw r, a
731 case 0x89: // movw a, r
732 debug_only(has_disp32 = true);
733 break;
734 case 0xC7: // movw a, #16
735 debug_only(has_disp32 = true);
736 tail_size = 2; // the imm16
737 break;
738 case 0x0F: // several SSE/SSE2 variants
739 ip--; // reparse the 0x0F
740 goto again_after_prefix;
741 default:
742 ShouldNotReachHere();
743 }
744 break;
745
746 case REP8(0xB8): // movl/q r, #32/#64(oop?)
747 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
748 // these asserts are somewhat nonsensical
749 #ifndef _LP64
750 assert(which == imm_operand || which == disp32_operand,
751 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
752 #else
753 assert((which == call32_operand || which == imm_operand) && is_64bit ||
754 which == narrow_oop_operand && !is_64bit,
755 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
756 #endif // _LP64
757 return ip;
758
759 case 0x69: // imul r, a, #32
760 case 0xC7: // movl a, #32(oop?)
761 tail_size = 4;
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 break;
764
765 case 0x0F: // movx..., etc.
766 switch (0xFF & *ip++) {
767 case 0x3A: // pcmpestri
768 tail_size = 1;
769 case 0x38: // ptest, pmovzxbw
770 ip++; // skip opcode
771 debug_only(has_disp32 = true); // has both kinds of operands!
772 break;
773
774 case 0x70: // pshufd r, r/a, #8
775 debug_only(has_disp32 = true); // has both kinds of operands!
776 case 0x73: // psrldq r, #8
777 tail_size = 1;
778 break;
779
780 case 0x12: // movlps
781 case 0x28: // movaps
782 case 0x2E: // ucomiss
783 case 0x2F: // comiss
784 case 0x54: // andps
785 case 0x55: // andnps
786 case 0x56: // orps
787 case 0x57: // xorps
788 case 0x58: // addpd
789 case 0x59: // mulpd
790 case 0x6E: // movd
791 case 0x7E: // movd
792 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
793 case 0xFE: // paddd
794 debug_only(has_disp32 = true);
795 break;
796
797 case 0xAD: // shrd r, a, %cl
798 case 0xAF: // imul r, a
799 case 0xBE: // movsbl r, a (movsxb)
800 case 0xBF: // movswl r, a (movsxw)
801 case 0xB6: // movzbl r, a (movzxb)
802 case 0xB7: // movzwl r, a (movzxw)
803 case REP16(0x40): // cmovl cc, r, a
804 case 0xB0: // cmpxchgb
805 case 0xB1: // cmpxchg
806 case 0xC1: // xaddl
807 case 0xC7: // cmpxchg8
808 case REP16(0x90): // setcc a
809 debug_only(has_disp32 = true);
810 // fall out of the switch to decode the address
811 break;
812
813 case 0xC4: // pinsrw r, a, #8
814 debug_only(has_disp32 = true);
815 case 0xC5: // pextrw r, r, #8
816 tail_size = 1; // the imm8
817 break;
818
819 case 0xAC: // shrd r, a, #8
820 debug_only(has_disp32 = true);
821 tail_size = 1; // the imm8
822 break;
823
824 case REP16(0x80): // jcc rdisp32
825 if (which == end_pc_operand) return ip + 4;
826 assert(which == call32_operand, "jcc has no disp32 or imm");
827 return ip;
828 default:
829 ShouldNotReachHere();
830 }
831 break;
832
833 case 0x81: // addl a, #32; addl r, #32
834 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
835 // on 32bit in the case of cmpl, the imm might be an oop
836 tail_size = 4;
837 debug_only(has_disp32 = true); // has both kinds of operands!
838 break;
839
840 case 0x83: // addl a, #8; addl r, #8
841 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
842 debug_only(has_disp32 = true); // has both kinds of operands!
843 tail_size = 1;
844 break;
845
846 case 0x9B:
847 switch (0xFF & *ip++) {
848 case 0xD9: // fnstcw a
849 debug_only(has_disp32 = true);
850 break;
851 default:
852 ShouldNotReachHere();
853 }
854 break;
855
856 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
857 case REP4(0x10): // adc...
858 case REP4(0x20): // and...
859 case REP4(0x30): // xor...
860 case REP4(0x08): // or...
861 case REP4(0x18): // sbb...
862 case REP4(0x28): // sub...
863 case 0xF7: // mull a
864 case 0x8D: // lea r, a
865 case 0x87: // xchg r, a
866 case REP4(0x38): // cmp...
867 case 0x85: // test r, a
868 debug_only(has_disp32 = true); // has both kinds of operands!
869 break;
870
871 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
872 case 0xC6: // movb a, #8
873 case 0x80: // cmpb a, #8
874 case 0x6B: // imul r, a, #8
875 debug_only(has_disp32 = true); // has both kinds of operands!
876 tail_size = 1; // the imm8
877 break;
878
879 case 0xC4: // VEX_3bytes
880 case 0xC5: // VEX_2bytes
881 assert((UseAVX > 0), "shouldn't have VEX prefix");
882 assert(ip == inst+1, "no prefixes allowed");
883 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
884 // but they have prefix 0x0F and processed when 0x0F processed above.
885 //
886 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
887 // instructions (these instructions are not supported in 64-bit mode).
888 // To distinguish them bits [7:6] are set in the VEX second byte since
889 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
890 // those VEX bits REX and vvvv bits are inverted.
891 //
892 // Fortunately C2 doesn't generate these instructions so we don't need
893 // to check for them in product version.
894
895 // Check second byte
896 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
897
898 int vex_opcode;
899 // First byte
900 if ((0xFF & *inst) == VEX_3bytes) {
901 vex_opcode = VEX_OPCODE_MASK & *ip;
902 ip++; // third byte
903 is_64bit = ((VEX_W & *ip) == VEX_W);
904 } else {
905 vex_opcode = VEX_OPCODE_0F;
906 }
907 ip++; // opcode
908 // To find the end of instruction (which == end_pc_operand).
909 switch (vex_opcode) {
910 case VEX_OPCODE_0F:
911 switch (0xFF & *ip) {
912 case 0x70: // pshufd r, r/a, #8
913 case 0x71: // ps[rl|ra|ll]w r, #8
914 case 0x72: // ps[rl|ra|ll]d r, #8
915 case 0x73: // ps[rl|ra|ll]q r, #8
916 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
917 case 0xC4: // pinsrw r, r, r/a, #8
918 case 0xC5: // pextrw r/a, r, #8
919 case 0xC6: // shufp[s|d] r, r, r/a, #8
920 tail_size = 1; // the imm8
921 break;
922 }
923 break;
924 case VEX_OPCODE_0F_3A:
925 tail_size = 1;
926 break;
927 }
928 ip++; // skip opcode
929 debug_only(has_disp32 = true); // has both kinds of operands!
930 break;
931
932 case 0x62: // EVEX_4bytes
933 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
934 assert(ip == inst+1, "no prefixes allowed");
935 // no EVEX collisions, all instructions that have 0x62 opcodes
936 // have EVEX versions and are subopcodes of 0x66
937 ip++; // skip P0 and exmaine W in P1
938 is_64bit = ((VEX_W & *ip) == VEX_W);
939 ip++; // move to P2
940 ip++; // skip P2, move to opcode
941 // To find the end of instruction (which == end_pc_operand).
942 switch (0xFF & *ip) {
943 case 0x22: // pinsrd r, r/a, #8
944 case 0x61: // pcmpestri r, r/a, #8
945 case 0x70: // pshufd r, r/a, #8
946 case 0x73: // psrldq r, #8
947 tail_size = 1; // the imm8
948 break;
949 default:
950 break;
951 }
952 ip++; // skip opcode
953 debug_only(has_disp32 = true); // has both kinds of operands!
954 break;
955
956 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
957 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
958 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
959 case 0xDD: // fld_d a; fst_d a; fstp_d a
960 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
961 case 0xDF: // fild_d a; fistp_d a
962 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
963 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
964 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
965 debug_only(has_disp32 = true);
966 break;
967
968 case 0xE8: // call rdisp32
969 case 0xE9: // jmp rdisp32
970 if (which == end_pc_operand) return ip + 4;
971 assert(which == call32_operand, "call has no disp32 or imm");
972 return ip;
973
974 case 0xF0: // Lock
975 assert(os::is_MP(), "only on MP");
976 goto again_after_prefix;
977
978 case 0xF3: // For SSE
979 case 0xF2: // For SSE2
980 switch (0xFF & *ip++) {
981 case REX:
982 case REX_B:
983 case REX_X:
984 case REX_XB:
985 case REX_R:
986 case REX_RB:
987 case REX_RX:
988 case REX_RXB:
989 case REX_W:
990 case REX_WB:
991 case REX_WX:
992 case REX_WXB:
993 case REX_WR:
994 case REX_WRB:
995 case REX_WRX:
996 case REX_WRXB:
997 NOT_LP64(assert(false, "found 64bit prefix"));
998 ip++;
999 default:
1000 ip++;
1001 }
1002 debug_only(has_disp32 = true); // has both kinds of operands!
1003 break;
1004
1005 default:
1006 ShouldNotReachHere();
1007
1008 #undef REP8
1009 #undef REP16
1010 }
1011
1012 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1013 #ifdef _LP64
1014 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1015 #else
1016 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1017 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1018 #endif // LP64
1019 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1020
1021 // parse the output of emit_operand
1022 int op2 = 0xFF & *ip++;
1023 int base = op2 & 0x07;
1024 int op3 = -1;
1025 const int b100 = 4;
1026 const int b101 = 5;
1027 if (base == b100 && (op2 >> 6) != 3) {
1028 op3 = 0xFF & *ip++;
1029 base = op3 & 0x07; // refetch the base
1030 }
1031 // now ip points at the disp (if any)
1032
1033 switch (op2 >> 6) {
1034 case 0:
1035 // [00 reg 100][ss index base]
1036 // [00 reg 100][00 100 esp]
1037 // [00 reg base]
1038 // [00 reg 100][ss index 101][disp32]
1039 // [00 reg 101] [disp32]
1040
1041 if (base == b101) {
1042 if (which == disp32_operand)
1043 return ip; // caller wants the disp32
1044 ip += 4; // skip the disp32
1045 }
1046 break;
1047
1048 case 1:
1049 // [01 reg 100][ss index base][disp8]
1050 // [01 reg 100][00 100 esp][disp8]
1051 // [01 reg base] [disp8]
1052 ip += 1; // skip the disp8
1053 break;
1054
1055 case 2:
1056 // [10 reg 100][ss index base][disp32]
1057 // [10 reg 100][00 100 esp][disp32]
1058 // [10 reg base] [disp32]
1059 if (which == disp32_operand)
1060 return ip; // caller wants the disp32
1061 ip += 4; // skip the disp32
1062 break;
1063
1064 case 3:
1065 // [11 reg base] (not a memory addressing mode)
1066 break;
1067 }
1068
1069 if (which == end_pc_operand) {
1070 return ip + tail_size;
1071 }
1072
1073 #ifdef _LP64
1074 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1075 #else
1076 assert(which == imm_operand, "instruction has only an imm field");
1077 #endif // LP64
1078 return ip;
1079 }
1080
1081 address Assembler::locate_next_instruction(address inst) {
1082 // Secretly share code with locate_operand:
1083 return locate_operand(inst, end_pc_operand);
1084 }
1085
1086
1087 #ifdef ASSERT
1088 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1089 address inst = inst_mark();
1090 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1091 address opnd;
1092
1093 Relocation* r = rspec.reloc();
1094 if (r->type() == relocInfo::none) {
1095 return;
1096 } else if (r->is_call() || format == call32_operand) {
1097 // assert(format == imm32_operand, "cannot specify a nonzero format");
1098 opnd = locate_operand(inst, call32_operand);
1099 } else if (r->is_data()) {
1100 assert(format == imm_operand || format == disp32_operand
1101 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1102 opnd = locate_operand(inst, (WhichOperand)format);
1103 } else {
1104 assert(format == imm_operand, "cannot specify a format");
1105 return;
1106 }
1107 assert(opnd == pc(), "must put operand where relocs can find it");
1108 }
1109 #endif // ASSERT
1110
1111 void Assembler::emit_operand32(Register reg, Address adr) {
1112 assert(reg->encoding() < 8, "no extended registers");
1113 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1114 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1115 adr._rspec);
1116 }
1117
1118 void Assembler::emit_operand(Register reg, Address adr,
1119 int rip_relative_correction) {
1120 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1121 adr._rspec,
1122 rip_relative_correction);
1123 }
1124
1125 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1126 if (adr.isxmmindex()) {
1127 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
1128 } else {
1129 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1130 adr._rspec);
1131 }
1132 }
1133
1134 // MMX operations
1135 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1136 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1137 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1138 }
1139
1140 // work around gcc (3.2.1-7a) bug
1141 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1142 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1143 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1144 }
1145
1146
1147 void Assembler::emit_farith(int b1, int b2, int i) {
1148 assert(isByte(b1) && isByte(b2), "wrong opcode");
1149 assert(0 <= i && i < 8, "illegal stack offset");
1150 emit_int8(b1);
1151 emit_int8(b2 + i);
1152 }
1153
1154
1155 // Now the Assembler instructions (identical for 32/64 bits)
1156
1157 void Assembler::adcl(Address dst, int32_t imm32) {
1158 InstructionMark im(this);
1159 prefix(dst);
1160 emit_arith_operand(0x81, rdx, dst, imm32);
1161 }
1162
1163 void Assembler::adcl(Address dst, Register src) {
1164 InstructionMark im(this);
1165 prefix(dst, src);
1166 emit_int8(0x11);
1167 emit_operand(src, dst);
1168 }
1169
1170 void Assembler::adcl(Register dst, int32_t imm32) {
1171 prefix(dst);
1172 emit_arith(0x81, 0xD0, dst, imm32);
1173 }
1174
1175 void Assembler::adcl(Register dst, Address src) {
1176 InstructionMark im(this);
1177 prefix(src, dst);
1178 emit_int8(0x13);
1179 emit_operand(dst, src);
1180 }
1181
1182 void Assembler::adcl(Register dst, Register src) {
1183 (void) prefix_and_encode(dst->encoding(), src->encoding());
1184 emit_arith(0x13, 0xC0, dst, src);
1185 }
1186
1187 void Assembler::addl(Address dst, int32_t imm32) {
1188 InstructionMark im(this);
1189 prefix(dst);
1190 emit_arith_operand(0x81, rax, dst, imm32);
1191 }
1192
1193 void Assembler::addb(Address dst, int imm8) {
1194 InstructionMark im(this);
1195 prefix(dst);
1196 emit_int8((unsigned char)0x80);
1197 emit_operand(rax, dst, 1);
1198 emit_int8(imm8);
1199 }
1200
1201 void Assembler::addw(Address dst, int imm16) {
1202 InstructionMark im(this);
1203 emit_int8(0x66);
1204 prefix(dst);
1205 emit_int8((unsigned char)0x81);
1206 emit_operand(rax, dst, 2);
1207 emit_int16(imm16);
1208 }
1209
1210 void Assembler::addl(Address dst, Register src) {
1211 InstructionMark im(this);
1212 prefix(dst, src);
1213 emit_int8(0x01);
1214 emit_operand(src, dst);
1215 }
1216
1217 void Assembler::addl(Register dst, int32_t imm32) {
1218 prefix(dst);
1219 emit_arith(0x81, 0xC0, dst, imm32);
1220 }
1221
1222 void Assembler::addl(Register dst, Address src) {
1223 InstructionMark im(this);
1224 prefix(src, dst);
1225 emit_int8(0x03);
1226 emit_operand(dst, src);
1227 }
1228
1229 void Assembler::addl(Register dst, Register src) {
1230 (void) prefix_and_encode(dst->encoding(), src->encoding());
1231 emit_arith(0x03, 0xC0, dst, src);
1232 }
1233
1234 void Assembler::addr_nop_4() {
1235 assert(UseAddressNop, "no CPU support");
1236 // 4 bytes: NOP DWORD PTR [EAX+0]
1237 emit_int8(0x0F);
1238 emit_int8(0x1F);
1239 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1240 emit_int8(0); // 8-bits offset (1 byte)
1241 }
1242
1243 void Assembler::addr_nop_5() {
1244 assert(UseAddressNop, "no CPU support");
1245 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1246 emit_int8(0x0F);
1247 emit_int8(0x1F);
1248 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1249 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1250 emit_int8(0); // 8-bits offset (1 byte)
1251 }
1252
1253 void Assembler::addr_nop_7() {
1254 assert(UseAddressNop, "no CPU support");
1255 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1256 emit_int8(0x0F);
1257 emit_int8(0x1F);
1258 emit_int8((unsigned char)0x80);
1259 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1260 emit_int32(0); // 32-bits offset (4 bytes)
1261 }
1262
1263 void Assembler::addr_nop_8() {
1264 assert(UseAddressNop, "no CPU support");
1265 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1266 emit_int8(0x0F);
1267 emit_int8(0x1F);
1268 emit_int8((unsigned char)0x84);
1269 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1270 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1271 emit_int32(0); // 32-bits offset (4 bytes)
1272 }
1273
1274 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1275 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1277 attributes.set_rex_vex_w_reverted();
1278 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1279 emit_int8(0x58);
1280 emit_int8((unsigned char)(0xC0 | encode));
1281 }
1282
1283 void Assembler::addsd(XMMRegister dst, Address src) {
1284 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1285 InstructionMark im(this);
1286 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1288 attributes.set_rex_vex_w_reverted();
1289 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1290 emit_int8(0x58);
1291 emit_operand(dst, src);
1292 }
1293
1294 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1295 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1298 emit_int8(0x58);
1299 emit_int8((unsigned char)(0xC0 | encode));
1300 }
1301
1302 void Assembler::addss(XMMRegister dst, Address src) {
1303 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1304 InstructionMark im(this);
1305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1306 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1307 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1308 emit_int8(0x58);
1309 emit_operand(dst, src);
1310 }
1311
1312 void Assembler::aesdec(XMMRegister dst, Address src) {
1313 assert(VM_Version::supports_aes(), "");
1314 InstructionMark im(this);
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDE);
1318 emit_operand(dst, src);
1319 }
1320
1321 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1325 emit_int8((unsigned char)0xDE);
1326 emit_int8(0xC0 | encode);
1327 }
1328
1329 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1330 assert(VM_Version::supports_vaes(), "");
1331 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1332 attributes.set_is_evex_instruction();
1333 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDE);
1335 emit_int8((unsigned char)(0xC0 | encode));
1336 }
1337
1338
1339 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1340 assert(VM_Version::supports_aes(), "");
1341 InstructionMark im(this);
1342 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1343 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1344 emit_int8((unsigned char)0xDF);
1345 emit_operand(dst, src);
1346 }
1347
1348 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1349 assert(VM_Version::supports_aes(), "");
1350 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1351 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1352 emit_int8((unsigned char)0xDF);
1353 emit_int8((unsigned char)(0xC0 | encode));
1354 }
1355
1356 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1357 assert(VM_Version::supports_vaes(), "");
1358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1359 attributes.set_is_evex_instruction();
1360 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1361 emit_int8((unsigned char)0xDF);
1362 emit_int8((unsigned char)(0xC0 | encode));
1363 }
1364
1365 void Assembler::aesenc(XMMRegister dst, Address src) {
1366 assert(VM_Version::supports_aes(), "");
1367 InstructionMark im(this);
1368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1369 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1370 emit_int8((unsigned char)0xDC);
1371 emit_operand(dst, src);
1372 }
1373
1374 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1375 assert(VM_Version::supports_aes(), "");
1376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1377 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1378 emit_int8((unsigned char)0xDC);
1379 emit_int8(0xC0 | encode);
1380 }
1381
1382 void Assembler::aesenclast(XMMRegister dst, Address src) {
1383 assert(VM_Version::supports_aes(), "");
1384 InstructionMark im(this);
1385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1386 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1387 emit_int8((unsigned char)0xDD);
1388 emit_operand(dst, src);
1389 }
1390
1391 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1392 assert(VM_Version::supports_aes(), "");
1393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1394 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1395 emit_int8((unsigned char)0xDD);
1396 emit_int8((unsigned char)(0xC0 | encode));
1397 }
1398
1399 void Assembler::andl(Address dst, int32_t imm32) {
1400 InstructionMark im(this);
1401 prefix(dst);
1402 emit_int8((unsigned char)0x81);
1403 emit_operand(rsp, dst, 4);
1404 emit_int32(imm32);
1405 }
1406
1407 void Assembler::andl(Register dst, int32_t imm32) {
1408 prefix(dst);
1409 emit_arith(0x81, 0xE0, dst, imm32);
1410 }
1411
1412 void Assembler::andl(Register dst, Address src) {
1413 InstructionMark im(this);
1414 prefix(src, dst);
1415 emit_int8(0x23);
1416 emit_operand(dst, src);
1417 }
1418
1419 void Assembler::andl(Register dst, Register src) {
1420 (void) prefix_and_encode(dst->encoding(), src->encoding());
1421 emit_arith(0x23, 0xC0, dst, src);
1422 }
1423
1424 void Assembler::andnl(Register dst, Register src1, Register src2) {
1425 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1426 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1427 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1428 emit_int8((unsigned char)0xF2);
1429 emit_int8((unsigned char)(0xC0 | encode));
1430 }
1431
1432 void Assembler::andnl(Register dst, Register src1, Address src2) {
1433 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1434 InstructionMark im(this);
1435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1436 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1437 emit_int8((unsigned char)0xF2);
1438 emit_operand(dst, src2);
1439 }
1440
1441 void Assembler::bsfl(Register dst, Register src) {
1442 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1443 emit_int8(0x0F);
1444 emit_int8((unsigned char)0xBC);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::bsrl(Register dst, Register src) {
1449 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1450 emit_int8(0x0F);
1451 emit_int8((unsigned char)0xBD);
1452 emit_int8((unsigned char)(0xC0 | encode));
1453 }
1454
1455 void Assembler::bswapl(Register reg) { // bswap
1456 int encode = prefix_and_encode(reg->encoding());
1457 emit_int8(0x0F);
1458 emit_int8((unsigned char)(0xC8 | encode));
1459 }
1460
1461 void Assembler::blsil(Register dst, Register src) {
1462 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1463 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1464 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1465 emit_int8((unsigned char)0xF3);
1466 emit_int8((unsigned char)(0xC0 | encode));
1467 }
1468
1469 void Assembler::blsil(Register dst, Address src) {
1470 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1471 InstructionMark im(this);
1472 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1473 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1474 emit_int8((unsigned char)0xF3);
1475 emit_operand(rbx, src);
1476 }
1477
1478 void Assembler::blsmskl(Register dst, Register src) {
1479 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1480 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1481 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1482 emit_int8((unsigned char)0xF3);
1483 emit_int8((unsigned char)(0xC0 | encode));
1484 }
1485
1486 void Assembler::blsmskl(Register dst, Address src) {
1487 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1488 InstructionMark im(this);
1489 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1490 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1491 emit_int8((unsigned char)0xF3);
1492 emit_operand(rdx, src);
1493 }
1494
1495 void Assembler::blsrl(Register dst, Register src) {
1496 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1497 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1498 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1499 emit_int8((unsigned char)0xF3);
1500 emit_int8((unsigned char)(0xC0 | encode));
1501 }
1502
1503 void Assembler::blsrl(Register dst, Address src) {
1504 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1505 InstructionMark im(this);
1506 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1507 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1508 emit_int8((unsigned char)0xF3);
1509 emit_operand(rcx, src);
1510 }
1511
1512 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1513 // suspect disp32 is always good
1514 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1515
1516 if (L.is_bound()) {
1517 const int long_size = 5;
1518 int offs = (int)( target(L) - pc() );
1519 assert(offs <= 0, "assembler error");
1520 InstructionMark im(this);
1521 // 1110 1000 #32-bit disp
1522 emit_int8((unsigned char)0xE8);
1523 emit_data(offs - long_size, rtype, operand);
1524 } else {
1525 InstructionMark im(this);
1526 // 1110 1000 #32-bit disp
1527 L.add_patch_at(code(), locator());
1528
1529 emit_int8((unsigned char)0xE8);
1530 emit_data(int(0), rtype, operand);
1531 }
1532 }
1533
1534 void Assembler::call(Register dst) {
1535 int encode = prefix_and_encode(dst->encoding());
1536 emit_int8((unsigned char)0xFF);
1537 emit_int8((unsigned char)(0xD0 | encode));
1538 }
1539
1540
1541 void Assembler::call(Address adr) {
1542 InstructionMark im(this);
1543 prefix(adr);
1544 emit_int8((unsigned char)0xFF);
1545 emit_operand(rdx, adr);
1546 }
1547
1548 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1549 InstructionMark im(this);
1550 emit_int8((unsigned char)0xE8);
1551 intptr_t disp = entry - (pc() + sizeof(int32_t));
1552 // Entry is NULL in case of a scratch emit.
1553 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1554 // Technically, should use call32_operand, but this format is
1555 // implied by the fact that we're emitting a call instruction.
1556
1557 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1558 emit_data((int) disp, rspec, operand);
1559 }
1560
1561 void Assembler::cdql() {
1562 emit_int8((unsigned char)0x99);
1563 }
1564
1565 void Assembler::cld() {
1566 emit_int8((unsigned char)0xFC);
1567 }
1568
1569 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1570 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1571 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1572 emit_int8(0x0F);
1573 emit_int8(0x40 | cc);
1574 emit_int8((unsigned char)(0xC0 | encode));
1575 }
1576
1577
1578 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1579 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1580 prefix(src, dst);
1581 emit_int8(0x0F);
1582 emit_int8(0x40 | cc);
1583 emit_operand(dst, src);
1584 }
1585
1586 void Assembler::cmpb(Address dst, int imm8) {
1587 InstructionMark im(this);
1588 prefix(dst);
1589 emit_int8((unsigned char)0x80);
1590 emit_operand(rdi, dst, 1);
1591 emit_int8(imm8);
1592 }
1593
1594 void Assembler::cmpl(Address dst, int32_t imm32) {
1595 InstructionMark im(this);
1596 prefix(dst);
1597 emit_int8((unsigned char)0x81);
1598 emit_operand(rdi, dst, 4);
1599 emit_int32(imm32);
1600 }
1601
1602 void Assembler::cmpl(Register dst, int32_t imm32) {
1603 prefix(dst);
1604 emit_arith(0x81, 0xF8, dst, imm32);
1605 }
1606
1607 void Assembler::cmpl(Register dst, Register src) {
1608 (void) prefix_and_encode(dst->encoding(), src->encoding());
1609 emit_arith(0x3B, 0xC0, dst, src);
1610 }
1611
1612 void Assembler::cmpl(Register dst, Address src) {
1613 InstructionMark im(this);
1614 prefix(src, dst);
1615 emit_int8((unsigned char)0x3B);
1616 emit_operand(dst, src);
1617 }
1618
1619 void Assembler::cmpw(Address dst, int imm16) {
1620 InstructionMark im(this);
1621 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1622 emit_int8(0x66);
1623 emit_int8((unsigned char)0x81);
1624 emit_operand(rdi, dst, 2);
1625 emit_int16(imm16);
1626 }
1627
1628 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1629 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1630 // The ZF is set if the compared values were equal, and cleared otherwise.
1631 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1632 InstructionMark im(this);
1633 prefix(adr, reg);
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xB1);
1636 emit_operand(reg, adr);
1637 }
1638
1639 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1640 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1641 // The ZF is set if the compared values were equal, and cleared otherwise.
1642 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1643 InstructionMark im(this);
1644 prefix(adr, reg, true);
1645 emit_int8(0x0F);
1646 emit_int8((unsigned char)0xB0);
1647 emit_operand(reg, adr);
1648 }
1649
1650 void Assembler::comisd(XMMRegister dst, Address src) {
1651 // NOTE: dbx seems to decode this as comiss even though the
1652 // 0x66 is there. Strangly ucomisd comes out correct
1653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1654 InstructionMark im(this);
1655 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1656 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1657 attributes.set_rex_vex_w_reverted();
1658 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1659 emit_int8(0x2F);
1660 emit_operand(dst, src);
1661 }
1662
1663 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1664 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1665 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1666 attributes.set_rex_vex_w_reverted();
1667 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1668 emit_int8(0x2F);
1669 emit_int8((unsigned char)(0xC0 | encode));
1670 }
1671
1672 void Assembler::comiss(XMMRegister dst, Address src) {
1673 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1674 InstructionMark im(this);
1675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1676 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1677 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1678 emit_int8(0x2F);
1679 emit_operand(dst, src);
1680 }
1681
1682 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1683 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1685 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1686 emit_int8(0x2F);
1687 emit_int8((unsigned char)(0xC0 | encode));
1688 }
1689
1690 void Assembler::cpuid() {
1691 emit_int8(0x0F);
1692 emit_int8((unsigned char)0xA2);
1693 }
1694
1695 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1696 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1697 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1698 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1699 //
1700 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1701 //
1702 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1703 //
1704 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1705 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1706 assert(VM_Version::supports_sse4_2(), "");
1707 int8_t w = 0x01;
1708 Prefix p = Prefix_EMPTY;
1709
1710 emit_int8((int8_t)0xF2);
1711 switch (sizeInBytes) {
1712 case 1:
1713 w = 0;
1714 break;
1715 case 2:
1716 case 4:
1717 break;
1718 LP64_ONLY(case 8:)
1719 // This instruction is not valid in 32 bits
1720 // Note:
1721 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1722 //
1723 // Page B - 72 Vol. 2C says
1724 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1725 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1726 // F0!!!
1727 // while 3 - 208 Vol. 2A
1728 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1729 //
1730 // the 0 on a last bit is reserved for a different flavor of this instruction :
1731 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1732 p = REX_W;
1733 break;
1734 default:
1735 assert(0, "Unsupported value for a sizeInBytes argument");
1736 break;
1737 }
1738 LP64_ONLY(prefix(crc, v, p);)
1739 emit_int8((int8_t)0x0F);
1740 emit_int8(0x38);
1741 emit_int8((int8_t)(0xF0 | w));
1742 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1743 }
1744
1745 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1746 assert(VM_Version::supports_sse4_2(), "");
1747 InstructionMark im(this);
1748 int8_t w = 0x01;
1749 Prefix p = Prefix_EMPTY;
1750
1751 emit_int8((int8_t)0xF2);
1752 switch (sizeInBytes) {
1753 case 1:
1754 w = 0;
1755 break;
1756 case 2:
1757 case 4:
1758 break;
1759 LP64_ONLY(case 8:)
1760 // This instruction is not valid in 32 bits
1761 p = REX_W;
1762 break;
1763 default:
1764 assert(0, "Unsupported value for a sizeInBytes argument");
1765 break;
1766 }
1767 LP64_ONLY(prefix(crc, adr, p);)
1768 emit_int8((int8_t)0x0F);
1769 emit_int8(0x38);
1770 emit_int8((int8_t)(0xF0 | w));
1771 emit_operand(crc, adr);
1772 }
1773
1774 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1775 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1777 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1778 emit_int8((unsigned char)0xE6);
1779 emit_int8((unsigned char)(0xC0 | encode));
1780 }
1781
1782 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1785 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1786 emit_int8(0x5B);
1787 emit_int8((unsigned char)(0xC0 | encode));
1788 }
1789
1790 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1791 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1792 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1793 attributes.set_rex_vex_w_reverted();
1794 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1795 emit_int8(0x5A);
1796 emit_int8((unsigned char)(0xC0 | encode));
1797 }
1798
1799 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1800 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1801 InstructionMark im(this);
1802 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1804 attributes.set_rex_vex_w_reverted();
1805 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x5A);
1807 emit_operand(dst, src);
1808 }
1809
1810 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1811 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1814 emit_int8(0x2A);
1815 emit_int8((unsigned char)(0xC0 | encode));
1816 }
1817
1818 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1819 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1820 InstructionMark im(this);
1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1822 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1823 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2A);
1825 emit_operand(dst, src);
1826 }
1827
1828 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1829 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1831 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1832 emit_int8(0x2A);
1833 emit_int8((unsigned char)(0xC0 | encode));
1834 }
1835
1836 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1838 InstructionMark im(this);
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1841 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x2A);
1843 emit_operand(dst, src);
1844 }
1845
1846 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1847 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1849 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1850 emit_int8(0x2A);
1851 emit_int8((unsigned char)(0xC0 | encode));
1852 }
1853
1854 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1857 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1858 emit_int8(0x5A);
1859 emit_int8((unsigned char)(0xC0 | encode));
1860 }
1861
1862 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1863 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1864 InstructionMark im(this);
1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1866 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1867 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1868 emit_int8(0x5A);
1869 emit_operand(dst, src);
1870 }
1871
1872
1873 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1874 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1876 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1877 emit_int8(0x2C);
1878 emit_int8((unsigned char)(0xC0 | encode));
1879 }
1880
1881 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1882 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1884 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1885 emit_int8(0x2C);
1886 emit_int8((unsigned char)(0xC0 | encode));
1887 }
1888
1889 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1890 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1891 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1892 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1894 emit_int8((unsigned char)0xE6);
1895 emit_int8((unsigned char)(0xC0 | encode));
1896 }
1897
1898 void Assembler::decl(Address dst) {
1899 // Don't use it directly. Use MacroAssembler::decrement() instead.
1900 InstructionMark im(this);
1901 prefix(dst);
1902 emit_int8((unsigned char)0xFF);
1903 emit_operand(rcx, dst);
1904 }
1905
1906 void Assembler::divsd(XMMRegister dst, Address src) {
1907 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1908 InstructionMark im(this);
1909 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1910 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1911 attributes.set_rex_vex_w_reverted();
1912 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1913 emit_int8(0x5E);
1914 emit_operand(dst, src);
1915 }
1916
1917 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1920 attributes.set_rex_vex_w_reverted();
1921 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1922 emit_int8(0x5E);
1923 emit_int8((unsigned char)(0xC0 | encode));
1924 }
1925
1926 void Assembler::divss(XMMRegister dst, Address src) {
1927 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1928 InstructionMark im(this);
1929 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1930 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1931 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1932 emit_int8(0x5E);
1933 emit_operand(dst, src);
1934 }
1935
1936 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1937 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1939 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1940 emit_int8(0x5E);
1941 emit_int8((unsigned char)(0xC0 | encode));
1942 }
1943
1944 void Assembler::emms() {
1945 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1946 emit_int8(0x0F);
1947 emit_int8(0x77);
1948 }
1949
1950 void Assembler::hlt() {
1951 emit_int8((unsigned char)0xF4);
1952 }
1953
1954 void Assembler::idivl(Register src) {
1955 int encode = prefix_and_encode(src->encoding());
1956 emit_int8((unsigned char)0xF7);
1957 emit_int8((unsigned char)(0xF8 | encode));
1958 }
1959
1960 void Assembler::divl(Register src) { // Unsigned
1961 int encode = prefix_and_encode(src->encoding());
1962 emit_int8((unsigned char)0xF7);
1963 emit_int8((unsigned char)(0xF0 | encode));
1964 }
1965
1966 void Assembler::imull(Register src) {
1967 int encode = prefix_and_encode(src->encoding());
1968 emit_int8((unsigned char)0xF7);
1969 emit_int8((unsigned char)(0xE8 | encode));
1970 }
1971
1972 void Assembler::imull(Register dst, Register src) {
1973 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1974 emit_int8(0x0F);
1975 emit_int8((unsigned char)0xAF);
1976 emit_int8((unsigned char)(0xC0 | encode));
1977 }
1978
1979
1980 void Assembler::imull(Register dst, Register src, int value) {
1981 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1982 if (is8bit(value)) {
1983 emit_int8(0x6B);
1984 emit_int8((unsigned char)(0xC0 | encode));
1985 emit_int8(value & 0xFF);
1986 } else {
1987 emit_int8(0x69);
1988 emit_int8((unsigned char)(0xC0 | encode));
1989 emit_int32(value);
1990 }
1991 }
1992
1993 void Assembler::imull(Register dst, Address src) {
1994 InstructionMark im(this);
1995 prefix(src, dst);
1996 emit_int8(0x0F);
1997 emit_int8((unsigned char) 0xAF);
1998 emit_operand(dst, src);
1999 }
2000
2001
2002 void Assembler::incl(Address dst) {
2003 // Don't use it directly. Use MacroAssembler::increment() instead.
2004 InstructionMark im(this);
2005 prefix(dst);
2006 emit_int8((unsigned char)0xFF);
2007 emit_operand(rax, dst);
2008 }
2009
2010 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2011 InstructionMark im(this);
2012 assert((0 <= cc) && (cc < 16), "illegal cc");
2013 if (L.is_bound()) {
2014 address dst = target(L);
2015 assert(dst != NULL, "jcc most probably wrong");
2016
2017 const int short_size = 2;
2018 const int long_size = 6;
2019 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2020 if (maybe_short && is8bit(offs - short_size)) {
2021 // 0111 tttn #8-bit disp
2022 emit_int8(0x70 | cc);
2023 emit_int8((offs - short_size) & 0xFF);
2024 } else {
2025 // 0000 1111 1000 tttn #32-bit disp
2026 assert(is_simm32(offs - long_size),
2027 "must be 32bit offset (call4)");
2028 emit_int8(0x0F);
2029 emit_int8((unsigned char)(0x80 | cc));
2030 emit_int32(offs - long_size);
2031 }
2032 } else {
2033 // Note: could eliminate cond. jumps to this jump if condition
2034 // is the same however, seems to be rather unlikely case.
2035 // Note: use jccb() if label to be bound is very close to get
2036 // an 8-bit displacement
2037 L.add_patch_at(code(), locator());
2038 emit_int8(0x0F);
2039 emit_int8((unsigned char)(0x80 | cc));
2040 emit_int32(0);
2041 }
2042 }
2043
2044 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2045 if (L.is_bound()) {
2046 const int short_size = 2;
2047 address entry = target(L);
2048 #ifdef ASSERT
2049 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2050 intptr_t delta = short_branch_delta();
2051 if (delta != 0) {
2052 dist += (dist < 0 ? (-delta) :delta);
2053 }
2054 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2055 #endif
2056 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2057 // 0111 tttn #8-bit disp
2058 emit_int8(0x70 | cc);
2059 emit_int8((offs - short_size) & 0xFF);
2060 } else {
2061 InstructionMark im(this);
2062 L.add_patch_at(code(), locator(), file, line);
2063 emit_int8(0x70 | cc);
2064 emit_int8(0);
2065 }
2066 }
2067
2068 void Assembler::jmp(Address adr) {
2069 InstructionMark im(this);
2070 prefix(adr);
2071 emit_int8((unsigned char)0xFF);
2072 emit_operand(rsp, adr);
2073 }
2074
2075 void Assembler::jmp(Label& L, bool maybe_short) {
2076 if (L.is_bound()) {
2077 address entry = target(L);
2078 assert(entry != NULL, "jmp most probably wrong");
2079 InstructionMark im(this);
2080 const int short_size = 2;
2081 const int long_size = 5;
2082 intptr_t offs = entry - pc();
2083 if (maybe_short && is8bit(offs - short_size)) {
2084 emit_int8((unsigned char)0xEB);
2085 emit_int8((offs - short_size) & 0xFF);
2086 } else {
2087 emit_int8((unsigned char)0xE9);
2088 emit_int32(offs - long_size);
2089 }
2090 } else {
2091 // By default, forward jumps are always 32-bit displacements, since
2092 // we can't yet know where the label will be bound. If you're sure that
2093 // the forward jump will not run beyond 256 bytes, use jmpb to
2094 // force an 8-bit displacement.
2095 InstructionMark im(this);
2096 L.add_patch_at(code(), locator());
2097 emit_int8((unsigned char)0xE9);
2098 emit_int32(0);
2099 }
2100 }
2101
2102 void Assembler::jmp(Register entry) {
2103 int encode = prefix_and_encode(entry->encoding());
2104 emit_int8((unsigned char)0xFF);
2105 emit_int8((unsigned char)(0xE0 | encode));
2106 }
2107
2108 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2109 InstructionMark im(this);
2110 emit_int8((unsigned char)0xE9);
2111 assert(dest != NULL, "must have a target");
2112 intptr_t disp = dest - (pc() + sizeof(int32_t));
2113 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2114 emit_data(disp, rspec.reloc(), call32_operand);
2115 }
2116
2117 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2118 if (L.is_bound()) {
2119 const int short_size = 2;
2120 address entry = target(L);
2121 assert(entry != NULL, "jmp most probably wrong");
2122 #ifdef ASSERT
2123 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2124 intptr_t delta = short_branch_delta();
2125 if (delta != 0) {
2126 dist += (dist < 0 ? (-delta) :delta);
2127 }
2128 assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
2129 #endif
2130 intptr_t offs = entry - pc();
2131 emit_int8((unsigned char)0xEB);
2132 emit_int8((offs - short_size) & 0xFF);
2133 } else {
2134 InstructionMark im(this);
2135 L.add_patch_at(code(), locator(), file, line);
2136 emit_int8((unsigned char)0xEB);
2137 emit_int8(0);
2138 }
2139 }
2140
2141 void Assembler::ldmxcsr( Address src) {
2142 if (UseAVX > 0 ) {
2143 InstructionMark im(this);
2144 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2145 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2146 emit_int8((unsigned char)0xAE);
2147 emit_operand(as_Register(2), src);
2148 } else {
2149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2150 InstructionMark im(this);
2151 prefix(src);
2152 emit_int8(0x0F);
2153 emit_int8((unsigned char)0xAE);
2154 emit_operand(as_Register(2), src);
2155 }
2156 }
2157
2158 void Assembler::leal(Register dst, Address src) {
2159 InstructionMark im(this);
2160 #ifdef _LP64
2161 emit_int8(0x67); // addr32
2162 prefix(src, dst);
2163 #endif // LP64
2164 emit_int8((unsigned char)0x8D);
2165 emit_operand(dst, src);
2166 }
2167
2168 void Assembler::lfence() {
2169 emit_int8(0x0F);
2170 emit_int8((unsigned char)0xAE);
2171 emit_int8((unsigned char)0xE8);
2172 }
2173
2174 void Assembler::lock() {
2175 emit_int8((unsigned char)0xF0);
2176 }
2177
2178 void Assembler::lzcntl(Register dst, Register src) {
2179 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2180 emit_int8((unsigned char)0xF3);
2181 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2182 emit_int8(0x0F);
2183 emit_int8((unsigned char)0xBD);
2184 emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186
2187 // Emit mfence instruction
2188 void Assembler::mfence() {
2189 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2190 emit_int8(0x0F);
2191 emit_int8((unsigned char)0xAE);
2192 emit_int8((unsigned char)0xF0);
2193 }
2194
2195 void Assembler::mov(Register dst, Register src) {
2196 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2197 }
2198
2199 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2201 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2202 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2203 attributes.set_rex_vex_w_reverted();
2204 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2205 emit_int8(0x28);
2206 emit_int8((unsigned char)(0xC0 | encode));
2207 }
2208
2209 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2210 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2211 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2212 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2213 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2214 emit_int8(0x28);
2215 emit_int8((unsigned char)(0xC0 | encode));
2216 }
2217
2218 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2219 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2221 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2222 emit_int8(0x16);
2223 emit_int8((unsigned char)(0xC0 | encode));
2224 }
2225
2226 void Assembler::movb(Register dst, Address src) {
2227 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2228 InstructionMark im(this);
2229 prefix(src, dst, true);
2230 emit_int8((unsigned char)0x8A);
2231 emit_operand(dst, src);
2232 }
2233
2234 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2235 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2236 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2237 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2238 attributes.set_rex_vex_w_reverted();
2239 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2240 emit_int8(0x12);
2241 emit_int8(0xC0 | encode);
2242 }
2243
2244 void Assembler::kmovbl(KRegister dst, Register src) {
2245 assert(VM_Version::supports_avx512dq(), "");
2246 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2247 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2248 emit_int8((unsigned char)0x92);
2249 emit_int8((unsigned char)(0xC0 | encode));
2250 }
2251
2252 void Assembler::kmovbl(Register dst, KRegister src) {
2253 assert(VM_Version::supports_avx512dq(), "");
2254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2255 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2256 emit_int8((unsigned char)0x93);
2257 emit_int8((unsigned char)(0xC0 | encode));
2258 }
2259
2260 void Assembler::kmovwl(KRegister dst, Register src) {
2261 assert(VM_Version::supports_evex(), "");
2262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2263 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2264 emit_int8((unsigned char)0x92);
2265 emit_int8((unsigned char)(0xC0 | encode));
2266 }
2267
2268 void Assembler::kmovwl(Register dst, KRegister src) {
2269 assert(VM_Version::supports_evex(), "");
2270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2271 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2272 emit_int8((unsigned char)0x93);
2273 emit_int8((unsigned char)(0xC0 | encode));
2274 }
2275
2276 void Assembler::kmovwl(KRegister dst, Address src) {
2277 assert(VM_Version::supports_evex(), "");
2278 InstructionMark im(this);
2279 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2280 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2281 emit_int8((unsigned char)0x90);
2282 emit_operand((Register)dst, src);
2283 }
2284
2285 void Assembler::kmovdl(KRegister dst, Register src) {
2286 assert(VM_Version::supports_avx512bw(), "");
2287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2288 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2289 emit_int8((unsigned char)0x92);
2290 emit_int8((unsigned char)(0xC0 | encode));
2291 }
2292
2293 void Assembler::kmovdl(Register dst, KRegister src) {
2294 assert(VM_Version::supports_avx512bw(), "");
2295 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2296 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2297 emit_int8((unsigned char)0x93);
2298 emit_int8((unsigned char)(0xC0 | encode));
2299 }
2300
2301 void Assembler::kmovql(KRegister dst, KRegister src) {
2302 assert(VM_Version::supports_avx512bw(), "");
2303 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2304 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2305 emit_int8((unsigned char)0x90);
2306 emit_int8((unsigned char)(0xC0 | encode));
2307 }
2308
2309 void Assembler::kmovql(KRegister dst, Address src) {
2310 assert(VM_Version::supports_avx512bw(), "");
2311 InstructionMark im(this);
2312 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2313 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2314 emit_int8((unsigned char)0x90);
2315 emit_operand((Register)dst, src);
2316 }
2317
2318 void Assembler::kmovql(Address dst, KRegister src) {
2319 assert(VM_Version::supports_avx512bw(), "");
2320 InstructionMark im(this);
2321 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2322 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2323 emit_int8((unsigned char)0x90);
2324 emit_operand((Register)src, dst);
2325 }
2326
2327 void Assembler::kmovql(KRegister dst, Register src) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x92);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::kmovql(Register dst, KRegister src) {
2336 assert(VM_Version::supports_avx512bw(), "");
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2339 emit_int8((unsigned char)0x93);
2340 emit_int8((unsigned char)(0xC0 | encode));
2341 }
2342
2343 void Assembler::knotwl(KRegister dst, KRegister src) {
2344 assert(VM_Version::supports_evex(), "");
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2346 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2347 emit_int8((unsigned char)0x44);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 // This instruction produces ZF or CF flags
2352 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2353 assert(VM_Version::supports_avx512dq(), "");
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2356 emit_int8((unsigned char)0x98);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 // This instruction produces ZF or CF flags
2361 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2362 assert(VM_Version::supports_evex(), "");
2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2364 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2365 emit_int8((unsigned char)0x98);
2366 emit_int8((unsigned char)(0xC0 | encode));
2367 }
2368
2369 // This instruction produces ZF or CF flags
2370 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2371 assert(VM_Version::supports_avx512bw(), "");
2372 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2373 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2374 emit_int8((unsigned char)0x98);
2375 emit_int8((unsigned char)(0xC0 | encode));
2376 }
2377
2378 // This instruction produces ZF or CF flags
2379 void Assembler::kortestql(KRegister src1, KRegister src2) {
2380 assert(VM_Version::supports_avx512bw(), "");
2381 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2382 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2383 emit_int8((unsigned char)0x98);
2384 emit_int8((unsigned char)(0xC0 | encode));
2385 }
2386
2387 // This instruction produces ZF or CF flags
2388 void Assembler::ktestql(KRegister src1, KRegister src2) {
2389 assert(VM_Version::supports_avx512bw(), "");
2390 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2391 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2392 emit_int8((unsigned char)0x99);
2393 emit_int8((unsigned char)(0xC0 | encode));
2394 }
2395
2396 void Assembler::ktestq(KRegister src1, KRegister src2) {
2397 assert(VM_Version::supports_avx512bw(), "");
2398 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2399 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2400 emit_int8((unsigned char)0x99);
2401 emit_int8((unsigned char)(0xC0 | encode));
2402 }
2403
2404 void Assembler::ktestd(KRegister src1, KRegister src2) {
2405 assert(VM_Version::supports_avx512bw(), "");
2406 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2407 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2408 emit_int8((unsigned char)0x99);
2409 emit_int8((unsigned char)(0xC0 | encode));
2410 }
2411
2412 void Assembler::movb(Address dst, int imm8) {
2413 InstructionMark im(this);
2414 prefix(dst);
2415 emit_int8((unsigned char)0xC6);
2416 emit_operand(rax, dst, 1);
2417 emit_int8(imm8);
2418 }
2419
2420
2421 void Assembler::movb(Address dst, Register src) {
2422 assert(src->has_byte_register(), "must have byte register");
2423 InstructionMark im(this);
2424 prefix(dst, src, true);
2425 emit_int8((unsigned char)0x88);
2426 emit_operand(src, dst);
2427 }
2428
2429 void Assembler::movdl(XMMRegister dst, Register src) {
2430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2431 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2432 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2433 emit_int8(0x6E);
2434 emit_int8((unsigned char)(0xC0 | encode));
2435 }
2436
2437 void Assembler::movdl(Register dst, XMMRegister src) {
2438 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2439 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2440 // swap src/dst to get correct prefix
2441 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2442 emit_int8(0x7E);
2443 emit_int8((unsigned char)(0xC0 | encode));
2444 }
2445
2446 void Assembler::movdl(XMMRegister dst, Address src) {
2447 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2448 InstructionMark im(this);
2449 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2450 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2451 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2452 emit_int8(0x6E);
2453 emit_operand(dst, src);
2454 }
2455
2456 void Assembler::movdl(Address dst, XMMRegister src) {
2457 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2458 InstructionMark im(this);
2459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2460 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2461 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2462 emit_int8(0x7E);
2463 emit_operand(src, dst);
2464 }
2465
2466 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2468 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2469 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2470 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2471 emit_int8(0x6F);
2472 emit_int8((unsigned char)(0xC0 | encode));
2473 }
2474
2475 void Assembler::movdqa(XMMRegister dst, Address src) {
2476 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2477 InstructionMark im(this);
2478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2479 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2480 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2481 emit_int8(0x6F);
2482 emit_operand(dst, src);
2483 }
2484
2485 void Assembler::movdqu(XMMRegister dst, Address src) {
2486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2487 InstructionMark im(this);
2488 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2489 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2490 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2491 emit_int8(0x6F);
2492 emit_operand(dst, src);
2493 }
2494
2495 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2496 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2497 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2498 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2499 emit_int8(0x6F);
2500 emit_int8((unsigned char)(0xC0 | encode));
2501 }
2502
2503 void Assembler::movdqu(Address dst, XMMRegister src) {
2504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2505 InstructionMark im(this);
2506 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2507 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2508 attributes.reset_is_clear_context();
2509 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2510 emit_int8(0x7F);
2511 emit_operand(src, dst);
2512 }
2513
2514 // Move Unaligned 256bit Vector
2515 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2516 assert(UseAVX > 0, "");
2517 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2518 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2519 emit_int8(0x6F);
2520 emit_int8((unsigned char)(0xC0 | encode));
2521 }
2522
2523 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2524 assert(UseAVX > 0, "");
2525 InstructionMark im(this);
2526 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2527 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2528 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2529 emit_int8(0x6F);
2530 emit_operand(dst, src);
2531 }
2532
2533 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2534 assert(UseAVX > 0, "");
2535 InstructionMark im(this);
2536 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2537 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2538 attributes.reset_is_clear_context();
2539 // swap src<->dst for encoding
2540 assert(src != xnoreg, "sanity");
2541 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2542 emit_int8(0x7F);
2543 emit_operand(src, dst);
2544 }
2545
2546 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2547 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2548 assert(VM_Version::supports_evex(), "");
2549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2550 attributes.set_is_evex_instruction();
2551 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2552 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2553 emit_int8(0x6F);
2554 emit_int8((unsigned char)(0xC0 | encode));
2555 }
2556
2557 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2558 assert(VM_Version::supports_evex(), "");
2559 InstructionMark im(this);
2560 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2561 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2562 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2563 attributes.set_is_evex_instruction();
2564 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2565 emit_int8(0x6F);
2566 emit_operand(dst, src);
2567 }
2568
2569 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2570 assert(VM_Version::supports_evex(), "");
2571 assert(src != xnoreg, "sanity");
2572 InstructionMark im(this);
2573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2574 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2575 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2576 attributes.set_is_evex_instruction();
2577 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2578 emit_int8(0x7F);
2579 emit_operand(src, dst);
2580 }
2581
2582 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2583 assert(VM_Version::supports_avx512vlbw(), "");
2584 assert(is_vector_masking(), ""); // For stub code use only
2585 InstructionMark im(this);
2586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2587 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2588 attributes.set_embedded_opmask_register_specifier(mask);
2589 attributes.set_is_evex_instruction();
2590 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2591 emit_int8(0x6F);
2592 emit_operand(dst, src);
2593 }
2594
2595 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2596 assert(VM_Version::supports_evex(), "");
2597 InstructionMark im(this);
2598 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2599 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2600 attributes.set_is_evex_instruction();
2601 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2602 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2603 emit_int8(0x6F);
2604 emit_operand(dst, src);
2605 }
2606
2607 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
2608 assert(is_vector_masking(), "");
2609 assert(VM_Version::supports_avx512vlbw(), "");
2610 InstructionMark im(this);
2611 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2612 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2613 attributes.set_embedded_opmask_register_specifier(mask);
2614 attributes.set_is_evex_instruction();
2615 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2616 emit_int8(0x6F);
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2621 assert(VM_Version::supports_evex(), "");
2622 assert(src != xnoreg, "sanity");
2623 InstructionMark im(this);
2624 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2625 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2626 attributes.set_is_evex_instruction();
2627 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2628 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2629 emit_int8(0x7F);
2630 emit_operand(src, dst);
2631 }
2632
2633 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) {
2634 assert(VM_Version::supports_avx512vlbw(), "");
2635 assert(src != xnoreg, "sanity");
2636 InstructionMark im(this);
2637 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2638 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2639 attributes.reset_is_clear_context();
2640 attributes.set_embedded_opmask_register_specifier(mask);
2641 attributes.set_is_evex_instruction();
2642 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2643 emit_int8(0x7F);
2644 emit_operand(src, dst);
2645 }
2646
2647 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2648 assert(VM_Version::supports_evex(), "");
2649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2650 attributes.set_is_evex_instruction();
2651 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2652 emit_int8(0x6F);
2653 emit_int8((unsigned char)(0xC0 | encode));
2654 }
2655
2656 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2657 assert(VM_Version::supports_evex(), "");
2658 InstructionMark im(this);
2659 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2660 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2661 attributes.set_is_evex_instruction();
2662 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2663 emit_int8(0x6F);
2664 emit_operand(dst, src);
2665 }
2666
2667 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2668 assert(VM_Version::supports_evex(), "");
2669 assert(src != xnoreg, "sanity");
2670 InstructionMark im(this);
2671 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2672 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2673 attributes.reset_is_clear_context();
2674 attributes.set_is_evex_instruction();
2675 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2676 emit_int8(0x7F);
2677 emit_operand(src, dst);
2678 }
2679
2680 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2681 assert(VM_Version::supports_evex(), "");
2682 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2683 attributes.set_is_evex_instruction();
2684 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2685 emit_int8(0x6F);
2686 emit_int8((unsigned char)(0xC0 | encode));
2687 }
2688
2689 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2690 assert(VM_Version::supports_evex(), "");
2691 InstructionMark im(this);
2692 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2693 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2694 attributes.set_is_evex_instruction();
2695 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2696 emit_int8(0x6F);
2697 emit_operand(dst, src);
2698 }
2699
2700 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2701 assert(VM_Version::supports_evex(), "");
2702 assert(src != xnoreg, "sanity");
2703 InstructionMark im(this);
2704 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2705 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2706 attributes.reset_is_clear_context();
2707 attributes.set_is_evex_instruction();
2708 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2709 emit_int8(0x7F);
2710 emit_operand(src, dst);
2711 }
2712
2713 // Uses zero extension on 64bit
2714
2715 void Assembler::movl(Register dst, int32_t imm32) {
2716 int encode = prefix_and_encode(dst->encoding());
2717 emit_int8((unsigned char)(0xB8 | encode));
2718 emit_int32(imm32);
2719 }
2720
2721 void Assembler::movl(Register dst, Register src) {
2722 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2723 emit_int8((unsigned char)0x8B);
2724 emit_int8((unsigned char)(0xC0 | encode));
2725 }
2726
2727 void Assembler::movl(Register dst, Address src) {
2728 InstructionMark im(this);
2729 prefix(src, dst);
2730 emit_int8((unsigned char)0x8B);
2731 emit_operand(dst, src);
2732 }
2733
2734 void Assembler::movl(Address dst, int32_t imm32) {
2735 InstructionMark im(this);
2736 prefix(dst);
2737 emit_int8((unsigned char)0xC7);
2738 emit_operand(rax, dst, 4);
2739 emit_int32(imm32);
2740 }
2741
2742 void Assembler::movl(Address dst, Register src) {
2743 InstructionMark im(this);
2744 prefix(dst, src);
2745 emit_int8((unsigned char)0x89);
2746 emit_operand(src, dst);
2747 }
2748
2749 // New cpus require to use movsd and movss to avoid partial register stall
2750 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2751 // The selection is done in MacroAssembler::movdbl() and movflt().
2752 void Assembler::movlpd(XMMRegister dst, Address src) {
2753 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2754 InstructionMark im(this);
2755 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2756 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2757 attributes.set_rex_vex_w_reverted();
2758 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2759 emit_int8(0x12);
2760 emit_operand(dst, src);
2761 }
2762
2763 void Assembler::movq( MMXRegister dst, Address src ) {
2764 assert( VM_Version::supports_mmx(), "" );
2765 emit_int8(0x0F);
2766 emit_int8(0x6F);
2767 emit_operand(dst, src);
2768 }
2769
2770 void Assembler::movq( Address dst, MMXRegister src ) {
2771 assert( VM_Version::supports_mmx(), "" );
2772 emit_int8(0x0F);
2773 emit_int8(0x7F);
2774 // workaround gcc (3.2.1-7a) bug
2775 // In that version of gcc with only an emit_operand(MMX, Address)
2776 // gcc will tail jump and try and reverse the parameters completely
2777 // obliterating dst in the process. By having a version available
2778 // that doesn't need to swap the args at the tail jump the bug is
2779 // avoided.
2780 emit_operand(dst, src);
2781 }
2782
2783 void Assembler::movq(XMMRegister dst, Address src) {
2784 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2785 InstructionMark im(this);
2786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2787 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2788 attributes.set_rex_vex_w_reverted();
2789 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2790 emit_int8(0x7E);
2791 emit_operand(dst, src);
2792 }
2793
2794 void Assembler::movq(Address dst, XMMRegister src) {
2795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2796 InstructionMark im(this);
2797 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2799 attributes.set_rex_vex_w_reverted();
2800 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2801 emit_int8((unsigned char)0xD6);
2802 emit_operand(src, dst);
2803 }
2804
2805 void Assembler::movsbl(Register dst, Address src) { // movsxb
2806 InstructionMark im(this);
2807 prefix(src, dst);
2808 emit_int8(0x0F);
2809 emit_int8((unsigned char)0xBE);
2810 emit_operand(dst, src);
2811 }
2812
2813 void Assembler::movsbl(Register dst, Register src) { // movsxb
2814 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2815 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2816 emit_int8(0x0F);
2817 emit_int8((unsigned char)0xBE);
2818 emit_int8((unsigned char)(0xC0 | encode));
2819 }
2820
2821 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2822 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2823 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2824 attributes.set_rex_vex_w_reverted();
2825 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2826 emit_int8(0x10);
2827 emit_int8((unsigned char)(0xC0 | encode));
2828 }
2829
2830 void Assembler::movsd(XMMRegister dst, Address src) {
2831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2832 InstructionMark im(this);
2833 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2835 attributes.set_rex_vex_w_reverted();
2836 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2837 emit_int8(0x10);
2838 emit_operand(dst, src);
2839 }
2840
2841 void Assembler::movsd(Address dst, XMMRegister src) {
2842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2843 InstructionMark im(this);
2844 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2845 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2846 attributes.reset_is_clear_context();
2847 attributes.set_rex_vex_w_reverted();
2848 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2849 emit_int8(0x11);
2850 emit_operand(src, dst);
2851 }
2852
2853 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2854 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2857 emit_int8(0x10);
2858 emit_int8((unsigned char)(0xC0 | encode));
2859 }
2860
2861 void Assembler::movss(XMMRegister dst, Address src) {
2862 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2863 InstructionMark im(this);
2864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2866 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2867 emit_int8(0x10);
2868 emit_operand(dst, src);
2869 }
2870
2871 void Assembler::movss(Address dst, XMMRegister src) {
2872 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2873 InstructionMark im(this);
2874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2875 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2876 attributes.reset_is_clear_context();
2877 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2878 emit_int8(0x11);
2879 emit_operand(src, dst);
2880 }
2881
2882 void Assembler::movswl(Register dst, Address src) { // movsxw
2883 InstructionMark im(this);
2884 prefix(src, dst);
2885 emit_int8(0x0F);
2886 emit_int8((unsigned char)0xBF);
2887 emit_operand(dst, src);
2888 }
2889
2890 void Assembler::movswl(Register dst, Register src) { // movsxw
2891 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2892 emit_int8(0x0F);
2893 emit_int8((unsigned char)0xBF);
2894 emit_int8((unsigned char)(0xC0 | encode));
2895 }
2896
2897 void Assembler::movw(Address dst, int imm16) {
2898 InstructionMark im(this);
2899
2900 emit_int8(0x66); // switch to 16-bit mode
2901 prefix(dst);
2902 emit_int8((unsigned char)0xC7);
2903 emit_operand(rax, dst, 2);
2904 emit_int16(imm16);
2905 }
2906
2907 void Assembler::movw(Register dst, Address src) {
2908 InstructionMark im(this);
2909 emit_int8(0x66);
2910 prefix(src, dst);
2911 emit_int8((unsigned char)0x8B);
2912 emit_operand(dst, src);
2913 }
2914
2915 void Assembler::movw(Address dst, Register src) {
2916 InstructionMark im(this);
2917 emit_int8(0x66);
2918 prefix(dst, src);
2919 emit_int8((unsigned char)0x89);
2920 emit_operand(src, dst);
2921 }
2922
2923 void Assembler::movzbl(Register dst, Address src) { // movzxb
2924 InstructionMark im(this);
2925 prefix(src, dst);
2926 emit_int8(0x0F);
2927 emit_int8((unsigned char)0xB6);
2928 emit_operand(dst, src);
2929 }
2930
2931 void Assembler::movzbl(Register dst, Register src) { // movzxb
2932 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2933 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2934 emit_int8(0x0F);
2935 emit_int8((unsigned char)0xB6);
2936 emit_int8(0xC0 | encode);
2937 }
2938
2939 void Assembler::movzwl(Register dst, Address src) { // movzxw
2940 InstructionMark im(this);
2941 prefix(src, dst);
2942 emit_int8(0x0F);
2943 emit_int8((unsigned char)0xB7);
2944 emit_operand(dst, src);
2945 }
2946
2947 void Assembler::movzwl(Register dst, Register src) { // movzxw
2948 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2949 emit_int8(0x0F);
2950 emit_int8((unsigned char)0xB7);
2951 emit_int8(0xC0 | encode);
2952 }
2953
2954 void Assembler::mull(Address src) {
2955 InstructionMark im(this);
2956 prefix(src);
2957 emit_int8((unsigned char)0xF7);
2958 emit_operand(rsp, src);
2959 }
2960
2961 void Assembler::mull(Register src) {
2962 int encode = prefix_and_encode(src->encoding());
2963 emit_int8((unsigned char)0xF7);
2964 emit_int8((unsigned char)(0xE0 | encode));
2965 }
2966
2967 void Assembler::mulsd(XMMRegister dst, Address src) {
2968 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2969 InstructionMark im(this);
2970 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2971 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2972 attributes.set_rex_vex_w_reverted();
2973 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2974 emit_int8(0x59);
2975 emit_operand(dst, src);
2976 }
2977
2978 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2980 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2981 attributes.set_rex_vex_w_reverted();
2982 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2983 emit_int8(0x59);
2984 emit_int8((unsigned char)(0xC0 | encode));
2985 }
2986
2987 void Assembler::mulss(XMMRegister dst, Address src) {
2988 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2989 InstructionMark im(this);
2990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2991 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2992 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2993 emit_int8(0x59);
2994 emit_operand(dst, src);
2995 }
2996
2997 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2998 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3001 emit_int8(0x59);
3002 emit_int8((unsigned char)(0xC0 | encode));
3003 }
3004
3005 void Assembler::negl(Register dst) {
3006 int encode = prefix_and_encode(dst->encoding());
3007 emit_int8((unsigned char)0xF7);
3008 emit_int8((unsigned char)(0xD8 | encode));
3009 }
3010
3011 void Assembler::nop(int i) {
3012 #ifdef ASSERT
3013 assert(i > 0, " ");
3014 // The fancy nops aren't currently recognized by debuggers making it a
3015 // pain to disassemble code while debugging. If asserts are on clearly
3016 // speed is not an issue so simply use the single byte traditional nop
3017 // to do alignment.
3018
3019 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3020 return;
3021
3022 #endif // ASSERT
3023
3024 if (UseAddressNop && VM_Version::is_intel()) {
3025 //
3026 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3027 // 1: 0x90
3028 // 2: 0x66 0x90
3029 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3030 // 4: 0x0F 0x1F 0x40 0x00
3031 // 5: 0x0F 0x1F 0x44 0x00 0x00
3032 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3033 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3034 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3035 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3036 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3037 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3038
3039 // The rest coding is Intel specific - don't use consecutive address nops
3040
3041 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3042 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3043 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3044 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3045
3046 while(i >= 15) {
3047 // For Intel don't generate consecutive addess nops (mix with regular nops)
3048 i -= 15;
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66); // size prefix
3051 emit_int8(0x66); // size prefix
3052 addr_nop_8();
3053 emit_int8(0x66); // size prefix
3054 emit_int8(0x66); // size prefix
3055 emit_int8(0x66); // size prefix
3056 emit_int8((unsigned char)0x90);
3057 // nop
3058 }
3059 switch (i) {
3060 case 14:
3061 emit_int8(0x66); // size prefix
3062 case 13:
3063 emit_int8(0x66); // size prefix
3064 case 12:
3065 addr_nop_8();
3066 emit_int8(0x66); // size prefix
3067 emit_int8(0x66); // size prefix
3068 emit_int8(0x66); // size prefix
3069 emit_int8((unsigned char)0x90);
3070 // nop
3071 break;
3072 case 11:
3073 emit_int8(0x66); // size prefix
3074 case 10:
3075 emit_int8(0x66); // size prefix
3076 case 9:
3077 emit_int8(0x66); // size prefix
3078 case 8:
3079 addr_nop_8();
3080 break;
3081 case 7:
3082 addr_nop_7();
3083 break;
3084 case 6:
3085 emit_int8(0x66); // size prefix
3086 case 5:
3087 addr_nop_5();
3088 break;
3089 case 4:
3090 addr_nop_4();
3091 break;
3092 case 3:
3093 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3094 emit_int8(0x66); // size prefix
3095 case 2:
3096 emit_int8(0x66); // size prefix
3097 case 1:
3098 emit_int8((unsigned char)0x90);
3099 // nop
3100 break;
3101 default:
3102 assert(i == 0, " ");
3103 }
3104 return;
3105 }
3106 if (UseAddressNop && VM_Version::is_amd()) {
3107 //
3108 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3109 // 1: 0x90
3110 // 2: 0x66 0x90
3111 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3112 // 4: 0x0F 0x1F 0x40 0x00
3113 // 5: 0x0F 0x1F 0x44 0x00 0x00
3114 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3115 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3116 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3117 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3118 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3119 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3120
3121 // The rest coding is AMD specific - use consecutive address nops
3122
3123 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3124 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3125 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3126 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3127 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3128 // Size prefixes (0x66) are added for larger sizes
3129
3130 while(i >= 22) {
3131 i -= 11;
3132 emit_int8(0x66); // size prefix
3133 emit_int8(0x66); // size prefix
3134 emit_int8(0x66); // size prefix
3135 addr_nop_8();
3136 }
3137 // Generate first nop for size between 21-12
3138 switch (i) {
3139 case 21:
3140 i -= 1;
3141 emit_int8(0x66); // size prefix
3142 case 20:
3143 case 19:
3144 i -= 1;
3145 emit_int8(0x66); // size prefix
3146 case 18:
3147 case 17:
3148 i -= 1;
3149 emit_int8(0x66); // size prefix
3150 case 16:
3151 case 15:
3152 i -= 8;
3153 addr_nop_8();
3154 break;
3155 case 14:
3156 case 13:
3157 i -= 7;
3158 addr_nop_7();
3159 break;
3160 case 12:
3161 i -= 6;
3162 emit_int8(0x66); // size prefix
3163 addr_nop_5();
3164 break;
3165 default:
3166 assert(i < 12, " ");
3167 }
3168
3169 // Generate second nop for size between 11-1
3170 switch (i) {
3171 case 11:
3172 emit_int8(0x66); // size prefix
3173 case 10:
3174 emit_int8(0x66); // size prefix
3175 case 9:
3176 emit_int8(0x66); // size prefix
3177 case 8:
3178 addr_nop_8();
3179 break;
3180 case 7:
3181 addr_nop_7();
3182 break;
3183 case 6:
3184 emit_int8(0x66); // size prefix
3185 case 5:
3186 addr_nop_5();
3187 break;
3188 case 4:
3189 addr_nop_4();
3190 break;
3191 case 3:
3192 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3193 emit_int8(0x66); // size prefix
3194 case 2:
3195 emit_int8(0x66); // size prefix
3196 case 1:
3197 emit_int8((unsigned char)0x90);
3198 // nop
3199 break;
3200 default:
3201 assert(i == 0, " ");
3202 }
3203 return;
3204 }
3205
3206 if (UseAddressNop && VM_Version::is_zx()) {
3207 //
3208 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3209 // 1: 0x90
3210 // 2: 0x66 0x90
3211 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3212 // 4: 0x0F 0x1F 0x40 0x00
3213 // 5: 0x0F 0x1F 0x44 0x00 0x00
3214 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3215 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3216 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3217 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3218 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3219 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3220
3221 // The rest coding is ZX specific - don't use consecutive address nops
3222
3223 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3224 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3225 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3226 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3227
3228 while (i >= 15) {
3229 // For ZX don't generate consecutive addess nops (mix with regular nops)
3230 i -= 15;
3231 emit_int8(0x66); // size prefix
3232 emit_int8(0x66); // size prefix
3233 emit_int8(0x66); // size prefix
3234 addr_nop_8();
3235 emit_int8(0x66); // size prefix
3236 emit_int8(0x66); // size prefix
3237 emit_int8(0x66); // size prefix
3238 emit_int8((unsigned char)0x90);
3239 // nop
3240 }
3241 switch (i) {
3242 case 14:
3243 emit_int8(0x66); // size prefix
3244 case 13:
3245 emit_int8(0x66); // size prefix
3246 case 12:
3247 addr_nop_8();
3248 emit_int8(0x66); // size prefix
3249 emit_int8(0x66); // size prefix
3250 emit_int8(0x66); // size prefix
3251 emit_int8((unsigned char)0x90);
3252 // nop
3253 break;
3254 case 11:
3255 emit_int8(0x66); // size prefix
3256 case 10:
3257 emit_int8(0x66); // size prefix
3258 case 9:
3259 emit_int8(0x66); // size prefix
3260 case 8:
3261 addr_nop_8();
3262 break;
3263 case 7:
3264 addr_nop_7();
3265 break;
3266 case 6:
3267 emit_int8(0x66); // size prefix
3268 case 5:
3269 addr_nop_5();
3270 break;
3271 case 4:
3272 addr_nop_4();
3273 break;
3274 case 3:
3275 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3276 emit_int8(0x66); // size prefix
3277 case 2:
3278 emit_int8(0x66); // size prefix
3279 case 1:
3280 emit_int8((unsigned char)0x90);
3281 // nop
3282 break;
3283 default:
3284 assert(i == 0, " ");
3285 }
3286 return;
3287 }
3288
3289 // Using nops with size prefixes "0x66 0x90".
3290 // From AMD Optimization Guide:
3291 // 1: 0x90
3292 // 2: 0x66 0x90
3293 // 3: 0x66 0x66 0x90
3294 // 4: 0x66 0x66 0x66 0x90
3295 // 5: 0x66 0x66 0x90 0x66 0x90
3296 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3297 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3298 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3299 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3300 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3301 //
3302 while(i > 12) {
3303 i -= 4;
3304 emit_int8(0x66); // size prefix
3305 emit_int8(0x66);
3306 emit_int8(0x66);
3307 emit_int8((unsigned char)0x90);
3308 // nop
3309 }
3310 // 1 - 12 nops
3311 if(i > 8) {
3312 if(i > 9) {
3313 i -= 1;
3314 emit_int8(0x66);
3315 }
3316 i -= 3;
3317 emit_int8(0x66);
3318 emit_int8(0x66);
3319 emit_int8((unsigned char)0x90);
3320 }
3321 // 1 - 8 nops
3322 if(i > 4) {
3323 if(i > 6) {
3324 i -= 1;
3325 emit_int8(0x66);
3326 }
3327 i -= 3;
3328 emit_int8(0x66);
3329 emit_int8(0x66);
3330 emit_int8((unsigned char)0x90);
3331 }
3332 switch (i) {
3333 case 4:
3334 emit_int8(0x66);
3335 case 3:
3336 emit_int8(0x66);
3337 case 2:
3338 emit_int8(0x66);
3339 case 1:
3340 emit_int8((unsigned char)0x90);
3341 break;
3342 default:
3343 assert(i == 0, " ");
3344 }
3345 }
3346
3347 void Assembler::notl(Register dst) {
3348 int encode = prefix_and_encode(dst->encoding());
3349 emit_int8((unsigned char)0xF7);
3350 emit_int8((unsigned char)(0xD0 | encode));
3351 }
3352
3353 void Assembler::btsl(Address dst, Register idx) {
3354 InstructionMark im(this);
3355
3356 prefix(dst, idx);
3357 emit_int8(0x0F);
3358 emit_int8(0xAB);
3359 emit_operand(idx, dst);
3360 }
3361
3362 void Assembler::btrl(Address dst, Register idx) {
3363 InstructionMark im(this);
3364
3365 prefix(dst, idx);
3366 emit_int8(0x0F);
3367 emit_int8(0xB3);
3368 emit_operand(idx, dst);
3369 }
3370
3371 void Assembler::orl(Address dst, int32_t imm32) {
3372 InstructionMark im(this);
3373 prefix(dst);
3374 emit_arith_operand(0x81, rcx, dst, imm32);
3375 }
3376
3377 void Assembler::orl(Register dst, int32_t imm32) {
3378 prefix(dst);
3379 emit_arith(0x81, 0xC8, dst, imm32);
3380 }
3381
3382 void Assembler::orl(Register dst, Address src) {
3383 InstructionMark im(this);
3384 prefix(src, dst);
3385 emit_int8(0x0B);
3386 emit_operand(dst, src);
3387 }
3388
3389 void Assembler::orl(Register dst, Register src) {
3390 (void) prefix_and_encode(dst->encoding(), src->encoding());
3391 emit_arith(0x0B, 0xC0, dst, src);
3392 }
3393
3394 void Assembler::orl(Address dst, Register src) {
3395 InstructionMark im(this);
3396 prefix(dst, src);
3397 emit_int8(0x09);
3398 emit_operand(src, dst);
3399 }
3400
3401 void Assembler::orb(Address dst, int imm8) {
3402 InstructionMark im(this);
3403 prefix(dst);
3404 emit_int8((unsigned char)0x80);
3405 emit_operand(rcx, dst, 1);
3406 emit_int8(imm8);
3407 }
3408
3409 void Assembler::packuswb(XMMRegister dst, Address src) {
3410 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3411 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3412 InstructionMark im(this);
3413 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3414 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3415 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3416 emit_int8(0x67);
3417 emit_operand(dst, src);
3418 }
3419
3420 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3422 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3423 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3424 emit_int8(0x67);
3425 emit_int8((unsigned char)(0xC0 | encode));
3426 }
3427
3428 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3429 assert(UseAVX > 0, "some form of AVX must be enabled");
3430 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3431 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3432 emit_int8(0x67);
3433 emit_int8((unsigned char)(0xC0 | encode));
3434 }
3435
3436 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3437 assert(VM_Version::supports_avx2(), "");
3438 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3439 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3440 emit_int8(0x00);
3441 emit_int8(0xC0 | encode);
3442 emit_int8(imm8);
3443 }
3444
3445 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3446 assert(VM_Version::supports_avx2(), "");
3447 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3448 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3449 emit_int8(0x46);
3450 emit_int8(0xC0 | encode);
3451 emit_int8(imm8);
3452 }
3453
3454 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3455 assert(VM_Version::supports_avx(), "");
3456 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3457 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3458 emit_int8(0x06);
3459 emit_int8(0xC0 | encode);
3460 emit_int8(imm8);
3461 }
3462
3463 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3464 assert(VM_Version::supports_evex(), "");
3465 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3466 attributes.set_is_evex_instruction();
3467 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3468 emit_int8(0x76);
3469 emit_int8((unsigned char)(0xC0 | encode));
3470 }
3471
3472
3473 void Assembler::pause() {
3474 emit_int8((unsigned char)0xF3);
3475 emit_int8((unsigned char)0x90);
3476 }
3477
3478 void Assembler::ud2() {
3479 emit_int8(0x0F);
3480 emit_int8(0x0B);
3481 }
3482
3483 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3484 assert(VM_Version::supports_sse4_2(), "");
3485 InstructionMark im(this);
3486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3487 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3488 emit_int8(0x61);
3489 emit_operand(dst, src);
3490 emit_int8(imm8);
3491 }
3492
3493 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3494 assert(VM_Version::supports_sse4_2(), "");
3495 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3496 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3497 emit_int8(0x61);
3498 emit_int8((unsigned char)(0xC0 | encode));
3499 emit_int8(imm8);
3500 }
3501
3502 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3503 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3504 assert(VM_Version::supports_sse2(), "");
3505 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3506 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3507 emit_int8(0x74);
3508 emit_int8((unsigned char)(0xC0 | encode));
3509 }
3510
3511 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3512 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3513 assert(VM_Version::supports_avx(), "");
3514 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3515 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3516 emit_int8(0x74);
3517 emit_int8((unsigned char)(0xC0 | encode));
3518 }
3519
3520 // In this context, kdst is written the mask used to process the equal components
3521 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3522 assert(VM_Version::supports_avx512bw(), "");
3523 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3524 attributes.set_is_evex_instruction();
3525 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3526 emit_int8(0x74);
3527 emit_int8((unsigned char)(0xC0 | encode));
3528 }
3529
3530 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3531 assert(VM_Version::supports_avx512vlbw(), "");
3532 InstructionMark im(this);
3533 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3534 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3535 attributes.set_is_evex_instruction();
3536 int dst_enc = kdst->encoding();
3537 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3538 emit_int8(0x64);
3539 emit_operand(as_Register(dst_enc), src);
3540 }
3541
3542 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3543 assert(is_vector_masking(), "");
3544 assert(VM_Version::supports_avx512vlbw(), "");
3545 InstructionMark im(this);
3546 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3547 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3548 attributes.reset_is_clear_context();
3549 attributes.set_embedded_opmask_register_specifier(mask);
3550 attributes.set_is_evex_instruction();
3551 int dst_enc = kdst->encoding();
3552 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3553 emit_int8(0x64);
3554 emit_operand(as_Register(dst_enc), src);
3555 }
3556
3557 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3558 assert(VM_Version::supports_avx512vlbw(), "");
3559 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3560 attributes.set_is_evex_instruction();
3561 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3562 emit_int8(0x3E);
3563 emit_int8((unsigned char)(0xC0 | encode));
3564 emit_int8(vcc);
3565 }
3566
3567 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3568 assert(is_vector_masking(), "");
3569 assert(VM_Version::supports_avx512vlbw(), "");
3570 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3571 attributes.reset_is_clear_context();
3572 attributes.set_embedded_opmask_register_specifier(mask);
3573 attributes.set_is_evex_instruction();
3574 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3575 emit_int8(0x3E);
3576 emit_int8((unsigned char)(0xC0 | encode));
3577 emit_int8(vcc);
3578 }
3579
3580 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3581 assert(VM_Version::supports_avx512vlbw(), "");
3582 InstructionMark im(this);
3583 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3584 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3585 attributes.set_is_evex_instruction();
3586 int dst_enc = kdst->encoding();
3587 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3588 emit_int8(0x3E);
3589 emit_operand(as_Register(dst_enc), src);
3590 emit_int8(vcc);
3591 }
3592
3593 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3594 assert(VM_Version::supports_avx512bw(), "");
3595 InstructionMark im(this);
3596 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3597 attributes.set_is_evex_instruction();
3598 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3599 int dst_enc = kdst->encoding();
3600 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3601 emit_int8(0x74);
3602 emit_operand(as_Register(dst_enc), src);
3603 }
3604
3605 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3606 assert(VM_Version::supports_avx512vlbw(), "");
3607 assert(is_vector_masking(), ""); // For stub code use only
3608 InstructionMark im(this);
3609 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3610 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3611 attributes.reset_is_clear_context();
3612 attributes.set_embedded_opmask_register_specifier(mask);
3613 attributes.set_is_evex_instruction();
3614 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3615 emit_int8(0x74);
3616 emit_operand(as_Register(kdst->encoding()), src);
3617 }
3618
3619 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3620 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3621 assert(VM_Version::supports_sse2(), "");
3622 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3623 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3624 emit_int8(0x75);
3625 emit_int8((unsigned char)(0xC0 | encode));
3626 }
3627
3628 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3629 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3630 assert(VM_Version::supports_avx(), "");
3631 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3632 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3633 emit_int8(0x75);
3634 emit_int8((unsigned char)(0xC0 | encode));
3635 }
3636
3637 // In this context, kdst is written the mask used to process the equal components
3638 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3639 assert(VM_Version::supports_avx512bw(), "");
3640 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3641 attributes.set_is_evex_instruction();
3642 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3643 emit_int8(0x75);
3644 emit_int8((unsigned char)(0xC0 | encode));
3645 }
3646
3647 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3648 assert(VM_Version::supports_avx512bw(), "");
3649 InstructionMark im(this);
3650 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3651 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3652 attributes.set_is_evex_instruction();
3653 int dst_enc = kdst->encoding();
3654 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3655 emit_int8(0x75);
3656 emit_operand(as_Register(dst_enc), src);
3657 }
3658
3659 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3660 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3661 assert(VM_Version::supports_sse2(), "");
3662 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3663 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3664 emit_int8(0x76);
3665 emit_int8((unsigned char)(0xC0 | encode));
3666 }
3667
3668 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3669 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3670 assert(VM_Version::supports_avx(), "");
3671 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3673 emit_int8(0x76);
3674 emit_int8((unsigned char)(0xC0 | encode));
3675 }
3676
3677 // In this context, kdst is written the mask used to process the equal components
3678 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3679 assert(VM_Version::supports_evex(), "");
3680 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3681 attributes.set_is_evex_instruction();
3682 attributes.reset_is_clear_context();
3683 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3684 emit_int8(0x76);
3685 emit_int8((unsigned char)(0xC0 | encode));
3686 }
3687
3688 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3689 assert(VM_Version::supports_evex(), "");
3690 InstructionMark im(this);
3691 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3692 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3693 attributes.reset_is_clear_context();
3694 attributes.set_is_evex_instruction();
3695 int dst_enc = kdst->encoding();
3696 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3697 emit_int8(0x76);
3698 emit_operand(as_Register(dst_enc), src);
3699 }
3700
3701 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3702 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3703 assert(VM_Version::supports_sse4_1(), "");
3704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3706 emit_int8(0x29);
3707 emit_int8((unsigned char)(0xC0 | encode));
3708 }
3709
3710 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3711 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3712 assert(VM_Version::supports_avx(), "");
3713 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3714 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3715 emit_int8(0x29);
3716 emit_int8((unsigned char)(0xC0 | encode));
3717 }
3718
3719 // In this context, kdst is written the mask used to process the equal components
3720 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3721 assert(VM_Version::supports_evex(), "");
3722 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3723 attributes.reset_is_clear_context();
3724 attributes.set_is_evex_instruction();
3725 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3726 emit_int8(0x29);
3727 emit_int8((unsigned char)(0xC0 | encode));
3728 }
3729
3730 // In this context, kdst is written the mask used to process the equal components
3731 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3732 assert(VM_Version::supports_evex(), "");
3733 InstructionMark im(this);
3734 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3735 attributes.reset_is_clear_context();
3736 attributes.set_is_evex_instruction();
3737 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3738 int dst_enc = kdst->encoding();
3739 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3740 emit_int8(0x29);
3741 emit_operand(as_Register(dst_enc), src);
3742 }
3743
3744 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3745 assert(VM_Version::supports_sse2(), "");
3746 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3747 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3748 emit_int8((unsigned char)0xD7);
3749 emit_int8((unsigned char)(0xC0 | encode));
3750 }
3751
3752 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3753 assert(VM_Version::supports_avx2(), "");
3754 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3755 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3756 emit_int8((unsigned char)0xD7);
3757 emit_int8((unsigned char)(0xC0 | encode));
3758 }
3759
3760 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3761 assert(VM_Version::supports_sse4_1(), "");
3762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3763 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3764 emit_int8(0x16);
3765 emit_int8((unsigned char)(0xC0 | encode));
3766 emit_int8(imm8);
3767 }
3768
3769 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3770 assert(VM_Version::supports_sse4_1(), "");
3771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3772 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3773 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3774 emit_int8(0x16);
3775 emit_operand(src, dst);
3776 emit_int8(imm8);
3777 }
3778
3779 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3780 assert(VM_Version::supports_sse4_1(), "");
3781 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3782 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3783 emit_int8(0x16);
3784 emit_int8((unsigned char)(0xC0 | encode));
3785 emit_int8(imm8);
3786 }
3787
3788 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3789 assert(VM_Version::supports_sse4_1(), "");
3790 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3791 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3792 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3793 emit_int8(0x16);
3794 emit_operand(src, dst);
3795 emit_int8(imm8);
3796 }
3797
3798 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3799 assert(VM_Version::supports_sse2(), "");
3800 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3801 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3802 emit_int8((unsigned char)0xC5);
3803 emit_int8((unsigned char)(0xC0 | encode));
3804 emit_int8(imm8);
3805 }
3806
3807 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3808 assert(VM_Version::supports_sse4_1(), "");
3809 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3810 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3811 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3812 emit_int8((unsigned char)0x15);
3813 emit_operand(src, dst);
3814 emit_int8(imm8);
3815 }
3816
3817 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3818 assert(VM_Version::supports_sse4_1(), "");
3819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3820 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3821 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3822 emit_int8(0x14);
3823 emit_operand(src, dst);
3824 emit_int8(imm8);
3825 }
3826
3827 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3828 assert(VM_Version::supports_sse4_1(), "");
3829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3830 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3831 emit_int8(0x22);
3832 emit_int8((unsigned char)(0xC0 | encode));
3833 emit_int8(imm8);
3834 }
3835
3836 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3837 assert(VM_Version::supports_sse4_1(), "");
3838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3840 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3841 emit_int8(0x22);
3842 emit_operand(dst,src);
3843 emit_int8(imm8);
3844 }
3845
3846 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3847 assert(VM_Version::supports_sse4_1(), "");
3848 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3849 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3850 emit_int8(0x22);
3851 emit_int8((unsigned char)(0xC0 | encode));
3852 emit_int8(imm8);
3853 }
3854
3855 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3856 assert(VM_Version::supports_sse4_1(), "");
3857 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3859 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3860 emit_int8(0x22);
3861 emit_operand(dst, src);
3862 emit_int8(imm8);
3863 }
3864
3865 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3866 assert(VM_Version::supports_sse2(), "");
3867 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3868 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3869 emit_int8((unsigned char)0xC4);
3870 emit_int8((unsigned char)(0xC0 | encode));
3871 emit_int8(imm8);
3872 }
3873
3874 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3875 assert(VM_Version::supports_sse2(), "");
3876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3877 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3878 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3879 emit_int8((unsigned char)0xC4);
3880 emit_operand(dst, src);
3881 emit_int8(imm8);
3882 }
3883
3884 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3885 assert(VM_Version::supports_sse4_1(), "");
3886 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3887 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3888 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3889 emit_int8(0x20);
3890 emit_operand(dst, src);
3891 emit_int8(imm8);
3892 }
3893
3894 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3895 assert(VM_Version::supports_sse4_1(), "");
3896 InstructionMark im(this);
3897 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3898 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3899 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3900 emit_int8(0x30);
3901 emit_operand(dst, src);
3902 }
3903
3904 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3905 assert(VM_Version::supports_sse4_1(), "");
3906 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3907 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3908 emit_int8(0x30);
3909 emit_int8((unsigned char)(0xC0 | encode));
3910 }
3911
3912 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3913 assert(VM_Version::supports_avx(), "");
3914 InstructionMark im(this);
3915 assert(dst != xnoreg, "sanity");
3916 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3917 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3918 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3919 emit_int8(0x30);
3920 emit_operand(dst, src);
3921 }
3922
3923 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
3924 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3925 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3926 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
3927 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3928 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3929 emit_int8(0x30);
3930 emit_int8((unsigned char) (0xC0 | encode));
3931 }
3932
3933
3934 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
3935 assert(is_vector_masking(), "");
3936 assert(VM_Version::supports_avx512vlbw(), "");
3937 assert(dst != xnoreg, "sanity");
3938 InstructionMark im(this);
3939 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3940 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3941 attributes.set_embedded_opmask_register_specifier(mask);
3942 attributes.set_is_evex_instruction();
3943 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3944 emit_int8(0x30);
3945 emit_operand(dst, src);
3946 }
3947 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
3948 assert(VM_Version::supports_avx512vlbw(), "");
3949 assert(src != xnoreg, "sanity");
3950 InstructionMark im(this);
3951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3952 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3953 attributes.set_is_evex_instruction();
3954 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3955 emit_int8(0x30);
3956 emit_operand(src, dst);
3957 }
3958
3959 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
3960 assert(is_vector_masking(), "");
3961 assert(VM_Version::supports_avx512vlbw(), "");
3962 assert(src != xnoreg, "sanity");
3963 InstructionMark im(this);
3964 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3965 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3966 attributes.reset_is_clear_context();
3967 attributes.set_embedded_opmask_register_specifier(mask);
3968 attributes.set_is_evex_instruction();
3969 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3970 emit_int8(0x30);
3971 emit_operand(src, dst);
3972 }
3973
3974 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
3975 assert(VM_Version::supports_evex(), "");
3976 assert(src != xnoreg, "sanity");
3977 InstructionMark im(this);
3978 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3979 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
3980 attributes.set_is_evex_instruction();
3981 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
3982 emit_int8(0x31);
3983 emit_operand(src, dst);
3984 }
3985
3986 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
3987 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
3988 vector_len == AVX_256bit? VM_Version::supports_avx2() :
3989 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
3990 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3991 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3992 emit_int8(0x33);
3993 emit_int8((unsigned char)(0xC0 | encode));
3994 }
3995
3996 // generic
3997 void Assembler::pop(Register dst) {
3998 int encode = prefix_and_encode(dst->encoding());
3999 emit_int8(0x58 | encode);
4000 }
4001
4002 void Assembler::popcntl(Register dst, Address src) {
4003 assert(VM_Version::supports_popcnt(), "must support");
4004 InstructionMark im(this);
4005 emit_int8((unsigned char)0xF3);
4006 prefix(src, dst);
4007 emit_int8(0x0F);
4008 emit_int8((unsigned char)0xB8);
4009 emit_operand(dst, src);
4010 }
4011
4012 void Assembler::popcntl(Register dst, Register src) {
4013 assert(VM_Version::supports_popcnt(), "must support");
4014 emit_int8((unsigned char)0xF3);
4015 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4016 emit_int8(0x0F);
4017 emit_int8((unsigned char)0xB8);
4018 emit_int8((unsigned char)(0xC0 | encode));
4019 }
4020
4021 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4022 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4023 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4024 attributes.set_is_evex_instruction();
4025 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4026 emit_int8(0x55);
4027 emit_int8((unsigned char)(0xC0 | encode));
4028 }
4029
4030 void Assembler::popf() {
4031 emit_int8((unsigned char)0x9D);
4032 }
4033
4034 #ifndef _LP64 // no 32bit push/pop on amd64
4035 void Assembler::popl(Address dst) {
4036 // NOTE: this will adjust stack by 8byte on 64bits
4037 InstructionMark im(this);
4038 prefix(dst);
4039 emit_int8((unsigned char)0x8F);
4040 emit_operand(rax, dst);
4041 }
4042 #endif
4043
4044 void Assembler::prefetch_prefix(Address src) {
4045 prefix(src);
4046 emit_int8(0x0F);
4047 }
4048
4049 void Assembler::prefetchnta(Address src) {
4050 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4051 InstructionMark im(this);
4052 prefetch_prefix(src);
4053 emit_int8(0x18);
4054 emit_operand(rax, src); // 0, src
4055 }
4056
4057 void Assembler::prefetchr(Address src) {
4058 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4059 InstructionMark im(this);
4060 prefetch_prefix(src);
4061 emit_int8(0x0D);
4062 emit_operand(rax, src); // 0, src
4063 }
4064
4065 void Assembler::prefetcht0(Address src) {
4066 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4067 InstructionMark im(this);
4068 prefetch_prefix(src);
4069 emit_int8(0x18);
4070 emit_operand(rcx, src); // 1, src
4071 }
4072
4073 void Assembler::prefetcht1(Address src) {
4074 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4075 InstructionMark im(this);
4076 prefetch_prefix(src);
4077 emit_int8(0x18);
4078 emit_operand(rdx, src); // 2, src
4079 }
4080
4081 void Assembler::prefetcht2(Address src) {
4082 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4083 InstructionMark im(this);
4084 prefetch_prefix(src);
4085 emit_int8(0x18);
4086 emit_operand(rbx, src); // 3, src
4087 }
4088
4089 void Assembler::prefetchw(Address src) {
4090 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4091 InstructionMark im(this);
4092 prefetch_prefix(src);
4093 emit_int8(0x0D);
4094 emit_operand(rcx, src); // 1, src
4095 }
4096
4097 void Assembler::prefix(Prefix p) {
4098 emit_int8(p);
4099 }
4100
4101 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4102 assert(VM_Version::supports_ssse3(), "");
4103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4104 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4105 emit_int8(0x00);
4106 emit_int8((unsigned char)(0xC0 | encode));
4107 }
4108
4109 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4110 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4111 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4112 0, "");
4113 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4114 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4115 emit_int8(0x00);
4116 emit_int8((unsigned char)(0xC0 | encode));
4117 }
4118
4119 void Assembler::pshufb(XMMRegister dst, Address src) {
4120 assert(VM_Version::supports_ssse3(), "");
4121 InstructionMark im(this);
4122 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4123 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4124 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4125 emit_int8(0x00);
4126 emit_operand(dst, src);
4127 }
4128
4129 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4130 assert(isByte(mode), "invalid value");
4131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4132 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4133 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4135 emit_int8(0x70);
4136 emit_int8((unsigned char)(0xC0 | encode));
4137 emit_int8(mode & 0xFF);
4138 }
4139
4140 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4141 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4142 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4143 0, "");
4144 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4145 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4146 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4147 emit_int8(0x70);
4148 emit_int8((unsigned char)(0xC0 | encode));
4149 emit_int8(mode & 0xFF);
4150 }
4151
4152 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4153 assert(isByte(mode), "invalid value");
4154 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4155 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4156 InstructionMark im(this);
4157 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4158 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4159 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4160 emit_int8(0x70);
4161 emit_operand(dst, src);
4162 emit_int8(mode & 0xFF);
4163 }
4164
4165 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4166 assert(isByte(mode), "invalid value");
4167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4168 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4169 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4170 emit_int8(0x70);
4171 emit_int8((unsigned char)(0xC0 | encode));
4172 emit_int8(mode & 0xFF);
4173 }
4174
4175 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4176 assert(isByte(mode), "invalid value");
4177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4178 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4179 InstructionMark im(this);
4180 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4181 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4182 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4183 emit_int8(0x70);
4184 emit_operand(dst, src);
4185 emit_int8(mode & 0xFF);
4186 }
4187 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4188 assert(VM_Version::supports_evex(), "requires EVEX support");
4189 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
4190 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4191 attributes.set_is_evex_instruction();
4192 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4193 emit_int8(0x43);
4194 emit_int8((unsigned char)(0xC0 | encode));
4195 emit_int8(imm8 & 0xFF);
4196 }
4197
4198 void Assembler::psrldq(XMMRegister dst, int shift) {
4199 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4202 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4203 emit_int8(0x73);
4204 emit_int8((unsigned char)(0xC0 | encode));
4205 emit_int8(shift);
4206 }
4207
4208 void Assembler::pslldq(XMMRegister dst, int shift) {
4209 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4210 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4211 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4212 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4213 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4214 emit_int8(0x73);
4215 emit_int8((unsigned char)(0xC0 | encode));
4216 emit_int8(shift);
4217 }
4218
4219 void Assembler::ptest(XMMRegister dst, Address src) {
4220 assert(VM_Version::supports_sse4_1(), "");
4221 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4222 InstructionMark im(this);
4223 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4224 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4225 emit_int8(0x17);
4226 emit_operand(dst, src);
4227 }
4228
4229 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4230 assert(VM_Version::supports_sse4_1(), "");
4231 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4232 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4233 emit_int8(0x17);
4234 emit_int8((unsigned char)(0xC0 | encode));
4235 }
4236
4237 void Assembler::vptest(XMMRegister dst, Address src) {
4238 assert(VM_Version::supports_avx(), "");
4239 InstructionMark im(this);
4240 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4241 assert(dst != xnoreg, "sanity");
4242 // swap src<->dst for encoding
4243 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4244 emit_int8(0x17);
4245 emit_operand(dst, src);
4246 }
4247
4248 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4249 assert(VM_Version::supports_avx(), "");
4250 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4251 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4252 emit_int8(0x17);
4253 emit_int8((unsigned char)(0xC0 | encode));
4254 }
4255
4256 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4257 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4258 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4259 InstructionMark im(this);
4260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4261 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4262 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4263 emit_int8(0x60);
4264 emit_operand(dst, src);
4265 }
4266
4267 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4271 emit_int8(0x60);
4272 emit_int8((unsigned char)(0xC0 | encode));
4273 }
4274
4275 void Assembler::punpckldq(XMMRegister dst, Address src) {
4276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4277 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4278 InstructionMark im(this);
4279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4280 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4281 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4282 emit_int8(0x62);
4283 emit_operand(dst, src);
4284 }
4285
4286 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4287 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4289 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4290 emit_int8(0x62);
4291 emit_int8((unsigned char)(0xC0 | encode));
4292 }
4293
4294 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4295 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4296 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4297 attributes.set_rex_vex_w_reverted();
4298 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4299 emit_int8(0x6C);
4300 emit_int8((unsigned char)(0xC0 | encode));
4301 }
4302
4303 void Assembler::push(int32_t imm32) {
4304 // in 64bits we push 64bits onto the stack but only
4305 // take a 32bit immediate
4306 emit_int8(0x68);
4307 emit_int32(imm32);
4308 }
4309
4310 void Assembler::push(Register src) {
4311 int encode = prefix_and_encode(src->encoding());
4312
4313 emit_int8(0x50 | encode);
4314 }
4315
4316 void Assembler::pushf() {
4317 emit_int8((unsigned char)0x9C);
4318 }
4319
4320 #ifndef _LP64 // no 32bit push/pop on amd64
4321 void Assembler::pushl(Address src) {
4322 // Note this will push 64bit on 64bit
4323 InstructionMark im(this);
4324 prefix(src);
4325 emit_int8((unsigned char)0xFF);
4326 emit_operand(rsi, src);
4327 }
4328 #endif
4329
4330 void Assembler::rcll(Register dst, int imm8) {
4331 assert(isShiftCount(imm8), "illegal shift count");
4332 int encode = prefix_and_encode(dst->encoding());
4333 if (imm8 == 1) {
4334 emit_int8((unsigned char)0xD1);
4335 emit_int8((unsigned char)(0xD0 | encode));
4336 } else {
4337 emit_int8((unsigned char)0xC1);
4338 emit_int8((unsigned char)0xD0 | encode);
4339 emit_int8(imm8);
4340 }
4341 }
4342
4343 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4344 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4345 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4346 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4347 emit_int8(0x53);
4348 emit_int8((unsigned char)(0xC0 | encode));
4349 }
4350
4351 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4352 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4354 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4355 emit_int8(0x53);
4356 emit_int8((unsigned char)(0xC0 | encode));
4357 }
4358
4359 void Assembler::rdtsc() {
4360 emit_int8((unsigned char)0x0F);
4361 emit_int8((unsigned char)0x31);
4362 }
4363
4364 // copies data from [esi] to [edi] using rcx pointer sized words
4365 // generic
4366 void Assembler::rep_mov() {
4367 emit_int8((unsigned char)0xF3);
4368 // MOVSQ
4369 LP64_ONLY(prefix(REX_W));
4370 emit_int8((unsigned char)0xA5);
4371 }
4372
4373 // sets rcx bytes with rax, value at [edi]
4374 void Assembler::rep_stosb() {
4375 emit_int8((unsigned char)0xF3); // REP
4376 LP64_ONLY(prefix(REX_W));
4377 emit_int8((unsigned char)0xAA); // STOSB
4378 }
4379
4380 // sets rcx pointer sized words with rax, value at [edi]
4381 // generic
4382 void Assembler::rep_stos() {
4383 emit_int8((unsigned char)0xF3); // REP
4384 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4385 emit_int8((unsigned char)0xAB);
4386 }
4387
4388 // scans rcx pointer sized words at [edi] for occurance of rax,
4389 // generic
4390 void Assembler::repne_scan() { // repne_scan
4391 emit_int8((unsigned char)0xF2);
4392 // SCASQ
4393 LP64_ONLY(prefix(REX_W));
4394 emit_int8((unsigned char)0xAF);
4395 }
4396
4397 #ifdef _LP64
4398 // scans rcx 4 byte words at [edi] for occurance of rax,
4399 // generic
4400 void Assembler::repne_scanl() { // repne_scan
4401 emit_int8((unsigned char)0xF2);
4402 // SCASL
4403 emit_int8((unsigned char)0xAF);
4404 }
4405 #endif
4406
4407 void Assembler::ret(int imm16) {
4408 if (imm16 == 0) {
4409 emit_int8((unsigned char)0xC3);
4410 } else {
4411 emit_int8((unsigned char)0xC2);
4412 emit_int16(imm16);
4413 }
4414 }
4415
4416 void Assembler::sahf() {
4417 #ifdef _LP64
4418 // Not supported in 64bit mode
4419 ShouldNotReachHere();
4420 #endif
4421 emit_int8((unsigned char)0x9E);
4422 }
4423
4424 void Assembler::sarl(Register dst, int imm8) {
4425 int encode = prefix_and_encode(dst->encoding());
4426 assert(isShiftCount(imm8), "illegal shift count");
4427 if (imm8 == 1) {
4428 emit_int8((unsigned char)0xD1);
4429 emit_int8((unsigned char)(0xF8 | encode));
4430 } else {
4431 emit_int8((unsigned char)0xC1);
4432 emit_int8((unsigned char)(0xF8 | encode));
4433 emit_int8(imm8);
4434 }
4435 }
4436
4437 void Assembler::sarl(Register dst) {
4438 int encode = prefix_and_encode(dst->encoding());
4439 emit_int8((unsigned char)0xD3);
4440 emit_int8((unsigned char)(0xF8 | encode));
4441 }
4442
4443 void Assembler::sbbl(Address dst, int32_t imm32) {
4444 InstructionMark im(this);
4445 prefix(dst);
4446 emit_arith_operand(0x81, rbx, dst, imm32);
4447 }
4448
4449 void Assembler::sbbl(Register dst, int32_t imm32) {
4450 prefix(dst);
4451 emit_arith(0x81, 0xD8, dst, imm32);
4452 }
4453
4454
4455 void Assembler::sbbl(Register dst, Address src) {
4456 InstructionMark im(this);
4457 prefix(src, dst);
4458 emit_int8(0x1B);
4459 emit_operand(dst, src);
4460 }
4461
4462 void Assembler::sbbl(Register dst, Register src) {
4463 (void) prefix_and_encode(dst->encoding(), src->encoding());
4464 emit_arith(0x1B, 0xC0, dst, src);
4465 }
4466
4467 void Assembler::setb(Condition cc, Register dst) {
4468 assert(0 <= cc && cc < 16, "illegal cc");
4469 int encode = prefix_and_encode(dst->encoding(), true);
4470 emit_int8(0x0F);
4471 emit_int8((unsigned char)0x90 | cc);
4472 emit_int8((unsigned char)(0xC0 | encode));
4473 }
4474
4475 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4476 assert(VM_Version::supports_ssse3(), "");
4477 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4478 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4479 emit_int8((unsigned char)0x0F);
4480 emit_int8((unsigned char)(0xC0 | encode));
4481 emit_int8(imm8);
4482 }
4483
4484 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4485 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4486 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4487 0, "");
4488 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4489 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4490 emit_int8((unsigned char)0x0F);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 emit_int8(imm8);
4493 }
4494
4495 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
4496 assert(VM_Version::supports_evex(), "");
4497 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4498 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4499 emit_int8(0x3);
4500 emit_int8((unsigned char)(0xC0 | encode));
4501 emit_int8(imm8);
4502 }
4503
4504 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4505 assert(VM_Version::supports_sse4_1(), "");
4506 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4507 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4508 emit_int8((unsigned char)0x0E);
4509 emit_int8((unsigned char)(0xC0 | encode));
4510 emit_int8(imm8);
4511 }
4512
4513 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4514 assert(VM_Version::supports_sha(), "");
4515 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4516 emit_int8((unsigned char)0xCC);
4517 emit_int8((unsigned char)(0xC0 | encode));
4518 emit_int8((unsigned char)imm8);
4519 }
4520
4521 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4522 assert(VM_Version::supports_sha(), "");
4523 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4524 emit_int8((unsigned char)0xC8);
4525 emit_int8((unsigned char)(0xC0 | encode));
4526 }
4527
4528 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4529 assert(VM_Version::supports_sha(), "");
4530 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4531 emit_int8((unsigned char)0xC9);
4532 emit_int8((unsigned char)(0xC0 | encode));
4533 }
4534
4535 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4536 assert(VM_Version::supports_sha(), "");
4537 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4538 emit_int8((unsigned char)0xCA);
4539 emit_int8((unsigned char)(0xC0 | encode));
4540 }
4541
4542 // xmm0 is implicit additional source to this instruction.
4543 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4544 assert(VM_Version::supports_sha(), "");
4545 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4546 emit_int8((unsigned char)0xCB);
4547 emit_int8((unsigned char)(0xC0 | encode));
4548 }
4549
4550 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4551 assert(VM_Version::supports_sha(), "");
4552 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4553 emit_int8((unsigned char)0xCC);
4554 emit_int8((unsigned char)(0xC0 | encode));
4555 }
4556
4557 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4558 assert(VM_Version::supports_sha(), "");
4559 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4560 emit_int8((unsigned char)0xCD);
4561 emit_int8((unsigned char)(0xC0 | encode));
4562 }
4563
4564
4565 void Assembler::shll(Register dst, int imm8) {
4566 assert(isShiftCount(imm8), "illegal shift count");
4567 int encode = prefix_and_encode(dst->encoding());
4568 if (imm8 == 1 ) {
4569 emit_int8((unsigned char)0xD1);
4570 emit_int8((unsigned char)(0xE0 | encode));
4571 } else {
4572 emit_int8((unsigned char)0xC1);
4573 emit_int8((unsigned char)(0xE0 | encode));
4574 emit_int8(imm8);
4575 }
4576 }
4577
4578 void Assembler::shll(Register dst) {
4579 int encode = prefix_and_encode(dst->encoding());
4580 emit_int8((unsigned char)0xD3);
4581 emit_int8((unsigned char)(0xE0 | encode));
4582 }
4583
4584 void Assembler::shrl(Register dst, int imm8) {
4585 assert(isShiftCount(imm8), "illegal shift count");
4586 int encode = prefix_and_encode(dst->encoding());
4587 emit_int8((unsigned char)0xC1);
4588 emit_int8((unsigned char)(0xE8 | encode));
4589 emit_int8(imm8);
4590 }
4591
4592 void Assembler::shrl(Register dst) {
4593 int encode = prefix_and_encode(dst->encoding());
4594 emit_int8((unsigned char)0xD3);
4595 emit_int8((unsigned char)(0xE8 | encode));
4596 }
4597
4598 // copies a single word from [esi] to [edi]
4599 void Assembler::smovl() {
4600 emit_int8((unsigned char)0xA5);
4601 }
4602
4603 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4605 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4606 attributes.set_rex_vex_w_reverted();
4607 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4608 emit_int8(0x51);
4609 emit_int8((unsigned char)(0xC0 | encode));
4610 }
4611
4612 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4614 InstructionMark im(this);
4615 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4616 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4617 attributes.set_rex_vex_w_reverted();
4618 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4619 emit_int8(0x51);
4620 emit_operand(dst, src);
4621 }
4622
4623 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4624 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4625 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4626 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4627 emit_int8(0x51);
4628 emit_int8((unsigned char)(0xC0 | encode));
4629 }
4630
4631 void Assembler::std() {
4632 emit_int8((unsigned char)0xFD);
4633 }
4634
4635 void Assembler::sqrtss(XMMRegister dst, Address src) {
4636 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4637 InstructionMark im(this);
4638 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4639 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4640 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4641 emit_int8(0x51);
4642 emit_operand(dst, src);
4643 }
4644
4645 void Assembler::stmxcsr( Address dst) {
4646 if (UseAVX > 0 ) {
4647 assert(VM_Version::supports_avx(), "");
4648 InstructionMark im(this);
4649 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4650 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4651 emit_int8((unsigned char)0xAE);
4652 emit_operand(as_Register(3), dst);
4653 } else {
4654 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4655 InstructionMark im(this);
4656 prefix(dst);
4657 emit_int8(0x0F);
4658 emit_int8((unsigned char)0xAE);
4659 emit_operand(as_Register(3), dst);
4660 }
4661 }
4662
4663 void Assembler::subl(Address dst, int32_t imm32) {
4664 InstructionMark im(this);
4665 prefix(dst);
4666 emit_arith_operand(0x81, rbp, dst, imm32);
4667 }
4668
4669 void Assembler::subl(Address dst, Register src) {
4670 InstructionMark im(this);
4671 prefix(dst, src);
4672 emit_int8(0x29);
4673 emit_operand(src, dst);
4674 }
4675
4676 void Assembler::subl(Register dst, int32_t imm32) {
4677 prefix(dst);
4678 emit_arith(0x81, 0xE8, dst, imm32);
4679 }
4680
4681 // Force generation of a 4 byte immediate value even if it fits into 8bit
4682 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4683 prefix(dst);
4684 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4685 }
4686
4687 void Assembler::subl(Register dst, Address src) {
4688 InstructionMark im(this);
4689 prefix(src, dst);
4690 emit_int8(0x2B);
4691 emit_operand(dst, src);
4692 }
4693
4694 void Assembler::subl(Register dst, Register src) {
4695 (void) prefix_and_encode(dst->encoding(), src->encoding());
4696 emit_arith(0x2B, 0xC0, dst, src);
4697 }
4698
4699 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4701 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4702 attributes.set_rex_vex_w_reverted();
4703 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4704 emit_int8(0x5C);
4705 emit_int8((unsigned char)(0xC0 | encode));
4706 }
4707
4708 void Assembler::subsd(XMMRegister dst, Address src) {
4709 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4710 InstructionMark im(this);
4711 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4712 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4713 attributes.set_rex_vex_w_reverted();
4714 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4715 emit_int8(0x5C);
4716 emit_operand(dst, src);
4717 }
4718
4719 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4720 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4721 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4722 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4723 emit_int8(0x5C);
4724 emit_int8((unsigned char)(0xC0 | encode));
4725 }
4726
4727 void Assembler::subss(XMMRegister dst, Address src) {
4728 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4729 InstructionMark im(this);
4730 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4731 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4732 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4733 emit_int8(0x5C);
4734 emit_operand(dst, src);
4735 }
4736
4737 void Assembler::testb(Register dst, int imm8) {
4738 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4739 (void) prefix_and_encode(dst->encoding(), true);
4740 emit_arith_b(0xF6, 0xC0, dst, imm8);
4741 }
4742
4743 void Assembler::testb(Address dst, int imm8) {
4744 InstructionMark im(this);
4745 prefix(dst);
4746 emit_int8((unsigned char)0xF6);
4747 emit_operand(rax, dst, 1);
4748 emit_int8(imm8);
4749 }
4750
4751 void Assembler::testl(Register dst, int32_t imm32) {
4752 // not using emit_arith because test
4753 // doesn't support sign-extension of
4754 // 8bit operands
4755 int encode = dst->encoding();
4756 if (encode == 0) {
4757 emit_int8((unsigned char)0xA9);
4758 } else {
4759 encode = prefix_and_encode(encode);
4760 emit_int8((unsigned char)0xF7);
4761 emit_int8((unsigned char)(0xC0 | encode));
4762 }
4763 emit_int32(imm32);
4764 }
4765
4766 void Assembler::testl(Register dst, Register src) {
4767 (void) prefix_and_encode(dst->encoding(), src->encoding());
4768 emit_arith(0x85, 0xC0, dst, src);
4769 }
4770
4771 void Assembler::testl(Register dst, Address src) {
4772 InstructionMark im(this);
4773 prefix(src, dst);
4774 emit_int8((unsigned char)0x85);
4775 emit_operand(dst, src);
4776 }
4777
4778 void Assembler::tzcntl(Register dst, Register src) {
4779 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4780 emit_int8((unsigned char)0xF3);
4781 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4782 emit_int8(0x0F);
4783 emit_int8((unsigned char)0xBC);
4784 emit_int8((unsigned char)0xC0 | encode);
4785 }
4786
4787 void Assembler::tzcntq(Register dst, Register src) {
4788 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4789 emit_int8((unsigned char)0xF3);
4790 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4791 emit_int8(0x0F);
4792 emit_int8((unsigned char)0xBC);
4793 emit_int8((unsigned char)(0xC0 | encode));
4794 }
4795
4796 void Assembler::ucomisd(XMMRegister dst, Address src) {
4797 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4798 InstructionMark im(this);
4799 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4800 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4801 attributes.set_rex_vex_w_reverted();
4802 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4803 emit_int8(0x2E);
4804 emit_operand(dst, src);
4805 }
4806
4807 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4808 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4809 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4810 attributes.set_rex_vex_w_reverted();
4811 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4812 emit_int8(0x2E);
4813 emit_int8((unsigned char)(0xC0 | encode));
4814 }
4815
4816 void Assembler::ucomiss(XMMRegister dst, Address src) {
4817 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4818 InstructionMark im(this);
4819 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4820 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4821 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4822 emit_int8(0x2E);
4823 emit_operand(dst, src);
4824 }
4825
4826 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4827 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4828 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4829 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4830 emit_int8(0x2E);
4831 emit_int8((unsigned char)(0xC0 | encode));
4832 }
4833
4834 void Assembler::xabort(int8_t imm8) {
4835 emit_int8((unsigned char)0xC6);
4836 emit_int8((unsigned char)0xF8);
4837 emit_int8((unsigned char)(imm8 & 0xFF));
4838 }
4839
4840 void Assembler::xaddb(Address dst, Register src) {
4841 InstructionMark im(this);
4842 prefix(dst, src, true);
4843 emit_int8(0x0F);
4844 emit_int8((unsigned char)0xC0);
4845 emit_operand(src, dst);
4846 }
4847
4848 void Assembler::xaddw(Address dst, Register src) {
4849 InstructionMark im(this);
4850 emit_int8(0x66);
4851 prefix(dst, src);
4852 emit_int8(0x0F);
4853 emit_int8((unsigned char)0xC1);
4854 emit_operand(src, dst);
4855 }
4856
4857 void Assembler::xaddl(Address dst, Register src) {
4858 InstructionMark im(this);
4859 prefix(dst, src);
4860 emit_int8(0x0F);
4861 emit_int8((unsigned char)0xC1);
4862 emit_operand(src, dst);
4863 }
4864
4865 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4866 InstructionMark im(this);
4867 relocate(rtype);
4868 if (abort.is_bound()) {
4869 address entry = target(abort);
4870 assert(entry != NULL, "abort entry NULL");
4871 intptr_t offset = entry - pc();
4872 emit_int8((unsigned char)0xC7);
4873 emit_int8((unsigned char)0xF8);
4874 emit_int32(offset - 6); // 2 opcode + 4 address
4875 } else {
4876 abort.add_patch_at(code(), locator());
4877 emit_int8((unsigned char)0xC7);
4878 emit_int8((unsigned char)0xF8);
4879 emit_int32(0);
4880 }
4881 }
4882
4883 void Assembler::xchgb(Register dst, Address src) { // xchg
4884 InstructionMark im(this);
4885 prefix(src, dst, true);
4886 emit_int8((unsigned char)0x86);
4887 emit_operand(dst, src);
4888 }
4889
4890 void Assembler::xchgw(Register dst, Address src) { // xchg
4891 InstructionMark im(this);
4892 emit_int8(0x66);
4893 prefix(src, dst);
4894 emit_int8((unsigned char)0x87);
4895 emit_operand(dst, src);
4896 }
4897
4898 void Assembler::xchgl(Register dst, Address src) { // xchg
4899 InstructionMark im(this);
4900 prefix(src, dst);
4901 emit_int8((unsigned char)0x87);
4902 emit_operand(dst, src);
4903 }
4904
4905 void Assembler::xchgl(Register dst, Register src) {
4906 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4907 emit_int8((unsigned char)0x87);
4908 emit_int8((unsigned char)(0xC0 | encode));
4909 }
4910
4911 void Assembler::xend() {
4912 emit_int8((unsigned char)0x0F);
4913 emit_int8((unsigned char)0x01);
4914 emit_int8((unsigned char)0xD5);
4915 }
4916
4917 void Assembler::xgetbv() {
4918 emit_int8(0x0F);
4919 emit_int8(0x01);
4920 emit_int8((unsigned char)0xD0);
4921 }
4922
4923 void Assembler::xorl(Register dst, int32_t imm32) {
4924 prefix(dst);
4925 emit_arith(0x81, 0xF0, dst, imm32);
4926 }
4927
4928 void Assembler::xorl(Register dst, Address src) {
4929 InstructionMark im(this);
4930 prefix(src, dst);
4931 emit_int8(0x33);
4932 emit_operand(dst, src);
4933 }
4934
4935 void Assembler::xorl(Register dst, Register src) {
4936 (void) prefix_and_encode(dst->encoding(), src->encoding());
4937 emit_arith(0x33, 0xC0, dst, src);
4938 }
4939
4940 void Assembler::xorb(Register dst, Address src) {
4941 InstructionMark im(this);
4942 prefix(src, dst);
4943 emit_int8(0x32);
4944 emit_operand(dst, src);
4945 }
4946
4947 // AVX 3-operands scalar float-point arithmetic instructions
4948
4949 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4950 assert(VM_Version::supports_avx(), "");
4951 InstructionMark im(this);
4952 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4953 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4954 attributes.set_rex_vex_w_reverted();
4955 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4956 emit_int8(0x58);
4957 emit_operand(dst, src);
4958 }
4959
4960 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4961 assert(VM_Version::supports_avx(), "");
4962 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4963 attributes.set_rex_vex_w_reverted();
4964 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4965 emit_int8(0x58);
4966 emit_int8((unsigned char)(0xC0 | encode));
4967 }
4968
4969 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4970 assert(VM_Version::supports_avx(), "");
4971 InstructionMark im(this);
4972 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4973 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4974 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4975 emit_int8(0x58);
4976 emit_operand(dst, src);
4977 }
4978
4979 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4980 assert(VM_Version::supports_avx(), "");
4981 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4982 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4983 emit_int8(0x58);
4984 emit_int8((unsigned char)(0xC0 | encode));
4985 }
4986
4987 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4988 assert(VM_Version::supports_avx(), "");
4989 InstructionMark im(this);
4990 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4991 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4992 attributes.set_rex_vex_w_reverted();
4993 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4994 emit_int8(0x5E);
4995 emit_operand(dst, src);
4996 }
4997
4998 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4999 assert(VM_Version::supports_avx(), "");
5000 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5001 attributes.set_rex_vex_w_reverted();
5002 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5003 emit_int8(0x5E);
5004 emit_int8((unsigned char)(0xC0 | encode));
5005 }
5006
5007 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5008 assert(VM_Version::supports_avx(), "");
5009 InstructionMark im(this);
5010 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5011 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5012 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5013 emit_int8(0x5E);
5014 emit_operand(dst, src);
5015 }
5016
5017 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5018 assert(VM_Version::supports_avx(), "");
5019 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5020 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5021 emit_int8(0x5E);
5022 emit_int8((unsigned char)(0xC0 | encode));
5023 }
5024
5025 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5026 assert(VM_Version::supports_fma(), "");
5027 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5028 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5029 emit_int8((unsigned char)0xB9);
5030 emit_int8((unsigned char)(0xC0 | encode));
5031 }
5032
5033 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5034 assert(VM_Version::supports_fma(), "");
5035 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5036 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5037 emit_int8((unsigned char)0xB9);
5038 emit_int8((unsigned char)(0xC0 | encode));
5039 }
5040
5041 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5042 assert(VM_Version::supports_avx(), "");
5043 InstructionMark im(this);
5044 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5045 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5046 attributes.set_rex_vex_w_reverted();
5047 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5048 emit_int8(0x59);
5049 emit_operand(dst, src);
5050 }
5051
5052 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5053 assert(VM_Version::supports_avx(), "");
5054 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5055 attributes.set_rex_vex_w_reverted();
5056 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5057 emit_int8(0x59);
5058 emit_int8((unsigned char)(0xC0 | encode));
5059 }
5060
5061 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5062 assert(VM_Version::supports_avx(), "");
5063 InstructionMark im(this);
5064 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5065 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5066 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5067 emit_int8(0x59);
5068 emit_operand(dst, src);
5069 }
5070
5071 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5072 assert(VM_Version::supports_avx(), "");
5073 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5074 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5075 emit_int8(0x59);
5076 emit_int8((unsigned char)(0xC0 | encode));
5077 }
5078
5079 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5080 assert(VM_Version::supports_avx(), "");
5081 InstructionMark im(this);
5082 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5083 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5084 attributes.set_rex_vex_w_reverted();
5085 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5086 emit_int8(0x5C);
5087 emit_operand(dst, src);
5088 }
5089
5090 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5091 assert(VM_Version::supports_avx(), "");
5092 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5093 attributes.set_rex_vex_w_reverted();
5094 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5095 emit_int8(0x5C);
5096 emit_int8((unsigned char)(0xC0 | encode));
5097 }
5098
5099 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5100 assert(VM_Version::supports_avx(), "");
5101 InstructionMark im(this);
5102 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5103 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5104 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5105 emit_int8(0x5C);
5106 emit_operand(dst, src);
5107 }
5108
5109 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5110 assert(VM_Version::supports_avx(), "");
5111 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5112 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5113 emit_int8(0x5C);
5114 emit_int8((unsigned char)(0xC0 | encode));
5115 }
5116
5117 //====================VECTOR ARITHMETIC=====================================
5118
5119 // Float-point vector arithmetic
5120
5121 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5123 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5124 attributes.set_rex_vex_w_reverted();
5125 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5126 emit_int8(0x58);
5127 emit_int8((unsigned char)(0xC0 | encode));
5128 }
5129
5130 void Assembler::addpd(XMMRegister dst, Address src) {
5131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5132 InstructionMark im(this);
5133 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5134 attributes.set_rex_vex_w_reverted();
5135 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5136 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5137 emit_int8(0x58);
5138 emit_operand(dst, src);
5139 }
5140
5141
5142 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5143 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5144 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5145 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5146 emit_int8(0x58);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 }
5149
5150 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5151 assert(VM_Version::supports_avx(), "");
5152 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5153 attributes.set_rex_vex_w_reverted();
5154 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5155 emit_int8(0x58);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5158
5159 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5160 assert(VM_Version::supports_avx(), "");
5161 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5162 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5163 emit_int8(0x58);
5164 emit_int8((unsigned char)(0xC0 | encode));
5165 }
5166
5167 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5168 assert(VM_Version::supports_avx(), "");
5169 InstructionMark im(this);
5170 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5171 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5172 attributes.set_rex_vex_w_reverted();
5173 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5174 emit_int8(0x58);
5175 emit_operand(dst, src);
5176 }
5177
5178 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5179 assert(VM_Version::supports_avx(), "");
5180 InstructionMark im(this);
5181 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5182 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5183 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5184 emit_int8(0x58);
5185 emit_operand(dst, src);
5186 }
5187
5188 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5190 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5191 attributes.set_rex_vex_w_reverted();
5192 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5193 emit_int8(0x5C);
5194 emit_int8((unsigned char)(0xC0 | encode));
5195 }
5196
5197 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5198 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5200 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5201 emit_int8(0x5C);
5202 emit_int8((unsigned char)(0xC0 | encode));
5203 }
5204
5205 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5206 assert(VM_Version::supports_avx(), "");
5207 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5208 attributes.set_rex_vex_w_reverted();
5209 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5210 emit_int8(0x5C);
5211 emit_int8((unsigned char)(0xC0 | encode));
5212 }
5213
5214 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5215 assert(VM_Version::supports_avx(), "");
5216 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5217 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5218 emit_int8(0x5C);
5219 emit_int8((unsigned char)(0xC0 | encode));
5220 }
5221
5222 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5223 assert(VM_Version::supports_avx(), "");
5224 InstructionMark im(this);
5225 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5226 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5227 attributes.set_rex_vex_w_reverted();
5228 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5229 emit_int8(0x5C);
5230 emit_operand(dst, src);
5231 }
5232
5233 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5234 assert(VM_Version::supports_avx(), "");
5235 InstructionMark im(this);
5236 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5237 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5238 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5239 emit_int8(0x5C);
5240 emit_operand(dst, src);
5241 }
5242
5243 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5244 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5245 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5246 attributes.set_rex_vex_w_reverted();
5247 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5248 emit_int8(0x59);
5249 emit_int8((unsigned char)(0xC0 | encode));
5250 }
5251
5252 void Assembler::mulpd(XMMRegister dst, Address src) {
5253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5254 InstructionMark im(this);
5255 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5256 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5257 attributes.set_rex_vex_w_reverted();
5258 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5259 emit_int8(0x59);
5260 emit_operand(dst, src);
5261 }
5262
5263 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5265 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5266 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5267 emit_int8(0x59);
5268 emit_int8((unsigned char)(0xC0 | encode));
5269 }
5270
5271 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5272 assert(VM_Version::supports_avx(), "");
5273 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5274 attributes.set_rex_vex_w_reverted();
5275 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5276 emit_int8(0x59);
5277 emit_int8((unsigned char)(0xC0 | encode));
5278 }
5279
5280 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5281 assert(VM_Version::supports_avx(), "");
5282 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5283 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5284 emit_int8(0x59);
5285 emit_int8((unsigned char)(0xC0 | encode));
5286 }
5287
5288 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5289 assert(VM_Version::supports_avx(), "");
5290 InstructionMark im(this);
5291 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5292 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5293 attributes.set_rex_vex_w_reverted();
5294 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5295 emit_int8(0x59);
5296 emit_operand(dst, src);
5297 }
5298
5299 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5300 assert(VM_Version::supports_avx(), "");
5301 InstructionMark im(this);
5302 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5303 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5304 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5305 emit_int8(0x59);
5306 emit_operand(dst, src);
5307 }
5308
5309 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5310 assert(VM_Version::supports_fma(), "");
5311 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5312 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5313 emit_int8((unsigned char)0xB8);
5314 emit_int8((unsigned char)(0xC0 | encode));
5315 }
5316
5317 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5318 assert(VM_Version::supports_fma(), "");
5319 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5320 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5321 emit_int8((unsigned char)0xB8);
5322 emit_int8((unsigned char)(0xC0 | encode));
5323 }
5324
5325 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5326 assert(VM_Version::supports_fma(), "");
5327 InstructionMark im(this);
5328 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5329 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5330 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5331 emit_int8((unsigned char)0xB8);
5332 emit_operand(dst, src2);
5333 }
5334
5335 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5336 assert(VM_Version::supports_fma(), "");
5337 InstructionMark im(this);
5338 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5339 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5340 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5341 emit_int8((unsigned char)0xB8);
5342 emit_operand(dst, src2);
5343 }
5344
5345 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5346 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5347 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5348 attributes.set_rex_vex_w_reverted();
5349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5350 emit_int8(0x5E);
5351 emit_int8((unsigned char)(0xC0 | encode));
5352 }
5353
5354 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5355 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5357 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5358 emit_int8(0x5E);
5359 emit_int8((unsigned char)(0xC0 | encode));
5360 }
5361
5362 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5363 assert(VM_Version::supports_avx(), "");
5364 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5365 attributes.set_rex_vex_w_reverted();
5366 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5367 emit_int8(0x5E);
5368 emit_int8((unsigned char)(0xC0 | encode));
5369 }
5370
5371 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5372 assert(VM_Version::supports_avx(), "");
5373 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5374 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5375 emit_int8(0x5E);
5376 emit_int8((unsigned char)(0xC0 | encode));
5377 }
5378
5379 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5380 assert(VM_Version::supports_avx(), "");
5381 InstructionMark im(this);
5382 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5383 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5384 attributes.set_rex_vex_w_reverted();
5385 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5386 emit_int8(0x5E);
5387 emit_operand(dst, src);
5388 }
5389
5390 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5391 assert(VM_Version::supports_avx(), "");
5392 InstructionMark im(this);
5393 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5394 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5395 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5396 emit_int8(0x5E);
5397 emit_operand(dst, src);
5398 }
5399
5400 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5401 assert(VM_Version::supports_avx(), "");
5402 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5403 attributes.set_rex_vex_w_reverted();
5404 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5405 emit_int8(0x51);
5406 emit_int8((unsigned char)(0xC0 | encode));
5407 }
5408
5409 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5410 assert(VM_Version::supports_avx(), "");
5411 InstructionMark im(this);
5412 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5413 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5414 attributes.set_rex_vex_w_reverted();
5415 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5416 emit_int8(0x51);
5417 emit_operand(dst, src);
5418 }
5419
5420 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5421 assert(VM_Version::supports_avx(), "");
5422 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5423 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5424 emit_int8(0x51);
5425 emit_int8((unsigned char)(0xC0 | encode));
5426 }
5427
5428 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5429 assert(VM_Version::supports_avx(), "");
5430 InstructionMark im(this);
5431 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5432 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5433 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5434 emit_int8(0x51);
5435 emit_operand(dst, src);
5436 }
5437
5438 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5440 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5441 attributes.set_rex_vex_w_reverted();
5442 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5443 emit_int8(0x54);
5444 emit_int8((unsigned char)(0xC0 | encode));
5445 }
5446
5447 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5448 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5449 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5450 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5451 emit_int8(0x54);
5452 emit_int8((unsigned char)(0xC0 | encode));
5453 }
5454
5455 void Assembler::andps(XMMRegister dst, Address src) {
5456 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5457 InstructionMark im(this);
5458 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5459 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5460 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5461 emit_int8(0x54);
5462 emit_operand(dst, src);
5463 }
5464
5465 void Assembler::andpd(XMMRegister dst, Address src) {
5466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5467 InstructionMark im(this);
5468 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5469 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5470 attributes.set_rex_vex_w_reverted();
5471 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5472 emit_int8(0x54);
5473 emit_operand(dst, src);
5474 }
5475
5476 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5477 assert(VM_Version::supports_avx(), "");
5478 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5479 attributes.set_rex_vex_w_reverted();
5480 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5481 emit_int8(0x54);
5482 emit_int8((unsigned char)(0xC0 | encode));
5483 }
5484
5485 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5486 assert(VM_Version::supports_avx(), "");
5487 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5488 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5489 emit_int8(0x54);
5490 emit_int8((unsigned char)(0xC0 | encode));
5491 }
5492
5493 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5494 assert(VM_Version::supports_avx(), "");
5495 InstructionMark im(this);
5496 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5497 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5498 attributes.set_rex_vex_w_reverted();
5499 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5500 emit_int8(0x54);
5501 emit_operand(dst, src);
5502 }
5503
5504 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5505 assert(VM_Version::supports_avx(), "");
5506 InstructionMark im(this);
5507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5508 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5509 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5510 emit_int8(0x54);
5511 emit_operand(dst, src);
5512 }
5513
5514 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5515 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5516 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5517 attributes.set_rex_vex_w_reverted();
5518 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5519 emit_int8(0x15);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 }
5522
5523 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5525 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5526 attributes.set_rex_vex_w_reverted();
5527 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5528 emit_int8(0x14);
5529 emit_int8((unsigned char)(0xC0 | encode));
5530 }
5531
5532 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5533 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5534 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5535 attributes.set_rex_vex_w_reverted();
5536 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5537 emit_int8(0x57);
5538 emit_int8((unsigned char)(0xC0 | encode));
5539 }
5540
5541 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5542 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5543 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5544 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5545 emit_int8(0x57);
5546 emit_int8((unsigned char)(0xC0 | encode));
5547 }
5548
5549 void Assembler::xorpd(XMMRegister dst, Address src) {
5550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5551 InstructionMark im(this);
5552 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5553 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5554 attributes.set_rex_vex_w_reverted();
5555 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5556 emit_int8(0x57);
5557 emit_operand(dst, src);
5558 }
5559
5560 void Assembler::xorps(XMMRegister dst, Address src) {
5561 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5562 InstructionMark im(this);
5563 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5564 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5565 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5566 emit_int8(0x57);
5567 emit_operand(dst, src);
5568 }
5569
5570 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5571 assert(VM_Version::supports_avx(), "");
5572 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5573 attributes.set_rex_vex_w_reverted();
5574 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5575 emit_int8(0x57);
5576 emit_int8((unsigned char)(0xC0 | encode));
5577 }
5578
5579 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5580 assert(VM_Version::supports_avx(), "");
5581 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5582 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5583 emit_int8(0x57);
5584 emit_int8((unsigned char)(0xC0 | encode));
5585 }
5586
5587 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5588 assert(VM_Version::supports_avx(), "");
5589 InstructionMark im(this);
5590 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5591 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5592 attributes.set_rex_vex_w_reverted();
5593 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5594 emit_int8(0x57);
5595 emit_operand(dst, src);
5596 }
5597
5598 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5599 assert(VM_Version::supports_avx(), "");
5600 InstructionMark im(this);
5601 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5602 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5603 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5604 emit_int8(0x57);
5605 emit_operand(dst, src);
5606 }
5607
5608 // Integer vector arithmetic
5609 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5610 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5611 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5612 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5613 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5614 emit_int8(0x01);
5615 emit_int8((unsigned char)(0xC0 | encode));
5616 }
5617
5618 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5619 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5620 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5621 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5622 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5623 emit_int8(0x02);
5624 emit_int8((unsigned char)(0xC0 | encode));
5625 }
5626
5627 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5629 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5630 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5631 emit_int8((unsigned char)0xFC);
5632 emit_int8((unsigned char)(0xC0 | encode));
5633 }
5634
5635 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5639 emit_int8((unsigned char)0xFD);
5640 emit_int8((unsigned char)(0xC0 | encode));
5641 }
5642
5643 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5644 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5645 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5647 emit_int8((unsigned char)0xFE);
5648 emit_int8((unsigned char)(0xC0 | encode));
5649 }
5650
5651 void Assembler::paddd(XMMRegister dst, Address src) {
5652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5653 InstructionMark im(this);
5654 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5655 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5656 emit_int8((unsigned char)0xFE);
5657 emit_operand(dst, src);
5658 }
5659
5660 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5661 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5662 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5663 attributes.set_rex_vex_w_reverted();
5664 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5665 emit_int8((unsigned char)0xD4);
5666 emit_int8((unsigned char)(0xC0 | encode));
5667 }
5668
5669 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5670 assert(VM_Version::supports_sse3(), "");
5671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5672 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5673 emit_int8(0x01);
5674 emit_int8((unsigned char)(0xC0 | encode));
5675 }
5676
5677 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5678 assert(VM_Version::supports_sse3(), "");
5679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5681 emit_int8(0x02);
5682 emit_int8((unsigned char)(0xC0 | encode));
5683 }
5684
5685 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5686 assert(UseAVX > 0, "requires some form of AVX");
5687 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5688 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5689 emit_int8((unsigned char)0xFC);
5690 emit_int8((unsigned char)(0xC0 | encode));
5691 }
5692
5693 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5694 assert(UseAVX > 0, "requires some form of AVX");
5695 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5696 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5697 emit_int8((unsigned char)0xFD);
5698 emit_int8((unsigned char)(0xC0 | encode));
5699 }
5700
5701 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5702 assert(UseAVX > 0, "requires some form of AVX");
5703 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5704 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5705 emit_int8((unsigned char)0xFE);
5706 emit_int8((unsigned char)(0xC0 | encode));
5707 }
5708
5709 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5710 assert(UseAVX > 0, "requires some form of AVX");
5711 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5712 attributes.set_rex_vex_w_reverted();
5713 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5714 emit_int8((unsigned char)0xD4);
5715 emit_int8((unsigned char)(0xC0 | encode));
5716 }
5717
5718 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5719 assert(UseAVX > 0, "requires some form of AVX");
5720 InstructionMark im(this);
5721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5722 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5723 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5724 emit_int8((unsigned char)0xFC);
5725 emit_operand(dst, src);
5726 }
5727
5728 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5729 assert(UseAVX > 0, "requires some form of AVX");
5730 InstructionMark im(this);
5731 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5732 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5733 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5734 emit_int8((unsigned char)0xFD);
5735 emit_operand(dst, src);
5736 }
5737
5738 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5739 assert(UseAVX > 0, "requires some form of AVX");
5740 InstructionMark im(this);
5741 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5742 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5743 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5744 emit_int8((unsigned char)0xFE);
5745 emit_operand(dst, src);
5746 }
5747
5748 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5749 assert(UseAVX > 0, "requires some form of AVX");
5750 InstructionMark im(this);
5751 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5752 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5753 attributes.set_rex_vex_w_reverted();
5754 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5755 emit_int8((unsigned char)0xD4);
5756 emit_operand(dst, src);
5757 }
5758
5759 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5761 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5762 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5763 emit_int8((unsigned char)0xF8);
5764 emit_int8((unsigned char)(0xC0 | encode));
5765 }
5766
5767 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5768 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5769 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5770 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5771 emit_int8((unsigned char)0xF9);
5772 emit_int8((unsigned char)(0xC0 | encode));
5773 }
5774
5775 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5777 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5778 emit_int8((unsigned char)0xFA);
5779 emit_int8((unsigned char)(0xC0 | encode));
5780 }
5781
5782 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5784 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5785 attributes.set_rex_vex_w_reverted();
5786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5787 emit_int8((unsigned char)0xFB);
5788 emit_int8((unsigned char)(0xC0 | encode));
5789 }
5790
5791 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5792 assert(UseAVX > 0, "requires some form of AVX");
5793 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5794 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5795 emit_int8((unsigned char)0xF8);
5796 emit_int8((unsigned char)(0xC0 | encode));
5797 }
5798
5799 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5800 assert(UseAVX > 0, "requires some form of AVX");
5801 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5802 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5803 emit_int8((unsigned char)0xF9);
5804 emit_int8((unsigned char)(0xC0 | encode));
5805 }
5806
5807 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5808 assert(UseAVX > 0, "requires some form of AVX");
5809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5810 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5811 emit_int8((unsigned char)0xFA);
5812 emit_int8((unsigned char)(0xC0 | encode));
5813 }
5814
5815 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5816 assert(UseAVX > 0, "requires some form of AVX");
5817 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5818 attributes.set_rex_vex_w_reverted();
5819 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5820 emit_int8((unsigned char)0xFB);
5821 emit_int8((unsigned char)(0xC0 | encode));
5822 }
5823
5824 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5825 assert(UseAVX > 0, "requires some form of AVX");
5826 InstructionMark im(this);
5827 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5828 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5829 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5830 emit_int8((unsigned char)0xF8);
5831 emit_operand(dst, src);
5832 }
5833
5834 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5835 assert(UseAVX > 0, "requires some form of AVX");
5836 InstructionMark im(this);
5837 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5838 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5839 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5840 emit_int8((unsigned char)0xF9);
5841 emit_operand(dst, src);
5842 }
5843
5844 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5845 assert(UseAVX > 0, "requires some form of AVX");
5846 InstructionMark im(this);
5847 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5848 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5849 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5850 emit_int8((unsigned char)0xFA);
5851 emit_operand(dst, src);
5852 }
5853
5854 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5855 assert(UseAVX > 0, "requires some form of AVX");
5856 InstructionMark im(this);
5857 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5858 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5859 attributes.set_rex_vex_w_reverted();
5860 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5861 emit_int8((unsigned char)0xFB);
5862 emit_operand(dst, src);
5863 }
5864
5865 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5866 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5867 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5868 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5869 emit_int8((unsigned char)0xD5);
5870 emit_int8((unsigned char)(0xC0 | encode));
5871 }
5872
5873 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5874 assert(VM_Version::supports_sse4_1(), "");
5875 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5876 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5877 emit_int8(0x40);
5878 emit_int8((unsigned char)(0xC0 | encode));
5879 }
5880
5881 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5882 assert(UseAVX > 0, "requires some form of AVX");
5883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5884 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5885 emit_int8((unsigned char)0xD5);
5886 emit_int8((unsigned char)(0xC0 | encode));
5887 }
5888
5889 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5890 assert(UseAVX > 0, "requires some form of AVX");
5891 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5893 emit_int8(0x40);
5894 emit_int8((unsigned char)(0xC0 | encode));
5895 }
5896
5897 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5898 assert(UseAVX > 2, "requires some form of EVEX");
5899 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5900 attributes.set_is_evex_instruction();
5901 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5902 emit_int8(0x40);
5903 emit_int8((unsigned char)(0xC0 | encode));
5904 }
5905
5906 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5907 assert(UseAVX > 0, "requires some form of AVX");
5908 InstructionMark im(this);
5909 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5910 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5911 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5912 emit_int8((unsigned char)0xD5);
5913 emit_operand(dst, src);
5914 }
5915
5916 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5917 assert(UseAVX > 0, "requires some form of AVX");
5918 InstructionMark im(this);
5919 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5920 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5921 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5922 emit_int8(0x40);
5923 emit_operand(dst, src);
5924 }
5925
5926 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5927 assert(UseAVX > 2, "requires some form of EVEX");
5928 InstructionMark im(this);
5929 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5930 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5931 attributes.set_is_evex_instruction();
5932 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5933 emit_int8(0x40);
5934 emit_operand(dst, src);
5935 }
5936
5937 // Shift packed integers left by specified number of bits.
5938 void Assembler::psllw(XMMRegister dst, int shift) {
5939 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5940 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5941 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5942 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5943 emit_int8(0x71);
5944 emit_int8((unsigned char)(0xC0 | encode));
5945 emit_int8(shift & 0xFF);
5946 }
5947
5948 void Assembler::pslld(XMMRegister dst, int shift) {
5949 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5950 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5951 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5952 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5953 emit_int8(0x72);
5954 emit_int8((unsigned char)(0xC0 | encode));
5955 emit_int8(shift & 0xFF);
5956 }
5957
5958 void Assembler::psllq(XMMRegister dst, int shift) {
5959 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5960 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5961 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5962 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5963 emit_int8(0x73);
5964 emit_int8((unsigned char)(0xC0 | encode));
5965 emit_int8(shift & 0xFF);
5966 }
5967
5968 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5969 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5970 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5971 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5972 emit_int8((unsigned char)0xF1);
5973 emit_int8((unsigned char)(0xC0 | encode));
5974 }
5975
5976 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5977 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5978 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5979 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5980 emit_int8((unsigned char)0xF2);
5981 emit_int8((unsigned char)(0xC0 | encode));
5982 }
5983
5984 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5985 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5986 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5987 attributes.set_rex_vex_w_reverted();
5988 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5989 emit_int8((unsigned char)0xF3);
5990 emit_int8((unsigned char)(0xC0 | encode));
5991 }
5992
5993 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5994 assert(UseAVX > 0, "requires some form of AVX");
5995 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5996 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5997 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5998 emit_int8(0x71);
5999 emit_int8((unsigned char)(0xC0 | encode));
6000 emit_int8(shift & 0xFF);
6001 }
6002
6003 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6004 assert(UseAVX > 0, "requires some form of AVX");
6005 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6006 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6007 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6008 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6009 emit_int8(0x72);
6010 emit_int8((unsigned char)(0xC0 | encode));
6011 emit_int8(shift & 0xFF);
6012 }
6013
6014 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6015 assert(UseAVX > 0, "requires some form of AVX");
6016 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6017 attributes.set_rex_vex_w_reverted();
6018 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6019 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6020 emit_int8(0x73);
6021 emit_int8((unsigned char)(0xC0 | encode));
6022 emit_int8(shift & 0xFF);
6023 }
6024
6025 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6026 assert(UseAVX > 0, "requires some form of AVX");
6027 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6028 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6029 emit_int8((unsigned char)0xF1);
6030 emit_int8((unsigned char)(0xC0 | encode));
6031 }
6032
6033 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6034 assert(UseAVX > 0, "requires some form of AVX");
6035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6036 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6037 emit_int8((unsigned char)0xF2);
6038 emit_int8((unsigned char)(0xC0 | encode));
6039 }
6040
6041 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6042 assert(UseAVX > 0, "requires some form of AVX");
6043 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6044 attributes.set_rex_vex_w_reverted();
6045 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6046 emit_int8((unsigned char)0xF3);
6047 emit_int8((unsigned char)(0xC0 | encode));
6048 }
6049
6050 // Shift packed integers logically right by specified number of bits.
6051 void Assembler::psrlw(XMMRegister dst, int shift) {
6052 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6054 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6055 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6056 emit_int8(0x71);
6057 emit_int8((unsigned char)(0xC0 | encode));
6058 emit_int8(shift & 0xFF);
6059 }
6060
6061 void Assembler::psrld(XMMRegister dst, int shift) {
6062 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6063 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6064 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6065 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6066 emit_int8(0x72);
6067 emit_int8((unsigned char)(0xC0 | encode));
6068 emit_int8(shift & 0xFF);
6069 }
6070
6071 void Assembler::psrlq(XMMRegister dst, int shift) {
6072 // Do not confuse it with psrldq SSE2 instruction which
6073 // shifts 128 bit value in xmm register by number of bytes.
6074 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6075 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6076 attributes.set_rex_vex_w_reverted();
6077 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6078 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6079 emit_int8(0x73);
6080 emit_int8((unsigned char)(0xC0 | encode));
6081 emit_int8(shift & 0xFF);
6082 }
6083
6084 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6085 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6087 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6088 emit_int8((unsigned char)0xD1);
6089 emit_int8((unsigned char)(0xC0 | encode));
6090 }
6091
6092 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6093 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6094 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6095 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6096 emit_int8((unsigned char)0xD2);
6097 emit_int8((unsigned char)(0xC0 | encode));
6098 }
6099
6100 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6101 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6102 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6103 attributes.set_rex_vex_w_reverted();
6104 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6105 emit_int8((unsigned char)0xD3);
6106 emit_int8((unsigned char)(0xC0 | encode));
6107 }
6108
6109 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6110 assert(UseAVX > 0, "requires some form of AVX");
6111 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6112 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6113 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6114 emit_int8(0x71);
6115 emit_int8((unsigned char)(0xC0 | encode));
6116 emit_int8(shift & 0xFF);
6117 }
6118
6119 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6120 assert(UseAVX > 0, "requires some form of AVX");
6121 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6122 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6123 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6124 emit_int8(0x72);
6125 emit_int8((unsigned char)(0xC0 | encode));
6126 emit_int8(shift & 0xFF);
6127 }
6128
6129 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6130 assert(UseAVX > 0, "requires some form of AVX");
6131 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6132 attributes.set_rex_vex_w_reverted();
6133 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6134 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6135 emit_int8(0x73);
6136 emit_int8((unsigned char)(0xC0 | encode));
6137 emit_int8(shift & 0xFF);
6138 }
6139
6140 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6141 assert(UseAVX > 0, "requires some form of AVX");
6142 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6143 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6144 emit_int8((unsigned char)0xD1);
6145 emit_int8((unsigned char)(0xC0 | encode));
6146 }
6147
6148 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6149 assert(UseAVX > 0, "requires some form of AVX");
6150 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6151 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6152 emit_int8((unsigned char)0xD2);
6153 emit_int8((unsigned char)(0xC0 | encode));
6154 }
6155
6156 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6157 assert(UseAVX > 0, "requires some form of AVX");
6158 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6159 attributes.set_rex_vex_w_reverted();
6160 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6161 emit_int8((unsigned char)0xD3);
6162 emit_int8((unsigned char)(0xC0 | encode));
6163 }
6164
6165 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6166 assert(VM_Version::supports_avx512bw(), "");
6167 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6168 attributes.set_is_evex_instruction();
6169 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6170 emit_int8(0x10);
6171 emit_int8((unsigned char)(0xC0 | encode));
6172 }
6173
6174 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6175 assert(VM_Version::supports_avx512bw(), "");
6176 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6177 attributes.set_is_evex_instruction();
6178 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6179 emit_int8(0x12);
6180 emit_int8((unsigned char)(0xC0 | encode));
6181 }
6182
6183 // Shift packed integers arithmetically right by specified number of bits.
6184 void Assembler::psraw(XMMRegister dst, int shift) {
6185 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6186 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6187 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6188 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6189 emit_int8(0x71);
6190 emit_int8((unsigned char)(0xC0 | encode));
6191 emit_int8(shift & 0xFF);
6192 }
6193
6194 void Assembler::psrad(XMMRegister dst, int shift) {
6195 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6196 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6197 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6198 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6199 emit_int8(0x72);
6200 emit_int8((unsigned char)(0xC0 | encode));
6201 emit_int8(shift & 0xFF);
6202 }
6203
6204 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6205 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6206 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6207 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6208 emit_int8((unsigned char)0xE1);
6209 emit_int8((unsigned char)(0xC0 | encode));
6210 }
6211
6212 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6213 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6214 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6215 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6216 emit_int8((unsigned char)0xE2);
6217 emit_int8((unsigned char)(0xC0 | encode));
6218 }
6219
6220 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6221 assert(UseAVX > 0, "requires some form of AVX");
6222 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6223 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6224 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6225 emit_int8(0x71);
6226 emit_int8((unsigned char)(0xC0 | encode));
6227 emit_int8(shift & 0xFF);
6228 }
6229
6230 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6231 assert(UseAVX > 0, "requires some form of AVX");
6232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6233 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6234 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6235 emit_int8(0x72);
6236 emit_int8((unsigned char)(0xC0 | encode));
6237 emit_int8(shift & 0xFF);
6238 }
6239
6240 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6241 assert(UseAVX > 0, "requires some form of AVX");
6242 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6243 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6244 emit_int8((unsigned char)0xE1);
6245 emit_int8((unsigned char)(0xC0 | encode));
6246 }
6247
6248 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6249 assert(UseAVX > 0, "requires some form of AVX");
6250 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6251 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6252 emit_int8((unsigned char)0xE2);
6253 emit_int8((unsigned char)(0xC0 | encode));
6254 }
6255
6256
6257 // logical operations packed integers
6258 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6262 emit_int8((unsigned char)0xDB);
6263 emit_int8((unsigned char)(0xC0 | encode));
6264 }
6265
6266 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6267 assert(UseAVX > 0, "requires some form of AVX");
6268 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6270 emit_int8((unsigned char)0xDB);
6271 emit_int8((unsigned char)(0xC0 | encode));
6272 }
6273
6274 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6275 assert(UseAVX > 0, "requires some form of AVX");
6276 InstructionMark im(this);
6277 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6278 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6279 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6280 emit_int8((unsigned char)0xDB);
6281 emit_operand(dst, src);
6282 }
6283
6284 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6285 assert(VM_Version::supports_evex(), "");
6286 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6287 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6288 emit_int8((unsigned char)0xDB);
6289 emit_int8((unsigned char)(0xC0 | encode));
6290 }
6291
6292
6293 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6294 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6295 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6296 attributes.set_rex_vex_w_reverted();
6297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6298 emit_int8((unsigned char)0xDF);
6299 emit_int8((unsigned char)(0xC0 | encode));
6300 }
6301
6302 void Assembler::por(XMMRegister dst, XMMRegister src) {
6303 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6304 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6306 emit_int8((unsigned char)0xEB);
6307 emit_int8((unsigned char)(0xC0 | encode));
6308 }
6309
6310 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6311 assert(UseAVX > 0, "requires some form of AVX");
6312 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6313 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6314 emit_int8((unsigned char)0xEB);
6315 emit_int8((unsigned char)(0xC0 | encode));
6316 }
6317
6318 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6319 assert(UseAVX > 0, "requires some form of AVX");
6320 InstructionMark im(this);
6321 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6322 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6323 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6324 emit_int8((unsigned char)0xEB);
6325 emit_operand(dst, src);
6326 }
6327
6328 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6329 assert(VM_Version::supports_evex(), "");
6330 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6331 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6332 emit_int8((unsigned char)0xEB);
6333 emit_int8((unsigned char)(0xC0 | encode));
6334 }
6335
6336
6337 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6338 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6339 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6340 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6341 emit_int8((unsigned char)0xEF);
6342 emit_int8((unsigned char)(0xC0 | encode));
6343 }
6344
6345 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6346 assert(UseAVX > 0, "requires some form of AVX");
6347 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6349 emit_int8((unsigned char)0xEF);
6350 emit_int8((unsigned char)(0xC0 | encode));
6351 }
6352
6353 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6354 assert(UseAVX > 0, "requires some form of AVX");
6355 InstructionMark im(this);
6356 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6357 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6358 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6359 emit_int8((unsigned char)0xEF);
6360 emit_operand(dst, src);
6361 }
6362
6363 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6364 assert(VM_Version::supports_evex(), "requires EVEX support");
6365 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6366 attributes.set_is_evex_instruction();
6367 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6368 emit_int8((unsigned char)0xEF);
6369 emit_int8((unsigned char)(0xC0 | encode));
6370 }
6371
6372 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6373 assert(VM_Version::supports_evex(), "requires EVEX support");
6374 assert(dst != xnoreg, "sanity");
6375 InstructionMark im(this);
6376 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6377 attributes.set_is_evex_instruction();
6378 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6379 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6380 emit_int8((unsigned char)0xEF);
6381 emit_operand(dst, src);
6382 }
6383
6384
6385 // vinserti forms
6386
6387 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6388 assert(VM_Version::supports_avx2(), "");
6389 assert(imm8 <= 0x01, "imm8: %u", imm8);
6390 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6392 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6393 emit_int8(0x38);
6394 emit_int8((unsigned char)(0xC0 | encode));
6395 // 0x00 - insert into lower 128 bits
6396 // 0x01 - insert into upper 128 bits
6397 emit_int8(imm8 & 0x01);
6398 }
6399
6400 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6401 assert(VM_Version::supports_avx2(), "");
6402 assert(dst != xnoreg, "sanity");
6403 assert(imm8 <= 0x01, "imm8: %u", imm8);
6404 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6405 InstructionMark im(this);
6406 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6407 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6408 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6409 emit_int8(0x38);
6410 emit_operand(dst, src);
6411 // 0x00 - insert into lower 128 bits
6412 // 0x01 - insert into upper 128 bits
6413 emit_int8(imm8 & 0x01);
6414 }
6415
6416 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6417 assert(VM_Version::supports_evex(), "");
6418 assert(imm8 <= 0x03, "imm8: %u", imm8);
6419 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6420 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6421 emit_int8(0x38);
6422 emit_int8((unsigned char)(0xC0 | encode));
6423 // 0x00 - insert into q0 128 bits (0..127)
6424 // 0x01 - insert into q1 128 bits (128..255)
6425 // 0x02 - insert into q2 128 bits (256..383)
6426 // 0x03 - insert into q3 128 bits (384..511)
6427 emit_int8(imm8 & 0x03);
6428 }
6429
6430 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6431 assert(VM_Version::supports_avx(), "");
6432 assert(dst != xnoreg, "sanity");
6433 assert(imm8 <= 0x03, "imm8: %u", imm8);
6434 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6435 InstructionMark im(this);
6436 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6437 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6438 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6439 emit_int8(0x18);
6440 emit_operand(dst, src);
6441 // 0x00 - insert into q0 128 bits (0..127)
6442 // 0x01 - insert into q1 128 bits (128..255)
6443 // 0x02 - insert into q2 128 bits (256..383)
6444 // 0x03 - insert into q3 128 bits (384..511)
6445 emit_int8(imm8 & 0x03);
6446 }
6447
6448 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6449 assert(VM_Version::supports_evex(), "");
6450 assert(imm8 <= 0x01, "imm8: %u", imm8);
6451 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6452 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6453 emit_int8(0x38);
6454 emit_int8((unsigned char)(0xC0 | encode));
6455 // 0x00 - insert into lower 256 bits
6456 // 0x01 - insert into upper 256 bits
6457 emit_int8(imm8 & 0x01);
6458 }
6459
6460
6461 // vinsertf forms
6462
6463 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6464 assert(VM_Version::supports_avx(), "");
6465 assert(imm8 <= 0x01, "imm8: %u", imm8);
6466 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6467 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6468 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6469 emit_int8(0x18);
6470 emit_int8((unsigned char)(0xC0 | encode));
6471 // 0x00 - insert into lower 128 bits
6472 // 0x01 - insert into upper 128 bits
6473 emit_int8(imm8 & 0x01);
6474 }
6475
6476 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6477 assert(VM_Version::supports_avx(), "");
6478 assert(dst != xnoreg, "sanity");
6479 assert(imm8 <= 0x01, "imm8: %u", imm8);
6480 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6481 InstructionMark im(this);
6482 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6483 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6484 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6485 emit_int8(0x18);
6486 emit_operand(dst, src);
6487 // 0x00 - insert into lower 128 bits
6488 // 0x01 - insert into upper 128 bits
6489 emit_int8(imm8 & 0x01);
6490 }
6491
6492 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6493 assert(VM_Version::supports_evex(), "");
6494 assert(imm8 <= 0x03, "imm8: %u", imm8);
6495 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6496 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6497 emit_int8(0x18);
6498 emit_int8((unsigned char)(0xC0 | encode));
6499 // 0x00 - insert into q0 128 bits (0..127)
6500 // 0x01 - insert into q1 128 bits (128..255)
6501 // 0x02 - insert into q2 128 bits (256..383)
6502 // 0x03 - insert into q3 128 bits (384..511)
6503 emit_int8(imm8 & 0x03);
6504 }
6505
6506 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6507 assert(VM_Version::supports_avx(), "");
6508 assert(dst != xnoreg, "sanity");
6509 assert(imm8 <= 0x03, "imm8: %u", imm8);
6510 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6511 InstructionMark im(this);
6512 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6513 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6514 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6515 emit_int8(0x18);
6516 emit_operand(dst, src);
6517 // 0x00 - insert into q0 128 bits (0..127)
6518 // 0x01 - insert into q1 128 bits (128..255)
6519 // 0x02 - insert into q2 128 bits (256..383)
6520 // 0x03 - insert into q3 128 bits (384..511)
6521 emit_int8(imm8 & 0x03);
6522 }
6523
6524 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6525 assert(VM_Version::supports_evex(), "");
6526 assert(imm8 <= 0x01, "imm8: %u", imm8);
6527 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6528 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6529 emit_int8(0x1A);
6530 emit_int8((unsigned char)(0xC0 | encode));
6531 // 0x00 - insert into lower 256 bits
6532 // 0x01 - insert into upper 256 bits
6533 emit_int8(imm8 & 0x01);
6534 }
6535
6536 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6537 assert(VM_Version::supports_evex(), "");
6538 assert(dst != xnoreg, "sanity");
6539 assert(imm8 <= 0x01, "imm8: %u", imm8);
6540 InstructionMark im(this);
6541 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6542 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
6543 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6544 emit_int8(0x1A);
6545 emit_operand(dst, src);
6546 // 0x00 - insert into lower 256 bits
6547 // 0x01 - insert into upper 256 bits
6548 emit_int8(imm8 & 0x01);
6549 }
6550
6551
6552 // vextracti forms
6553
6554 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6555 assert(VM_Version::supports_avx(), "");
6556 assert(imm8 <= 0x01, "imm8: %u", imm8);
6557 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6558 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6559 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6560 emit_int8(0x39);
6561 emit_int8((unsigned char)(0xC0 | encode));
6562 // 0x00 - extract from lower 128 bits
6563 // 0x01 - extract from upper 128 bits
6564 emit_int8(imm8 & 0x01);
6565 }
6566
6567 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
6568 assert(VM_Version::supports_avx2(), "");
6569 assert(src != xnoreg, "sanity");
6570 assert(imm8 <= 0x01, "imm8: %u", imm8);
6571 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6572 InstructionMark im(this);
6573 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6574 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6575 attributes.reset_is_clear_context();
6576 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6577 emit_int8(0x39);
6578 emit_operand(src, dst);
6579 // 0x00 - extract from lower 128 bits
6580 // 0x01 - extract from upper 128 bits
6581 emit_int8(imm8 & 0x01);
6582 }
6583
6584 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6585 assert(VM_Version::supports_avx(), "");
6586 assert(imm8 <= 0x03, "imm8: %u", imm8);
6587 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6588 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6589 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6590 emit_int8(0x39);
6591 emit_int8((unsigned char)(0xC0 | encode));
6592 // 0x00 - extract from bits 127:0
6593 // 0x01 - extract from bits 255:128
6594 // 0x02 - extract from bits 383:256
6595 // 0x03 - extract from bits 511:384
6596 emit_int8(imm8 & 0x03);
6597 }
6598
6599 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
6600 assert(VM_Version::supports_evex(), "");
6601 assert(src != xnoreg, "sanity");
6602 assert(imm8 <= 0x03, "imm8: %u", imm8);
6603 InstructionMark im(this);
6604 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6605 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6606 attributes.reset_is_clear_context();
6607 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6608 emit_int8(0x39);
6609 emit_operand(src, dst);
6610 // 0x00 - extract from bits 127:0
6611 // 0x01 - extract from bits 255:128
6612 // 0x02 - extract from bits 383:256
6613 // 0x03 - extract from bits 511:384
6614 emit_int8(imm8 & 0x03);
6615 }
6616
6617 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6618 assert(VM_Version::supports_avx512dq(), "");
6619 assert(imm8 <= 0x03, "imm8: %u", imm8);
6620 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6621 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6622 emit_int8(0x39);
6623 emit_int8((unsigned char)(0xC0 | encode));
6624 // 0x00 - extract from bits 127:0
6625 // 0x01 - extract from bits 255:128
6626 // 0x02 - extract from bits 383:256
6627 // 0x03 - extract from bits 511:384
6628 emit_int8(imm8 & 0x03);
6629 }
6630
6631 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6632 assert(VM_Version::supports_evex(), "");
6633 assert(imm8 <= 0x01, "imm8: %u", imm8);
6634 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6635 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6636 emit_int8(0x3B);
6637 emit_int8((unsigned char)(0xC0 | encode));
6638 // 0x00 - extract from lower 256 bits
6639 // 0x01 - extract from upper 256 bits
6640 emit_int8(imm8 & 0x01);
6641 }
6642
6643
6644 // vextractf forms
6645
6646 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6647 assert(VM_Version::supports_avx(), "");
6648 assert(imm8 <= 0x01, "imm8: %u", imm8);
6649 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6650 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6651 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6652 emit_int8(0x19);
6653 emit_int8((unsigned char)(0xC0 | encode));
6654 // 0x00 - extract from lower 128 bits
6655 // 0x01 - extract from upper 128 bits
6656 emit_int8(imm8 & 0x01);
6657 }
6658
6659 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
6660 assert(VM_Version::supports_avx(), "");
6661 assert(src != xnoreg, "sanity");
6662 assert(imm8 <= 0x01, "imm8: %u", imm8);
6663 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6664 InstructionMark im(this);
6665 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6666 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6667 attributes.reset_is_clear_context();
6668 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6669 emit_int8(0x19);
6670 emit_operand(src, dst);
6671 // 0x00 - extract from lower 128 bits
6672 // 0x01 - extract from upper 128 bits
6673 emit_int8(imm8 & 0x01);
6674 }
6675
6676 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6677 assert(VM_Version::supports_avx(), "");
6678 assert(imm8 <= 0x03, "imm8: %u", imm8);
6679 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6680 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6681 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6682 emit_int8(0x19);
6683 emit_int8((unsigned char)(0xC0 | encode));
6684 // 0x00 - extract from bits 127:0
6685 // 0x01 - extract from bits 255:128
6686 // 0x02 - extract from bits 383:256
6687 // 0x03 - extract from bits 511:384
6688 emit_int8(imm8 & 0x03);
6689 }
6690
6691 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
6692 assert(VM_Version::supports_evex(), "");
6693 assert(src != xnoreg, "sanity");
6694 assert(imm8 <= 0x03, "imm8: %u", imm8);
6695 InstructionMark im(this);
6696 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6697 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6698 attributes.reset_is_clear_context();
6699 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6700 emit_int8(0x19);
6701 emit_operand(src, dst);
6702 // 0x00 - extract from bits 127:0
6703 // 0x01 - extract from bits 255:128
6704 // 0x02 - extract from bits 383:256
6705 // 0x03 - extract from bits 511:384
6706 emit_int8(imm8 & 0x03);
6707 }
6708
6709 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6710 assert(VM_Version::supports_avx512dq(), "");
6711 assert(imm8 <= 0x03, "imm8: %u", imm8);
6712 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6713 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6714 emit_int8(0x19);
6715 emit_int8((unsigned char)(0xC0 | encode));
6716 // 0x00 - extract from bits 127:0
6717 // 0x01 - extract from bits 255:128
6718 // 0x02 - extract from bits 383:256
6719 // 0x03 - extract from bits 511:384
6720 emit_int8(imm8 & 0x03);
6721 }
6722
6723 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
6724 assert(VM_Version::supports_evex(), "");
6725 assert(imm8 <= 0x01, "imm8: %u", imm8);
6726 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6727 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6728 emit_int8(0x1B);
6729 emit_int8((unsigned char)(0xC0 | encode));
6730 // 0x00 - extract from lower 256 bits
6731 // 0x01 - extract from upper 256 bits
6732 emit_int8(imm8 & 0x01);
6733 }
6734
6735 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
6736 assert(VM_Version::supports_evex(), "");
6737 assert(src != xnoreg, "sanity");
6738 assert(imm8 <= 0x01, "imm8: %u", imm8);
6739 InstructionMark im(this);
6740 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6741 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
6742 attributes.reset_is_clear_context();
6743 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6744 emit_int8(0x1B);
6745 emit_operand(src, dst);
6746 // 0x00 - extract from lower 256 bits
6747 // 0x01 - extract from upper 256 bits
6748 emit_int8(imm8 & 0x01);
6749 }
6750
6751
6752 // legacy word/dword replicate
6753 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6754 assert(VM_Version::supports_avx2(), "");
6755 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6756 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6757 emit_int8(0x79);
6758 emit_int8((unsigned char)(0xC0 | encode));
6759 }
6760
6761 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6762 assert(VM_Version::supports_avx2(), "");
6763 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6764 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6765 emit_int8(0x58);
6766 emit_int8((unsigned char)(0xC0 | encode));
6767 }
6768
6769
6770 // xmm/mem sourced byte/word/dword/qword replicate
6771
6772 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6773 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6774 assert(VM_Version::supports_evex(), "");
6775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6776 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6777 emit_int8(0x78);
6778 emit_int8((unsigned char)(0xC0 | encode));
6779 }
6780
6781 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6782 assert(VM_Version::supports_evex(), "");
6783 assert(dst != xnoreg, "sanity");
6784 InstructionMark im(this);
6785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6787 // swap src<->dst for encoding
6788 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6789 emit_int8(0x78);
6790 emit_operand(dst, src);
6791 }
6792
6793 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6794 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6795 assert(VM_Version::supports_evex(), "");
6796 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6797 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6798 emit_int8(0x79);
6799 emit_int8((unsigned char)(0xC0 | encode));
6800 }
6801
6802 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6803 assert(VM_Version::supports_evex(), "");
6804 assert(dst != xnoreg, "sanity");
6805 InstructionMark im(this);
6806 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6808 // swap src<->dst for encoding
6809 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6810 emit_int8(0x79);
6811 emit_operand(dst, src);
6812 }
6813
6814 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6815 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6816 assert(VM_Version::supports_evex(), "");
6817 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6818 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6819 emit_int8(0x58);
6820 emit_int8((unsigned char)(0xC0 | encode));
6821 }
6822
6823 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6824 assert(VM_Version::supports_evex(), "");
6825 assert(dst != xnoreg, "sanity");
6826 InstructionMark im(this);
6827 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6828 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6829 // swap src<->dst for encoding
6830 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6831 emit_int8(0x58);
6832 emit_operand(dst, src);
6833 }
6834
6835 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6836 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6837 assert(VM_Version::supports_evex(), "");
6838 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6839 attributes.set_rex_vex_w_reverted();
6840 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6841 emit_int8(0x59);
6842 emit_int8((unsigned char)(0xC0 | encode));
6843 }
6844
6845 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6846 assert(VM_Version::supports_evex(), "");
6847 assert(dst != xnoreg, "sanity");
6848 InstructionMark im(this);
6849 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6850 attributes.set_rex_vex_w_reverted();
6851 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6852 // swap src<->dst for encoding
6853 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6854 emit_int8(0x59);
6855 emit_operand(dst, src);
6856 }
6857 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
6858 assert(vector_len != Assembler::AVX_128bit, "");
6859 assert(VM_Version::supports_avx512dq(), "");
6860 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6861 attributes.set_rex_vex_w_reverted();
6862 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6863 emit_int8(0x5A);
6864 emit_int8((unsigned char)(0xC0 | encode));
6865 }
6866
6867 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
6868 assert(vector_len != Assembler::AVX_128bit, "");
6869 assert(VM_Version::supports_avx512dq(), "");
6870 assert(dst != xnoreg, "sanity");
6871 InstructionMark im(this);
6872 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6873 attributes.set_rex_vex_w_reverted();
6874 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
6875 // swap src<->dst for encoding
6876 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6877 emit_int8(0x5A);
6878 emit_operand(dst, src);
6879 }
6880
6881 // scalar single/double precision replicate
6882
6883 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6884 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6885 assert(VM_Version::supports_evex(), "");
6886 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6887 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6888 emit_int8(0x18);
6889 emit_int8((unsigned char)(0xC0 | encode));
6890 }
6891
6892 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6893 assert(VM_Version::supports_evex(), "");
6894 assert(dst != xnoreg, "sanity");
6895 InstructionMark im(this);
6896 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6897 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6898 // swap src<->dst for encoding
6899 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6900 emit_int8(0x18);
6901 emit_operand(dst, src);
6902 }
6903
6904 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6905 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6906 assert(VM_Version::supports_evex(), "");
6907 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6908 attributes.set_rex_vex_w_reverted();
6909 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6910 emit_int8(0x19);
6911 emit_int8((unsigned char)(0xC0 | encode));
6912 }
6913
6914 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6915 assert(VM_Version::supports_evex(), "");
6916 assert(dst != xnoreg, "sanity");
6917 InstructionMark im(this);
6918 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6919 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6920 attributes.set_rex_vex_w_reverted();
6921 // swap src<->dst for encoding
6922 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6923 emit_int8(0x19);
6924 emit_operand(dst, src);
6925 }
6926
6927
6928 // gpr source broadcast forms
6929
6930 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6931 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6932 assert(VM_Version::supports_evex(), "");
6933 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6934 attributes.set_is_evex_instruction();
6935 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6936 emit_int8(0x7A);
6937 emit_int8((unsigned char)(0xC0 | encode));
6938 }
6939
6940 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6941 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6942 assert(VM_Version::supports_evex(), "");
6943 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6944 attributes.set_is_evex_instruction();
6945 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6946 emit_int8(0x7B);
6947 emit_int8((unsigned char)(0xC0 | encode));
6948 }
6949
6950 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6951 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6952 assert(VM_Version::supports_evex(), "");
6953 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6954 attributes.set_is_evex_instruction();
6955 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6956 emit_int8(0x7C);
6957 emit_int8((unsigned char)(0xC0 | encode));
6958 }
6959
6960 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6961 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6962 assert(VM_Version::supports_evex(), "");
6963 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6964 attributes.set_is_evex_instruction();
6965 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6966 emit_int8(0x7C);
6967 emit_int8((unsigned char)(0xC0 | encode));
6968 }
6969
6970 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
6971 assert(VM_Version::supports_evex(), "");
6972 assert(dst != xnoreg, "sanity");
6973 InstructionMark im(this);
6974 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6975 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6976 attributes.reset_is_clear_context();
6977 attributes.set_embedded_opmask_register_specifier(mask);
6978 attributes.set_is_evex_instruction();
6979 // swap src<->dst for encoding
6980 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6981 emit_int8((unsigned char)0x90);
6982 emit_operand(dst, src);
6983 }
6984
6985 // Carry-Less Multiplication Quadword
6986 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6987 assert(VM_Version::supports_clmul(), "");
6988 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6989 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6990 emit_int8(0x44);
6991 emit_int8((unsigned char)(0xC0 | encode));
6992 emit_int8((unsigned char)mask);
6993 }
6994
6995 // Carry-Less Multiplication Quadword
6996 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6997 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6998 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6999 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7000 emit_int8(0x44);
7001 emit_int8((unsigned char)(0xC0 | encode));
7002 emit_int8((unsigned char)mask);
7003 }
7004
7005 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
7006 assert(VM_Version::supports_vpclmulqdq(), "Requires vector carryless multiplication support");
7007 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7008 attributes.set_is_evex_instruction();
7009 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7010 emit_int8(0x44);
7011 emit_int8((unsigned char)(0xC0 | encode));
7012 emit_int8((unsigned char)mask);
7013 }
7014
7015 void Assembler::vzeroupper() {
7016 if (VM_Version::supports_vzeroupper()) {
7017 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7018 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7019 emit_int8(0x77);
7020 }
7021 }
7022
7023 #ifndef _LP64
7024 // 32bit only pieces of the assembler
7025
7026 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7027 // NO PREFIX AS NEVER 64BIT
7028 InstructionMark im(this);
7029 emit_int8((unsigned char)0x81);
7030 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7031 emit_data(imm32, rspec, 0);
7032 }
7033
7034 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7035 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7036 InstructionMark im(this);
7037 emit_int8((unsigned char)0x81);
7038 emit_operand(rdi, src1);
7039 emit_data(imm32, rspec, 0);
7040 }
7041
7042 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7043 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7044 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7045 void Assembler::cmpxchg8(Address adr) {
7046 InstructionMark im(this);
7047 emit_int8(0x0F);
7048 emit_int8((unsigned char)0xC7);
7049 emit_operand(rcx, adr);
7050 }
7051
7052 void Assembler::decl(Register dst) {
7053 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7054 emit_int8(0x48 | dst->encoding());
7055 }
7056
7057 #endif // _LP64
7058
7059 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7060
7061 void Assembler::fabs() {
7062 emit_int8((unsigned char)0xD9);
7063 emit_int8((unsigned char)0xE1);
7064 }
7065
7066 void Assembler::fadd(int i) {
7067 emit_farith(0xD8, 0xC0, i);
7068 }
7069
7070 void Assembler::fadd_d(Address src) {
7071 InstructionMark im(this);
7072 emit_int8((unsigned char)0xDC);
7073 emit_operand32(rax, src);
7074 }
7075
7076 void Assembler::fadd_s(Address src) {
7077 InstructionMark im(this);
7078 emit_int8((unsigned char)0xD8);
7079 emit_operand32(rax, src);
7080 }
7081
7082 void Assembler::fadda(int i) {
7083 emit_farith(0xDC, 0xC0, i);
7084 }
7085
7086 void Assembler::faddp(int i) {
7087 emit_farith(0xDE, 0xC0, i);
7088 }
7089
7090 void Assembler::fchs() {
7091 emit_int8((unsigned char)0xD9);
7092 emit_int8((unsigned char)0xE0);
7093 }
7094
7095 void Assembler::fcom(int i) {
7096 emit_farith(0xD8, 0xD0, i);
7097 }
7098
7099 void Assembler::fcomp(int i) {
7100 emit_farith(0xD8, 0xD8, i);
7101 }
7102
7103 void Assembler::fcomp_d(Address src) {
7104 InstructionMark im(this);
7105 emit_int8((unsigned char)0xDC);
7106 emit_operand32(rbx, src);
7107 }
7108
7109 void Assembler::fcomp_s(Address src) {
7110 InstructionMark im(this);
7111 emit_int8((unsigned char)0xD8);
7112 emit_operand32(rbx, src);
7113 }
7114
7115 void Assembler::fcompp() {
7116 emit_int8((unsigned char)0xDE);
7117 emit_int8((unsigned char)0xD9);
7118 }
7119
7120 void Assembler::fcos() {
7121 emit_int8((unsigned char)0xD9);
7122 emit_int8((unsigned char)0xFF);
7123 }
7124
7125 void Assembler::fdecstp() {
7126 emit_int8((unsigned char)0xD9);
7127 emit_int8((unsigned char)0xF6);
7128 }
7129
7130 void Assembler::fdiv(int i) {
7131 emit_farith(0xD8, 0xF0, i);
7132 }
7133
7134 void Assembler::fdiv_d(Address src) {
7135 InstructionMark im(this);
7136 emit_int8((unsigned char)0xDC);
7137 emit_operand32(rsi, src);
7138 }
7139
7140 void Assembler::fdiv_s(Address src) {
7141 InstructionMark im(this);
7142 emit_int8((unsigned char)0xD8);
7143 emit_operand32(rsi, src);
7144 }
7145
7146 void Assembler::fdiva(int i) {
7147 emit_farith(0xDC, 0xF8, i);
7148 }
7149
7150 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7151 // is erroneous for some of the floating-point instructions below.
7152
7153 void Assembler::fdivp(int i) {
7154 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7155 }
7156
7157 void Assembler::fdivr(int i) {
7158 emit_farith(0xD8, 0xF8, i);
7159 }
7160
7161 void Assembler::fdivr_d(Address src) {
7162 InstructionMark im(this);
7163 emit_int8((unsigned char)0xDC);
7164 emit_operand32(rdi, src);
7165 }
7166
7167 void Assembler::fdivr_s(Address src) {
7168 InstructionMark im(this);
7169 emit_int8((unsigned char)0xD8);
7170 emit_operand32(rdi, src);
7171 }
7172
7173 void Assembler::fdivra(int i) {
7174 emit_farith(0xDC, 0xF0, i);
7175 }
7176
7177 void Assembler::fdivrp(int i) {
7178 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7179 }
7180
7181 void Assembler::ffree(int i) {
7182 emit_farith(0xDD, 0xC0, i);
7183 }
7184
7185 void Assembler::fild_d(Address adr) {
7186 InstructionMark im(this);
7187 emit_int8((unsigned char)0xDF);
7188 emit_operand32(rbp, adr);
7189 }
7190
7191 void Assembler::fild_s(Address adr) {
7192 InstructionMark im(this);
7193 emit_int8((unsigned char)0xDB);
7194 emit_operand32(rax, adr);
7195 }
7196
7197 void Assembler::fincstp() {
7198 emit_int8((unsigned char)0xD9);
7199 emit_int8((unsigned char)0xF7);
7200 }
7201
7202 void Assembler::finit() {
7203 emit_int8((unsigned char)0x9B);
7204 emit_int8((unsigned char)0xDB);
7205 emit_int8((unsigned char)0xE3);
7206 }
7207
7208 void Assembler::fist_s(Address adr) {
7209 InstructionMark im(this);
7210 emit_int8((unsigned char)0xDB);
7211 emit_operand32(rdx, adr);
7212 }
7213
7214 void Assembler::fistp_d(Address adr) {
7215 InstructionMark im(this);
7216 emit_int8((unsigned char)0xDF);
7217 emit_operand32(rdi, adr);
7218 }
7219
7220 void Assembler::fistp_s(Address adr) {
7221 InstructionMark im(this);
7222 emit_int8((unsigned char)0xDB);
7223 emit_operand32(rbx, adr);
7224 }
7225
7226 void Assembler::fld1() {
7227 emit_int8((unsigned char)0xD9);
7228 emit_int8((unsigned char)0xE8);
7229 }
7230
7231 void Assembler::fld_d(Address adr) {
7232 InstructionMark im(this);
7233 emit_int8((unsigned char)0xDD);
7234 emit_operand32(rax, adr);
7235 }
7236
7237 void Assembler::fld_s(Address adr) {
7238 InstructionMark im(this);
7239 emit_int8((unsigned char)0xD9);
7240 emit_operand32(rax, adr);
7241 }
7242
7243
7244 void Assembler::fld_s(int index) {
7245 emit_farith(0xD9, 0xC0, index);
7246 }
7247
7248 void Assembler::fld_x(Address adr) {
7249 InstructionMark im(this);
7250 emit_int8((unsigned char)0xDB);
7251 emit_operand32(rbp, adr);
7252 }
7253
7254 void Assembler::fldcw(Address src) {
7255 InstructionMark im(this);
7256 emit_int8((unsigned char)0xD9);
7257 emit_operand32(rbp, src);
7258 }
7259
7260 void Assembler::fldenv(Address src) {
7261 InstructionMark im(this);
7262 emit_int8((unsigned char)0xD9);
7263 emit_operand32(rsp, src);
7264 }
7265
7266 void Assembler::fldlg2() {
7267 emit_int8((unsigned char)0xD9);
7268 emit_int8((unsigned char)0xEC);
7269 }
7270
7271 void Assembler::fldln2() {
7272 emit_int8((unsigned char)0xD9);
7273 emit_int8((unsigned char)0xED);
7274 }
7275
7276 void Assembler::fldz() {
7277 emit_int8((unsigned char)0xD9);
7278 emit_int8((unsigned char)0xEE);
7279 }
7280
7281 void Assembler::flog() {
7282 fldln2();
7283 fxch();
7284 fyl2x();
7285 }
7286
7287 void Assembler::flog10() {
7288 fldlg2();
7289 fxch();
7290 fyl2x();
7291 }
7292
7293 void Assembler::fmul(int i) {
7294 emit_farith(0xD8, 0xC8, i);
7295 }
7296
7297 void Assembler::fmul_d(Address src) {
7298 InstructionMark im(this);
7299 emit_int8((unsigned char)0xDC);
7300 emit_operand32(rcx, src);
7301 }
7302
7303 void Assembler::fmul_s(Address src) {
7304 InstructionMark im(this);
7305 emit_int8((unsigned char)0xD8);
7306 emit_operand32(rcx, src);
7307 }
7308
7309 void Assembler::fmula(int i) {
7310 emit_farith(0xDC, 0xC8, i);
7311 }
7312
7313 void Assembler::fmulp(int i) {
7314 emit_farith(0xDE, 0xC8, i);
7315 }
7316
7317 void Assembler::fnsave(Address dst) {
7318 InstructionMark im(this);
7319 emit_int8((unsigned char)0xDD);
7320 emit_operand32(rsi, dst);
7321 }
7322
7323 void Assembler::fnstcw(Address src) {
7324 InstructionMark im(this);
7325 emit_int8((unsigned char)0x9B);
7326 emit_int8((unsigned char)0xD9);
7327 emit_operand32(rdi, src);
7328 }
7329
7330 void Assembler::fnstsw_ax() {
7331 emit_int8((unsigned char)0xDF);
7332 emit_int8((unsigned char)0xE0);
7333 }
7334
7335 void Assembler::fprem() {
7336 emit_int8((unsigned char)0xD9);
7337 emit_int8((unsigned char)0xF8);
7338 }
7339
7340 void Assembler::fprem1() {
7341 emit_int8((unsigned char)0xD9);
7342 emit_int8((unsigned char)0xF5);
7343 }
7344
7345 void Assembler::frstor(Address src) {
7346 InstructionMark im(this);
7347 emit_int8((unsigned char)0xDD);
7348 emit_operand32(rsp, src);
7349 }
7350
7351 void Assembler::fsin() {
7352 emit_int8((unsigned char)0xD9);
7353 emit_int8((unsigned char)0xFE);
7354 }
7355
7356 void Assembler::fsqrt() {
7357 emit_int8((unsigned char)0xD9);
7358 emit_int8((unsigned char)0xFA);
7359 }
7360
7361 void Assembler::fst_d(Address adr) {
7362 InstructionMark im(this);
7363 emit_int8((unsigned char)0xDD);
7364 emit_operand32(rdx, adr);
7365 }
7366
7367 void Assembler::fst_s(Address adr) {
7368 InstructionMark im(this);
7369 emit_int8((unsigned char)0xD9);
7370 emit_operand32(rdx, adr);
7371 }
7372
7373 void Assembler::fstp_d(Address adr) {
7374 InstructionMark im(this);
7375 emit_int8((unsigned char)0xDD);
7376 emit_operand32(rbx, adr);
7377 }
7378
7379 void Assembler::fstp_d(int index) {
7380 emit_farith(0xDD, 0xD8, index);
7381 }
7382
7383 void Assembler::fstp_s(Address adr) {
7384 InstructionMark im(this);
7385 emit_int8((unsigned char)0xD9);
7386 emit_operand32(rbx, adr);
7387 }
7388
7389 void Assembler::fstp_x(Address adr) {
7390 InstructionMark im(this);
7391 emit_int8((unsigned char)0xDB);
7392 emit_operand32(rdi, adr);
7393 }
7394
7395 void Assembler::fsub(int i) {
7396 emit_farith(0xD8, 0xE0, i);
7397 }
7398
7399 void Assembler::fsub_d(Address src) {
7400 InstructionMark im(this);
7401 emit_int8((unsigned char)0xDC);
7402 emit_operand32(rsp, src);
7403 }
7404
7405 void Assembler::fsub_s(Address src) {
7406 InstructionMark im(this);
7407 emit_int8((unsigned char)0xD8);
7408 emit_operand32(rsp, src);
7409 }
7410
7411 void Assembler::fsuba(int i) {
7412 emit_farith(0xDC, 0xE8, i);
7413 }
7414
7415 void Assembler::fsubp(int i) {
7416 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7417 }
7418
7419 void Assembler::fsubr(int i) {
7420 emit_farith(0xD8, 0xE8, i);
7421 }
7422
7423 void Assembler::fsubr_d(Address src) {
7424 InstructionMark im(this);
7425 emit_int8((unsigned char)0xDC);
7426 emit_operand32(rbp, src);
7427 }
7428
7429 void Assembler::fsubr_s(Address src) {
7430 InstructionMark im(this);
7431 emit_int8((unsigned char)0xD8);
7432 emit_operand32(rbp, src);
7433 }
7434
7435 void Assembler::fsubra(int i) {
7436 emit_farith(0xDC, 0xE0, i);
7437 }
7438
7439 void Assembler::fsubrp(int i) {
7440 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7441 }
7442
7443 void Assembler::ftan() {
7444 emit_int8((unsigned char)0xD9);
7445 emit_int8((unsigned char)0xF2);
7446 emit_int8((unsigned char)0xDD);
7447 emit_int8((unsigned char)0xD8);
7448 }
7449
7450 void Assembler::ftst() {
7451 emit_int8((unsigned char)0xD9);
7452 emit_int8((unsigned char)0xE4);
7453 }
7454
7455 void Assembler::fucomi(int i) {
7456 // make sure the instruction is supported (introduced for P6, together with cmov)
7457 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7458 emit_farith(0xDB, 0xE8, i);
7459 }
7460
7461 void Assembler::fucomip(int i) {
7462 // make sure the instruction is supported (introduced for P6, together with cmov)
7463 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7464 emit_farith(0xDF, 0xE8, i);
7465 }
7466
7467 void Assembler::fwait() {
7468 emit_int8((unsigned char)0x9B);
7469 }
7470
7471 void Assembler::fxch(int i) {
7472 emit_farith(0xD9, 0xC8, i);
7473 }
7474
7475 void Assembler::fyl2x() {
7476 emit_int8((unsigned char)0xD9);
7477 emit_int8((unsigned char)0xF1);
7478 }
7479
7480 void Assembler::frndint() {
7481 emit_int8((unsigned char)0xD9);
7482 emit_int8((unsigned char)0xFC);
7483 }
7484
7485 void Assembler::f2xm1() {
7486 emit_int8((unsigned char)0xD9);
7487 emit_int8((unsigned char)0xF0);
7488 }
7489
7490 void Assembler::fldl2e() {
7491 emit_int8((unsigned char)0xD9);
7492 emit_int8((unsigned char)0xEA);
7493 }
7494
7495 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7496 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7497 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7498 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7499
7500 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7501 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7502 if (pre > 0) {
7503 emit_int8(simd_pre[pre]);
7504 }
7505 if (rex_w) {
7506 prefixq(adr, xreg);
7507 } else {
7508 prefix(adr, xreg);
7509 }
7510 if (opc > 0) {
7511 emit_int8(0x0F);
7512 int opc2 = simd_opc[opc];
7513 if (opc2 > 0) {
7514 emit_int8(opc2);
7515 }
7516 }
7517 }
7518
7519 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7520 if (pre > 0) {
7521 emit_int8(simd_pre[pre]);
7522 }
7523 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7524 if (opc > 0) {
7525 emit_int8(0x0F);
7526 int opc2 = simd_opc[opc];
7527 if (opc2 > 0) {
7528 emit_int8(opc2);
7529 }
7530 }
7531 return encode;
7532 }
7533
7534
7535 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7536 int vector_len = _attributes->get_vector_len();
7537 bool vex_w = _attributes->is_rex_vex_w();
7538 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7539 prefix(VEX_3bytes);
7540
7541 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7542 byte1 = (~byte1) & 0xE0;
7543 byte1 |= opc;
7544 emit_int8(byte1);
7545
7546 int byte2 = ((~nds_enc) & 0xf) << 3;
7547 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7548 emit_int8(byte2);
7549 } else {
7550 prefix(VEX_2bytes);
7551
7552 int byte1 = vex_r ? VEX_R : 0;
7553 byte1 = (~byte1) & 0x80;
7554 byte1 |= ((~nds_enc) & 0xf) << 3;
7555 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7556 emit_int8(byte1);
7557 }
7558 }
7559
7560 // This is a 4 byte encoding
7561 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7562 // EVEX 0x62 prefix
7563 prefix(EVEX_4bytes);
7564 bool vex_w = _attributes->is_rex_vex_w();
7565 int evex_encoding = (vex_w ? VEX_W : 0);
7566 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7567 _attributes->set_evex_encoding(evex_encoding);
7568
7569 // P0: byte 2, initialized to RXBR`00mm
7570 // instead of not'd
7571 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7572 byte2 = (~byte2) & 0xF0;
7573 // confine opc opcode extensions in mm bits to lower two bits
7574 // of form {0F, 0F_38, 0F_3A}
7575 byte2 |= opc;
7576 emit_int8(byte2);
7577
7578 // P1: byte 3 as Wvvvv1pp
7579 int byte3 = ((~nds_enc) & 0xf) << 3;
7580 // p[10] is always 1
7581 byte3 |= EVEX_F;
7582 byte3 |= (vex_w & 1) << 7;
7583 // confine pre opcode extensions in pp bits to lower two bits
7584 // of form {66, F3, F2}
7585 byte3 |= pre;
7586 emit_int8(byte3);
7587
7588 // P2: byte 4 as zL'Lbv'aaa
7589 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
7590 int byte4 = (_attributes->is_no_reg_mask()) ?
7591 0 :
7592 _attributes->get_embedded_opmask_register_specifier();
7593 // EVEX.v` for extending EVEX.vvvv or VIDX
7594 byte4 |= (evex_v ? 0: EVEX_V);
7595 // third EXEC.b for broadcast actions
7596 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
7597 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
7598 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
7599 // last is EVEX.z for zero/merge actions
7600 if (_attributes->is_no_reg_mask() == false) {
7601 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
7602 }
7603 emit_int8(byte4);
7604 }
7605
7606 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7607 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
7608 bool vex_b = adr.base_needs_rex();
7609 bool vex_x;
7610 if (adr.isxmmindex()) {
7611 vex_x = adr.xmmindex_needs_rex();
7612 } else {
7613 vex_x = adr.index_needs_rex();
7614 }
7615 set_attributes(attributes);
7616 attributes->set_current_assembler(this);
7617
7618 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7619 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7620 switch (attributes->get_vector_len()) {
7621 case AVX_128bit:
7622 case AVX_256bit:
7623 attributes->set_is_legacy_mode();
7624 break;
7625 }
7626 }
7627
7628 // For pure EVEX check and see if this instruction
7629 // is allowed in legacy mode and has resources which will
7630 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7631 // else that field is set when we encode to EVEX
7632 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7633 !_is_managed && !attributes->is_evex_instruction()) {
7634 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7635 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7636 if (check_register_bank) {
7637 // check nds_enc and xreg_enc for upper bank usage
7638 if (nds_enc < 16 && xreg_enc < 16) {
7639 attributes->set_is_legacy_mode();
7640 }
7641 } else {
7642 attributes->set_is_legacy_mode();
7643 }
7644 }
7645 }
7646
7647 _is_managed = false;
7648 if (UseAVX > 2 && !attributes->is_legacy_mode())
7649 {
7650 bool evex_r = (xreg_enc >= 16);
7651 bool evex_v;
7652 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
7653 if (adr.isxmmindex()) {
7654 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
7655 } else {
7656 evex_v = (nds_enc >= 16);
7657 }
7658 attributes->set_is_evex_instruction();
7659 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7660 } else {
7661 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7662 attributes->set_rex_vex_w(false);
7663 }
7664 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7665 }
7666 }
7667
7668 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
7669 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
7670 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
7671 bool vex_x = false;
7672 set_attributes(attributes);
7673 attributes->set_current_assembler(this);
7674 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
7675
7676 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
7677 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
7678 switch (attributes->get_vector_len()) {
7679 case AVX_128bit:
7680 case AVX_256bit:
7681 if (check_register_bank) {
7682 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
7683 // up propagate arithmetic instructions to meet RA requirements
7684 attributes->set_vector_len(AVX_512bit);
7685 } else {
7686 attributes->set_is_legacy_mode();
7687 }
7688 } else {
7689 attributes->set_is_legacy_mode();
7690 }
7691 break;
7692 }
7693 }
7694
7695 // For pure EVEX check and see if this instruction
7696 // is allowed in legacy mode and has resources which will
7697 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
7698 // else that field is set when we encode to EVEX
7699 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
7700 !_is_managed && !attributes->is_evex_instruction()) {
7701 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
7702 if (check_register_bank) {
7703 // check dst_enc, nds_enc and src_enc for upper bank usage
7704 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
7705 attributes->set_is_legacy_mode();
7706 }
7707 } else {
7708 attributes->set_is_legacy_mode();
7709 }
7710 }
7711 }
7712
7713 _is_managed = false;
7714 if (UseAVX > 2 && !attributes->is_legacy_mode())
7715 {
7716 bool evex_r = (dst_enc >= 16);
7717 bool evex_v = (nds_enc >= 16);
7718 // can use vex_x as bank extender on rm encoding
7719 vex_x = (src_enc >= 16);
7720 attributes->set_is_evex_instruction();
7721 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
7722 } else {
7723 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
7724 attributes->set_rex_vex_w(false);
7725 }
7726 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
7727 }
7728
7729 // return modrm byte components for operands
7730 return (((dst_enc & 7) << 3) | (src_enc & 7));
7731 }
7732
7733
7734 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
7735 VexOpcode opc, InstructionAttr *attributes) {
7736 if (UseAVX > 0) {
7737 int xreg_enc = xreg->encoding();
7738 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7739 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
7740 } else {
7741 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
7742 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
7743 }
7744 }
7745
7746 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
7747 VexOpcode opc, InstructionAttr *attributes) {
7748 int dst_enc = dst->encoding();
7749 int src_enc = src->encoding();
7750 if (UseAVX > 0) {
7751 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
7752 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
7753 } else {
7754 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
7755 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
7756 }
7757 }
7758
7759 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7760 assert(VM_Version::supports_avx(), "");
7761 assert(!VM_Version::supports_evex(), "");
7762 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7763 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7764 emit_int8((unsigned char)0xC2);
7765 emit_int8((unsigned char)(0xC0 | encode));
7766 emit_int8((unsigned char)(0xF & cop));
7767 }
7768
7769 void Assembler::blendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7770 assert(VM_Version::supports_avx(), "");
7771 assert(!VM_Version::supports_evex(), "");
7772 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7773 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7774 emit_int8((unsigned char)0x4B);
7775 emit_int8((unsigned char)(0xC0 | encode));
7776 int src2_enc = src2->encoding();
7777 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7778 }
7779
7780 void Assembler::cmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
7781 assert(VM_Version::supports_avx(), "");
7782 assert(!VM_Version::supports_evex(), "");
7783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7784 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7785 emit_int8((unsigned char)0xC2);
7786 emit_int8((unsigned char)(0xC0 | encode));
7787 emit_int8((unsigned char)(0xF & cop));
7788 }
7789
7790 void Assembler::blendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
7791 assert(VM_Version::supports_avx(), "");
7792 assert(!VM_Version::supports_evex(), "");
7793 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7794 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7795 emit_int8((unsigned char)0x4A);
7796 emit_int8((unsigned char)(0xC0 | encode));
7797 int src2_enc = src2->encoding();
7798 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
7799 }
7800
7801 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
7802 assert(VM_Version::supports_avx2(), "");
7803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7804 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7805 emit_int8((unsigned char)0x02);
7806 emit_int8((unsigned char)(0xC0 | encode));
7807 emit_int8((unsigned char)imm8);
7808 }
7809
7810 void Assembler::shlxl(Register dst, Register src1, Register src2) {
7811 assert(VM_Version::supports_bmi2(), "");
7812 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7813 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7814 emit_int8((unsigned char)0xF7);
7815 emit_int8((unsigned char)(0xC0 | encode));
7816 }
7817
7818 void Assembler::shlxq(Register dst, Register src1, Register src2) {
7819 assert(VM_Version::supports_bmi2(), "");
7820 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7821 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7822 emit_int8((unsigned char)0xF7);
7823 emit_int8((unsigned char)(0xC0 | encode));
7824 }
7825
7826 #ifndef _LP64
7827
7828 void Assembler::incl(Register dst) {
7829 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7830 emit_int8(0x40 | dst->encoding());
7831 }
7832
7833 void Assembler::lea(Register dst, Address src) {
7834 leal(dst, src);
7835 }
7836
7837 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7838 InstructionMark im(this);
7839 emit_int8((unsigned char)0xC7);
7840 emit_operand(rax, dst);
7841 emit_data((int)imm32, rspec, 0);
7842 }
7843
7844 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7845 InstructionMark im(this);
7846 int encode = prefix_and_encode(dst->encoding());
7847 emit_int8((unsigned char)(0xB8 | encode));
7848 emit_data((int)imm32, rspec, 0);
7849 }
7850
7851 void Assembler::popa() { // 32bit
7852 emit_int8(0x61);
7853 }
7854
7855 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7856 InstructionMark im(this);
7857 emit_int8(0x68);
7858 emit_data(imm32, rspec, 0);
7859 }
7860
7861 void Assembler::pusha() { // 32bit
7862 emit_int8(0x60);
7863 }
7864
7865 void Assembler::set_byte_if_not_zero(Register dst) {
7866 emit_int8(0x0F);
7867 emit_int8((unsigned char)0x95);
7868 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7869 }
7870
7871 void Assembler::shldl(Register dst, Register src) {
7872 emit_int8(0x0F);
7873 emit_int8((unsigned char)0xA5);
7874 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7875 }
7876
7877 // 0F A4 / r ib
7878 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7879 emit_int8(0x0F);
7880 emit_int8((unsigned char)0xA4);
7881 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7882 emit_int8(imm8);
7883 }
7884
7885 void Assembler::shrdl(Register dst, Register src) {
7886 emit_int8(0x0F);
7887 emit_int8((unsigned char)0xAD);
7888 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7889 }
7890
7891 #else // LP64
7892
7893 void Assembler::set_byte_if_not_zero(Register dst) {
7894 int enc = prefix_and_encode(dst->encoding(), true);
7895 emit_int8(0x0F);
7896 emit_int8((unsigned char)0x95);
7897 emit_int8((unsigned char)(0xE0 | enc));
7898 }
7899
7900 // 64bit only pieces of the assembler
7901 // This should only be used by 64bit instructions that can use rip-relative
7902 // it cannot be used by instructions that want an immediate value.
7903
7904 bool Assembler::reachable(AddressLiteral adr) {
7905 int64_t disp;
7906 // None will force a 64bit literal to the code stream. Likely a placeholder
7907 // for something that will be patched later and we need to certain it will
7908 // always be reachable.
7909 if (adr.reloc() == relocInfo::none) {
7910 return false;
7911 }
7912 if (adr.reloc() == relocInfo::internal_word_type) {
7913 // This should be rip relative and easily reachable.
7914 return true;
7915 }
7916 if (adr.reloc() == relocInfo::virtual_call_type ||
7917 adr.reloc() == relocInfo::opt_virtual_call_type ||
7918 adr.reloc() == relocInfo::static_call_type ||
7919 adr.reloc() == relocInfo::static_stub_type ) {
7920 // This should be rip relative within the code cache and easily
7921 // reachable until we get huge code caches. (At which point
7922 // ic code is going to have issues).
7923 return true;
7924 }
7925 if (adr.reloc() != relocInfo::external_word_type &&
7926 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7927 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7928 adr.reloc() != relocInfo::runtime_call_type ) {
7929 return false;
7930 }
7931
7932 // Stress the correction code
7933 if (ForceUnreachable) {
7934 // Must be runtimecall reloc, see if it is in the codecache
7935 // Flipping stuff in the codecache to be unreachable causes issues
7936 // with things like inline caches where the additional instructions
7937 // are not handled.
7938 if (CodeCache::find_blob(adr._target) == NULL) {
7939 return false;
7940 }
7941 }
7942 // For external_word_type/runtime_call_type if it is reachable from where we
7943 // are now (possibly a temp buffer) and where we might end up
7944 // anywhere in the codeCache then we are always reachable.
7945 // This would have to change if we ever save/restore shared code
7946 // to be more pessimistic.
7947 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7948 if (!is_simm32(disp)) return false;
7949 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7950 if (!is_simm32(disp)) return false;
7951
7952 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7953
7954 // Because rip relative is a disp + address_of_next_instruction and we
7955 // don't know the value of address_of_next_instruction we apply a fudge factor
7956 // to make sure we will be ok no matter the size of the instruction we get placed into.
7957 // We don't have to fudge the checks above here because they are already worst case.
7958
7959 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7960 // + 4 because better safe than sorry.
7961 const int fudge = 12 + 4;
7962 if (disp < 0) {
7963 disp -= fudge;
7964 } else {
7965 disp += fudge;
7966 }
7967 return is_simm32(disp);
7968 }
7969
7970 // Check if the polling page is not reachable from the code cache using rip-relative
7971 // addressing.
7972 bool Assembler::is_polling_page_far() {
7973 intptr_t addr = (intptr_t)os::get_polling_page();
7974 return ForceUnreachable ||
7975 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7976 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7977 }
7978
7979 void Assembler::emit_data64(jlong data,
7980 relocInfo::relocType rtype,
7981 int format) {
7982 if (rtype == relocInfo::none) {
7983 emit_int64(data);
7984 } else {
7985 emit_data64(data, Relocation::spec_simple(rtype), format);
7986 }
7987 }
7988
7989 void Assembler::emit_data64(jlong data,
7990 RelocationHolder const& rspec,
7991 int format) {
7992 assert(imm_operand == 0, "default format must be immediate in this file");
7993 assert(imm_operand == format, "must be immediate");
7994 assert(inst_mark() != NULL, "must be inside InstructionMark");
7995 // Do not use AbstractAssembler::relocate, which is not intended for
7996 // embedded words. Instead, relocate to the enclosing instruction.
7997 code_section()->relocate(inst_mark(), rspec, format);
7998 #ifdef ASSERT
7999 check_relocation(rspec, format);
8000 #endif
8001 emit_int64(data);
8002 }
8003
8004 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
8005 if (reg_enc >= 8) {
8006 prefix(REX_B);
8007 reg_enc -= 8;
8008 } else if (byteinst && reg_enc >= 4) {
8009 prefix(REX);
8010 }
8011 return reg_enc;
8012 }
8013
8014 int Assembler::prefixq_and_encode(int reg_enc) {
8015 if (reg_enc < 8) {
8016 prefix(REX_W);
8017 } else {
8018 prefix(REX_WB);
8019 reg_enc -= 8;
8020 }
8021 return reg_enc;
8022 }
8023
8024 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8025 if (dst_enc < 8) {
8026 if (src_enc >= 8) {
8027 prefix(REX_B);
8028 src_enc -= 8;
8029 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8030 prefix(REX);
8031 }
8032 } else {
8033 if (src_enc < 8) {
8034 prefix(REX_R);
8035 } else {
8036 prefix(REX_RB);
8037 src_enc -= 8;
8038 }
8039 dst_enc -= 8;
8040 }
8041 return dst_enc << 3 | src_enc;
8042 }
8043
8044 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8045 if (dst_enc < 8) {
8046 if (src_enc < 8) {
8047 prefix(REX_W);
8048 } else {
8049 prefix(REX_WB);
8050 src_enc -= 8;
8051 }
8052 } else {
8053 if (src_enc < 8) {
8054 prefix(REX_WR);
8055 } else {
8056 prefix(REX_WRB);
8057 src_enc -= 8;
8058 }
8059 dst_enc -= 8;
8060 }
8061 return dst_enc << 3 | src_enc;
8062 }
8063
8064 void Assembler::prefix(Register reg) {
8065 if (reg->encoding() >= 8) {
8066 prefix(REX_B);
8067 }
8068 }
8069
8070 void Assembler::prefix(Register dst, Register src, Prefix p) {
8071 if (src->encoding() >= 8) {
8072 p = (Prefix)(p | REX_B);
8073 }
8074 if (dst->encoding() >= 8) {
8075 p = (Prefix)( p | REX_R);
8076 }
8077 if (p != Prefix_EMPTY) {
8078 // do not generate an empty prefix
8079 prefix(p);
8080 }
8081 }
8082
8083 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8084 if (adr.base_needs_rex()) {
8085 if (adr.index_needs_rex()) {
8086 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8087 } else {
8088 prefix(REX_B);
8089 }
8090 } else {
8091 if (adr.index_needs_rex()) {
8092 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8093 }
8094 }
8095 if (dst->encoding() >= 8) {
8096 p = (Prefix)(p | REX_R);
8097 }
8098 if (p != Prefix_EMPTY) {
8099 // do not generate an empty prefix
8100 prefix(p);
8101 }
8102 }
8103
8104 void Assembler::prefix(Address adr) {
8105 if (adr.base_needs_rex()) {
8106 if (adr.index_needs_rex()) {
8107 prefix(REX_XB);
8108 } else {
8109 prefix(REX_B);
8110 }
8111 } else {
8112 if (adr.index_needs_rex()) {
8113 prefix(REX_X);
8114 }
8115 }
8116 }
8117
8118 void Assembler::prefixq(Address adr) {
8119 if (adr.base_needs_rex()) {
8120 if (adr.index_needs_rex()) {
8121 prefix(REX_WXB);
8122 } else {
8123 prefix(REX_WB);
8124 }
8125 } else {
8126 if (adr.index_needs_rex()) {
8127 prefix(REX_WX);
8128 } else {
8129 prefix(REX_W);
8130 }
8131 }
8132 }
8133
8134
8135 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8136 if (reg->encoding() < 8) {
8137 if (adr.base_needs_rex()) {
8138 if (adr.index_needs_rex()) {
8139 prefix(REX_XB);
8140 } else {
8141 prefix(REX_B);
8142 }
8143 } else {
8144 if (adr.index_needs_rex()) {
8145 prefix(REX_X);
8146 } else if (byteinst && reg->encoding() >= 4 ) {
8147 prefix(REX);
8148 }
8149 }
8150 } else {
8151 if (adr.base_needs_rex()) {
8152 if (adr.index_needs_rex()) {
8153 prefix(REX_RXB);
8154 } else {
8155 prefix(REX_RB);
8156 }
8157 } else {
8158 if (adr.index_needs_rex()) {
8159 prefix(REX_RX);
8160 } else {
8161 prefix(REX_R);
8162 }
8163 }
8164 }
8165 }
8166
8167 void Assembler::prefixq(Address adr, Register src) {
8168 if (src->encoding() < 8) {
8169 if (adr.base_needs_rex()) {
8170 if (adr.index_needs_rex()) {
8171 prefix(REX_WXB);
8172 } else {
8173 prefix(REX_WB);
8174 }
8175 } else {
8176 if (adr.index_needs_rex()) {
8177 prefix(REX_WX);
8178 } else {
8179 prefix(REX_W);
8180 }
8181 }
8182 } else {
8183 if (adr.base_needs_rex()) {
8184 if (adr.index_needs_rex()) {
8185 prefix(REX_WRXB);
8186 } else {
8187 prefix(REX_WRB);
8188 }
8189 } else {
8190 if (adr.index_needs_rex()) {
8191 prefix(REX_WRX);
8192 } else {
8193 prefix(REX_WR);
8194 }
8195 }
8196 }
8197 }
8198
8199 void Assembler::prefix(Address adr, XMMRegister reg) {
8200 if (reg->encoding() < 8) {
8201 if (adr.base_needs_rex()) {
8202 if (adr.index_needs_rex()) {
8203 prefix(REX_XB);
8204 } else {
8205 prefix(REX_B);
8206 }
8207 } else {
8208 if (adr.index_needs_rex()) {
8209 prefix(REX_X);
8210 }
8211 }
8212 } else {
8213 if (adr.base_needs_rex()) {
8214 if (adr.index_needs_rex()) {
8215 prefix(REX_RXB);
8216 } else {
8217 prefix(REX_RB);
8218 }
8219 } else {
8220 if (adr.index_needs_rex()) {
8221 prefix(REX_RX);
8222 } else {
8223 prefix(REX_R);
8224 }
8225 }
8226 }
8227 }
8228
8229 void Assembler::prefixq(Address adr, XMMRegister src) {
8230 if (src->encoding() < 8) {
8231 if (adr.base_needs_rex()) {
8232 if (adr.index_needs_rex()) {
8233 prefix(REX_WXB);
8234 } else {
8235 prefix(REX_WB);
8236 }
8237 } else {
8238 if (adr.index_needs_rex()) {
8239 prefix(REX_WX);
8240 } else {
8241 prefix(REX_W);
8242 }
8243 }
8244 } else {
8245 if (adr.base_needs_rex()) {
8246 if (adr.index_needs_rex()) {
8247 prefix(REX_WRXB);
8248 } else {
8249 prefix(REX_WRB);
8250 }
8251 } else {
8252 if (adr.index_needs_rex()) {
8253 prefix(REX_WRX);
8254 } else {
8255 prefix(REX_WR);
8256 }
8257 }
8258 }
8259 }
8260
8261 void Assembler::adcq(Register dst, int32_t imm32) {
8262 (void) prefixq_and_encode(dst->encoding());
8263 emit_arith(0x81, 0xD0, dst, imm32);
8264 }
8265
8266 void Assembler::adcq(Register dst, Address src) {
8267 InstructionMark im(this);
8268 prefixq(src, dst);
8269 emit_int8(0x13);
8270 emit_operand(dst, src);
8271 }
8272
8273 void Assembler::adcq(Register dst, Register src) {
8274 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8275 emit_arith(0x13, 0xC0, dst, src);
8276 }
8277
8278 void Assembler::addq(Address dst, int32_t imm32) {
8279 InstructionMark im(this);
8280 prefixq(dst);
8281 emit_arith_operand(0x81, rax, dst,imm32);
8282 }
8283
8284 void Assembler::addq(Address dst, Register src) {
8285 InstructionMark im(this);
8286 prefixq(dst, src);
8287 emit_int8(0x01);
8288 emit_operand(src, dst);
8289 }
8290
8291 void Assembler::addq(Register dst, int32_t imm32) {
8292 (void) prefixq_and_encode(dst->encoding());
8293 emit_arith(0x81, 0xC0, dst, imm32);
8294 }
8295
8296 void Assembler::addq(Register dst, Address src) {
8297 InstructionMark im(this);
8298 prefixq(src, dst);
8299 emit_int8(0x03);
8300 emit_operand(dst, src);
8301 }
8302
8303 void Assembler::addq(Register dst, Register src) {
8304 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8305 emit_arith(0x03, 0xC0, dst, src);
8306 }
8307
8308 void Assembler::adcxq(Register dst, Register src) {
8309 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8310 emit_int8((unsigned char)0x66);
8311 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8312 emit_int8(0x0F);
8313 emit_int8(0x38);
8314 emit_int8((unsigned char)0xF6);
8315 emit_int8((unsigned char)(0xC0 | encode));
8316 }
8317
8318 void Assembler::adoxq(Register dst, Register src) {
8319 //assert(VM_Version::supports_adx(), "adx instructions not supported");
8320 emit_int8((unsigned char)0xF3);
8321 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8322 emit_int8(0x0F);
8323 emit_int8(0x38);
8324 emit_int8((unsigned char)0xF6);
8325 emit_int8((unsigned char)(0xC0 | encode));
8326 }
8327
8328 void Assembler::andq(Address dst, int32_t imm32) {
8329 InstructionMark im(this);
8330 prefixq(dst);
8331 emit_int8((unsigned char)0x81);
8332 emit_operand(rsp, dst, 4);
8333 emit_int32(imm32);
8334 }
8335
8336 void Assembler::andq(Register dst, int32_t imm32) {
8337 (void) prefixq_and_encode(dst->encoding());
8338 emit_arith(0x81, 0xE0, dst, imm32);
8339 }
8340
8341 void Assembler::andq(Register dst, Address src) {
8342 InstructionMark im(this);
8343 prefixq(src, dst);
8344 emit_int8(0x23);
8345 emit_operand(dst, src);
8346 }
8347
8348 void Assembler::andq(Register dst, Register src) {
8349 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8350 emit_arith(0x23, 0xC0, dst, src);
8351 }
8352
8353 void Assembler::andnq(Register dst, Register src1, Register src2) {
8354 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8355 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8356 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8357 emit_int8((unsigned char)0xF2);
8358 emit_int8((unsigned char)(0xC0 | encode));
8359 }
8360
8361 void Assembler::andnq(Register dst, Register src1, Address src2) {
8362 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8363 InstructionMark im(this);
8364 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8365 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8366 emit_int8((unsigned char)0xF2);
8367 emit_operand(dst, src2);
8368 }
8369
8370 void Assembler::bsfq(Register dst, Register src) {
8371 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8372 emit_int8(0x0F);
8373 emit_int8((unsigned char)0xBC);
8374 emit_int8((unsigned char)(0xC0 | encode));
8375 }
8376
8377 void Assembler::bsrq(Register dst, Register src) {
8378 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8379 emit_int8(0x0F);
8380 emit_int8((unsigned char)0xBD);
8381 emit_int8((unsigned char)(0xC0 | encode));
8382 }
8383
8384 void Assembler::bswapq(Register reg) {
8385 int encode = prefixq_and_encode(reg->encoding());
8386 emit_int8(0x0F);
8387 emit_int8((unsigned char)(0xC8 | encode));
8388 }
8389
8390 void Assembler::blsiq(Register dst, Register src) {
8391 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8392 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8393 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8394 emit_int8((unsigned char)0xF3);
8395 emit_int8((unsigned char)(0xC0 | encode));
8396 }
8397
8398 void Assembler::blsiq(Register dst, Address src) {
8399 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8400 InstructionMark im(this);
8401 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8402 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8403 emit_int8((unsigned char)0xF3);
8404 emit_operand(rbx, src);
8405 }
8406
8407 void Assembler::blsmskq(Register dst, Register src) {
8408 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8409 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8410 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8411 emit_int8((unsigned char)0xF3);
8412 emit_int8((unsigned char)(0xC0 | encode));
8413 }
8414
8415 void Assembler::blsmskq(Register dst, Address src) {
8416 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8417 InstructionMark im(this);
8418 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8419 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8420 emit_int8((unsigned char)0xF3);
8421 emit_operand(rdx, src);
8422 }
8423
8424 void Assembler::blsrq(Register dst, Register src) {
8425 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8426 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8427 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8428 emit_int8((unsigned char)0xF3);
8429 emit_int8((unsigned char)(0xC0 | encode));
8430 }
8431
8432 void Assembler::blsrq(Register dst, Address src) {
8433 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
8434 InstructionMark im(this);
8435 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8436 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
8437 emit_int8((unsigned char)0xF3);
8438 emit_operand(rcx, src);
8439 }
8440
8441 void Assembler::cdqq() {
8442 prefix(REX_W);
8443 emit_int8((unsigned char)0x99);
8444 }
8445
8446 void Assembler::clflush(Address adr) {
8447 prefix(adr);
8448 emit_int8(0x0F);
8449 emit_int8((unsigned char)0xAE);
8450 emit_operand(rdi, adr);
8451 }
8452
8453 void Assembler::cmovq(Condition cc, Register dst, Register src) {
8454 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8455 emit_int8(0x0F);
8456 emit_int8(0x40 | cc);
8457 emit_int8((unsigned char)(0xC0 | encode));
8458 }
8459
8460 void Assembler::cmovq(Condition cc, Register dst, Address src) {
8461 InstructionMark im(this);
8462 prefixq(src, dst);
8463 emit_int8(0x0F);
8464 emit_int8(0x40 | cc);
8465 emit_operand(dst, src);
8466 }
8467
8468 void Assembler::cmpq(Address dst, int32_t imm32) {
8469 InstructionMark im(this);
8470 prefixq(dst);
8471 emit_int8((unsigned char)0x81);
8472 emit_operand(rdi, dst, 4);
8473 emit_int32(imm32);
8474 }
8475
8476 void Assembler::cmpq(Register dst, int32_t imm32) {
8477 (void) prefixq_and_encode(dst->encoding());
8478 emit_arith(0x81, 0xF8, dst, imm32);
8479 }
8480
8481 void Assembler::cmpq(Address dst, Register src) {
8482 InstructionMark im(this);
8483 prefixq(dst, src);
8484 emit_int8(0x3B);
8485 emit_operand(src, dst);
8486 }
8487
8488 void Assembler::cmpq(Register dst, Register src) {
8489 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8490 emit_arith(0x3B, 0xC0, dst, src);
8491 }
8492
8493 void Assembler::cmpq(Register dst, Address src) {
8494 InstructionMark im(this);
8495 prefixq(src, dst);
8496 emit_int8(0x3B);
8497 emit_operand(dst, src);
8498 }
8499
8500 void Assembler::cmpxchgq(Register reg, Address adr) {
8501 InstructionMark im(this);
8502 prefixq(adr, reg);
8503 emit_int8(0x0F);
8504 emit_int8((unsigned char)0xB1);
8505 emit_operand(reg, adr);
8506 }
8507
8508 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
8509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8510 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8511 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8512 emit_int8(0x2A);
8513 emit_int8((unsigned char)(0xC0 | encode));
8514 }
8515
8516 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
8517 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8518 InstructionMark im(this);
8519 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8520 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8521 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8522 emit_int8(0x2A);
8523 emit_operand(dst, src);
8524 }
8525
8526 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
8527 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8528 InstructionMark im(this);
8529 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8530 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
8531 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8532 emit_int8(0x2A);
8533 emit_operand(dst, src);
8534 }
8535
8536 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
8537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8538 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8539 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
8540 emit_int8(0x2C);
8541 emit_int8((unsigned char)(0xC0 | encode));
8542 }
8543
8544 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
8545 NOT_LP64(assert(VM_Version::supports_sse(), ""));
8546 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8547 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
8548 emit_int8(0x2C);
8549 emit_int8((unsigned char)(0xC0 | encode));
8550 }
8551
8552 void Assembler::decl(Register dst) {
8553 // Don't use it directly. Use MacroAssembler::decrementl() instead.
8554 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
8555 int encode = prefix_and_encode(dst->encoding());
8556 emit_int8((unsigned char)0xFF);
8557 emit_int8((unsigned char)(0xC8 | encode));
8558 }
8559
8560 void Assembler::decq(Register dst) {
8561 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8562 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8563 int encode = prefixq_and_encode(dst->encoding());
8564 emit_int8((unsigned char)0xFF);
8565 emit_int8(0xC8 | encode);
8566 }
8567
8568 void Assembler::decq(Address dst) {
8569 // Don't use it directly. Use MacroAssembler::decrementq() instead.
8570 InstructionMark im(this);
8571 prefixq(dst);
8572 emit_int8((unsigned char)0xFF);
8573 emit_operand(rcx, dst);
8574 }
8575
8576 void Assembler::fxrstor(Address src) {
8577 prefixq(src);
8578 emit_int8(0x0F);
8579 emit_int8((unsigned char)0xAE);
8580 emit_operand(as_Register(1), src);
8581 }
8582
8583 void Assembler::xrstor(Address src) {
8584 prefixq(src);
8585 emit_int8(0x0F);
8586 emit_int8((unsigned char)0xAE);
8587 emit_operand(as_Register(5), src);
8588 }
8589
8590 void Assembler::fxsave(Address dst) {
8591 prefixq(dst);
8592 emit_int8(0x0F);
8593 emit_int8((unsigned char)0xAE);
8594 emit_operand(as_Register(0), dst);
8595 }
8596
8597 void Assembler::xsave(Address dst) {
8598 prefixq(dst);
8599 emit_int8(0x0F);
8600 emit_int8((unsigned char)0xAE);
8601 emit_operand(as_Register(4), dst);
8602 }
8603
8604 void Assembler::idivq(Register src) {
8605 int encode = prefixq_and_encode(src->encoding());
8606 emit_int8((unsigned char)0xF7);
8607 emit_int8((unsigned char)(0xF8 | encode));
8608 }
8609
8610 void Assembler::imulq(Register dst, Register src) {
8611 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8612 emit_int8(0x0F);
8613 emit_int8((unsigned char)0xAF);
8614 emit_int8((unsigned char)(0xC0 | encode));
8615 }
8616
8617 void Assembler::imulq(Register dst, Register src, int value) {
8618 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8619 if (is8bit(value)) {
8620 emit_int8(0x6B);
8621 emit_int8((unsigned char)(0xC0 | encode));
8622 emit_int8(value & 0xFF);
8623 } else {
8624 emit_int8(0x69);
8625 emit_int8((unsigned char)(0xC0 | encode));
8626 emit_int32(value);
8627 }
8628 }
8629
8630 void Assembler::imulq(Register dst, Address src) {
8631 InstructionMark im(this);
8632 prefixq(src, dst);
8633 emit_int8(0x0F);
8634 emit_int8((unsigned char) 0xAF);
8635 emit_operand(dst, src);
8636 }
8637
8638 void Assembler::incl(Register dst) {
8639 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8640 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8641 int encode = prefix_and_encode(dst->encoding());
8642 emit_int8((unsigned char)0xFF);
8643 emit_int8((unsigned char)(0xC0 | encode));
8644 }
8645
8646 void Assembler::incq(Register dst) {
8647 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8648 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
8649 int encode = prefixq_and_encode(dst->encoding());
8650 emit_int8((unsigned char)0xFF);
8651 emit_int8((unsigned char)(0xC0 | encode));
8652 }
8653
8654 void Assembler::incq(Address dst) {
8655 // Don't use it directly. Use MacroAssembler::incrementq() instead.
8656 InstructionMark im(this);
8657 prefixq(dst);
8658 emit_int8((unsigned char)0xFF);
8659 emit_operand(rax, dst);
8660 }
8661
8662 void Assembler::lea(Register dst, Address src) {
8663 leaq(dst, src);
8664 }
8665
8666 void Assembler::leaq(Register dst, Address src) {
8667 InstructionMark im(this);
8668 prefixq(src, dst);
8669 emit_int8((unsigned char)0x8D);
8670 emit_operand(dst, src);
8671 }
8672
8673 void Assembler::mov64(Register dst, int64_t imm64) {
8674 InstructionMark im(this);
8675 int encode = prefixq_and_encode(dst->encoding());
8676 emit_int8((unsigned char)(0xB8 | encode));
8677 emit_int64(imm64);
8678 }
8679
8680 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
8681 InstructionMark im(this);
8682 int encode = prefixq_and_encode(dst->encoding());
8683 emit_int8(0xB8 | encode);
8684 emit_data64(imm64, rspec);
8685 }
8686
8687 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8688 InstructionMark im(this);
8689 int encode = prefix_and_encode(dst->encoding());
8690 emit_int8((unsigned char)(0xB8 | encode));
8691 emit_data((int)imm32, rspec, narrow_oop_operand);
8692 }
8693
8694 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8695 InstructionMark im(this);
8696 prefix(dst);
8697 emit_int8((unsigned char)0xC7);
8698 emit_operand(rax, dst, 4);
8699 emit_data((int)imm32, rspec, narrow_oop_operand);
8700 }
8701
8702 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
8703 InstructionMark im(this);
8704 int encode = prefix_and_encode(src1->encoding());
8705 emit_int8((unsigned char)0x81);
8706 emit_int8((unsigned char)(0xF8 | encode));
8707 emit_data((int)imm32, rspec, narrow_oop_operand);
8708 }
8709
8710 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
8711 InstructionMark im(this);
8712 prefix(src1);
8713 emit_int8((unsigned char)0x81);
8714 emit_operand(rax, src1, 4);
8715 emit_data((int)imm32, rspec, narrow_oop_operand);
8716 }
8717
8718 void Assembler::lzcntq(Register dst, Register src) {
8719 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
8720 emit_int8((unsigned char)0xF3);
8721 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8722 emit_int8(0x0F);
8723 emit_int8((unsigned char)0xBD);
8724 emit_int8((unsigned char)(0xC0 | encode));
8725 }
8726
8727 void Assembler::movdq(XMMRegister dst, Register src) {
8728 // table D-1 says MMX/SSE2
8729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8730 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8731 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8732 emit_int8(0x6E);
8733 emit_int8((unsigned char)(0xC0 | encode));
8734 }
8735
8736 void Assembler::movdq(Register dst, XMMRegister src) {
8737 // table D-1 says MMX/SSE2
8738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8739 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8740 // swap src/dst to get correct prefix
8741 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8742 emit_int8(0x7E);
8743 emit_int8((unsigned char)(0xC0 | encode));
8744 }
8745
8746 void Assembler::movq(Register dst, Register src) {
8747 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8748 emit_int8((unsigned char)0x8B);
8749 emit_int8((unsigned char)(0xC0 | encode));
8750 }
8751
8752 void Assembler::movq(Register dst, Address src) {
8753 InstructionMark im(this);
8754 prefixq(src, dst);
8755 emit_int8((unsigned char)0x8B);
8756 emit_operand(dst, src);
8757 }
8758
8759 void Assembler::movq(Address dst, Register src) {
8760 InstructionMark im(this);
8761 prefixq(dst, src);
8762 emit_int8((unsigned char)0x89);
8763 emit_operand(src, dst);
8764 }
8765
8766 void Assembler::movsbq(Register dst, Address src) {
8767 InstructionMark im(this);
8768 prefixq(src, dst);
8769 emit_int8(0x0F);
8770 emit_int8((unsigned char)0xBE);
8771 emit_operand(dst, src);
8772 }
8773
8774 void Assembler::movsbq(Register dst, Register src) {
8775 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8776 emit_int8(0x0F);
8777 emit_int8((unsigned char)0xBE);
8778 emit_int8((unsigned char)(0xC0 | encode));
8779 }
8780
8781 void Assembler::movslq(Register dst, int32_t imm32) {
8782 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
8783 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
8784 // as a result we shouldn't use until tested at runtime...
8785 ShouldNotReachHere();
8786 InstructionMark im(this);
8787 int encode = prefixq_and_encode(dst->encoding());
8788 emit_int8((unsigned char)(0xC7 | encode));
8789 emit_int32(imm32);
8790 }
8791
8792 void Assembler::movslq(Address dst, int32_t imm32) {
8793 assert(is_simm32(imm32), "lost bits");
8794 InstructionMark im(this);
8795 prefixq(dst);
8796 emit_int8((unsigned char)0xC7);
8797 emit_operand(rax, dst, 4);
8798 emit_int32(imm32);
8799 }
8800
8801 void Assembler::movslq(Register dst, Address src) {
8802 InstructionMark im(this);
8803 prefixq(src, dst);
8804 emit_int8(0x63);
8805 emit_operand(dst, src);
8806 }
8807
8808 void Assembler::movslq(Register dst, Register src) {
8809 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8810 emit_int8(0x63);
8811 emit_int8((unsigned char)(0xC0 | encode));
8812 }
8813
8814 void Assembler::movswq(Register dst, Address src) {
8815 InstructionMark im(this);
8816 prefixq(src, dst);
8817 emit_int8(0x0F);
8818 emit_int8((unsigned char)0xBF);
8819 emit_operand(dst, src);
8820 }
8821
8822 void Assembler::movswq(Register dst, Register src) {
8823 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8824 emit_int8((unsigned char)0x0F);
8825 emit_int8((unsigned char)0xBF);
8826 emit_int8((unsigned char)(0xC0 | encode));
8827 }
8828
8829 void Assembler::movzbq(Register dst, Address src) {
8830 InstructionMark im(this);
8831 prefixq(src, dst);
8832 emit_int8((unsigned char)0x0F);
8833 emit_int8((unsigned char)0xB6);
8834 emit_operand(dst, src);
8835 }
8836
8837 void Assembler::movzbq(Register dst, Register src) {
8838 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8839 emit_int8(0x0F);
8840 emit_int8((unsigned char)0xB6);
8841 emit_int8(0xC0 | encode);
8842 }
8843
8844 void Assembler::movzwq(Register dst, Address src) {
8845 InstructionMark im(this);
8846 prefixq(src, dst);
8847 emit_int8((unsigned char)0x0F);
8848 emit_int8((unsigned char)0xB7);
8849 emit_operand(dst, src);
8850 }
8851
8852 void Assembler::movzwq(Register dst, Register src) {
8853 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8854 emit_int8((unsigned char)0x0F);
8855 emit_int8((unsigned char)0xB7);
8856 emit_int8((unsigned char)(0xC0 | encode));
8857 }
8858
8859 void Assembler::mulq(Address src) {
8860 InstructionMark im(this);
8861 prefixq(src);
8862 emit_int8((unsigned char)0xF7);
8863 emit_operand(rsp, src);
8864 }
8865
8866 void Assembler::mulq(Register src) {
8867 int encode = prefixq_and_encode(src->encoding());
8868 emit_int8((unsigned char)0xF7);
8869 emit_int8((unsigned char)(0xE0 | encode));
8870 }
8871
8872 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8873 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8874 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8875 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8876 emit_int8((unsigned char)0xF6);
8877 emit_int8((unsigned char)(0xC0 | encode));
8878 }
8879
8880 void Assembler::negq(Register dst) {
8881 int encode = prefixq_and_encode(dst->encoding());
8882 emit_int8((unsigned char)0xF7);
8883 emit_int8((unsigned char)(0xD8 | encode));
8884 }
8885
8886 void Assembler::notq(Register dst) {
8887 int encode = prefixq_and_encode(dst->encoding());
8888 emit_int8((unsigned char)0xF7);
8889 emit_int8((unsigned char)(0xD0 | encode));
8890 }
8891
8892 void Assembler::orq(Address dst, int32_t imm32) {
8893 InstructionMark im(this);
8894 prefixq(dst);
8895 emit_int8((unsigned char)0x81);
8896 emit_operand(rcx, dst, 4);
8897 emit_int32(imm32);
8898 }
8899
8900 void Assembler::orq(Register dst, int32_t imm32) {
8901 (void) prefixq_and_encode(dst->encoding());
8902 emit_arith(0x81, 0xC8, dst, imm32);
8903 }
8904
8905 void Assembler::orq(Register dst, Address src) {
8906 InstructionMark im(this);
8907 prefixq(src, dst);
8908 emit_int8(0x0B);
8909 emit_operand(dst, src);
8910 }
8911
8912 void Assembler::orq(Register dst, Register src) {
8913 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8914 emit_arith(0x0B, 0xC0, dst, src);
8915 }
8916
8917 void Assembler::popa() { // 64bit
8918 movq(r15, Address(rsp, 0));
8919 movq(r14, Address(rsp, wordSize));
8920 movq(r13, Address(rsp, 2 * wordSize));
8921 movq(r12, Address(rsp, 3 * wordSize));
8922 movq(r11, Address(rsp, 4 * wordSize));
8923 movq(r10, Address(rsp, 5 * wordSize));
8924 movq(r9, Address(rsp, 6 * wordSize));
8925 movq(r8, Address(rsp, 7 * wordSize));
8926 movq(rdi, Address(rsp, 8 * wordSize));
8927 movq(rsi, Address(rsp, 9 * wordSize));
8928 movq(rbp, Address(rsp, 10 * wordSize));
8929 // skip rsp
8930 movq(rbx, Address(rsp, 12 * wordSize));
8931 movq(rdx, Address(rsp, 13 * wordSize));
8932 movq(rcx, Address(rsp, 14 * wordSize));
8933 movq(rax, Address(rsp, 15 * wordSize));
8934
8935 addq(rsp, 16 * wordSize);
8936 }
8937
8938 void Assembler::popcntq(Register dst, Address src) {
8939 assert(VM_Version::supports_popcnt(), "must support");
8940 InstructionMark im(this);
8941 emit_int8((unsigned char)0xF3);
8942 prefixq(src, dst);
8943 emit_int8((unsigned char)0x0F);
8944 emit_int8((unsigned char)0xB8);
8945 emit_operand(dst, src);
8946 }
8947
8948 void Assembler::popcntq(Register dst, Register src) {
8949 assert(VM_Version::supports_popcnt(), "must support");
8950 emit_int8((unsigned char)0xF3);
8951 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8952 emit_int8((unsigned char)0x0F);
8953 emit_int8((unsigned char)0xB8);
8954 emit_int8((unsigned char)(0xC0 | encode));
8955 }
8956
8957 void Assembler::popq(Address dst) {
8958 InstructionMark im(this);
8959 prefixq(dst);
8960 emit_int8((unsigned char)0x8F);
8961 emit_operand(rax, dst);
8962 }
8963
8964 void Assembler::pusha() { // 64bit
8965 // we have to store original rsp. ABI says that 128 bytes
8966 // below rsp are local scratch.
8967 movq(Address(rsp, -5 * wordSize), rsp);
8968
8969 subq(rsp, 16 * wordSize);
8970
8971 movq(Address(rsp, 15 * wordSize), rax);
8972 movq(Address(rsp, 14 * wordSize), rcx);
8973 movq(Address(rsp, 13 * wordSize), rdx);
8974 movq(Address(rsp, 12 * wordSize), rbx);
8975 // skip rsp
8976 movq(Address(rsp, 10 * wordSize), rbp);
8977 movq(Address(rsp, 9 * wordSize), rsi);
8978 movq(Address(rsp, 8 * wordSize), rdi);
8979 movq(Address(rsp, 7 * wordSize), r8);
8980 movq(Address(rsp, 6 * wordSize), r9);
8981 movq(Address(rsp, 5 * wordSize), r10);
8982 movq(Address(rsp, 4 * wordSize), r11);
8983 movq(Address(rsp, 3 * wordSize), r12);
8984 movq(Address(rsp, 2 * wordSize), r13);
8985 movq(Address(rsp, wordSize), r14);
8986 movq(Address(rsp, 0), r15);
8987 }
8988
8989 void Assembler::pushq(Address src) {
8990 InstructionMark im(this);
8991 prefixq(src);
8992 emit_int8((unsigned char)0xFF);
8993 emit_operand(rsi, src);
8994 }
8995
8996 void Assembler::rclq(Register dst, int imm8) {
8997 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8998 int encode = prefixq_and_encode(dst->encoding());
8999 if (imm8 == 1) {
9000 emit_int8((unsigned char)0xD1);
9001 emit_int8((unsigned char)(0xD0 | encode));
9002 } else {
9003 emit_int8((unsigned char)0xC1);
9004 emit_int8((unsigned char)(0xD0 | encode));
9005 emit_int8(imm8);
9006 }
9007 }
9008
9009 void Assembler::rcrq(Register dst, int imm8) {
9010 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9011 int encode = prefixq_and_encode(dst->encoding());
9012 if (imm8 == 1) {
9013 emit_int8((unsigned char)0xD1);
9014 emit_int8((unsigned char)(0xD8 | encode));
9015 } else {
9016 emit_int8((unsigned char)0xC1);
9017 emit_int8((unsigned char)(0xD8 | encode));
9018 emit_int8(imm8);
9019 }
9020 }
9021
9022 void Assembler::rorq(Register dst, int imm8) {
9023 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9024 int encode = prefixq_and_encode(dst->encoding());
9025 if (imm8 == 1) {
9026 emit_int8((unsigned char)0xD1);
9027 emit_int8((unsigned char)(0xC8 | encode));
9028 } else {
9029 emit_int8((unsigned char)0xC1);
9030 emit_int8((unsigned char)(0xc8 | encode));
9031 emit_int8(imm8);
9032 }
9033 }
9034
9035 void Assembler::rorxq(Register dst, Register src, int imm8) {
9036 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9037 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9038 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9039 emit_int8((unsigned char)0xF0);
9040 emit_int8((unsigned char)(0xC0 | encode));
9041 emit_int8(imm8);
9042 }
9043
9044 void Assembler::rorxd(Register dst, Register src, int imm8) {
9045 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9046 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9047 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9048 emit_int8((unsigned char)0xF0);
9049 emit_int8((unsigned char)(0xC0 | encode));
9050 emit_int8(imm8);
9051 }
9052
9053 void Assembler::sarq(Register dst, int imm8) {
9054 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9055 int encode = prefixq_and_encode(dst->encoding());
9056 if (imm8 == 1) {
9057 emit_int8((unsigned char)0xD1);
9058 emit_int8((unsigned char)(0xF8 | encode));
9059 } else {
9060 emit_int8((unsigned char)0xC1);
9061 emit_int8((unsigned char)(0xF8 | encode));
9062 emit_int8(imm8);
9063 }
9064 }
9065
9066 void Assembler::sarq(Register dst) {
9067 int encode = prefixq_and_encode(dst->encoding());
9068 emit_int8((unsigned char)0xD3);
9069 emit_int8((unsigned char)(0xF8 | encode));
9070 }
9071
9072 void Assembler::sbbq(Address dst, int32_t imm32) {
9073 InstructionMark im(this);
9074 prefixq(dst);
9075 emit_arith_operand(0x81, rbx, dst, imm32);
9076 }
9077
9078 void Assembler::sbbq(Register dst, int32_t imm32) {
9079 (void) prefixq_and_encode(dst->encoding());
9080 emit_arith(0x81, 0xD8, dst, imm32);
9081 }
9082
9083 void Assembler::sbbq(Register dst, Address src) {
9084 InstructionMark im(this);
9085 prefixq(src, dst);
9086 emit_int8(0x1B);
9087 emit_operand(dst, src);
9088 }
9089
9090 void Assembler::sbbq(Register dst, Register src) {
9091 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9092 emit_arith(0x1B, 0xC0, dst, src);
9093 }
9094
9095 void Assembler::shlq(Register dst, int imm8) {
9096 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9097 int encode = prefixq_and_encode(dst->encoding());
9098 if (imm8 == 1) {
9099 emit_int8((unsigned char)0xD1);
9100 emit_int8((unsigned char)(0xE0 | encode));
9101 } else {
9102 emit_int8((unsigned char)0xC1);
9103 emit_int8((unsigned char)(0xE0 | encode));
9104 emit_int8(imm8);
9105 }
9106 }
9107
9108 void Assembler::shlq(Register dst) {
9109 int encode = prefixq_and_encode(dst->encoding());
9110 emit_int8((unsigned char)0xD3);
9111 emit_int8((unsigned char)(0xE0 | encode));
9112 }
9113
9114 void Assembler::shrq(Register dst, int imm8) {
9115 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9116 int encode = prefixq_and_encode(dst->encoding());
9117 emit_int8((unsigned char)0xC1);
9118 emit_int8((unsigned char)(0xE8 | encode));
9119 emit_int8(imm8);
9120 }
9121
9122 void Assembler::shrq(Register dst) {
9123 int encode = prefixq_and_encode(dst->encoding());
9124 emit_int8((unsigned char)0xD3);
9125 emit_int8(0xE8 | encode);
9126 }
9127
9128 void Assembler::subq(Address dst, int32_t imm32) {
9129 InstructionMark im(this);
9130 prefixq(dst);
9131 emit_arith_operand(0x81, rbp, dst, imm32);
9132 }
9133
9134 void Assembler::subq(Address dst, Register src) {
9135 InstructionMark im(this);
9136 prefixq(dst, src);
9137 emit_int8(0x29);
9138 emit_operand(src, dst);
9139 }
9140
9141 void Assembler::subq(Register dst, int32_t imm32) {
9142 (void) prefixq_and_encode(dst->encoding());
9143 emit_arith(0x81, 0xE8, dst, imm32);
9144 }
9145
9146 // Force generation of a 4 byte immediate value even if it fits into 8bit
9147 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9148 (void) prefixq_and_encode(dst->encoding());
9149 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9150 }
9151
9152 void Assembler::subq(Register dst, Address src) {
9153 InstructionMark im(this);
9154 prefixq(src, dst);
9155 emit_int8(0x2B);
9156 emit_operand(dst, src);
9157 }
9158
9159 void Assembler::subq(Register dst, Register src) {
9160 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9161 emit_arith(0x2B, 0xC0, dst, src);
9162 }
9163
9164 void Assembler::testq(Register dst, int32_t imm32) {
9165 // not using emit_arith because test
9166 // doesn't support sign-extension of
9167 // 8bit operands
9168 int encode = dst->encoding();
9169 if (encode == 0) {
9170 prefix(REX_W);
9171 emit_int8((unsigned char)0xA9);
9172 } else {
9173 encode = prefixq_and_encode(encode);
9174 emit_int8((unsigned char)0xF7);
9175 emit_int8((unsigned char)(0xC0 | encode));
9176 }
9177 emit_int32(imm32);
9178 }
9179
9180 void Assembler::testq(Register dst, Register src) {
9181 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9182 emit_arith(0x85, 0xC0, dst, src);
9183 }
9184
9185 void Assembler::testq(Register dst, Address src) {
9186 InstructionMark im(this);
9187 prefixq(src, dst);
9188 emit_int8((unsigned char)0x85);
9189 emit_operand(dst, src);
9190 }
9191
9192 void Assembler::xaddq(Address dst, Register src) {
9193 InstructionMark im(this);
9194 prefixq(dst, src);
9195 emit_int8(0x0F);
9196 emit_int8((unsigned char)0xC1);
9197 emit_operand(src, dst);
9198 }
9199
9200 void Assembler::xchgq(Register dst, Address src) {
9201 InstructionMark im(this);
9202 prefixq(src, dst);
9203 emit_int8((unsigned char)0x87);
9204 emit_operand(dst, src);
9205 }
9206
9207 void Assembler::xchgq(Register dst, Register src) {
9208 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9209 emit_int8((unsigned char)0x87);
9210 emit_int8((unsigned char)(0xc0 | encode));
9211 }
9212
9213 void Assembler::xorq(Register dst, Register src) {
9214 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9215 emit_arith(0x33, 0xC0, dst, src);
9216 }
9217
9218 void Assembler::xorq(Register dst, Address src) {
9219 InstructionMark im(this);
9220 prefixq(src, dst);
9221 emit_int8(0x33);
9222 emit_operand(dst, src);
9223 }
9224
9225 #endif // !LP64