# HG changeset patch # User burban # Date 1596224959 14400 # Fri Jul 31 15:49:19 2020 -0400 # Node ID ce56315ab9c0e95c3658aa290b85a41ff4e92153 # Parent 20f85f25f27dcf494f02187cbe114013ef73414b 8248672: utilities: Disallow cmp method using C++ feature Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -200,7 +200,7 @@ inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); } inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); } - inline void cmp(Register Rd, unsigned imm) __attribute__ ((deprecated)); + inline void cmp(Register Rd, unsigned imm) = delete; inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); } inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); } # HG changeset patch # User burban # Date 1596225007 14400 # Fri Jul 31 15:50:07 2020 -0400 # Node ID afb5d1e8aee2986c92e86f415b57ae44b3411762 # Parent ce56315ab9c0e95c3658aa290b85a41ff4e92153 8248500: AArch64: Remove the r18 dependency on Windows AArch64 Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py --- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py +++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py @@ -4,6 +4,9 @@ AARCH64_OBJDUMP = "objdump" AARCH64_OBJCOPY = "objcopy" +# r18 is used for TLS on Windows ABI. +REGS = [reg for reg in range(0,32) if reg != 18] + class Operand(object): def generate(self): @@ -12,7 +15,7 @@ class Register(Operand): def generate(self): - self.number = random.randint(0, 30) + self.number = random.choice(REGS) return self def astr(self, prefix): @@ -36,7 +39,7 @@ class GeneralRegisterOrZr(Register): def generate(self): - self.number = random.randint(0, 31) + self.number = random.choice(REGS) return self def astr(self, prefix = ""): @@ -53,7 +56,7 @@ class GeneralRegisterOrSp(Register): def generate(self): - self.number = random.randint(0, 31) + self.number = random.choice(REGS) return self def astr(self, prefix = ""): diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -110,8 +110,8 @@ reg_def R16_H ( SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next()); reg_def R17 ( SOC, SOC, Op_RegI, 17, r17->as_VMReg() ); reg_def R17_H ( SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next()); -reg_def R18 ( SOC, SOC, Op_RegI, 18, r18->as_VMReg() ); -reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next()); +reg_def R18 ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg() ); +reg_def R18_H ( SOC, SOC, Op_RegI, 18, r18_tls->as_VMReg()->next()); reg_def R19 ( SOC, SOE, Op_RegI, 19, r19->as_VMReg() ); reg_def R19_H ( SOC, SOE, Op_RegI, 19, r19->as_VMReg()->next()); reg_def R20 ( SOC, SOE, Op_RegI, 20, r20->as_VMReg() ); // caller esp @@ -532,6 +532,10 @@ // Class for non-allocatable 32 bit registers reg_class non_allocatable_reg32( +#ifdef _WIN64 + // See comment in register_aarch64.hpp + R18, // tls on Windows +#endif R28, // thread R30, // lr R31 // sp @@ -539,6 +543,10 @@ // Class for non-allocatable 64 bit registers reg_class non_allocatable_reg( +#ifdef _WIN64 + // See comment in register_aarch64.hpp + R18, R18_H, // tls on Windows +#endif R28, R28_H, // thread R30, R30_H, // lr R31, R31_H // sp diff --git a/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp b/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp --- a/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/c1_Defs_aarch64.hpp @@ -44,13 +44,13 @@ pd_nof_cpu_regs_frame_map = RegisterImpl::number_of_registers, // number of registers used during code emission pd_nof_fpu_regs_frame_map = FloatRegisterImpl::number_of_registers, // number of registers used during code emission - pd_nof_caller_save_cpu_regs_frame_map = 19 - 2, // number of registers killed by calls + pd_nof_caller_save_cpu_regs_frame_map = 19 - 2 /* rscratch1 and rscratch2 */ WIN64_ONLY(- 1 /* r18 */), // number of registers killed by calls pd_nof_caller_save_fpu_regs_frame_map = 32, // number of registers killed by calls - pd_first_callee_saved_reg = 19 - 2, - pd_last_callee_saved_reg = 26 - 2, + pd_first_callee_saved_reg = 19 - 2 /* rscratch1 and rscratch2 */ WIN64_ONLY(- 1 /* r18 */), + pd_last_callee_saved_reg = 26 - 2 /* rscratch1 and rscratch2 */ WIN64_ONLY(- 1 /* r18 */), - pd_last_allocatable_cpu_reg = 16, + pd_last_allocatable_cpu_reg = 16 WIN64_ONLY(- 1 /* r18 */), pd_nof_cpu_regs_reg_alloc = pd_last_allocatable_cpu_reg + 1, // number of registers that are visible to register allocator @@ -60,9 +60,9 @@ pd_nof_fpu_regs_linearscan = pd_nof_fpu_regs_frame_map, // number of registers visible to linear scan pd_nof_xmm_regs_linearscan = 0, // like sparc we don't have any of these pd_first_cpu_reg = 0, - pd_last_cpu_reg = 16, + pd_last_cpu_reg = 16 WIN64_ONLY(- 1 /* r18 */), pd_first_byte_reg = 0, - pd_last_byte_reg = 16, + pd_last_byte_reg = 16 WIN64_ONLY(- 1 /* r18 */), pd_first_fpu_reg = pd_nof_cpu_regs_frame_map, pd_last_fpu_reg = pd_first_fpu_reg + 31, diff --git a/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp --- a/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_FrameMap_aarch64.cpp @@ -181,7 +181,10 @@ map_register(i, r15); r15_opr = LIR_OprFact::single_cpu(i); i++; map_register(i, r16); r16_opr = LIR_OprFact::single_cpu(i); i++; map_register(i, r17); r17_opr = LIR_OprFact::single_cpu(i); i++; - map_register(i, r18); r18_opr = LIR_OprFact::single_cpu(i); i++; +#ifndef _WIN64 + // See comment in register_aarch64.hpp + map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++; +#endif map_register(i, r19); r19_opr = LIR_OprFact::single_cpu(i); i++; map_register(i, r20); r20_opr = LIR_OprFact::single_cpu(i); i++; map_register(i, r21); r21_opr = LIR_OprFact::single_cpu(i); i++; @@ -199,6 +202,11 @@ map_register(i, r8); r8_opr = LIR_OprFact::single_cpu(i); i++; // rscratch1 map_register(i, r9); r9_opr = LIR_OprFact::single_cpu(i); i++; // rscratch2 +#ifdef _WIN64 + // See comment in register_aarch64.hpp + map_register(i, r18_tls); r18_opr = LIR_OprFact::single_cpu(i); i++; // TLS for Win +#endif + rscratch1_opr = r8_opr; rscratch2_opr = r9_opr; rscratch1_long_opr = LIR_OprFact::double_cpu(r8_opr->cpu_regnr(), r8_opr->cpu_regnr()); @@ -227,7 +235,10 @@ _caller_save_cpu_regs[13] = r15_opr; _caller_save_cpu_regs[14] = r16_opr; _caller_save_cpu_regs[15] = r17_opr; +#ifndef _WIN64 + // See comment in register_aarch64.hpp _caller_save_cpu_regs[16] = r18_opr; +#endif for (int i = 0; i < 8; i++) { _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); @@ -253,7 +264,7 @@ r15_oop_opr = as_oop_opr(r15); r16_oop_opr = as_oop_opr(r16); r17_oop_opr = as_oop_opr(r17); - r18_oop_opr = as_oop_opr(r18); + r18_oop_opr = as_oop_opr(r18_tls); r19_oop_opr = as_oop_opr(r19); r20_oop_opr = as_oop_opr(r20); r21_oop_opr = as_oop_opr(r21); diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp @@ -2626,9 +2626,17 @@ fatal("DEBUG MESSAGE: %s", msg); } +RegSet MacroAssembler::call_clobbered_registers() { + RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2); +#ifndef _WIN64 + regs += r18_tls; +#endif + return regs; +} + void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) { int step = 4 * wordSize; - push(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2) - exclude, sp); + push(call_clobbered_registers() - exclude, sp); sub(sp, sp, step); mov(rscratch1, -step); // Push v0-v7, v16-v31. @@ -2648,7 +2656,7 @@ as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize))); } - pop(RegSet::range(r0, r18) - RegSet::of(rscratch1, rscratch2) - exclude, sp); + pop(call_clobbered_registers() - exclude, sp); } void MacroAssembler::push_CPU_state(bool save_vectors) { diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -474,6 +474,8 @@ void push_fp(RegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); } void pop_fp(RegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); } + static RegSet call_clobbered_registers(); + // Push and pop everything that might be clobbered by a native // runtime call except rscratch1 and rscratch2. (They are always // scratch, so we don't have to protect them.) Only save the lower diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64_trig.cpp @@ -689,7 +689,7 @@ RECOMP_FOR1_CHECK; Register tmp2 = r1, n = r2, jv = r4, tmp5 = r5, jx = r6, tmp3 = r7, iqBase = r10, ih = r11, tmp4 = r12, tmp1 = r13, - jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r18; + jz = r14, j = r15, twoOverPiBase = r16, i = r17, qBase = r19; // jp = jk == init_jk[prec] = init_jk[2] == {2,3,4,6}[2] == 4 // jx = nx - 1 lea(twoOverPiBase, ExternalAddress(two_over_pi)); @@ -1421,6 +1421,12 @@ Label DONE, ARG_REDUCTION, TINY_X, RETURN_SIN, EARLY_CASE; Register X = r0, absX = r1, n = r2, ix = r3; FloatRegister y0 = v4, y1 = v5; + + enter(); + // r19 is used in TemplateInterpreterGenerator::generate_math_entry + RegSet saved_regs = RegSet::of(r19); + push (saved_regs, sp); + block_comment("check |x| ~< pi/4, NaN, Inf and |x| < 2**-27 cases"); { fmovd(X, v0); mov(rscratch2, 0x3e400000); @@ -1438,14 +1444,14 @@ // Set last bit unconditionally to make it NaN orr(r10, r10, 1); fmovd(v0, r10); - ret(lr); + b(DONE); } block_comment("kernel_sin/kernel_cos: if(ix<0x3e400000) {}"); { bind(TINY_X); if (isCos) { fmovd(v0, 1.0); } - ret(lr); + b(DONE); } bind(ARG_REDUCTION); /* argument reduction needed */ block_comment("n = __ieee754_rem_pio2(x,y);"); { @@ -1465,7 +1471,7 @@ tbz(n, 1, DONE); } fnegd(v0, v0); - ret(lr); + b(DONE); bind(RETURN_SIN); generate_kernel_sin(y0, true, dsin_coef); if (isCos) { @@ -1474,7 +1480,7 @@ tbz(n, 1, DONE); } fnegd(v0, v0); - ret(lr); + b(DONE); } bind(EARLY_CASE); eor(y1, T8B, y1, y1); @@ -1484,5 +1490,7 @@ generate_kernel_sin(v0, false, dsin_coef); } bind(DONE); + pop(saved_regs, sp); + leave(); ret(lr); } diff --git a/src/hotspot/cpu/aarch64/register_aarch64.cpp b/src/hotspot/cpu/aarch64/register_aarch64.cpp --- a/src/hotspot/cpu/aarch64/register_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.cpp @@ -38,7 +38,7 @@ "c_rarg0", "c_rarg1", "c_rarg2", "c_rarg3", "c_rarg4", "c_rarg5", "c_rarg6", "c_rarg7", "rscratch1", "rscratch2", "r10", "r11", "r12", "r13", "r14", "r15", "r16", - "r17", "r18", "r19", + "r17", NOT_WIN64("r18") WIN64_ONLY("rtls"), "r19", "resp", "rdispatch", "rbcp", "r23", "rlocals", "rmonitors", "rcpool", "rheapbase", "rthread", "rfp", "lr", "sp" }; diff --git a/src/hotspot/cpu/aarch64/register_aarch64.hpp b/src/hotspot/cpu/aarch64/register_aarch64.hpp --- a/src/hotspot/cpu/aarch64/register_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/register_aarch64.hpp @@ -91,7 +91,18 @@ CONSTANT_REGISTER_DECLARATION(Register, r15, (15)); CONSTANT_REGISTER_DECLARATION(Register, r16, (16)); CONSTANT_REGISTER_DECLARATION(Register, r17, (17)); -CONSTANT_REGISTER_DECLARATION(Register, r18, (18)); + +// In the ABI for Windows+AArch64 the register r18 is used to store the pointer +// to the current thread's TEB (where TLS variables are stored). We could +// carefully save and restore r18 at key places, however Win32 Structured +// Exception Handling (SEH) is using TLS to unwind the stack. If r18 is used +// for any other purpose at the time of an exception happening, SEH would not +// be able to unwind the stack properly and most likely crash. +// +// It's easier to avoid allocating r18 altogether. +// +// See https://docs.microsoft.com/en-us/cpp/build/arm64-windows-abi-conventions?view=vs-2019#integer-registers +CONSTANT_REGISTER_DECLARATION(Register, r18_tls, (18)); CONSTANT_REGISTER_DECLARATION(Register, r19, (19)); CONSTANT_REGISTER_DECLARATION(Register, r20, (20)); CONSTANT_REGISTER_DECLARATION(Register, r21, (21)); @@ -207,6 +218,8 @@ static const int max_fpr; }; +class RegSetIterator; + // A set of registers class RegSet { uint32_t _bitset; @@ -265,6 +278,49 @@ } uint32_t bits() const { return _bitset; } + +private: + + Register first() { + uint32_t first = _bitset & -_bitset; + return first ? as_Register(exact_log2(first)) : noreg; + } + +public: + + friend class RegSetIterator; + + RegSetIterator begin(); }; +class RegSetIterator { + RegSet _regs; + +public: + RegSetIterator(RegSet x): _regs(x) {} + RegSetIterator(const RegSetIterator& mit) : _regs(mit._regs) {} + + RegSetIterator& operator++() { + Register r = _regs.first(); + if (r != noreg) + _regs -= r; + return *this; + } + + bool operator==(const RegSetIterator& rhs) const { + return _regs.bits() == rhs._regs.bits(); + } + bool operator!=(const RegSetIterator& rhs) const { + return ! (rhs == *this); + } + + Register operator*() { + return _regs.first(); + } +}; + +inline RegSetIterator RegSet::begin() { + return RegSetIterator(*this); +} + #endif // CPU_AARCH64_REGISTER_AARCH64_HPP diff --git a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp --- a/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/register_definitions_aarch64.cpp @@ -50,7 +50,7 @@ REGISTER_DEFINITION(Register, r15); REGISTER_DEFINITION(Register, r16); REGISTER_DEFINITION(Register, r17); -REGISTER_DEFINITION(Register, r18); +REGISTER_DEFINITION(Register, r18_tls); // see comment in register_aarch64.hpp REGISTER_DEFINITION(Register, r19); REGISTER_DEFINITION(Register, r20); REGISTER_DEFINITION(Register, r21); diff --git a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp --- a/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/stubGenerator_aarch64.cpp @@ -1087,7 +1087,7 @@ Label copy4, copy8, copy16, copy32, copy80, copy_big, finish; const Register t2 = r5, t3 = r6, t4 = r7, t5 = r8; const Register t6 = r9, t7 = r10, t8 = r11, t9 = r12; - const Register send = r17, dend = r18; + const Register send = r17, dend = r16; if (PrefetchCopyIntervalInBytes > 0) __ prfm(Address(s, 0), PLDL1KEEP); @@ -1277,11 +1277,15 @@ void clobber_registers() { #ifdef ASSERT + RegSet clobbered + = MacroAssembler::call_clobbered_registers() - rscratch1; __ mov(rscratch1, (uint64_t)0xdeadbeef); __ orr(rscratch1, rscratch1, rscratch1, Assembler::LSL, 32); - for (Register r = r3; r <= r18; r++) - if (r != rscratch1) __ mov(r, rscratch1); + for (RegSetIterator it = clobbered.begin(); *it != noreg; ++it) { + __ mov(*it, rscratch1); + } #endif + } // Scan over array at a for count oops, verifying each one. @@ -1714,10 +1718,10 @@ RegSet wb_pre_saved_regs = RegSet::range(c_rarg0, c_rarg4); RegSet wb_post_saved_regs = RegSet::of(count); - // Registers used as temps (r18, r19, r20 are save-on-entry) + // Registers used as temps (r19, r20, r21, r22 are save-on-entry) + const Register copied_oop = r22; // actual oop copied const Register count_save = r21; // orig elementscount const Register start_to = r20; // destination array start address - const Register copied_oop = r18; // actual oop copied const Register r19_klass = r19; // oop._klass //--------------------------------------------------------------- @@ -1754,8 +1758,7 @@ // Empty array: Nothing to do. __ cbz(count, L_done); - - __ push(RegSet::of(r18, r19, r20, r21), sp); + __ push(RegSet::of(r19, r20, r21, r22), sp); #ifdef ASSERT BLOCK_COMMENT("assert consistent ckoff/ckval"); @@ -1824,7 +1827,7 @@ bs->arraycopy_epilogue(_masm, decorators, is_oop, start_to, count_save, rscratch1, wb_post_saved_regs); __ bind(L_done_pop); - __ pop(RegSet::of(r18, r19, r20, r21), sp); + __ pop(RegSet::of(r19, r20, r21, r22), sp); inc_counter_np(SharedRuntime::_checkcast_array_copy_ctr); __ bind(L_done); @@ -2001,7 +2004,7 @@ // registers used as temp const Register scratch_length = r16; // elements count to copy const Register scratch_src_klass = r17; // array klass - const Register lh = r18; // layout helper + const Register lh = r15; // layout helper // if (length < 0) return -1; __ movw(scratch_length, length); // length (elements count, 32-bits value) @@ -2072,7 +2075,7 @@ // const Register rscratch1_offset = rscratch1; // array offset - const Register r18_elsize = lh; // element size + const Register r15_elsize = lh; // element size __ ubfx(rscratch1_offset, lh, Klass::_lh_header_size_shift, exact_log2(Klass::_lh_header_size_mask+1)); // array_offset @@ -2093,8 +2096,8 @@ // The possible values of elsize are 0-3, i.e. exact_log2(element // size in bytes). We do a simple bitwise binary search. __ BIND(L_copy_bytes); - __ tbnz(r18_elsize, 1, L_copy_ints); - __ tbnz(r18_elsize, 0, L_copy_shorts); + __ tbnz(r15_elsize, 1, L_copy_ints); + __ tbnz(r15_elsize, 0, L_copy_shorts); __ lea(from, Address(src, src_pos));// src_addr __ lea(to, Address(dst, dst_pos));// dst_addr __ movw(count, scratch_length); // length @@ -2107,7 +2110,7 @@ __ b(RuntimeAddress(short_copy_entry)); __ BIND(L_copy_ints); - __ tbnz(r18_elsize, 0, L_copy_longs); + __ tbnz(r15_elsize, 0, L_copy_longs); __ lea(from, Address(src, src_pos, Address::lsl(2)));// src_addr __ lea(to, Address(dst, dst_pos, Address::lsl(2)));// dst_addr __ movw(count, scratch_length); // length @@ -2118,8 +2121,8 @@ { BLOCK_COMMENT("assert long copy {"); Label L; - __ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r18_elsize - __ cmpw(r18_elsize, LogBytesPerLong); + __ andw(lh, lh, Klass::_lh_log2_element_size_mask); // lh -> r15_elsize + __ cmpw(r15_elsize, LogBytesPerLong); __ br(Assembler::EQ, L); __ stop("must be long copy, but elsize is wrong"); __ bind(L); @@ -2137,8 +2140,8 @@ Label L_plain_copy, L_checkcast_copy; // test array classes for subtyping - __ load_klass(r18, dst); - __ cmp(scratch_src_klass, r18); // usual case is exact equality + __ load_klass(r15, dst); + __ cmp(scratch_src_klass, r15); // usual case is exact equality __ br(Assembler::NE, L_checkcast_copy); // Identically typed arrays can be copied without element-wise checks. @@ -2154,17 +2157,17 @@ __ b(RuntimeAddress(oop_copy_entry)); __ BIND(L_checkcast_copy); - // live at this point: scratch_src_klass, scratch_length, r18 (dst_klass) + // live at this point: scratch_src_klass, scratch_length, r15 (dst_klass) { // Before looking at dst.length, make sure dst is also an objArray. - __ ldrw(rscratch1, Address(r18, lh_offset)); + __ ldrw(rscratch1, Address(r15, lh_offset)); __ movw(rscratch2, objArray_lh); __ eorw(rscratch1, rscratch1, rscratch2); __ cbnzw(rscratch1, L_failed); // It is safe to examine both src.length and dst.length. arraycopy_range_checks(src, src_pos, dst, dst_pos, scratch_length, - r18, L_failed); + r15, L_failed); __ load_klass(dst_klass, dst); // reload @@ -5055,42 +5058,42 @@ // Register allocation - Register reg = c_rarg0; - Pa_base = reg; // Argument registers + RegSetIterator regs = (RegSet::range(r0, r26) - r18_tls).begin(); + Pa_base = *regs; // Argument registers if (squaring) Pb_base = Pa_base; else - Pb_base = ++reg; - Pn_base = ++reg; - Rlen= ++reg; - inv = ++reg; - Pm_base = ++reg; + Pb_base = *++regs; + Pn_base = *++regs; + Rlen= *++regs; + inv = *++regs; + Pm_base = *++regs; // Working registers: - Ra = ++reg; // The current digit of a, b, n, and m. - Rb = ++reg; - Rm = ++reg; - Rn = ++reg; - - Pa = ++reg; // Pointers to the current/next digit of a, b, n, and m. - Pb = ++reg; - Pm = ++reg; - Pn = ++reg; - - t0 = ++reg; // Three registers which form a - t1 = ++reg; // triple-precision accumuator. - t2 = ++reg; - - Ri = ++reg; // Inner and outer loop indexes. - Rj = ++reg; - - Rhi_ab = ++reg; // Product registers: low and high parts - Rlo_ab = ++reg; // of a*b and m*n. - Rhi_mn = ++reg; - Rlo_mn = ++reg; + Ra = *++regs; // The current digit of a, b, n, and m. + Rb = *++regs; + Rm = *++regs; + Rn = *++regs; + + Pa = *++regs; // Pointers to the current/next digit of a, b, n, and m. + Pb = *++regs; + Pm = *++regs; + Pn = *++regs; + + t0 = *++regs; // Three registers which form a + t1 = *++regs; // triple-precision accumuator. + t2 = *++regs; + + Ri = *++regs; // Inner and outer loop indexes. + Rj = *++regs; + + Rhi_ab = *++regs; // Product registers: low and high parts + Rlo_ab = *++regs; // of a*b and m*n. + Rhi_mn = *++regs; + Rlo_mn = *++regs; // r19 and up are callee-saved. - _toSave = RegSet::range(r19, reg) + Pm_base; + _toSave = RegSet::range(r19, *regs) + Pm_base; } private: # HG changeset patch # User burban # Date 1596225021 14400 # Fri Jul 31 15:50:21 2020 -0400 # Node ID ebbe00c38bc9606cf540c58a7eb93bc090c1ce50 # Parent afb5d1e8aee2986c92e86f415b57ae44b3411762 8248500: AArch64: Remove the r18 dependency on Windows AArch64 (regenerate tests) Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/aarch64-asmtest.py b/src/hotspot/cpu/aarch64/aarch64-asmtest.py --- a/src/hotspot/cpu/aarch64/aarch64-asmtest.py +++ b/src/hotspot/cpu/aarch64/aarch64-asmtest.py @@ -5,7 +5,8 @@ AARCH64_OBJCOPY = "objcopy" # r18 is used for TLS on Windows ABI. -REGS = [reg for reg in range(0,32) if reg != 18] +REGS30 = [reg for reg in range(0,30) if reg != 18] +REGS31 = REGS30 + [31] class Operand(object): @@ -15,7 +16,7 @@ class Register(Operand): def generate(self): - self.number = random.choice(REGS) + self.number = random.choice(REGS30) return self def astr(self, prefix): @@ -39,7 +40,7 @@ class GeneralRegisterOrZr(Register): def generate(self): - self.number = random.choice(REGS) + self.number = random.choice(REGS31) return self def astr(self, prefix = ""): @@ -56,7 +57,7 @@ class GeneralRegisterOrSp(Register): def generate(self): - self.number = random.choice(REGS) + self.number = random.choice(REGS31) return self def astr(self, prefix = ""): diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp @@ -96,668 +96,662 @@ __ bind(back); // ArithOp - __ add(r26, r23, r13, Assembler::LSL, 32); // add x26, x23, x13, LSL #32 - __ sub(r12, r24, r9, Assembler::LSR, 37); // sub x12, x24, x9, LSR #37 - __ adds(r28, r15, r8, Assembler::ASR, 39); // adds x28, x15, x8, ASR #39 - __ subs(r7, r28, r30, Assembler::ASR, 57); // subs x7, x28, x30, ASR #57 - __ addw(r9, r22, r27, Assembler::ASR, 15); // add w9, w22, w27, ASR #15 - __ subw(r3, r13, r18, Assembler::ASR, 30); // sub w3, w13, w18, ASR #30 - __ addsw(r14, r26, r8, Assembler::ASR, 17); // adds w14, w26, w8, ASR #17 - __ subsw(r0, r22, r12, Assembler::ASR, 21); // subs w0, w22, w12, ASR #21 - __ andr(r0, r15, r26, Assembler::LSL, 20); // and x0, x15, x26, LSL #20 - __ orr(r26, r5, r17, Assembler::LSL, 61); // orr x26, x5, x17, LSL #61 - __ eor(r24, r13, r2, Assembler::LSL, 32); // eor x24, x13, x2, LSL #32 - __ ands(r28, r3, r17, Assembler::ASR, 35); // ands x28, x3, x17, ASR #35 - __ andw(r25, r16, r29, Assembler::LSR, 18); // and w25, w16, w29, LSR #18 - __ orrw(r13, r18, r11, Assembler::LSR, 9); // orr w13, w18, w11, LSR #9 - __ eorw(r5, r5, r18, Assembler::LSR, 15); // eor w5, w5, w18, LSR #15 - __ andsw(r2, r23, r27, Assembler::ASR, 26); // ands w2, w23, w27, ASR #26 - __ bic(r27, r28, r16, Assembler::LSR, 45); // bic x27, x28, x16, LSR #45 - __ orn(r8, r25, r26, Assembler::ASR, 37); // orn x8, x25, x26, ASR #37 - __ eon(r29, r17, r13, Assembler::LSR, 63); // eon x29, x17, x13, LSR #63 - __ bics(r28, r24, r2, Assembler::LSR, 31); // bics x28, x24, x2, LSR #31 - __ bicw(r19, r26, r7, Assembler::ASR, 3); // bic w19, w26, w7, ASR #3 - __ ornw(r6, r24, r10, Assembler::ASR, 3); // orn w6, w24, w10, ASR #3 - __ eonw(r4, r21, r1, Assembler::LSR, 29); // eon w4, w21, w1, LSR #29 - __ bicsw(r16, r21, r0, Assembler::LSR, 19); // bics w16, w21, w0, LSR #19 + __ add(r20, r0, r26, Assembler::LSL, 52); // add x20, x0, x26, LSL #52 + __ sub(r5, r28, r3, Assembler::ASR, 54); // sub x5, x28, x3, ASR #54 + __ adds(r11, r22, r3, Assembler::ASR, 39); // adds x11, x22, x3, ASR #39 + __ subs(r11, r3, r12, Assembler::LSR, 25); // subs x11, x3, x12, LSR #25 + __ addw(r27, r12, r13, Assembler::LSL, 14); // add w27, w12, w13, LSL #14 + __ subw(r10, r21, r27, Assembler::ASR, 7); // sub w10, w21, w27, ASR #7 + __ addsw(r3, r14, r16, Assembler::LSL, 4); // adds w3, w14, w16, LSL #4 + __ subsw(r1, r19, r29, Assembler::LSL, 5); // subs w1, w19, w29, LSL #5 + __ andr(r16, r17, r27, Assembler::LSR, 6); // and x16, x17, x27, LSR #6 + __ orr(r22, r28, r28, Assembler::LSL, 35); // orr x22, x28, x28, LSL #35 + __ eor(r11, r10, r28, Assembler::LSR, 51); // eor x11, x10, x28, LSR #51 + __ ands(r13, r8, r14, Assembler::ASR, 48); // ands x13, x8, x14, ASR #48 + __ andw(r1, r3, r1, Assembler::LSR, 3); // and w1, w3, w1, LSR #3 + __ orrw(r9, r8, r5, Assembler::ASR, 22); // orr w9, w8, w5, ASR #22 + __ eorw(r2, r28, r27, Assembler::ASR, 19); // eor w2, w28, w27, ASR #19 + __ andsw(r24, r9, r7, Assembler::LSL, 14); // ands w24, w9, w7, LSL #14 + __ bic(r11, r19, r25, Assembler::ASR, 32); // bic x11, x19, x25, ASR #32 + __ orn(r24, r24, r29, Assembler::LSL, 28); // orn x24, x24, x29, LSL #28 + __ eon(r11, r16, r17, Assembler::ASR, 27); // eon x11, x16, x17, ASR #27 + __ bics(r5, r13, r10, Assembler::LSR, 58); // bics x5, x13, x10, LSR #58 + __ bicw(r5, r10, r21, Assembler::LSL, 29); // bic w5, w10, w21, LSL #29 + __ ornw(r4, r11, r21, Assembler::LSL, 19); // orn w4, w11, w21, LSL #19 + __ eonw(r21, r28, r28, Assembler::LSR, 15); // eon w21, w28, w28, LSR #15 + __ bicsw(r6, r10, r14, Assembler::LSL, 28); // bics w6, w10, w14, LSL #28 // AddSubImmOp - __ addw(r17, r12, 379u); // add w17, w12, #379 - __ addsw(r30, r1, 22u); // adds w30, w1, #22 - __ subw(r29, r5, 126u); // sub w29, w5, #126 - __ subsw(r6, r24, 960u); // subs w6, w24, #960 - __ add(r0, r13, 104u); // add x0, x13, #104 - __ adds(r8, r6, 663u); // adds x8, x6, #663 - __ sub(r10, r5, 516u); // sub x10, x5, #516 - __ subs(r1, r3, 1012u); // subs x1, x3, #1012 + __ addw(r10, r22, 945u); // add w10, w22, #945 + __ addsw(r15, r11, 935u); // adds w15, w11, #935 + __ subw(r5, r6, 703u); // sub w5, w6, #703 + __ subsw(r19, r0, 568u); // subs w19, w0, #568 + __ add(r20, r8, 608u); // add x20, x8, #608 + __ adds(r16, r6, 269u); // adds x16, x6, #269 + __ sub(r23, r0, 877u); // sub x23, x0, #877 + __ subs(r26, r25, 801u); // subs x26, x25, #801 // LogicalImmOp - __ andw(r6, r11, 4294049777ull); // and w6, w11, #0xfff1fff1 - __ orrw(r28, r5, 4294966791ull); // orr w28, w5, #0xfffffe07 - __ eorw(r1, r20, 134217216ull); // eor w1, w20, #0x7fffe00 - __ andsw(r7, r18, 1048576ull); // ands w7, w18, #0x100000 - __ andr(r14, r12, 9223372036854775808ull); // and x14, x12, #0x8000000000000000 - __ orr(r9, r11, 562675075514368ull); // orr x9, x11, #0x1ffc000000000 - __ eor(r17, r0, 18014398509481728ull); // eor x17, x0, #0x3fffffffffff00 - __ ands(r1, r8, 18446744073705357315ull); // ands x1, x8, #0xffffffffffc00003 + __ andw(r12, r16, 4294459391ull); // and w12, w16, #0xfff83fff + __ orrw(r1, r24, 4229955583ull); // orr w1, w24, #0xfc1fffff + __ eorw(r19, r3, 16744448ull); // eor w19, w3, #0xff8000 + __ andsw(r29, r9, 4290777087ull); // ands w29, w9, #0xffc00fff + __ andr(r26, r5, 18446744073172942847ull); // and x26, x5, #0xffffffffe003ffff + __ orr(r24, r14, 1150687262887383032ull); // orr x24, x14, #0xff80ff80ff80ff8 + __ eor(r4, r0, 18446744073709289487ull); // eor x4, x0, #0xfffffffffffc000f + __ ands(r28, r6, 536608768ull); // ands x28, x6, #0x1ffc0000 // AbsOp - __ b(__ pc()); // b . - __ b(back); // b back - __ b(forth); // b forth - __ bl(__ pc()); // bl . - __ bl(back); // bl back - __ bl(forth); // bl forth + __ b(__ pc()); // b . + __ b(back); // b back + __ b(forth); // b forth + __ bl(__ pc()); // bl . + __ bl(back); // bl back + __ bl(forth); // bl forth // RegAndAbsOp - __ cbzw(r10, __ pc()); // cbz w10, . - __ cbzw(r10, back); // cbz w10, back - __ cbzw(r10, forth); // cbz w10, forth - __ cbnzw(r8, __ pc()); // cbnz w8, . - __ cbnzw(r8, back); // cbnz w8, back - __ cbnzw(r8, forth); // cbnz w8, forth - __ cbz(r11, __ pc()); // cbz x11, . - __ cbz(r11, back); // cbz x11, back - __ cbz(r11, forth); // cbz x11, forth - __ cbnz(r29, __ pc()); // cbnz x29, . - __ cbnz(r29, back); // cbnz x29, back - __ cbnz(r29, forth); // cbnz x29, forth - __ adr(r19, __ pc()); // adr x19, . - __ adr(r19, back); // adr x19, back - __ adr(r19, forth); // adr x19, forth - __ _adrp(r19, __ pc()); // adrp x19, . + __ cbzw(r21, __ pc()); // cbz w21, . + __ cbzw(r21, back); // cbz w21, back + __ cbzw(r21, forth); // cbz w21, forth + __ cbnzw(r12, __ pc()); // cbnz w12, . + __ cbnzw(r12, back); // cbnz w12, back + __ cbnzw(r12, forth); // cbnz w12, forth + __ cbz(r14, __ pc()); // cbz x14, . + __ cbz(r14, back); // cbz x14, back + __ cbz(r14, forth); // cbz x14, forth + __ cbnz(r27, __ pc()); // cbnz x27, . + __ cbnz(r27, back); // cbnz x27, back + __ cbnz(r27, forth); // cbnz x27, forth + __ adr(r14, __ pc()); // adr x14, . + __ adr(r14, back); // adr x14, back + __ adr(r14, forth); // adr x14, forth + __ _adrp(r22, __ pc()); // adrp x22, . // RegImmAbsOp - __ tbz(r22, 6, __ pc()); // tbz x22, #6, . - __ tbz(r22, 6, back); // tbz x22, #6, back - __ tbz(r22, 6, forth); // tbz x22, #6, forth - __ tbnz(r12, 11, __ pc()); // tbnz x12, #11, . - __ tbnz(r12, 11, back); // tbnz x12, #11, back - __ tbnz(r12, 11, forth); // tbnz x12, #11, forth + __ tbz(r0, 5, __ pc()); // tbz x0, #5, . + __ tbz(r0, 5, back); // tbz x0, #5, back + __ tbz(r0, 5, forth); // tbz x0, #5, forth + __ tbnz(r3, 11, __ pc()); // tbnz x3, #11, . + __ tbnz(r3, 11, back); // tbnz x3, #11, back + __ tbnz(r3, 11, forth); // tbnz x3, #11, forth // MoveWideImmOp - __ movnw(r0, 6301, 0); // movn w0, #6301, lsl 0 - __ movzw(r7, 20886, 0); // movz w7, #20886, lsl 0 - __ movkw(r27, 18617, 0); // movk w27, #18617, lsl 0 - __ movn(r12, 22998, 16); // movn x12, #22998, lsl 16 - __ movz(r20, 1532, 16); // movz x20, #1532, lsl 16 - __ movk(r8, 5167, 32); // movk x8, #5167, lsl 32 + __ movnw(r19, 6842, 0); // movn w19, #6842, lsl 0 + __ movzw(r28, 5843, 16); // movz w28, #5843, lsl 16 + __ movkw(r13, 20344, 16); // movk w13, #20344, lsl 16 + __ movn(r1, 1215, 32); // movn x1, #1215, lsl 32 + __ movz(r26, 28755, 0); // movz x26, #28755, lsl 0 + __ movk(r27, 5762, 48); // movk x27, #5762, lsl 48 // BitfieldOp - __ sbfm(r15, r17, 24, 28); // sbfm x15, x17, #24, #28 - __ bfmw(r15, r9, 14, 25); // bfm w15, w9, #14, #25 - __ ubfmw(r27, r25, 6, 31); // ubfm w27, w25, #6, #31 - __ sbfm(r19, r2, 23, 31); // sbfm x19, x2, #23, #31 - __ bfm(r12, r21, 10, 6); // bfm x12, x21, #10, #6 - __ ubfm(r22, r0, 26, 16); // ubfm x22, x0, #26, #16 + __ sbfm(r1, r24, 9, 24); // sbfm x1, x24, #9, #24 + __ bfmw(r25, r0, 5, 16); // bfm w25, w0, #5, #16 + __ ubfmw(r16, r27, 15, 7); // ubfm w16, w27, #15, #7 + __ sbfm(r16, r14, 15, 28); // sbfm x16, x14, #15, #28 + __ bfm(r24, r10, 0, 13); // bfm x24, x10, #0, #13 + __ ubfm(r1, r14, 2, 22); // ubfm x1, x14, #2, #22 // ExtractOp - __ extrw(r3, r3, r20, 27); // extr w3, w3, w20, #27 - __ extr(r8, r30, r3, 54); // extr x8, x30, x3, #54 + __ extrw(r10, r0, r1, 21); // extr w10, w0, w1, #21 + __ extr(r26, r26, r23, 61); // extr x26, x26, x23, #61 // CondBranchOp - __ br(Assembler::EQ, __ pc()); // b.EQ . - __ br(Assembler::EQ, back); // b.EQ back - __ br(Assembler::EQ, forth); // b.EQ forth - __ br(Assembler::NE, __ pc()); // b.NE . - __ br(Assembler::NE, back); // b.NE back - __ br(Assembler::NE, forth); // b.NE forth - __ br(Assembler::HS, __ pc()); // b.HS . - __ br(Assembler::HS, back); // b.HS back - __ br(Assembler::HS, forth); // b.HS forth - __ br(Assembler::CS, __ pc()); // b.CS . - __ br(Assembler::CS, back); // b.CS back - __ br(Assembler::CS, forth); // b.CS forth - __ br(Assembler::LO, __ pc()); // b.LO . - __ br(Assembler::LO, back); // b.LO back - __ br(Assembler::LO, forth); // b.LO forth - __ br(Assembler::CC, __ pc()); // b.CC . - __ br(Assembler::CC, back); // b.CC back - __ br(Assembler::CC, forth); // b.CC forth - __ br(Assembler::MI, __ pc()); // b.MI . - __ br(Assembler::MI, back); // b.MI back - __ br(Assembler::MI, forth); // b.MI forth - __ br(Assembler::PL, __ pc()); // b.PL . - __ br(Assembler::PL, back); // b.PL back - __ br(Assembler::PL, forth); // b.PL forth - __ br(Assembler::VS, __ pc()); // b.VS . - __ br(Assembler::VS, back); // b.VS back - __ br(Assembler::VS, forth); // b.VS forth - __ br(Assembler::VC, __ pc()); // b.VC . - __ br(Assembler::VC, back); // b.VC back - __ br(Assembler::VC, forth); // b.VC forth - __ br(Assembler::HI, __ pc()); // b.HI . - __ br(Assembler::HI, back); // b.HI back - __ br(Assembler::HI, forth); // b.HI forth - __ br(Assembler::LS, __ pc()); // b.LS . - __ br(Assembler::LS, back); // b.LS back - __ br(Assembler::LS, forth); // b.LS forth - __ br(Assembler::GE, __ pc()); // b.GE . - __ br(Assembler::GE, back); // b.GE back - __ br(Assembler::GE, forth); // b.GE forth - __ br(Assembler::LT, __ pc()); // b.LT . - __ br(Assembler::LT, back); // b.LT back - __ br(Assembler::LT, forth); // b.LT forth - __ br(Assembler::GT, __ pc()); // b.GT . - __ br(Assembler::GT, back); // b.GT back - __ br(Assembler::GT, forth); // b.GT forth - __ br(Assembler::LE, __ pc()); // b.LE . - __ br(Assembler::LE, back); // b.LE back - __ br(Assembler::LE, forth); // b.LE forth - __ br(Assembler::AL, __ pc()); // b.AL . - __ br(Assembler::AL, back); // b.AL back - __ br(Assembler::AL, forth); // b.AL forth - __ br(Assembler::NV, __ pc()); // b.NV . - __ br(Assembler::NV, back); // b.NV back - __ br(Assembler::NV, forth); // b.NV forth + __ br(Assembler::EQ, __ pc()); // b.EQ . + __ br(Assembler::EQ, back); // b.EQ back + __ br(Assembler::EQ, forth); // b.EQ forth + __ br(Assembler::NE, __ pc()); // b.NE . + __ br(Assembler::NE, back); // b.NE back + __ br(Assembler::NE, forth); // b.NE forth + __ br(Assembler::HS, __ pc()); // b.HS . + __ br(Assembler::HS, back); // b.HS back + __ br(Assembler::HS, forth); // b.HS forth + __ br(Assembler::CS, __ pc()); // b.CS . + __ br(Assembler::CS, back); // b.CS back + __ br(Assembler::CS, forth); // b.CS forth + __ br(Assembler::LO, __ pc()); // b.LO . + __ br(Assembler::LO, back); // b.LO back + __ br(Assembler::LO, forth); // b.LO forth + __ br(Assembler::CC, __ pc()); // b.CC . + __ br(Assembler::CC, back); // b.CC back + __ br(Assembler::CC, forth); // b.CC forth + __ br(Assembler::MI, __ pc()); // b.MI . + __ br(Assembler::MI, back); // b.MI back + __ br(Assembler::MI, forth); // b.MI forth + __ br(Assembler::PL, __ pc()); // b.PL . + __ br(Assembler::PL, back); // b.PL back + __ br(Assembler::PL, forth); // b.PL forth + __ br(Assembler::VS, __ pc()); // b.VS . + __ br(Assembler::VS, back); // b.VS back + __ br(Assembler::VS, forth); // b.VS forth + __ br(Assembler::VC, __ pc()); // b.VC . + __ br(Assembler::VC, back); // b.VC back + __ br(Assembler::VC, forth); // b.VC forth + __ br(Assembler::HI, __ pc()); // b.HI . + __ br(Assembler::HI, back); // b.HI back + __ br(Assembler::HI, forth); // b.HI forth + __ br(Assembler::LS, __ pc()); // b.LS . + __ br(Assembler::LS, back); // b.LS back + __ br(Assembler::LS, forth); // b.LS forth + __ br(Assembler::GE, __ pc()); // b.GE . + __ br(Assembler::GE, back); // b.GE back + __ br(Assembler::GE, forth); // b.GE forth + __ br(Assembler::LT, __ pc()); // b.LT . + __ br(Assembler::LT, back); // b.LT back + __ br(Assembler::LT, forth); // b.LT forth + __ br(Assembler::GT, __ pc()); // b.GT . + __ br(Assembler::GT, back); // b.GT back + __ br(Assembler::GT, forth); // b.GT forth + __ br(Assembler::LE, __ pc()); // b.LE . + __ br(Assembler::LE, back); // b.LE back + __ br(Assembler::LE, forth); // b.LE forth + __ br(Assembler::AL, __ pc()); // b.AL . + __ br(Assembler::AL, back); // b.AL back + __ br(Assembler::AL, forth); // b.AL forth + __ br(Assembler::NV, __ pc()); // b.NV . + __ br(Assembler::NV, back); // b.NV back + __ br(Assembler::NV, forth); // b.NV forth // ImmOp - __ svc(12999); // svc #12999 - __ hvc(2665); // hvc #2665 - __ smc(9002); // smc #9002 - __ brk(14843); // brk #14843 - __ hlt(25964); // hlt #25964 + __ svc(15523); // svc #15523 + __ hvc(3191); // hvc #3191 + __ smc(18110); // smc #18110 + __ brk(2818); // brk #2818 + __ hlt(20860); // hlt #20860 // Op - __ nop(); // nop - __ eret(); // eret - __ drps(); // drps - __ isb(); // isb + __ nop(); // nop + __ eret(); // eret + __ drps(); // drps + __ isb(); // isb // SystemOp - __ dsb(Assembler::ST); // dsb ST - __ dmb(Assembler::OSHST); // dmb OSHST + __ dsb(Assembler::OSHST); // dsb OSHST + __ dmb(Assembler::ISHLD); // dmb ISHLD // OneRegOp - __ br(r16); // br x16 - __ blr(r20); // blr x20 + __ br(r10); // br x10 + __ blr(r22); // blr x22 // LoadStoreExclusiveOp - __ stxr(r10, r27, r8); // stxr w10, x27, [x8] - __ stlxr(r0, r1, r21); // stlxr w0, x1, [x21] - __ ldxr(r17, r29); // ldxr x17, [x29] - __ ldaxr(r29, r28); // ldaxr x29, [x28] - __ stlr(r1, r23); // stlr x1, [x23] - __ ldar(r21, r20); // ldar x21, [x20] + __ stxr(r3, r21, r5); // stxr w3, x21, [x5] + __ stlxr(r28, r9, r29); // stlxr w28, x9, [x29] + __ ldxr(r28, r7); // ldxr x28, [x7] + __ ldaxr(r10, r23); // ldaxr x10, [x23] + __ stlr(r7, r26); // stlr x7, [x26] + __ ldar(r16, r23); // ldar x16, [x23] // LoadStoreExclusiveOp - __ stxrw(r22, r27, r19); // stxr w22, w27, [x19] - __ stlxrw(r11, r16, r6); // stlxr w11, w16, [x6] - __ ldxrw(r18, r0); // ldxr w18, [x0] - __ ldaxrw(r4, r10); // ldaxr w4, [x10] - __ stlrw(r24, r22); // stlr w24, [x22] - __ ldarw(r10, r19); // ldar w10, [x19] + __ stxrw(r11, r7, r12); // stxr w11, w7, [x12] + __ stlxrw(r16, r13, r26); // stlxr w16, w13, [x26] + __ ldxrw(r25, r21); // ldxr w25, [x21] + __ ldaxrw(r14, r4); // ldaxr w14, [x4] + __ stlrw(r26, r9); // stlr w26, [x9] + __ ldarw(r0, r23); // ldar w0, [x23] // LoadStoreExclusiveOp - __ stxrh(r1, r5, r30); // stxrh w1, w5, [x30] - __ stlxrh(r8, r12, r17); // stlxrh w8, w12, [x17] - __ ldxrh(r9, r14); // ldxrh w9, [x14] - __ ldaxrh(r7, r1); // ldaxrh w7, [x1] - __ stlrh(r5, r16); // stlrh w5, [x16] - __ ldarh(r2, r12); // ldarh w2, [x12] + __ stxrh(r8, r0, r10); // stxrh w8, w0, [x10] + __ stlxrh(r11, r1, r4); // stlxrh w11, w1, [x4] + __ ldxrh(r14, r26); // ldxrh w14, [x26] + __ ldaxrh(r19, r7); // ldaxrh w19, [x7] + __ stlrh(r17, r22); // stlrh w17, [x22] + __ ldarh(r20, r6); // ldarh w20, [x6] // LoadStoreExclusiveOp - __ stxrb(r10, r12, r3); // stxrb w10, w12, [x3] - __ stlxrb(r28, r14, r26); // stlxrb w28, w14, [x26] - __ ldxrb(r30, r10); // ldxrb w30, [x10] - __ ldaxrb(r14, r21); // ldaxrb w14, [x21] - __ stlrb(r13, r9); // stlrb w13, [x9] - __ ldarb(r22, r27); // ldarb w22, [x27] + __ stxrb(r25, r8, r6); // stxrb w25, w8, [x6] + __ stlxrb(r5, r10, r25); // stlxrb w5, w10, [x25] + __ ldxrb(r0, r22); // ldxrb w0, [x22] + __ ldaxrb(r8, r3); // ldaxrb w8, [x3] + __ stlrb(r5, r2); // stlrb w5, [x2] + __ ldarb(r6, r28); // ldarb w6, [x28] // LoadStoreExclusiveOp - __ ldxp(r28, r19, r11); // ldxp x28, x19, [x11] - __ ldaxp(r30, r19, r2); // ldaxp x30, x19, [x2] - __ stxp(r2, r23, r1, r0); // stxp w2, x23, x1, [x0] - __ stlxp(r12, r16, r13, r15); // stlxp w12, x16, x13, [x15] + __ ldxp(r17, r8, r14); // ldxp x17, x8, [x14] + __ ldaxp(r14, r3, r2); // ldaxp x14, x3, [x2] + __ stxp(r25, r17, r4, r19); // stxp w25, x17, x4, [x19] + __ stlxp(r10, r16, r15, r8); // stlxp w10, x16, x15, [x8] // LoadStoreExclusiveOp - __ ldxpw(r18, r21, r13); // ldxp w18, w21, [x13] - __ ldaxpw(r11, r30, r8); // ldaxp w11, w30, [x8] - __ stxpw(r24, r13, r11, r1); // stxp w24, w13, w11, [x1] - __ stlxpw(r26, r21, r27, r13); // stlxp w26, w21, w27, [x13] + __ ldxpw(r1, r11, r3); // ldxp w1, w11, [x3] + __ ldaxpw(r0, r27, r12); // ldaxp w0, w27, [x12] + __ stxpw(r4, r20, r21, r29); // stxp w4, w20, w21, [x29] + __ stlxpw(r0, r9, r5, r29); // stlxp w0, w9, w5, [x29] -// base_plus_unscaled_offset +// base_plus_unscaled_offset // LoadStoreOp - __ str(r11, Address(r20, -103)); // str x11, [x20, -103] - __ strw(r28, Address(r16, 62)); // str w28, [x16, 62] - __ strb(r27, Address(r9, -9)); // strb w27, [x9, -9] - __ strh(r2, Address(r25, -50)); // strh w2, [x25, -50] - __ ldr(r4, Address(r2, -241)); // ldr x4, [x2, -241] - __ ldrw(r30, Address(r20, -31)); // ldr w30, [x20, -31] - __ ldrb(r18, Address(r23, -23)); // ldrb w18, [x23, -23] - __ ldrh(r29, Address(r26, -1)); // ldrh w29, [x26, -1] - __ ldrsb(r1, Address(r9, 6)); // ldrsb x1, [x9, 6] - __ ldrsh(r11, Address(r12, 19)); // ldrsh x11, [x12, 19] - __ ldrshw(r11, Address(r1, -50)); // ldrsh w11, [x1, -50] - __ ldrsw(r19, Address(r24, 41)); // ldrsw x19, [x24, 41] - __ ldrd(v24, Address(r24, 95)); // ldr d24, [x24, 95] - __ ldrs(v15, Address(r5, -43)); // ldr s15, [x5, -43] - __ strd(v21, Address(r27, 1)); // str d21, [x27, 1] - __ strs(v23, Address(r13, -107)); // str s23, [x13, -107] + __ str(r17, Address(r4, -227)); // str x17, [x4, -227] + __ strw(r6, Address(r4, -33)); // str w6, [x4, -33] + __ strb(r13, Address(r16, 11)); // strb w13, [x16, 11] + __ strh(r23, Address(r22, -64)); // strh w23, [x22, -64] + __ ldr(r2, Address(r3, 13)); // ldr x2, [x3, 13] + __ ldrw(r5, Address(r20, 35)); // ldr w5, [x20, 35] + __ ldrb(r2, Address(r10, -15)); // ldrb w2, [x10, -15] + __ ldrh(r23, Address(r0, -8)); // ldrh w23, [x0, -8] + __ ldrsb(r15, Address(r14, -3)); // ldrsb x15, [x14, -3] + __ ldrsh(r3, Address(r3, -12)); // ldrsh x3, [x3, -12] + __ ldrshw(r25, Address(r24, -7)); // ldrsh w25, [x24, -7] + __ ldrsw(r17, Address(r0, -29)); // ldrsw x17, [x0, -29] + __ ldrd(v7, Address(r9, -79)); // ldr d7, [x9, -79] + __ ldrs(v11, Address(r11, -68)); // ldr s11, [x11, -68] + __ strd(v16, Address(r2, -119)); // str d16, [x2, -119] + __ strs(v25, Address(r28, -124)); // str s25, [x28, -124] -// pre +// pre // LoadStoreOp - __ str(r11, Address(__ pre(r0, 8))); // str x11, [x0, 8]! - __ strw(r3, Address(__ pre(r0, 29))); // str w3, [x0, 29]! - __ strb(r11, Address(__ pre(r14, 9))); // strb w11, [x14, 9]! - __ strh(r29, Address(__ pre(r24, -3))); // strh w29, [x24, -3]! - __ ldr(r13, Address(__ pre(r17, -144))); // ldr x13, [x17, -144]! - __ ldrw(r12, Address(__ pre(r22, -6))); // ldr w12, [x22, -6]! - __ ldrb(r13, Address(__ pre(r12, -10))); // ldrb w13, [x12, -10]! - __ ldrh(r0, Address(__ pre(r21, -21))); // ldrh w0, [x21, -21]! - __ ldrsb(r23, Address(__ pre(r7, 4))); // ldrsb x23, [x7, 4]! - __ ldrsh(r3, Address(__ pre(r7, -53))); // ldrsh x3, [x7, -53]! - __ ldrshw(r28, Address(__ pre(r5, -7))); // ldrsh w28, [x5, -7]! - __ ldrsw(r24, Address(__ pre(r9, -18))); // ldrsw x24, [x9, -18]! - __ ldrd(v14, Address(__ pre(r11, 12))); // ldr d14, [x11, 12]! - __ ldrs(v19, Address(__ pre(r12, -67))); // ldr s19, [x12, -67]! - __ strd(v20, Address(__ pre(r0, -253))); // str d20, [x0, -253]! - __ strs(v8, Address(__ pre(r0, 64))); // str s8, [x0, 64]! + __ str(r28, Address(__ pre(r19, 82))); // str x28, [x19, 82]! + __ strw(r7, Address(__ pre(r13, 50))); // str w7, [x13, 50]! + __ strb(r2, Address(__ pre(r19, -32))); // strb w2, [x19, -32]! + __ strh(r24, Address(__ pre(r1, -58))); // strh w24, [x1, -58]! + __ ldr(r23, Address(__ pre(r29, -143))); // ldr x23, [x29, -143]! + __ ldrw(r13, Address(__ pre(r27, 0))); // ldr w13, [x27, 0]! + __ ldrb(r11, Address(__ pre(r10, -26))); // ldrb w11, [x10, -26]! + __ ldrh(r3, Address(__ pre(r6, -54))); // ldrh w3, [x6, -54]! + __ ldrsb(r2, Address(__ pre(r9, 3))); // ldrsb x2, [x9, 3]! + __ ldrsh(r28, Address(__ pre(r4, 30))); // ldrsh x28, [x4, 30]! + __ ldrshw(r17, Address(__ pre(r0, -23))); // ldrsh w17, [x0, -23]! + __ ldrsw(r29, Address(__ pre(r25, -117))); // ldrsw x29, [x25, -117]! + __ ldrd(v21, Address(__ pre(r10, -142))); // ldr d21, [x10, -142]! + __ ldrs(v11, Address(__ pre(r20, 35))); // ldr s11, [x20, 35]! + __ strd(v1, Address(__ pre(r15, -214))); // str d1, [x15, -214]! + __ strs(v19, Address(__ pre(r5, -55))); // str s19, [x5, -55]! -// post +// post // LoadStoreOp - __ str(r4, Address(__ post(r28, -94))); // str x4, [x28], -94 - __ strw(r12, Address(__ post(r7, -54))); // str w12, [x7], -54 - __ strb(r27, Address(__ post(r10, -24))); // strb w27, [x10], -24 - __ strh(r6, Address(__ post(r8, 27))); // strh w6, [x8], 27 - __ ldr(r14, Address(__ post(r10, -202))); // ldr x14, [x10], -202 - __ ldrw(r16, Address(__ post(r5, -41))); // ldr w16, [x5], -41 - __ ldrb(r2, Address(__ post(r14, 9))); // ldrb w2, [x14], 9 - __ ldrh(r28, Address(__ post(r13, -20))); // ldrh w28, [x13], -20 - __ ldrsb(r9, Address(__ post(r13, -31))); // ldrsb x9, [x13], -31 - __ ldrsh(r3, Address(__ post(r24, -36))); // ldrsh x3, [x24], -36 - __ ldrshw(r20, Address(__ post(r3, 6))); // ldrsh w20, [x3], 6 - __ ldrsw(r7, Address(__ post(r19, -1))); // ldrsw x7, [x19], -1 - __ ldrd(v30, Address(__ post(r8, -130))); // ldr d30, [x8], -130 - __ ldrs(v25, Address(__ post(r15, 21))); // ldr s25, [x15], 21 - __ strd(v14, Address(__ post(r23, 90))); // str d14, [x23], 90 - __ strs(v8, Address(__ post(r0, -33))); // str s8, [x0], -33 + __ str(r28, Address(__ post(r17, -20))); // str x28, [x17], -20 + __ strw(r8, Address(__ post(r13, -9))); // str w8, [x13], -9 + __ strb(r14, Address(__ post(r24, -23))); // strb w14, [x24], -23 + __ strh(r2, Address(__ post(r4, -60))); // strh w2, [x4], -60 + __ ldr(r24, Address(__ post(r25, 34))); // ldr x24, [x25], 34 + __ ldrw(r16, Address(__ post(r28, -27))); // ldr w16, [x28], -27 + __ ldrb(r8, Address(__ post(r23, -27))); // ldrb w8, [x23], -27 + __ ldrh(r3, Address(__ post(r0, -58))); // ldrh w3, [x0], -58 + __ ldrsb(r14, Address(__ post(r15, -10))); // ldrsb x14, [x15], -10 + __ ldrsh(r12, Address(__ post(r1, 13))); // ldrsh x12, [x1], 13 + __ ldrshw(r9, Address(__ post(r1, -19))); // ldrsh w9, [x1], -19 + __ ldrsw(r29, Address(__ post(r10, -61))); // ldrsw x29, [x10], -61 + __ ldrd(v13, Address(__ post(r28, -9))); // ldr d13, [x28], -9 + __ ldrs(v20, Address(__ post(r27, -88))); // ldr s20, [x27], -88 + __ strd(v7, Address(__ post(r11, -199))); // str d7, [x11], -199 + __ strs(v20, Address(__ post(r22, -61))); // str s20, [x22], -61 -// base_plus_reg +// base_plus_reg // LoadStoreOp - __ str(r10, Address(r18, r21, Address::sxtw(3))); // str x10, [x18, w21, sxtw #3] - __ strw(r4, Address(r13, r22, Address::sxtw(2))); // str w4, [x13, w22, sxtw #2] - __ strb(r13, Address(r0, r19, Address::uxtw(0))); // strb w13, [x0, w19, uxtw #0] - __ strh(r12, Address(r27, r6, Address::sxtw(0))); // strh w12, [x27, w6, sxtw #0] - __ ldr(r0, Address(r8, r16, Address::lsl(0))); // ldr x0, [x8, x16, lsl #0] - __ ldrw(r0, Address(r4, r26, Address::sxtx(0))); // ldr w0, [x4, x26, sxtx #0] - __ ldrb(r14, Address(r25, r5, Address::sxtw(0))); // ldrb w14, [x25, w5, sxtw #0] - __ ldrh(r9, Address(r4, r18, Address::uxtw(0))); // ldrh w9, [x4, w18, uxtw #0] - __ ldrsb(r27, Address(r4, r7, Address::lsl(0))); // ldrsb x27, [x4, x7, lsl #0] - __ ldrsh(r15, Address(r17, r30, Address::sxtw(0))); // ldrsh x15, [x17, w30, sxtw #0] - __ ldrshw(r16, Address(r0, r22, Address::sxtw(0))); // ldrsh w16, [x0, w22, sxtw #0] - __ ldrsw(r22, Address(r10, r30, Address::sxtx(2))); // ldrsw x22, [x10, x30, sxtx #2] - __ ldrd(v29, Address(r21, r10, Address::sxtx(3))); // ldr d29, [x21, x10, sxtx #3] - __ ldrs(v3, Address(r11, r19, Address::uxtw(0))); // ldr s3, [x11, w19, uxtw #0] - __ strd(v13, Address(r28, r29, Address::uxtw(3))); // str d13, [x28, w29, uxtw #3] - __ strs(v23, Address(r29, r5, Address::sxtx(2))); // str s23, [x29, x5, sxtx #2] + __ str(r3, Address(r10, r16, Address::sxtw(0))); // str x3, [x10, w16, sxtw #0] + __ strw(r1, Address(r29, r21, Address::lsl(2))); // str w1, [x29, x21, lsl #2] + __ strb(r26, Address(r0, r23, Address::uxtw(0))); // strb w26, [x0, w23, uxtw #0] + __ strh(r26, Address(r0, r21, Address::lsl(0))); // strh w26, [x0, x21, lsl #0] + __ ldr(r3, Address(r25, r22, Address::lsl(0))); // ldr x3, [x25, x22, lsl #0] + __ ldrw(r25, Address(r9, r24, Address::uxtw(2))); // ldr w25, [x9, w24, uxtw #2] + __ ldrb(r10, Address(r0, r14, Address::sxtw(0))); // ldrb w10, [x0, w14, sxtw #0] + __ ldrh(r2, Address(r21, r20, Address::lsl(1))); // ldrh w2, [x21, x20, lsl #1] + __ ldrsb(r19, Address(r27, r28, Address::sxtx(0))); // ldrsb x19, [x27, x28, sxtx #0] + __ ldrsh(r1, Address(r8, r3, Address::lsl(1))); // ldrsh x1, [x8, x3, lsl #1] + __ ldrshw(r20, Address(r15, r16, Address::sxtx(0))); // ldrsh w20, [x15, x16, sxtx #0] + __ ldrsw(r7, Address(r7, r12, Address::lsl(2))); // ldrsw x7, [x7, x12, lsl #2] + __ ldrd(v15, Address(r4, r13, Address::sxtw(3))); // ldr d15, [x4, w13, sxtw #3] + __ ldrs(v14, Address(r10, r3, Address::uxtw(0))); // ldr s14, [x10, w3, uxtw #0] + __ strd(v24, Address(r23, r9, Address::sxtx(3))); // str d24, [x23, x9, sxtx #3] + __ strs(v9, Address(r12, r26, Address::uxtw(2))); // str s9, [x12, w26, uxtw #2] -// base_plus_scaled_offset +// base_plus_scaled_offset // LoadStoreOp - __ str(r5, Address(r8, 12600)); // str x5, [x8, 12600] - __ strw(r29, Address(r24, 7880)); // str w29, [x24, 7880] - __ strb(r19, Address(r17, 1566)); // strb w19, [x17, 1566] - __ strh(r13, Address(r19, 3984)); // strh w13, [x19, 3984] - __ ldr(r19, Address(r23, 13632)); // ldr x19, [x23, 13632] - __ ldrw(r23, Address(r29, 6264)); // ldr w23, [x29, 6264] - __ ldrb(r22, Address(r11, 2012)); // ldrb w22, [x11, 2012] - __ ldrh(r3, Address(r10, 3784)); // ldrh w3, [x10, 3784] - __ ldrsb(r8, Address(r16, 1951)); // ldrsb x8, [x16, 1951] - __ ldrsh(r23, Address(r20, 3346)); // ldrsh x23, [x20, 3346] - __ ldrshw(r2, Address(r1, 3994)); // ldrsh w2, [x1, 3994] - __ ldrsw(r4, Address(r17, 7204)); // ldrsw x4, [x17, 7204] - __ ldrd(v20, Address(r27, 14400)); // ldr d20, [x27, 14400] - __ ldrs(v25, Address(r14, 8096)); // ldr s25, [x14, 8096] - __ strd(v26, Address(r10, 15024)); // str d26, [x10, 15024] - __ strs(v9, Address(r3, 6936)); // str s9, [x3, 6936] + __ str(r14, Address(r24, 13472)); // str x14, [x24, 13472] + __ strw(r0, Address(r14, 7392)); // str w0, [x14, 7392] + __ strb(r23, Address(r19, 1536)); // strb w23, [x19, 1536] + __ strh(r15, Address(r11, 3608)); // strh w15, [x11, 3608] + __ ldr(r21, Address(r25, 13672)); // ldr x21, [x25, 13672] + __ ldrw(r23, Address(r7, 6160)); // ldr w23, [x7, 6160] + __ ldrb(r23, Address(r16, 1975)); // ldrb w23, [x16, 1975] + __ ldrh(r24, Address(r24, 3850)); // ldrh w24, [x24, 3850] + __ ldrsb(r12, Address(r9, 1613)); // ldrsb x12, [x9, 1613] + __ ldrsh(r5, Address(r21, 3840)); // ldrsh x5, [x21, 3840] + __ ldrshw(r14, Address(r0, 3590)); // ldrsh w14, [x0, 3590] + __ ldrsw(r13, Address(r2, 7928)); // ldrsw x13, [x2, 7928] + __ ldrd(v15, Address(r19, 15800)); // ldr d15, [x19, 15800] + __ ldrs(v23, Address(r5, 6272)); // ldr s23, [x5, 6272] + __ strd(v6, Address(r6, 15136)); // str d6, [x6, 15136] + __ strs(v9, Address(r11, 6180)); // str s9, [x11, 6180] -// pcrel +// pcrel // LoadStoreOp - __ ldr(r27, forth); // ldr x27, forth - __ ldrw(r11, __ pc()); // ldr w11, . + __ ldr(r7, forth); // ldr x7, forth + __ ldrw(r29, __ pc()); // ldr w29, . // LoadStoreOp - __ prfm(Address(r3, -187)); // prfm PLDL1KEEP, [x3, -187] + __ prfm(Address(r0, -215)); // prfm PLDL1KEEP, [x0, -215] // LoadStoreOp - __ prfm(__ pc()); // prfm PLDL1KEEP, . + __ prfm(forth); // prfm PLDL1KEEP, forth // LoadStoreOp - __ prfm(Address(r29, r14, Address::lsl(0))); // prfm PLDL1KEEP, [x29, x14, lsl #0] + __ prfm(Address(r4, r3, Address::uxtw(0))); // prfm PLDL1KEEP, [x4, w3, uxtw #0] // LoadStoreOp - __ prfm(Address(r4, 13312)); // prfm PLDL1KEEP, [x4, 13312] + __ prfm(Address(r14, 12360)); // prfm PLDL1KEEP, [x14, 12360] // AddSubCarryOp - __ adcw(r21, r1, r7); // adc w21, w1, w7 - __ adcsw(r8, r5, r7); // adcs w8, w5, w7 - __ sbcw(r7, r27, r14); // sbc w7, w27, w14 - __ sbcsw(r27, r4, r17); // sbcs w27, w4, w17 - __ adc(r0, r28, r0); // adc x0, x28, x0 - __ adcs(r12, r24, r30); // adcs x12, x24, x30 - __ sbc(r0, r25, r15); // sbc x0, x25, x15 - __ sbcs(r1, r24, r3); // sbcs x1, x24, x3 + __ adcw(r7, r6, r4); // adc w7, w6, w4 + __ adcsw(r27, r12, r5); // adcs w27, w12, w5 + __ sbcw(r25, r24, r26); // sbc w25, w24, w26 + __ sbcsw(r5, r7, r23); // sbcs w5, w7, w23 + __ adc(r22, r11, r1); // adc x22, x11, x1 + __ adcs(r13, r9, r29); // adcs x13, x9, x29 + __ sbc(r4, r14, r26); // sbc x4, x14, x26 + __ sbcs(r28, r29, r24); // sbcs x28, x29, x24 // AddSubExtendedOp - __ addw(r18, r24, r20, ext::uxtb, 2); // add w18, w24, w20, uxtb #2 - __ addsw(r13, r28, r10, ext::uxth, 1); // adds w13, w28, w10, uxth #1 - __ sub(r15, r16, r2, ext::sxth, 2); // sub x15, x16, x2, sxth #2 - __ subsw(r29, r13, r13, ext::uxth, 2); // subs w29, w13, w13, uxth #2 - __ add(r12, r20, r12, ext::sxtw, 3); // add x12, x20, x12, sxtw #3 - __ adds(r30, r27, r11, ext::sxtb, 1); // adds x30, x27, x11, sxtb #1 - __ sub(r14, r7, r1, ext::sxtw, 2); // sub x14, x7, x1, sxtw #2 - __ subs(r29, r3, r27, ext::sxth, 1); // subs x29, x3, x27, sxth #1 + __ addw(r17, r21, r21, ext::uxtw, 1); // add w17, w21, w21, uxtw #1 + __ addsw(r12, r9, r26, ext::sxth, 3); // adds w12, w9, w26, sxth #3 + __ sub(r14, r5, r3, ext::uxth, 1); // sub x14, x5, x3, uxth #1 + __ subsw(r17, r26, r6, ext::uxtx, 4); // subs w17, w26, w6, uxtx #4 + __ add(r17, r5, r20, ext::sxth, 3); // add x17, x5, x20, sxth #3 + __ adds(r16, r1, r25, ext::sxtw, 3); // adds x16, x1, x25, sxtw #3 + __ sub(r25, r1, r26, ext::sxtx, 3); // sub x25, x1, x26, sxtx #3 + __ subs(r19, r1, r23, ext::sxth, 3); // subs x19, x1, x23, sxth #3 // ConditionalCompareOp - __ ccmnw(r0, r13, 14u, Assembler::MI); // ccmn w0, w13, #14, MI - __ ccmpw(r22, r18, 6u, Assembler::CC); // ccmp w22, w18, #6, CC - __ ccmn(r18, r30, 14u, Assembler::VS); // ccmn x18, x30, #14, VS - __ ccmp(r10, r19, 12u, Assembler::HI); // ccmp x10, x19, #12, HI + __ ccmnw(r1, r24, 9u, Assembler::LS); // ccmn w1, w24, #9, LS + __ ccmpw(r14, r10, 4u, Assembler::GT); // ccmp w14, w10, #4, GT + __ ccmn(r9, r29, 0u, Assembler::CC); // ccmn x9, x29, #0, CC + __ ccmp(r6, r6, 13u, Assembler::MI); // ccmp x6, x6, #13, MI // ConditionalCompareImmedOp - __ ccmnw(r6, 18, 2, Assembler::LE); // ccmn w6, #18, #2, LE - __ ccmpw(r9, 13, 4, Assembler::HI); // ccmp w9, #13, #4, HI - __ ccmn(r21, 11, 11, Assembler::LO); // ccmn x21, #11, #11, LO - __ ccmp(r4, 13, 2, Assembler::VC); // ccmp x4, #13, #2, VC + __ ccmnw(r19, 11, 5, Assembler::NE); // ccmn w19, #11, #5, NE + __ ccmpw(r11, 31, 15, Assembler::GE); // ccmp w11, #31, #15, GE + __ ccmn(r12, 14, 5, Assembler::VS); // ccmn x12, #14, #5, VS + __ ccmp(r1, 7, 10, Assembler::MI); // ccmp x1, #7, #10, MI // ConditionalSelectOp - __ cselw(r12, r2, r22, Assembler::HI); // csel w12, w2, w22, HI - __ csincw(r24, r16, r17, Assembler::HS); // csinc w24, w16, w17, HS - __ csinvw(r6, r7, r16, Assembler::LT); // csinv w6, w7, w16, LT - __ csnegw(r11, r27, r22, Assembler::LS); // csneg w11, w27, w22, LS - __ csel(r10, r3, r29, Assembler::LT); // csel x10, x3, x29, LT - __ csinc(r12, r26, r27, Assembler::CC); // csinc x12, x26, x27, CC - __ csinv(r15, r10, r21, Assembler::GT); // csinv x15, x10, x21, GT - __ csneg(r30, r23, r9, Assembler::GT); // csneg x30, x23, x9, GT + __ cselw(r6, r2, r22, Assembler::LO); // csel w6, w2, w22, LO + __ csincw(r29, r22, r26, Assembler::VS); // csinc w29, w22, w26, VS + __ csinvw(r26, r25, r11, Assembler::LS); // csinv w26, w25, w11, LS + __ csnegw(r19, r14, r16, Assembler::GT); // csneg w19, w14, w16, GT + __ csel(r13, r21, r20, Assembler::CS); // csel x13, x21, x20, CS + __ csinc(r12, r11, r27, Assembler::HI); // csinc x12, x11, x27, HI + __ csinv(r3, r17, r19, Assembler::LE); // csinv x3, x17, x19, LE + __ csneg(r24, r1, r7, Assembler::VS); // csneg x24, x1, x7, VS // TwoRegOp - __ rbitw(r30, r10); // rbit w30, w10 - __ rev16w(r29, r15); // rev16 w29, w15 - __ revw(r29, r30); // rev w29, w30 - __ clzw(r25, r21); // clz w25, w21 - __ clsw(r4, r0); // cls w4, w0 - __ rbit(r18, r21); // rbit x18, x21 - __ rev16(r29, r16); // rev16 x29, x16 - __ rev32(r21, r20); // rev32 x21, x20 - __ rev(r6, r19); // rev x6, x19 - __ clz(r30, r3); // clz x30, x3 - __ cls(r21, r19); // cls x21, x19 + __ rbitw(r23, r1); // rbit w23, w1 + __ rev16w(r16, r16); // rev16 w16, w16 + __ revw(r24, r25); // rev w24, w25 + __ clzw(r25, r8); // clz w25, w8 + __ clsw(r27, r12); // cls w27, w12 + __ rbit(r21, r5); // rbit x21, x5 + __ rev16(r20, r9); // rev16 x20, x9 + __ rev32(r20, r9); // rev32 x20, x9 + __ rev(r19, r10); // rev x19, x10 + __ clz(r8, r2); // clz x8, x2 + __ cls(r29, r3); // cls x29, x3 // ThreeRegOp - __ udivw(r11, r24, r0); // udiv w11, w24, w0 - __ sdivw(r27, r25, r14); // sdiv w27, w25, w14 - __ lslvw(r3, r14, r18); // lslv w3, w14, w18 - __ lsrvw(r7, r15, r24); // lsrv w7, w15, w24 - __ asrvw(r28, r17, r25); // asrv w28, w17, w25 - __ rorvw(r2, r26, r28); // rorv w2, w26, w28 - __ udiv(r5, r25, r26); // udiv x5, x25, x26 - __ sdiv(r27, r16, r18); // sdiv x27, x16, x18 - __ lslv(r6, r21, r12); // lslv x6, x21, x12 - __ lsrv(r0, r4, r12); // lsrv x0, x4, x12 - __ asrv(r27, r17, r28); // asrv x27, x17, x28 - __ rorv(r28, r2, r18); // rorv x28, x2, x18 - __ umulh(r10, r15, r14); // umulh x10, x15, x14 - __ smulh(r14, r3, r25); // smulh x14, x3, x25 + __ udivw(r19, r7, r29); // udiv w19, w7, w29 + __ sdivw(r26, r27, r10); // sdiv w26, w27, w10 + __ lslvw(r0, r24, r16); // lslv w0, w24, w16 + __ lsrvw(r22, r10, r24); // lsrv w22, w10, w24 + __ asrvw(r0, r26, r16); // asrv w0, w26, w16 + __ rorvw(r27, r25, r15); // rorv w27, w25, w15 + __ udiv(r8, r28, r15); // udiv x8, x28, x15 + __ sdiv(r20, r11, r5); // sdiv x20, x11, x5 + __ lslv(r21, r25, r16); // lslv x21, x25, x16 + __ lsrv(r7, r2, r14); // lsrv x7, x2, x14 + __ asrv(r21, r8, r22); // asrv x21, x8, x22 + __ rorv(r7, r5, r15); // rorv x7, x5, x15 + __ umulh(r12, r21, r22); // umulh x12, x21, x22 + __ smulh(r16, r10, r5); // smulh x16, x10, x5 // FourRegMulOp - __ maddw(r15, r19, r14, r5); // madd w15, w19, w14, w5 - __ msubw(r16, r4, r26, r25); // msub w16, w4, w26, w25 - __ madd(r4, r2, r2, r12); // madd x4, x2, x2, x12 - __ msub(r29, r17, r8, r7); // msub x29, x17, x8, x7 - __ smaddl(r3, r4, r25, r4); // smaddl x3, w4, w25, x4 - __ smsubl(r26, r25, r4, r17); // smsubl x26, w25, w4, x17 - __ umaddl(r0, r26, r17, r23); // umaddl x0, w26, w17, x23 - __ umsubl(r15, r21, r28, r17); // umsubl x15, w21, w28, x17 + __ maddw(r2, r6, r26, r21); // madd w2, w6, w26, w21 + __ msubw(r27, r19, r3, r27); // msub w27, w19, w3, w27 + __ madd(r27, r5, r8, r3); // madd x27, x5, x8, x3 + __ msub(r8, r13, r28, r13); // msub x8, x13, x28, x13 + __ smaddl(r29, r9, r8, r0); // smaddl x29, w9, w8, x0 + __ smsubl(r14, r9, r14, r23); // smsubl x14, w9, w14, x23 + __ umaddl(r15, r4, r11, r13); // umaddl x15, w4, w11, x13 + __ umsubl(r23, r3, r17, r24); // umsubl x23, w3, w17, x24 // ThreeRegFloatOp - __ fmuls(v27, v10, v3); // fmul s27, s10, s3 - __ fdivs(v0, v7, v25); // fdiv s0, s7, s25 - __ fadds(v9, v6, v15); // fadd s9, s6, s15 - __ fsubs(v29, v15, v10); // fsub s29, s15, s10 - __ fmuls(v2, v17, v7); // fmul s2, s17, s7 - __ fmuld(v11, v11, v23); // fmul d11, d11, d23 - __ fdivd(v7, v29, v23); // fdiv d7, d29, d23 - __ faddd(v14, v27, v11); // fadd d14, d27, d11 - __ fsubd(v11, v4, v24); // fsub d11, d4, d24 - __ fmuld(v12, v15, v14); // fmul d12, d15, d14 + __ fmuls(v29, v1, v17); // fmul s29, s1, s17 + __ fdivs(v23, v28, v9); // fdiv s23, s28, s9 + __ fadds(v14, v19, v12); // fadd s14, s19, s12 + __ fsubs(v27, v17, v0); // fsub s27, s17, s0 + __ fmuls(v16, v24, v6); // fmul s16, s24, s6 + __ fmuld(v4, v23, v10); // fmul d4, d23, d10 + __ fdivd(v11, v9, v23); // fdiv d11, d9, d23 + __ faddd(v7, v15, v7); // fadd d7, d15, d7 + __ fsubd(v29, v21, v12); // fsub d29, d21, d12 + __ fmuld(v27, v4, v9); // fmul d27, d4, d9 // FourRegFloatOp - __ fmadds(v20, v11, v28, v13); // fmadd s20, s11, s28, s13 - __ fmsubs(v11, v12, v23, v30); // fmsub s11, s12, s23, s30 - __ fnmadds(v26, v14, v9, v13); // fnmadd s26, s14, s9, s13 - __ fnmadds(v10, v7, v5, v29); // fnmadd s10, s7, s5, s29 - __ fmaddd(v15, v3, v11, v12); // fmadd d15, d3, d11, d12 - __ fmsubd(v15, v30, v30, v17); // fmsub d15, d30, d30, d17 - __ fnmaddd(v19, v20, v15, v15); // fnmadd d19, d20, d15, d15 - __ fnmaddd(v9, v21, v2, v9); // fnmadd d9, d21, d2, d9 + __ fmadds(v27, v14, v11, v25); // fmadd s27, s14, s11, s25 + __ fmsubs(v11, v22, v15, v3); // fmsub s11, s22, s15, s3 + __ fnmadds(v10, v27, v24, v4); // fnmadd s10, s27, s24, s4 + __ fnmadds(v4, v6, v1, v1); // fnmadd s4, s6, s1, s1 + __ fmaddd(v13, v28, v3, v2); // fmadd d13, d28, d3, d2 + __ fmsubd(v26, v24, v7, v26); // fmsub d26, d24, d7, d26 + __ fnmaddd(v21, v5, v12, v26); // fnmadd d21, d5, d12, d26 + __ fnmaddd(v11, v16, v20, v3); // fnmadd d11, d16, d20, d3 // TwoRegFloatOp - __ fmovs(v27, v7); // fmov s27, s7 - __ fabss(v29, v30); // fabs s29, s30 - __ fnegs(v17, v1); // fneg s17, s1 - __ fsqrts(v2, v6); // fsqrt s2, s6 - __ fcvts(v10, v3); // fcvt d10, s3 - __ fmovd(v24, v11); // fmov d24, d11 - __ fabsd(v7, v1); // fabs d7, d1 - __ fnegd(v11, v0); // fneg d11, d0 - __ fsqrtd(v3, v18); // fsqrt d3, d18 - __ fcvtd(v28, v6); // fcvt s28, d6 + __ fmovs(v5, v17); // fmov s5, s17 + __ fabss(v7, v9); // fabs s7, s9 + __ fnegs(v25, v1); // fneg s25, s1 + __ fsqrts(v24, v6); // fsqrt s24, s6 + __ fcvts(v27, v17); // fcvt d27, s17 + __ fmovd(v22, v2); // fmov d22, d2 + __ fabsd(v14, v20); // fabs d14, d20 + __ fnegd(v29, v11); // fneg d29, d11 + __ fsqrtd(v28, v12); // fsqrt d28, d12 + __ fcvtd(v4, v3); // fcvt s4, d3 // FloatConvertOp - __ fcvtzsw(r22, v6); // fcvtzs w22, s6 - __ fcvtzs(r0, v27); // fcvtzs x0, s27 - __ fcvtzdw(r26, v2); // fcvtzs w26, d2 - __ fcvtzd(r5, v7); // fcvtzs x5, d7 - __ scvtfws(v28, r11); // scvtf s28, w11 - __ scvtfs(v25, r13); // scvtf s25, x13 - __ scvtfwd(v11, r23); // scvtf d11, w23 - __ scvtfd(v19, r8); // scvtf d19, x8 - __ fmovs(r18, v21); // fmov w18, s21 - __ fmovd(r25, v20); // fmov x25, d20 - __ fmovs(v19, r18); // fmov s19, w18 - __ fmovd(v2, r29); // fmov d2, x29 + __ fcvtzsw(r28, v13); // fcvtzs w28, s13 + __ fcvtzs(r7, v28); // fcvtzs x7, s28 + __ fcvtzdw(r12, v15); // fcvtzs w12, d15 + __ fcvtzd(r11, v6); // fcvtzs x11, d6 + __ scvtfws(v22, r22); // scvtf s22, w22 + __ scvtfs(v5, r16); // scvtf s5, x16 + __ scvtfwd(v3, r15); // scvtf d3, w15 + __ scvtfd(v6, r8); // scvtf d6, x8 + __ fmovs(r26, v29); // fmov w26, s29 + __ fmovd(r24, v17); // fmov x24, d17 + __ fmovs(v2, r19); // fmov s2, w19 + __ fmovd(v21, r5); // fmov d21, x5 // TwoRegFloatOp - __ fcmps(v22, v8); // fcmp s22, s8 - __ fcmpd(v21, v19); // fcmp d21, d19 - __ fcmps(v20, 0.0); // fcmp s20, #0.0 - __ fcmpd(v11, 0.0); // fcmp d11, #0.0 + __ fcmps(v23, v8); // fcmp s23, s8 + __ fcmpd(v12, v2); // fcmp d12, d2 + __ fcmps(v14, 0.0); // fcmp s14, #0.0 + __ fcmpd(v10, 0.0); // fcmp d10, #0.0 // LoadStorePairOp - __ stpw(r20, r6, Address(r15, -32)); // stp w20, w6, [x15, #-32] - __ ldpw(r27, r14, Address(r3, -208)); // ldp w27, w14, [x3, #-208] - __ ldpsw(r17, r10, Address(r11, -80)); // ldpsw x17, x10, [x11, #-80] - __ stp(r7, r7, Address(r14, 64)); // stp x7, x7, [x14, #64] - __ ldp(r12, r23, Address(r0, 112)); // ldp x12, x23, [x0, #112] + __ stpw(r8, r17, Address(r12, -96)); // stp w8, w17, [x12, #-96] + __ ldpw(r1, r21, Address(r28, -192)); // ldp w1, w21, [x28, #-192] + __ ldpsw(r25, r22, Address(r16, -64)); // ldpsw x25, x22, [x16, #-64] + __ stp(r6, r8, Address(r23, -128)); // stp x6, x8, [x23, #-128] + __ ldp(r25, r16, Address(r19, -112)); // ldp x25, x16, [x19, #-112] // LoadStorePairOp - __ stpw(r13, r7, Address(__ pre(r6, -80))); // stp w13, w7, [x6, #-80]! - __ ldpw(r30, r16, Address(__ pre(r2, -144))); // ldp w30, w16, [x2, #-144]! - __ ldpsw(r4, r1, Address(__ pre(r26, -144))); // ldpsw x4, x1, [x26, #-144]! - __ stp(r23, r14, Address(__ pre(r11, 64))); // stp x23, x14, [x11, #64]! - __ ldp(r29, r27, Address(__ pre(r21, -192))); // ldp x29, x27, [x21, #-192]! + __ stpw(r29, r27, Address(__ pre(r13, -240))); // stp w29, w27, [x13, #-240]! + __ ldpw(r12, r20, Address(__ pre(r21, -32))); // ldp w12, w20, [x21, #-32]! + __ ldpsw(r0, r15, Address(__ pre(r4, -144))); // ldpsw x0, x15, [x4, #-144]! + __ stp(r13, r12, Address(__ pre(r19, 128))); // stp x13, x12, [x19, #128]! + __ ldp(r25, r2, Address(__ pre(r9, 96))); // ldp x25, x2, [x9, #96]! // LoadStorePairOp - __ stpw(r22, r5, Address(__ post(r21, -48))); // stp w22, w5, [x21], #-48 - __ ldpw(r27, r17, Address(__ post(r6, -32))); // ldp w27, w17, [x6], #-32 - __ ldpsw(r17, r6, Address(__ post(r1, -80))); // ldpsw x17, x6, [x1], #-80 - __ stp(r13, r20, Address(__ post(r21, -208))); // stp x13, x20, [x21], #-208 - __ ldp(r30, r27, Address(__ post(r10, 80))); // ldp x30, x27, [x10], #80 + __ stpw(r11, r1, Address(__ post(r26, 128))); // stp w11, w1, [x26], #128 + __ ldpw(r26, r25, Address(__ post(r3, 32))); // ldp w26, w25, [x3], #32 + __ ldpsw(r10, r14, Address(__ post(r2, -240))); // ldpsw x10, x14, [x2], #-240 + __ stp(r1, r3, Address(__ post(r10, 128))); // stp x1, x3, [x10], #128 + __ ldp(r23, r12, Address(__ post(r25, -144))); // ldp x23, x12, [x25], #-144 // LoadStorePairOp - __ stnpw(r5, r17, Address(r11, 16)); // stnp w5, w17, [x11, #16] - __ ldnpw(r14, r4, Address(r26, -96)); // ldnp w14, w4, [x26, #-96] - __ stnp(r23, r29, Address(r12, 32)); // stnp x23, x29, [x12, #32] - __ ldnp(r0, r6, Address(r21, -80)); // ldnp x0, x6, [x21, #-80] + __ stnpw(r5, r8, Address(r25, 64)); // stnp w5, w8, [x25, #64] + __ ldnpw(r20, r19, Address(r22, -240)); // ldnp w20, w19, [x22, #-240] + __ stnp(r23, r7, Address(r14, -176)); // stnp x23, x7, [x14, #-176] + __ ldnp(r14, r28, Address(r21, 64)); // ldnp x14, x28, [x21, #64] // LdStSIMDOp - __ ld1(v15, __ T8B, Address(r26)); // ld1 {v15.8B}, [x26] - __ ld1(v23, v24, __ T16B, Address(__ post(r11, 32))); // ld1 {v23.16B, v24.16B}, [x11], 32 - __ ld1(v8, v9, v10, __ T1D, Address(__ post(r23, r7))); // ld1 {v8.1D, v9.1D, v10.1D}, [x23], x7 - __ ld1(v19, v20, v21, v22, __ T8H, Address(__ post(r25, 64))); // ld1 {v19.8H, v20.8H, v21.8H, v22.8H}, [x25], 64 - __ ld1r(v29, __ T8B, Address(r17)); // ld1r {v29.8B}, [x17] - __ ld1r(v24, __ T4S, Address(__ post(r23, 4))); // ld1r {v24.4S}, [x23], 4 - __ ld1r(v10, __ T1D, Address(__ post(r5, r25))); // ld1r {v10.1D}, [x5], x25 - __ ld2(v18, v19, __ T2D, Address(r10)); // ld2 {v18.2D, v19.2D}, [x10] - __ ld2(v12, v13, __ T4H, Address(__ post(r15, 16))); // ld2 {v12.4H, v13.4H}, [x15], 16 - __ ld2r(v25, v26, __ T16B, Address(r18)); // ld2r {v25.16B, v26.16B}, [x18] - __ ld2r(v1, v2, __ T2S, Address(__ post(r30, 8))); // ld2r {v1.2S, v2.2S}, [x30], 8 - __ ld2r(v16, v17, __ T2D, Address(__ post(r18, r9))); // ld2r {v16.2D, v17.2D}, [x18], x9 - __ ld3(v25, v26, v27, __ T4S, Address(__ post(r12, r2))); // ld3 {v25.4S, v26.4S, v27.4S}, [x12], x2 - __ ld3(v26, v27, v28, __ T2S, Address(r19)); // ld3 {v26.2S, v27.2S, v28.2S}, [x19] - __ ld3r(v15, v16, v17, __ T8H, Address(r21)); // ld3r {v15.8H, v16.8H, v17.8H}, [x21] - __ ld3r(v25, v26, v27, __ T4S, Address(__ post(r13, 12))); // ld3r {v25.4S, v26.4S, v27.4S}, [x13], 12 - __ ld3r(v14, v15, v16, __ T1D, Address(__ post(r28, r29))); // ld3r {v14.1D, v15.1D, v16.1D}, [x28], x29 - __ ld4(v17, v18, v19, v20, __ T8H, Address(__ post(r29, 64))); // ld4 {v17.8H, v18.8H, v19.8H, v20.8H}, [x29], 64 - __ ld4(v27, v28, v29, v30, __ T8B, Address(__ post(r7, r0))); // ld4 {v27.8B, v28.8B, v29.8B, v30.8B}, [x7], x0 - __ ld4r(v24, v25, v26, v27, __ T8B, Address(r18)); // ld4r {v24.8B, v25.8B, v26.8B, v27.8B}, [x18] - __ ld4r(v0, v1, v2, v3, __ T4H, Address(__ post(r26, 8))); // ld4r {v0.4H, v1.4H, v2.4H, v3.4H}, [x26], 8 - __ ld4r(v12, v13, v14, v15, __ T2S, Address(__ post(r25, r2))); // ld4r {v12.2S, v13.2S, v14.2S, v15.2S}, [x25], x2 - -// SHA512SIMDOp - __ sha512h(v22, __ T2D, v27, v4); // sha512h q22, q27, v4.2D - __ sha512h2(v7, __ T2D, v6, v1); // sha512h2 q7, q6, v1.2D - __ sha512su0(v26, __ T2D, v15); // sha512su0 v26.2D, v15.2D - __ sha512su1(v2, __ T2D, v13, v13); // sha512su1 v2.2D, v13.2D, v13.2D + __ ld1(v10, __ T8B, Address(r4)); // ld1 {v10.8B}, [x4] + __ ld1(v25, v26, __ T16B, Address(__ post(r26, 32))); // ld1 {v25.16B, v26.16B}, [x26], 32 + __ ld1(v27, v28, v29, __ T1D, Address(__ post(r4, r23))); // ld1 {v27.1D, v28.1D, v29.1D}, [x4], x23 + __ ld1(v16, v17, v18, v19, __ T8H, Address(__ post(r6, 64))); // ld1 {v16.8H, v17.8H, v18.8H, v19.8H}, [x6], 64 + __ ld1r(v1, __ T8B, Address(r27)); // ld1r {v1.8B}, [x27] + __ ld1r(v4, __ T4S, Address(__ post(r2, 4))); // ld1r {v4.4S}, [x2], 4 + __ ld1r(v21, __ T1D, Address(__ post(r29, r15))); // ld1r {v21.1D}, [x29], x15 + __ ld2(v1, v2, __ T2D, Address(r22)); // ld2 {v1.2D, v2.2D}, [x22] + __ ld2(v29, v30, __ T4H, Address(__ post(r8, 16))); // ld2 {v29.4H, v30.4H}, [x8], 16 + __ ld2r(v24, v25, __ T16B, Address(r4)); // ld2r {v24.16B, v25.16B}, [x4] + __ ld2r(v21, v22, __ T2S, Address(__ post(r19, 8))); // ld2r {v21.2S, v22.2S}, [x19], 8 + __ ld2r(v13, v14, __ T2D, Address(__ post(r13, r6))); // ld2r {v13.2D, v14.2D}, [x13], x6 + __ ld3(v1, v2, v3, __ T4S, Address(__ post(r4, r17))); // ld3 {v1.4S, v2.4S, v3.4S}, [x4], x17 + __ ld3(v22, v23, v24, __ T2S, Address(r17)); // ld3 {v22.2S, v23.2S, v24.2S}, [x17] + __ ld3r(v17, v18, v19, __ T8H, Address(r17)); // ld3r {v17.8H, v18.8H, v19.8H}, [x17] + __ ld3r(v8, v9, v10, __ T4S, Address(__ post(r28, 12))); // ld3r {v8.4S, v9.4S, v10.4S}, [x28], 12 + __ ld3r(v5, v6, v7, __ T1D, Address(__ post(r1, r19))); // ld3r {v5.1D, v6.1D, v7.1D}, [x1], x19 + __ ld4(v1, v2, v3, v4, __ T8H, Address(__ post(r15, 64))); // ld4 {v1.8H, v2.8H, v3.8H, v4.8H}, [x15], 64 + __ ld4(v17, v18, v19, v20, __ T8B, Address(__ post(r6, r26))); // ld4 {v17.8B, v18.8B, v19.8B, v20.8B}, [x6], x26 + __ ld4r(v25, v26, v27, v28, __ T8B, Address(r7)); // ld4r {v25.8B, v26.8B, v27.8B, v28.8B}, [x7] + __ ld4r(v12, v13, v14, v15, __ T4H, Address(__ post(r8, 8))); // ld4r {v12.4H, v13.4H, v14.4H, v15.4H}, [x8], 8 + __ ld4r(v9, v10, v11, v12, __ T2S, Address(__ post(r13, r1))); // ld4r {v9.2S, v10.2S, v11.2S, v12.2S}, [x13], x1 // SpecialCases - __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE - __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ - __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE - __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT - __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 - __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] - __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] - __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] - __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] - __ dup(v0, __ T16B, zr); // dup v0.16b, wzr - __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr - __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr - __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr - __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr - __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 + __ ccmn(zr, zr, 3u, Assembler::LE); // ccmn xzr, xzr, #3, LE + __ ccmnw(zr, zr, 5u, Assembler::EQ); // ccmn wzr, wzr, #5, EQ + __ ccmp(zr, 1, 4u, Assembler::NE); // ccmp xzr, 1, #4, NE + __ ccmpw(zr, 2, 2, Assembler::GT); // ccmp wzr, 2, #2, GT + __ extr(zr, zr, zr, 0); // extr xzr, xzr, xzr, 0 + __ stlxp(r0, zr, zr, sp); // stlxp w0, xzr, xzr, [sp] + __ stlxpw(r2, zr, zr, r3); // stlxp w2, wzr, wzr, [x3] + __ stxp(r4, zr, zr, r5); // stxp w4, xzr, xzr, [x5] + __ stxpw(r6, zr, zr, sp); // stxp w6, wzr, wzr, [sp] + __ dup(v0, __ T16B, zr); // dup v0.16b, wzr + __ mov(v1, __ T1D, 0, zr); // mov v1.d[0], xzr + __ mov(v1, __ T2S, 1, zr); // mov v1.s[1], wzr + __ mov(v1, __ T4H, 2, zr); // mov v1.h[2], wzr + __ mov(v1, __ T8B, 3, zr); // mov v1.b[3], wzr + __ ld1(v31, v0, __ T2D, Address(__ post(r1, r0))); // ld1 {v31.2d, v0.2d}, [x1], x0 // FloatImmediateOp - __ fmovd(v0, 2.0); // fmov d0, #2.0 - __ fmovd(v0, 2.125); // fmov d0, #2.125 - __ fmovd(v0, 4.0); // fmov d0, #4.0 - __ fmovd(v0, 4.25); // fmov d0, #4.25 - __ fmovd(v0, 8.0); // fmov d0, #8.0 - __ fmovd(v0, 8.5); // fmov d0, #8.5 - __ fmovd(v0, 16.0); // fmov d0, #16.0 - __ fmovd(v0, 17.0); // fmov d0, #17.0 - __ fmovd(v0, 0.125); // fmov d0, #0.125 - __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 - __ fmovd(v0, 0.25); // fmov d0, #0.25 - __ fmovd(v0, 0.265625); // fmov d0, #0.265625 - __ fmovd(v0, 0.5); // fmov d0, #0.5 - __ fmovd(v0, 0.53125); // fmov d0, #0.53125 - __ fmovd(v0, 1.0); // fmov d0, #1.0 - __ fmovd(v0, 1.0625); // fmov d0, #1.0625 - __ fmovd(v0, -2.0); // fmov d0, #-2.0 - __ fmovd(v0, -2.125); // fmov d0, #-2.125 - __ fmovd(v0, -4.0); // fmov d0, #-4.0 - __ fmovd(v0, -4.25); // fmov d0, #-4.25 - __ fmovd(v0, -8.0); // fmov d0, #-8.0 - __ fmovd(v0, -8.5); // fmov d0, #-8.5 - __ fmovd(v0, -16.0); // fmov d0, #-16.0 - __ fmovd(v0, -17.0); // fmov d0, #-17.0 - __ fmovd(v0, -0.125); // fmov d0, #-0.125 - __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 - __ fmovd(v0, -0.25); // fmov d0, #-0.25 - __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 - __ fmovd(v0, -0.5); // fmov d0, #-0.5 - __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 - __ fmovd(v0, -1.0); // fmov d0, #-1.0 - __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 + __ fmovd(v0, 2.0); // fmov d0, #2.0 + __ fmovd(v0, 2.125); // fmov d0, #2.125 + __ fmovd(v0, 4.0); // fmov d0, #4.0 + __ fmovd(v0, 4.25); // fmov d0, #4.25 + __ fmovd(v0, 8.0); // fmov d0, #8.0 + __ fmovd(v0, 8.5); // fmov d0, #8.5 + __ fmovd(v0, 16.0); // fmov d0, #16.0 + __ fmovd(v0, 17.0); // fmov d0, #17.0 + __ fmovd(v0, 0.125); // fmov d0, #0.125 + __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125 + __ fmovd(v0, 0.25); // fmov d0, #0.25 + __ fmovd(v0, 0.265625); // fmov d0, #0.265625 + __ fmovd(v0, 0.5); // fmov d0, #0.5 + __ fmovd(v0, 0.53125); // fmov d0, #0.53125 + __ fmovd(v0, 1.0); // fmov d0, #1.0 + __ fmovd(v0, 1.0625); // fmov d0, #1.0625 + __ fmovd(v0, -2.0); // fmov d0, #-2.0 + __ fmovd(v0, -2.125); // fmov d0, #-2.125 + __ fmovd(v0, -4.0); // fmov d0, #-4.0 + __ fmovd(v0, -4.25); // fmov d0, #-4.25 + __ fmovd(v0, -8.0); // fmov d0, #-8.0 + __ fmovd(v0, -8.5); // fmov d0, #-8.5 + __ fmovd(v0, -16.0); // fmov d0, #-16.0 + __ fmovd(v0, -17.0); // fmov d0, #-17.0 + __ fmovd(v0, -0.125); // fmov d0, #-0.125 + __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125 + __ fmovd(v0, -0.25); // fmov d0, #-0.25 + __ fmovd(v0, -0.265625); // fmov d0, #-0.265625 + __ fmovd(v0, -0.5); // fmov d0, #-0.5 + __ fmovd(v0, -0.53125); // fmov d0, #-0.53125 + __ fmovd(v0, -1.0); // fmov d0, #-1.0 + __ fmovd(v0, -1.0625); // fmov d0, #-1.0625 // LSEOp - __ swp(Assembler::xword, r24, r24, r4); // swp x24, x24, [x4] - __ ldadd(Assembler::xword, r20, r16, r0); // ldadd x20, x16, [x0] - __ ldbic(Assembler::xword, r4, r21, r11); // ldclr x4, x21, [x11] - __ ldeor(Assembler::xword, r30, r16, r22); // ldeor x30, x16, [x22] - __ ldorr(Assembler::xword, r4, r15, r23); // ldset x4, x15, [x23] - __ ldsmin(Assembler::xword, r26, r6, r12); // ldsmin x26, x6, [x12] - __ ldsmax(Assembler::xword, r15, r14, r15); // ldsmax x15, x14, [x15] - __ ldumin(Assembler::xword, r9, r25, r29); // ldumin x9, x25, [x29] - __ ldumax(Assembler::xword, r11, r20, r12); // ldumax x11, x20, [x12] + __ swp(Assembler::xword, r26, r3, r6); // swp x26, x3, [x6] + __ ldadd(Assembler::xword, r20, r12, r4); // ldadd x20, x12, [x4] + __ ldbic(Assembler::xword, r23, r4, r11); // ldclr x23, x4, [x11] + __ ldeor(Assembler::xword, r15, r15, r24); // ldeor x15, x15, [x24] + __ ldorr(Assembler::xword, r29, r2, r17); // ldset x29, x2, [x17] + __ ldsmin(Assembler::xword, r25, r5, r1); // ldsmin x25, x5, [x1] + __ ldsmax(Assembler::xword, r15, r15, r7); // ldsmax x15, x15, [x7] + __ ldumin(Assembler::xword, r28, zr, r29); // ldumin x28, xzr, [x29] + __ ldumax(Assembler::xword, r17, r17, sp); // ldumax x17, x17, [sp] // LSEOp - __ swpa(Assembler::xword, r18, r22, r16); // swpa x18, x22, [x16] - __ ldadda(Assembler::xword, r21, r24, r26); // ldadda x21, x24, [x26] - __ ldbica(Assembler::xword, r6, r6, r16); // ldclra x6, x6, [x16] - __ ldeora(Assembler::xword, r16, r25, r16); // ldeora x16, x25, [x16] - __ ldorra(Assembler::xword, r28, r24, r16); // ldseta x28, x24, [x16] - __ ldsmina(Assembler::xword, r26, r15, r10); // ldsmina x26, x15, [x10] - __ ldsmaxa(Assembler::xword, r13, r14, r20); // ldsmaxa x13, x14, [x20] - __ ldumina(Assembler::xword, r1, r23, r30); // ldumina x1, x23, [x30] - __ ldumaxa(Assembler::xword, r14, r2, r6); // ldumaxa x14, x2, [x6] + __ swpa(Assembler::xword, r7, r16, r21); // swpa x7, x16, [x21] + __ ldadda(Assembler::xword, r17, r10, r20); // ldadda x17, x10, [x20] + __ ldbica(Assembler::xword, r25, r14, r29); // ldclra x25, x14, [x29] + __ ldeora(Assembler::xword, r25, r13, r3); // ldeora x25, x13, [x3] + __ ldorra(Assembler::xword, r13, r7, r28); // ldseta x13, x7, [x28] + __ ldsmina(Assembler::xword, r20, r25, r7); // ldsmina x20, x25, [x7] + __ ldsmaxa(Assembler::xword, r21, r4, r2); // ldsmaxa x21, x4, [x2] + __ ldumina(Assembler::xword, r8, r5, r8); // ldumina x8, x5, [x8] + __ ldumaxa(Assembler::xword, r10, r12, r6); // ldumaxa x10, x12, [x6] // LSEOp - __ swpal(Assembler::xword, r3, r8, r25); // swpal x3, x8, [x25] - __ ldaddal(Assembler::xword, r0, r27, r30); // ldaddal x0, x27, [x30] - __ ldbical(Assembler::xword, r5, r5, r30); // ldclral x5, x5, [x30] - __ ldeoral(Assembler::xword, r11, r25, r0); // ldeoral x11, x25, [x0] - __ ldorral(Assembler::xword, zr, r0, r19); // ldsetal xzr, x0, [x19] - __ ldsminal(Assembler::xword, r29, r26, r9); // ldsminal x29, x26, [x9] - __ ldsmaxal(Assembler::xword, r26, r12, r15); // ldsmaxal x26, x12, [x15] - __ lduminal(Assembler::xword, r11, r11, r18); // lduminal x11, x11, [x18] - __ ldumaxal(Assembler::xword, r25, r22, r24); // ldumaxal x25, x22, [x24] + __ swpal(Assembler::xword, r25, r12, r10); // swpal x25, x12, [x10] + __ ldaddal(Assembler::xword, r12, r1, r4); // ldaddal x12, x1, [x4] + __ ldbical(Assembler::xword, r26, r6, r12); // ldclral x26, x6, [x12] + __ ldeoral(Assembler::xword, r1, r14, r12); // ldeoral x1, x14, [x12] + __ ldorral(Assembler::xword, r22, r6, r21); // ldsetal x22, x6, [x21] + __ ldsminal(Assembler::xword, r15, r4, r6); // ldsminal x15, x4, [x6] + __ ldsmaxal(Assembler::xword, r24, r16, r7); // ldsmaxal x24, x16, [x7] + __ lduminal(Assembler::xword, r5, r3, r11); // lduminal x5, x3, [x11] + __ ldumaxal(Assembler::xword, r22, r2, r25); // ldumaxal x22, x2, [x25] // LSEOp - __ swpl(Assembler::xword, r0, r17, r11); // swpl x0, x17, [x11] - __ ldaddl(Assembler::xword, r6, r29, r6); // ldaddl x6, x29, [x6] - __ ldbicl(Assembler::xword, r5, r5, r21); // ldclrl x5, x5, [x21] - __ ldeorl(Assembler::xword, r19, r16, r18); // ldeorl x19, x16, [x18] - __ ldorrl(Assembler::xword, r30, r27, r28); // ldsetl x30, x27, [x28] - __ ldsminl(Assembler::xword, r1, r28, r1); // ldsminl x1, x28, [x1] - __ ldsmaxl(Assembler::xword, r20, r29, r16); // ldsmaxl x20, x29, [x16] - __ lduminl(Assembler::xword, r13, r10, r29); // lduminl x13, x10, [x29] - __ ldumaxl(Assembler::xword, r29, r19, r22); // ldumaxl x29, x19, [x22] + __ swpl(Assembler::xword, r6, r29, r0); // swpl x6, x29, [x0] + __ ldaddl(Assembler::xword, r26, r6, r23); // ldaddl x26, x6, [x23] + __ ldbicl(Assembler::xword, r4, r7, r9); // ldclrl x4, x7, [x9] + __ ldeorl(Assembler::xword, r6, r11, r1); // ldeorl x6, x11, [x1] + __ ldorrl(Assembler::xword, r11, r13, r29); // ldsetl x11, x13, [x29] + __ ldsminl(Assembler::xword, r11, r3, r6); // ldsminl x11, x3, [x6] + __ ldsmaxl(Assembler::xword, r21, r0, r11); // ldsmaxl x21, x0, [x11] + __ lduminl(Assembler::xword, r11, r23, r9); // lduminl x11, x23, [x9] + __ ldumaxl(Assembler::xword, r17, r16, r16); // ldumaxl x17, x16, [x16] // LSEOp - __ swp(Assembler::word, r10, r4, sp); // swp w10, w4, [sp] - __ ldadd(Assembler::word, r21, r8, sp); // ldadd w21, w8, [sp] - __ ldbic(Assembler::word, r19, r10, r28); // ldclr w19, w10, [x28] - __ ldeor(Assembler::word, r2, r25, r5); // ldeor w2, w25, [x5] - __ ldorr(Assembler::word, r3, r8, r22); // ldset w3, w8, [x22] - __ ldsmin(Assembler::word, r19, r13, r5); // ldsmin w19, w13, [x5] - __ ldsmax(Assembler::word, r29, r24, r21); // ldsmax w29, w24, [x21] - __ ldumin(Assembler::word, r26, r24, r3); // ldumin w26, w24, [x3] - __ ldumax(Assembler::word, r24, r26, r23); // ldumax w24, w26, [x23] + __ swp(Assembler::word, r21, r5, sp); // swp w21, w5, [sp] + __ ldadd(Assembler::word, r24, r11, r4); // ldadd w24, w11, [x4] + __ ldbic(Assembler::word, r17, r29, r4); // ldclr w17, w29, [x4] + __ ldeor(Assembler::word, r15, r11, r15); // ldeor w15, w11, [x15] + __ ldorr(Assembler::word, r27, r26, r11); // ldset w27, w26, [x11] + __ ldsmin(Assembler::word, r27, r12, r8); // ldsmin w27, w12, [x8] + __ ldsmax(Assembler::word, r6, r20, r1); // ldsmax w6, w20, [x1] + __ ldumin(Assembler::word, r14, r16, r29); // ldumin w14, w16, [x29] + __ ldumax(Assembler::word, r24, r13, r26); // ldumax w24, w13, [x26] // LSEOp - __ swpa(Assembler::word, r15, r21, r3); // swpa w15, w21, [x3] - __ ldadda(Assembler::word, r24, r8, r25); // ldadda w24, w8, [x25] - __ ldbica(Assembler::word, r20, r16, r17); // ldclra w20, w16, [x17] - __ ldeora(Assembler::word, r2, r1, r0); // ldeora w2, w1, [x0] - __ ldorra(Assembler::word, r24, r4, r3); // ldseta w24, w4, [x3] - __ ldsmina(Assembler::word, r12, zr, r28); // ldsmina w12, wzr, [x28] - __ ldsmaxa(Assembler::word, r10, r26, r2); // ldsmaxa w10, w26, [x2] - __ ldumina(Assembler::word, r12, r18, sp); // ldumina w12, w18, [sp] - __ ldumaxa(Assembler::word, r1, r13, r29); // ldumaxa w1, w13, [x29] + __ swpa(Assembler::word, r4, r2, r11); // swpa w4, w2, [x11] + __ ldadda(Assembler::word, r20, r29, r4); // ldadda w20, w29, [x4] + __ ldbica(Assembler::word, r20, zr, r29); // ldclra w20, wzr, [x29] + __ ldeora(Assembler::word, r0, r15, r25); // ldeora w0, w15, [x25] + __ ldorra(Assembler::word, r23, r5, r20); // ldseta w23, w5, [x20] + __ ldsmina(Assembler::word, r29, r26, r19); // ldsmina w29, w26, [x19] + __ ldsmaxa(Assembler::word, r21, r20, r22); // ldsmaxa w21, w20, [x22] + __ ldumina(Assembler::word, r26, r21, r16); // ldumina w26, w21, [x16] + __ ldumaxa(Assembler::word, r8, r21, r10); // ldumaxa w8, w21, [x10] // LSEOp - __ swpal(Assembler::word, r0, r19, r12); // swpal w0, w19, [x12] - __ ldaddal(Assembler::word, r17, r22, r13); // ldaddal w17, w22, [x13] - __ ldbical(Assembler::word, r28, r30, sp); // ldclral w28, w30, [sp] - __ ldeoral(Assembler::word, r1, r26, r28); // ldeoral w1, w26, [x28] - __ ldorral(Assembler::word, r4, r30, r4); // ldsetal w4, w30, [x4] - __ ldsminal(Assembler::word, r6, r30, r26); // ldsminal w6, w30, [x26] - __ ldsmaxal(Assembler::word, r18, r9, r8); // ldsmaxal w18, w9, [x8] - __ lduminal(Assembler::word, r12, r0, r20); // lduminal w12, w0, [x20] - __ ldumaxal(Assembler::word, r1, r24, r2); // ldumaxal w1, w24, [x2] + __ swpal(Assembler::word, r27, r11, r11); // swpal w27, w11, [x11] + __ ldaddal(Assembler::word, r5, r8, r28); // ldaddal w5, w8, [x28] + __ ldbical(Assembler::word, r0, r5, r5); // ldclral w0, w5, [x5] + __ ldeoral(Assembler::word, r2, r10, r24); // ldeoral w2, w10, [x24] + __ ldorral(Assembler::word, r13, zr, sp); // ldsetal w13, wzr, [sp] + __ ldsminal(Assembler::word, r26, r25, r24); // ldsminal w26, w25, [x24] + __ ldsmaxal(Assembler::word, r8, r5, r6); // ldsmaxal w8, w5, [x6] + __ lduminal(Assembler::word, r5, r27, r27); // lduminal w5, w27, [x27] + __ ldumaxal(Assembler::word, r23, r20, r23); // ldumaxal w23, w20, [x23] // LSEOp - __ swpl(Assembler::word, r0, r9, r24); // swpl w0, w9, [x24] - __ ldaddl(Assembler::word, r26, r16, r30); // ldaddl w26, w16, [x30] - __ ldbicl(Assembler::word, r3, r10, r23); // ldclrl w3, w10, [x23] - __ ldeorl(Assembler::word, r10, r4, r18); // ldeorl w10, w4, [x18] - __ ldorrl(Assembler::word, r2, r11, r8); // ldsetl w2, w11, [x8] - __ ldsminl(Assembler::word, r10, r15, r17); // ldsminl w10, w15, [x17] - __ ldsmaxl(Assembler::word, r2, r10, r12); // ldsmaxl w2, w10, [x12] - __ lduminl(Assembler::word, r12, r15, r13); // lduminl w12, w15, [x13] - __ ldumaxl(Assembler::word, r2, r7, r20); // ldumaxl w2, w7, [x20] + __ swpl(Assembler::word, r25, r3, r28); // swpl w25, w3, [x28] + __ ldaddl(Assembler::word, r10, r8, r13); // ldaddl w10, w8, [x13] + __ ldbicl(Assembler::word, r21, r11, sp); // ldclrl w21, w11, [sp] + __ ldeorl(Assembler::word, zr, r3, r28); // ldeorl wzr, w3, [x28] + __ ldorrl(Assembler::word, r15, r0, r24); // ldsetl w15, w0, [x24] + __ ldsminl(Assembler::word, r4, r9, r29); // ldsminl w4, w9, [x29] + __ ldsmaxl(Assembler::word, r8, r6, r21); // ldsmaxl w8, w6, [x21] + __ lduminl(Assembler::word, r9, r22, r3); // lduminl w9, w22, [x3] + __ ldumaxl(Assembler::word, r26, r10, r28); // ldumaxl w26, w10, [x28] __ bind(forth); @@ -768,656 +762,651 @@ Disassembly of section .text: 0000000000000000 : - 0: 8b0d82fa add x26, x23, x13, lsl #32 - 4: cb49970c sub x12, x24, x9, lsr #37 - 8: ab889dfc adds x28, x15, x8, asr #39 - c: eb9ee787 subs x7, x28, x30, asr #57 - 10: 0b9b3ec9 add w9, w22, w27, asr #15 - 14: 4b9279a3 sub w3, w13, w18, asr #30 - 18: 2b88474e adds w14, w26, w8, asr #17 - 1c: 6b8c56c0 subs w0, w22, w12, asr #21 - 20: 8a1a51e0 and x0, x15, x26, lsl #20 - 24: aa11f4ba orr x26, x5, x17, lsl #61 - 28: ca0281b8 eor x24, x13, x2, lsl #32 - 2c: ea918c7c ands x28, x3, x17, asr #35 - 30: 0a5d4a19 and w25, w16, w29, lsr #18 - 34: 2a4b264d orr w13, w18, w11, lsr #9 - 38: 4a523ca5 eor w5, w5, w18, lsr #15 - 3c: 6a9b6ae2 ands w2, w23, w27, asr #26 - 40: 8a70b79b bic x27, x28, x16, lsr #45 - 44: aaba9728 orn x8, x25, x26, asr #37 - 48: ca6dfe3d eon x29, x17, x13, lsr #63 - 4c: ea627f1c bics x28, x24, x2, lsr #31 - 50: 0aa70f53 bic w19, w26, w7, asr #3 - 54: 2aaa0f06 orn w6, w24, w10, asr #3 - 58: 4a6176a4 eon w4, w21, w1, lsr #29 - 5c: 6a604eb0 bics w16, w21, w0, lsr #19 - 60: 1105ed91 add w17, w12, #0x17b - 64: 3100583e adds w30, w1, #0x16 - 68: 5101f8bd sub w29, w5, #0x7e - 6c: 710f0306 subs w6, w24, #0x3c0 - 70: 9101a1a0 add x0, x13, #0x68 - 74: b10a5cc8 adds x8, x6, #0x297 - 78: d10810aa sub x10, x5, #0x204 - 7c: f10fd061 subs x1, x3, #0x3f4 - 80: 120cb166 and w6, w11, #0xfff1fff1 - 84: 321764bc orr w28, w5, #0xfffffe07 - 88: 52174681 eor w1, w20, #0x7fffe00 - 8c: 720c0247 ands w7, w18, #0x100000 - 90: 9241018e and x14, x12, #0x8000000000000000 - 94: b25a2969 orr x9, x11, #0x1ffc000000000 - 98: d278b411 eor x17, x0, #0x3fffffffffff00 - 9c: f26aad01 ands x1, x8, #0xffffffffffc00003 - a0: 14000000 b a0 - a4: 17ffffd7 b 0 - a8: 140001f2 b 870 - ac: 94000000 bl ac - b0: 97ffffd4 bl 0 - b4: 940001ef bl 870 - b8: 3400000a cbz w10, b8 - bc: 34fffa2a cbz w10, 0 - c0: 34003d8a cbz w10, 870 - c4: 35000008 cbnz w8, c4 - c8: 35fff9c8 cbnz w8, 0 - cc: 35003d28 cbnz w8, 870 - d0: b400000b cbz x11, d0 - d4: b4fff96b cbz x11, 0 - d8: b4003ccb cbz x11, 870 - dc: b500001d cbnz x29, dc - e0: b5fff91d cbnz x29, 0 - e4: b5003c7d cbnz x29, 870 - e8: 10000013 adr x19, e8 - ec: 10fff8b3 adr x19, 0 - f0: 10003c13 adr x19, 870 - f4: 90000013 adrp x19, 0 - f8: 36300016 tbz w22, #6, f8 - fc: 3637f836 tbz w22, #6, 0 - 100: 36303b96 tbz w22, #6, 870 - 104: 3758000c tbnz w12, #11, 104 - 108: 375ff7cc tbnz w12, #11, 0 - 10c: 37583b2c tbnz w12, #11, 870 - 110: 128313a0 mov w0, #0xffffe762 // #-6302 - 114: 528a32c7 mov w7, #0x5196 // #20886 - 118: 7289173b movk w27, #0x48b9 - 11c: 92ab3acc mov x12, #0xffffffffa629ffff // #-1507196929 - 120: d2a0bf94 mov x20, #0x5fc0000 // #100401152 - 124: f2c285e8 movk x8, #0x142f, lsl #32 - 128: 9358722f sbfx x15, x17, #24, #5 - 12c: 330e652f bfxil w15, w9, #14, #12 - 130: 53067f3b lsr w27, w25, #6 - 134: 93577c53 sbfx x19, x2, #23, #9 - 138: b34a1aac bfi x12, x21, #54, #7 - 13c: d35a4016 ubfiz x22, x0, #38, #17 - 140: 13946c63 extr w3, w3, w20, #27 - 144: 93c3dbc8 extr x8, x30, x3, #54 - 148: 54000000 b.eq 148 // b.none - 14c: 54fff5a0 b.eq 0 // b.none - 150: 54003900 b.eq 870 // b.none - 154: 54000001 b.ne 154 // b.any - 158: 54fff541 b.ne 0 // b.any - 15c: 540038a1 b.ne 870 // b.any - 160: 54000002 b.cs 160 // b.hs, b.nlast - 164: 54fff4e2 b.cs 0 // b.hs, b.nlast - 168: 54003842 b.cs 870 // b.hs, b.nlast - 16c: 54000002 b.cs 16c // b.hs, b.nlast - 170: 54fff482 b.cs 0 // b.hs, b.nlast - 174: 540037e2 b.cs 870 // b.hs, b.nlast - 178: 54000003 b.cc 178 // b.lo, b.ul, b.last - 17c: 54fff423 b.cc 0 // b.lo, b.ul, b.last - 180: 54003783 b.cc 870 // b.lo, b.ul, b.last - 184: 54000003 b.cc 184 // b.lo, b.ul, b.last - 188: 54fff3c3 b.cc 0 // b.lo, b.ul, b.last - 18c: 54003723 b.cc 870 // b.lo, b.ul, b.last - 190: 54000004 b.mi 190 // b.first - 194: 54fff364 b.mi 0 // b.first - 198: 540036c4 b.mi 870 // b.first - 19c: 54000005 b.pl 19c // b.nfrst - 1a0: 54fff305 b.pl 0 // b.nfrst - 1a4: 54003665 b.pl 870 // b.nfrst - 1a8: 54000006 b.vs 1a8 - 1ac: 54fff2a6 b.vs 0 - 1b0: 54003606 b.vs 870 - 1b4: 54000007 b.vc 1b4 - 1b8: 54fff247 b.vc 0 - 1bc: 540035a7 b.vc 870 - 1c0: 54000008 b.hi 1c0 // b.pmore - 1c4: 54fff1e8 b.hi 0 // b.pmore - 1c8: 54003548 b.hi 870 // b.pmore - 1cc: 54000009 b.ls 1cc // b.plast - 1d0: 54fff189 b.ls 0 // b.plast - 1d4: 540034e9 b.ls 870 // b.plast - 1d8: 5400000a b.ge 1d8 // b.tcont - 1dc: 54fff12a b.ge 0 // b.tcont - 1e0: 5400348a b.ge 870 // b.tcont - 1e4: 5400000b b.lt 1e4 // b.tstop - 1e8: 54fff0cb b.lt 0 // b.tstop - 1ec: 5400342b b.lt 870 // b.tstop - 1f0: 5400000c b.gt 1f0 - 1f4: 54fff06c b.gt 0 - 1f8: 540033cc b.gt 870 - 1fc: 5400000d b.le 1fc - 200: 54fff00d b.le 0 - 204: 5400336d b.le 870 - 208: 5400000e b.al 208 - 20c: 54ffefae b.al 0 - 210: 5400330e b.al 870 - 214: 5400000f b.nv 214 - 218: 54ffef4f b.nv 0 - 21c: 540032af b.nv 870 - 220: d40658e1 svc #0x32c7 - 224: d4014d22 hvc #0xa69 - 228: d4046543 smc #0x232a - 22c: d4273f60 brk #0x39fb - 230: d44cad80 hlt #0x656c - 234: d503201f nop - 238: d69f03e0 eret - 23c: d6bf03e0 drps - 240: d5033fdf isb - 244: d5033e9f dsb st - 248: d50332bf dmb oshst - 24c: d61f0200 br x16 - 250: d63f0280 blr x20 - 254: c80a7d1b stxr w10, x27, [x8] - 258: c800fea1 stlxr w0, x1, [x21] - 25c: c85f7fb1 ldxr x17, [x29] - 260: c85fff9d ldaxr x29, [x28] - 264: c89ffee1 stlr x1, [x23] - 268: c8dffe95 ldar x21, [x20] - 26c: 88167e7b stxr w22, w27, [x19] - 270: 880bfcd0 stlxr w11, w16, [x6] - 274: 885f7c12 ldxr w18, [x0] - 278: 885ffd44 ldaxr w4, [x10] - 27c: 889ffed8 stlr w24, [x22] - 280: 88dffe6a ldar w10, [x19] - 284: 48017fc5 stxrh w1, w5, [x30] - 288: 4808fe2c stlxrh w8, w12, [x17] - 28c: 485f7dc9 ldxrh w9, [x14] - 290: 485ffc27 ldaxrh w7, [x1] - 294: 489ffe05 stlrh w5, [x16] - 298: 48dffd82 ldarh w2, [x12] - 29c: 080a7c6c stxrb w10, w12, [x3] - 2a0: 081cff4e stlxrb w28, w14, [x26] - 2a4: 085f7d5e ldxrb w30, [x10] - 2a8: 085ffeae ldaxrb w14, [x21] - 2ac: 089ffd2d stlrb w13, [x9] - 2b0: 08dfff76 ldarb w22, [x27] - 2b4: c87f4d7c ldxp x28, x19, [x11] - 2b8: c87fcc5e ldaxp x30, x19, [x2] - 2bc: c8220417 stxp w2, x23, x1, [x0] - 2c0: c82cb5f0 stlxp w12, x16, x13, [x15] - 2c4: 887f55b2 ldxp w18, w21, [x13] - 2c8: 887ff90b ldaxp w11, w30, [x8] - 2cc: 88382c2d stxp w24, w13, w11, [x1] - 2d0: 883aedb5 stlxp w26, w21, w27, [x13] - 2d4: f819928b stur x11, [x20, #-103] - 2d8: b803e21c stur w28, [x16, #62] - 2dc: 381f713b sturb w27, [x9, #-9] - 2e0: 781ce322 sturh w2, [x25, #-50] - 2e4: f850f044 ldur x4, [x2, #-241] - 2e8: b85e129e ldur w30, [x20, #-31] - 2ec: 385e92f2 ldurb w18, [x23, #-23] - 2f0: 785ff35d ldurh w29, [x26, #-1] - 2f4: 39801921 ldrsb x1, [x9, #6] - 2f8: 7881318b ldursh x11, [x12, #19] - 2fc: 78dce02b ldursh w11, [x1, #-50] - 300: b8829313 ldursw x19, [x24, #41] - 304: fc45f318 ldur d24, [x24, #95] - 308: bc5d50af ldur s15, [x5, #-43] - 30c: fc001375 stur d21, [x27, #1] - 310: bc1951b7 stur s23, [x13, #-107] - 314: f8008c0b str x11, [x0, #8]! - 318: b801dc03 str w3, [x0, #29]! - 31c: 38009dcb strb w11, [x14, #9]! - 320: 781fdf1d strh w29, [x24, #-3]! - 324: f8570e2d ldr x13, [x17, #-144]! - 328: b85faecc ldr w12, [x22, #-6]! - 32c: 385f6d8d ldrb w13, [x12, #-10]! - 330: 785ebea0 ldrh w0, [x21, #-21]! - 334: 38804cf7 ldrsb x23, [x7, #4]! - 338: 789cbce3 ldrsh x3, [x7, #-53]! - 33c: 78df9cbc ldrsh w28, [x5, #-7]! - 340: b89eed38 ldrsw x24, [x9, #-18]! - 344: fc40cd6e ldr d14, [x11, #12]! - 348: bc5bdd93 ldr s19, [x12, #-67]! - 34c: fc103c14 str d20, [x0, #-253]! - 350: bc040c08 str s8, [x0, #64]! - 354: f81a2784 str x4, [x28], #-94 - 358: b81ca4ec str w12, [x7], #-54 - 35c: 381e855b strb w27, [x10], #-24 - 360: 7801b506 strh w6, [x8], #27 - 364: f853654e ldr x14, [x10], #-202 - 368: b85d74b0 ldr w16, [x5], #-41 - 36c: 384095c2 ldrb w2, [x14], #9 - 370: 785ec5bc ldrh w28, [x13], #-20 - 374: 389e15a9 ldrsb x9, [x13], #-31 - 378: 789dc703 ldrsh x3, [x24], #-36 - 37c: 78c06474 ldrsh w20, [x3], #6 - 380: b89ff667 ldrsw x7, [x19], #-1 - 384: fc57e51e ldr d30, [x8], #-130 - 388: bc4155f9 ldr s25, [x15], #21 - 38c: fc05a6ee str d14, [x23], #90 - 390: bc1df408 str s8, [x0], #-33 - 394: f835da4a str x10, [x18, w21, sxtw #3] - 398: b836d9a4 str w4, [x13, w22, sxtw #2] - 39c: 3833580d strb w13, [x0, w19, uxtw #0] - 3a0: 7826cb6c strh w12, [x27, w6, sxtw] - 3a4: f8706900 ldr x0, [x8, x16] - 3a8: b87ae880 ldr w0, [x4, x26, sxtx] - 3ac: 3865db2e ldrb w14, [x25, w5, sxtw #0] - 3b0: 78724889 ldrh w9, [x4, w18, uxtw] - 3b4: 38a7789b ldrsb x27, [x4, x7, lsl #0] - 3b8: 78beca2f ldrsh x15, [x17, w30, sxtw] - 3bc: 78f6c810 ldrsh w16, [x0, w22, sxtw] - 3c0: b8bef956 ldrsw x22, [x10, x30, sxtx #2] - 3c4: fc6afabd ldr d29, [x21, x10, sxtx #3] - 3c8: bc734963 ldr s3, [x11, w19, uxtw] - 3cc: fc3d5b8d str d13, [x28, w29, uxtw #3] - 3d0: bc25fbb7 str s23, [x29, x5, sxtx #2] - 3d4: f9189d05 str x5, [x8, #12600] - 3d8: b91ecb1d str w29, [x24, #7880] - 3dc: 39187a33 strb w19, [x17, #1566] - 3e0: 791f226d strh w13, [x19, #3984] - 3e4: f95aa2f3 ldr x19, [x23, #13632] - 3e8: b9587bb7 ldr w23, [x29, #6264] - 3ec: 395f7176 ldrb w22, [x11, #2012] - 3f0: 795d9143 ldrh w3, [x10, #3784] - 3f4: 399e7e08 ldrsb x8, [x16, #1951] - 3f8: 799a2697 ldrsh x23, [x20, #3346] - 3fc: 79df3422 ldrsh w2, [x1, #3994] - 400: b99c2624 ldrsw x4, [x17, #7204] - 404: fd5c2374 ldr d20, [x27, #14400] - 408: bd5fa1d9 ldr s25, [x14, #8096] - 40c: fd1d595a str d26, [x10, #15024] - 410: bd1b1869 str s9, [x3, #6936] - 414: 580022fb ldr x27, 870 - 418: 1800000b ldr w11, 418 - 41c: f8945060 prfum pldl1keep, [x3, #-187] - 420: d8000000 prfm pldl1keep, 420 - 424: f8ae6ba0 prfm pldl1keep, [x29, x14] - 428: f99a0080 prfm pldl1keep, [x4, #13312] - 42c: 1a070035 adc w21, w1, w7 - 430: 3a0700a8 adcs w8, w5, w7 - 434: 5a0e0367 sbc w7, w27, w14 - 438: 7a11009b sbcs w27, w4, w17 - 43c: 9a000380 adc x0, x28, x0 - 440: ba1e030c adcs x12, x24, x30 - 444: da0f0320 sbc x0, x25, x15 - 448: fa030301 sbcs x1, x24, x3 - 44c: 0b340b12 add w18, w24, w20, uxtb #2 - 450: 2b2a278d adds w13, w28, w10, uxth #1 - 454: cb22aa0f sub x15, x16, w2, sxth #2 - 458: 6b2d29bd subs w29, w13, w13, uxth #2 - 45c: 8b2cce8c add x12, x20, w12, sxtw #3 - 460: ab2b877e adds x30, x27, w11, sxtb #1 - 464: cb21c8ee sub x14, x7, w1, sxtw #2 - 468: eb3ba47d subs x29, x3, w27, sxth #1 - 46c: 3a4d400e ccmn w0, w13, #0xe, mi // mi = first - 470: 7a5232c6 ccmp w22, w18, #0x6, cc // cc = lo, ul, last - 474: ba5e624e ccmn x18, x30, #0xe, vs - 478: fa53814c ccmp x10, x19, #0xc, hi // hi = pmore - 47c: 3a52d8c2 ccmn w6, #0x12, #0x2, le - 480: 7a4d8924 ccmp w9, #0xd, #0x4, hi // hi = pmore - 484: ba4b3aab ccmn x21, #0xb, #0xb, cc // cc = lo, ul, last - 488: fa4d7882 ccmp x4, #0xd, #0x2, vc - 48c: 1a96804c csel w12, w2, w22, hi // hi = pmore - 490: 1a912618 csinc w24, w16, w17, cs // cs = hs, nlast - 494: 5a90b0e6 csinv w6, w7, w16, lt // lt = tstop - 498: 5a96976b csneg w11, w27, w22, ls // ls = plast - 49c: 9a9db06a csel x10, x3, x29, lt // lt = tstop - 4a0: 9a9b374c csinc x12, x26, x27, cc // cc = lo, ul, last - 4a4: da95c14f csinv x15, x10, x21, gt - 4a8: da89c6fe csneg x30, x23, x9, gt - 4ac: 5ac0015e rbit w30, w10 - 4b0: 5ac005fd rev16 w29, w15 - 4b4: 5ac00bdd rev w29, w30 - 4b8: 5ac012b9 clz w25, w21 - 4bc: 5ac01404 cls w4, w0 - 4c0: dac002b2 rbit x18, x21 - 4c4: dac0061d rev16 x29, x16 - 4c8: dac00a95 rev32 x21, x20 - 4cc: dac00e66 rev x6, x19 - 4d0: dac0107e clz x30, x3 - 4d4: dac01675 cls x21, x19 - 4d8: 1ac00b0b udiv w11, w24, w0 - 4dc: 1ace0f3b sdiv w27, w25, w14 - 4e0: 1ad221c3 lsl w3, w14, w18 - 4e4: 1ad825e7 lsr w7, w15, w24 - 4e8: 1ad92a3c asr w28, w17, w25 - 4ec: 1adc2f42 ror w2, w26, w28 - 4f0: 9ada0b25 udiv x5, x25, x26 - 4f4: 9ad20e1b sdiv x27, x16, x18 - 4f8: 9acc22a6 lsl x6, x21, x12 - 4fc: 9acc2480 lsr x0, x4, x12 - 500: 9adc2a3b asr x27, x17, x28 - 504: 9ad22c5c ror x28, x2, x18 - 508: 9bce7dea umulh x10, x15, x14 - 50c: 9b597c6e smulh x14, x3, x25 - 510: 1b0e166f madd w15, w19, w14, w5 - 514: 1b1ae490 msub w16, w4, w26, w25 - 518: 9b023044 madd x4, x2, x2, x12 - 51c: 9b089e3d msub x29, x17, x8, x7 - 520: 9b391083 smaddl x3, w4, w25, x4 - 524: 9b24c73a smsubl x26, w25, w4, x17 - 528: 9bb15f40 umaddl x0, w26, w17, x23 - 52c: 9bbcc6af umsubl x15, w21, w28, x17 - 530: 1e23095b fmul s27, s10, s3 - 534: 1e3918e0 fdiv s0, s7, s25 - 538: 1e2f28c9 fadd s9, s6, s15 - 53c: 1e2a39fd fsub s29, s15, s10 - 540: 1e270a22 fmul s2, s17, s7 - 544: 1e77096b fmul d11, d11, d23 - 548: 1e771ba7 fdiv d7, d29, d23 - 54c: 1e6b2b6e fadd d14, d27, d11 - 550: 1e78388b fsub d11, d4, d24 - 554: 1e6e09ec fmul d12, d15, d14 - 558: 1f1c3574 fmadd s20, s11, s28, s13 - 55c: 1f17f98b fmsub s11, s12, s23, s30 - 560: 1f2935da fnmadd s26, s14, s9, s13 - 564: 1f2574ea fnmadd s10, s7, s5, s29 - 568: 1f4b306f fmadd d15, d3, d11, d12 - 56c: 1f5ec7cf fmsub d15, d30, d30, d17 - 570: 1f6f3e93 fnmadd d19, d20, d15, d15 - 574: 1f6226a9 fnmadd d9, d21, d2, d9 - 578: 1e2040fb fmov s27, s7 - 57c: 1e20c3dd fabs s29, s30 - 580: 1e214031 fneg s17, s1 - 584: 1e21c0c2 fsqrt s2, s6 - 588: 1e22c06a fcvt d10, s3 - 58c: 1e604178 fmov d24, d11 - 590: 1e60c027 fabs d7, d1 - 594: 1e61400b fneg d11, d0 - 598: 1e61c243 fsqrt d3, d18 - 59c: 1e6240dc fcvt s28, d6 - 5a0: 1e3800d6 fcvtzs w22, s6 - 5a4: 9e380360 fcvtzs x0, s27 - 5a8: 1e78005a fcvtzs w26, d2 - 5ac: 9e7800e5 fcvtzs x5, d7 - 5b0: 1e22017c scvtf s28, w11 - 5b4: 9e2201b9 scvtf s25, x13 - 5b8: 1e6202eb scvtf d11, w23 - 5bc: 9e620113 scvtf d19, x8 - 5c0: 1e2602b2 fmov w18, s21 - 5c4: 9e660299 fmov x25, d20 - 5c8: 1e270253 fmov s19, w18 - 5cc: 9e6703a2 fmov d2, x29 - 5d0: 1e2822c0 fcmp s22, s8 - 5d4: 1e7322a0 fcmp d21, d19 - 5d8: 1e202288 fcmp s20, #0.0 - 5dc: 1e602168 fcmp d11, #0.0 - 5e0: 293c19f4 stp w20, w6, [x15, #-32] - 5e4: 2966387b ldp w27, w14, [x3, #-208] - 5e8: 69762971 ldpsw x17, x10, [x11, #-80] - 5ec: a9041dc7 stp x7, x7, [x14, #64] - 5f0: a9475c0c ldp x12, x23, [x0, #112] - 5f4: 29b61ccd stp w13, w7, [x6, #-80]! - 5f8: 29ee405e ldp w30, w16, [x2, #-144]! - 5fc: 69ee0744 ldpsw x4, x1, [x26, #-144]! - 600: a9843977 stp x23, x14, [x11, #64]! - 604: a9f46ebd ldp x29, x27, [x21, #-192]! - 608: 28ba16b6 stp w22, w5, [x21], #-48 - 60c: 28fc44db ldp w27, w17, [x6], #-32 - 610: 68f61831 ldpsw x17, x6, [x1], #-80 - 614: a8b352ad stp x13, x20, [x21], #-208 - 618: a8c56d5e ldp x30, x27, [x10], #80 - 61c: 28024565 stnp w5, w17, [x11, #16] - 620: 2874134e ldnp w14, w4, [x26, #-96] - 624: a8027597 stnp x23, x29, [x12, #32] - 628: a87b1aa0 ldnp x0, x6, [x21, #-80] - 62c: 0c40734f ld1 {v15.8b}, [x26] - 630: 4cdfa177 ld1 {v23.16b, v24.16b}, [x11], #32 - 634: 0cc76ee8 ld1 {v8.1d-v10.1d}, [x23], x7 - 638: 4cdf2733 ld1 {v19.8h-v22.8h}, [x25], #64 - 63c: 0d40c23d ld1r {v29.8b}, [x17] - 640: 4ddfcaf8 ld1r {v24.4s}, [x23], #4 - 644: 0dd9ccaa ld1r {v10.1d}, [x5], x25 - 648: 4c408d52 ld2 {v18.2d, v19.2d}, [x10] - 64c: 0cdf85ec ld2 {v12.4h, v13.4h}, [x15], #16 - 650: 4d60c259 ld2r {v25.16b, v26.16b}, [x18] - 654: 0dffcbc1 ld2r {v1.2s, v2.2s}, [x30], #8 - 658: 4de9ce50 ld2r {v16.2d, v17.2d}, [x18], x9 - 65c: 4cc24999 ld3 {v25.4s-v27.4s}, [x12], x2 - 660: 0c404a7a ld3 {v26.2s-v28.2s}, [x19] - 664: 4d40e6af ld3r {v15.8h-v17.8h}, [x21] - 668: 4ddfe9b9 ld3r {v25.4s-v27.4s}, [x13], #12 - 66c: 0dddef8e ld3r {v14.1d-v16.1d}, [x28], x29 - 670: 4cdf07b1 ld4 {v17.8h-v20.8h}, [x29], #64 - 674: 0cc000fb ld4 {v27.8b-v30.8b}, [x7], x0 - 678: 0d60e258 ld4r {v24.8b-v27.8b}, [x18] - 67c: 0dffe740 ld4r {v0.4h-v3.4h}, [x26], #8 - 680: 0de2eb2c ld4r {v12.2s-v15.2s}, [x25], x2 - 684: ce648376 sha512h q22, q27, v4.2d - 688: ce6184c7 sha512h2 q7, q6, v1.2d - 68c: cec081fa sha512su0 v26.2d, v15.2d - 690: ce6d89a2 sha512su1 v2.2d, v13.2d, v13.2d - 694: ba5fd3e3 ccmn xzr, xzr, #0x3, le - 698: 3a5f03e5 ccmn wzr, wzr, #0x5, eq // eq = none - 69c: fa411be4 ccmp xzr, #0x1, #0x4, ne // ne = any - 6a0: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt - 6a4: 93df03ff ror xzr, xzr, #0 - 6a8: c820ffff stlxp w0, xzr, xzr, [sp] - 6ac: 8822fc7f stlxp w2, wzr, wzr, [x3] - 6b0: c8247cbf stxp w4, xzr, xzr, [x5] - 6b4: 88267fff stxp w6, wzr, wzr, [sp] - 6b8: 4e010fe0 dup v0.16b, wzr - 6bc: 4e081fe1 mov v1.d[0], xzr - 6c0: 4e0c1fe1 mov v1.s[1], wzr - 6c4: 4e0a1fe1 mov v1.h[2], wzr - 6c8: 4e071fe1 mov v1.b[3], wzr - 6cc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 - 6d0: 1e601000 fmov d0, #2.000000000000000000e+00 - 6d4: 1e603000 fmov d0, #2.125000000000000000e+00 - 6d8: 1e621000 fmov d0, #4.000000000000000000e+00 - 6dc: 1e623000 fmov d0, #4.250000000000000000e+00 - 6e0: 1e641000 fmov d0, #8.000000000000000000e+00 - 6e4: 1e643000 fmov d0, #8.500000000000000000e+00 - 6e8: 1e661000 fmov d0, #1.600000000000000000e+01 - 6ec: 1e663000 fmov d0, #1.700000000000000000e+01 - 6f0: 1e681000 fmov d0, #1.250000000000000000e-01 - 6f4: 1e683000 fmov d0, #1.328125000000000000e-01 - 6f8: 1e6a1000 fmov d0, #2.500000000000000000e-01 - 6fc: 1e6a3000 fmov d0, #2.656250000000000000e-01 - 700: 1e6c1000 fmov d0, #5.000000000000000000e-01 - 704: 1e6c3000 fmov d0, #5.312500000000000000e-01 - 708: 1e6e1000 fmov d0, #1.000000000000000000e+00 - 70c: 1e6e3000 fmov d0, #1.062500000000000000e+00 - 710: 1e701000 fmov d0, #-2.000000000000000000e+00 - 714: 1e703000 fmov d0, #-2.125000000000000000e+00 - 718: 1e721000 fmov d0, #-4.000000000000000000e+00 - 71c: 1e723000 fmov d0, #-4.250000000000000000e+00 - 720: 1e741000 fmov d0, #-8.000000000000000000e+00 - 724: 1e743000 fmov d0, #-8.500000000000000000e+00 - 728: 1e761000 fmov d0, #-1.600000000000000000e+01 - 72c: 1e763000 fmov d0, #-1.700000000000000000e+01 - 730: 1e781000 fmov d0, #-1.250000000000000000e-01 - 734: 1e783000 fmov d0, #-1.328125000000000000e-01 - 738: 1e7a1000 fmov d0, #-2.500000000000000000e-01 - 73c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 - 740: 1e7c1000 fmov d0, #-5.000000000000000000e-01 - 744: 1e7c3000 fmov d0, #-5.312500000000000000e-01 - 748: 1e7e1000 fmov d0, #-1.000000000000000000e+00 - 74c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 - 750: f8388098 swp x24, x24, [x4] - 754: f8340010 ldadd x20, x16, [x0] - 758: f8241175 ldclr x4, x21, [x11] - 75c: f83e22d0 ldeor x30, x16, [x22] - 760: f82432ef ldset x4, x15, [x23] - 764: f83a5186 ldsmin x26, x6, [x12] - 768: f82f41ee ldsmax x15, x14, [x15] - 76c: f82973b9 ldumin x9, x25, [x29] - 770: f82b6194 ldumax x11, x20, [x12] - 774: f8b28216 swpa x18, x22, [x16] - 778: f8b50358 ldadda x21, x24, [x26] - 77c: f8a61206 ldclra x6, x6, [x16] - 780: f8b02219 ldeora x16, x25, [x16] - 784: f8bc3218 ldseta x28, x24, [x16] - 788: f8ba514f ldsmina x26, x15, [x10] - 78c: f8ad428e ldsmaxa x13, x14, [x20] - 790: f8a173d7 ldumina x1, x23, [x30] - 794: f8ae60c2 ldumaxa x14, x2, [x6] - 798: f8e38328 swpal x3, x8, [x25] - 79c: f8e003db ldaddal x0, x27, [x30] - 7a0: f8e513c5 ldclral x5, x5, [x30] - 7a4: f8eb2019 ldeoral x11, x25, [x0] - 7a8: f8ff3260 ldsetal xzr, x0, [x19] - 7ac: f8fd513a ldsminal x29, x26, [x9] - 7b0: f8fa41ec ldsmaxal x26, x12, [x15] - 7b4: f8eb724b lduminal x11, x11, [x18] - 7b8: f8f96316 ldumaxal x25, x22, [x24] - 7bc: f8608171 swpl x0, x17, [x11] - 7c0: f86600dd ldaddl x6, x29, [x6] - 7c4: f86512a5 ldclrl x5, x5, [x21] - 7c8: f8732250 ldeorl x19, x16, [x18] - 7cc: f87e339b ldsetl x30, x27, [x28] - 7d0: f861503c ldsminl x1, x28, [x1] - 7d4: f874421d ldsmaxl x20, x29, [x16] - 7d8: f86d73aa lduminl x13, x10, [x29] - 7dc: f87d62d3 ldumaxl x29, x19, [x22] - 7e0: b82a83e4 swp w10, w4, [sp] - 7e4: b83503e8 ldadd w21, w8, [sp] - 7e8: b833138a ldclr w19, w10, [x28] - 7ec: b82220b9 ldeor w2, w25, [x5] - 7f0: b82332c8 ldset w3, w8, [x22] - 7f4: b83350ad ldsmin w19, w13, [x5] - 7f8: b83d42b8 ldsmax w29, w24, [x21] - 7fc: b83a7078 ldumin w26, w24, [x3] - 800: b83862fa ldumax w24, w26, [x23] - 804: b8af8075 swpa w15, w21, [x3] - 808: b8b80328 ldadda w24, w8, [x25] - 80c: b8b41230 ldclra w20, w16, [x17] - 810: b8a22001 ldeora w2, w1, [x0] - 814: b8b83064 ldseta w24, w4, [x3] - 818: b8ac539f ldsmina w12, wzr, [x28] - 81c: b8aa405a ldsmaxa w10, w26, [x2] - 820: b8ac73f2 ldumina w12, w18, [sp] - 824: b8a163ad ldumaxa w1, w13, [x29] - 828: b8e08193 swpal w0, w19, [x12] - 82c: b8f101b6 ldaddal w17, w22, [x13] - 830: b8fc13fe ldclral w28, w30, [sp] - 834: b8e1239a ldeoral w1, w26, [x28] - 838: b8e4309e ldsetal w4, w30, [x4] - 83c: b8e6535e ldsminal w6, w30, [x26] - 840: b8f24109 ldsmaxal w18, w9, [x8] - 844: b8ec7280 lduminal w12, w0, [x20] - 848: b8e16058 ldumaxal w1, w24, [x2] - 84c: b8608309 swpl w0, w9, [x24] - 850: b87a03d0 ldaddl w26, w16, [x30] - 854: b86312ea ldclrl w3, w10, [x23] - 858: b86a2244 ldeorl w10, w4, [x18] - 85c: b862310b ldsetl w2, w11, [x8] - 860: b86a522f ldsminl w10, w15, [x17] - 864: b862418a ldsmaxl w2, w10, [x12] - 868: b86c71af lduminl w12, w15, [x13] - 86c: b8626287 ldumaxl w2, w7, [x20] + 0: 8b1ad014 add x20, x0, x26, lsl #52 + 4: cb83db85 sub x5, x28, x3, asr #54 + 8: ab839ecb adds x11, x22, x3, asr #39 + c: eb4c646b subs x11, x3, x12, lsr #25 + 10: 0b0d399b add w27, w12, w13, lsl #14 + 14: 4b9b1eaa sub w10, w21, w27, asr #7 + 18: 2b1011c3 adds w3, w14, w16, lsl #4 + 1c: 6b1d1661 subs w1, w19, w29, lsl #5 + 20: 8a5b1a30 and x16, x17, x27, lsr #6 + 24: aa1c8f96 orr x22, x28, x28, lsl #35 + 28: ca5ccd4b eor x11, x10, x28, lsr #51 + 2c: ea8ec10d ands x13, x8, x14, asr #48 + 30: 0a410c61 and w1, w3, w1, lsr #3 + 34: 2a855909 orr w9, w8, w5, asr #22 + 38: 4a9b4f82 eor w2, w28, w27, asr #19 + 3c: 6a073938 ands w24, w9, w7, lsl #14 + 40: 8ab9826b bic x11, x19, x25, asr #32 + 44: aa3d7318 orn x24, x24, x29, lsl #28 + 48: cab16e0b eon x11, x16, x17, asr #27 + 4c: ea6ae9a5 bics x5, x13, x10, lsr #58 + 50: 0a357545 bic w5, w10, w21, lsl #29 + 54: 2a354d64 orn w4, w11, w21, lsl #19 + 58: 4a7c3f95 eon w21, w28, w28, lsr #15 + 5c: 6a2e7146 bics w6, w10, w14, lsl #28 + 60: 110ec6ca add w10, w22, #0x3b1 + 64: 310e9d6f adds w15, w11, #0x3a7 + 68: 510afcc5 sub w5, w6, #0x2bf + 6c: 7108e013 subs w19, w0, #0x238 + 70: 91098114 add x20, x8, #0x260 + 74: b10434d0 adds x16, x6, #0x10d + 78: d10db417 sub x23, x0, #0x36d + 7c: f10c873a subs x26, x25, #0x321 + 80: 120d6a0c and w12, w16, #0xfff83fff + 84: 32066b01 orr w1, w24, #0xfc1fffff + 88: 52112073 eor w19, w3, #0xff8000 + 8c: 720a553d ands w29, w9, #0xffc00fff + 90: 9263d0ba and x26, x5, #0xffffffffe003ffff + 94: b20da1d8 orr x24, x14, #0xff80ff80ff80ff8 + 98: d26ec404 eor x4, x0, #0xfffffffffffc000f + 9c: f26e28dc ands x28, x6, #0x1ffc0000 + a0: 14000000 b a0 + a4: 17ffffd7 b 0 + a8: 140001ee b 860 + ac: 94000000 bl ac + b0: 97ffffd4 bl 0 + b4: 940001eb bl 860 + b8: 34000015 cbz w21, b8 + bc: 34fffa35 cbz w21, 0 + c0: 34003d15 cbz w21, 860 + c4: 3500000c cbnz w12, c4 + c8: 35fff9cc cbnz w12, 0 + cc: 35003cac cbnz w12, 860 + d0: b400000e cbz x14, d0 + d4: b4fff96e cbz x14, 0 + d8: b4003c4e cbz x14, 860 + dc: b500001b cbnz x27, dc + e0: b5fff91b cbnz x27, 0 + e4: b5003bfb cbnz x27, 860 + e8: 1000000e adr x14, e8 + ec: 10fff8ae adr x14, 0 + f0: 10003b8e adr x14, 860 + f4: 90000016 adrp x22, 0 + f8: 36280000 tbz w0, #5, f8 + fc: 362ff820 tbz w0, #5, 0 + 100: 36283b00 tbz w0, #5, 860 + 104: 37580003 tbnz w3, #11, 104 + 108: 375ff7c3 tbnz w3, #11, 0 + 10c: 37583aa3 tbnz w3, #11, 860 + 110: 12835753 mov w19, #0xffffe545 // #-6843 + 114: 52a2da7c mov w28, #0x16d30000 // #382926848 + 118: 72a9ef0d movk w13, #0x4f78, lsl #16 + 11c: 92c097e1 mov x1, #0xfffffb40ffffffff // #-5218385264641 + 120: d28e0a7a mov x26, #0x7053 // #28755 + 124: f2e2d05b movk x27, #0x1682, lsl #48 + 128: 93496301 sbfx x1, x24, #9, #16 + 12c: 33054019 bfxil w25, w0, #5, #12 + 130: 530f1f70 ubfiz w16, w27, #17, #8 + 134: 934f71d0 sbfx x16, x14, #15, #14 + 138: b3403558 bfxil x24, x10, #0, #14 + 13c: d34259c1 ubfx x1, x14, #2, #21 + 140: 1381540a extr w10, w0, w1, #21 + 144: 93d7f75a extr x26, x26, x23, #61 + 148: 54000000 b.eq 148 + 14c: 54fff5a0 b.eq 0 + 150: 54003880 b.eq 860 + 154: 54000001 b.ne 154 + 158: 54fff541 b.ne 0 + 15c: 54003821 b.ne 860 + 160: 54000002 b.cs 160 + 164: 54fff4e2 b.cs 0 + 168: 540037c2 b.cs 860 + 16c: 54000002 b.cs 16c + 170: 54fff482 b.cs 0 + 174: 54003762 b.cs 860 + 178: 54000003 b.cc 178 + 17c: 54fff423 b.cc 0 + 180: 54003703 b.cc 860 + 184: 54000003 b.cc 184 + 188: 54fff3c3 b.cc 0 + 18c: 540036a3 b.cc 860 + 190: 54000004 b.mi 190 + 194: 54fff364 b.mi 0 + 198: 54003644 b.mi 860 + 19c: 54000005 b.pl 19c + 1a0: 54fff305 b.pl 0 + 1a4: 540035e5 b.pl 860 + 1a8: 54000006 b.vs 1a8 + 1ac: 54fff2a6 b.vs 0 + 1b0: 54003586 b.vs 860 + 1b4: 54000007 b.vc 1b4 + 1b8: 54fff247 b.vc 0 + 1bc: 54003527 b.vc 860 + 1c0: 54000008 b.hi 1c0 + 1c4: 54fff1e8 b.hi 0 + 1c8: 540034c8 b.hi 860 + 1cc: 54000009 b.ls 1cc + 1d0: 54fff189 b.ls 0 + 1d4: 54003469 b.ls 860 + 1d8: 5400000a b.ge 1d8 + 1dc: 54fff12a b.ge 0 + 1e0: 5400340a b.ge 860 + 1e4: 5400000b b.lt 1e4 + 1e8: 54fff0cb b.lt 0 + 1ec: 540033ab b.lt 860 + 1f0: 5400000c b.gt 1f0 + 1f4: 54fff06c b.gt 0 + 1f8: 5400334c b.gt 860 + 1fc: 5400000d b.le 1fc + 200: 54fff00d b.le 0 + 204: 540032ed b.le 860 + 208: 5400000e b.al 208 + 20c: 54ffefae b.al 0 + 210: 5400328e b.al 860 + 214: 5400000f b.nv 214 + 218: 54ffef4f b.nv 0 + 21c: 5400322f b.nv 860 + 220: d4079461 svc #0x3ca3 + 224: d4018ee2 hvc #0xc77 + 228: d408d7c3 smc #0x46be + 22c: d4216040 brk #0xb02 + 230: d44a2f80 hlt #0x517c + 234: d503201f nop + 238: d69f03e0 eret + 23c: d6bf03e0 drps + 240: d5033fdf isb + 244: d503329f dsb oshst + 248: d50339bf dmb ishld + 24c: d61f0140 br x10 + 250: d63f02c0 blr x22 + 254: c8037cb5 stxr w3, x21, [x5] + 258: c81cffa9 stlxr w28, x9, [x29] + 25c: c85f7cfc ldxr x28, [x7] + 260: c85ffeea ldaxr x10, [x23] + 264: c89fff47 stlr x7, [x26] + 268: c8dffef0 ldar x16, [x23] + 26c: 880b7d87 stxr w11, w7, [x12] + 270: 8810ff4d stlxr w16, w13, [x26] + 274: 885f7eb9 ldxr w25, [x21] + 278: 885ffc8e ldaxr w14, [x4] + 27c: 889ffd3a stlr w26, [x9] + 280: 88dffee0 ldar w0, [x23] + 284: 48087d40 stxrh w8, w0, [x10] + 288: 480bfc81 stlxrh w11, w1, [x4] + 28c: 485f7f4e ldxrh w14, [x26] + 290: 485ffcf3 ldaxrh w19, [x7] + 294: 489ffed1 stlrh w17, [x22] + 298: 48dffcd4 ldarh w20, [x6] + 29c: 08197cc8 stxrb w25, w8, [x6] + 2a0: 0805ff2a stlxrb w5, w10, [x25] + 2a4: 085f7ec0 ldxrb w0, [x22] + 2a8: 085ffc68 ldaxrb w8, [x3] + 2ac: 089ffc45 stlrb w5, [x2] + 2b0: 08dfff86 ldarb w6, [x28] + 2b4: c87f21d1 ldxp x17, x8, [x14] + 2b8: c87f8c4e ldaxp x14, x3, [x2] + 2bc: c8391271 stxp w25, x17, x4, [x19] + 2c0: c82abd10 stlxp w10, x16, x15, [x8] + 2c4: 887f2c61 ldxp w1, w11, [x3] + 2c8: 887fed80 ldaxp w0, w27, [x12] + 2cc: 882457b4 stxp w4, w20, w21, [x29] + 2d0: 882097a9 stlxp w0, w9, w5, [x29] + 2d4: f811d091 stur x17, [x4,#-227] + 2d8: b81df086 stur w6, [x4,#-33] + 2dc: 39002e0d strb w13, [x16,#11] + 2e0: 781c02d7 sturh w23, [x22,#-64] + 2e4: f840d062 ldur x2, [x3,#13] + 2e8: b8423285 ldur w5, [x20,#35] + 2ec: 385f1142 ldurb w2, [x10,#-15] + 2f0: 785f8017 ldurh w23, [x0,#-8] + 2f4: 389fd1cf ldursb x15, [x14,#-3] + 2f8: 789f4063 ldursh x3, [x3,#-12] + 2fc: 78df9319 ldursh w25, [x24,#-7] + 300: b89e3011 ldursw x17, [x0,#-29] + 304: fc5b1127 ldur d7, [x9,#-79] + 308: bc5bc16b ldur s11, [x11,#-68] + 30c: fc189050 stur d16, [x2,#-119] + 310: bc184399 stur s25, [x28,#-124] + 314: f8052e7c str x28, [x19,#82]! + 318: b8032da7 str w7, [x13,#50]! + 31c: 381e0e62 strb w2, [x19,#-32]! + 320: 781c6c38 strh w24, [x1,#-58]! + 324: f8571fb7 ldr x23, [x29,#-143]! + 328: b8400f6d ldr w13, [x27,#0]! + 32c: 385e6d4b ldrb w11, [x10,#-26]! + 330: 785cacc3 ldrh w3, [x6,#-54]! + 334: 38803d22 ldrsb x2, [x9,#3]! + 338: 7881ec9c ldrsh x28, [x4,#30]! + 33c: 78de9c11 ldrsh w17, [x0,#-23]! + 340: b898bf3d ldrsw x29, [x25,#-117]! + 344: fc572d55 ldr d21, [x10,#-142]! + 348: bc423e8b ldr s11, [x20,#35]! + 34c: fc12ade1 str d1, [x15,#-214]! + 350: bc1c9cb3 str s19, [x5,#-55]! + 354: f81ec63c str x28, [x17],#-20 + 358: b81f75a8 str w8, [x13],#-9 + 35c: 381e970e strb w14, [x24],#-23 + 360: 781c4482 strh w2, [x4],#-60 + 364: f8422738 ldr x24, [x25],#34 + 368: b85e5790 ldr w16, [x28],#-27 + 36c: 385e56e8 ldrb w8, [x23],#-27 + 370: 785c6403 ldrh w3, [x0],#-58 + 374: 389f65ee ldrsb x14, [x15],#-10 + 378: 7880d42c ldrsh x12, [x1],#13 + 37c: 78ded429 ldrsh w9, [x1],#-19 + 380: b89c355d ldrsw x29, [x10],#-61 + 384: fc5f778d ldr d13, [x28],#-9 + 388: bc5a8774 ldr s20, [x27],#-88 + 38c: fc139567 str d7, [x11],#-199 + 390: bc1c36d4 str s20, [x22],#-61 + 394: f830c943 str x3, [x10,w16,sxtw] + 398: b8357ba1 str w1, [x29,x21,lsl #2] + 39c: 3837581a strb w26, [x0,w23,uxtw #0] + 3a0: 7835681a strh w26, [x0,x21] + 3a4: f8766b23 ldr x3, [x25,x22] + 3a8: b8785939 ldr w25, [x9,w24,uxtw #2] + 3ac: 386ed80a ldrb w10, [x0,w14,sxtw #0] + 3b0: 78747aa2 ldrh w2, [x21,x20,lsl #1] + 3b4: 38bcfb73 ldrsb x19, [x27,x28,sxtx #0] + 3b8: 78a37901 ldrsh x1, [x8,x3,lsl #1] + 3bc: 78f0e9f4 ldrsh w20, [x15,x16,sxtx] + 3c0: b8ac78e7 ldrsw x7, [x7,x12,lsl #2] + 3c4: fc6dd88f ldr d15, [x4,w13,sxtw #3] + 3c8: bc63494e ldr s14, [x10,w3,uxtw] + 3cc: fc29faf8 str d24, [x23,x9,sxtx #3] + 3d0: bc3a5989 str s9, [x12,w26,uxtw #2] + 3d4: f91a530e str x14, [x24,#13472] + 3d8: b91ce1c0 str w0, [x14,#7392] + 3dc: 39180277 strb w23, [x19,#1536] + 3e0: 791c316f strh w15, [x11,#3608] + 3e4: f95ab735 ldr x21, [x25,#13672] + 3e8: b95810f7 ldr w23, [x7,#6160] + 3ec: 395ede17 ldrb w23, [x16,#1975] + 3f0: 795e1718 ldrh w24, [x24,#3850] + 3f4: 3999352c ldrsb x12, [x9,#1613] + 3f8: 799e02a5 ldrsh x5, [x21,#3840] + 3fc: 79dc0c0e ldrsh w14, [x0,#3590] + 400: b99ef84d ldrsw x13, [x2,#7928] + 404: fd5ede6f ldr d15, [x19,#15800] + 408: bd5880b7 ldr s23, [x5,#6272] + 40c: fd1d90c6 str d6, [x6,#15136] + 410: bd182569 str s9, [x11,#6180] + 414: 58002267 ldr x7, 860 + 418: 1800001d ldr w29, 418 + 41c: f8929000 prfum pldl1keep, [x0,#-215] + 420: d8002200 prfm pldl1keep, 860 + 424: f8a34880 prfm pldl1keep, [x4,w3,uxtw] + 428: f99825c0 prfm pldl1keep, [x14,#12360] + 42c: 1a0400c7 adc w7, w6, w4 + 430: 3a05019b adcs w27, w12, w5 + 434: 5a1a0319 sbc w25, w24, w26 + 438: 7a1700e5 sbcs w5, w7, w23 + 43c: 9a010176 adc x22, x11, x1 + 440: ba1d012d adcs x13, x9, x29 + 444: da1a01c4 sbc x4, x14, x26 + 448: fa1803bc sbcs x28, x29, x24 + 44c: 0b3546b1 add w17, w21, w21, uxtw #1 + 450: 2b3aad2c adds w12, w9, w26, sxth #3 + 454: cb2324ae sub x14, x5, w3, uxth #1 + 458: 6b267351 subs w17, w26, w6, uxtx #4 + 45c: 8b34acb1 add x17, x5, w20, sxth #3 + 460: ab39cc30 adds x16, x1, w25, sxtw #3 + 464: cb3aec39 sub x25, x1, x26, sxtx #3 + 468: eb37ac33 subs x19, x1, w23, sxth #3 + 46c: 3a589029 ccmn w1, w24, #0x9, ls + 470: 7a4ac1c4 ccmp w14, w10, #0x4, gt + 474: ba5d3120 ccmn x9, x29, #0x0, cc + 478: fa4640cd ccmp x6, x6, #0xd, mi + 47c: 3a4b1a65 ccmn w19, #0xb, #0x5, ne + 480: 7a5fa96f ccmp w11, #0x1f, #0xf, ge + 484: ba4e6985 ccmn x12, #0xe, #0x5, vs + 488: fa47482a ccmp x1, #0x7, #0xa, mi + 48c: 1a963046 csel w6, w2, w22, cc + 490: 1a9a66dd csinc w29, w22, w26, vs + 494: 5a8b933a csinv w26, w25, w11, ls + 498: 5a90c5d3 csneg w19, w14, w16, gt + 49c: 9a9422ad csel x13, x21, x20, cs + 4a0: 9a9b856c csinc x12, x11, x27, hi + 4a4: da93d223 csinv x3, x17, x19, le + 4a8: da876438 csneg x24, x1, x7, vs + 4ac: 5ac00037 rbit w23, w1 + 4b0: 5ac00610 rev16 w16, w16 + 4b4: 5ac00b38 rev w24, w25 + 4b8: 5ac01119 clz w25, w8 + 4bc: 5ac0159b cls w27, w12 + 4c0: dac000b5 rbit x21, x5 + 4c4: dac00534 rev16 x20, x9 + 4c8: dac00934 rev32 x20, x9 + 4cc: dac00d53 rev x19, x10 + 4d0: dac01048 clz x8, x2 + 4d4: dac0147d cls x29, x3 + 4d8: 1add08f3 udiv w19, w7, w29 + 4dc: 1aca0f7a sdiv w26, w27, w10 + 4e0: 1ad02300 lsl w0, w24, w16 + 4e4: 1ad82556 lsr w22, w10, w24 + 4e8: 1ad02b40 asr w0, w26, w16 + 4ec: 1acf2f3b ror w27, w25, w15 + 4f0: 9acf0b88 udiv x8, x28, x15 + 4f4: 9ac50d74 sdiv x20, x11, x5 + 4f8: 9ad02335 lsl x21, x25, x16 + 4fc: 9ace2447 lsr x7, x2, x14 + 500: 9ad62915 asr x21, x8, x22 + 504: 9acf2ca7 ror x7, x5, x15 + 508: 9bd67eac umulh x12, x21, x22 + 50c: 9b457d50 smulh x16, x10, x5 + 510: 1b1a54c2 madd w2, w6, w26, w21 + 514: 1b03ee7b msub w27, w19, w3, w27 + 518: 9b080cbb madd x27, x5, x8, x3 + 51c: 9b1cb5a8 msub x8, x13, x28, x13 + 520: 9b28013d smaddl x29, w9, w8, x0 + 524: 9b2edd2e smsubl x14, w9, w14, x23 + 528: 9bab348f umaddl x15, w4, w11, x13 + 52c: 9bb1e077 umsubl x23, w3, w17, x24 + 530: 1e31083d fmul s29, s1, s17 + 534: 1e291b97 fdiv s23, s28, s9 + 538: 1e2c2a6e fadd s14, s19, s12 + 53c: 1e203a3b fsub s27, s17, s0 + 540: 1e260b10 fmul s16, s24, s6 + 544: 1e6a0ae4 fmul d4, d23, d10 + 548: 1e77192b fdiv d11, d9, d23 + 54c: 1e6729e7 fadd d7, d15, d7 + 550: 1e6c3abd fsub d29, d21, d12 + 554: 1e69089b fmul d27, d4, d9 + 558: 1f0b65db fmadd s27, s14, s11, s25 + 55c: 1f0f8ecb fmsub s11, s22, s15, s3 + 560: 1f38136a fnmadd s10, s27, s24, s4 + 564: 1f2104c4 fnmadd s4, s6, s1, s1 + 568: 1f430b8d fmadd d13, d28, d3, d2 + 56c: 1f47eb1a fmsub d26, d24, d7, d26 + 570: 1f6c68b5 fnmadd d21, d5, d12, d26 + 574: 1f740e0b fnmadd d11, d16, d20, d3 + 578: 1e204225 fmov s5, s17 + 57c: 1e20c127 fabs s7, s9 + 580: 1e214039 fneg s25, s1 + 584: 1e21c0d8 fsqrt s24, s6 + 588: 1e22c23b fcvt d27, s17 + 58c: 1e604056 fmov d22, d2 + 590: 1e60c28e fabs d14, d20 + 594: 1e61417d fneg d29, d11 + 598: 1e61c19c fsqrt d28, d12 + 59c: 1e624064 fcvt s4, d3 + 5a0: 1e3801bc fcvtzs w28, s13 + 5a4: 9e380387 fcvtzs x7, s28 + 5a8: 1e7801ec fcvtzs w12, d15 + 5ac: 9e7800cb fcvtzs x11, d6 + 5b0: 1e2202d6 scvtf s22, w22 + 5b4: 9e220205 scvtf s5, x16 + 5b8: 1e6201e3 scvtf d3, w15 + 5bc: 9e620106 scvtf d6, x8 + 5c0: 1e2603ba fmov w26, s29 + 5c4: 9e660238 fmov x24, d17 + 5c8: 1e270262 fmov s2, w19 + 5cc: 9e6700b5 fmov d21, x5 + 5d0: 1e2822e0 fcmp s23, s8 + 5d4: 1e622180 fcmp d12, d2 + 5d8: 1e2021c8 fcmp s14, #0.0 + 5dc: 1e602148 fcmp d10, #0.0 + 5e0: 29344588 stp w8, w17, [x12,#-96] + 5e4: 29685781 ldp w1, w21, [x28,#-192] + 5e8: 69785a19 ldpsw x25, x22, [x16,#-64] + 5ec: a93822e6 stp x6, x8, [x23,#-128] + 5f0: a9794279 ldp x25, x16, [x19,#-112] + 5f4: 29a26dbd stp w29, w27, [x13,#-240]! + 5f8: 29fc52ac ldp w12, w20, [x21,#-32]! + 5fc: 69ee3c80 ldpsw x0, x15, [x4,#-144]! + 600: a988326d stp x13, x12, [x19,#128]! + 604: a9c60939 ldp x25, x2, [x9,#96]! + 608: 2890074b stp w11, w1, [x26],#128 + 60c: 28c4647a ldp w26, w25, [x3],#32 + 610: 68e2384a ldpsw x10, x14, [x2],#-240 + 614: a8880d41 stp x1, x3, [x10],#128 + 618: a8f73337 ldp x23, x12, [x25],#-144 + 61c: 28082325 stnp w5, w8, [x25,#64] + 620: 28624ed4 ldnp w20, w19, [x22,#-240] + 624: a8351dd7 stnp x23, x7, [x14,#-176] + 628: a84472ae ldnp x14, x28, [x21,#64] + 62c: 0c40708a ld1 {v10.8b}, [x4] + 630: 4cdfa359 ld1 {v25.16b, v26.16b}, [x26], #32 + 634: 0cd76c9b ld1 {v27.1d-v29.1d}, [x4], x23 + 638: 4cdf24d0 ld1 {v16.8h-v19.8h}, [x6], #64 + 63c: 0d40c361 ld1r {v1.8b}, [x27] + 640: 4ddfc844 ld1r {v4.4s}, [x2], #4 + 644: 0dcfcfb5 ld1r {v21.1d}, [x29], x15 + 648: 4c408ec1 ld2 {v1.2d, v2.2d}, [x22] + 64c: 0cdf851d ld2 {v29.4h, v30.4h}, [x8], #16 + 650: 4d60c098 ld2r {v24.16b, v25.16b}, [x4] + 654: 0dffca75 ld2r {v21.2s, v22.2s}, [x19], #8 + 658: 4de6cdad ld2r {v13.2d, v14.2d}, [x13], x6 + 65c: 4cd14881 ld3 {v1.4s-v3.4s}, [x4], x17 + 660: 0c404a36 ld3 {v22.2s-v24.2s}, [x17] + 664: 4d40e631 ld3r {v17.8h-v19.8h}, [x17] + 668: 4ddfeb88 ld3r {v8.4s-v10.4s}, [x28], #12 + 66c: 0dd3ec25 ld3r {v5.1d-v7.1d}, [x1], x19 + 670: 4cdf05e1 ld4 {v1.8h-v4.8h}, [x15], #64 + 674: 0cda00d1 ld4 {v17.8b-v20.8b}, [x6], x26 + 678: 0d60e0f9 ld4r {v25.8b-v28.8b}, [x7] + 67c: 0dffe50c ld4r {v12.4h-v15.4h}, [x8], #8 + 680: 0de1e9a9 ld4r {v9.2s-v12.2s}, [x13], x1 + 684: ba5fd3e3 ccmn xzr, xzr, #0x3, le + 688: 3a5f03e5 ccmn wzr, wzr, #0x5, eq + 68c: fa411be4 ccmp xzr, #0x1, #0x4, ne + 690: 7a42cbe2 ccmp wzr, #0x2, #0x2, gt + 694: 93df03ff ror xzr, xzr, #0 + 698: c820ffff stlxp w0, xzr, xzr, [sp] + 69c: 8822fc7f stlxp w2, wzr, wzr, [x3] + 6a0: c8247cbf stxp w4, xzr, xzr, [x5] + 6a4: 88267fff stxp w6, wzr, wzr, [sp] + 6a8: 4e010fe0 dup v0.16b, wzr + 6ac: 4e081fe1 mov v1.d[0], xzr + 6b0: 4e0c1fe1 mov v1.s[1], wzr + 6b4: 4e0a1fe1 mov v1.h[2], wzr + 6b8: 4e071fe1 mov v1.b[3], wzr + 6bc: 4cc0ac3f ld1 {v31.2d, v0.2d}, [x1], x0 + 6c0: 1e601000 fmov d0, #2.000000000000000000e+00 + 6c4: 1e603000 fmov d0, #2.125000000000000000e+00 + 6c8: 1e621000 fmov d0, #4.000000000000000000e+00 + 6cc: 1e623000 fmov d0, #4.250000000000000000e+00 + 6d0: 1e641000 fmov d0, #8.000000000000000000e+00 + 6d4: 1e643000 fmov d0, #8.500000000000000000e+00 + 6d8: 1e661000 fmov d0, #1.600000000000000000e+01 + 6dc: 1e663000 fmov d0, #1.700000000000000000e+01 + 6e0: 1e681000 fmov d0, #1.250000000000000000e-01 + 6e4: 1e683000 fmov d0, #1.328125000000000000e-01 + 6e8: 1e6a1000 fmov d0, #2.500000000000000000e-01 + 6ec: 1e6a3000 fmov d0, #2.656250000000000000e-01 + 6f0: 1e6c1000 fmov d0, #5.000000000000000000e-01 + 6f4: 1e6c3000 fmov d0, #5.312500000000000000e-01 + 6f8: 1e6e1000 fmov d0, #1.000000000000000000e+00 + 6fc: 1e6e3000 fmov d0, #1.062500000000000000e+00 + 700: 1e701000 fmov d0, #-2.000000000000000000e+00 + 704: 1e703000 fmov d0, #-2.125000000000000000e+00 + 708: 1e721000 fmov d0, #-4.000000000000000000e+00 + 70c: 1e723000 fmov d0, #-4.250000000000000000e+00 + 710: 1e741000 fmov d0, #-8.000000000000000000e+00 + 714: 1e743000 fmov d0, #-8.500000000000000000e+00 + 718: 1e761000 fmov d0, #-1.600000000000000000e+01 + 71c: 1e763000 fmov d0, #-1.700000000000000000e+01 + 720: 1e781000 fmov d0, #-1.250000000000000000e-01 + 724: 1e783000 fmov d0, #-1.328125000000000000e-01 + 728: 1e7a1000 fmov d0, #-2.500000000000000000e-01 + 72c: 1e7a3000 fmov d0, #-2.656250000000000000e-01 + 730: 1e7c1000 fmov d0, #-5.000000000000000000e-01 + 734: 1e7c3000 fmov d0, #-5.312500000000000000e-01 + 738: 1e7e1000 fmov d0, #-1.000000000000000000e+00 + 73c: 1e7e3000 fmov d0, #-1.062500000000000000e+00 + 740: f83a80c3 swp x26, x3, [x6] + 744: f834008c ldadd x20, x12, [x4] + 748: f8371164 ldclr x23, x4, [x11] + 74c: f82f230f ldeor x15, x15, [x24] + 750: f83d3222 ldset x29, x2, [x17] + 754: f8395025 ldsmin x25, x5, [x1] + 758: f82f40ef ldsmax x15, x15, [x7] + 75c: f83c73bf stumin x28, [x29] + 760: f83163f1 ldumax x17, x17, [sp] + 764: f8a782b0 swpa x7, x16, [x21] + 768: f8b1028a ldadda x17, x10, [x20] + 76c: f8b913ae ldclra x25, x14, [x29] + 770: f8b9206d ldeora x25, x13, [x3] + 774: f8ad3387 ldseta x13, x7, [x28] + 778: f8b450f9 ldsmina x20, x25, [x7] + 77c: f8b54044 ldsmaxa x21, x4, [x2] + 780: f8a87105 ldumina x8, x5, [x8] + 784: f8aa60cc ldumaxa x10, x12, [x6] + 788: f8f9814c swpal x25, x12, [x10] + 78c: f8ec0081 ldaddal x12, x1, [x4] + 790: f8fa1186 ldclral x26, x6, [x12] + 794: f8e1218e ldeoral x1, x14, [x12] + 798: f8f632a6 ldsetal x22, x6, [x21] + 79c: f8ef50c4 ldsminal x15, x4, [x6] + 7a0: f8f840f0 ldsmaxal x24, x16, [x7] + 7a4: f8e57163 lduminal x5, x3, [x11] + 7a8: f8f66322 ldumaxal x22, x2, [x25] + 7ac: f866801d swpl x6, x29, [x0] + 7b0: f87a02e6 ldaddl x26, x6, [x23] + 7b4: f8641127 ldclrl x4, x7, [x9] + 7b8: f866202b ldeorl x6, x11, [x1] + 7bc: f86b33ad ldsetl x11, x13, [x29] + 7c0: f86b50c3 ldsminl x11, x3, [x6] + 7c4: f8754160 ldsmaxl x21, x0, [x11] + 7c8: f86b7137 lduminl x11, x23, [x9] + 7cc: f8716210 ldumaxl x17, x16, [x16] + 7d0: b83583e5 swp w21, w5, [sp] + 7d4: b838008b ldadd w24, w11, [x4] + 7d8: b831109d ldclr w17, w29, [x4] + 7dc: b82f21eb ldeor w15, w11, [x15] + 7e0: b83b317a ldset w27, w26, [x11] + 7e4: b83b510c ldsmin w27, w12, [x8] + 7e8: b8264034 ldsmax w6, w20, [x1] + 7ec: b82e73b0 ldumin w14, w16, [x29] + 7f0: b838634d ldumax w24, w13, [x26] + 7f4: b8a48162 swpa w4, w2, [x11] + 7f8: b8b4009d ldadda w20, w29, [x4] + 7fc: b8b413bf ldclra w20, wzr, [x29] + 800: b8a0232f ldeora w0, w15, [x25] + 804: b8b73285 ldseta w23, w5, [x20] + 808: b8bd527a ldsmina w29, w26, [x19] + 80c: b8b542d4 ldsmaxa w21, w20, [x22] + 810: b8ba7215 ldumina w26, w21, [x16] + 814: b8a86155 ldumaxa w8, w21, [x10] + 818: b8fb816b swpal w27, w11, [x11] + 81c: b8e50388 ldaddal w5, w8, [x28] + 820: b8e010a5 ldclral w0, w5, [x5] + 824: b8e2230a ldeoral w2, w10, [x24] + 828: b8ed33ff ldsetal w13, wzr, [sp] + 82c: b8fa5319 ldsminal w26, w25, [x24] + 830: b8e840c5 ldsmaxal w8, w5, [x6] + 834: b8e5737b lduminal w5, w27, [x27] + 838: b8f762f4 ldumaxal w23, w20, [x23] + 83c: b8798383 swpl w25, w3, [x28] + 840: b86a01a8 ldaddl w10, w8, [x13] + 844: b87513eb ldclrl w21, w11, [sp] + 848: b87f2383 ldeorl wzr, w3, [x28] + 84c: b86f3300 ldsetl w15, w0, [x24] + 850: b86453a9 ldsminl w4, w9, [x29] + 854: b86842a6 ldsmaxl w8, w6, [x21] + 858: b8697076 lduminl w9, w22, [x3] + 85c: b87a638a ldumaxl w26, w10, [x28] */ static const unsigned int insns[] = { - 0x8b0d82fa, 0xcb49970c, 0xab889dfc, 0xeb9ee787, - 0x0b9b3ec9, 0x4b9279a3, 0x2b88474e, 0x6b8c56c0, - 0x8a1a51e0, 0xaa11f4ba, 0xca0281b8, 0xea918c7c, - 0x0a5d4a19, 0x2a4b264d, 0x4a523ca5, 0x6a9b6ae2, - 0x8a70b79b, 0xaaba9728, 0xca6dfe3d, 0xea627f1c, - 0x0aa70f53, 0x2aaa0f06, 0x4a6176a4, 0x6a604eb0, - 0x1105ed91, 0x3100583e, 0x5101f8bd, 0x710f0306, - 0x9101a1a0, 0xb10a5cc8, 0xd10810aa, 0xf10fd061, - 0x120cb166, 0x321764bc, 0x52174681, 0x720c0247, - 0x9241018e, 0xb25a2969, 0xd278b411, 0xf26aad01, - 0x14000000, 0x17ffffd7, 0x140001f2, 0x94000000, - 0x97ffffd4, 0x940001ef, 0x3400000a, 0x34fffa2a, - 0x34003d8a, 0x35000008, 0x35fff9c8, 0x35003d28, - 0xb400000b, 0xb4fff96b, 0xb4003ccb, 0xb500001d, - 0xb5fff91d, 0xb5003c7d, 0x10000013, 0x10fff8b3, - 0x10003c13, 0x90000013, 0x36300016, 0x3637f836, - 0x36303b96, 0x3758000c, 0x375ff7cc, 0x37583b2c, - 0x128313a0, 0x528a32c7, 0x7289173b, 0x92ab3acc, - 0xd2a0bf94, 0xf2c285e8, 0x9358722f, 0x330e652f, - 0x53067f3b, 0x93577c53, 0xb34a1aac, 0xd35a4016, - 0x13946c63, 0x93c3dbc8, 0x54000000, 0x54fff5a0, - 0x54003900, 0x54000001, 0x54fff541, 0x540038a1, - 0x54000002, 0x54fff4e2, 0x54003842, 0x54000002, - 0x54fff482, 0x540037e2, 0x54000003, 0x54fff423, - 0x54003783, 0x54000003, 0x54fff3c3, 0x54003723, - 0x54000004, 0x54fff364, 0x540036c4, 0x54000005, - 0x54fff305, 0x54003665, 0x54000006, 0x54fff2a6, - 0x54003606, 0x54000007, 0x54fff247, 0x540035a7, - 0x54000008, 0x54fff1e8, 0x54003548, 0x54000009, - 0x54fff189, 0x540034e9, 0x5400000a, 0x54fff12a, - 0x5400348a, 0x5400000b, 0x54fff0cb, 0x5400342b, - 0x5400000c, 0x54fff06c, 0x540033cc, 0x5400000d, - 0x54fff00d, 0x5400336d, 0x5400000e, 0x54ffefae, - 0x5400330e, 0x5400000f, 0x54ffef4f, 0x540032af, - 0xd40658e1, 0xd4014d22, 0xd4046543, 0xd4273f60, - 0xd44cad80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, - 0xd5033fdf, 0xd5033e9f, 0xd50332bf, 0xd61f0200, - 0xd63f0280, 0xc80a7d1b, 0xc800fea1, 0xc85f7fb1, - 0xc85fff9d, 0xc89ffee1, 0xc8dffe95, 0x88167e7b, - 0x880bfcd0, 0x885f7c12, 0x885ffd44, 0x889ffed8, - 0x88dffe6a, 0x48017fc5, 0x4808fe2c, 0x485f7dc9, - 0x485ffc27, 0x489ffe05, 0x48dffd82, 0x080a7c6c, - 0x081cff4e, 0x085f7d5e, 0x085ffeae, 0x089ffd2d, - 0x08dfff76, 0xc87f4d7c, 0xc87fcc5e, 0xc8220417, - 0xc82cb5f0, 0x887f55b2, 0x887ff90b, 0x88382c2d, - 0x883aedb5, 0xf819928b, 0xb803e21c, 0x381f713b, - 0x781ce322, 0xf850f044, 0xb85e129e, 0x385e92f2, - 0x785ff35d, 0x39801921, 0x7881318b, 0x78dce02b, - 0xb8829313, 0xfc45f318, 0xbc5d50af, 0xfc001375, - 0xbc1951b7, 0xf8008c0b, 0xb801dc03, 0x38009dcb, - 0x781fdf1d, 0xf8570e2d, 0xb85faecc, 0x385f6d8d, - 0x785ebea0, 0x38804cf7, 0x789cbce3, 0x78df9cbc, - 0xb89eed38, 0xfc40cd6e, 0xbc5bdd93, 0xfc103c14, - 0xbc040c08, 0xf81a2784, 0xb81ca4ec, 0x381e855b, - 0x7801b506, 0xf853654e, 0xb85d74b0, 0x384095c2, - 0x785ec5bc, 0x389e15a9, 0x789dc703, 0x78c06474, - 0xb89ff667, 0xfc57e51e, 0xbc4155f9, 0xfc05a6ee, - 0xbc1df408, 0xf835da4a, 0xb836d9a4, 0x3833580d, - 0x7826cb6c, 0xf8706900, 0xb87ae880, 0x3865db2e, - 0x78724889, 0x38a7789b, 0x78beca2f, 0x78f6c810, - 0xb8bef956, 0xfc6afabd, 0xbc734963, 0xfc3d5b8d, - 0xbc25fbb7, 0xf9189d05, 0xb91ecb1d, 0x39187a33, - 0x791f226d, 0xf95aa2f3, 0xb9587bb7, 0x395f7176, - 0x795d9143, 0x399e7e08, 0x799a2697, 0x79df3422, - 0xb99c2624, 0xfd5c2374, 0xbd5fa1d9, 0xfd1d595a, - 0xbd1b1869, 0x580022fb, 0x1800000b, 0xf8945060, - 0xd8000000, 0xf8ae6ba0, 0xf99a0080, 0x1a070035, - 0x3a0700a8, 0x5a0e0367, 0x7a11009b, 0x9a000380, - 0xba1e030c, 0xda0f0320, 0xfa030301, 0x0b340b12, - 0x2b2a278d, 0xcb22aa0f, 0x6b2d29bd, 0x8b2cce8c, - 0xab2b877e, 0xcb21c8ee, 0xeb3ba47d, 0x3a4d400e, - 0x7a5232c6, 0xba5e624e, 0xfa53814c, 0x3a52d8c2, - 0x7a4d8924, 0xba4b3aab, 0xfa4d7882, 0x1a96804c, - 0x1a912618, 0x5a90b0e6, 0x5a96976b, 0x9a9db06a, - 0x9a9b374c, 0xda95c14f, 0xda89c6fe, 0x5ac0015e, - 0x5ac005fd, 0x5ac00bdd, 0x5ac012b9, 0x5ac01404, - 0xdac002b2, 0xdac0061d, 0xdac00a95, 0xdac00e66, - 0xdac0107e, 0xdac01675, 0x1ac00b0b, 0x1ace0f3b, - 0x1ad221c3, 0x1ad825e7, 0x1ad92a3c, 0x1adc2f42, - 0x9ada0b25, 0x9ad20e1b, 0x9acc22a6, 0x9acc2480, - 0x9adc2a3b, 0x9ad22c5c, 0x9bce7dea, 0x9b597c6e, - 0x1b0e166f, 0x1b1ae490, 0x9b023044, 0x9b089e3d, - 0x9b391083, 0x9b24c73a, 0x9bb15f40, 0x9bbcc6af, - 0x1e23095b, 0x1e3918e0, 0x1e2f28c9, 0x1e2a39fd, - 0x1e270a22, 0x1e77096b, 0x1e771ba7, 0x1e6b2b6e, - 0x1e78388b, 0x1e6e09ec, 0x1f1c3574, 0x1f17f98b, - 0x1f2935da, 0x1f2574ea, 0x1f4b306f, 0x1f5ec7cf, - 0x1f6f3e93, 0x1f6226a9, 0x1e2040fb, 0x1e20c3dd, - 0x1e214031, 0x1e21c0c2, 0x1e22c06a, 0x1e604178, - 0x1e60c027, 0x1e61400b, 0x1e61c243, 0x1e6240dc, - 0x1e3800d6, 0x9e380360, 0x1e78005a, 0x9e7800e5, - 0x1e22017c, 0x9e2201b9, 0x1e6202eb, 0x9e620113, - 0x1e2602b2, 0x9e660299, 0x1e270253, 0x9e6703a2, - 0x1e2822c0, 0x1e7322a0, 0x1e202288, 0x1e602168, - 0x293c19f4, 0x2966387b, 0x69762971, 0xa9041dc7, - 0xa9475c0c, 0x29b61ccd, 0x29ee405e, 0x69ee0744, - 0xa9843977, 0xa9f46ebd, 0x28ba16b6, 0x28fc44db, - 0x68f61831, 0xa8b352ad, 0xa8c56d5e, 0x28024565, - 0x2874134e, 0xa8027597, 0xa87b1aa0, 0x0c40734f, - 0x4cdfa177, 0x0cc76ee8, 0x4cdf2733, 0x0d40c23d, - 0x4ddfcaf8, 0x0dd9ccaa, 0x4c408d52, 0x0cdf85ec, - 0x4d60c259, 0x0dffcbc1, 0x4de9ce50, 0x4cc24999, - 0x0c404a7a, 0x4d40e6af, 0x4ddfe9b9, 0x0dddef8e, - 0x4cdf07b1, 0x0cc000fb, 0x0d60e258, 0x0dffe740, - 0x0de2eb2c, 0xce648376, 0xce6184c7, 0xcec081fa, - 0xce6d89a2, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, + 0x8b1ad014, 0xcb83db85, 0xab839ecb, 0xeb4c646b, + 0x0b0d399b, 0x4b9b1eaa, 0x2b1011c3, 0x6b1d1661, + 0x8a5b1a30, 0xaa1c8f96, 0xca5ccd4b, 0xea8ec10d, + 0x0a410c61, 0x2a855909, 0x4a9b4f82, 0x6a073938, + 0x8ab9826b, 0xaa3d7318, 0xcab16e0b, 0xea6ae9a5, + 0x0a357545, 0x2a354d64, 0x4a7c3f95, 0x6a2e7146, + 0x110ec6ca, 0x310e9d6f, 0x510afcc5, 0x7108e013, + 0x91098114, 0xb10434d0, 0xd10db417, 0xf10c873a, + 0x120d6a0c, 0x32066b01, 0x52112073, 0x720a553d, + 0x9263d0ba, 0xb20da1d8, 0xd26ec404, 0xf26e28dc, + 0x14000000, 0x17ffffd7, 0x140001ee, 0x94000000, + 0x97ffffd4, 0x940001eb, 0x34000015, 0x34fffa35, + 0x34003d15, 0x3500000c, 0x35fff9cc, 0x35003cac, + 0xb400000e, 0xb4fff96e, 0xb4003c4e, 0xb500001b, + 0xb5fff91b, 0xb5003bfb, 0x1000000e, 0x10fff8ae, + 0x10003b8e, 0x90000016, 0x36280000, 0x362ff820, + 0x36283b00, 0x37580003, 0x375ff7c3, 0x37583aa3, + 0x12835753, 0x52a2da7c, 0x72a9ef0d, 0x92c097e1, + 0xd28e0a7a, 0xf2e2d05b, 0x93496301, 0x33054019, + 0x530f1f70, 0x934f71d0, 0xb3403558, 0xd34259c1, + 0x1381540a, 0x93d7f75a, 0x54000000, 0x54fff5a0, + 0x54003880, 0x54000001, 0x54fff541, 0x54003821, + 0x54000002, 0x54fff4e2, 0x540037c2, 0x54000002, + 0x54fff482, 0x54003762, 0x54000003, 0x54fff423, + 0x54003703, 0x54000003, 0x54fff3c3, 0x540036a3, + 0x54000004, 0x54fff364, 0x54003644, 0x54000005, + 0x54fff305, 0x540035e5, 0x54000006, 0x54fff2a6, + 0x54003586, 0x54000007, 0x54fff247, 0x54003527, + 0x54000008, 0x54fff1e8, 0x540034c8, 0x54000009, + 0x54fff189, 0x54003469, 0x5400000a, 0x54fff12a, + 0x5400340a, 0x5400000b, 0x54fff0cb, 0x540033ab, + 0x5400000c, 0x54fff06c, 0x5400334c, 0x5400000d, + 0x54fff00d, 0x540032ed, 0x5400000e, 0x54ffefae, + 0x5400328e, 0x5400000f, 0x54ffef4f, 0x5400322f, + 0xd4079461, 0xd4018ee2, 0xd408d7c3, 0xd4216040, + 0xd44a2f80, 0xd503201f, 0xd69f03e0, 0xd6bf03e0, + 0xd5033fdf, 0xd503329f, 0xd50339bf, 0xd61f0140, + 0xd63f02c0, 0xc8037cb5, 0xc81cffa9, 0xc85f7cfc, + 0xc85ffeea, 0xc89fff47, 0xc8dffef0, 0x880b7d87, + 0x8810ff4d, 0x885f7eb9, 0x885ffc8e, 0x889ffd3a, + 0x88dffee0, 0x48087d40, 0x480bfc81, 0x485f7f4e, + 0x485ffcf3, 0x489ffed1, 0x48dffcd4, 0x08197cc8, + 0x0805ff2a, 0x085f7ec0, 0x085ffc68, 0x089ffc45, + 0x08dfff86, 0xc87f21d1, 0xc87f8c4e, 0xc8391271, + 0xc82abd10, 0x887f2c61, 0x887fed80, 0x882457b4, + 0x882097a9, 0xf811d091, 0xb81df086, 0x39002e0d, + 0x781c02d7, 0xf840d062, 0xb8423285, 0x385f1142, + 0x785f8017, 0x389fd1cf, 0x789f4063, 0x78df9319, + 0xb89e3011, 0xfc5b1127, 0xbc5bc16b, 0xfc189050, + 0xbc184399, 0xf8052e7c, 0xb8032da7, 0x381e0e62, + 0x781c6c38, 0xf8571fb7, 0xb8400f6d, 0x385e6d4b, + 0x785cacc3, 0x38803d22, 0x7881ec9c, 0x78de9c11, + 0xb898bf3d, 0xfc572d55, 0xbc423e8b, 0xfc12ade1, + 0xbc1c9cb3, 0xf81ec63c, 0xb81f75a8, 0x381e970e, + 0x781c4482, 0xf8422738, 0xb85e5790, 0x385e56e8, + 0x785c6403, 0x389f65ee, 0x7880d42c, 0x78ded429, + 0xb89c355d, 0xfc5f778d, 0xbc5a8774, 0xfc139567, + 0xbc1c36d4, 0xf830c943, 0xb8357ba1, 0x3837581a, + 0x7835681a, 0xf8766b23, 0xb8785939, 0x386ed80a, + 0x78747aa2, 0x38bcfb73, 0x78a37901, 0x78f0e9f4, + 0xb8ac78e7, 0xfc6dd88f, 0xbc63494e, 0xfc29faf8, + 0xbc3a5989, 0xf91a530e, 0xb91ce1c0, 0x39180277, + 0x791c316f, 0xf95ab735, 0xb95810f7, 0x395ede17, + 0x795e1718, 0x3999352c, 0x799e02a5, 0x79dc0c0e, + 0xb99ef84d, 0xfd5ede6f, 0xbd5880b7, 0xfd1d90c6, + 0xbd182569, 0x58002267, 0x1800001d, 0xf8929000, + 0xd8002200, 0xf8a34880, 0xf99825c0, 0x1a0400c7, + 0x3a05019b, 0x5a1a0319, 0x7a1700e5, 0x9a010176, + 0xba1d012d, 0xda1a01c4, 0xfa1803bc, 0x0b3546b1, + 0x2b3aad2c, 0xcb2324ae, 0x6b267351, 0x8b34acb1, + 0xab39cc30, 0xcb3aec39, 0xeb37ac33, 0x3a589029, + 0x7a4ac1c4, 0xba5d3120, 0xfa4640cd, 0x3a4b1a65, + 0x7a5fa96f, 0xba4e6985, 0xfa47482a, 0x1a963046, + 0x1a9a66dd, 0x5a8b933a, 0x5a90c5d3, 0x9a9422ad, + 0x9a9b856c, 0xda93d223, 0xda876438, 0x5ac00037, + 0x5ac00610, 0x5ac00b38, 0x5ac01119, 0x5ac0159b, + 0xdac000b5, 0xdac00534, 0xdac00934, 0xdac00d53, + 0xdac01048, 0xdac0147d, 0x1add08f3, 0x1aca0f7a, + 0x1ad02300, 0x1ad82556, 0x1ad02b40, 0x1acf2f3b, + 0x9acf0b88, 0x9ac50d74, 0x9ad02335, 0x9ace2447, + 0x9ad62915, 0x9acf2ca7, 0x9bd67eac, 0x9b457d50, + 0x1b1a54c2, 0x1b03ee7b, 0x9b080cbb, 0x9b1cb5a8, + 0x9b28013d, 0x9b2edd2e, 0x9bab348f, 0x9bb1e077, + 0x1e31083d, 0x1e291b97, 0x1e2c2a6e, 0x1e203a3b, + 0x1e260b10, 0x1e6a0ae4, 0x1e77192b, 0x1e6729e7, + 0x1e6c3abd, 0x1e69089b, 0x1f0b65db, 0x1f0f8ecb, + 0x1f38136a, 0x1f2104c4, 0x1f430b8d, 0x1f47eb1a, + 0x1f6c68b5, 0x1f740e0b, 0x1e204225, 0x1e20c127, + 0x1e214039, 0x1e21c0d8, 0x1e22c23b, 0x1e604056, + 0x1e60c28e, 0x1e61417d, 0x1e61c19c, 0x1e624064, + 0x1e3801bc, 0x9e380387, 0x1e7801ec, 0x9e7800cb, + 0x1e2202d6, 0x9e220205, 0x1e6201e3, 0x9e620106, + 0x1e2603ba, 0x9e660238, 0x1e270262, 0x9e6700b5, + 0x1e2822e0, 0x1e622180, 0x1e2021c8, 0x1e602148, + 0x29344588, 0x29685781, 0x69785a19, 0xa93822e6, + 0xa9794279, 0x29a26dbd, 0x29fc52ac, 0x69ee3c80, + 0xa988326d, 0xa9c60939, 0x2890074b, 0x28c4647a, + 0x68e2384a, 0xa8880d41, 0xa8f73337, 0x28082325, + 0x28624ed4, 0xa8351dd7, 0xa84472ae, 0x0c40708a, + 0x4cdfa359, 0x0cd76c9b, 0x4cdf24d0, 0x0d40c361, + 0x4ddfc844, 0x0dcfcfb5, 0x4c408ec1, 0x0cdf851d, + 0x4d60c098, 0x0dffca75, 0x4de6cdad, 0x4cd14881, + 0x0c404a36, 0x4d40e631, 0x4ddfeb88, 0x0dd3ec25, + 0x4cdf05e1, 0x0cda00d1, 0x0d60e0f9, 0x0dffe50c, + 0x0de1e9a9, 0xba5fd3e3, 0x3a5f03e5, 0xfa411be4, 0x7a42cbe2, 0x93df03ff, 0xc820ffff, 0x8822fc7f, 0xc8247cbf, 0x88267fff, 0x4e010fe0, 0x4e081fe1, 0x4e0c1fe1, 0x4e0a1fe1, 0x4e071fe1, 0x4cc0ac3f, @@ -1429,24 +1418,24 @@ 0x1e741000, 0x1e743000, 0x1e761000, 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000, 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000, 0x1e7e3000, - 0xf8388098, 0xf8340010, 0xf8241175, 0xf83e22d0, - 0xf82432ef, 0xf83a5186, 0xf82f41ee, 0xf82973b9, - 0xf82b6194, 0xf8b28216, 0xf8b50358, 0xf8a61206, - 0xf8b02219, 0xf8bc3218, 0xf8ba514f, 0xf8ad428e, - 0xf8a173d7, 0xf8ae60c2, 0xf8e38328, 0xf8e003db, - 0xf8e513c5, 0xf8eb2019, 0xf8ff3260, 0xf8fd513a, - 0xf8fa41ec, 0xf8eb724b, 0xf8f96316, 0xf8608171, - 0xf86600dd, 0xf86512a5, 0xf8732250, 0xf87e339b, - 0xf861503c, 0xf874421d, 0xf86d73aa, 0xf87d62d3, - 0xb82a83e4, 0xb83503e8, 0xb833138a, 0xb82220b9, - 0xb82332c8, 0xb83350ad, 0xb83d42b8, 0xb83a7078, - 0xb83862fa, 0xb8af8075, 0xb8b80328, 0xb8b41230, - 0xb8a22001, 0xb8b83064, 0xb8ac539f, 0xb8aa405a, - 0xb8ac73f2, 0xb8a163ad, 0xb8e08193, 0xb8f101b6, - 0xb8fc13fe, 0xb8e1239a, 0xb8e4309e, 0xb8e6535e, - 0xb8f24109, 0xb8ec7280, 0xb8e16058, 0xb8608309, - 0xb87a03d0, 0xb86312ea, 0xb86a2244, 0xb862310b, - 0xb86a522f, 0xb862418a, 0xb86c71af, 0xb8626287, + 0xf83a80c3, 0xf834008c, 0xf8371164, 0xf82f230f, + 0xf83d3222, 0xf8395025, 0xf82f40ef, 0xf83c73bf, + 0xf83163f1, 0xf8a782b0, 0xf8b1028a, 0xf8b913ae, + 0xf8b9206d, 0xf8ad3387, 0xf8b450f9, 0xf8b54044, + 0xf8a87105, 0xf8aa60cc, 0xf8f9814c, 0xf8ec0081, + 0xf8fa1186, 0xf8e1218e, 0xf8f632a6, 0xf8ef50c4, + 0xf8f840f0, 0xf8e57163, 0xf8f66322, 0xf866801d, + 0xf87a02e6, 0xf8641127, 0xf866202b, 0xf86b33ad, + 0xf86b50c3, 0xf8754160, 0xf86b7137, 0xf8716210, + 0xb83583e5, 0xb838008b, 0xb831109d, 0xb82f21eb, + 0xb83b317a, 0xb83b510c, 0xb8264034, 0xb82e73b0, + 0xb838634d, 0xb8a48162, 0xb8b4009d, 0xb8b413bf, + 0xb8a0232f, 0xb8b73285, 0xb8bd527a, 0xb8b542d4, + 0xb8ba7215, 0xb8a86155, 0xb8fb816b, 0xb8e50388, + 0xb8e010a5, 0xb8e2230a, 0xb8ed33ff, 0xb8fa5319, + 0xb8e840c5, 0xb8e5737b, 0xb8f762f4, 0xb8798383, + 0xb86a01a8, 0xb87513eb, 0xb87f2383, 0xb86f3300, + 0xb86453a9, 0xb86842a6, 0xb8697076, 0xb87a638a, }; // END Generated code -- do not edit # HG changeset patch # User burban # Date 1596225036 14400 # Fri Jul 31 15:50:36 2020 -0400 # Node ID 5ff0bad9baa9c821ccdd6a44e903ec9fe66ac869 # Parent ebbe00c38bc9606cf540c58a7eb93bc090c1ce50 8248676: AArch64: Add workaround for LITable constructor Reviewed-by: aph Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp --- a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp @@ -244,7 +244,10 @@ // constructor to initialise the lookup tables -static void initLITables() __attribute__ ((constructor)); +static void initLITables(); +// Use an empty struct with a construtor as MSVC doesn't support `__attribute__ ((constructor))` +// See https://stackoverflow.com/questions/1113409/attribute-constructor-equivalent-in-vc +static struct initLITables_t { initLITables_t(void) { initLITables(); } } _initLITables; static void initLITables() { li_table_entry_count = 0; # HG changeset patch # User burban # Date 1596225049 14400 # Fri Jul 31 15:50:49 2020 -0400 # Node ID 8b9aeaaf8260b729488094b37670de830d43ad98 # Parent 5ff0bad9baa9c821ccdd6a44e903ec9fe66ac869 8248663: AArch64: Avoid existing macros/keywords of MSVC Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -1522,6 +1522,11 @@ #undef INSN +#ifdef _WIN64 +// In MSVC, `mvn` is defined as a macro and it affects compilation +#undef mvn +#endif + // Aliases for short forms of orn void mvn(Register Rd, Register Rm, enum shift_kind kind = LSL, unsigned shift = 0) { diff --git a/src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp --- a/src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.cpp @@ -543,7 +543,7 @@ Register cnt1, Register cnt2, Register result, Register tmp1, Register tmp2, FloatRegister vtmp1, FloatRegister vtmp2, FloatRegister vtmp3, int ae) { Label DONE, SHORT_LOOP, SHORT_STRING, SHORT_LAST, TAIL, STUB, - DIFFERENCE, NEXT_WORD, SHORT_LOOP_TAIL, SHORT_LAST2, SHORT_LAST_INIT, + DIFF, NEXT_WORD, SHORT_LOOP_TAIL, SHORT_LAST2, SHORT_LAST_INIT, SHORT_LOOP_START, TAIL_CHECK; bool isLL = ae == StrIntrinsicNode::LL; @@ -634,7 +634,7 @@ adds(cnt2, cnt2, isUL ? 4 : 8); br(GE, TAIL); eor(rscratch2, tmp1, tmp2); - cbnz(rscratch2, DIFFERENCE); + cbnz(rscratch2, DIFF); // main loop bind(NEXT_WORD); if (str1_isL == str2_isL) { @@ -660,10 +660,10 @@ eor(rscratch2, tmp1, tmp2); cbz(rscratch2, NEXT_WORD); - b(DIFFERENCE); + b(DIFF); bind(TAIL); eor(rscratch2, tmp1, tmp2); - cbnz(rscratch2, DIFFERENCE); + cbnz(rscratch2, DIFF); // Last longword. In the case where length == 4 we compare the // same longword twice, but that's still faster than another // conditional branch. @@ -687,7 +687,7 @@ // Find the first different characters in the longwords and // compute their difference. - bind(DIFFERENCE); + bind(DIFF); rev(rscratch2, rscratch2); clz(rscratch2, rscratch2); andr(rscratch2, rscratch2, isLL ? -8 : -16); diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -539,10 +539,10 @@ // Generalized Test Bit And Branch, including a "far" variety which // spans more than 32KiB. - void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) { + void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) { assert(cond == EQ || cond == NE, "must be"); - if (far) + if (isfar) cond = ~cond; void (Assembler::* branch)(Register Rt, int bitpos, Label &L); @@ -551,7 +551,7 @@ else branch = &Assembler::tbnz; - if (far) { + if (isfar) { Label L; (this->*branch)(Rt, bitpos, L); b(dest); # HG changeset patch # User burban # Date 1596225078 14400 # Fri Jul 31 15:51:18 2020 -0400 # Node ID 4b601a01242418da0db9da13db7a5091d2b17b34 # Parent 8b9aeaaf8260b729488094b37670de830d43ad98 8248681: AArch64: MSVC doesn't support __PRETTY_FUNCTION__ Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp @@ -192,7 +192,15 @@ mov(rscratch2, call_site); } +// Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__ +// Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention." +// https://reviews.llvm.org/D3311 + +#ifdef _WIN64 +#define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__) +#else #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__) +#endif // aliases defined in AARCH64 spec # HG changeset patch # User burban # Date 1596225089 14400 # Fri Jul 31 15:51:29 2020 -0400 # Node ID 19513275382c33aab8345dfcaef9dac8ca35274b # Parent 4b601a01242418da0db9da13db7a5091d2b17b34 8248498: Add build system support for Windows AArch64 Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/make/autoconf/basic.m4 b/make/autoconf/basic.m4 --- a/make/autoconf/basic.m4 +++ b/make/autoconf/basic.m4 @@ -118,6 +118,16 @@ ]) ############################################################################### +# Evaluates platform specific overrides for build devkit variables. +# $1: Name of variable +AC_DEFUN([BASIC_EVAL_BUILD_DEVKIT_VARIABLE], +[ + if test "x[$]$1" = x; then + eval $1="\${$1_${OPENJDK_BUILD_CPU}}" + fi +]) + +############################################################################### AC_DEFUN_ONCE([BASIC_SETUP_DEVKIT], [ AC_ARG_WITH([devkit], [AS_HELP_STRING([--with-devkit], diff --git a/make/autoconf/flags-cflags.m4 b/make/autoconf/flags-cflags.m4 --- a/make/autoconf/flags-cflags.m4 +++ b/make/autoconf/flags-cflags.m4 @@ -662,7 +662,9 @@ # toolchain dependend, per-cpu if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then - if test "x$FLAGS_CPU" = xx86_64; then + if test "x$FLAGS_CPU" = xaarch64; then + $1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_ARM64_ -Darm64" + elif test "x$FLAGS_CPU" = xx86_64; then $1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_AMD64_ -Damd64" else $1_DEFINES_CPU_JDK="${$1_DEFINES_CPU_JDK} -D_X86_ -Dx86" diff --git a/make/autoconf/flags-ldflags.m4 b/make/autoconf/flags-ldflags.m4 --- a/make/autoconf/flags-ldflags.m4 +++ b/make/autoconf/flags-ldflags.m4 @@ -165,14 +165,13 @@ fi elif test "x$TOOLCHAIN_TYPE" = xmicrosoft; then + if test "x${OPENJDK_$1_CPU_BITS}" = "x32"; then + $1_CPU_EXECUTABLE_LDFLAGS="-stack:327680" + elif test "x${OPENJDK_$1_CPU_BITS}" = "x64"; then + $1_CPU_EXECUTABLE_LDFLAGS="-stack:1048576" + fi if test "x${OPENJDK_$1_CPU}" = "xx86"; then $1_CPU_LDFLAGS="-safeseh" - # NOTE: Old build added -machine. Probably not needed. - $1_CPU_LDFLAGS_JVM_ONLY="-machine:I386" - $1_CPU_EXECUTABLE_LDFLAGS="-stack:327680" - else - $1_CPU_LDFLAGS_JVM_ONLY="-machine:AMD64" - $1_CPU_EXECUTABLE_LDFLAGS="-stack:1048576" fi fi diff --git a/make/autoconf/jvm-features.m4 b/make/autoconf/jvm-features.m4 --- a/make/autoconf/jvm-features.m4 +++ b/make/autoconf/jvm-features.m4 @@ -237,8 +237,9 @@ JVM_FEATURES_CHECK_AVAILABILITY(aot, [ AC_MSG_CHECKING([if platform is supported by AOT]) # AOT is only available where JVMCI is available since it requires JVMCI. - if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || \ - test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then + if test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then + AC_MSG_RESULT([yes]) + elif test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64"; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) @@ -303,8 +304,9 @@ JVM_FEATURES_CHECK_AVAILABILITY(graal, [ AC_MSG_CHECKING([if platform is supported by Graal]) # Graal is only available where JVMCI is available since it requires JVMCI. - if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || \ - test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then + if test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then + AC_MSG_RESULT([yes]) + elif test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64"; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) @@ -336,8 +338,9 @@ [ JVM_FEATURES_CHECK_AVAILABILITY(jvmci, [ AC_MSG_CHECKING([if platform is supported by JVMCI]) - if test "x$OPENJDK_TARGET_CPU" = "xx86_64" || \ - test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then + if test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then + AC_MSG_RESULT([yes]) + elif test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64"; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) @@ -353,8 +356,9 @@ [ JVM_FEATURES_CHECK_AVAILABILITY(shenandoahgc, [ AC_MSG_CHECKING([if platform is supported by Shenandoah]) - if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86" || \ - test "x$OPENJDK_TARGET_CPU" = "xaarch64" ; then + if test "x$OPENJDK_TARGET_CPU_ARCH" = "xx86"; then + AC_MSG_RESULT([yes]) + elif test "x$OPENJDK_TARGET_OS-$OPENJDK_TARGET_CPU" = "xlinux-aarch64"; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no, $OPENJDK_TARGET_CPU]) diff --git a/make/autoconf/toolchain.m4 b/make/autoconf/toolchain.m4 --- a/make/autoconf/toolchain.m4 +++ b/make/autoconf/toolchain.m4 @@ -872,14 +872,18 @@ . $CONFIGURESUPPORT_OUTPUTDIR/build-devkit.info # This potentially sets the following: # A descriptive name of the devkit - BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_NAME]) + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_NAME]) # Corresponds to --with-extra-path - BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_EXTRA_PATH]) + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_EXTRA_PATH]) # Corresponds to --with-toolchain-path - BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_TOOLCHAIN_PATH]) + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_TOOLCHAIN_PATH]) # Corresponds to --with-sysroot - BASIC_EVAL_DEVKIT_VARIABLE([BUILD_DEVKIT_SYSROOT]) - # Skip the Window specific parts + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_SYSROOT]) + + if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_VS_INCLUDE]) + BASIC_EVAL_BUILD_DEVKIT_VARIABLE([BUILD_DEVKIT_VS_LIB]) + fi fi AC_MSG_CHECKING([for build platform devkit]) @@ -889,13 +893,22 @@ AC_MSG_RESULT([$BUILD_DEVKIT_ROOT]) fi - BUILD_SYSROOT="$BUILD_DEVKIT_SYSROOT" + UTIL_PREPEND_TO_PATH([PATH],$BUILD_DEVKIT_EXTRA_PATH) - # Fallback default of just /bin if DEVKIT_PATH is not defined + # Fallback default of just /bin if DEVKIT_PATH is not defined if test "x$BUILD_DEVKIT_TOOLCHAIN_PATH" = x; then BUILD_DEVKIT_TOOLCHAIN_PATH="$BUILD_DEVKIT_ROOT/bin" fi - PATH="$BUILD_DEVKIT_TOOLCHAIN_PATH:$BUILD_DEVKIT_EXTRA_PATH" + UTIL_PREPEND_TO_PATH([PATH],$BUILD_DEVKIT_TOOLCHAIN_PATH) + + BUILD_SYSROOT="$BUILD_DEVKIT_SYSROOT" + + if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then + BUILD_VS_INCLUDE="$BUILD_DEVKIT_VS_INCLUDE" + BUILD_VS_LIB="$BUILD_DEVKIT_VS_LIB" + + TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS([BUILD_]) + fi fi fi @@ -921,9 +934,37 @@ UTIL_FIXUP_EXECUTABLE(BUILD_STRIP) # Assume the C compiler is the assembler BUILD_AS="$BUILD_CC -c" - # Just like for the target compiler, use the compiler as linker - BUILD_LD="$BUILD_CC" - BUILD_LDCXX="$BUILD_CXX" + if test "x$TOOLCHAIN_TYPE" = xmicrosoft; then + # In the Microsoft toolchain we have a separate LD command "link". + # Make sure we reject /usr/bin/link (as determined in CYGWIN_LINK), which is + # a cygwin program for something completely different. + AC_CHECK_PROG([BUILD_LD], [link$EXE_SUFFIX],[link$EXE_SUFFIX],,, [$CYGWIN_LINK]) + UTIL_FIXUP_EXECUTABLE(BUILD_LD) + # Verify that we indeed succeeded with this trick. + AC_MSG_CHECKING([if the found link.exe is actually the Visual Studio linker]) + + # Reset PATH since it can contain a mix of WSL/linux paths and Windows paths from VS, + # which, in combination with WSLENV, will make the WSL layer complain + old_path="$PATH" + PATH= + + "$BUILD_LD" --version > /dev/null + + if test $? -eq 0 ; then + AC_MSG_RESULT([no]) + AC_MSG_ERROR([This is the Cygwin link tool. Please check your PATH and rerun configure.]) + else + AC_MSG_RESULT([yes]) + fi + + PATH="$old_path" + + BUILD_LDCXX="$BUILD_LD" + else + # Just like for the target compiler, use the compiler as linker + BUILD_LD="$BUILD_CC" + BUILD_LDCXX="$BUILD_CXX" + fi PATH="$OLDPATH" @@ -974,6 +1015,10 @@ if test "x$COMPILER_CPU_TEST" != "xx64"; then AC_MSG_ERROR([Target CPU mismatch. We are building for $OPENJDK_TARGET_CPU but CL is for "$COMPILER_CPU_TEST"; expected "x64".]) fi + elif test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then + if test "x$COMPILER_CPU_TEST" != "xARM64"; then + AC_MSG_ERROR([Target CPU mismatch. We are building for $OPENJDK_TARGET_CPU but CL is for "$COMPILER_CPU_TEST"; expected "arm64".]) + fi fi fi diff --git a/make/autoconf/toolchain_windows.m4 b/make/autoconf/toolchain_windows.m4 --- a/make/autoconf/toolchain_windows.m4 +++ b/make/autoconf/toolchain_windows.m4 @@ -79,11 +79,15 @@ if test -d "$VS_BASE"; then AC_MSG_NOTICE([Found Visual Studio installation at $VS_BASE using $METHOD]) - if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then + if test "x$OPENJDK_TARGET_CPU" = xx86; then VCVARSFILES="vc/bin/vcvars32.bat vc/auxiliary/build/vcvars32.bat" - else + elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then VCVARSFILES="vc/bin/amd64/vcvars64.bat vc/bin/x86_amd64/vcvarsx86_amd64.bat \ VC/Auxiliary/Build/vcvarsx86_amd64.bat VC/Auxiliary/Build/vcvars64.bat" + elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then + # for host x86-64, target aarch64 + VCVARSFILES="vc/auxiliary/build/vcvarsamd64_arm64.bat \ + vc/auxiliary/build/vcvarsx86_arm64.bat" fi for VCVARSFILE in $VCVARSFILES; do @@ -123,10 +127,12 @@ elif test -f "$WIN_SDK_BASE/Bin/SetEnv.Cmd"; then AC_MSG_NOTICE([Found Windows SDK installation at $WIN_SDK_BASE using $METHOD]) VS_ENV_CMD="$WIN_SDK_BASE/Bin/SetEnv.Cmd" - if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then + if test "x$OPENJDK_TARGET_CPU" = xx86; then VS_ENV_ARGS="/x86" - else + elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then VS_ENV_ARGS="/x64" + elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then + VS_ENV_ARGS="/arm64" fi # PLATFORM_TOOLSET is used during the compilation of the freetype sources (see # 'LIB_BUILD_FREETYPE' in libraries.m4) and must be 'Windows7.1SDK' for Windows7.1SDK @@ -520,41 +526,7 @@ AC_SUBST(VS_INCLUDE) AC_SUBST(VS_LIB) - # Convert VS_INCLUDE into SYSROOT_CFLAGS - OLDIFS="$IFS" - IFS=";" - for i in $VS_INCLUDE; do - ipath=$i - # Only process non-empty elements - if test "x$ipath" != x; then - IFS="$OLDIFS" - # Check that directory exists before calling fixup_path - testpath=$ipath - UTIL_REWRITE_AS_UNIX_PATH([testpath]) - if test -d "$testpath"; then - UTIL_FIXUP_PATH([ipath]) - SYSROOT_CFLAGS="$SYSROOT_CFLAGS -I$ipath" - fi - IFS=";" - fi - done - # Convert VS_LIB into SYSROOT_LDFLAGS - for i in $VS_LIB; do - libpath=$i - # Only process non-empty elements - if test "x$libpath" != x; then - IFS="$OLDIFS" - # Check that directory exists before calling fixup_path - testpath=$libpath - UTIL_REWRITE_AS_UNIX_PATH([testpath]) - if test -d "$testpath"; then - UTIL_FIXUP_PATH([libpath]) - SYSROOT_LDFLAGS="$SYSROOT_LDFLAGS -libpath:$libpath" - fi - IFS=";" - fi - done - IFS="$OLDIFS" + TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS AC_SUBST(VS_PATH_WINDOWS) fi @@ -593,10 +565,15 @@ CORRECT_MSVCR_ARCH="PE32+ executable" fi else - if test "x$OPENJDK_TARGET_CPU_BITS" = x32; then + if test "x$OPENJDK_TARGET_CPU" = xx86; then CORRECT_MSVCR_ARCH=386 - else + elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then CORRECT_MSVCR_ARCH=x86-64 + elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then + # The cygwin 'file' command only returns "PE32+ executable (DLL) (console), for MS Windows", + # without specifying which architecture it is for specifically. This has been fixed upstream. + # https://github.com/file/file/commit/b849b1af098ddd530094bf779b58431395db2e10#diff-ff2eced09e6860de75057dd731d092aeR142 + CORRECT_MSVCR_ARCH="PE32+ executable" fi fi if $ECHO "$MSVC_DLL_FILETYPE" | $GREP "$CORRECT_MSVCR_ARCH" 2>&1 > /dev/null; then @@ -616,26 +593,26 @@ DLL_NAME="$1" MSVC_DLL= + if test "x$OPENJDK_TARGET_CPU" = xx86; then + vs_target_cpu=x86 + elif test "x$OPENJDK_TARGET_CPU" = xx86_64; then + vs_target_cpu=x64 + elif test "x$OPENJDK_TARGET_CPU" = xaarch64; then + vs_target_cpu=arm64 + fi + if test "x$MSVC_DLL" = x; then if test "x$VCINSTALLDIR" != x; then CYGWIN_VC_INSTALL_DIR="$VCINSTALLDIR" UTIL_FIXUP_PATH(CYGWIN_VC_INSTALL_DIR) if test "$VS_VERSION" -lt 2017; then # Probe: Using well-known location from Visual Studio 12.0 and older - if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then - POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME" - else - POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME" - fi + POSSIBLE_MSVC_DLL="$CYGWIN_VC_INSTALL_DIR/redist/$vs_target_cpu/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME" else CYGWIN_VC_TOOLS_REDIST_DIR="$VCToolsRedistDir" UTIL_FIXUP_PATH(CYGWIN_VC_TOOLS_REDIST_DIR) # Probe: Using well-known location from VS 2017 and VS 2019 - if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then - POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/x64/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" - else - POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/x86/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" - fi + POSSIBLE_MSVC_DLL="`ls $CYGWIN_VC_TOOLS_REDIST_DIR/$vs_target_cpu/Microsoft.VC${VS_VERSION_INTERNAL}.CRT/$DLL_NAME`" fi # In case any of the above finds more than one file, loop over them. for possible_msvc_dll in $POSSIBLE_MSVC_DLL; do @@ -667,13 +644,8 @@ if test "x$VS100COMNTOOLS" != x; then CYGWIN_VS_TOOLS_DIR="$VS100COMNTOOLS/.." UTIL_REWRITE_AS_UNIX_PATH(CYGWIN_VS_TOOLS_DIR) - if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then - POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \ - | $GREP -i /x64/ | $HEAD --lines 1` - else - POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \ - | $GREP -i /x86/ | $HEAD --lines 1` - fi + POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VS_TOOLS_DIR" -name $DLL_NAME \ + | $GREP -i /$vs_target_cpu/ | $HEAD --lines 1` TOOLCHAIN_CHECK_POSSIBLE_MSVC_DLL([$DLL_NAME], [$POSSIBLE_MSVC_DLL], [search of VS100COMNTOOLS]) fi @@ -683,17 +655,17 @@ # Probe: Search wildly in the VCINSTALLDIR. We've probably lost by now. # (This was the original behaviour; kept since it might turn something up) if test "x$CYGWIN_VC_INSTALL_DIR" != x; then - if test "x$OPENJDK_TARGET_CPU_BITS" = x64; then + if test "x$OPENJDK_TARGET_CPU" = xx86; then POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \ - | $GREP x64 | $HEAD --lines 1` - else - POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \ - | $GREP x86 | $GREP -v ia64 | $GREP -v x64 | $HEAD --lines 1` + | $GREP x86 | $GREP -v ia64 | $GREP -v x64 | $GREP -v arm64 | $HEAD --lines 1` if test "x$POSSIBLE_MSVC_DLL" = x; then # We're grasping at straws now... POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \ | $HEAD --lines 1` fi + else + POSSIBLE_MSVC_DLL=`$FIND "$CYGWIN_VC_INSTALL_DIR" -name $DLL_NAME \ + | $GREP $vs_target_cpu | $HEAD --lines 1` fi TOOLCHAIN_CHECK_POSSIBLE_MSVC_DLL([$DLL_NAME], [$POSSIBLE_MSVC_DLL], @@ -757,9 +729,9 @@ fi AC_ARG_WITH(vcruntime-1-dll, [AS_HELP_STRING([--with-vcruntime-1-dll], - [path to microsoft C++ runtime dll (vcruntime*_1.dll) (Windows only) @<:@probed@:>@])]) + [path to microsoft C++ runtime dll (vcruntime*_1.dll) (Windows 64-bits only) @<:@probed@:>@])]) - if test "x$VCRUNTIME_1_NAME" != "x"; then + if test "x$VCRUNTIME_1_NAME" != "x" -a "x$OPENJDK_TARGET_CPU_BITS" = x64; then if test "x$with_vcruntime_1_dll" != x; then # If given explicitly by user, do not probe. If not present, fail directly. TOOLCHAIN_CHECK_POSSIBLE_MSVC_DLL($VCRUNTIME_1_NAME, [$with_vcruntime_1_dll], @@ -801,9 +773,12 @@ else CYGWIN_WINDOWSSDKDIR="${WINDOWSSDKDIR}" UTIL_FIXUP_PATH([CYGWIN_WINDOWSSDKDIR]) - dll_subdir=$OPENJDK_TARGET_CPU - if test "x$dll_subdir" = "xx86_64"; then + if test "x$OPENJDK_TARGET_CPU" = "xaarch64"; then + dll_subdir="arm64" + elif test "x$OPENJDK_TARGET_CPU" = "xx86_64"; then dll_subdir="x64" + elif test "x$OPENJDK_TARGET_CPU" = "xx86"; then + dll_subdir="x86" fi UCRT_DLL_DIR="$CYGWIN_WINDOWSSDKDIR/Redist/ucrt/DLLs/$dll_subdir" if test -z "$(ls -d "$UCRT_DLL_DIR/"*.dll 2> /dev/null)"; then @@ -826,3 +801,49 @@ fi AC_SUBST(UCRT_DLL_DIR) ]) + +# Setup the sysroot flags and add them to global CFLAGS and LDFLAGS so +# that configure can use them while detecting compilers. +# TOOLCHAIN_TYPE is available here. +# Param 1 - Optional prefix to all variables. (e.g BUILD_) +AC_DEFUN([TOOLCHAIN_SETUP_VISUAL_STUDIO_SYSROOT_FLAGS], +[ + OLDIFS="$IFS" + IFS=";" + # Convert $1VS_INCLUDE into $1SYSROOT_CFLAGS + for i in [$]$1VS_INCLUDE; do + ipath=$i + # Only process non-empty elements + if test "x$ipath" != x; then + IFS="$OLDIFS" + # Check that directory exists before calling fixup_path + testpath=$ipath + UTIL_REWRITE_AS_UNIX_PATH([testpath]) + if test -d "$testpath"; then + UTIL_FIXUP_PATH([ipath]) + $1SYSROOT_CFLAGS="[$]$1SYSROOT_CFLAGS -I$ipath" + fi + IFS=";" + fi + done + # Convert $1VS_LIB into $1SYSROOT_LDFLAGS + for i in [$]$1VS_LIB; do + libpath=$i + # Only process non-empty elements + if test "x$libpath" != x; then + IFS="$OLDIFS" + # Check that directory exists before calling fixup_path + testpath=$libpath + UTIL_REWRITE_AS_UNIX_PATH([testpath]) + if test -d "$testpath"; then + UTIL_FIXUP_PATH([libpath]) + $1SYSROOT_LDFLAGS="[$]$1SYSROOT_LDFLAGS -libpath:$libpath" + fi + IFS=";" + fi + done + IFS="$OLDIFS" + + AC_SUBST($1SYSROOT_CFLAGS) + AC_SUBST($1SYSROOT_LDFLAGS) +]) diff --git a/make/devkit/createWindowsDevkit2017.sh b/make/devkit/createWindowsDevkit2017.sh --- a/make/devkit/createWindowsDevkit2017.sh +++ b/make/devkit/createWindowsDevkit2017.sh @@ -113,19 +113,23 @@ echo "Copying VC..." rm -rf $DEVKIT_ROOT/VC mkdir -p $DEVKIT_ROOT/VC/bin +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/arm64" $DEVKIT_ROOT/VC/bin/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/x64" $DEVKIT_ROOT/VC/bin/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx86/x86" $DEVKIT_ROOT/VC/bin/ mkdir -p $DEVKIT_ROOT/VC/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/arm64" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x64" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x86" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/include" $DEVKIT_ROOT/VC/ mkdir -p $DEVKIT_ROOT/VC/atlmfc/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/arm64" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x64" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x86" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/include" $DEVKIT_ROOT/VC/atlmfc/ mkdir -p $DEVKIT_ROOT/VC/Auxiliary cp -r "$VS_INSTALL_DIR/VC/Auxiliary/Build" $DEVKIT_ROOT/VC/Auxiliary/ mkdir -p $DEVKIT_ROOT/VC/redist +cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/arm64" $DEVKIT_ROOT/VC/redist/ cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x64" $DEVKIT_ROOT/VC/redist/ cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x86" $DEVKIT_ROOT/VC/redist/ @@ -134,7 +138,9 @@ cp $DEVKIT_ROOT/VC/redist/x86/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x86 cp $DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x86 cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64 -cp $DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x64 +cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64 +cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/arm64 +cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/arm64 ################################################################################ # Copy SDK files @@ -152,8 +158,10 @@ cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x64" $DEVKIT_ROOT/$SDK_VERSION/bin/ cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x86" $DEVKIT_ROOT/$SDK_VERSION/bin/ mkdir -p $DEVKIT_ROOT/$SDK_VERSION/lib +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ mkdir -p $DEVKIT_ROOT/$SDK_VERSION/Redist @@ -188,6 +196,13 @@ echo-info "DEVKIT_MSVCP_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL\"" echo-info "DEVKIT_UCRT_DLL_DIR_x86_64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x64\"" echo-info "" +echo-info "DEVKIT_TOOLCHAIN_PATH_aarch64=\"\$DEVKIT_ROOT/VC/bin/arm64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\"" +echo-info "DEVKIT_VS_INCLUDE_aarch64=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\"" +echo-info "DEVKIT_VS_LIB_aarch64=\"\$DEVKIT_ROOT/VC/lib/arm64;\$DEVKIT_ROOT/VC/atlmfc/lib/arm64;\$DEVKIT_ROOT/$SDK_VERSION/lib/arm64\"" +echo-info "DEVKIT_MSVCR_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCR_DLL\"" +echo-info "DEVKIT_MSVCP_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL\"" +echo-info "DEVKIT_UCRT_DLL_DIR_aarch64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/arm64\"" +echo-info "" echo-info "DEVKIT_TOOLS_VERSION=\"$TOOLS_VERSION\"" echo-info "DEVKIT_REDIST_VERSION=\"$REDIST_VERSION\"" echo-info "DEVKIT_SDK_VERSION=\"$SDK_FULL_VERSION\"" diff --git a/make/devkit/createWindowsDevkit2019.sh b/make/devkit/createWindowsDevkit2019.sh --- a/make/devkit/createWindowsDevkit2019.sh +++ b/make/devkit/createWindowsDevkit2019.sh @@ -117,19 +117,23 @@ echo "Copying VC..." rm -rf $DEVKIT_ROOT/VC mkdir -p $DEVKIT_ROOT/VC/bin +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/arm64" $DEVKIT_ROOT/VC/bin/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx64/x64" $DEVKIT_ROOT/VC/bin/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/bin/Hostx86/x86" $DEVKIT_ROOT/VC/bin/ mkdir -p $DEVKIT_ROOT/VC/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/arm64" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x64" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/lib/x86" $DEVKIT_ROOT/VC/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/include" $DEVKIT_ROOT/VC/ mkdir -p $DEVKIT_ROOT/VC/atlmfc/lib +cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/arm64" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x64" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/lib/x86" $DEVKIT_ROOT/VC/atlmfc/lib/ cp -r "$VS_INSTALL_DIR/${VC_SUBDIR}/atlmfc/include" $DEVKIT_ROOT/VC/atlmfc/ mkdir -p $DEVKIT_ROOT/VC/Auxiliary cp -r "$VS_INSTALL_DIR/VC/Auxiliary/Build" $DEVKIT_ROOT/VC/Auxiliary/ mkdir -p $DEVKIT_ROOT/VC/redist +cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/arm64" $DEVKIT_ROOT/VC/redist/ cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x64" $DEVKIT_ROOT/VC/redist/ cp -r "$VS_INSTALL_DIR/$REDIST_SUBDIR/x86" $DEVKIT_ROOT/VC/redist/ @@ -139,6 +143,8 @@ cp $DEVKIT_ROOT/VC/redist/x86/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x86 cp $DEVKIT_ROOT/VC/redist/x64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/x64 cp $DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/x64 +cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCR_DLL $DEVKIT_ROOT/VC/bin/arm64 +cp $DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL $DEVKIT_ROOT/VC/bin/arm64 ################################################################################ # Copy SDK files @@ -156,8 +162,10 @@ cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x64" $DEVKIT_ROOT/$SDK_VERSION/bin/ cp -r "$SDK_INSTALL_DIR/bin/$SDK_FULL_VERSION/x86" $DEVKIT_ROOT/$SDK_VERSION/bin/ mkdir -p $DEVKIT_ROOT/$SDK_VERSION/lib +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/um/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ +cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/arm64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x64" $DEVKIT_ROOT/$SDK_VERSION/lib/ cp -r "$SDK_INSTALL_DIR/lib/$SDK_FULL_VERSION/ucrt/x86" $DEVKIT_ROOT/$SDK_VERSION/lib/ mkdir -p $DEVKIT_ROOT/$SDK_VERSION/Redist @@ -193,6 +201,14 @@ echo-info "DEVKIT_MSVCP_DLL_x86_64=\"\$DEVKIT_ROOT/VC/redist/x64/$MSVCP_DLL\"" echo-info "DEVKIT_UCRT_DLL_DIR_x86_64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/x64\"" echo-info "" +echo-info "DEVKIT_TOOLCHAIN_PATH_aarch64=\"\$DEVKIT_ROOT/VC/bin/arm64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x64:\$DEVKIT_ROOT/$SDK_VERSION/bin/x86\"" +echo-info "DEVKIT_VS_INCLUDE_aarch64=\"\$DEVKIT_ROOT/VC/include;\$DEVKIT_ROOT/VC/atlmfc/include;\$DEVKIT_ROOT/$SDK_VERSION/include/shared;\$DEVKIT_ROOT/$SDK_VERSION/include/ucrt;\$DEVKIT_ROOT/$SDK_VERSION/include/um;\$DEVKIT_ROOT/$SDK_VERSION/include/winrt\"" +echo-info "DEVKIT_VS_LIB_aarch64=\"\$DEVKIT_ROOT/VC/lib/arm64;\$DEVKIT_ROOT/VC/atlmfc/lib/arm64;\$DEVKIT_ROOT/$SDK_VERSION/lib/arm64\"" +echo-info "DEVKIT_MSVCR_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCR_DLL\"" +echo-info "DEVKIT_VCRUNTIME_1_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$VCRUNTIME_1_DLL\"" +echo-info "DEVKIT_MSVCP_DLL_aarch64=\"\$DEVKIT_ROOT/VC/redist/arm64/$MSVCP_DLL\"" +echo-info "DEVKIT_UCRT_DLL_DIR_aarch64=\"\$DEVKIT_ROOT/10/Redist/ucrt/DLLs/arm64\"" +echo-info "" echo-info "DEVKIT_TOOLS_VERSION=\"$TOOLS_VERSION\"" echo-info "DEVKIT_REDIST_VERSION=\"$REDIST_VERSION\"" echo-info "DEVKIT_SDK_VERSION=\"$SDK_FULL_VERSION\"" diff --git a/make/hotspot/gensrc/GensrcAdlc.gmk b/make/hotspot/gensrc/GensrcAdlc.gmk --- a/make/hotspot/gensrc/GensrcAdlc.gmk +++ b/make/hotspot/gensrc/GensrcAdlc.gmk @@ -88,6 +88,10 @@ ADLCFLAGS += -DAIX=1 else ifeq ($(call isTargetOs, macosx), true) ADLCFLAGS += -D_ALLBSD_SOURCE=1 -D_GNU_SOURCE=1 + else ifeq ($(call isTargetOs, windows), true) + ifeq ($(call isTargetCpuBits, 64), true) + ADLCFLAGS += -D_WIN64=1 + endif endif ifeq ($(call isTargetOs, windows), false) diff --git a/make/modules/java.base/gensrc/GensrcMisc.gmk b/make/modules/java.base/gensrc/GensrcMisc.gmk --- a/make/modules/java.base/gensrc/GensrcMisc.gmk +++ b/make/modules/java.base/gensrc/GensrcMisc.gmk @@ -60,6 +60,12 @@ CPP_FLAGS += -x c else ifeq ($(TOOLCHAIN_TYPE), microsoft) CPP_FLAGS += -nologo + + ifeq ($(OPENJDK_TARGET_CPU),aarch64) + # cl.exe does only recognize few file extensions as valid (ex: .c, .h, .cpp), so + # make sure *.java.template files are recognized as valid input files + CPP_FILEPREFIX = -Tc + endif endif # Generate a java source file from a template through the C preprocessor for the @@ -73,7 +79,7 @@ $(call MakeDir, $(@D)) $(call ExecuteWithLog, $(SUPPORT_OUTPUTDIR)/gensrc/java.base/_$(@F), \ ( $(NAWK) '/@@END_COPYRIGHT@@/{exit}1' $< && \ - $(CPP) $(CPP_FLAGS) $(SYSROOT_CFLAGS) $(CFLAGS_JDKLIB) $< \ + $(CPP) $(CPP_FLAGS) $(SYSROOT_CFLAGS) $(CFLAGS_JDKLIB) $(CPP_FILEPREFIX) $< \ 2> >($(GREP) -v '^$(&2) \ | $(NAWK) '/@@START_HERE@@/,0' \ | $(SED) -e 's/@@START_HERE@@/\/\/ AUTOMATICALLY GENERATED FILE - DO NOT EDIT/' \ # HG changeset patch # User burban # Date 1596225102 14400 # Fri Jul 31 15:51:42 2020 -0400 # Node ID 068f53660ed97f21af6a95f32ba14a41c351eb5b # Parent 19513275382c33aab8345dfcaef9dac8ca35274b 8248656: Add Windows AArch64 platform support code Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/aarch64.ad b/src/hotspot/cpu/aarch64/aarch64.ad --- a/src/hotspot/cpu/aarch64/aarch64.ad +++ b/src/hotspot/cpu/aarch64/aarch64.ad @@ -5900,7 +5900,7 @@ attributes %{ // ARM instructions are of fixed length fixed_size_instructions; // Fixed size instructions TODO does - max_instructions_per_bundle = 2; // A53 = 2, A57 = 4 + max_instructions_per_bundle = 4; // A53 = 2, A57 = 4 // ARM instructions come in 32-bit word units instruction_unit_size = 4; // An instruction is 4 bytes long instruction_fetch_unit_size = 64; // The processor fetches one line diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp --- a/src/hotspot/cpu/aarch64/assembler_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.cpp @@ -1784,3 +1784,7 @@ ival = fp_immediate_for_encoding(value, 0); return val; } + +address Assembler::locate_next_instruction(address inst) { + return inst + Assembler::instruction_size; +} diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -653,6 +653,8 @@ return Address(Post(base, idx)); } + static address locate_next_instruction(address inst); + Instruction_aarch64* current; void set_current(Instruction_aarch64* i) { current = i; } diff --git a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp --- a/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/c1_FpuStackSim_aarch64.cpp @@ -28,3 +28,4 @@ //-------------------------------------------------------- // No FPU stack on AARCH64 +#include "precompiled.hpp" diff --git a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad --- a/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad +++ b/src/hotspot/cpu/aarch64/gc/shenandoah/shenandoah_aarch64.ad @@ -23,6 +23,7 @@ // source_hpp %{ +#include "gc/shenandoah/shenandoahBarrierSet.hpp" #include "gc/shenandoah/shenandoahBarrierSetAssembler.hpp" %} diff --git a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp --- a/src/hotspot/cpu/aarch64/immediate_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/immediate_aarch64.cpp @@ -24,6 +24,9 @@ #include #include + +#include "precompiled.hpp" +#include "utilities/globalDefinitions.hpp" #include "immediate_aarch64.hpp" // there are at most 2^13 possible logical immediate encodings diff --git a/src/hotspot/os/windows/os_windows.cpp b/src/hotspot/os/windows/os_windows.cpp --- a/src/hotspot/os/windows/os_windows.cpp +++ b/src/hotspot/os/windows/os_windows.cpp @@ -32,6 +32,7 @@ #include "classfile/vmSymbols.hpp" #include "code/codeCache.hpp" #include "code/icBuffer.hpp" +#include "code/nativeInst.hpp" #include "code/vtableStubs.hpp" #include "compiler/compileBroker.hpp" #include "compiler/disassembler.hpp" @@ -118,7 +119,9 @@ static FILETIME process_user_time; static FILETIME process_kernel_time; -#ifdef _M_AMD64 +#if defined(_M_ARM64) + #define __CPU__ aarch64 +#elif defined(_M_AMD64) #define __CPU__ amd64 #else #define __CPU__ i486 @@ -1427,15 +1430,18 @@ static const arch_t arch_array[] = { {IMAGE_FILE_MACHINE_I386, (char*)"IA 32"}, - {IMAGE_FILE_MACHINE_AMD64, (char*)"AMD 64"} + {IMAGE_FILE_MACHINE_AMD64, (char*)"AMD 64"}, + {IMAGE_FILE_MACHINE_ARM64, (char*)"ARM 64"} }; -#if (defined _M_AMD64) +#if (defined _M_ARM64) + static const uint16_t running_arch = IMAGE_FILE_MACHINE_ARM64; +#elif (defined _M_AMD64) static const uint16_t running_arch = IMAGE_FILE_MACHINE_AMD64; #elif (defined _M_IX86) static const uint16_t running_arch = IMAGE_FILE_MACHINE_I386; #else #error Method os::dll_load requires that one of following \ - is defined :_M_AMD64 or _M_IX86 + is defined :_M_AMD64 or _M_IX86 or _M_ARM64 #endif @@ -1732,7 +1738,8 @@ SYSTEM_INFO si; ZeroMemory(&si, sizeof(SYSTEM_INFO)); GetNativeSystemInfo(&si); - if (si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_AMD64) { + if ((si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_AMD64) || + (si.wProcessorArchitecture == PROCESSOR_ARCHITECTURE_ARM64)) { st->print(" , 64 bit"); } @@ -2140,7 +2147,14 @@ address handler) { JavaThread* thread = (JavaThread*) Thread::current_or_null(); // Save pc in thread -#ifdef _M_AMD64 +#if defined(_M_ARM64) + // Do not blow up if no thread info available. + if (thread) { + thread->set_saved_exception_pc((address)(DWORD_PTR)exceptionInfo->ContextRecord->Pc); + } + // Set pc to handler + exceptionInfo->ContextRecord->Pc = (DWORD64)handler; +#elif defined(_M_AMD64) // Do not blow up if no thread info available. if (thread) { thread->set_saved_exception_pc((address)(DWORD_PTR)exceptionInfo->ContextRecord->Rip); @@ -2238,7 +2252,17 @@ LONG Handle_IDiv_Exception(struct _EXCEPTION_POINTERS* exceptionInfo) { // handle exception caused by idiv; should only happen for -MinInt/-1 // (division by zero is handled explicitly) -#ifdef _M_AMD64 +#if defined(_M_ARM64) + PCONTEXT ctx = exceptionInfo->ContextRecord; + address pc = (address)ctx->Sp; + assert(pc[0] == 0x83, "not an sdiv opcode"); //Fixme did i get the right opcode? + assert(ctx->X4 == min_jint, "unexpected idiv exception"); + // set correct result values and continue after idiv instruction + ctx->Pc = (uint64_t)pc + 4; // idiv reg, reg, reg is 4 bytes + ctx->X4 = (uint64_t)min_jint; // result + ctx->X5 = (uint64_t)0; // remainder + // Continue the execution +#elif defined(_M_AMD64) PCONTEXT ctx = exceptionInfo->ContextRecord; address pc = (address)ctx->Rip; assert(pc[0] >= Assembler::REX && pc[0] <= Assembler::REX_WRXB && pc[1] == 0xF7 || pc[0] == 0xF7, "not an idiv opcode"); @@ -2269,6 +2293,7 @@ return EXCEPTION_CONTINUE_EXECUTION; } +#if defined(_M_AMD64) || defined(_M_IX86) //----------------------------------------------------------------------------- LONG WINAPI Handle_FLT_Exception(struct _EXCEPTION_POINTERS* exceptionInfo) { PCONTEXT ctx = exceptionInfo->ContextRecord; @@ -2314,6 +2339,7 @@ return EXCEPTION_CONTINUE_SEARCH; } +#endif static inline void report_error(Thread* t, DWORD exception_code, address addr, void* siginfo, void* context) { @@ -2323,66 +2349,14 @@ // somewhere where we can find it in the minidump. } -bool os::win32::get_frame_at_stack_banging_point(JavaThread* thread, - struct _EXCEPTION_POINTERS* exceptionInfo, address pc, frame* fr) { - PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord; - address addr = (address) exceptionRecord->ExceptionInformation[1]; - if (Interpreter::contains(pc)) { - *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord); - if (!fr->is_first_java_frame()) { - // get_frame_at_stack_banging_point() is only called when we - // have well defined stacks so java_sender() calls do not need - // to assert safe_for_sender() first. - *fr = fr->java_sender(); - } - } else { - // more complex code with compiled code - assert(!Interpreter::contains(pc), "Interpreted methods should have been handled above"); - CodeBlob* cb = CodeCache::find_blob(pc); - if (cb == NULL || !cb->is_nmethod() || cb->is_frame_complete_at(pc)) { - // Not sure where the pc points to, fallback to default - // stack overflow handling - return false; - } else { - *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord); - // in compiled code, the stack banging is performed just after the return pc - // has been pushed on the stack - *fr = frame(fr->sp() + 1, fr->fp(), (address)*(fr->sp())); - if (!fr->is_java_frame()) { - // See java_sender() comment above. - *fr = fr->java_sender(); - } - } - } - assert(fr->is_java_frame(), "Safety check"); - return true; -} - -#if INCLUDE_AOT -LONG WINAPI topLevelVectoredExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) { - PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord; - address addr = (address) exceptionRecord->ExceptionInformation[1]; - address pc = (address) exceptionInfo->ContextRecord->Rip; - - // Handle the case where we get an implicit exception in AOT generated - // code. AOT DLL's loaded are not registered for structured exceptions. - // If the exception occurred in the codeCache or AOT code, pass control - // to our normal exception handler. - CodeBlob* cb = CodeCache::find_blob(pc); - if (cb != NULL) { - return topLevelExceptionFilter(exceptionInfo); - } - - return EXCEPTION_CONTINUE_SEARCH; -} -#endif - //----------------------------------------------------------------------------- LONG WINAPI topLevelExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) { if (InterceptOSException) return EXCEPTION_CONTINUE_SEARCH; PEXCEPTION_RECORD exception_record = exceptionInfo->ExceptionRecord; DWORD exception_code = exception_record->ExceptionCode; -#ifdef _M_AMD64 +#if defined(_M_ARM64) + address pc = (address)exceptionInfo->ContextRecord->Pc; +#elif defined(_M_AMD64) address pc = (address) exceptionInfo->ContextRecord->Rip; #else address pc = (address) exceptionInfo->ContextRecord->Eip; @@ -2472,11 +2446,13 @@ } #endif // _WIN64 +#if defined(_M_AMD64) || defined(_M_IX86) if ((exception_code == EXCEPTION_ACCESS_VIOLATION) && VM_Version::is_cpuinfo_segv_addr(pc)) { // Verify that OS save/restore AVX registers. return Handle_Exception(exceptionInfo, VM_Version::cpuinfo_cont_addr()); } +#endif if (t != NULL && t->is_Java_thread()) { JavaThread* thread = (JavaThread*) t; @@ -2553,6 +2529,27 @@ return EXCEPTION_CONTINUE_SEARCH; } +#ifdef _M_ARM64 + // Unsafe memory access + CompiledMethod* nm = NULL; + JavaThread* thread = (JavaThread*)t; + if (in_java) { + CodeBlob* cb = CodeCache::find_blob_unsafe(pc); + nm = (cb != NULL) ? cb->as_compiled_method_or_null() : NULL; + } + + bool is_unsafe_arraycopy = (in_native || in_java) && UnsafeCopyMemory::contains_pc(pc); + if (is_unsafe_arraycopy || + ((in_vm || in_native) && thread->doing_unsafe_access()) || + (nm != NULL && nm->has_unsafe_access())) { + address next_pc = Assembler::locate_next_instruction(pc); + if (is_unsafe_arraycopy) { + next_pc = UnsafeCopyMemory::page_error_continue_pc(pc); + } + return Handle_Exception(exceptionInfo, SharedRuntime::handle_unsafe_access(thread, next_pc)); + } +#endif + #ifdef _WIN64 // Special care for fast JNI field accessors. // jni_fast_GetField can trap at certain pc's if a GC kicks @@ -2589,6 +2586,19 @@ } } +#ifdef _M_ARM64 + if (in_java && + (exception_code == EXCEPTION_ILLEGAL_INSTRUCTION || + exception_code == EXCEPTION_ILLEGAL_INSTRUCTION_2)) { + if (nativeInstruction_at(pc)->is_sigill_zombie_not_entrant()) { + if (TraceTraps) { + tty->print_cr("trap: zombie_not_entrant"); + } + return Handle_Exception(exceptionInfo, SharedRuntime::get_handle_wrong_method_stub()); + } + } +#endif + if (in_java) { switch (exception_code) { case EXCEPTION_INT_DIVIDE_BY_ZERO: @@ -2599,10 +2609,13 @@ } // switch } + +#if defined(_M_AMD64) || defined(_M_IX86) if ((in_java || in_native) && exception_code != EXCEPTION_UNCAUGHT_CXX_EXCEPTION) { LONG result=Handle_FLT_Exception(exceptionInfo); if (result==EXCEPTION_CONTINUE_EXECUTION) return result; } +#endif } if (exception_code != EXCEPTION_BREAKPOINT) { @@ -3610,7 +3623,12 @@ // Must never look like an address returned by reserve_memory, // even in its subfields (as defined by the CPU immediate fields, // if the CPU splits constants across multiple instructions). +#ifdef _M_ARM64 + // AArch64 has a maximum addressable space of 48-bits + return (char*)((1ull << 48) - 1); +#else return (char*)-1; +#endif } #define MAX_ERROR_COUNT 100 @@ -5591,7 +5609,7 @@ // WINDOWS CONTEXT Flags for THREAD_SAMPLING #if defined(IA32) #define sampling_context_flags (CONTEXT_FULL | CONTEXT_FLOATING_POINT | CONTEXT_EXTENDED_REGISTERS) -#elif defined (AMD64) +#elif defined(AMD64) || defined(_M_ARM64) #define sampling_context_flags (CONTEXT_FULL | CONTEXT_FLOATING_POINT) #endif diff --git a/src/hotspot/os_cpu/windows_aarch64/assembler_windows_aarch64.cpp b/src/hotspot/os_cpu/windows_aarch64/assembler_windows_aarch64.cpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/assembler_windows_aarch64.cpp @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +// nothing required here +#include "precompiled.hpp" diff --git a/src/hotspot/os_cpu/windows_aarch64/atomic_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/atomic_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/atomic_windows_aarch64.hpp @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_ATOMIC_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_ATOMIC_WINDOWS_AARCH64_HPP + +#include +#include "runtime/os.hpp" +#include "runtime/vm_version.hpp" + + +// As per atomic.hpp all read-modify-write operations have to provide two-way +// barriers semantics. The memory_order parameter is ignored - we always provide +// the strongest/most-conservative ordering +// +// For AARCH64 we add explicit barriers in the stubs. + +template +struct Atomic::PlatformAdd { + template + D add_and_fetch(D volatile* dest, I add_value, atomic_memory_order order) const; + + template + D fetch_and_add(D volatile* dest, I add_value, atomic_memory_order order) const { + return add_and_fetch(dest, add_value, order) - add_value; + } +}; + +#define DEFINE_STUB_ADD(ByteSize, StubType, StubName) \ + template<> \ + template \ + inline D Atomic::PlatformAdd::add_and_fetch(D volatile* dest, \ + I add_value, \ + atomic_memory_order order) const { \ + STATIC_ASSERT(ByteSize == sizeof(D)); \ + return PrimitiveConversions::cast( \ + StubName(reinterpret_cast(dest), \ + PrimitiveConversions::cast(add_value))); \ + } + +DEFINE_STUB_ADD(4, long, InterlockedAdd) +DEFINE_STUB_ADD(8, __int64, InterlockedAdd64) + +#undef DEFINE_STUB_ADD + +#define DEFINE_STUB_XCHG(ByteSize, StubType, StubName) \ + template<> \ + template \ + inline T Atomic::PlatformXchg::operator()(T volatile* dest, \ + T exchange_value, \ + atomic_memory_order order) const { \ + STATIC_ASSERT(ByteSize == sizeof(T)); \ + return PrimitiveConversions::cast( \ + StubName(reinterpret_cast(dest), \ + PrimitiveConversions::cast(exchange_value))); \ + } + +DEFINE_STUB_XCHG(4, long, InterlockedExchange) +DEFINE_STUB_XCHG(8, __int64, InterlockedExchange64) + +#undef DEFINE_STUB_XCHG + +#define DEFINE_STUB_CMPXCHG(ByteSize, StubType, StubName) \ + template<> \ + template \ + inline T Atomic::PlatformCmpxchg::operator()(T volatile* dest, \ + T compare_value, \ + T exchange_value, \ + atomic_memory_order order) const { \ + STATIC_ASSERT(ByteSize == sizeof(T)); \ + return PrimitiveConversions::cast( \ + StubName(reinterpret_cast(dest), \ + PrimitiveConversions::cast(exchange_value), \ + PrimitiveConversions::cast(compare_value))); \ + } + +DEFINE_STUB_CMPXCHG(1, char, _InterlockedCompareExchange8) // Use the intrinsic as InterlockedCompareExchange8 does not exist +DEFINE_STUB_CMPXCHG(4, long, InterlockedCompareExchange) +DEFINE_STUB_CMPXCHG(8, __int64, InterlockedCompareExchange64) + +#undef DEFINE_STUB_CMPXCHG + +#endif // OS_CPU_WINDOWS_AARCH64_ATOMIC_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/bytes_windows_aarch64.inline.hpp b/src/hotspot/os_cpu/windows_aarch64/bytes_windows_aarch64.inline.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/bytes_windows_aarch64.inline.hpp @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_BYTES_WINDOWS_AARCH64_INLINE_HPP +#define OS_CPU_WINDOWS_AARCH64_BYTES_WINDOWS_AARCH64_INLINE_HPP + +#include + +// Efficient swapping of data bytes from Java byte +// ordering to native byte ordering and vice versa. +inline u2 Bytes::swap_u2(u2 x) { + return _byteswap_ushort(x); +} + +inline u4 Bytes::swap_u4(u4 x) { + return _byteswap_ulong(x); +} + +inline u8 Bytes::swap_u8(u8 x) { + return _byteswap_uint64(x); +} + +#pragma warning(default: 4035) // Enable warning 4035: no return value + +#endif // OS_CPU_WINDOWS_AARCH64_BYTES_WINDOWS_AARCH64_INLINE_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/copy_windows_aarch64.inline.hpp b/src/hotspot/os_cpu/windows_aarch64/copy_windows_aarch64.inline.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/copy_windows_aarch64.inline.hpp @@ -0,0 +1,158 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_COPY_WINDOWS_AARCH64_INLINE_HPP +#define OS_CPU_WINDOWS_AARCH64_COPY_WINDOWS_AARCH64_INLINE_HPP + +#include + +static void pd_conjoint_words(const HeapWord* from, HeapWord* to, size_t count) { + (void)memmove(to, from, count * HeapWordSize); +} + +static void pd_disjoint_words(const HeapWord* from, HeapWord* to, size_t count) { + switch (count) { + case 8: to[7] = from[7]; + case 7: to[6] = from[6]; + case 6: to[5] = from[5]; + case 5: to[4] = from[4]; + case 4: to[3] = from[3]; + case 3: to[2] = from[2]; + case 2: to[1] = from[1]; + case 1: to[0] = from[0]; + case 0: break; + default: + (void)memcpy(to, from, count * HeapWordSize); + break; + } +} + +static void pd_disjoint_words_atomic(const HeapWord* from, HeapWord* to, size_t count) { + switch (count) { + case 8: to[7] = from[7]; + case 7: to[6] = from[6]; + case 6: to[5] = from[5]; + case 5: to[4] = from[4]; + case 4: to[3] = from[3]; + case 3: to[2] = from[2]; + case 2: to[1] = from[1]; + case 1: to[0] = from[0]; + case 0: break; + default: while (count-- > 0) { + *to++ = *from++; + } + break; + } +} + +static void pd_aligned_conjoint_words(const HeapWord* from, HeapWord* to, size_t count) { + // pd_conjoint_words(from, to, count); + (void)memmove(to, from, count * HeapWordSize); +} + +static void pd_aligned_disjoint_words(const HeapWord* from, HeapWord* to, size_t count) { + pd_disjoint_words(from, to, count); +} + +static void pd_conjoint_bytes(const void* from, void* to, size_t count) { + (void)memmove(to, from, count); +} + +static void pd_conjoint_bytes_atomic(const void* from, void* to, size_t count) { + pd_conjoint_bytes(from, to, count); +} + +static void pd_conjoint_jshorts_atomic(const jshort* from, jshort* to, size_t count) { + if (from > to) { + while (count-- > 0) { + // Copy forwards + *to++ = *from++; + } + } else { + from += count - 1; + to += count - 1; + while (count-- > 0) { + // Copy backwards + *to-- = *from--; + } + } +} + +static void pd_conjoint_jints_atomic(const jint* from, jint* to, size_t count) { + if (from > to) { + while (count-- > 0) { + // Copy forwards + *to++ = *from++; + } + } else { + from += count - 1; + to += count - 1; + while (count-- > 0) { + // Copy backwards + *to-- = *from--; + } + } +} + +static void pd_conjoint_jlongs_atomic(const jlong* from, jlong* to, size_t count) { + pd_conjoint_oops_atomic((const oop*)from, (oop*)to, count); +} + +static void pd_conjoint_oops_atomic(const oop* from, oop* to, size_t count) { + if (from > to) { + while (count-- > 0) { + // Copy forwards + *to++ = *from++; + } + } else { + from += count - 1; + to += count - 1; + while (count-- > 0) { + // Copy backwards + *to-- = *from--; + } + } +} + +static void pd_arrayof_conjoint_bytes(const HeapWord* from, HeapWord* to, size_t count) { + pd_conjoint_bytes_atomic(from, to, count); +} + +static void pd_arrayof_conjoint_jshorts(const HeapWord* from, HeapWord* to, size_t count) { + pd_conjoint_jshorts_atomic((const jshort*)from, (jshort*)to, count); +} + +static void pd_arrayof_conjoint_jints(const HeapWord* from, HeapWord* to, size_t count) { + pd_conjoint_jints_atomic((const jint*)from, (jint*)to, count); +} + +static void pd_arrayof_conjoint_jlongs(const HeapWord* from, HeapWord* to, size_t count) { + pd_conjoint_jlongs_atomic((const jlong*)from, (jlong*)to, count); +} + +static void pd_arrayof_conjoint_oops(const HeapWord* from, HeapWord* to, size_t count) { + pd_conjoint_oops_atomic((const oop*)from, (oop*)to, count); +} + +#endif // OS_CPU_WINDOWS_AARCH64_COPY_WINDOWS_AARCH64_INLINE_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/globals_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/globals_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/globals_windows_aarch64.hpp @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_GLOBALS_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_GLOBALS_WINDOWS_AARCH64_HPP + +// Sets the default values for platform dependent flags used by the runtime system. +// (see globals.hpp) + +define_pd_global(bool, DontYieldALot, false); + +// Default stack size on Windows is determined by the executable (java.exe +// has a default value of 320K/1MB [32bit/64bit]). Depending on Windows version, changing +// ThreadStackSize to non-zero may have significant impact on memory usage. +// See comments in os_windows.cpp. +define_pd_global(intx, ThreadStackSize, 0); // 0 => use system default +define_pd_global(intx, VMThreadStackSize, 0); + +#ifdef ASSERT +define_pd_global(intx, CompilerThreadStackSize, 1024); +#else +define_pd_global(intx, CompilerThreadStackSize, 0); +#endif + +define_pd_global(uintx,JVMInvokeMethodSlack, 8192); + +// Used on 64 bit platforms for UseCompressedOops base address +define_pd_global(uintx,HeapBaseMinAddress, 2*G); +#endif // OS_CPU_WINDOWS_AARCH64_GLOBALS_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/orderAccess_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/orderAccess_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/orderAccess_windows_aarch64.hpp @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_ORDERACCESS_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_ORDERACCESS_WINDOWS_AARCH64_HPP + +// Included in orderAccess.hpp header file. + +#include +#include "vm_version_aarch64.hpp" +#include "runtime/vm_version.hpp" + +// Implementation of class OrderAccess. + +inline void OrderAccess::loadload() { acquire(); } +inline void OrderAccess::storestore() { release(); } +inline void OrderAccess::loadstore() { acquire(); } +inline void OrderAccess::storeload() { fence(); } + +inline void OrderAccess::acquire() { + _ReadBarrier(); + __dmb(_ARM64_BARRIER_ISHLD); +} + +inline void OrderAccess::release() { + _WriteBarrier(); + __dmb(_ARM64_BARRIER_ISHST); +} + +inline void OrderAccess::fence() { + _ReadWriteBarrier(); + __dmb(_ARM64_BARRIER_ISH); +} + +inline void OrderAccess::cross_modify_fence() { } + +#endif // OS_CPU_WINDOWS_AARCH64_ORDERACCESS_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.cpp b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.cpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.cpp @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "jvm.h" +#include "asm/macroAssembler.hpp" +#include "classfile/classLoader.hpp" +#include "classfile/systemDictionary.hpp" +#include "classfile/vmSymbols.hpp" +#include "code/codeCache.hpp" +#include "code/icBuffer.hpp" +#include "code/vtableStubs.hpp" +#include "code/nativeInst.hpp" +#include "interpreter/interpreter.hpp" +#include "memory/allocation.inline.hpp" +#include "prims/jniFastGetField.hpp" +#include "prims/jvm_misc.hpp" +#include "runtime/arguments.hpp" +#include "runtime/frame.inline.hpp" +#include "runtime/interfaceSupport.inline.hpp" +#include "runtime/java.hpp" +#include "runtime/javaCalls.hpp" +#include "runtime/mutexLocker.hpp" +#include "runtime/osThread.hpp" +#include "runtime/sharedRuntime.hpp" +#include "runtime/stubRoutines.hpp" +#include "runtime/thread.inline.hpp" +#include "runtime/timer.hpp" +#include "unwind_windows_aarch64.hpp" +#include "utilities/debug.hpp" +#include "utilities/events.hpp" +#include "utilities/vmError.hpp" + + +// put OS-includes here +# include +# include +# include +# include +# include +# include + +void os::os_exception_wrapper(java_call_t f, JavaValue* value, const methodHandle& method, JavaCallArguments* args, Thread* thread) { + f(value, method, args, thread); +} + +PRAGMA_DISABLE_MSVC_WARNING(4172) +// Returns an estimate of the current stack pointer. Result must be guaranteed +// to point into the calling threads stack, and be no lower than the current +// stack pointer. +address os::current_stack_pointer() { + int dummy; + address sp = (address)&dummy; + return sp; +} + +address os::fetch_frame_from_context(const void* ucVoid, + intptr_t** ret_sp, intptr_t** ret_fp) { + address epc; + CONTEXT* uc = (CONTEXT*)ucVoid; + + if (uc != NULL) { + epc = (address)uc->Pc; + if (ret_sp) *ret_sp = (intptr_t*)uc->Sp; + if (ret_fp) *ret_fp = (intptr_t*)uc->Fp; + } else { + // construct empty ExtendedPC for return value checking + epc = NULL; + if (ret_sp) *ret_sp = (intptr_t *)NULL; + if (ret_fp) *ret_fp = (intptr_t *)NULL; + } + return epc; +} + +frame os::fetch_frame_from_context(const void* ucVoid) { + intptr_t* sp; + intptr_t* fp; + address epc = fetch_frame_from_context(ucVoid, &sp, &fp); + return frame(sp, fp, epc); +} + +bool os::win32::get_frame_at_stack_banging_point(JavaThread* thread, + struct _EXCEPTION_POINTERS* exceptionInfo, address pc, frame* fr) { + PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord; + address addr = (address) exceptionRecord->ExceptionInformation[1]; + if (Interpreter::contains(pc)) { + // interpreter performs stack banging after the fixed frame header has + // been generated while the compilers perform it before. To maintain + // semantic consistency between interpreted and compiled frames, the + // method returns the Java sender of the current frame. + *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord); + if (!fr->is_first_java_frame()) { + assert(fr->safe_for_sender(thread), "Safety check"); + *fr = fr->java_sender(); + } + } else { + // more complex code with compiled code + assert(!Interpreter::contains(pc), "Interpreted methods should have been handled above"); + CodeBlob* cb = CodeCache::find_blob(pc); + if (cb == NULL || !cb->is_nmethod() || cb->is_frame_complete_at(pc)) { + // Not sure where the pc points to, fallback to default + // stack overflow handling + return false; + } else { + // In compiled code, the stack banging is performed before LR + // has been saved in the frame. LR is live, and SP and FP + // belong to the caller. + intptr_t* fp = (intptr_t*)exceptionInfo->ContextRecord->Fp; + intptr_t* sp = (intptr_t*)exceptionInfo->ContextRecord->Sp; + address pc = (address)(exceptionInfo->ContextRecord->Lr + - NativeInstruction::instruction_size); + *fr = frame(sp, fp, pc); + if (!fr->is_java_frame()) { + assert(fr->safe_for_sender(thread), "Safety check"); + assert(!fr->is_first_frame(), "Safety check"); + *fr = fr->java_sender(); + } + } + } + assert(fr->is_java_frame(), "Safety check"); + return true; +} + +// By default, gcc always saves frame pointer rfp on this stack. This +// may get turned off by -fomit-frame-pointer. +frame os::get_sender_for_C_frame(frame* fr) { + return frame(fr->link(), fr->link(), fr->sender_pc()); +} + +frame os::current_frame() { + typedef intptr_t* get_fp_func (); + get_fp_func* func = CAST_TO_FN_PTR(get_fp_func*, + StubRoutines::aarch64::get_previous_fp_entry()); + if (func == NULL) return frame(); + intptr_t* fp = (*func)(); + if (fp == NULL) { + return frame(); + } + + frame myframe((intptr_t*)os::current_stack_pointer(), + (intptr_t*)fp, + CAST_FROM_FN_PTR(address, os::current_frame)); + if (os::is_first_C_frame(&myframe)) { + + // stack is not walkable + return frame(); + } else { + return os::get_sender_for_C_frame(&myframe); + } +} + +//////////////////////////////////////////////////////////////////////////////// +// thread stack + +// Minimum usable stack sizes required to get to user code. Space for +// HotSpot guard pages is added later. + +///////////////////////////////////////////////////////////////////////////// +// helper functions for fatal error handler + +void os::print_context(outputStream *st, const void *context) { + if (context == NULL) return; + + const CONTEXT* uc = (const CONTEXT*)context; + + st->print_cr("Registers:"); + + st->print( "X0 =" INTPTR_FORMAT, uc->X0); + st->print(", X1 =" INTPTR_FORMAT, uc->X1); + st->print(", X2 =" INTPTR_FORMAT, uc->X2); + st->print(", X3 =" INTPTR_FORMAT, uc->X3); + st->cr(); + st->print( "X4 =" INTPTR_FORMAT, uc->X4); + st->print(", X5 =" INTPTR_FORMAT, uc->X5); + st->print(", X6 =" INTPTR_FORMAT, uc->X6); + st->print(", X7 =" INTPTR_FORMAT, uc->X7); + st->cr(); + st->print( "X8 =" INTPTR_FORMAT, uc->X8); + st->print(", X9 =" INTPTR_FORMAT, uc->X9); + st->print(", X10=" INTPTR_FORMAT, uc->X10); + st->print(", X11=" INTPTR_FORMAT, uc->X11); + st->cr(); + st->print( "X12=" INTPTR_FORMAT, uc->X12); + st->print(", X13=" INTPTR_FORMAT, uc->X13); + st->print(", X14=" INTPTR_FORMAT, uc->X14); + st->print(", X15=" INTPTR_FORMAT, uc->X15); + st->cr(); + st->print( "X16=" INTPTR_FORMAT, uc->X16); + st->print(", X17=" INTPTR_FORMAT, uc->X17); + st->print(", X18=" INTPTR_FORMAT, uc->X18); + st->print(", X19=" INTPTR_FORMAT, uc->X19); + st->cr(); + st->print(", X20=" INTPTR_FORMAT, uc->X20); + st->print(", X21=" INTPTR_FORMAT, uc->X21); + st->print(", X22=" INTPTR_FORMAT, uc->X22); + st->print(", X23=" INTPTR_FORMAT, uc->X23); + st->cr(); + st->print(", X24=" INTPTR_FORMAT, uc->X24); + st->print(", X25=" INTPTR_FORMAT, uc->X25); + st->print(", X26=" INTPTR_FORMAT, uc->X26); + st->print(", X27=" INTPTR_FORMAT, uc->X27); + st->print(", X28=" INTPTR_FORMAT, uc->X28); + st->cr(); + st->cr(); + + intptr_t *sp = (intptr_t *)uc->Sp; + st->print_cr("Top of Stack: (sp=" PTR_FORMAT ")", sp); + print_hex_dump(st, (address)sp, (address)(sp + 32), sizeof(intptr_t)); + st->cr(); + + // Note: it may be unsafe to inspect memory near pc. For example, pc may + // point to garbage if entry point in an nmethod is corrupted. Leave + // this at the end, and hope for the best. + address pc = (address)uc->Pc; + st->print_cr("Instructions: (pc=" PTR_FORMAT ")", pc); + print_hex_dump(st, pc - 32, pc + 32, sizeof(char)); + st->cr(); + +} + +void os::print_register_info(outputStream *st, const void *context) { + if (context == NULL) return; + + const CONTEXT* uc = (const CONTEXT*)context; + + st->print_cr("Register to memory mapping:"); + st->cr(); + // this is only for the "general purpose" registers + st->print(" X0="); print_location(st, uc->X0); + st->print(" X1="); print_location(st, uc->X1); + st->print(" X2="); print_location(st, uc->X2); + st->print(" X3="); print_location(st, uc->X3); + st->cr(); + st->print(" X4="); print_location(st, uc->X4); + st->print(" X5="); print_location(st, uc->X5); + st->print(" X6="); print_location(st, uc->X6); + st->print(" X7="); print_location(st, uc->X7); + st->cr(); + st->print(" X8="); print_location(st, uc->X8); + st->print(" X9="); print_location(st, uc->X9); + st->print("X10="); print_location(st, uc->X10); + st->print("X11="); print_location(st, uc->X11); + st->cr(); + st->print("X12="); print_location(st, uc->X12); + st->print("X13="); print_location(st, uc->X13); + st->print("X14="); print_location(st, uc->X14); + st->print("X15="); print_location(st, uc->X15); + st->cr(); + st->print("X16="); print_location(st, uc->X16); + st->print("X17="); print_location(st, uc->X17); + st->print("X18="); print_location(st, uc->X18); + st->print("X19="); print_location(st, uc->X19); + st->cr(); + st->print("X20="); print_location(st, uc->X20); + st->print("X21="); print_location(st, uc->X21); + st->print("X22="); print_location(st, uc->X22); + st->print("X23="); print_location(st, uc->X23); + st->cr(); + st->print("X24="); print_location(st, uc->X24); + st->print("X25="); print_location(st, uc->X25); + st->print("X26="); print_location(st, uc->X26); + st->print("X27="); print_location(st, uc->X27); + st->print("X28="); print_location(st, uc->X28); + + st->cr(); +} + +void os::setup_fpu() { +} + +bool os::supports_sse() { + return true; +} + +#ifndef PRODUCT +void os::verify_stack_alignment() { + assert(((intptr_t)os::current_stack_pointer() & (StackAlignmentInBytes-1)) == 0, "incorrect stack alignment"); +} +#endif + +int os::extra_bang_size_in_bytes() { + // AArch64 does not require the additional stack bang. + return 0; +} + +extern "C" { + int SpinPause() { + return 0; + } +}; diff --git a/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.hpp @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_HPP + + static void setup_fpu(); + static bool supports_sse(); + + static bool register_code_area(char *low, char *high) { + // Using Vectored Exception Handling + return true; + } + +#endif // OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.inline.hpp b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.inline.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/os_windows_aarch64.inline.hpp @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_INLINE_HPP +#define OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_INLINE_HPP + +#include "runtime/os.hpp" + +#endif // OS_CPU_WINDOWS_AARCH64_OS_WINDOWS_AARCH64_INLINE_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/prefetch_windows_aarch64.inline.hpp b/src/hotspot/os_cpu/windows_aarch64/prefetch_windows_aarch64.inline.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/prefetch_windows_aarch64.inline.hpp @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_PREFETCH_WINDOWS_AARCH64_INLINE_HPP +#define OS_CPU_WINDOWS_AARCH64_PREFETCH_WINDOWS_AARCH64_INLINE_HPP + +#include "runtime/prefetch.hpp" + + +inline void Prefetch::read (void *loc, intx interval) { +} + +inline void Prefetch::write(void *loc, intx interval) { +} + +#endif // OS_CPU_WINDOWS_AARCH64_PREFETCH_WINDOWS_AARCH64_INLINE_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.cpp b/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.cpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.cpp @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "memory/metaspaceShared.hpp" +#include "runtime/frame.inline.hpp" +#include "runtime/thread.inline.hpp" + +frame JavaThread::pd_last_frame() { + assert(has_last_Java_frame(), "must have last_Java_sp() when suspended"); + vmassert(_anchor.last_Java_pc() != NULL, "not walkable"); + return frame(_anchor.last_Java_sp(), _anchor.last_Java_fp(), _anchor.last_Java_pc()); +} + +// For Forte Analyzer AsyncGetCallTrace profiling support - thread is +// currently interrupted by SIGPROF +bool JavaThread::pd_get_top_frame_for_signal_handler(frame* fr_addr, + void* ucontext, bool isInJava) { + + assert(Thread::current() == this, "caller must be current thread"); + return pd_get_top_frame(fr_addr, ucontext, isInJava); +} + +bool JavaThread::pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava) { + return pd_get_top_frame(fr_addr, ucontext, isInJava); +} + +bool JavaThread::pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava) { + + assert(this->is_Java_thread(), "must be JavaThread"); + + JavaThread* jt = (JavaThread *)this; + + // If we have a last_Java_frame, then we should use it even if + // isInJava == true. It should be more reliable than CONTEXT info. + if (jt->has_last_Java_frame() && jt->frame_anchor()->walkable()) { + *fr_addr = jt->pd_last_frame(); + return true; + } + + // At this point, we don't have a last_Java_frame, so + // we try to glean some information out of the CONTEXT + // if we were running Java code when SIGPROF came in. + if (isInJava) { + frame ret_frame = os::fetch_frame_from_context(ucontext); + if (ret_frame.pc() == NULL || ret_frame.sp() == NULL ) { + // CONTEXT wasn't useful + return false; + } + + if (MetaspaceShared::is_in_trampoline_frame(ret_frame.pc())) { + // In the middle of a trampoline call. Bail out for safety. + // This happens rarely so shouldn't affect profiling. + return false; + } + + if (!ret_frame.safe_for_sender(jt)) { +#if COMPILER2_OR_JVMCI + // C2 and JVMCI use ebp as a general register see if NULL fp helps + frame ret_frame2(ret_frame.sp(), NULL, ret_frame.pc()); + if (!ret_frame2.safe_for_sender(jt)) { + // nothing else to try if the frame isn't good + return false; + } + ret_frame = ret_frame2; +#else + // nothing else to try if the frame isn't good + return false; +#endif // COMPILER2_OR_JVMCI + } + *fr_addr = ret_frame; + return true; + } + + // nothing else to try + return false; +} + +void JavaThread::cache_global_variables() { } diff --git a/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/thread_windows_aarch64.hpp @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_THREAD_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_THREAD_WINDOWS_AARCH64_HPP + + private: + +#ifdef ASSERT + // spill stack holds N callee-save registers at each Java call and + // grows downwards towards limit + // we need limit to check we have space for a spill and base so we + // can identify all live spill frames at GC (eventually) + address _spill_stack; + address _spill_stack_base; + address _spill_stack_limit; +#endif // ASSERT + + void pd_initialize() { + _anchor.clear(); + } + + frame pd_last_frame(); + + public: + // Mutators are highly dangerous.... + intptr_t* last_Java_fp() { return _anchor.last_Java_fp(); } + void set_last_Java_fp(intptr_t* fp) { _anchor.set_last_Java_fp(fp); } + + void set_base_of_stack_pointer(intptr_t* base_sp) { + } + + static ByteSize last_Java_fp_offset() { + return byte_offset_of(JavaThread, _anchor) + JavaFrameAnchor::last_Java_fp_offset(); + } + + intptr_t* base_of_stack_pointer() { + return NULL; + } + void record_base_of_stack_pointer() { + } + + bool pd_get_top_frame_for_signal_handler(frame* fr_addr, void* ucontext, + bool isInJava); + + bool pd_get_top_frame_for_profiling(frame* fr_addr, void* ucontext, bool isInJava); +private: + bool pd_get_top_frame(frame* fr_addr, void* ucontext, bool isInJava); +public: + + static Thread *aarch64_get_thread_helper() { + return Thread::current(); + } + + // These routines are only used on cpu architectures that + // have separate register stacks (Itanium). + static bool register_stack_overflow() { return false; } + static void enable_register_stack_guard() {} + static void disable_register_stack_guard() {} + +#endif // OS_CPU_WINDOWS_AARCH64_THREAD_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/unwind_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/unwind_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/unwind_windows_aarch64.hpp @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_UNWIND_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_UNWIND_WINDOWS_AARCH64_HPP + + +typedef unsigned char UBYTE; + +#if _MSC_VER < 1700 + +/* Not needed for VS2012 compiler, comes from winnt.h. */ +#define UNW_FLAG_EHANDLER 0x01 +#define UNW_FLAG_UHANDLER 0x02 +#define UNW_FLAG_CHAININFO 0x04 + +#endif + +// See https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling#xdata-records +typedef struct _UNWIND_INFO_EH_ONLY { + DWORD FunctionLength : 18; + DWORD Version : 2; + DWORD X : 1; // = 1 + DWORD E : 1; // = 1 + DWORD EpilogCount : 5; // = 0 + DWORD CodeWords : 5; // = 1 + DWORD UnwindCode0 : 8; + DWORD UnwindCode1 : 8; + DWORD UnwindCode2 : 8; + DWORD UnwindCode3 : 8; + DWORD ExceptionHandler; +} UNWIND_INFO_EH_ONLY, *PUNWIND_INFO_EH_ONLY; + +/* +typedef struct _RUNTIME_FUNCTION { + DWORD BeginAddress; + union { + DWORD UnwindData; + struct { + DWORD Flag : 2; + DWORD FunctionLength : 11; + DWORD RegF : 3; + DWORD RegI : 4; + DWORD H : 1; + DWORD CR : 2; + DWORD FrameSize : 9; + } DUMMYSTRUCTNAME; + } DUMMYUNIONNAME; +} RUNTIME_FUNCTION, *PRUNTIME_FUNCTION; +*/ + +#if _MSC_VER < 1700 + +/* Not needed for VS2012 compiler, comes from winnt.h. */ +typedef struct _DISPATCHER_CONTEXT { + ULONG64 ControlPc; + ULONG64 ImageBase; + PRUNTIME_FUNCTION FunctionEntry; + ULONG64 EstablisherFrame; + ULONG64 TargetIp; + PCONTEXT ContextRecord; +// PEXCEPTION_ROUTINE LanguageHandler; + char * LanguageHandler; // double dependency problem + PVOID HandlerData; +} DISPATCHER_CONTEXT, *PDISPATCHER_CONTEXT; + +#endif + +#if _MSC_VER < 1500 + +/* Not needed for VS2008 compiler, comes from winnt.h. */ +typedef EXCEPTION_DISPOSITION (*PEXCEPTION_ROUTINE) ( + IN PEXCEPTION_RECORD ExceptionRecord, + IN ULONG64 EstablisherFrame, + IN OUT PCONTEXT ContextRecord, + IN OUT PDISPATCHER_CONTEXT DispatcherContext +); + +#endif + +#endif // OS_CPU_WINDOWS_AARCH64_UNWIND_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/vmStructs_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/vmStructs_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/vmStructs_windows_aarch64.hpp @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_VMSTRUCTS_WINDOWS_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_VMSTRUCTS_WINDOWS_AARCH64_HPP + +// These are the OS and CPU-specific fields, types and integer +// constants required by the Serviceability Agent. This file is +// referenced by vmStructs.cpp. + +#define VM_STRUCTS_OS_CPU(nonstatic_field, static_field, unchecked_nonstatic_field, volatile_nonstatic_field, nonproduct_nonstatic_field, c2_nonstatic_field, unchecked_c1_static_field, unchecked_c2_static_field) \ + \ + /******************************/ \ + /* Threads (NOTE: incomplete) */ \ + /******************************/ \ + \ + nonstatic_field(OSThread, _thread_id, OSThread::thread_id_t) \ + unchecked_nonstatic_field(OSThread, _thread_handle, sizeof(HANDLE)) /* NOTE: no type */ + +#define VM_TYPES_OS_CPU(declare_type, declare_toplevel_type, declare_oop_type, declare_integer_type, declare_unsigned_integer_type, declare_c1_toplevel_type, declare_c2_type, declare_c2_toplevel_type) \ + \ + declare_unsigned_integer_type(OSThread::thread_id_t) + +#define VM_INT_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#define VM_LONG_CONSTANTS_OS_CPU(declare_constant, declare_preprocessor_constant, declare_c1_constant, declare_c2_constant, declare_c2_preprocessor_constant) + +#endif // OS_CPU_WINDOWS_AARCH64_VMSTRUCTS_WINDOWS_AARCH64_HPP diff --git a/src/hotspot/os_cpu/windows_aarch64/vm_version_windows_aarch64.cpp b/src/hotspot/os_cpu/windows_aarch64/vm_version_windows_aarch64.cpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/vm_version_windows_aarch64.cpp @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#include "precompiled.hpp" +#include "runtime/os.hpp" +#include "runtime/vm_version.hpp" + diff --git a/src/hotspot/os_cpu/windows_x86/os_windows_x86.cpp b/src/hotspot/os_cpu/windows_x86/os_windows_x86.cpp --- a/src/hotspot/os_cpu/windows_x86/os_windows_x86.cpp +++ b/src/hotspot/os_cpu/windows_x86/os_windows_x86.cpp @@ -354,6 +354,41 @@ } #endif +bool os::win32::get_frame_at_stack_banging_point(JavaThread* thread, + struct _EXCEPTION_POINTERS* exceptionInfo, address pc, frame* fr) { + PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord; + address addr = (address) exceptionRecord->ExceptionInformation[1]; + if (Interpreter::contains(pc)) { + *fr = os::fetch_frame_from_context((void*)exceptionInfo->ContextRecord); + if (!fr->is_first_java_frame()) { + // get_frame_at_stack_banging_point() is only called when we + // have well defined stacks so java_sender() calls do not need + // to assert safe_for_sender() first. + *fr = fr->java_sender(); + } + } else { + // more complex code with compiled code + assert(!Interpreter::contains(pc), "Interpreted methods should have been handled above"); + CodeBlob* cb = CodeCache::find_blob(pc); + if (cb == NULL || !cb->is_nmethod() || cb->is_frame_complete_at(pc)) { + // Not sure where the pc points to, fallback to default + // stack overflow handling + return false; + } else { + // in compiled code, the stack banging is performed just after the return pc + // has been pushed on the stack + intptr_t* fp = (intptr_t*)exceptionInfo->ContextRecord->REG_FP; + intptr_t* sp = (intptr_t*)exceptionInfo->ContextRecord->REG_SP; + *fr = frame(sp + 1, fp, (address)*sp); + if (!fr->is_java_frame()) { + // See java_sender() comment above. + *fr = fr->java_sender(); + } + } + } + assert(fr->is_java_frame(), "Safety check"); + return true; +} #ifndef AMD64 intptr_t* _get_previous_fp() { diff --git a/src/hotspot/share/runtime/stubRoutines.cpp b/src/hotspot/share/runtime/stubRoutines.cpp --- a/src/hotspot/share/runtime/stubRoutines.cpp +++ b/src/hotspot/share/runtime/stubRoutines.cpp @@ -394,7 +394,7 @@ // test safefetch routines // Not on Windows 32bit until 8074860 is fixed -#if ! (defined(_WIN32) && defined(_M_IX86)) +#if ! (defined(_WIN32) && defined(_M_IX86)) && !defined(_M_ARM64) test_safefetch32(); test_safefetchN(); #endif diff --git a/src/java.base/windows/native/libjava/java_props_md.c b/src/java.base/windows/native/libjava/java_props_md.c --- a/src/java.base/windows/native/libjava/java_props_md.c +++ b/src/java.base/windows/native/libjava/java_props_md.c @@ -569,6 +569,8 @@ sprops.os_arch = "amd64"; #elif defined(_X86_) sprops.os_arch = "x86"; +#elif defined(_M_ARM64) + sprops.os_arch = "aarch64"; #else sprops.os_arch = "unknown"; #endif diff --git a/src/jdk.attach/windows/classes/sun/tools/attach/AttachProviderImpl.java b/src/jdk.attach/windows/classes/sun/tools/attach/AttachProviderImpl.java --- a/src/jdk.attach/windows/classes/sun/tools/attach/AttachProviderImpl.java +++ b/src/jdk.attach/windows/classes/sun/tools/attach/AttachProviderImpl.java @@ -43,7 +43,7 @@ "This provider is not supported on this version of Windows"); } String arch = System.getProperty("os.arch"); - if (!arch.equals("x86") && !arch.equals("amd64")) { + if (!arch.equals("x86") && !arch.equals("amd64") && !arch.equals("aarch64")) { throw new RuntimeException( "This provider is not supported on this processor architecture"); } diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java --- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/HotSpotAgent.java @@ -530,8 +530,10 @@ machDesc = new MachineDescriptionIntelX86(); } else if (cpu.equals("amd64")) { machDesc = new MachineDescriptionAMD64(); + } else if (cpu.equals("aarch64")) { + machDesc = new MachineDescriptionAArch64(); } else { - throw new DebuggerException("Win32 supported under x86 and amd64 only"); + throw new DebuggerException("Win32 supported under x86, amd64 and aarch64 only"); } // Note we do not use a cache for the local debugger in server diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/WindbgDebuggerLocal.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/WindbgDebuggerLocal.java --- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/WindbgDebuggerLocal.java +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/WindbgDebuggerLocal.java @@ -28,8 +28,10 @@ import java.net.*; import java.util.*; import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.aarch64.*; import sun.jvm.hotspot.debugger.amd64.*; import sun.jvm.hotspot.debugger.x86.*; +import sun.jvm.hotspot.debugger.windbg.aarch64.*; import sun.jvm.hotspot.debugger.windbg.amd64.*; import sun.jvm.hotspot.debugger.windbg.x86.*; import sun.jvm.hotspot.debugger.win32.coff.*; @@ -113,6 +115,8 @@ threadFactory = new WindbgX86ThreadFactory(this); } else if (cpu.equals("amd64")) { threadFactory = new WindbgAMD64ThreadFactory(this); + } else if (cpu.equals("aarch64")) { + threadFactory = new WindbgAARCH64ThreadFactory(this); } if (useCache) { diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64Thread.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64Thread.java new file mode 100644 --- /dev/null +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64Thread.java @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +package sun.jvm.hotspot.debugger.windbg.aarch64; + +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.aarch64.*; +import sun.jvm.hotspot.debugger.windbg.*; + +class WindbgAARCH64Thread implements ThreadProxy { + private WindbgDebugger debugger; + private long sysId; + private boolean gotID; + private long id; + + // The address argument must be the address of the OSThread::_thread_id + WindbgAARCH64Thread(WindbgDebugger debugger, Address addr) { + this.debugger = debugger; + this.sysId = (long)addr.getCIntegerAt(0, 4, true); + gotID = false; + } + + WindbgAARCH64Thread(WindbgDebugger debugger, long sysId) { + this.debugger = debugger; + this.sysId = sysId; + gotID = false; + } + + public ThreadContext getContext() throws IllegalThreadStateException { + long[] data = debugger.getThreadIntegerRegisterSet(getThreadID()); + WindbgAARCH64ThreadContext context = new WindbgAARCH64ThreadContext(debugger); + for (int i = 0; i < data.length; i++) { + context.setRegister(i, data[i]); + } + return context; + } + + public boolean canSetContext() throws DebuggerException { + return false; + } + + public void setContext(ThreadContext thrCtx) + throws IllegalThreadStateException, DebuggerException { + throw new DebuggerException("Unimplemented"); + } + + public boolean equals(Object obj) { + if ((obj == null) || !(obj instanceof WindbgAARCH64Thread)) { + return false; + } + + return (((WindbgAARCH64Thread) obj).getThreadID() == getThreadID()); + } + + public int hashCode() { + return (int) getThreadID(); + } + + public String toString() { + return Long.toString(getThreadID()); + } + + /** Retrieves the thread ID of this thread by examining the Thread + Information Block. */ + private long getThreadID() { + if (!gotID) { + id = debugger.getThreadIdFromSysId(sysId); + } + + return id; + } +} diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadContext.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadContext.java new file mode 100644 --- /dev/null +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadContext.java @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +package sun.jvm.hotspot.debugger.windbg.aarch64; + +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.aarch64.*; +import sun.jvm.hotspot.debugger.windbg.*; + +class WindbgAARCH64ThreadContext extends AARCH64ThreadContext { + private WindbgDebugger debugger; + + public WindbgAARCH64ThreadContext(WindbgDebugger debugger) { + super(); + this.debugger = debugger; + } + + public void setRegisterAsAddress(int index, Address value) { + setRegister(index, debugger.getAddressValue(value)); + } + + public Address getRegisterAsAddress(int index) { + return debugger.newAddress(getRegister(index)); + } +} diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadFactory.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadFactory.java new file mode 100644 --- /dev/null +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/debugger/windbg/aarch64/WindbgAARCH64ThreadFactory.java @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +package sun.jvm.hotspot.debugger.windbg.aarch64; + +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.windbg.*; + +public class WindbgAARCH64ThreadFactory implements WindbgThreadFactory { + private WindbgDebugger debugger; + + public WindbgAARCH64ThreadFactory(WindbgDebugger debugger) { + this.debugger = debugger; + } + + public ThreadProxy createThreadWrapper(Address threadIdentifierAddr) { + return new WindbgAARCH64Thread(debugger, threadIdentifierAddr); + } + + public ThreadProxy createThreadWrapper(long id) { + return new WindbgAARCH64Thread(debugger, id); + } +} diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java --- a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/Threads.java @@ -28,8 +28,9 @@ import sun.jvm.hotspot.debugger.*; import sun.jvm.hotspot.types.*; +import sun.jvm.hotspot.runtime.win32_x86.Win32X86JavaThreadPDAccess; import sun.jvm.hotspot.runtime.win32_amd64.Win32AMD64JavaThreadPDAccess; -import sun.jvm.hotspot.runtime.win32_x86.Win32X86JavaThreadPDAccess; +import sun.jvm.hotspot.runtime.win32_aarch64.Win32AARCH64JavaThreadPDAccess; import sun.jvm.hotspot.runtime.linux_x86.LinuxX86JavaThreadPDAccess; import sun.jvm.hotspot.runtime.linux_amd64.LinuxAMD64JavaThreadPDAccess; import sun.jvm.hotspot.runtime.linux_aarch64.LinuxAARCH64JavaThreadPDAccess; @@ -99,6 +100,8 @@ access = new Win32X86JavaThreadPDAccess(); } else if (cpu.equals("amd64")) { access = new Win32AMD64JavaThreadPDAccess(); + } else if (cpu.equals("aarch64")) { + access = new Win32AARCH64JavaThreadPDAccess(); } } else if (os.equals("linux")) { if (cpu.equals("x86")) { diff --git a/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/win32_aarch64/Win32AARCH64JavaThreadPDAccess.java b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/win32_aarch64/Win32AARCH64JavaThreadPDAccess.java new file mode 100644 --- /dev/null +++ b/src/jdk.hotspot.agent/share/classes/sun/jvm/hotspot/runtime/win32_aarch64/Win32AARCH64JavaThreadPDAccess.java @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2020, Microsoft Corporation. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +package sun.jvm.hotspot.runtime.win32_aarch64; + +import java.io.*; +import java.util.*; +import sun.jvm.hotspot.debugger.*; +import sun.jvm.hotspot.debugger.aarch64.*; +import sun.jvm.hotspot.runtime.*; +import sun.jvm.hotspot.runtime.aarch64.*; +import sun.jvm.hotspot.types.*; +import sun.jvm.hotspot.utilities.*; +import sun.jvm.hotspot.utilities.Observable; +import sun.jvm.hotspot.utilities.Observer; + +/** This class is only public to allow using the VMObjectFactory to + instantiate these. +*/ + +public class Win32AARCH64JavaThreadPDAccess implements JavaThreadPDAccess { + private static AddressField lastJavaFPField; + private static AddressField osThreadField; + + // Field from OSThread + private static Field osThreadThreadIDField; + + // This is currently unneeded but is being kept in case we change + // the currentFrameGuess algorithm + private static final long GUESS_SCAN_RANGE = 128 * 1024; + + static { + VM.registerVMInitializedObserver(new Observer() { + public void update(Observable o, Object data) { + initialize(VM.getVM().getTypeDataBase()); + } + }); + } + + private static synchronized void initialize(TypeDataBase db) { + Type type = db.lookupType("JavaThread"); + osThreadField = type.getAddressField("_osthread"); + + Type anchorType = db.lookupType("JavaFrameAnchor"); + lastJavaFPField = anchorType.getAddressField("_last_Java_fp"); + + Type osThreadType = db.lookupType("OSThread"); + osThreadThreadIDField = osThreadType.getField("_thread_id"); + } + + public Address getLastJavaFP(Address addr) { + return lastJavaFPField.getValue(addr.addOffsetTo(sun.jvm.hotspot.runtime.JavaThread.getAnchorField().getOffset())); + } + + public Address getLastJavaPC(Address addr) { + return null; + } + + public Address getBaseOfStackPointer(Address addr) { + return null; + } + + public Frame getLastFramePD(JavaThread thread, Address addr) { + Address fp = thread.getLastJavaFP(); + if (fp == null) { + return null; // no information + } + Address pc = thread.getLastJavaPC(); + if ( pc != null ) { + return new AARCH64Frame(thread.getLastJavaSP(), fp, pc); + } else { + return new AARCH64Frame(thread.getLastJavaSP(), fp); + } + } + + public RegisterMap newRegisterMap(JavaThread thread, boolean updateMap) { + return new AARCH64RegisterMap(thread, updateMap); + } + + public Frame getCurrentFrameGuess(JavaThread thread, Address addr) { + ThreadProxy t = getThreadProxy(addr); + AARCH64ThreadContext context = (AARCH64ThreadContext) t.getContext(); + AARCH64CurrentFrameGuess guesser = new AARCH64CurrentFrameGuess(context, thread); + if (!guesser.run(GUESS_SCAN_RANGE)) { + return null; + } + if (guesser.getPC() == null) { + return new AARCH64Frame(guesser.getSP(), guesser.getFP()); + } else { + return new AARCH64Frame(guesser.getSP(), guesser.getFP(), guesser.getPC()); + } + } + + public void printThreadIDOn(Address addr, PrintStream tty) { + tty.print(getThreadProxy(addr)); + } + + public void printInfoOn(Address threadAddr, PrintStream tty) { + } + + public Address getLastSP(Address addr) { + ThreadProxy t = getThreadProxy(addr); + AARCH64ThreadContext context = (AARCH64ThreadContext) t.getContext(); + return context.getRegisterAsAddress(AARCH64ThreadContext.SP); + } + + public ThreadProxy getThreadProxy(Address addr) { + // Addr is the address of the JavaThread. + // Fetch the OSThread (for now and for simplicity, not making a + // separate "OSThread" class in this package) + Address osThreadAddr = osThreadField.getValue(addr); + // Get the address of the thread_id within the OSThread + Address threadIdAddr = osThreadAddr.addOffsetTo(osThreadThreadIDField.getOffset()); + + JVMDebugger debugger = VM.getVM().getDebugger(); + return debugger.getThreadForIdentifierAddress(threadIdAddr); + } +} diff --git a/src/jdk.hotspot.agent/windows/native/libsaproc/sawindbg.cpp b/src/jdk.hotspot.agent/windows/native/libsaproc/sawindbg.cpp --- a/src/jdk.hotspot.agent/windows/native/libsaproc/sawindbg.cpp +++ b/src/jdk.hotspot.agent/windows/native/libsaproc/sawindbg.cpp @@ -36,6 +36,9 @@ #elif _M_AMD64 #include "sun_jvm_hotspot_debugger_amd64_AMD64ThreadContext.h" #define NPRGREG sun_jvm_hotspot_debugger_amd64_AMD64ThreadContext_NPRGREG +#elif _M_ARM64 + #include "sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext.h" + #define NPRGREG sun_jvm_hotspot_debugger_aarch64_AARCH64ThreadContext_NPRGREG #else #error "SA windbg back-end is not supported for your cpu!" #endif # HG changeset patch # User burban # Date 1597872449 14400 # Wed Aug 19 17:27:29 2020 -0400 # Node ID a80c5cf2e6155581f1125f409b7359cc745291c7 # Parent 068f53660ed97f21af6a95f32ba14a41c351eb5b 8248659: AArch64: Extend CPU Feature detection Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.cpp @@ -26,44 +26,20 @@ #include "precompiled.hpp" #include "asm/macroAssembler.hpp" #include "asm/macroAssembler.inline.hpp" +#include "logging/log.hpp" #include "memory/resourceArea.hpp" #include "runtime/java.hpp" #include "runtime/os.hpp" #include "runtime/stubCodeGenerator.hpp" #include "runtime/vm_version.hpp" #include "utilities/macros.hpp" +#include "vm_version_aarch64.hpp" #include OS_HEADER_INLINE(os) +#ifndef _WIN64 #include #include - -#ifndef HWCAP_AES -#define HWCAP_AES (1<<3) -#endif - -#ifndef HWCAP_PMULL -#define HWCAP_PMULL (1<<4) -#endif - -#ifndef HWCAP_SHA1 -#define HWCAP_SHA1 (1<<5) -#endif - -#ifndef HWCAP_SHA2 -#define HWCAP_SHA2 (1<<6) -#endif - -#ifndef HWCAP_CRC32 -#define HWCAP_CRC32 (1<<7) -#endif - -#ifndef HWCAP_ATOMICS -#define HWCAP_ATOMICS (1<<8) -#endif - -#ifndef HWCAP_SHA512 -#define HWCAP_SHA512 (1 << 21) #endif int VM_Version::_cpu; @@ -103,8 +79,10 @@ __ get_dczid_el0(rscratch1); __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset()))); +#ifndef _WIN64 __ get_ctr_el0(rscratch1); __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset()))); +#endif __ leave(); __ ret(lr); @@ -165,13 +143,19 @@ SoftwarePrefetchHintDistance &= ~7; } - uint64_t auxv = getauxval(AT_HWCAP); +#ifndef _WIN64 + _features = getauxval(AT_HWCAP); +#else + if (IsProcessorFeaturePresent(PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE)) _features |= CPU_CRC32; + if (IsProcessorFeaturePresent(PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE)) _features |= CPU_AES | CPU_SHA1 | CPU_SHA2; + if (IsProcessorFeaturePresent(PF_ARM_VFP_32_REGISTERS_AVAILABLE)) _features |= CPU_ASIMD; + // No check for CPU_PMULL +#endif // _WIN64 char buf[512]; - _features = auxv; - int cpu_lines = 0; +#ifndef _WIN64 if (FILE *f = fopen("/proc/cpuinfo", "r")) { // need a large buffer as the flags line may include lots of text char buf[1024], *p; @@ -197,6 +181,28 @@ } fclose(f); } +#else + { + char* buf = ::getenv("PROCESSOR_IDENTIFIER"); + if (buf && strstr(buf, "Ampere(TM)") != NULL) { + _cpu = CPU_AMCC; + cpu_lines++; + } else if (buf && strstr(buf, "Cavium Inc.") != NULL) { + _cpu = CPU_CAVIUM; + cpu_lines++; + } else { + log_info(os)("VM_Version: unknown CPU model"); + } + + if (_cpu) { + SYSTEM_INFO si; + GetSystemInfo(&si); + _model = si.wProcessorLevel; + _variant = si.wProcessorRevision / 0xFF; + _revision = si.wProcessorRevision & 0xFF; + } + } +#endif // _WIN64 if (os::supports_map_sync()) { // if dcpop is available publish data cache line flush size via @@ -284,21 +290,21 @@ sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision); if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2); - if (auxv & HWCAP_ASIMD) strcat(buf, ", simd"); - if (auxv & HWCAP_CRC32) strcat(buf, ", crc"); - if (auxv & HWCAP_AES) strcat(buf, ", aes"); - if (auxv & HWCAP_SHA1) strcat(buf, ", sha1"); - if (auxv & HWCAP_SHA2) strcat(buf, ", sha256"); - if (auxv & HWCAP_SHA512) strcat(buf, ", sha512"); - if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse"); + if (_features & CPU_ASIMD) strcat(buf, ", simd"); + if (_features & CPU_CRC32) strcat(buf, ", crc"); + if (_features & CPU_AES) strcat(buf, ", aes"); + if (_features & CPU_SHA1) strcat(buf, ", sha1"); + if (_features & CPU_SHA2) strcat(buf, ", sha256"); + if (_features & CPU_SHA512) strcat(buf, ", sha512"); + if (_features & CPU_LSE) strcat(buf, ", lse"); _features_string = os::strdup(buf); if (FLAG_IS_DEFAULT(UseCRC32)) { - UseCRC32 = (auxv & HWCAP_CRC32) != 0; + UseCRC32 = (_features & CPU_CRC32) != 0; } - if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) { + if (UseCRC32 && (_features & CPU_CRC32) == 0) { warning("UseCRC32 specified, but not supported on this CPU"); FLAG_SET_DEFAULT(UseCRC32, false); } @@ -312,7 +318,7 @@ FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); } - if (auxv & HWCAP_ATOMICS) { + if (_features & CPU_LSE) { if (FLAG_IS_DEFAULT(UseLSE)) FLAG_SET_DEFAULT(UseLSE, true); } else { @@ -322,7 +328,7 @@ } } - if (auxv & HWCAP_AES) { + if (_features & CPU_AES) { UseAES = UseAES || FLAG_IS_DEFAULT(UseAES); UseAESIntrinsics = UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics)); @@ -350,7 +356,7 @@ UseCRC32Intrinsics = true; } - if (auxv & HWCAP_CRC32) { + if (_features & CPU_CRC32) { if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); } @@ -368,7 +374,7 @@ FLAG_SET_DEFAULT(UseMD5Intrinsics, false); } - if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) { + if (_features & (CPU_SHA1 | CPU_SHA2)) { if (FLAG_IS_DEFAULT(UseSHA)) { FLAG_SET_DEFAULT(UseSHA, true); } @@ -377,7 +383,7 @@ FLAG_SET_DEFAULT(UseSHA, false); } - if (UseSHA && (auxv & HWCAP_SHA1)) { + if (UseSHA && (_features & CPU_SHA1)) { if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); } @@ -386,7 +392,7 @@ FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); } - if (UseSHA && (auxv & HWCAP_SHA2)) { + if (UseSHA && (_features & CPU_SHA2)) { if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); } @@ -395,7 +401,7 @@ FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); } - if (UseSHA && (auxv & HWCAP_SHA512)) { + if (UseSHA && (_features & CPU_SHA512)) { // Do not auto-enable UseSHA512Intrinsics until it has been fully tested on hardware // if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { // FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); @@ -409,7 +415,7 @@ FLAG_SET_DEFAULT(UseSHA, false); } - if (auxv & HWCAP_PMULL) { + if (_features & CPU_PMULL) { if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { FLAG_SET_DEFAULT(UseGHASHIntrinsics, true); } diff --git a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp --- a/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/vm_version_aarch64.hpp @@ -29,6 +29,7 @@ #include "runtime/abstract_vm_version.hpp" #include "runtime/globals_extension.hpp" #include "utilities/sizes.hpp" +#include "runtime/java.hpp" class VM_Version : public Abstract_VM_Version { friend class JVMCIVMStructs; @@ -43,7 +44,12 @@ static bool _dcpop; struct PsrInfo { uint32_t dczid_el0; +#ifndef _WIN64 + // On Windows-aarch64, this register is not accessible. We then need to + // access the cache line size in a different way. Instead, we get the cache + // line size in os::win32::get_cacheline_size. uint32_t ctr_el0; +#endif }; static PsrInfo _psr_info; static void get_processor_features(); @@ -96,6 +102,7 @@ CPU_SHA2 = (1<<6), CPU_CRC32 = (1<<7), CPU_LSE = (1<<8), + CPU_SHA512 = (1 << 21), CPU_STXR_PREFETCH= (1 << 29), CPU_A53MAC = (1 << 30), }; @@ -106,8 +113,11 @@ static int cpu_variant() { return _variant; } static int cpu_revision() { return _revision; } static bool supports_dcpop() { return _dcpop; } + static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); } +#ifndef _WIN64 static ByteSize ctr_el0_offset() { return byte_offset_of(PsrInfo, ctr_el0); } +#endif static bool is_zva_enabled() { // Check the DZP bit (bit 4) of dczid_el0 is zero // and block size (bit 0~3) is not zero. @@ -119,10 +129,18 @@ return 4 << (_psr_info.dczid_el0 & 0xf); } static int icache_line_size() { +#ifndef _WIN64 return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4; +#else + return os::win32::get_cacheline_size(); +#endif } static int dcache_line_size() { +#ifndef _WIN64 return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4; +#else + return os::win32::get_cacheline_size(); +#endif } static bool supports_fast_class_init_checks() { return true; } }; diff --git a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp --- a/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp +++ b/src/hotspot/cpu/aarch64/vm_version_ext_aarch64.cpp @@ -22,6 +22,7 @@ * */ +#include "precompiled.hpp" #include "memory/allocation.hpp" #include "memory/allocation.inline.hpp" #include "runtime/os.inline.hpp" diff --git a/src/hotspot/os/windows/os_windows.cpp b/src/hotspot/os/windows/os_windows.cpp --- a/src/hotspot/os/windows/os_windows.cpp +++ b/src/hotspot/os/windows/os_windows.cpp @@ -3824,6 +3824,34 @@ initialize_performance_counter(); } +int os::win32::get_cacheline_size() { + PSYSTEM_LOGICAL_PROCESSOR_INFORMATION buffer = NULL; + DWORD returnLength = 0; + + // See https://docs.microsoft.com/en-us/windows/win32/api/sysinfoapi/nf-sysinfoapi-getlogicalprocessorinformation + + GetLogicalProcessorInformation(NULL, &returnLength); + assert(GetLastError() == ERROR_INSUFFICIENT_BUFFER, "Unexpected return from GetLogicalProcessorInformation"); + + buffer = (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION)os::malloc(returnLength, mtInternal); + BOOL rc = GetLogicalProcessorInformation(buffer, &returnLength); + assert(rc, "Unexpected return from GetLogicalProcessorInformation"); + + int line_sz = -1; + for (PSYSTEM_LOGICAL_PROCESSOR_INFORMATION ptr = buffer; ptr < buffer + returnLength / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION); ptr++) { + switch (ptr->Relationship) { + case RelationCache: + // Cache data is in ptr->Cache, one CACHE_DESCRIPTOR structure for each cache. + PCACHE_DESCRIPTOR Cache = &ptr->Cache; + if (Cache->Level == 1) { + line_sz = Cache->LineSize; + } + break; + } + } + os::free(buffer); + return line_sz; +} HINSTANCE os::win32::load_Windows_dll(const char* name, char *ebuf, int ebuflen) { diff --git a/src/hotspot/os/windows/os_windows.hpp b/src/hotspot/os/windows/os_windows.hpp --- a/src/hotspot/os/windows/os_windows.hpp +++ b/src/hotspot/os/windows/os_windows.hpp @@ -70,6 +70,8 @@ static julong available_memory(); static julong physical_memory() { return _physical_memory; } + static int get_cacheline_size(); + // load dll from Windows system directory or Windows directory static HINSTANCE load_Windows_dll(const char* name, char *ebuf, int ebuflen); # HG changeset patch # User burban # Date 1596225151 14400 # Fri Jul 31 15:52:31 2020 -0400 # Node ID 06f533cf804227699709344c27fa5ac7008848ee # Parent a80c5cf2e6155581f1125f409b7359cc745291c7 8248660: AArch64: Make _clear_cache and _nop portable Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp --- a/src/hotspot/cpu/aarch64/assembler_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/assembler_aarch64.hpp @@ -28,6 +28,20 @@ #include "asm/register.hpp" +#ifdef __GNUC__ + +// __nop needs volatile so that compiler doesn't optimize it away +#define NOP() asm volatile ("nop"); + +#elif defined(_MSC_VER) + +// Use MSVC instrinsic: https://docs.microsoft.com/en-us/cpp/intrinsics/arm64-intrinsics?view=vs-2019#I +#define NOP() __nop(); + +#endif + + + // definitions of various symbolic names for machine registers // First intercalls between C and Java which use 8 general registers @@ -613,7 +627,7 @@ void emit_long(jint x) { if ((uintptr_t)pc() == asm_bp) - asm volatile ("nop"); + NOP(); AbstractAssembler::emit_int32(x); } #else diff --git a/src/hotspot/cpu/aarch64/icache_aarch64.hpp b/src/hotspot/cpu/aarch64/icache_aarch64.hpp --- a/src/hotspot/cpu/aarch64/icache_aarch64.hpp +++ b/src/hotspot/cpu/aarch64/icache_aarch64.hpp @@ -26,19 +26,6 @@ #ifndef CPU_AARCH64_ICACHE_AARCH64_HPP #define CPU_AARCH64_ICACHE_AARCH64_HPP -// Interface for updating the instruction cache. Whenever the VM -// modifies code, part of the processor instruction cache potentially -// has to be flushed. - -class ICache : public AbstractICache { - public: - static void initialize(); - static void invalidate_word(address addr) { - __builtin___clear_cache((char *)addr, (char *)(addr + 3)); - } - static void invalidate_range(address start, int nbytes) { - __builtin___clear_cache((char *)start, (char *)(start + nbytes)); - } -}; +#include OS_CPU_HEADER(icache) #endif // CPU_AARCH64_ICACHE_AARCH64_HPP diff --git a/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp b/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/linux_aarch64/icache_linux_aarch64.hpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1999, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP +#define OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP + +// Interface for updating the instruction cache. Whenever the VM +// modifies code, part of the processor instruction cache potentially +// has to be flushed. + +class ICache : public AbstractICache { + public: + static void initialize(); + static void invalidate_word(address addr) { + __builtin___clear_cache((char *)addr, (char *)(addr + 4)); + } + static void invalidate_range(address start, int nbytes) { + __builtin___clear_cache((char *)start, (char *)(start + nbytes)); + } +}; + +#endif // OS_CPU_LINUX_AARCH64_ICACHE_AARCH64_HPP \ No newline at end of file diff --git a/src/hotspot/os_cpu/windows_aarch64/icache_windows_aarch64.hpp b/src/hotspot/os_cpu/windows_aarch64/icache_windows_aarch64.hpp new file mode 100644 --- /dev/null +++ b/src/hotspot/os_cpu/windows_aarch64/icache_windows_aarch64.hpp @@ -0,0 +1,44 @@ +/* + * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved. + * Copyright (c) 2014, Red Hat Inc. All rights reserved. + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. + * + * This code is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 only, as + * published by the Free Software Foundation. + * + * This code is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * version 2 for more details (a copy is included in the LICENSE file that + * accompanied this code). + * + * You should have received a copy of the GNU General Public License version + * 2 along with this work; if not, write to the Free Software Foundation, + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. + * + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA + * or visit www.oracle.com if you need additional information or have any + * questions. + * + */ + +#ifndef OS_CPU_WINDOWS_AARCH64_ICACHE_AARCH64_HPP +#define OS_CPU_WINDOWS_AARCH64_ICACHE_AARCH64_HPP + +// Interface for updating the instruction cache. Whenever the VM +// modifies code, part of the processor instruction cache potentially +// has to be flushed. + +class ICache : public AbstractICache { + public: + static void initialize(); + static void invalidate_word(address addr) { + invalidate_range(addr, 4); + } + static void invalidate_range(address start, int nbytes) { + FlushInstructionCache((HANDLE)GetCurrentProcess(), start, (SIZE_T)(nbytes)); + } +}; + +#endif // OS_CPU_WINDOWS_AARCH64_ICACHE_AARCH64_HPP # HG changeset patch # User burban # Date 1596225200 14400 # Fri Jul 31 15:53:20 2020 -0400 # Node ID 0a75bf475248442e8e2ee048cf49bd4ba6e0ee7a # Parent 06f533cf804227699709344c27fa5ac7008848ee 8248670: Windows: Exception handling support on AArch64 Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/os/windows/os_windows.cpp b/src/hotspot/os/windows/os_windows.cpp --- a/src/hotspot/os/windows/os_windows.cpp +++ b/src/hotspot/os/windows/os_windows.cpp @@ -127,7 +127,10 @@ #define __CPU__ i486 #endif -#if INCLUDE_AOT +#if defined(USE_VECTORED_EXCEPTION_HANDLING) +PVOID topLevelVectoredExceptionHandler = NULL; +LPTOP_LEVEL_EXCEPTION_FILTER previousUnhandledExceptionFilter = NULL; +#elif INCLUDE_AOT PVOID topLevelVectoredExceptionHandler = NULL; LONG WINAPI topLevelVectoredExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo); #endif @@ -150,7 +153,7 @@ if (ForceTimeHighResolution) { timeEndPeriod(1L); } -#if INCLUDE_AOT +#if defined(USE_VECTORED_EXCEPTION_HANDLING) || INCLUDE_AOT if (topLevelVectoredExceptionHandler != NULL) { RemoveVectoredExceptionHandler(topLevelVectoredExceptionHandler); topLevelVectoredExceptionHandler = NULL; @@ -459,6 +462,12 @@ log_info(os, thread)("Thread is alive (tid: " UINTX_FORMAT ").", os::current_thread_id()); +#ifdef USE_VECTORED_EXCEPTION_HANDLING + // Any exception is caught by the Vectored Exception Handler, so VM can + // generate error dump when an exception occurred in non-Java thread + // (e.g. VM thread). + thread->call_run(); +#else // Install a win32 structured exception handler around every thread created // by VM, so VM can generate error dump when an exception occurred in non- // Java thread (e.g. VM thread). @@ -468,6 +477,7 @@ (_EXCEPTION_POINTERS*)_exception_info())) { // Nothing to do. } +#endif // Note: at this point the thread object may already have deleted itself. // Do not dereference it from here on out. @@ -2355,7 +2365,7 @@ PEXCEPTION_RECORD exception_record = exceptionInfo->ExceptionRecord; DWORD exception_code = exception_record->ExceptionCode; #if defined(_M_ARM64) - address pc = (address)exceptionInfo->ContextRecord->Pc; + address pc = (address) exceptionInfo->ContextRecord->Pc; #elif defined(_M_AMD64) address pc = (address) exceptionInfo->ContextRecord->Rip; #else @@ -2439,8 +2449,10 @@ // Last unguard failed or not unguarding tty->print_raw_cr("Execution protection violation"); +#if !defined(USE_VECTORED_EXCEPTION_HANDLING) report_error(t, exception_code, addr, exception_record, exceptionInfo->ContextRecord); +#endif return EXCEPTION_CONTINUE_SEARCH; } } @@ -2483,8 +2495,10 @@ // Fatal red zone violation. thread->disable_stack_red_zone(); tty->print_raw_cr("An unrecoverable stack overflow has occurred."); +#if !defined(USE_VECTORED_EXCEPTION_HANDLING) report_error(t, exception_code, pc, exception_record, exceptionInfo->ContextRecord); +#endif return EXCEPTION_CONTINUE_SEARCH; } } else if (exception_code == EXCEPTION_ACCESS_VIOLATION) { @@ -2561,8 +2575,10 @@ #endif // Stack overflow or null pointer exception in native code. +#if !defined(USE_VECTORED_EXCEPTION_HANDLING) report_error(t, exception_code, pc, exception_record, exceptionInfo->ContextRecord); +#endif return EXCEPTION_CONTINUE_SEARCH; } // /EXCEPTION_ACCESS_VIOLATION // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - @@ -2618,13 +2634,66 @@ #endif } +#if !defined(USE_VECTORED_EXCEPTION_HANDLING) if (exception_code != EXCEPTION_BREAKPOINT) { report_error(t, exception_code, pc, exception_record, exceptionInfo->ContextRecord); } +#endif return EXCEPTION_CONTINUE_SEARCH; } +#if defined(USE_VECTORED_EXCEPTION_HANDLING) || INCLUDE_AOT +LONG WINAPI topLevelVectoredExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) { + PEXCEPTION_RECORD exceptionRecord = exceptionInfo->ExceptionRecord; +#if defined(_M_ARM64) + address pc = (address) exceptionInfo->ContextRecord->Pc; +#elif defined(_M_AMD64) + address pc = (address) exceptionInfo->ContextRecord->Rip; +#else + address pc = (address) exceptionInfo->ContextRecord->Eip; +#endif + + // Fast path for code part of the code cache + if (CodeCache::low_bound() <= pc && pc < CodeCache::high_bound()) { + return topLevelExceptionFilter(exceptionInfo); + } + + // Handle the case where we get an implicit exception in AOT generated + // code. AOT DLL's loaded are not registered for structured exceptions. + // If the exception occurred in the codeCache or AOT code, pass control + // to our normal exception handler. + CodeBlob* cb = CodeCache::find_blob(pc); + if (cb != NULL) { + return topLevelExceptionFilter(exceptionInfo); + } + + return EXCEPTION_CONTINUE_SEARCH; +} +#endif + +#if defined(USE_VECTORED_EXCEPTION_HANDLING) +LONG WINAPI topLevelUnhandledExceptionFilter(struct _EXCEPTION_POINTERS* exceptionInfo) { + if (InterceptOSException) goto exit; + DWORD exception_code = exceptionInfo->ExceptionRecord->ExceptionCode; +#if defined(_M_ARM64) + address pc = (address)exceptionInfo->ContextRecord->Pc; +#elif defined(_M_AMD64) + address pc = (address) exceptionInfo->ContextRecord->Rip; +#else + address pc = (address) exceptionInfo->ContextRecord->Eip; +#endif + Thread* t = Thread::current_or_null_safe(); + + if (exception_code != EXCEPTION_BREAKPOINT) { + report_error(t, exception_code, pc, exceptionInfo->ExceptionRecord, + exceptionInfo->ContextRecord); + } +exit: + return previousUnhandledExceptionFilter ? previousUnhandledExceptionFilter(exceptionInfo) : EXCEPTION_CONTINUE_SEARCH; +} +#endif + #ifndef _WIN64 // Special care for fast JNI accessors. // jni_fast_GetField can trap at certain pc's if a GC kicks in and @@ -4180,7 +4249,10 @@ // Setup Windows Exceptions -#if INCLUDE_AOT +#if defined(USE_VECTORED_EXCEPTION_HANDLING) + topLevelVectoredExceptionHandler = AddVectoredExceptionHandler(1, topLevelVectoredExceptionFilter); + previousUnhandledExceptionFilter = SetUnhandledExceptionFilter(topLevelUnhandledExceptionFilter); +#elif INCLUDE_AOT // If AOT is enabled we need to install a vectored exception handler // in order to forward implicit exceptions from code in AOT // generated DLLs. This is necessary since these DLLs are not diff --git a/src/hotspot/share/prims/jni.cpp b/src/hotspot/share/prims/jni.cpp --- a/src/hotspot/share/prims/jni.cpp +++ b/src/hotspot/share/prims/jni.cpp @@ -93,7 +93,7 @@ static jint CurrentVersion = JNI_VERSION_10; -#ifdef _WIN32 +#if defined(_WIN32) && !defined(USE_VECTORED_EXCEPTION_HANDLING) extern LONG WINAPI topLevelExceptionFilter(_EXCEPTION_POINTERS* ); #endif @@ -3841,11 +3841,11 @@ _JNI_IMPORT_OR_EXPORT_ jint JNICALL JNI_CreateJavaVM(JavaVM **vm, void **penv, void *args) { jint result = JNI_ERR; // On Windows, let CreateJavaVM run with SEH protection -#ifdef _WIN32 +#if defined(_WIN32) && !defined(USE_VECTORED_EXCEPTION_HANDLING) __try { #endif result = JNI_CreateJavaVM_inner(vm, penv, args); -#ifdef _WIN32 +#if defined(_WIN32) && !defined(USE_VECTORED_EXCEPTION_HANDLING) } __except(topLevelExceptionFilter((_EXCEPTION_POINTERS*)_exception_info())) { // Nothing to do. } @@ -3913,11 +3913,11 @@ jint JNICALL jni_DestroyJavaVM(JavaVM *vm) { jint result = JNI_ERR; // On Windows, we need SEH protection -#ifdef _WIN32 +#if defined(_WIN32) && !defined(USE_VECTORED_EXCEPTION_HANDLING) __try { #endif result = jni_DestroyJavaVM_inner(vm); -#ifdef _WIN32 +#if defined(_WIN32) && !defined(USE_VECTORED_EXCEPTION_HANDLING) } __except(topLevelExceptionFilter((_EXCEPTION_POINTERS*)_exception_info())) { // Nothing to do. } diff --git a/src/hotspot/share/utilities/globalDefinitions_visCPP.hpp b/src/hotspot/share/utilities/globalDefinitions_visCPP.hpp --- a/src/hotspot/share/utilities/globalDefinitions_visCPP.hpp +++ b/src/hotspot/share/utilities/globalDefinitions_visCPP.hpp @@ -136,4 +136,8 @@ // Alignment #define ATTRIBUTE_ALIGNED(x) __declspec(align(x)) +#ifdef _M_ARM64 +#define USE_VECTORED_EXCEPTION_HANDLING +#endif + #endif // SHARE_UTILITIES_GLOBALDEFINITIONS_VISCPP_HPP # HG changeset patch # User burban # Date 1596225211 14400 # Fri Jul 31 15:53:31 2020 -0400 # Node ID 1beedd65b1a88bd97b349a69df128f85606aaf07 # Parent 0a75bf475248442e8e2ee048cf49bd4ba6e0ee7a 8248787: G1: Workaround MSVC bug Reviewed-by: Contributed-by: mbeckwit, luhenry, burban diff --git a/src/hotspot/share/gc/g1/g1HeapRegionAttr.hpp b/src/hotspot/share/gc/g1/g1HeapRegionAttr.hpp --- a/src/hotspot/share/gc/g1/g1HeapRegionAttr.hpp +++ b/src/hotspot/share/gc/g1/g1HeapRegionAttr.hpp @@ -32,7 +32,13 @@ // lookups for that information all over the place. struct G1HeapRegionAttr { public: +#if defined(_M_ARM64)&& defined(_MSC_VER) && _MSC_VER <= 1927 + // workaround for MSCV ARM64 bug + // https://developercommunity.visualstudio.com/content/problem/1079221/arm64-bad-code-generation-around-signed-char-arith.html + typedef int32_t region_type_t; +#else typedef int8_t region_type_t; +#endif typedef uint8_t needs_remset_update_t; private: